i915_gem.c 108.7 KB
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/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eric Anholt <eric@anholt.net>
 *
 */

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#include <drm/drmP.h>
#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#include "i915_trace.h"
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#include "intel_drv.h"
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#include <linux/shmem_fs.h>
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#include <linux/slab.h>
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#include <linux/swap.h>
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#include <linux/pci.h>
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#include <linux/dma-buf.h>
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static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
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static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
						    unsigned alignment,
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						    bool map_and_fenceable,
						    bool nonblocking);
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static int i915_gem_phys_pwrite(struct drm_device *dev,
				struct drm_i915_gem_object *obj,
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				struct drm_i915_gem_pwrite *args,
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				struct drm_file *file);
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static void i915_gem_write_fence(struct drm_device *dev, int reg,
				 struct drm_i915_gem_object *obj);
static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
					 struct drm_i915_fence_reg *fence,
					 bool enable);

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static int i915_gem_inactive_shrink(struct shrinker *shrinker,
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				    struct shrink_control *sc);
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static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
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static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
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static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
{
	if (obj->tiling_mode)
		i915_gem_release_mmap(obj);

	/* As we do not have an associated fence register, we will force
	 * a tiling change if we ever need to acquire one.
	 */
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	obj->fence_dirty = false;
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	obj->fence_reg = I915_FENCE_REG_NONE;
}

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/* some bookkeeping */
static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
				  size_t size)
{
	dev_priv->mm.object_count++;
	dev_priv->mm.object_memory += size;
}

static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
				     size_t size)
{
	dev_priv->mm.object_count--;
	dev_priv->mm.object_memory -= size;
}

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static int
i915_gem_wait_for_error(struct drm_device *dev)
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{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct completion *x = &dev_priv->error_completion;
	unsigned long flags;
	int ret;

	if (!atomic_read(&dev_priv->mm.wedged))
		return 0;

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	/*
	 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
	 * userspace. If it takes that long something really bad is going on and
	 * we should simply try to bail out and fail as gracefully as possible.
	 */
	ret = wait_for_completion_interruptible_timeout(x, 10*HZ);
	if (ret == 0) {
		DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
		return -EIO;
	} else if (ret < 0) {
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		return ret;
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	}
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	if (atomic_read(&dev_priv->mm.wedged)) {
		/* GPU is hung, bump the completion count to account for
		 * the token we just consumed so that we never hit zero and
		 * end up waiting upon a subsequent completion event that
		 * will never happen.
		 */
		spin_lock_irqsave(&x->wait.lock, flags);
		x->done++;
		spin_unlock_irqrestore(&x->wait.lock, flags);
	}
	return 0;
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}

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int i915_mutex_lock_interruptible(struct drm_device *dev)
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{
	int ret;

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	ret = i915_gem_wait_for_error(dev);
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	if (ret)
		return ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

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	WARN_ON(i915_verify_lists(dev));
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	return 0;
}
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static inline bool
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i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
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{
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	return obj->gtt_space && !obj->active;
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}

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int
i915_gem_init_ioctl(struct drm_device *dev, void *data,
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		    struct drm_file *file)
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{
	struct drm_i915_gem_init *args = data;
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	if (drm_core_check_feature(dev, DRIVER_MODESET))
		return -ENODEV;

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	if (args->gtt_start >= args->gtt_end ||
	    (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
		return -EINVAL;
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	/* GEM with user mode setting was never supported on ilk and later. */
	if (INTEL_INFO(dev)->gen >= 5)
		return -ENODEV;

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	mutex_lock(&dev->struct_mutex);
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	i915_gem_init_global_gtt(dev, args->gtt_start,
				 args->gtt_end, args->gtt_end);
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	mutex_unlock(&dev->struct_mutex);

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	return 0;
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}

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int
i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
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			    struct drm_file *file)
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{
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	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct drm_i915_gem_get_aperture *args = data;
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	struct drm_i915_gem_object *obj;
	size_t pinned;
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	pinned = 0;
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	mutex_lock(&dev->struct_mutex);
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	list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
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		if (obj->pin_count)
			pinned += obj->gtt_space->size;
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	mutex_unlock(&dev->struct_mutex);
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	args->aper_size = dev_priv->mm.gtt_total;
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	args->aper_available_size = args->aper_size - pinned;
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	return 0;
}

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static int
i915_gem_create(struct drm_file *file,
		struct drm_device *dev,
		uint64_t size,
		uint32_t *handle_p)
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{
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	struct drm_i915_gem_object *obj;
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	int ret;
	u32 handle;
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	size = roundup(size, PAGE_SIZE);
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	if (size == 0)
		return -EINVAL;
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	/* Allocate the new object */
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	obj = i915_gem_alloc_object(dev, size);
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	if (obj == NULL)
		return -ENOMEM;

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	ret = drm_gem_handle_create(file, &obj->base, &handle);
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	if (ret) {
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		drm_gem_object_release(&obj->base);
		i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
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		kfree(obj);
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		return ret;
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	}
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	/* drop reference from allocate - handle holds it now */
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	drm_gem_object_unreference(&obj->base);
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	trace_i915_gem_object_create(obj);

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	*handle_p = handle;
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	return 0;
}

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int
i915_gem_dumb_create(struct drm_file *file,
		     struct drm_device *dev,
		     struct drm_mode_create_dumb *args)
{
	/* have to work out size/pitch and return them */
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	args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
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	args->size = args->pitch * args->height;
	return i915_gem_create(file, dev,
			       args->size, &args->handle);
}

int i915_gem_dumb_destroy(struct drm_file *file,
			  struct drm_device *dev,
			  uint32_t handle)
{
	return drm_gem_handle_delete(file, handle);
}

/**
 * Creates a new mm object and returns a handle to it.
 */
int
i915_gem_create_ioctl(struct drm_device *dev, void *data,
		      struct drm_file *file)
{
	struct drm_i915_gem_create *args = data;
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	return i915_gem_create(file, dev,
			       args->size, &args->handle);
}

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static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
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{
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	drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
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	return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
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		obj->tiling_mode != I915_TILING_NONE;
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}

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static inline int
__copy_to_user_swizzled(char __user *cpu_vaddr,
			const char *gpu_vaddr, int gpu_offset,
			int length)
{
	int ret, cpu_offset = 0;

	while (length > 0) {
		int cacheline_end = ALIGN(gpu_offset + 1, 64);
		int this_length = min(cacheline_end - gpu_offset, length);
		int swizzled_gpu_offset = gpu_offset ^ 64;

		ret = __copy_to_user(cpu_vaddr + cpu_offset,
				     gpu_vaddr + swizzled_gpu_offset,
				     this_length);
		if (ret)
			return ret + length;

		cpu_offset += this_length;
		gpu_offset += this_length;
		length -= this_length;
	}

	return 0;
}

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static inline int
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__copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
			  const char __user *cpu_vaddr,
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			  int length)
{
	int ret, cpu_offset = 0;

	while (length > 0) {
		int cacheline_end = ALIGN(gpu_offset + 1, 64);
		int this_length = min(cacheline_end - gpu_offset, length);
		int swizzled_gpu_offset = gpu_offset ^ 64;

		ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
				       cpu_vaddr + cpu_offset,
				       this_length);
		if (ret)
			return ret + length;

		cpu_offset += this_length;
		gpu_offset += this_length;
		length -= this_length;
	}

	return 0;
}

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/* Per-page copy function for the shmem pread fastpath.
 * Flushes invalid cachelines before reading the target if
 * needs_clflush is set. */
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static int
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shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
		 char __user *user_data,
		 bool page_do_bit17_swizzling, bool needs_clflush)
{
	char *vaddr;
	int ret;

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	if (unlikely(page_do_bit17_swizzling))
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		return -EINVAL;

	vaddr = kmap_atomic(page);
	if (needs_clflush)
		drm_clflush_virt_range(vaddr + shmem_page_offset,
				       page_length);
	ret = __copy_to_user_inatomic(user_data,
				      vaddr + shmem_page_offset,
				      page_length);
	kunmap_atomic(vaddr);

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	return ret ? -EFAULT : 0;
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}

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static void
shmem_clflush_swizzled_range(char *addr, unsigned long length,
			     bool swizzled)
{
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	if (unlikely(swizzled)) {
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		unsigned long start = (unsigned long) addr;
		unsigned long end = (unsigned long) addr + length;

		/* For swizzling simply ensure that we always flush both
		 * channels. Lame, but simple and it works. Swizzled
		 * pwrite/pread is far from a hotpath - current userspace
		 * doesn't use it at all. */
		start = round_down(start, 128);
		end = round_up(end, 128);

		drm_clflush_virt_range((void *)start, end - start);
	} else {
		drm_clflush_virt_range(addr, length);
	}

}

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/* Only difference to the fast-path function is that this can handle bit17
 * and uses non-atomic copy and kmap functions. */
static int
shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
		 char __user *user_data,
		 bool page_do_bit17_swizzling, bool needs_clflush)
{
	char *vaddr;
	int ret;

	vaddr = kmap(page);
	if (needs_clflush)
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		shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
					     page_length,
					     page_do_bit17_swizzling);
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	if (page_do_bit17_swizzling)
		ret = __copy_to_user_swizzled(user_data,
					      vaddr, shmem_page_offset,
					      page_length);
	else
		ret = __copy_to_user(user_data,
				     vaddr + shmem_page_offset,
				     page_length);
	kunmap(page);

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	return ret ? - EFAULT : 0;
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}

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static int
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i915_gem_shmem_pread(struct drm_device *dev,
		     struct drm_i915_gem_object *obj,
		     struct drm_i915_gem_pread *args,
		     struct drm_file *file)
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{
405
	char __user *user_data;
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	ssize_t remain;
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	loff_t offset;
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	int shmem_page_offset, page_length, ret = 0;
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	int obj_do_bit17_swizzling, page_do_bit17_swizzling;
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	int hit_slowpath = 0;
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	int prefaulted = 0;
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	int needs_clflush = 0;
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	struct scatterlist *sg;
	int i;
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416
	user_data = (char __user *) (uintptr_t) args->data_ptr;
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	remain = args->size;

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	obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
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	if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
		/* If we're not in the cpu read domain, set ourself into the gtt
		 * read domain and manually flush cachelines (if required). This
		 * optimizes for the case when the gpu will dirty the data
		 * anyway again before the next pread happens. */
		if (obj->cache_level == I915_CACHE_NONE)
			needs_clflush = 1;
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		if (obj->gtt_space) {
			ret = i915_gem_object_set_to_gtt_domain(obj, false);
			if (ret)
				return ret;
		}
433
	}
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	ret = i915_gem_object_get_pages(obj);
	if (ret)
		return ret;

	i915_gem_object_pin_pages(obj);

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	offset = args->offset;
442

443
	for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) {
444 445
		struct page *page;

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		if (i < offset >> PAGE_SHIFT)
			continue;

		if (remain <= 0)
			break;

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		/* Operation in this page
		 *
		 * shmem_page_offset = offset within page in shmem file
		 * page_length = bytes to copy for this page
		 */
457
		shmem_page_offset = offset_in_page(offset);
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		page_length = remain;
		if ((shmem_page_offset + page_length) > PAGE_SIZE)
			page_length = PAGE_SIZE - shmem_page_offset;

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		page = sg_page(sg);
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		page_do_bit17_swizzling = obj_do_bit17_swizzling &&
			(page_to_phys(page) & (1 << 17)) != 0;

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		ret = shmem_pread_fast(page, shmem_page_offset, page_length,
				       user_data, page_do_bit17_swizzling,
				       needs_clflush);
		if (ret == 0)
			goto next_page;
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		hit_slowpath = 1;
		mutex_unlock(&dev->struct_mutex);

475
		if (!prefaulted) {
476
			ret = fault_in_multipages_writeable(user_data, remain);
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			/* Userspace is tricking us, but we've already clobbered
			 * its pages with the prefault and promised to write the
			 * data up to the first fault. Hence ignore any errors
			 * and just continue. */
			(void)ret;
			prefaulted = 1;
		}
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		ret = shmem_pread_slow(page, shmem_page_offset, page_length,
				       user_data, page_do_bit17_swizzling,
				       needs_clflush);
488

489
		mutex_lock(&dev->struct_mutex);
490

491
next_page:
492 493
		mark_page_accessed(page);

494
		if (ret)
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			goto out;

497
		remain -= page_length;
498
		user_data += page_length;
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		offset += page_length;
	}

502
out:
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	i915_gem_object_unpin_pages(obj);

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	if (hit_slowpath) {
		/* Fixup: Kill any reinstated backing storage pages */
		if (obj->madv == __I915_MADV_PURGED)
			i915_gem_object_truncate(obj);
	}
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	return ret;
}

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/**
 * Reads data from the object referenced by handle.
 *
 * On error, the contents of *data are undefined.
 */
int
i915_gem_pread_ioctl(struct drm_device *dev, void *data,
521
		     struct drm_file *file)
522 523
{
	struct drm_i915_gem_pread *args = data;
524
	struct drm_i915_gem_object *obj;
525
	int ret = 0;
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	if (args->size == 0)
		return 0;

	if (!access_ok(VERIFY_WRITE,
		       (char __user *)(uintptr_t)args->data_ptr,
		       args->size))
		return -EFAULT;

535
	ret = i915_mutex_lock_interruptible(dev);
536
	if (ret)
537
		return ret;
538

539
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
540
	if (&obj->base == NULL) {
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		ret = -ENOENT;
		goto unlock;
543
	}
544

545
	/* Bounds check source.  */
546 547
	if (args->offset > obj->base.size ||
	    args->size > obj->base.size - args->offset) {
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		ret = -EINVAL;
549
		goto out;
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	}

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	/* prime objects have no backing filp to GEM pread/pwrite
	 * pages from.
	 */
	if (!obj->base.filp) {
		ret = -EINVAL;
		goto out;
	}

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	trace_i915_gem_object_pread(obj, args->offset, args->size);

562
	ret = i915_gem_shmem_pread(dev, obj, args, file);
563

564
out:
565
	drm_gem_object_unreference(&obj->base);
566
unlock:
567
	mutex_unlock(&dev->struct_mutex);
568
	return ret;
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}

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/* This is the fast write path which cannot handle
 * page faults in the source data
573
 */
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static inline int
fast_user_write(struct io_mapping *mapping,
		loff_t page_base, int page_offset,
		char __user *user_data,
		int length)
580
{
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	void __iomem *vaddr_atomic;
	void *vaddr;
583
	unsigned long unwritten;
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	vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
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	/* We can use the cpu mem copy function because this is X86. */
	vaddr = (void __force*)vaddr_atomic + page_offset;
	unwritten = __copy_from_user_inatomic_nocache(vaddr,
589
						      user_data, length);
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	io_mapping_unmap_atomic(vaddr_atomic);
591
	return unwritten;
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}

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/**
 * This is the fast pwrite path, where we copy the data directly from the
 * user into the GTT, uncached.
 */
598
static int
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i915_gem_gtt_pwrite_fast(struct drm_device *dev,
			 struct drm_i915_gem_object *obj,
601
			 struct drm_i915_gem_pwrite *args,
602
			 struct drm_file *file)
603
{
604
	drm_i915_private_t *dev_priv = dev->dev_private;
605
	ssize_t remain;
606
	loff_t offset, page_base;
607
	char __user *user_data;
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	int page_offset, page_length, ret;

610
	ret = i915_gem_object_pin(obj, 0, true, true);
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	if (ret)
		goto out;

	ret = i915_gem_object_set_to_gtt_domain(obj, true);
	if (ret)
		goto out_unpin;

	ret = i915_gem_object_put_fence(obj);
	if (ret)
		goto out_unpin;
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	user_data = (char __user *) (uintptr_t) args->data_ptr;
	remain = args->size;

625
	offset = obj->gtt_offset + args->offset;
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	while (remain > 0) {
		/* Operation in this page
		 *
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		 * page_base = page offset within aperture
		 * page_offset = offset within page
		 * page_length = bytes to copy for this page
633
		 */
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		page_base = offset & PAGE_MASK;
		page_offset = offset_in_page(offset);
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		page_length = remain;
		if ((page_offset + remain) > PAGE_SIZE)
			page_length = PAGE_SIZE - page_offset;

		/* If we get a fault while copying data, then (presumably) our
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		 * source page isn't available.  Return the error and we'll
		 * retry in the slow path.
643
		 */
644
		if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
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				    page_offset, user_data, page_length)) {
			ret = -EFAULT;
			goto out_unpin;
		}
649

650 651 652
		remain -= page_length;
		user_data += page_length;
		offset += page_length;
653 654
	}

D
Daniel Vetter 已提交
655 656 657
out_unpin:
	i915_gem_object_unpin(obj);
out:
658
	return ret;
659 660
}

661 662 663 664
/* Per-page copy function for the shmem pwrite fastpath.
 * Flushes invalid cachelines before writing to the target if
 * needs_clflush_before is set and flushes out any written cachelines after
 * writing if needs_clflush is set. */
665
static int
666 667 668 669 670
shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
		  char __user *user_data,
		  bool page_do_bit17_swizzling,
		  bool needs_clflush_before,
		  bool needs_clflush_after)
671
{
672
	char *vaddr;
673
	int ret;
674

675
	if (unlikely(page_do_bit17_swizzling))
676
		return -EINVAL;
677

678 679 680 681 682 683 684 685 686 687 688
	vaddr = kmap_atomic(page);
	if (needs_clflush_before)
		drm_clflush_virt_range(vaddr + shmem_page_offset,
				       page_length);
	ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
						user_data,
						page_length);
	if (needs_clflush_after)
		drm_clflush_virt_range(vaddr + shmem_page_offset,
				       page_length);
	kunmap_atomic(vaddr);
689

690
	return ret ? -EFAULT : 0;
691 692
}

693 694
/* Only difference to the fast-path function is that this can handle bit17
 * and uses non-atomic copy and kmap functions. */
695
static int
696 697 698 699 700
shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
		  char __user *user_data,
		  bool page_do_bit17_swizzling,
		  bool needs_clflush_before,
		  bool needs_clflush_after)
701
{
702 703
	char *vaddr;
	int ret;
704

705
	vaddr = kmap(page);
706
	if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
707 708 709
		shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
					     page_length,
					     page_do_bit17_swizzling);
710 711
	if (page_do_bit17_swizzling)
		ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
712 713
						user_data,
						page_length);
714 715 716 717 718
	else
		ret = __copy_from_user(vaddr + shmem_page_offset,
				       user_data,
				       page_length);
	if (needs_clflush_after)
719 720 721
		shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
					     page_length,
					     page_do_bit17_swizzling);
722
	kunmap(page);
723

724
	return ret ? -EFAULT : 0;
725 726 727
}

static int
728 729 730 731
i915_gem_shmem_pwrite(struct drm_device *dev,
		      struct drm_i915_gem_object *obj,
		      struct drm_i915_gem_pwrite *args,
		      struct drm_file *file)
732 733
{
	ssize_t remain;
734 735
	loff_t offset;
	char __user *user_data;
736
	int shmem_page_offset, page_length, ret = 0;
737
	int obj_do_bit17_swizzling, page_do_bit17_swizzling;
738
	int hit_slowpath = 0;
739 740
	int needs_clflush_after = 0;
	int needs_clflush_before = 0;
741 742
	int i;
	struct scatterlist *sg;
743

744
	user_data = (char __user *) (uintptr_t) args->data_ptr;
745 746
	remain = args->size;

747
	obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
748

749 750 751 752 753 754 755
	if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
		/* If we're not in the cpu write domain, set ourself into the gtt
		 * write domain and manually flush cachelines (if required). This
		 * optimizes for the case when the gpu will use the data
		 * right away and we therefore have to clflush anyway. */
		if (obj->cache_level == I915_CACHE_NONE)
			needs_clflush_after = 1;
C
Chris Wilson 已提交
756 757 758 759 760
		if (obj->gtt_space) {
			ret = i915_gem_object_set_to_gtt_domain(obj, true);
			if (ret)
				return ret;
		}
761 762 763 764 765 766 767
	}
	/* Same trick applies for invalidate partially written cachelines before
	 * writing.  */
	if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
	    && obj->cache_level == I915_CACHE_NONE)
		needs_clflush_before = 1;

768 769 770 771 772 773
	ret = i915_gem_object_get_pages(obj);
	if (ret)
		return ret;

	i915_gem_object_pin_pages(obj);

774
	offset = args->offset;
775
	obj->dirty = 1;
776

777
	for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) {
778
		struct page *page;
779
		int partial_cacheline_write;
780

781 782 783 784 785 786
		if (i < offset >> PAGE_SHIFT)
			continue;

		if (remain <= 0)
			break;

787 788 789 790 791
		/* Operation in this page
		 *
		 * shmem_page_offset = offset within page in shmem file
		 * page_length = bytes to copy for this page
		 */
792
		shmem_page_offset = offset_in_page(offset);
793 794 795 796 797

		page_length = remain;
		if ((shmem_page_offset + page_length) > PAGE_SIZE)
			page_length = PAGE_SIZE - shmem_page_offset;

798 799 800 801 802 803 804
		/* If we don't overwrite a cacheline completely we need to be
		 * careful to have up-to-date data by first clflushing. Don't
		 * overcomplicate things and flush the entire patch. */
		partial_cacheline_write = needs_clflush_before &&
			((shmem_page_offset | page_length)
				& (boot_cpu_data.x86_clflush_size - 1));

805
		page = sg_page(sg);
806 807 808
		page_do_bit17_swizzling = obj_do_bit17_swizzling &&
			(page_to_phys(page) & (1 << 17)) != 0;

809 810 811 812 813 814
		ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
					user_data, page_do_bit17_swizzling,
					partial_cacheline_write,
					needs_clflush_after);
		if (ret == 0)
			goto next_page;
815 816 817

		hit_slowpath = 1;
		mutex_unlock(&dev->struct_mutex);
818 819 820 821
		ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
					user_data, page_do_bit17_swizzling,
					partial_cacheline_write,
					needs_clflush_after);
822

823
		mutex_lock(&dev->struct_mutex);
824

825
next_page:
826 827 828
		set_page_dirty(page);
		mark_page_accessed(page);

829
		if (ret)
830 831
			goto out;

832
		remain -= page_length;
833
		user_data += page_length;
834
		offset += page_length;
835 836
	}

837
out:
838 839
	i915_gem_object_unpin_pages(obj);

840 841 842 843 844 845 846 847
	if (hit_slowpath) {
		/* Fixup: Kill any reinstated backing storage pages */
		if (obj->madv == __I915_MADV_PURGED)
			i915_gem_object_truncate(obj);
		/* and flush dirty cachelines in case the object isn't in the cpu write
		 * domain anymore. */
		if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
			i915_gem_clflush_object(obj);
848
			i915_gem_chipset_flush(dev);
849
		}
850
	}
851

852
	if (needs_clflush_after)
853
		i915_gem_chipset_flush(dev);
854

855
	return ret;
856 857 858 859 860 861 862 863 864
}

/**
 * Writes data to the object referenced by handle.
 *
 * On error, the contents of the buffer that were to be modified are undefined.
 */
int
i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
865
		      struct drm_file *file)
866 867
{
	struct drm_i915_gem_pwrite *args = data;
868
	struct drm_i915_gem_object *obj;
869 870 871 872 873 874 875 876 877 878
	int ret;

	if (args->size == 0)
		return 0;

	if (!access_ok(VERIFY_READ,
		       (char __user *)(uintptr_t)args->data_ptr,
		       args->size))
		return -EFAULT;

879 880
	ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr,
					   args->size);
881 882
	if (ret)
		return -EFAULT;
883

884
	ret = i915_mutex_lock_interruptible(dev);
885
	if (ret)
886
		return ret;
887

888
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
889
	if (&obj->base == NULL) {
890 891
		ret = -ENOENT;
		goto unlock;
892
	}
893

894
	/* Bounds check destination. */
895 896
	if (args->offset > obj->base.size ||
	    args->size > obj->base.size - args->offset) {
C
Chris Wilson 已提交
897
		ret = -EINVAL;
898
		goto out;
C
Chris Wilson 已提交
899 900
	}

901 902 903 904 905 906 907 908
	/* prime objects have no backing filp to GEM pread/pwrite
	 * pages from.
	 */
	if (!obj->base.filp) {
		ret = -EINVAL;
		goto out;
	}

C
Chris Wilson 已提交
909 910
	trace_i915_gem_object_pwrite(obj, args->offset, args->size);

D
Daniel Vetter 已提交
911
	ret = -EFAULT;
912 913 914 915 916 917
	/* We can only do the GTT pwrite on untiled buffers, as otherwise
	 * it would end up going through the fenced access, and we'll get
	 * different detiling behavior between reading and writing.
	 * pread/pwrite currently are reading and writing from the CPU
	 * perspective, requiring manual detiling by the client.
	 */
918
	if (obj->phys_obj) {
919
		ret = i915_gem_phys_pwrite(dev, obj, args, file);
920 921 922
		goto out;
	}

923
	if (obj->cache_level == I915_CACHE_NONE &&
924
	    obj->tiling_mode == I915_TILING_NONE &&
925
	    obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
926
		ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
D
Daniel Vetter 已提交
927 928 929
		/* Note that the gtt paths might fail with non-page-backed user
		 * pointers (e.g. gtt mappings when moving data between
		 * textures). Fallback to the shmem path in that case. */
930
	}
931

932
	if (ret == -EFAULT || ret == -ENOSPC)
D
Daniel Vetter 已提交
933
		ret = i915_gem_shmem_pwrite(dev, obj, args, file);
934

935
out:
936
	drm_gem_object_unreference(&obj->base);
937
unlock:
938
	mutex_unlock(&dev->struct_mutex);
939 940 941
	return ret;
}

942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129
int
i915_gem_check_wedge(struct drm_i915_private *dev_priv,
		     bool interruptible)
{
	if (atomic_read(&dev_priv->mm.wedged)) {
		struct completion *x = &dev_priv->error_completion;
		bool recovery_complete;
		unsigned long flags;

		/* Give the error handler a chance to run. */
		spin_lock_irqsave(&x->wait.lock, flags);
		recovery_complete = x->done > 0;
		spin_unlock_irqrestore(&x->wait.lock, flags);

		/* Non-interruptible callers can't handle -EAGAIN, hence return
		 * -EIO unconditionally for these. */
		if (!interruptible)
			return -EIO;

		/* Recovery complete, but still wedged means reset failure. */
		if (recovery_complete)
			return -EIO;

		return -EAGAIN;
	}

	return 0;
}

/*
 * Compare seqno against outstanding lazy request. Emit a request if they are
 * equal.
 */
static int
i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
{
	int ret;

	BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));

	ret = 0;
	if (seqno == ring->outstanding_lazy_request)
		ret = i915_add_request(ring, NULL, NULL);

	return ret;
}

/**
 * __wait_seqno - wait until execution of seqno has finished
 * @ring: the ring expected to report seqno
 * @seqno: duh!
 * @interruptible: do an interruptible wait (normally yes)
 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
 *
 * Returns 0 if the seqno was found within the alloted time. Else returns the
 * errno with remaining time filled in timeout argument.
 */
static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
			bool interruptible, struct timespec *timeout)
{
	drm_i915_private_t *dev_priv = ring->dev->dev_private;
	struct timespec before, now, wait_time={1,0};
	unsigned long timeout_jiffies;
	long end;
	bool wait_forever = true;
	int ret;

	if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
		return 0;

	trace_i915_gem_request_wait_begin(ring, seqno);

	if (timeout != NULL) {
		wait_time = *timeout;
		wait_forever = false;
	}

	timeout_jiffies = timespec_to_jiffies(&wait_time);

	if (WARN_ON(!ring->irq_get(ring)))
		return -ENODEV;

	/* Record current time in case interrupted by signal, or wedged * */
	getrawmonotonic(&before);

#define EXIT_COND \
	(i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
	atomic_read(&dev_priv->mm.wedged))
	do {
		if (interruptible)
			end = wait_event_interruptible_timeout(ring->irq_queue,
							       EXIT_COND,
							       timeout_jiffies);
		else
			end = wait_event_timeout(ring->irq_queue, EXIT_COND,
						 timeout_jiffies);

		ret = i915_gem_check_wedge(dev_priv, interruptible);
		if (ret)
			end = ret;
	} while (end == 0 && wait_forever);

	getrawmonotonic(&now);

	ring->irq_put(ring);
	trace_i915_gem_request_wait_end(ring, seqno);
#undef EXIT_COND

	if (timeout) {
		struct timespec sleep_time = timespec_sub(now, before);
		*timeout = timespec_sub(*timeout, sleep_time);
	}

	switch (end) {
	case -EIO:
	case -EAGAIN: /* Wedged */
	case -ERESTARTSYS: /* Signal */
		return (int)end;
	case 0: /* Timeout */
		if (timeout)
			set_normalized_timespec(timeout, 0, 0);
		return -ETIME;
	default: /* Completed */
		WARN_ON(end < 0); /* We're not aware of other errors */
		return 0;
	}
}

/**
 * Waits for a sequence number to be signaled, and cleans up the
 * request and object lists appropriately for that event.
 */
int
i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
{
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	bool interruptible = dev_priv->mm.interruptible;
	int ret;

	BUG_ON(!mutex_is_locked(&dev->struct_mutex));
	BUG_ON(seqno == 0);

	ret = i915_gem_check_wedge(dev_priv, interruptible);
	if (ret)
		return ret;

	ret = i915_gem_check_olr(ring, seqno);
	if (ret)
		return ret;

	return __wait_seqno(ring, seqno, interruptible, NULL);
}

/**
 * Ensures that all rendering to the object has completed and the object is
 * safe to unbind from the GTT or access from the CPU.
 */
static __must_check int
i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
			       bool readonly)
{
	struct intel_ring_buffer *ring = obj->ring;
	u32 seqno;
	int ret;

	seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
	if (seqno == 0)
		return 0;

	ret = i915_wait_seqno(ring, seqno);
	if (ret)
		return ret;

	i915_gem_retire_requests_ring(ring);

	/* Manually manage the write flush as we may have not yet
	 * retired the buffer.
	 */
	if (obj->last_write_seqno &&
	    i915_seqno_passed(seqno, obj->last_write_seqno)) {
		obj->last_write_seqno = 0;
		obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
	}

	return 0;
}

1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175
/* A nonblocking variant of the above wait. This is a highly dangerous routine
 * as the object state may change during this call.
 */
static __must_check int
i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
					    bool readonly)
{
	struct drm_device *dev = obj->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_ring_buffer *ring = obj->ring;
	u32 seqno;
	int ret;

	BUG_ON(!mutex_is_locked(&dev->struct_mutex));
	BUG_ON(!dev_priv->mm.interruptible);

	seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
	if (seqno == 0)
		return 0;

	ret = i915_gem_check_wedge(dev_priv, true);
	if (ret)
		return ret;

	ret = i915_gem_check_olr(ring, seqno);
	if (ret)
		return ret;

	mutex_unlock(&dev->struct_mutex);
	ret = __wait_seqno(ring, seqno, true, NULL);
	mutex_lock(&dev->struct_mutex);

	i915_gem_retire_requests_ring(ring);

	/* Manually manage the write flush as we may have not yet
	 * retired the buffer.
	 */
	if (obj->last_write_seqno &&
	    i915_seqno_passed(seqno, obj->last_write_seqno)) {
		obj->last_write_seqno = 0;
		obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
	}

	return ret;
}

1176
/**
1177 1178
 * Called when user space prepares to use an object with the CPU, either
 * through the mmap ioctl's mapping or a GTT mapping.
1179 1180 1181
 */
int
i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1182
			  struct drm_file *file)
1183 1184
{
	struct drm_i915_gem_set_domain *args = data;
1185
	struct drm_i915_gem_object *obj;
1186 1187
	uint32_t read_domains = args->read_domains;
	uint32_t write_domain = args->write_domain;
1188 1189
	int ret;

1190
	/* Only handle setting domains to types used by the CPU. */
1191
	if (write_domain & I915_GEM_GPU_DOMAINS)
1192 1193
		return -EINVAL;

1194
	if (read_domains & I915_GEM_GPU_DOMAINS)
1195 1196 1197 1198 1199 1200 1201 1202
		return -EINVAL;

	/* Having something in the write domain implies it's in the read
	 * domain, and only that read domain.  Enforce that in the request.
	 */
	if (write_domain != 0 && read_domains != write_domain)
		return -EINVAL;

1203
	ret = i915_mutex_lock_interruptible(dev);
1204
	if (ret)
1205
		return ret;
1206

1207
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1208
	if (&obj->base == NULL) {
1209 1210
		ret = -ENOENT;
		goto unlock;
1211
	}
1212

1213 1214 1215 1216 1217 1218 1219 1220
	/* Try to flush the object off the GPU without holding the lock.
	 * We will repeat the flush holding the lock in the normal manner
	 * to catch cases where we are gazumped.
	 */
	ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
	if (ret)
		goto unref;

1221 1222
	if (read_domains & I915_GEM_DOMAIN_GTT) {
		ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1223 1224 1225 1226 1227 1228 1229

		/* Silently promote "you're not bound, there was nothing to do"
		 * to success, since the client was just asking us to
		 * make sure everything was done.
		 */
		if (ret == -EINVAL)
			ret = 0;
1230
	} else {
1231
		ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1232 1233
	}

1234
unref:
1235
	drm_gem_object_unreference(&obj->base);
1236
unlock:
1237 1238 1239 1240 1241 1242 1243 1244 1245
	mutex_unlock(&dev->struct_mutex);
	return ret;
}

/**
 * Called when user space has done writes to this buffer
 */
int
i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1246
			 struct drm_file *file)
1247 1248
{
	struct drm_i915_gem_sw_finish *args = data;
1249
	struct drm_i915_gem_object *obj;
1250 1251
	int ret = 0;

1252
	ret = i915_mutex_lock_interruptible(dev);
1253
	if (ret)
1254
		return ret;
1255

1256
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1257
	if (&obj->base == NULL) {
1258 1259
		ret = -ENOENT;
		goto unlock;
1260 1261 1262
	}

	/* Pinned buffers may be scanout, so flush the cache */
1263
	if (obj->pin_count)
1264 1265
		i915_gem_object_flush_cpu_write_domain(obj);

1266
	drm_gem_object_unreference(&obj->base);
1267
unlock:
1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280
	mutex_unlock(&dev->struct_mutex);
	return ret;
}

/**
 * Maps the contents of an object, returning the address it is mapped
 * into.
 *
 * While the mapping holds a reference on the contents of the object, it doesn't
 * imply a ref on the object itself.
 */
int
i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1281
		    struct drm_file *file)
1282 1283 1284 1285 1286
{
	struct drm_i915_gem_mmap *args = data;
	struct drm_gem_object *obj;
	unsigned long addr;

1287
	obj = drm_gem_object_lookup(dev, file, args->handle);
1288
	if (obj == NULL)
1289
		return -ENOENT;
1290

1291 1292 1293 1294 1295 1296 1297 1298
	/* prime objects have no backing filp to GEM mmap
	 * pages from.
	 */
	if (!obj->filp) {
		drm_gem_object_unreference_unlocked(obj);
		return -EINVAL;
	}

1299
	addr = vm_mmap(obj->filp, 0, args->size,
1300 1301
		       PROT_READ | PROT_WRITE, MAP_SHARED,
		       args->offset);
1302
	drm_gem_object_unreference_unlocked(obj);
1303 1304 1305 1306 1307 1308 1309 1310
	if (IS_ERR((void *)addr))
		return addr;

	args->addr_ptr = (uint64_t) addr;

	return 0;
}

1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328
/**
 * i915_gem_fault - fault a page into the GTT
 * vma: VMA in question
 * vmf: fault info
 *
 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
 * from userspace.  The fault handler takes care of binding the object to
 * the GTT (if needed), allocating and programming a fence register (again,
 * only if needed based on whether the old reg is still valid or the object
 * is tiled) and inserting a new PTE into the faulting process.
 *
 * Note that the faulting process may involve evicting existing objects
 * from the GTT and/or fence registers to make room.  So performance may
 * suffer if the GTT working set is large or there are few fence registers
 * left.
 */
int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
{
1329 1330
	struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
	struct drm_device *dev = obj->base.dev;
1331
	drm_i915_private_t *dev_priv = dev->dev_private;
1332 1333 1334
	pgoff_t page_offset;
	unsigned long pfn;
	int ret = 0;
1335
	bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1336 1337 1338 1339 1340

	/* We don't use vmf->pgoff since that has the fake offset */
	page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
		PAGE_SHIFT;

1341 1342 1343
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		goto out;
1344

C
Chris Wilson 已提交
1345 1346
	trace_i915_gem_object_fault(obj, page_offset, true, write);

1347
	/* Now bind it into the GTT if needed */
1348 1349 1350 1351
	if (!obj->map_and_fenceable) {
		ret = i915_gem_object_unbind(obj);
		if (ret)
			goto unlock;
1352
	}
1353
	if (!obj->gtt_space) {
1354
		ret = i915_gem_object_bind_to_gtt(obj, 0, true, false);
1355 1356
		if (ret)
			goto unlock;
1357

1358 1359 1360 1361
		ret = i915_gem_object_set_to_gtt_domain(obj, write);
		if (ret)
			goto unlock;
	}
1362

1363 1364 1365
	if (!obj->has_global_gtt_mapping)
		i915_gem_gtt_bind_object(obj, obj->cache_level);

1366
	ret = i915_gem_object_get_fence(obj);
1367 1368
	if (ret)
		goto unlock;
1369

1370 1371
	if (i915_gem_object_is_inactive(obj))
		list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1372

1373 1374
	obj->fault_mappable = true;

1375
	pfn = ((dev_priv->mm.gtt_base_addr + obj->gtt_offset) >> PAGE_SHIFT) +
1376 1377 1378 1379
		page_offset;

	/* Finally, remap it using the new GTT offset */
	ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1380
unlock:
1381
	mutex_unlock(&dev->struct_mutex);
1382
out:
1383
	switch (ret) {
1384
	case -EIO:
1385 1386 1387 1388 1389
		/* If this -EIO is due to a gpu hang, give the reset code a
		 * chance to clean up the mess. Otherwise return the proper
		 * SIGBUS. */
		if (!atomic_read(&dev_priv->mm.wedged))
			return VM_FAULT_SIGBUS;
1390
	case -EAGAIN:
1391 1392 1393 1394 1395 1396 1397
		/* Give the error handler a chance to run and move the
		 * objects off the GPU active list. Next time we service the
		 * fault, we should be able to transition the page into the
		 * GTT without touching the GPU (and so avoid further
		 * EIO/EGAIN). If the GPU is wedged, then there is no issue
		 * with coherency, just lost writes.
		 */
1398
		set_need_resched();
1399 1400
	case 0:
	case -ERESTARTSYS:
1401
	case -EINTR:
1402 1403 1404 1405 1406
	case -EBUSY:
		/*
		 * EBUSY is ok: this just means that another thread
		 * already did the job.
		 */
1407
		return VM_FAULT_NOPAGE;
1408 1409 1410
	case -ENOMEM:
		return VM_FAULT_OOM;
	default:
1411
		WARN_ON_ONCE(ret);
1412
		return VM_FAULT_SIGBUS;
1413 1414 1415
	}
}

1416 1417 1418 1419
/**
 * i915_gem_release_mmap - remove physical page mappings
 * @obj: obj in question
 *
1420
 * Preserve the reservation of the mmapping with the DRM core code, but
1421 1422 1423 1424 1425 1426 1427 1428 1429
 * relinquish ownership of the pages back to the system.
 *
 * It is vital that we remove the page mapping if we have mapped a tiled
 * object through the GTT and then lose the fence register due to
 * resource pressure. Similarly if the object has been moved out of the
 * aperture, than pages mapped into userspace must be revoked. Removing the
 * mapping will then trigger a page fault on the next user access, allowing
 * fixup by i915_gem_fault().
 */
1430
void
1431
i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1432
{
1433 1434
	if (!obj->fault_mappable)
		return;
1435

1436 1437 1438 1439
	if (obj->base.dev->dev_mapping)
		unmap_mapping_range(obj->base.dev->dev_mapping,
				    (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
				    obj->base.size, 1);
1440

1441
	obj->fault_mappable = false;
1442 1443
}

1444
static uint32_t
1445
i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1446
{
1447
	uint32_t gtt_size;
1448 1449

	if (INTEL_INFO(dev)->gen >= 4 ||
1450 1451
	    tiling_mode == I915_TILING_NONE)
		return size;
1452 1453 1454

	/* Previous chips need a power-of-two fence region when tiling */
	if (INTEL_INFO(dev)->gen == 3)
1455
		gtt_size = 1024*1024;
1456
	else
1457
		gtt_size = 512*1024;
1458

1459 1460
	while (gtt_size < size)
		gtt_size <<= 1;
1461

1462
	return gtt_size;
1463 1464
}

1465 1466 1467 1468 1469
/**
 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
 * @obj: object to check
 *
 * Return the required GTT alignment for an object, taking into account
1470
 * potential fence register mapping.
1471 1472
 */
static uint32_t
1473 1474 1475
i915_gem_get_gtt_alignment(struct drm_device *dev,
			   uint32_t size,
			   int tiling_mode)
1476 1477 1478 1479 1480
{
	/*
	 * Minimum alignment is 4k (GTT page size), but might be greater
	 * if a fence register is needed for the object.
	 */
1481
	if (INTEL_INFO(dev)->gen >= 4 ||
1482
	    tiling_mode == I915_TILING_NONE)
1483 1484
		return 4096;

1485 1486 1487 1488
	/*
	 * Previous chips need to be aligned to the size of the smallest
	 * fence register that can contain the object.
	 */
1489
	return i915_gem_get_gtt_size(dev, size, tiling_mode);
1490 1491
}

1492 1493 1494
/**
 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
 *					 unfenced object
1495 1496 1497
 * @dev: the device
 * @size: size of the object
 * @tiling_mode: tiling mode of the object
1498 1499 1500 1501
 *
 * Return the required GTT alignment for an object, only taking into account
 * unfenced tiled surface requirements.
 */
1502
uint32_t
1503 1504 1505
i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
				    uint32_t size,
				    int tiling_mode)
1506 1507 1508 1509 1510
{
	/*
	 * Minimum alignment is 4k (GTT page size) for sane hw.
	 */
	if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1511
	    tiling_mode == I915_TILING_NONE)
1512 1513
		return 4096;

1514 1515 1516
	/* Previous hardware however needs to be aligned to a power-of-two
	 * tile height. The simplest method for determining this is to reuse
	 * the power-of-tile object size.
1517
	 */
1518
	return i915_gem_get_gtt_size(dev, size, tiling_mode);
1519 1520
}

1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556
static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
	int ret;

	if (obj->base.map_list.map)
		return 0;

	ret = drm_gem_create_mmap_offset(&obj->base);
	if (ret != -ENOSPC)
		return ret;

	/* Badly fragmented mmap space? The only way we can recover
	 * space is by destroying unwanted objects. We can't randomly release
	 * mmap_offsets as userspace expects them to be persistent for the
	 * lifetime of the objects. The closest we can is to release the
	 * offsets on purgeable objects by truncating it and marking it purged,
	 * which prevents userspace from ever using that object again.
	 */
	i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
	ret = drm_gem_create_mmap_offset(&obj->base);
	if (ret != -ENOSPC)
		return ret;

	i915_gem_shrink_all(dev_priv);
	return drm_gem_create_mmap_offset(&obj->base);
}

static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
{
	if (!obj->base.map_list.map)
		return;

	drm_gem_free_mmap_offset(&obj->base);
}

1557
int
1558 1559 1560 1561
i915_gem_mmap_gtt(struct drm_file *file,
		  struct drm_device *dev,
		  uint32_t handle,
		  uint64_t *offset)
1562
{
1563
	struct drm_i915_private *dev_priv = dev->dev_private;
1564
	struct drm_i915_gem_object *obj;
1565 1566
	int ret;

1567
	ret = i915_mutex_lock_interruptible(dev);
1568
	if (ret)
1569
		return ret;
1570

1571
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1572
	if (&obj->base == NULL) {
1573 1574 1575
		ret = -ENOENT;
		goto unlock;
	}
1576

1577
	if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1578
		ret = -E2BIG;
1579
		goto out;
1580 1581
	}

1582
	if (obj->madv != I915_MADV_WILLNEED) {
1583
		DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1584 1585
		ret = -EINVAL;
		goto out;
1586 1587
	}

1588 1589 1590
	ret = i915_gem_object_create_mmap_offset(obj);
	if (ret)
		goto out;
1591

1592
	*offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1593

1594
out:
1595
	drm_gem_object_unreference(&obj->base);
1596
unlock:
1597
	mutex_unlock(&dev->struct_mutex);
1598
	return ret;
1599 1600
}

1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624
/**
 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
 * @dev: DRM device
 * @data: GTT mapping ioctl data
 * @file: GEM object info
 *
 * Simply returns the fake offset to userspace so it can mmap it.
 * The mmap call will end up in drm_gem_mmap(), which will set things
 * up so we can get faults in the handler above.
 *
 * The fault handler will take care of binding the object into the GTT
 * (since it may have been evicted to make room for something), allocating
 * a fence register, and mapping the appropriate aperture address into
 * userspace.
 */
int
i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file)
{
	struct drm_i915_gem_mmap_gtt *args = data;

	return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
}

D
Daniel Vetter 已提交
1625 1626 1627
/* Immediately discard the backing storage */
static void
i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1628 1629 1630
{
	struct inode *inode;

1631
	i915_gem_object_free_mmap_offset(obj);
1632

1633 1634
	if (obj->base.filp == NULL)
		return;
1635

D
Daniel Vetter 已提交
1636 1637 1638 1639 1640
	/* Our goal here is to return as much of the memory as
	 * is possible back to the system as we are called from OOM.
	 * To do this we must instruct the shmfs to drop all of its
	 * backing pages, *now*.
	 */
1641
	inode = obj->base.filp->f_path.dentry->d_inode;
D
Daniel Vetter 已提交
1642
	shmem_truncate_range(inode, 0, (loff_t)-1);
1643

D
Daniel Vetter 已提交
1644 1645
	obj->madv = __I915_MADV_PURGED;
}
1646

D
Daniel Vetter 已提交
1647 1648 1649 1650
static inline int
i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
{
	return obj->madv == I915_MADV_DONTNEED;
1651 1652
}

1653
static void
1654
i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1655
{
1656
	int page_count = obj->base.size / PAGE_SIZE;
1657
	struct scatterlist *sg;
C
Chris Wilson 已提交
1658
	int ret, i;
1659

1660
	BUG_ON(obj->madv == __I915_MADV_PURGED);
1661

C
Chris Wilson 已提交
1662 1663 1664 1665 1666 1667 1668 1669 1670 1671
	ret = i915_gem_object_set_to_cpu_domain(obj, true);
	if (ret) {
		/* In the event of a disaster, abandon all caches and
		 * hope for the best.
		 */
		WARN_ON(ret != -EIO);
		i915_gem_clflush_object(obj);
		obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
	}

1672
	if (i915_gem_object_needs_bit17_swizzle(obj))
1673 1674
		i915_gem_object_save_bit_17_swizzle(obj);

1675 1676
	if (obj->madv == I915_MADV_DONTNEED)
		obj->dirty = 0;
1677

1678 1679 1680
	for_each_sg(obj->pages->sgl, sg, page_count, i) {
		struct page *page = sg_page(sg);

1681
		if (obj->dirty)
1682
			set_page_dirty(page);
1683

1684
		if (obj->madv == I915_MADV_WILLNEED)
1685
			mark_page_accessed(page);
1686

1687
		page_cache_release(page);
1688
	}
1689
	obj->dirty = 0;
1690

1691 1692
	sg_free_table(obj->pages);
	kfree(obj->pages);
1693
}
C
Chris Wilson 已提交
1694

1695 1696 1697 1698 1699
static int
i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
{
	const struct drm_i915_gem_object_ops *ops = obj->ops;

1700
	if (obj->pages == NULL)
1701 1702 1703
		return 0;

	BUG_ON(obj->gtt_space);
C
Chris Wilson 已提交
1704

1705 1706 1707
	if (obj->pages_pin_count)
		return -EBUSY;

1708
	ops->put_pages(obj);
1709
	obj->pages = NULL;
1710 1711

	list_del(&obj->gtt_list);
C
Chris Wilson 已提交
1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727
	if (i915_gem_object_is_purgeable(obj))
		i915_gem_object_truncate(obj);

	return 0;
}

static long
i915_gem_purge(struct drm_i915_private *dev_priv, long target)
{
	struct drm_i915_gem_object *obj, *next;
	long count = 0;

	list_for_each_entry_safe(obj, next,
				 &dev_priv->mm.unbound_list,
				 gtt_list) {
		if (i915_gem_object_is_purgeable(obj) &&
1728
		    i915_gem_object_put_pages(obj) == 0) {
C
Chris Wilson 已提交
1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739
			count += obj->base.size >> PAGE_SHIFT;
			if (count >= target)
				return count;
		}
	}

	list_for_each_entry_safe(obj, next,
				 &dev_priv->mm.inactive_list,
				 mm_list) {
		if (i915_gem_object_is_purgeable(obj) &&
		    i915_gem_object_unbind(obj) == 0 &&
1740
		    i915_gem_object_put_pages(obj) == 0) {
C
Chris Wilson 已提交
1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757
			count += obj->base.size >> PAGE_SHIFT;
			if (count >= target)
				return count;
		}
	}

	return count;
}

static void
i915_gem_shrink_all(struct drm_i915_private *dev_priv)
{
	struct drm_i915_gem_object *obj, *next;

	i915_gem_evict_everything(dev_priv->dev);

	list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list)
1758
		i915_gem_object_put_pages(obj);
D
Daniel Vetter 已提交
1759 1760
}

1761
static int
C
Chris Wilson 已提交
1762
i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1763
{
C
Chris Wilson 已提交
1764
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1765 1766
	int page_count, i;
	struct address_space *mapping;
1767 1768
	struct sg_table *st;
	struct scatterlist *sg;
1769
	struct page *page;
C
Chris Wilson 已提交
1770
	gfp_t gfp;
1771

C
Chris Wilson 已提交
1772 1773 1774 1775 1776 1777 1778
	/* Assert that the object is not currently in any GPU domain. As it
	 * wasn't in the GTT, there shouldn't be any way it could have been in
	 * a GPU cache
	 */
	BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
	BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);

1779 1780 1781 1782
	st = kmalloc(sizeof(*st), GFP_KERNEL);
	if (st == NULL)
		return -ENOMEM;

1783
	page_count = obj->base.size / PAGE_SIZE;
1784 1785 1786
	if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
		sg_free_table(st);
		kfree(st);
1787
		return -ENOMEM;
1788
	}
1789

1790 1791 1792 1793 1794
	/* Get the list of pages out of our struct file.  They'll be pinned
	 * at this point until we release them.
	 *
	 * Fail silently without starting the shrinker
	 */
C
Chris Wilson 已提交
1795 1796
	mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
	gfp = mapping_gfp_mask(mapping);
S
Sedat Dilek 已提交
1797
	gfp |= __GFP_NORETRY | __GFP_NOWARN;
C
Chris Wilson 已提交
1798
	gfp &= ~(__GFP_IO | __GFP_WAIT);
1799
	for_each_sg(st->sgl, sg, page_count, i) {
C
Chris Wilson 已提交
1800 1801 1802 1803 1804 1805 1806 1807 1808 1809
		page = shmem_read_mapping_page_gfp(mapping, i, gfp);
		if (IS_ERR(page)) {
			i915_gem_purge(dev_priv, page_count);
			page = shmem_read_mapping_page_gfp(mapping, i, gfp);
		}
		if (IS_ERR(page)) {
			/* We've tried hard to allocate the memory by reaping
			 * our own buffer, now let the real VM do its job and
			 * go down in flames if truly OOM.
			 */
S
Sedat Dilek 已提交
1810
			gfp &= ~(__GFP_NORETRY | __GFP_NOWARN);
C
Chris Wilson 已提交
1811 1812 1813 1814 1815 1816 1817
			gfp |= __GFP_IO | __GFP_WAIT;

			i915_gem_shrink_all(dev_priv);
			page = shmem_read_mapping_page_gfp(mapping, i, gfp);
			if (IS_ERR(page))
				goto err_pages;

S
Sedat Dilek 已提交
1818
			gfp |= __GFP_NORETRY | __GFP_NOWARN;
C
Chris Wilson 已提交
1819 1820
			gfp &= ~(__GFP_IO | __GFP_WAIT);
		}
1821

1822
		sg_set_page(sg, page, PAGE_SIZE, 0);
1823 1824
	}

1825
	if (i915_gem_object_needs_bit17_swizzle(obj))
1826 1827
		i915_gem_object_do_bit_17_swizzle(obj);

1828
	obj->pages = st;
1829 1830 1831
	return 0;

err_pages:
1832 1833 1834 1835
	for_each_sg(st->sgl, sg, i, page_count)
		page_cache_release(sg_page(sg));
	sg_free_table(st);
	kfree(st);
1836
	return PTR_ERR(page);
1837 1838
}

1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852
/* Ensure that the associated pages are gathered from the backing storage
 * and pinned into our object. i915_gem_object_get_pages() may be called
 * multiple times before they are released by a single call to
 * i915_gem_object_put_pages() - once the pages are no longer referenced
 * either as a result of memory pressure (reaping pages under the shrinker)
 * or as the object is itself released.
 */
int
i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
{
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
	const struct drm_i915_gem_object_ops *ops = obj->ops;
	int ret;

1853
	if (obj->pages)
1854 1855
		return 0;

1856 1857
	BUG_ON(obj->pages_pin_count);

1858 1859 1860 1861 1862 1863 1864 1865
	ret = ops->get_pages(obj);
	if (ret)
		return ret;

	list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
	return 0;
}

1866
void
1867
i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1868 1869
			       struct intel_ring_buffer *ring,
			       u32 seqno)
1870
{
1871
	struct drm_device *dev = obj->base.dev;
1872
	struct drm_i915_private *dev_priv = dev->dev_private;
1873

1874
	BUG_ON(ring == NULL);
1875
	obj->ring = ring;
1876 1877

	/* Add a reference if we're newly entering the active list. */
1878 1879 1880
	if (!obj->active) {
		drm_gem_object_reference(&obj->base);
		obj->active = 1;
1881
	}
1882

1883
	/* Move from whatever list we were on to the tail of execution. */
1884 1885
	list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
	list_move_tail(&obj->ring_list, &ring->active_list);
1886

1887
	obj->last_read_seqno = seqno;
1888

1889
	if (obj->fenced_gpu_access) {
1890 1891
		obj->last_fenced_seqno = seqno;

1892 1893 1894 1895 1896 1897 1898 1899
		/* Bump MRU to take account of the delayed flush */
		if (obj->fence_reg != I915_FENCE_REG_NONE) {
			struct drm_i915_fence_reg *reg;

			reg = &dev_priv->fence_regs[obj->fence_reg];
			list_move_tail(&reg->lru_list,
				       &dev_priv->mm.fence_list);
		}
1900 1901 1902 1903 1904 1905 1906 1907 1908
	}
}

static void
i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
{
	struct drm_device *dev = obj->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

1909
	BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1910
	BUG_ON(!obj->active);
1911

1912 1913 1914 1915 1916
	if (obj->pin_count) /* are we a framebuffer? */
		intel_mark_fb_idle(obj);

	list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);

1917
	list_del_init(&obj->ring_list);
1918 1919
	obj->ring = NULL;

1920 1921 1922 1923 1924
	obj->last_read_seqno = 0;
	obj->last_write_seqno = 0;
	obj->base.write_domain = 0;

	obj->last_fenced_seqno = 0;
1925 1926 1927 1928 1929 1930
	obj->fenced_gpu_access = false;

	obj->active = 0;
	drm_gem_object_unreference(&obj->base);

	WARN_ON(i915_verify_lists(dev));
1931
}
1932

1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954
static u32
i915_gem_get_seqno(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	u32 seqno = dev_priv->next_seqno;

	/* reserve 0 for non-seqno */
	if (++dev_priv->next_seqno == 0)
		dev_priv->next_seqno = 1;

	return seqno;
}

u32
i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
{
	if (ring->outstanding_lazy_request == 0)
		ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev);

	return ring->outstanding_lazy_request;
}

1955
int
C
Chris Wilson 已提交
1956
i915_add_request(struct intel_ring_buffer *ring,
1957
		 struct drm_file *file,
1958
		 u32 *out_seqno)
1959
{
C
Chris Wilson 已提交
1960
	drm_i915_private_t *dev_priv = ring->dev->dev_private;
1961
	struct drm_i915_gem_request *request;
1962
	u32 request_ring_position;
1963
	u32 seqno;
1964
	int was_empty;
1965 1966
	int ret;

1967 1968 1969 1970 1971 1972 1973
	/*
	 * Emit any outstanding flushes - execbuf can fail to emit the flush
	 * after having emitted the batchbuffer command. Hence we need to fix
	 * things up similar to emitting the lazy request. The difference here
	 * is that the flush _must_ happen before the next request, no matter
	 * what.
	 */
1974 1975 1976
	ret = intel_ring_flush_all_caches(ring);
	if (ret)
		return ret;
1977

1978 1979 1980
	request = kmalloc(sizeof(*request), GFP_KERNEL);
	if (request == NULL)
		return -ENOMEM;
1981

1982
	seqno = i915_gem_next_request_seqno(ring);
1983

1984 1985 1986 1987 1988 1989 1990
	/* Record the position of the start of the request so that
	 * should we detect the updated seqno part-way through the
	 * GPU processing the request, we never over-estimate the
	 * position of the head.
	 */
	request_ring_position = intel_ring_get_tail(ring);

1991
	ret = ring->add_request(ring, &seqno);
1992 1993 1994 1995
	if (ret) {
		kfree(request);
		return ret;
	}
1996

C
Chris Wilson 已提交
1997
	trace_i915_gem_request_add(ring, seqno);
1998 1999

	request->seqno = seqno;
2000
	request->ring = ring;
2001
	request->tail = request_ring_position;
2002
	request->emitted_jiffies = jiffies;
2003 2004
	was_empty = list_empty(&ring->request_list);
	list_add_tail(&request->list, &ring->request_list);
2005
	request->file_priv = NULL;
2006

C
Chris Wilson 已提交
2007 2008 2009
	if (file) {
		struct drm_i915_file_private *file_priv = file->driver_priv;

2010
		spin_lock(&file_priv->mm.lock);
2011
		request->file_priv = file_priv;
2012
		list_add_tail(&request->client_list,
2013
			      &file_priv->mm.request_list);
2014
		spin_unlock(&file_priv->mm.lock);
2015
	}
2016

2017
	ring->outstanding_lazy_request = 0;
C
Chris Wilson 已提交
2018

B
Ben Gamari 已提交
2019
	if (!dev_priv->mm.suspended) {
2020 2021
		if (i915_enable_hangcheck) {
			mod_timer(&dev_priv->hangcheck_timer,
2022
				  round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2023
		}
2024
		if (was_empty) {
2025
			queue_delayed_work(dev_priv->wq,
2026 2027
					   &dev_priv->mm.retire_work,
					   round_jiffies_up_relative(HZ));
2028 2029
			intel_mark_busy(dev_priv->dev);
		}
B
Ben Gamari 已提交
2030
	}
2031

2032 2033
	if (out_seqno)
		*out_seqno = seqno;
2034
	return 0;
2035 2036
}

2037 2038
static inline void
i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2039
{
2040
	struct drm_i915_file_private *file_priv = request->file_priv;
2041

2042 2043
	if (!file_priv)
		return;
C
Chris Wilson 已提交
2044

2045
	spin_lock(&file_priv->mm.lock);
2046 2047 2048 2049
	if (request->file_priv) {
		list_del(&request->client_list);
		request->file_priv = NULL;
	}
2050
	spin_unlock(&file_priv->mm.lock);
2051 2052
}

2053 2054
static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
				      struct intel_ring_buffer *ring)
2055
{
2056 2057
	while (!list_empty(&ring->request_list)) {
		struct drm_i915_gem_request *request;
2058

2059 2060 2061
		request = list_first_entry(&ring->request_list,
					   struct drm_i915_gem_request,
					   list);
2062

2063
		list_del(&request->list);
2064
		i915_gem_request_remove_from_client(request);
2065 2066
		kfree(request);
	}
2067

2068
	while (!list_empty(&ring->active_list)) {
2069
		struct drm_i915_gem_object *obj;
2070

2071 2072 2073
		obj = list_first_entry(&ring->active_list,
				       struct drm_i915_gem_object,
				       ring_list);
2074

2075
		i915_gem_object_move_to_inactive(obj);
2076 2077 2078
	}
}

2079 2080 2081 2082 2083
static void i915_gem_reset_fences(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;

2084
	for (i = 0; i < dev_priv->num_fence_regs; i++) {
2085
		struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2086

2087
		i915_gem_write_fence(dev, i, NULL);
2088

2089 2090
		if (reg->obj)
			i915_gem_object_fence_lost(reg->obj);
2091

2092 2093 2094
		reg->pin_count = 0;
		reg->obj = NULL;
		INIT_LIST_HEAD(&reg->lru_list);
2095
	}
2096 2097

	INIT_LIST_HEAD(&dev_priv->mm.fence_list);
2098 2099
}

2100
void i915_gem_reset(struct drm_device *dev)
2101
{
2102
	struct drm_i915_private *dev_priv = dev->dev_private;
2103
	struct drm_i915_gem_object *obj;
2104
	struct intel_ring_buffer *ring;
2105
	int i;
2106

2107 2108
	for_each_ring(ring, dev_priv, i)
		i915_gem_reset_ring_lists(dev_priv, ring);
2109 2110 2111 2112

	/* Move everything out of the GPU domains to ensure we do any
	 * necessary invalidation upon reuse.
	 */
2113
	list_for_each_entry(obj,
2114
			    &dev_priv->mm.inactive_list,
2115
			    mm_list)
2116
	{
2117
		obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2118
	}
2119 2120

	/* The fence registers are invalidated so clear them out */
2121
	i915_gem_reset_fences(dev);
2122 2123 2124 2125 2126
}

/**
 * This function clears the request list as sequence numbers are passed.
 */
2127
void
C
Chris Wilson 已提交
2128
i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2129 2130
{
	uint32_t seqno;
2131
	int i;
2132

C
Chris Wilson 已提交
2133
	if (list_empty(&ring->request_list))
2134 2135
		return;

C
Chris Wilson 已提交
2136
	WARN_ON(i915_verify_lists(ring->dev));
2137

2138
	seqno = ring->get_seqno(ring, true);
2139

2140
	for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++)
2141 2142
		if (seqno >= ring->sync_seqno[i])
			ring->sync_seqno[i] = 0;
2143

2144
	while (!list_empty(&ring->request_list)) {
2145
		struct drm_i915_gem_request *request;
2146

2147
		request = list_first_entry(&ring->request_list,
2148 2149
					   struct drm_i915_gem_request,
					   list);
2150

2151
		if (!i915_seqno_passed(seqno, request->seqno))
2152
			break;
2153

C
Chris Wilson 已提交
2154
		trace_i915_gem_request_retire(ring, request->seqno);
2155 2156 2157 2158 2159 2160
		/* We know the GPU must have read the request to have
		 * sent us the seqno + interrupt, so use the position
		 * of tail of the request to update the last known position
		 * of the GPU head.
		 */
		ring->last_retired_head = request->tail;
2161

2162
		list_del(&request->list);
2163
		i915_gem_request_remove_from_client(request);
2164
		kfree(request);
2165 2166
	}

2167 2168 2169 2170
	/* Move any buffers on the active list that are no longer referenced
	 * by the ringbuffer to the flushing/inactive lists as appropriate.
	 */
	while (!list_empty(&ring->active_list)) {
2171
		struct drm_i915_gem_object *obj;
2172

2173
		obj = list_first_entry(&ring->active_list,
2174 2175
				      struct drm_i915_gem_object,
				      ring_list);
2176

2177
		if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2178 2179
			break;

2180
		i915_gem_object_move_to_inactive(obj);
2181
	}
2182

C
Chris Wilson 已提交
2183 2184
	if (unlikely(ring->trace_irq_seqno &&
		     i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2185
		ring->irq_put(ring);
C
Chris Wilson 已提交
2186
		ring->trace_irq_seqno = 0;
2187
	}
2188

C
Chris Wilson 已提交
2189
	WARN_ON(i915_verify_lists(ring->dev));
2190
}
2191

2192 2193 2194 2195
void
i915_gem_retire_requests(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
2196
	struct intel_ring_buffer *ring;
2197
	int i;
2198

2199 2200
	for_each_ring(ring, dev_priv, i)
		i915_gem_retire_requests_ring(ring);
2201 2202
}

2203
static void
2204 2205 2206 2207
i915_gem_retire_work_handler(struct work_struct *work)
{
	drm_i915_private_t *dev_priv;
	struct drm_device *dev;
2208
	struct intel_ring_buffer *ring;
2209 2210
	bool idle;
	int i;
2211 2212 2213 2214

	dev_priv = container_of(work, drm_i915_private_t,
				mm.retire_work.work);
	dev = dev_priv->dev;
2215

2216 2217
	/* Come back later if the device is busy... */
	if (!mutex_trylock(&dev->struct_mutex)) {
2218 2219
		queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
				   round_jiffies_up_relative(HZ));
2220 2221 2222
		return;
	}

2223
	i915_gem_retire_requests(dev);
2224

2225 2226
	/* Send a periodic flush down the ring so we don't hold onto GEM
	 * objects indefinitely.
2227
	 */
2228
	idle = true;
2229
	for_each_ring(ring, dev_priv, i) {
2230 2231
		if (ring->gpu_caches_dirty)
			i915_add_request(ring, NULL, NULL);
2232 2233

		idle &= list_empty(&ring->request_list);
2234 2235
	}

2236
	if (!dev_priv->mm.suspended && !idle)
2237 2238
		queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
				   round_jiffies_up_relative(HZ));
2239 2240
	if (idle)
		intel_mark_idle(dev);
2241

2242 2243 2244
	mutex_unlock(&dev->struct_mutex);
}

2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255
/**
 * Ensures that an object will eventually get non-busy by flushing any required
 * write domains, emitting any outstanding lazy request and retiring and
 * completed requests.
 */
static int
i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
{
	int ret;

	if (obj->active) {
2256
		ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2257 2258
		if (ret)
			return ret;
2259

2260 2261 2262 2263 2264 2265
		i915_gem_retire_requests_ring(obj->ring);
	}

	return 0;
}

2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293
/**
 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
 * @DRM_IOCTL_ARGS: standard ioctl arguments
 *
 * Returns 0 if successful, else an error is returned with the remaining time in
 * the timeout parameter.
 *  -ETIME: object is still busy after timeout
 *  -ERESTARTSYS: signal interrupted the wait
 *  -ENONENT: object doesn't exist
 * Also possible, but rare:
 *  -EAGAIN: GPU wedged
 *  -ENOMEM: damn
 *  -ENODEV: Internal IRQ fail
 *  -E?: The add request failed
 *
 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
 * non-zero timeout parameter the wait ioctl will wait for the given number of
 * nanoseconds on an object becoming unbusy. Since the wait itself does so
 * without holding struct_mutex the object may become re-busied before this
 * function completes. A similar but shorter * race condition exists in the busy
 * ioctl
 */
int
i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
{
	struct drm_i915_gem_wait *args = data;
	struct drm_i915_gem_object *obj;
	struct intel_ring_buffer *ring = NULL;
2294
	struct timespec timeout_stack, *timeout = NULL;
2295 2296 2297
	u32 seqno = 0;
	int ret = 0;

2298 2299 2300 2301
	if (args->timeout_ns >= 0) {
		timeout_stack = ns_to_timespec(args->timeout_ns);
		timeout = &timeout_stack;
	}
2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312

	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;

	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
	if (&obj->base == NULL) {
		mutex_unlock(&dev->struct_mutex);
		return -ENOENT;
	}

2313 2314
	/* Need to make sure the object gets inactive eventually. */
	ret = i915_gem_object_flush_active(obj);
2315 2316 2317 2318
	if (ret)
		goto out;

	if (obj->active) {
2319
		seqno = obj->last_read_seqno;
2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336
		ring = obj->ring;
	}

	if (seqno == 0)
		 goto out;

	/* Do this after OLR check to make sure we make forward progress polling
	 * on this IOCTL with a 0 timeout (like busy ioctl)
	 */
	if (!args->timeout_ns) {
		ret = -ETIME;
		goto out;
	}

	drm_gem_object_unreference(&obj->base);
	mutex_unlock(&dev->struct_mutex);

2337 2338 2339 2340 2341
	ret = __wait_seqno(ring, seqno, true, timeout);
	if (timeout) {
		WARN_ON(!timespec_valid(timeout));
		args->timeout_ns = timespec_to_ns(timeout);
	}
2342 2343 2344 2345 2346 2347 2348 2349
	return ret;

out:
	drm_gem_object_unreference(&obj->base);
	mutex_unlock(&dev->struct_mutex);
	return ret;
}

2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361
/**
 * i915_gem_object_sync - sync an object to a ring.
 *
 * @obj: object which may be in use on another ring.
 * @to: ring we wish to use the object on. May be NULL.
 *
 * This code is meant to abstract object synchronization with the GPU.
 * Calling with NULL implies synchronizing the object with the CPU
 * rather than a particular GPU ring.
 *
 * Returns 0 if successful, else propagates up the lower layer error.
 */
2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372
int
i915_gem_object_sync(struct drm_i915_gem_object *obj,
		     struct intel_ring_buffer *to)
{
	struct intel_ring_buffer *from = obj->ring;
	u32 seqno;
	int ret, idx;

	if (from == NULL || to == from)
		return 0;

2373
	if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2374
		return i915_gem_object_wait_rendering(obj, false);
2375 2376 2377

	idx = intel_ring_sync_index(from, to);

2378
	seqno = obj->last_read_seqno;
2379 2380 2381
	if (seqno <= from->sync_seqno[idx])
		return 0;

2382 2383 2384
	ret = i915_gem_check_olr(obj->ring, seqno);
	if (ret)
		return ret;
2385

2386
	ret = to->sync_to(to, from, seqno);
2387 2388
	if (!ret)
		from->sync_seqno[idx] = seqno;
2389

2390
	return ret;
2391 2392
}

2393 2394 2395 2396 2397 2398 2399 2400 2401 2402
static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
{
	u32 old_write_domain, old_read_domains;

	/* Act a barrier for all accesses through the GTT */
	mb();

	/* Force a pagefault for domain tracking on next user access */
	i915_gem_release_mmap(obj);

2403 2404 2405
	if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
		return;

2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416
	old_read_domains = obj->base.read_domains;
	old_write_domain = obj->base.write_domain;

	obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
	obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;

	trace_i915_gem_object_change_domain(obj,
					    old_read_domains,
					    old_write_domain);
}

2417 2418 2419
/**
 * Unbinds an object from the GTT aperture.
 */
2420
int
2421
i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2422
{
2423
	drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2424 2425
	int ret = 0;

2426
	if (obj->gtt_space == NULL)
2427 2428
		return 0;

2429 2430
	if (obj->pin_count)
		return -EBUSY;
2431

2432 2433
	BUG_ON(obj->pages == NULL);

2434
	ret = i915_gem_object_finish_gpu(obj);
2435
	if (ret)
2436 2437 2438 2439 2440 2441
		return ret;
	/* Continue on if we fail due to EIO, the GPU is hung so we
	 * should be safe and we need to cleanup or else we might
	 * cause memory corruption through use-after-free.
	 */

2442
	i915_gem_object_finish_gtt(obj);
2443

2444
	/* release the fence reg _after_ flushing */
2445
	ret = i915_gem_object_put_fence(obj);
2446
	if (ret)
2447
		return ret;
2448

C
Chris Wilson 已提交
2449 2450
	trace_i915_gem_object_unbind(obj);

2451 2452
	if (obj->has_global_gtt_mapping)
		i915_gem_gtt_unbind_object(obj);
2453 2454 2455 2456
	if (obj->has_aliasing_ppgtt_mapping) {
		i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
		obj->has_aliasing_ppgtt_mapping = 0;
	}
2457
	i915_gem_gtt_finish_object(obj);
2458

C
Chris Wilson 已提交
2459 2460
	list_del(&obj->mm_list);
	list_move_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
2461
	/* Avoid an unnecessary call to unbind on rebind. */
2462
	obj->map_and_fenceable = true;
2463

2464 2465 2466
	drm_mm_put_block(obj->gtt_space);
	obj->gtt_space = NULL;
	obj->gtt_offset = 0;
2467

C
Chris Wilson 已提交
2468
	return 0;
2469 2470
}

2471
static int i915_ring_idle(struct intel_ring_buffer *ring)
2472
{
2473
	if (list_empty(&ring->active_list))
2474 2475
		return 0;

2476
	return i915_wait_seqno(ring, i915_gem_next_request_seqno(ring));
2477 2478
}

2479
int i915_gpu_idle(struct drm_device *dev)
2480 2481
{
	drm_i915_private_t *dev_priv = dev->dev_private;
2482
	struct intel_ring_buffer *ring;
2483
	int ret, i;
2484 2485

	/* Flush everything onto the inactive list. */
2486
	for_each_ring(ring, dev_priv, i) {
2487
		ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2488 2489
		if (ret)
			return ret;
2490 2491

		ret = i915_ring_idle(ring);
2492 2493
		if (ret)
			return ret;
2494
	}
2495

2496
	return 0;
2497 2498
}

2499 2500
static void sandybridge_write_fence_reg(struct drm_device *dev, int reg,
					struct drm_i915_gem_object *obj)
2501 2502 2503 2504
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	uint64_t val;

2505 2506
	if (obj) {
		u32 size = obj->gtt_space->size;
2507

2508 2509 2510 2511 2512
		val = (uint64_t)((obj->gtt_offset + size - 4096) &
				 0xfffff000) << 32;
		val |= obj->gtt_offset & 0xfffff000;
		val |= (uint64_t)((obj->stride / 128) - 1) <<
			SANDYBRIDGE_FENCE_PITCH_SHIFT;
2513

2514 2515 2516 2517 2518
		if (obj->tiling_mode == I915_TILING_Y)
			val |= 1 << I965_FENCE_TILING_Y_SHIFT;
		val |= I965_FENCE_REG_VALID;
	} else
		val = 0;
2519

2520 2521
	I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val);
	POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8);
2522 2523
}

2524 2525
static void i965_write_fence_reg(struct drm_device *dev, int reg,
				 struct drm_i915_gem_object *obj)
2526 2527 2528 2529
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	uint64_t val;

2530 2531
	if (obj) {
		u32 size = obj->gtt_space->size;
2532

2533 2534 2535 2536 2537 2538 2539 2540 2541
		val = (uint64_t)((obj->gtt_offset + size - 4096) &
				 0xfffff000) << 32;
		val |= obj->gtt_offset & 0xfffff000;
		val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
		if (obj->tiling_mode == I915_TILING_Y)
			val |= 1 << I965_FENCE_TILING_Y_SHIFT;
		val |= I965_FENCE_REG_VALID;
	} else
		val = 0;
2542

2543 2544
	I915_WRITE64(FENCE_REG_965_0 + reg * 8, val);
	POSTING_READ(FENCE_REG_965_0 + reg * 8);
2545 2546
}

2547 2548
static void i915_write_fence_reg(struct drm_device *dev, int reg,
				 struct drm_i915_gem_object *obj)
2549 2550
{
	drm_i915_private_t *dev_priv = dev->dev_private;
2551
	u32 val;
2552

2553 2554 2555 2556
	if (obj) {
		u32 size = obj->gtt_space->size;
		int pitch_val;
		int tile_width;
2557

2558 2559 2560 2561 2562
		WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
		     (size & -size) != size ||
		     (obj->gtt_offset & (size - 1)),
		     "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
		     obj->gtt_offset, obj->map_and_fenceable, size);
2563

2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588
		if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
			tile_width = 128;
		else
			tile_width = 512;

		/* Note: pitch better be a power of two tile widths */
		pitch_val = obj->stride / tile_width;
		pitch_val = ffs(pitch_val) - 1;

		val = obj->gtt_offset;
		if (obj->tiling_mode == I915_TILING_Y)
			val |= 1 << I830_FENCE_TILING_Y_SHIFT;
		val |= I915_FENCE_SIZE_BITS(size);
		val |= pitch_val << I830_FENCE_PITCH_SHIFT;
		val |= I830_FENCE_REG_VALID;
	} else
		val = 0;

	if (reg < 8)
		reg = FENCE_REG_830_0 + reg * 4;
	else
		reg = FENCE_REG_945_8 + (reg - 8) * 4;

	I915_WRITE(reg, val);
	POSTING_READ(reg);
2589 2590
}

2591 2592
static void i830_write_fence_reg(struct drm_device *dev, int reg,
				struct drm_i915_gem_object *obj)
2593 2594 2595 2596
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	uint32_t val;

2597 2598 2599
	if (obj) {
		u32 size = obj->gtt_space->size;
		uint32_t pitch_val;
2600

2601 2602 2603 2604 2605
		WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
		     (size & -size) != size ||
		     (obj->gtt_offset & (size - 1)),
		     "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
		     obj->gtt_offset, size);
2606

2607 2608
		pitch_val = obj->stride / 128;
		pitch_val = ffs(pitch_val) - 1;
2609

2610 2611 2612 2613 2614 2615 2616 2617
		val = obj->gtt_offset;
		if (obj->tiling_mode == I915_TILING_Y)
			val |= 1 << I830_FENCE_TILING_Y_SHIFT;
		val |= I830_FENCE_SIZE_BITS(size);
		val |= pitch_val << I830_FENCE_PITCH_SHIFT;
		val |= I830_FENCE_REG_VALID;
	} else
		val = 0;
2618

2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634
	I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
	POSTING_READ(FENCE_REG_830_0 + reg * 4);
}

static void i915_gem_write_fence(struct drm_device *dev, int reg,
				 struct drm_i915_gem_object *obj)
{
	switch (INTEL_INFO(dev)->gen) {
	case 7:
	case 6: sandybridge_write_fence_reg(dev, reg, obj); break;
	case 5:
	case 4: i965_write_fence_reg(dev, reg, obj); break;
	case 3: i915_write_fence_reg(dev, reg, obj); break;
	case 2: i830_write_fence_reg(dev, reg, obj); break;
	default: break;
	}
2635 2636
}

2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662
static inline int fence_number(struct drm_i915_private *dev_priv,
			       struct drm_i915_fence_reg *fence)
{
	return fence - dev_priv->fence_regs;
}

static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
					 struct drm_i915_fence_reg *fence,
					 bool enable)
{
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
	int reg = fence_number(dev_priv, fence);

	i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);

	if (enable) {
		obj->fence_reg = reg;
		fence->obj = obj;
		list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
	} else {
		obj->fence_reg = I915_FENCE_REG_NONE;
		fence->obj = NULL;
		list_del_init(&fence->lru_list);
	}
}

2663
static int
C
Chris Wilson 已提交
2664
i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
2665
{
2666
	if (obj->last_fenced_seqno) {
2667
		int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2668 2669
		if (ret)
			return ret;
2670 2671 2672 2673

		obj->last_fenced_seqno = 0;
	}

2674 2675 2676 2677 2678 2679
	/* Ensure that all CPU reads are completed before installing a fence
	 * and all writes before removing the fence.
	 */
	if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
		mb();

2680
	obj->fenced_gpu_access = false;
2681 2682 2683 2684 2685 2686
	return 0;
}

int
i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
{
2687
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2688 2689
	int ret;

C
Chris Wilson 已提交
2690
	ret = i915_gem_object_flush_fence(obj);
2691 2692 2693
	if (ret)
		return ret;

2694 2695
	if (obj->fence_reg == I915_FENCE_REG_NONE)
		return 0;
2696

2697 2698 2699 2700
	i915_gem_object_update_fence(obj,
				     &dev_priv->fence_regs[obj->fence_reg],
				     false);
	i915_gem_object_fence_lost(obj);
2701 2702 2703 2704 2705

	return 0;
}

static struct drm_i915_fence_reg *
C
Chris Wilson 已提交
2706
i915_find_fence_reg(struct drm_device *dev)
2707 2708
{
	struct drm_i915_private *dev_priv = dev->dev_private;
C
Chris Wilson 已提交
2709
	struct drm_i915_fence_reg *reg, *avail;
2710
	int i;
2711 2712

	/* First try to find a free reg */
2713
	avail = NULL;
2714 2715 2716
	for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
		reg = &dev_priv->fence_regs[i];
		if (!reg->obj)
2717
			return reg;
2718

2719
		if (!reg->pin_count)
2720
			avail = reg;
2721 2722
	}

2723 2724
	if (avail == NULL)
		return NULL;
2725 2726

	/* None available, try to steal one or wait for a user to finish */
2727
	list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2728
		if (reg->pin_count)
2729 2730
			continue;

C
Chris Wilson 已提交
2731
		return reg;
2732 2733
	}

C
Chris Wilson 已提交
2734
	return NULL;
2735 2736
}

2737
/**
2738
 * i915_gem_object_get_fence - set up fencing for an object
2739 2740 2741 2742 2743 2744 2745 2746 2747
 * @obj: object to map through a fence reg
 *
 * When mapping objects through the GTT, userspace wants to be able to write
 * to them without having to worry about swizzling if the object is tiled.
 * This function walks the fence regs looking for a free one for @obj,
 * stealing one if it can't find any.
 *
 * It then sets up the reg based on the object's properties: address, pitch
 * and tiling format.
2748 2749
 *
 * For an untiled surface, this removes any existing fence.
2750
 */
2751
int
2752
i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2753
{
2754
	struct drm_device *dev = obj->base.dev;
J
Jesse Barnes 已提交
2755
	struct drm_i915_private *dev_priv = dev->dev_private;
2756
	bool enable = obj->tiling_mode != I915_TILING_NONE;
2757
	struct drm_i915_fence_reg *reg;
2758
	int ret;
2759

2760 2761 2762
	/* Have we updated the tiling parameters upon the object and so
	 * will need to serialise the write to the associated fence register?
	 */
2763
	if (obj->fence_dirty) {
2764 2765 2766 2767
		ret = i915_gem_object_flush_fence(obj);
		if (ret)
			return ret;
	}
2768

2769
	/* Just update our place in the LRU if our fence is getting reused. */
2770 2771
	if (obj->fence_reg != I915_FENCE_REG_NONE) {
		reg = &dev_priv->fence_regs[obj->fence_reg];
2772
		if (!obj->fence_dirty) {
2773 2774 2775 2776 2777 2778 2779 2780
			list_move_tail(&reg->lru_list,
				       &dev_priv->mm.fence_list);
			return 0;
		}
	} else if (enable) {
		reg = i915_find_fence_reg(dev);
		if (reg == NULL)
			return -EDEADLK;
2781

2782 2783 2784 2785
		if (reg->obj) {
			struct drm_i915_gem_object *old = reg->obj;

			ret = i915_gem_object_flush_fence(old);
2786 2787 2788
			if (ret)
				return ret;

2789
			i915_gem_object_fence_lost(old);
2790
		}
2791
	} else
2792 2793
		return 0;

2794
	i915_gem_object_update_fence(obj, reg, enable);
2795
	obj->fence_dirty = false;
2796

2797
	return 0;
2798 2799
}

2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869
static bool i915_gem_valid_gtt_space(struct drm_device *dev,
				     struct drm_mm_node *gtt_space,
				     unsigned long cache_level)
{
	struct drm_mm_node *other;

	/* On non-LLC machines we have to be careful when putting differing
	 * types of snoopable memory together to avoid the prefetcher
	 * crossing memory domains and dieing.
	 */
	if (HAS_LLC(dev))
		return true;

	if (gtt_space == NULL)
		return true;

	if (list_empty(&gtt_space->node_list))
		return true;

	other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
	if (other->allocated && !other->hole_follows && other->color != cache_level)
		return false;

	other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
	if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
		return false;

	return true;
}

static void i915_gem_verify_gtt(struct drm_device *dev)
{
#if WATCH_GTT
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_gem_object *obj;
	int err = 0;

	list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
		if (obj->gtt_space == NULL) {
			printk(KERN_ERR "object found on GTT list with no space reserved\n");
			err++;
			continue;
		}

		if (obj->cache_level != obj->gtt_space->color) {
			printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
			       obj->gtt_space->start,
			       obj->gtt_space->start + obj->gtt_space->size,
			       obj->cache_level,
			       obj->gtt_space->color);
			err++;
			continue;
		}

		if (!i915_gem_valid_gtt_space(dev,
					      obj->gtt_space,
					      obj->cache_level)) {
			printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
			       obj->gtt_space->start,
			       obj->gtt_space->start + obj->gtt_space->size,
			       obj->cache_level);
			err++;
			continue;
		}
	}

	WARN_ON(err);
#endif
}

2870 2871 2872 2873
/**
 * Finds free space in the GTT aperture and binds the object there.
 */
static int
2874
i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2875
			    unsigned alignment,
2876 2877
			    bool map_and_fenceable,
			    bool nonblocking)
2878
{
2879
	struct drm_device *dev = obj->base.dev;
2880 2881
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_mm_node *free_space;
2882
	u32 size, fence_size, fence_alignment, unfenced_alignment;
2883
	bool mappable, fenceable;
2884
	int ret;
2885

2886
	if (obj->madv != I915_MADV_WILLNEED) {
2887 2888 2889 2890
		DRM_ERROR("Attempting to bind a purgeable object\n");
		return -EINVAL;
	}

2891 2892 2893 2894 2895 2896 2897 2898 2899 2900
	fence_size = i915_gem_get_gtt_size(dev,
					   obj->base.size,
					   obj->tiling_mode);
	fence_alignment = i915_gem_get_gtt_alignment(dev,
						     obj->base.size,
						     obj->tiling_mode);
	unfenced_alignment =
		i915_gem_get_unfenced_gtt_alignment(dev,
						    obj->base.size,
						    obj->tiling_mode);
2901

2902
	if (alignment == 0)
2903 2904
		alignment = map_and_fenceable ? fence_alignment :
						unfenced_alignment;
2905
	if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2906 2907 2908 2909
		DRM_ERROR("Invalid object alignment requested %u\n", alignment);
		return -EINVAL;
	}

2910
	size = map_and_fenceable ? fence_size : obj->base.size;
2911

2912 2913 2914
	/* If the object is bigger than the entire aperture, reject it early
	 * before evicting everything in a vain attempt to find space.
	 */
2915
	if (obj->base.size >
2916
	    (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2917 2918 2919 2920
		DRM_ERROR("Attempting to bind an object larger than the aperture\n");
		return -E2BIG;
	}

2921
	ret = i915_gem_object_get_pages(obj);
C
Chris Wilson 已提交
2922 2923 2924
	if (ret)
		return ret;

2925
 search_free:
2926
	if (map_and_fenceable)
2927
		free_space =
2928 2929 2930 2931
			drm_mm_search_free_in_range_color(&dev_priv->mm.gtt_space,
							  size, alignment, obj->cache_level,
							  0, dev_priv->mm.gtt_mappable_end,
							  false);
2932
	else
2933 2934 2935
		free_space = drm_mm_search_free_color(&dev_priv->mm.gtt_space,
						      size, alignment, obj->cache_level,
						      false);
2936 2937

	if (free_space != NULL) {
2938
		if (map_and_fenceable)
2939
			obj->gtt_space =
2940
				drm_mm_get_block_range_generic(free_space,
2941
							       size, alignment, obj->cache_level,
2942
							       0, dev_priv->mm.gtt_mappable_end,
2943
							       false);
2944
		else
2945
			obj->gtt_space =
2946 2947 2948
				drm_mm_get_block_generic(free_space,
							 size, alignment, obj->cache_level,
							 false);
2949
	}
2950
	if (obj->gtt_space == NULL) {
2951
		ret = i915_gem_evict_something(dev, size, alignment,
2952
					       obj->cache_level,
2953 2954
					       map_and_fenceable,
					       nonblocking);
2955
		if (ret)
2956
			return ret;
2957

2958 2959
		goto search_free;
	}
2960 2961 2962 2963 2964 2965 2966
	if (WARN_ON(!i915_gem_valid_gtt_space(dev,
					      obj->gtt_space,
					      obj->cache_level))) {
		drm_mm_put_block(obj->gtt_space);
		obj->gtt_space = NULL;
		return -EINVAL;
	}
2967 2968


2969
	ret = i915_gem_gtt_prepare_object(obj);
2970
	if (ret) {
2971 2972
		drm_mm_put_block(obj->gtt_space);
		obj->gtt_space = NULL;
C
Chris Wilson 已提交
2973
		return ret;
2974 2975
	}

2976 2977
	if (!dev_priv->mm.aliasing_ppgtt)
		i915_gem_gtt_bind_object(obj, obj->cache_level);
2978

C
Chris Wilson 已提交
2979
	list_move_tail(&obj->gtt_list, &dev_priv->mm.bound_list);
2980
	list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2981

2982
	obj->gtt_offset = obj->gtt_space->start;
C
Chris Wilson 已提交
2983

2984
	fenceable =
2985
		obj->gtt_space->size == fence_size &&
2986
		(obj->gtt_space->start & (fence_alignment - 1)) == 0;
2987

2988
	mappable =
2989
		obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2990

2991
	obj->map_and_fenceable = mappable && fenceable;
2992

C
Chris Wilson 已提交
2993
	trace_i915_gem_object_bind(obj, map_and_fenceable);
2994
	i915_gem_verify_gtt(dev);
2995 2996 2997 2998
	return 0;
}

void
2999
i915_gem_clflush_object(struct drm_i915_gem_object *obj)
3000 3001 3002 3003 3004
{
	/* If we don't have a page list set up, then we're not pinned
	 * to GPU, and we can ignore the cache flush because it'll happen
	 * again at bind time.
	 */
3005
	if (obj->pages == NULL)
3006 3007
		return;

3008 3009 3010 3011 3012 3013 3014 3015 3016 3017 3018
	/* If the GPU is snooping the contents of the CPU cache,
	 * we do not need to manually clear the CPU cache lines.  However,
	 * the caches are only snooped when the render cache is
	 * flushed/invalidated.  As we always have to emit invalidations
	 * and flushes when moving into and out of the RENDER domain, correct
	 * snooping behaviour occurs naturally as the result of our domain
	 * tracking.
	 */
	if (obj->cache_level != I915_CACHE_NONE)
		return;

C
Chris Wilson 已提交
3019
	trace_i915_gem_object_clflush(obj);
3020

3021
	drm_clflush_sg(obj->pages);
3022 3023
}

3024 3025
/** Flushes the GTT write domain for the object if it's dirty. */
static void
3026
i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3027
{
C
Chris Wilson 已提交
3028 3029
	uint32_t old_write_domain;

3030
	if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3031 3032
		return;

3033
	/* No actual flushing is required for the GTT write domain.  Writes
3034 3035
	 * to it immediately go to main memory as far as we know, so there's
	 * no chipset flush.  It also doesn't land in render cache.
3036 3037 3038 3039
	 *
	 * However, we do have to enforce the order so that all writes through
	 * the GTT land before any writes to the device, such as updates to
	 * the GATT itself.
3040
	 */
3041 3042
	wmb();

3043 3044
	old_write_domain = obj->base.write_domain;
	obj->base.write_domain = 0;
C
Chris Wilson 已提交
3045 3046

	trace_i915_gem_object_change_domain(obj,
3047
					    obj->base.read_domains,
C
Chris Wilson 已提交
3048
					    old_write_domain);
3049 3050 3051 3052
}

/** Flushes the CPU write domain for the object if it's dirty. */
static void
3053
i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3054
{
C
Chris Wilson 已提交
3055
	uint32_t old_write_domain;
3056

3057
	if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3058 3059 3060
		return;

	i915_gem_clflush_object(obj);
3061
	i915_gem_chipset_flush(obj->base.dev);
3062 3063
	old_write_domain = obj->base.write_domain;
	obj->base.write_domain = 0;
C
Chris Wilson 已提交
3064 3065

	trace_i915_gem_object_change_domain(obj,
3066
					    obj->base.read_domains,
C
Chris Wilson 已提交
3067
					    old_write_domain);
3068 3069
}

3070 3071 3072 3073 3074 3075
/**
 * Moves a single object to the GTT read, and possibly write domain.
 *
 * This function returns when the move is complete, including waiting on
 * flushes to occur.
 */
J
Jesse Barnes 已提交
3076
int
3077
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3078
{
3079
	drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
C
Chris Wilson 已提交
3080
	uint32_t old_write_domain, old_read_domains;
3081
	int ret;
3082

3083
	/* Not valid to be called on unbound objects. */
3084
	if (obj->gtt_space == NULL)
3085 3086
		return -EINVAL;

3087 3088 3089
	if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
		return 0;

3090 3091 3092
	ret = i915_gem_object_wait_rendering(obj, !write);
	if (ret)
		return ret;
3093

3094
	i915_gem_object_flush_cpu_write_domain(obj);
C
Chris Wilson 已提交
3095

3096 3097
	old_write_domain = obj->base.write_domain;
	old_read_domains = obj->base.read_domains;
C
Chris Wilson 已提交
3098

3099 3100 3101
	/* It should now be out of any other write domains, and we can update
	 * the domain values for our changes.
	 */
3102 3103
	BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
	obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3104
	if (write) {
3105 3106 3107
		obj->base.read_domains = I915_GEM_DOMAIN_GTT;
		obj->base.write_domain = I915_GEM_DOMAIN_GTT;
		obj->dirty = 1;
3108 3109
	}

C
Chris Wilson 已提交
3110 3111 3112 3113
	trace_i915_gem_object_change_domain(obj,
					    old_read_domains,
					    old_write_domain);

3114 3115 3116 3117
	/* And bump the LRU for this access */
	if (i915_gem_object_is_inactive(obj))
		list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);

3118 3119 3120
	return 0;
}

3121 3122 3123
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
				    enum i915_cache_level cache_level)
{
3124 3125
	struct drm_device *dev = obj->base.dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
3126 3127 3128 3129 3130 3131 3132 3133 3134 3135
	int ret;

	if (obj->cache_level == cache_level)
		return 0;

	if (obj->pin_count) {
		DRM_DEBUG("can not change the cache level of pinned objects\n");
		return -EBUSY;
	}

3136 3137 3138 3139 3140 3141
	if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) {
		ret = i915_gem_object_unbind(obj);
		if (ret)
			return ret;
	}

3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152
	if (obj->gtt_space) {
		ret = i915_gem_object_finish_gpu(obj);
		if (ret)
			return ret;

		i915_gem_object_finish_gtt(obj);

		/* Before SandyBridge, you could not use tiling or fence
		 * registers with snooped memory, so relinquish any fences
		 * currently pointing to our region in the aperture.
		 */
3153
		if (INTEL_INFO(dev)->gen < 6) {
3154 3155 3156 3157 3158
			ret = i915_gem_object_put_fence(obj);
			if (ret)
				return ret;
		}

3159 3160
		if (obj->has_global_gtt_mapping)
			i915_gem_gtt_bind_object(obj, cache_level);
3161 3162 3163
		if (obj->has_aliasing_ppgtt_mapping)
			i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
					       obj, cache_level);
3164 3165

		obj->gtt_space->color = cache_level;
3166 3167 3168 3169 3170 3171 3172 3173 3174 3175 3176 3177 3178 3179 3180 3181 3182 3183 3184 3185 3186 3187 3188 3189 3190 3191
	}

	if (cache_level == I915_CACHE_NONE) {
		u32 old_read_domains, old_write_domain;

		/* If we're coming from LLC cached, then we haven't
		 * actually been tracking whether the data is in the
		 * CPU cache or not, since we only allow one bit set
		 * in obj->write_domain and have been skipping the clflushes.
		 * Just set it to the CPU cache for now.
		 */
		WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
		WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);

		old_read_domains = obj->base.read_domains;
		old_write_domain = obj->base.write_domain;

		obj->base.read_domains = I915_GEM_DOMAIN_CPU;
		obj->base.write_domain = I915_GEM_DOMAIN_CPU;

		trace_i915_gem_object_change_domain(obj,
						    old_read_domains,
						    old_write_domain);
	}

	obj->cache_level = cache_level;
3192
	i915_gem_verify_gtt(dev);
3193 3194 3195
	return 0;
}

B
Ben Widawsky 已提交
3196 3197
int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file)
3198
{
B
Ben Widawsky 已提交
3199
	struct drm_i915_gem_caching *args = data;
3200 3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211 3212
	struct drm_i915_gem_object *obj;
	int ret;

	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;

	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
	if (&obj->base == NULL) {
		ret = -ENOENT;
		goto unlock;
	}

B
Ben Widawsky 已提交
3213
	args->caching = obj->cache_level != I915_CACHE_NONE;
3214 3215 3216 3217 3218 3219 3220

	drm_gem_object_unreference(&obj->base);
unlock:
	mutex_unlock(&dev->struct_mutex);
	return ret;
}

B
Ben Widawsky 已提交
3221 3222
int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file)
3223
{
B
Ben Widawsky 已提交
3224
	struct drm_i915_gem_caching *args = data;
3225 3226 3227 3228
	struct drm_i915_gem_object *obj;
	enum i915_cache_level level;
	int ret;

B
Ben Widawsky 已提交
3229 3230
	switch (args->caching) {
	case I915_CACHING_NONE:
3231 3232
		level = I915_CACHE_NONE;
		break;
B
Ben Widawsky 已提交
3233
	case I915_CACHING_CACHED:
3234 3235 3236 3237 3238 3239
		level = I915_CACHE_LLC;
		break;
	default:
		return -EINVAL;
	}

B
Ben Widawsky 已提交
3240 3241 3242 3243
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;

3244 3245 3246 3247 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
	if (&obj->base == NULL) {
		ret = -ENOENT;
		goto unlock;
	}

	ret = i915_gem_object_set_cache_level(obj, level);

	drm_gem_object_unreference(&obj->base);
unlock:
	mutex_unlock(&dev->struct_mutex);
	return ret;
}

3258
/*
3259 3260 3261
 * Prepare buffer for display plane (scanout, cursors, etc).
 * Can be called from an uninterruptible phase (modesetting) and allows
 * any flushes to be pipelined (for pageflips).
3262 3263
 */
int
3264 3265
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
				     u32 alignment,
3266
				     struct intel_ring_buffer *pipelined)
3267
{
3268
	u32 old_read_domains, old_write_domain;
3269 3270
	int ret;

3271
	if (pipelined != obj->ring) {
3272 3273
		ret = i915_gem_object_sync(obj, pipelined);
		if (ret)
3274 3275 3276
			return ret;
	}

3277 3278 3279 3280 3281 3282 3283 3284 3285 3286 3287 3288 3289
	/* The display engine is not coherent with the LLC cache on gen6.  As
	 * a result, we make sure that the pinning that is about to occur is
	 * done with uncached PTEs. This is lowest common denominator for all
	 * chipsets.
	 *
	 * However for gen6+, we could do better by using the GFDT bit instead
	 * of uncaching, which would allow us to flush all the LLC-cached data
	 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
	 */
	ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
	if (ret)
		return ret;

3290 3291 3292 3293
	/* As the user may map the buffer once pinned in the display plane
	 * (e.g. libkms for the bootup splash), we have to ensure that we
	 * always use map_and_fenceable for all scanout buffers.
	 */
3294
	ret = i915_gem_object_pin(obj, alignment, true, false);
3295 3296 3297
	if (ret)
		return ret;

3298 3299
	i915_gem_object_flush_cpu_write_domain(obj);

3300
	old_write_domain = obj->base.write_domain;
3301
	old_read_domains = obj->base.read_domains;
3302 3303 3304 3305

	/* It should now be out of any other write domains, and we can update
	 * the domain values for our changes.
	 */
3306
	obj->base.write_domain = 0;
3307
	obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3308 3309 3310

	trace_i915_gem_object_change_domain(obj,
					    old_read_domains,
3311
					    old_write_domain);
3312 3313 3314 3315

	return 0;
}

3316
int
3317
i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3318
{
3319 3320
	int ret;

3321
	if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3322 3323
		return 0;

3324
	ret = i915_gem_object_wait_rendering(obj, false);
3325 3326 3327
	if (ret)
		return ret;

3328 3329
	/* Ensure that we invalidate the GPU's caches and TLBs. */
	obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3330
	return 0;
3331 3332
}

3333 3334 3335 3336 3337 3338
/**
 * Moves a single object to the CPU read, and possibly write domain.
 *
 * This function returns when the move is complete, including waiting on
 * flushes to occur.
 */
3339
int
3340
i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3341
{
C
Chris Wilson 已提交
3342
	uint32_t old_write_domain, old_read_domains;
3343 3344
	int ret;

3345 3346 3347
	if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
		return 0;

3348 3349 3350
	ret = i915_gem_object_wait_rendering(obj, !write);
	if (ret)
		return ret;
3351

3352
	i915_gem_object_flush_gtt_write_domain(obj);
3353

3354 3355
	old_write_domain = obj->base.write_domain;
	old_read_domains = obj->base.read_domains;
C
Chris Wilson 已提交
3356

3357
	/* Flush the CPU cache if it's still invalid. */
3358
	if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3359 3360
		i915_gem_clflush_object(obj);

3361
		obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3362 3363 3364 3365 3366
	}

	/* It should now be out of any other write domains, and we can update
	 * the domain values for our changes.
	 */
3367
	BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3368 3369 3370 3371 3372

	/* If we're writing through the CPU, then the GPU read domains will
	 * need to be invalidated at next use.
	 */
	if (write) {
3373 3374
		obj->base.read_domains = I915_GEM_DOMAIN_CPU;
		obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3375
	}
3376

C
Chris Wilson 已提交
3377 3378 3379 3380
	trace_i915_gem_object_change_domain(obj,
					    old_read_domains,
					    old_write_domain);

3381 3382 3383
	return 0;
}

3384 3385 3386
/* Throttle our rendering by waiting until the ring has completed our requests
 * emitted over 20 msec ago.
 *
3387 3388 3389 3390
 * Note that if we were to use the current jiffies each time around the loop,
 * we wouldn't escape the function with any frames outstanding if the time to
 * render a frame was over 20ms.
 *
3391 3392 3393
 * This should get us reasonable parallelism between CPU and GPU but also
 * relatively low latency when blocking on a particular request to finish.
 */
3394
static int
3395
i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3396
{
3397 3398
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_file_private *file_priv = file->driver_priv;
3399
	unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3400 3401 3402 3403
	struct drm_i915_gem_request *request;
	struct intel_ring_buffer *ring = NULL;
	u32 seqno = 0;
	int ret;
3404

3405 3406 3407
	if (atomic_read(&dev_priv->mm.wedged))
		return -EIO;

3408
	spin_lock(&file_priv->mm.lock);
3409
	list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3410 3411
		if (time_after_eq(request->emitted_jiffies, recent_enough))
			break;
3412

3413 3414
		ring = request->ring;
		seqno = request->seqno;
3415
	}
3416
	spin_unlock(&file_priv->mm.lock);
3417

3418 3419
	if (seqno == 0)
		return 0;
3420

3421
	ret = __wait_seqno(ring, seqno, true, NULL);
3422 3423
	if (ret == 0)
		queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3424 3425 3426 3427

	return ret;
}

3428
int
3429 3430
i915_gem_object_pin(struct drm_i915_gem_object *obj,
		    uint32_t alignment,
3431 3432
		    bool map_and_fenceable,
		    bool nonblocking)
3433 3434 3435
{
	int ret;

3436 3437
	if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
		return -EBUSY;
3438

3439 3440 3441 3442
	if (obj->gtt_space != NULL) {
		if ((alignment && obj->gtt_offset & (alignment - 1)) ||
		    (map_and_fenceable && !obj->map_and_fenceable)) {
			WARN(obj->pin_count,
3443
			     "bo is already pinned with incorrect alignment:"
3444 3445
			     " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
			     " obj->map_and_fenceable=%d\n",
3446
			     obj->gtt_offset, alignment,
3447
			     map_and_fenceable,
3448
			     obj->map_and_fenceable);
3449 3450 3451 3452 3453 3454
			ret = i915_gem_object_unbind(obj);
			if (ret)
				return ret;
		}
	}

3455
	if (obj->gtt_space == NULL) {
3456
		ret = i915_gem_object_bind_to_gtt(obj, alignment,
3457 3458
						  map_and_fenceable,
						  nonblocking);
3459
		if (ret)
3460
			return ret;
3461
	}
J
Jesse Barnes 已提交
3462

3463 3464 3465
	if (!obj->has_global_gtt_mapping && map_and_fenceable)
		i915_gem_gtt_bind_object(obj, obj->cache_level);

3466
	obj->pin_count++;
3467
	obj->pin_mappable |= map_and_fenceable;
3468 3469 3470 3471 3472

	return 0;
}

void
3473
i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3474
{
3475 3476
	BUG_ON(obj->pin_count == 0);
	BUG_ON(obj->gtt_space == NULL);
3477

3478
	if (--obj->pin_count == 0)
3479
		obj->pin_mappable = false;
3480 3481 3482 3483
}

int
i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3484
		   struct drm_file *file)
3485 3486
{
	struct drm_i915_gem_pin *args = data;
3487
	struct drm_i915_gem_object *obj;
3488 3489
	int ret;

3490 3491 3492
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;
3493

3494
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3495
	if (&obj->base == NULL) {
3496 3497
		ret = -ENOENT;
		goto unlock;
3498 3499
	}

3500
	if (obj->madv != I915_MADV_WILLNEED) {
C
Chris Wilson 已提交
3501
		DRM_ERROR("Attempting to pin a purgeable buffer\n");
3502 3503
		ret = -EINVAL;
		goto out;
3504 3505
	}

3506
	if (obj->pin_filp != NULL && obj->pin_filp != file) {
J
Jesse Barnes 已提交
3507 3508
		DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
			  args->handle);
3509 3510
		ret = -EINVAL;
		goto out;
J
Jesse Barnes 已提交
3511 3512
	}

3513 3514 3515
	obj->user_pin_count++;
	obj->pin_filp = file;
	if (obj->user_pin_count == 1) {
3516
		ret = i915_gem_object_pin(obj, args->alignment, true, false);
3517 3518
		if (ret)
			goto out;
3519 3520 3521 3522 3523
	}

	/* XXX - flush the CPU caches for pinned objects
	 * as the X server doesn't manage domains yet
	 */
3524
	i915_gem_object_flush_cpu_write_domain(obj);
3525
	args->offset = obj->gtt_offset;
3526
out:
3527
	drm_gem_object_unreference(&obj->base);
3528
unlock:
3529
	mutex_unlock(&dev->struct_mutex);
3530
	return ret;
3531 3532 3533 3534
}

int
i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3535
		     struct drm_file *file)
3536 3537
{
	struct drm_i915_gem_pin *args = data;
3538
	struct drm_i915_gem_object *obj;
3539
	int ret;
3540

3541 3542 3543
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;
3544

3545
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3546
	if (&obj->base == NULL) {
3547 3548
		ret = -ENOENT;
		goto unlock;
3549
	}
3550

3551
	if (obj->pin_filp != file) {
J
Jesse Barnes 已提交
3552 3553
		DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
			  args->handle);
3554 3555
		ret = -EINVAL;
		goto out;
J
Jesse Barnes 已提交
3556
	}
3557 3558 3559
	obj->user_pin_count--;
	if (obj->user_pin_count == 0) {
		obj->pin_filp = NULL;
J
Jesse Barnes 已提交
3560 3561
		i915_gem_object_unpin(obj);
	}
3562

3563
out:
3564
	drm_gem_object_unreference(&obj->base);
3565
unlock:
3566
	mutex_unlock(&dev->struct_mutex);
3567
	return ret;
3568 3569 3570 3571
}

int
i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3572
		    struct drm_file *file)
3573 3574
{
	struct drm_i915_gem_busy *args = data;
3575
	struct drm_i915_gem_object *obj;
3576 3577
	int ret;

3578
	ret = i915_mutex_lock_interruptible(dev);
3579
	if (ret)
3580
		return ret;
3581

3582
	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3583
	if (&obj->base == NULL) {
3584 3585
		ret = -ENOENT;
		goto unlock;
3586
	}
3587

3588 3589 3590 3591
	/* Count all active objects as busy, even if they are currently not used
	 * by the gpu. Users of this interface expect objects to eventually
	 * become non-busy without any further actions, therefore emit any
	 * necessary flushes here.
3592
	 */
3593
	ret = i915_gem_object_flush_active(obj);
3594

3595
	args->busy = obj->active;
3596 3597 3598 3599
	if (obj->ring) {
		BUILD_BUG_ON(I915_NUM_RINGS > 16);
		args->busy |= intel_ring_flag(obj->ring) << 16;
	}
3600

3601
	drm_gem_object_unreference(&obj->base);
3602
unlock:
3603
	mutex_unlock(&dev->struct_mutex);
3604
	return ret;
3605 3606 3607 3608 3609 3610
}

int
i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv)
{
3611
	return i915_gem_ring_throttle(dev, file_priv);
3612 3613
}

3614 3615 3616 3617 3618
int
i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
		       struct drm_file *file_priv)
{
	struct drm_i915_gem_madvise *args = data;
3619
	struct drm_i915_gem_object *obj;
3620
	int ret;
3621 3622 3623 3624 3625 3626 3627 3628 3629

	switch (args->madv) {
	case I915_MADV_DONTNEED:
	case I915_MADV_WILLNEED:
	    break;
	default:
	    return -EINVAL;
	}

3630 3631 3632 3633
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;

3634
	obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3635
	if (&obj->base == NULL) {
3636 3637
		ret = -ENOENT;
		goto unlock;
3638 3639
	}

3640
	if (obj->pin_count) {
3641 3642
		ret = -EINVAL;
		goto out;
3643 3644
	}

3645 3646
	if (obj->madv != __I915_MADV_PURGED)
		obj->madv = args->madv;
3647

C
Chris Wilson 已提交
3648 3649
	/* if the object is no longer attached, discard its backing storage */
	if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3650 3651
		i915_gem_object_truncate(obj);

3652
	args->retained = obj->madv != __I915_MADV_PURGED;
C
Chris Wilson 已提交
3653

3654
out:
3655
	drm_gem_object_unreference(&obj->base);
3656
unlock:
3657
	mutex_unlock(&dev->struct_mutex);
3658
	return ret;
3659 3660
}

3661 3662
void i915_gem_object_init(struct drm_i915_gem_object *obj,
			  const struct drm_i915_gem_object_ops *ops)
3663 3664 3665 3666 3667 3668
{
	INIT_LIST_HEAD(&obj->mm_list);
	INIT_LIST_HEAD(&obj->gtt_list);
	INIT_LIST_HEAD(&obj->ring_list);
	INIT_LIST_HEAD(&obj->exec_list);

3669 3670
	obj->ops = ops;

3671 3672 3673 3674 3675 3676 3677 3678
	obj->fence_reg = I915_FENCE_REG_NONE;
	obj->madv = I915_MADV_WILLNEED;
	/* Avoid an unnecessary call to unbind on the first bind. */
	obj->map_and_fenceable = true;

	i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
}

3679 3680 3681 3682 3683
static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
	.get_pages = i915_gem_object_get_pages_gtt,
	.put_pages = i915_gem_object_put_pages_gtt,
};

3684 3685
struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
						  size_t size)
3686
{
3687
	struct drm_i915_gem_object *obj;
3688
	struct address_space *mapping;
3689
	u32 mask;
3690

3691 3692 3693
	obj = kzalloc(sizeof(*obj), GFP_KERNEL);
	if (obj == NULL)
		return NULL;
3694

3695 3696 3697 3698
	if (drm_gem_object_init(dev, &obj->base, size) != 0) {
		kfree(obj);
		return NULL;
	}
3699

3700 3701 3702 3703 3704 3705 3706
	mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
	if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
		/* 965gm cannot relocate objects above 4GiB. */
		mask &= ~__GFP_HIGHMEM;
		mask |= __GFP_DMA32;
	}

3707
	mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3708
	mapping_set_gfp_mask(mapping, mask);
3709

3710
	i915_gem_object_init(obj, &i915_gem_object_ops);
3711

3712 3713
	obj->base.write_domain = I915_GEM_DOMAIN_CPU;
	obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3714

3715 3716
	if (HAS_LLC(dev)) {
		/* On some devices, we can have the GPU use the LLC (the CPU
3717 3718 3719 3720 3721 3722 3723 3724 3725 3726 3727 3728 3729 3730 3731
		 * cache) for about a 10% performance improvement
		 * compared to uncached.  Graphics requests other than
		 * display scanout are coherent with the CPU in
		 * accessing this cache.  This means in this mode we
		 * don't need to clflush on the CPU side, and on the
		 * GPU side we only need to flush internal caches to
		 * get data visible to the CPU.
		 *
		 * However, we maintain the display planes as UC, and so
		 * need to rebind when first used as such.
		 */
		obj->cache_level = I915_CACHE_LLC;
	} else
		obj->cache_level = I915_CACHE_NONE;

3732
	return obj;
3733 3734 3735 3736 3737
}

int i915_gem_init_object(struct drm_gem_object *obj)
{
	BUG();
3738

3739 3740 3741
	return 0;
}

3742
void i915_gem_free_object(struct drm_gem_object *gem_obj)
3743
{
3744
	struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3745
	struct drm_device *dev = obj->base.dev;
3746
	drm_i915_private_t *dev_priv = dev->dev_private;
3747

3748 3749
	trace_i915_gem_object_destroy(obj);

3750 3751 3752 3753 3754 3755 3756 3757 3758 3759 3760 3761 3762 3763 3764
	if (obj->phys_obj)
		i915_gem_detach_phys_object(dev, obj);

	obj->pin_count = 0;
	if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
		bool was_interruptible;

		was_interruptible = dev_priv->mm.interruptible;
		dev_priv->mm.interruptible = false;

		WARN_ON(i915_gem_object_unbind(obj));

		dev_priv->mm.interruptible = was_interruptible;
	}

3765
	obj->pages_pin_count = 0;
3766
	i915_gem_object_put_pages(obj);
3767
	i915_gem_object_free_mmap_offset(obj);
3768

3769 3770
	BUG_ON(obj->pages);

3771 3772 3773
	if (obj->base.import_attach)
		drm_prime_gem_destroy(&obj->base, NULL);

3774 3775
	drm_gem_object_release(&obj->base);
	i915_gem_info_remove_obj(dev_priv, obj->base.size);
3776

3777 3778
	kfree(obj->bit_17);
	kfree(obj);
3779 3780
}

3781 3782 3783 3784 3785
int
i915_gem_idle(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	int ret;
3786

3787
	mutex_lock(&dev->struct_mutex);
C
Chris Wilson 已提交
3788

3789
	if (dev_priv->mm.suspended) {
3790 3791
		mutex_unlock(&dev->struct_mutex);
		return 0;
3792 3793
	}

3794
	ret = i915_gpu_idle(dev);
3795 3796
	if (ret) {
		mutex_unlock(&dev->struct_mutex);
3797
		return ret;
3798
	}
3799
	i915_gem_retire_requests(dev);
3800

3801
	/* Under UMS, be paranoid and evict. */
3802
	if (!drm_core_check_feature(dev, DRIVER_MODESET))
C
Chris Wilson 已提交
3803
		i915_gem_evict_everything(dev);
3804

3805 3806
	i915_gem_reset_fences(dev);

3807 3808 3809 3810 3811
	/* Hack!  Don't let anybody do execbuf while we don't control the chip.
	 * We need to replace this with a semaphore, or something.
	 * And not confound mm.suspended!
	 */
	dev_priv->mm.suspended = 1;
3812
	del_timer_sync(&dev_priv->hangcheck_timer);
3813 3814

	i915_kernel_lost_context(dev);
3815
	i915_gem_cleanup_ringbuffer(dev);
3816

3817 3818
	mutex_unlock(&dev->struct_mutex);

3819 3820 3821
	/* Cancel the retire work handler, which should be idle now. */
	cancel_delayed_work_sync(&dev_priv->mm.retire_work);

3822 3823 3824
	return 0;
}

B
Ben Widawsky 已提交
3825 3826 3827 3828 3829 3830 3831 3832 3833
void i915_gem_l3_remap(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	u32 misccpctl;
	int i;

	if (!IS_IVYBRIDGE(dev))
		return;

3834
	if (!dev_priv->l3_parity.remap_info)
B
Ben Widawsky 已提交
3835 3836 3837 3838 3839 3840 3841 3842
		return;

	misccpctl = I915_READ(GEN7_MISCCPCTL);
	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
	POSTING_READ(GEN7_MISCCPCTL);

	for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
		u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
3843
		if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
B
Ben Widawsky 已提交
3844 3845
			DRM_DEBUG("0x%x was already programmed to %x\n",
				  GEN7_L3LOG_BASE + i, remap);
3846
		if (remap && !dev_priv->l3_parity.remap_info[i/4])
B
Ben Widawsky 已提交
3847
			DRM_DEBUG_DRIVER("Clearing remapped register\n");
3848
		I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
B
Ben Widawsky 已提交
3849 3850 3851 3852 3853 3854 3855 3856
	}

	/* Make sure all the writes land before disabling dop clock gating */
	POSTING_READ(GEN7_L3LOG_BASE);

	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
}

3857 3858 3859 3860
void i915_gem_init_swizzling(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;

3861
	if (INTEL_INFO(dev)->gen < 5 ||
3862 3863 3864 3865 3866 3867
	    dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
		return;

	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
				 DISP_TILE_SURFACE_SWIZZLING);

3868 3869 3870
	if (IS_GEN5(dev))
		return;

3871 3872
	I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
	if (IS_GEN6(dev))
3873
		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
3874
	else
3875
		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
3876
}
D
Daniel Vetter 已提交
3877

3878 3879 3880 3881 3882 3883 3884 3885 3886 3887 3888 3889 3890 3891 3892 3893
static bool
intel_enable_blt(struct drm_device *dev)
{
	if (!HAS_BLT(dev))
		return false;

	/* The blitter was dysfunctional on early prototypes */
	if (IS_GEN6(dev) && dev->pdev->revision < 8) {
		DRM_INFO("BLT not supported on this pre-production hardware;"
			 " graphics performance will be degraded.\n");
		return false;
	}

	return true;
}

3894
int
3895
i915_gem_init_hw(struct drm_device *dev)
3896 3897 3898
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	int ret;
3899

3900
	if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
D
Daniel Vetter 已提交
3901 3902
		return -EIO;

R
Rodrigo Vivi 已提交
3903 3904 3905
	if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
		I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);

B
Ben Widawsky 已提交
3906 3907
	i915_gem_l3_remap(dev);

3908 3909
	i915_gem_init_swizzling(dev);

3910
	ret = intel_init_render_ring_buffer(dev);
3911
	if (ret)
3912
		return ret;
3913 3914

	if (HAS_BSD(dev)) {
3915
		ret = intel_init_bsd_ring_buffer(dev);
3916 3917
		if (ret)
			goto cleanup_render_ring;
3918
	}
3919

3920
	if (intel_enable_blt(dev)) {
3921 3922 3923 3924 3925
		ret = intel_init_blt_ring_buffer(dev);
		if (ret)
			goto cleanup_bsd_ring;
	}

3926 3927
	dev_priv->next_seqno = 1;

3928 3929 3930 3931 3932
	/*
	 * XXX: There was some w/a described somewhere suggesting loading
	 * contexts before PPGTT.
	 */
	i915_gem_context_init(dev);
D
Daniel Vetter 已提交
3933 3934
	i915_gem_init_ppgtt(dev);

3935 3936
	return 0;

3937
cleanup_bsd_ring:
3938
	intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
3939
cleanup_render_ring:
3940
	intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
3941 3942 3943
	return ret;
}

3944 3945 3946 3947 3948 3949 3950 3951 3952 3953 3954 3955 3956 3957 3958 3959 3960 3961 3962 3963 3964 3965 3966 3967 3968 3969 3970 3971 3972 3973 3974 3975 3976 3977 3978 3979 3980 3981 3982 3983 3984 3985 3986 3987 3988 3989 3990 3991 3992 3993 3994 3995 3996 3997 3998 3999 4000 4001 4002
static bool
intel_enable_ppgtt(struct drm_device *dev)
{
	if (i915_enable_ppgtt >= 0)
		return i915_enable_ppgtt;

#ifdef CONFIG_INTEL_IOMMU
	/* Disable ppgtt on SNB if VT-d is on. */
	if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
		return false;
#endif

	return true;
}

int i915_gem_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long gtt_size, mappable_size;
	int ret;

	gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
	mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;

	mutex_lock(&dev->struct_mutex);
	if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
		/* PPGTT pdes are stolen from global gtt ptes, so shrink the
		 * aperture accordingly when using aliasing ppgtt. */
		gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;

		i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size);

		ret = i915_gem_init_aliasing_ppgtt(dev);
		if (ret) {
			mutex_unlock(&dev->struct_mutex);
			return ret;
		}
	} else {
		/* Let GEM Manage all of the aperture.
		 *
		 * However, leave one page at the end still bound to the scratch
		 * page.  There are a number of places where the hardware
		 * apparently prefetches past the end of the object, and we've
		 * seen multiple hangs with the GPU head pointer stuck in a
		 * batchbuffer bound at the last page of the aperture.  One page
		 * should be enough to keep any prefetching inside of the
		 * aperture.
		 */
		i915_gem_init_global_gtt(dev, 0, mappable_size,
					 gtt_size);
	}

	ret = i915_gem_init_hw(dev);
	mutex_unlock(&dev->struct_mutex);
	if (ret) {
		i915_gem_cleanup_aliasing_ppgtt(dev);
		return ret;
	}

4003 4004 4005
	/* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
	if (!drm_core_check_feature(dev, DRIVER_MODESET))
		dev_priv->dri1.allow_batchbuffer = 1;
4006 4007 4008
	return 0;
}

4009 4010 4011 4012
void
i915_gem_cleanup_ringbuffer(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
4013
	struct intel_ring_buffer *ring;
4014
	int i;
4015

4016 4017
	for_each_ring(ring, dev_priv, i)
		intel_cleanup_ring_buffer(ring);
4018 4019
}

4020 4021 4022 4023 4024
int
i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
		       struct drm_file *file_priv)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
4025
	int ret;
4026

J
Jesse Barnes 已提交
4027 4028 4029
	if (drm_core_check_feature(dev, DRIVER_MODESET))
		return 0;

4030
	if (atomic_read(&dev_priv->mm.wedged)) {
4031
		DRM_ERROR("Reenabling wedged hardware, good luck\n");
4032
		atomic_set(&dev_priv->mm.wedged, 0);
4033 4034 4035
	}

	mutex_lock(&dev->struct_mutex);
4036 4037
	dev_priv->mm.suspended = 0;

4038
	ret = i915_gem_init_hw(dev);
4039 4040
	if (ret != 0) {
		mutex_unlock(&dev->struct_mutex);
4041
		return ret;
4042
	}
4043

4044
	BUG_ON(!list_empty(&dev_priv->mm.active_list));
4045
	mutex_unlock(&dev->struct_mutex);
4046

4047 4048 4049
	ret = drm_irq_install(dev);
	if (ret)
		goto cleanup_ringbuffer;
4050

4051
	return 0;
4052 4053 4054 4055 4056 4057 4058 4059

cleanup_ringbuffer:
	mutex_lock(&dev->struct_mutex);
	i915_gem_cleanup_ringbuffer(dev);
	dev_priv->mm.suspended = 1;
	mutex_unlock(&dev->struct_mutex);

	return ret;
4060 4061 4062 4063 4064 4065
}

int
i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
		       struct drm_file *file_priv)
{
J
Jesse Barnes 已提交
4066 4067 4068
	if (drm_core_check_feature(dev, DRIVER_MODESET))
		return 0;

4069
	drm_irq_uninstall(dev);
4070
	return i915_gem_idle(dev);
4071 4072 4073 4074 4075 4076 4077
}

void
i915_gem_lastclose(struct drm_device *dev)
{
	int ret;

4078 4079 4080
	if (drm_core_check_feature(dev, DRIVER_MODESET))
		return;

4081 4082 4083
	ret = i915_gem_idle(dev);
	if (ret)
		DRM_ERROR("failed to idle hardware: %d\n", ret);
4084 4085
}

4086 4087 4088 4089 4090 4091 4092
static void
init_ring_lists(struct intel_ring_buffer *ring)
{
	INIT_LIST_HEAD(&ring->active_list);
	INIT_LIST_HEAD(&ring->request_list);
}

4093 4094 4095
void
i915_gem_load(struct drm_device *dev)
{
4096
	int i;
4097 4098
	drm_i915_private_t *dev_priv = dev->dev_private;

4099
	INIT_LIST_HEAD(&dev_priv->mm.active_list);
4100
	INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
C
Chris Wilson 已提交
4101 4102
	INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
	INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4103
	INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4104 4105
	for (i = 0; i < I915_NUM_RINGS; i++)
		init_ring_lists(&dev_priv->ring[i]);
4106
	for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4107
		INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4108 4109
	INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
			  i915_gem_retire_work_handler);
4110
	init_completion(&dev_priv->error_completion);
4111

4112 4113
	/* On GEN3 we really need to make sure the ARB C3 LP bit is set */
	if (IS_GEN3(dev)) {
4114 4115
		I915_WRITE(MI_ARB_STATE,
			   _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4116 4117
	}

4118 4119
	dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;

4120
	/* Old X drivers will take 0-2 for front, back, depth buffers */
4121 4122
	if (!drm_core_check_feature(dev, DRIVER_MODESET))
		dev_priv->fence_reg_start = 3;
4123

4124
	if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4125 4126 4127 4128
		dev_priv->num_fence_regs = 16;
	else
		dev_priv->num_fence_regs = 8;

4129
	/* Initialize fence registers to zero */
4130
	i915_gem_reset_fences(dev);
4131

4132
	i915_gem_detect_bit_6_swizzle(dev);
4133
	init_waitqueue_head(&dev_priv->pending_flip_queue);
4134

4135 4136
	dev_priv->mm.interruptible = true;

4137 4138 4139
	dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
	dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
	register_shrinker(&dev_priv->mm.inactive_shrinker);
4140
}
4141 4142 4143 4144 4145

/*
 * Create a physically contiguous memory object for this object
 * e.g. for cursor + overlay regs
 */
4146 4147
static int i915_gem_init_phys_object(struct drm_device *dev,
				     int id, int size, int align)
4148 4149 4150 4151 4152 4153 4154 4155
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_i915_gem_phys_object *phys_obj;
	int ret;

	if (dev_priv->mm.phys_objs[id - 1] || !size)
		return 0;

4156
	phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4157 4158 4159 4160 4161
	if (!phys_obj)
		return -ENOMEM;

	phys_obj->id = id;

4162
	phys_obj->handle = drm_pci_alloc(dev, size, align);
4163 4164 4165 4166 4167 4168 4169 4170 4171 4172 4173 4174
	if (!phys_obj->handle) {
		ret = -ENOMEM;
		goto kfree_obj;
	}
#ifdef CONFIG_X86
	set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
#endif

	dev_priv->mm.phys_objs[id - 1] = phys_obj;

	return 0;
kfree_obj:
4175
	kfree(phys_obj);
4176 4177 4178
	return ret;
}

4179
static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4180 4181 4182 4183 4184 4185 4186 4187 4188 4189 4190 4191 4192 4193 4194 4195 4196 4197 4198 4199 4200 4201 4202 4203
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_i915_gem_phys_object *phys_obj;

	if (!dev_priv->mm.phys_objs[id - 1])
		return;

	phys_obj = dev_priv->mm.phys_objs[id - 1];
	if (phys_obj->cur_obj) {
		i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
	}

#ifdef CONFIG_X86
	set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
#endif
	drm_pci_free(dev, phys_obj->handle);
	kfree(phys_obj);
	dev_priv->mm.phys_objs[id - 1] = NULL;
}

void i915_gem_free_all_phys_object(struct drm_device *dev)
{
	int i;

4204
	for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4205 4206 4207 4208
		i915_gem_free_phys_object(dev, i);
}

void i915_gem_detach_phys_object(struct drm_device *dev,
4209
				 struct drm_i915_gem_object *obj)
4210
{
4211
	struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4212
	char *vaddr;
4213 4214 4215
	int i;
	int page_count;

4216
	if (!obj->phys_obj)
4217
		return;
4218
	vaddr = obj->phys_obj->handle->vaddr;
4219

4220
	page_count = obj->base.size / PAGE_SIZE;
4221
	for (i = 0; i < page_count; i++) {
4222
		struct page *page = shmem_read_mapping_page(mapping, i);
4223 4224 4225 4226 4227 4228 4229 4230 4231 4232 4233
		if (!IS_ERR(page)) {
			char *dst = kmap_atomic(page);
			memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
			kunmap_atomic(dst);

			drm_clflush_pages(&page, 1);

			set_page_dirty(page);
			mark_page_accessed(page);
			page_cache_release(page);
		}
4234
	}
4235
	i915_gem_chipset_flush(dev);
4236

4237 4238
	obj->phys_obj->cur_obj = NULL;
	obj->phys_obj = NULL;
4239 4240 4241 4242
}

int
i915_gem_attach_phys_object(struct drm_device *dev,
4243
			    struct drm_i915_gem_object *obj,
4244 4245
			    int id,
			    int align)
4246
{
4247
	struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4248 4249 4250 4251 4252 4253 4254 4255
	drm_i915_private_t *dev_priv = dev->dev_private;
	int ret = 0;
	int page_count;
	int i;

	if (id > I915_MAX_PHYS_OBJECT)
		return -EINVAL;

4256 4257
	if (obj->phys_obj) {
		if (obj->phys_obj->id == id)
4258 4259 4260 4261 4262 4263 4264
			return 0;
		i915_gem_detach_phys_object(dev, obj);
	}

	/* create a new object */
	if (!dev_priv->mm.phys_objs[id - 1]) {
		ret = i915_gem_init_phys_object(dev, id,
4265
						obj->base.size, align);
4266
		if (ret) {
4267 4268
			DRM_ERROR("failed to init phys object %d size: %zu\n",
				  id, obj->base.size);
4269
			return ret;
4270 4271 4272 4273
		}
	}

	/* bind to the object */
4274 4275
	obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
	obj->phys_obj->cur_obj = obj;
4276

4277
	page_count = obj->base.size / PAGE_SIZE;
4278 4279

	for (i = 0; i < page_count; i++) {
4280 4281 4282
		struct page *page;
		char *dst, *src;

4283
		page = shmem_read_mapping_page(mapping, i);
4284 4285
		if (IS_ERR(page))
			return PTR_ERR(page);
4286

4287
		src = kmap_atomic(page);
4288
		dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4289
		memcpy(dst, src, PAGE_SIZE);
P
Peter Zijlstra 已提交
4290
		kunmap_atomic(src);
4291

4292 4293 4294
		mark_page_accessed(page);
		page_cache_release(page);
	}
4295

4296 4297 4298 4299
	return 0;
}

static int
4300 4301
i915_gem_phys_pwrite(struct drm_device *dev,
		     struct drm_i915_gem_object *obj,
4302 4303 4304
		     struct drm_i915_gem_pwrite *args,
		     struct drm_file *file_priv)
{
4305
	void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4306
	char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
4307

4308 4309 4310 4311 4312 4313 4314 4315 4316 4317 4318 4319 4320
	if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
		unsigned long unwritten;

		/* The physical object once assigned is fixed for the lifetime
		 * of the obj, so we can safely drop the lock and continue
		 * to access vaddr.
		 */
		mutex_unlock(&dev->struct_mutex);
		unwritten = copy_from_user(vaddr, user_data, args->size);
		mutex_lock(&dev->struct_mutex);
		if (unwritten)
			return -EFAULT;
	}
4321

4322
	i915_gem_chipset_flush(dev);
4323 4324
	return 0;
}
4325

4326
void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4327
{
4328
	struct drm_i915_file_private *file_priv = file->driver_priv;
4329 4330 4331 4332 4333

	/* Clean up our request list when the client is going away, so that
	 * later retire_requests won't dereference our soon-to-be-gone
	 * file_priv.
	 */
4334
	spin_lock(&file_priv->mm.lock);
4335 4336 4337 4338 4339 4340 4341 4342 4343
	while (!list_empty(&file_priv->mm.request_list)) {
		struct drm_i915_gem_request *request;

		request = list_first_entry(&file_priv->mm.request_list,
					   struct drm_i915_gem_request,
					   client_list);
		list_del(&request->client_list);
		request->file_priv = NULL;
	}
4344
	spin_unlock(&file_priv->mm.lock);
4345
}
4346 4347

static int
4348
i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4349
{
4350 4351 4352 4353 4354
	struct drm_i915_private *dev_priv =
		container_of(shrinker,
			     struct drm_i915_private,
			     mm.inactive_shrinker);
	struct drm_device *dev = dev_priv->dev;
C
Chris Wilson 已提交
4355
	struct drm_i915_gem_object *obj;
4356
	int nr_to_scan = sc->nr_to_scan;
4357 4358 4359
	int cnt;

	if (!mutex_trylock(&dev->struct_mutex))
4360
		return 0;
4361

C
Chris Wilson 已提交
4362 4363 4364 4365
	if (nr_to_scan) {
		nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan);
		if (nr_to_scan > 0)
			i915_gem_shrink_all(dev_priv);
4366 4367
	}

4368
	cnt = 0;
C
Chris Wilson 已提交
4369
	list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list)
4370 4371
		if (obj->pages_pin_count == 0)
			cnt += obj->base.size >> PAGE_SHIFT;
C
Chris Wilson 已提交
4372
	list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
4373
		if (obj->pin_count == 0 && obj->pages_pin_count == 0)
C
Chris Wilson 已提交
4374
			cnt += obj->base.size >> PAGE_SHIFT;
4375 4376

	mutex_unlock(&dev->struct_mutex);
C
Chris Wilson 已提交
4377
	return cnt;
4378
}