chip.c 133.1 KB
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/*
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 * Marvell 88e6xxx Ethernet switch single-chip support
 *
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 * Copyright (c) 2008 Marvell Semiconductor
 *
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 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
 *
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Vivien Didelot 已提交
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 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
 *	Vivien Didelot <vivien.didelot@savoirfairelinux.com>
 *
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 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

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#include <linux/delay.h>
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#include <linux/etherdevice.h>
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#include <linux/ethtool.h>
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#include <linux/if_bridge.h>
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#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
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#include <linux/jiffies.h>
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#include <linux/list.h>
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#include <linux/mdio.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/of_mdio.h>
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#include <linux/platform_data/mv88e6xxx.h>
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#include <linux/netdevice.h>
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#include <linux/gpio/consumer.h>
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#include <linux/phy.h>
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#include <linux/phylink.h>
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#include <net/dsa.h>
37

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#include "chip.h"
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#include "global1.h"
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#include "global2.h"
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#include "hwtstamp.h"
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#include "phy.h"
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#include "port.h"
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#include "ptp.h"
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#include "serdes.h"
46

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static void assert_reg_lock(struct mv88e6xxx_chip *chip)
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{
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	if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
		dev_err(chip->dev, "Switch registers lock not held!\n");
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		dump_stack();
	}
}

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/* The switch ADDR[4:1] configuration pins define the chip SMI device address
 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
 *
 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
 * is the only device connected to the SMI master. In this mode it responds to
 * all 32 possible SMI addresses, and thus maps directly the internal devices.
 *
 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
 * multiple devices to share the SMI interface. In this mode it responds to only
 * 2 registers, used to indirectly access the internal SMI devices.
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 */
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static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
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			      int addr, int reg, u16 *val)
{
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	if (!chip->smi_ops)
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		return -EOPNOTSUPP;

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	return chip->smi_ops->read(chip, addr, reg, val);
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}

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static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
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			       int addr, int reg, u16 val)
{
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	if (!chip->smi_ops)
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		return -EOPNOTSUPP;

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	return chip->smi_ops->write(chip, addr, reg, val);
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}

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static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
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					  int addr, int reg, u16 *val)
{
	int ret;

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	ret = mdiobus_read_nested(chip->bus, addr, reg);
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	if (ret < 0)
		return ret;

	*val = ret & 0xffff;

	return 0;
}

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static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
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					   int addr, int reg, u16 val)
{
	int ret;

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	ret = mdiobus_write_nested(chip->bus, addr, reg, val);
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	if (ret < 0)
		return ret;

	return 0;
}

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static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
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	.read = mv88e6xxx_smi_single_chip_read,
	.write = mv88e6xxx_smi_single_chip_write,
};

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static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
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{
	int ret;
	int i;

	for (i = 0; i < 16; i++) {
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		ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
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		if (ret < 0)
			return ret;

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		if ((ret & SMI_CMD_BUSY) == 0)
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			return 0;
	}

	return -ETIMEDOUT;
}

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static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
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					 int addr, int reg, u16 *val)
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{
	int ret;

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	/* Wait for the bus to become free. */
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	ret = mv88e6xxx_smi_multi_chip_wait(chip);
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	if (ret < 0)
		return ret;

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	/* Transmit the read command. */
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	ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
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				   SMI_CMD_OP_22_READ | (addr << 5) | reg);
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	if (ret < 0)
		return ret;

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	/* Wait for the read command to complete. */
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	ret = mv88e6xxx_smi_multi_chip_wait(chip);
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	if (ret < 0)
		return ret;

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	/* Read the data. */
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	ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
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	if (ret < 0)
		return ret;

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	*val = ret & 0xffff;
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	return 0;
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}

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static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
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					  int addr, int reg, u16 val)
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{
	int ret;

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	/* Wait for the bus to become free. */
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	ret = mv88e6xxx_smi_multi_chip_wait(chip);
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	if (ret < 0)
		return ret;

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	/* Transmit the data to write. */
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	ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
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	if (ret < 0)
		return ret;

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	/* Transmit the write command. */
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	ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
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				   SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
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	if (ret < 0)
		return ret;

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	/* Wait for the write command to complete. */
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	ret = mv88e6xxx_smi_multi_chip_wait(chip);
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	if (ret < 0)
		return ret;

	return 0;
}

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static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
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	.read = mv88e6xxx_smi_multi_chip_read,
	.write = mv88e6xxx_smi_multi_chip_write,
};

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int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
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{
	int err;

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	assert_reg_lock(chip);
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	err = mv88e6xxx_smi_read(chip, addr, reg, val);
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	if (err)
		return err;

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	dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
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		addr, reg, *val);

	return 0;
}

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int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
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{
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	int err;

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	assert_reg_lock(chip);
219

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	err = mv88e6xxx_smi_write(chip, addr, reg, val);
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	if (err)
		return err;

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	dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
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		addr, reg, val);

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	return 0;
}

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struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
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{
	struct mv88e6xxx_mdio_bus *mdio_bus;

	mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
				    list);
	if (!mdio_bus)
		return NULL;

	return mdio_bus->bus;
}

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static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
{
	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int n = d->hwirq;

	chip->g1_irq.masked |= (1 << n);
}

static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
{
	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int n = d->hwirq;

	chip->g1_irq.masked &= ~(1 << n);
}

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static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
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{
	unsigned int nhandled = 0;
	unsigned int sub_irq;
	unsigned int n;
	u16 reg;
	int err;

	mutex_lock(&chip->reg_lock);
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	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
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	mutex_unlock(&chip->reg_lock);

	if (err)
		goto out;

	for (n = 0; n < chip->g1_irq.nirqs; ++n) {
		if (reg & (1 << n)) {
			sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
			handle_nested_irq(sub_irq);
			++nhandled;
		}
	}
out:
	return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
}

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static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
{
	struct mv88e6xxx_chip *chip = dev_id;

	return mv88e6xxx_g1_irq_thread_work(chip);
}

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static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
{
	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);

	mutex_lock(&chip->reg_lock);
}

static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
{
	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
	u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
	u16 reg;
	int err;

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	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
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	if (err)
		goto out;

	reg &= ~mask;
	reg |= (~chip->g1_irq.masked & mask);

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	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
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	if (err)
		goto out;

out:
	mutex_unlock(&chip->reg_lock);
}

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static const struct irq_chip mv88e6xxx_g1_irq_chip = {
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	.name			= "mv88e6xxx-g1",
	.irq_mask		= mv88e6xxx_g1_irq_mask,
	.irq_unmask		= mv88e6xxx_g1_irq_unmask,
	.irq_bus_lock		= mv88e6xxx_g1_irq_bus_lock,
	.irq_bus_sync_unlock	= mv88e6xxx_g1_irq_bus_sync_unlock,
};

static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
				       unsigned int irq,
				       irq_hw_number_t hwirq)
{
	struct mv88e6xxx_chip *chip = d->host_data;

	irq_set_chip_data(irq, d->host_data);
	irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
	irq_set_noprobe(irq);

	return 0;
}

static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
	.map	= mv88e6xxx_g1_irq_domain_map,
	.xlate	= irq_domain_xlate_twocell,
};

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/* To be called with reg_lock held */
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static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
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{
	int irq, virq;
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	u16 mask;

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	mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
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	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
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	mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
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356
	for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
357
		virq = irq_find_mapping(chip->g1_irq.domain, irq);
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		irq_dispose_mapping(virq);
	}

361
	irq_domain_remove(chip->g1_irq.domain);
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}

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static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
{
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	/*
	 * free_irq must be called without reg_lock taken because the irq
	 * handler takes this lock, too.
	 */
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	free_irq(chip->irq, chip);
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	mutex_lock(&chip->reg_lock);
	mv88e6xxx_g1_irq_free_common(chip);
	mutex_unlock(&chip->reg_lock);
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}

static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
378
{
379 380
	int err, irq, virq;
	u16 reg, mask;
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	chip->g1_irq.nirqs = chip->info->g1_irqs;
	chip->g1_irq.domain = irq_domain_add_simple(
		NULL, chip->g1_irq.nirqs, 0,
		&mv88e6xxx_g1_irq_domain_ops, chip);
	if (!chip->g1_irq.domain)
		return -ENOMEM;

	for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
		irq_create_mapping(chip->g1_irq.domain, irq);

	chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
	chip->g1_irq.masked = ~0;

395
	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
396
	if (err)
397
		goto out_mapping;
398

399
	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
400

401
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
402
	if (err)
403
		goto out_disable;
404 405

	/* Reading the interrupt status clears (most of) them */
406
	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
407
	if (err)
408
		goto out_disable;
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	return 0;

412
out_disable:
413
	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
414
	mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
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out_mapping:
	for (irq = 0; irq < 16; irq++) {
		virq = irq_find_mapping(chip->g1_irq.domain, irq);
		irq_dispose_mapping(virq);
	}

	irq_domain_remove(chip->g1_irq.domain);
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	return err;
}

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static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
{
	int err;

	err = mv88e6xxx_g1_irq_setup_common(chip);
	if (err)
		return err;

	err = request_threaded_irq(chip->irq, NULL,
				   mv88e6xxx_g1_irq_thread_fn,
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				   IRQF_ONESHOT,
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				   dev_name(chip->dev), chip);
	if (err)
		mv88e6xxx_g1_irq_free_common(chip);

	return err;
}

static void mv88e6xxx_irq_poll(struct kthread_work *work)
{
	struct mv88e6xxx_chip *chip = container_of(work,
						   struct mv88e6xxx_chip,
						   irq_poll_work.work);
	mv88e6xxx_g1_irq_thread_work(chip);

	kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
				   msecs_to_jiffies(100));
}

static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
{
	int err;

	err = mv88e6xxx_g1_irq_setup_common(chip);
	if (err)
		return err;

	kthread_init_delayed_work(&chip->irq_poll_work,
				  mv88e6xxx_irq_poll);

	chip->kworker = kthread_create_worker(0, dev_name(chip->dev));
	if (IS_ERR(chip->kworker))
		return PTR_ERR(chip->kworker);

	kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
				   msecs_to_jiffies(100));

	return 0;
}

static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
{
	kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
	kthread_destroy_worker(chip->kworker);
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	mutex_lock(&chip->reg_lock);
	mv88e6xxx_g1_irq_free_common(chip);
	mutex_unlock(&chip->reg_lock);
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}

487
int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
488
{
489
	int i;
490

491
	for (i = 0; i < 16; i++) {
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		u16 val;
		int err;

		err = mv88e6xxx_read(chip, addr, reg, &val);
		if (err)
			return err;

		if (!(val & mask))
			return 0;

		usleep_range(1000, 2000);
	}

505
	dev_err(chip->dev, "Timeout while waiting for switch\n");
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	return -ETIMEDOUT;
}

509
/* Indirect write to single pointer-data register with an Update bit */
510
int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
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{
	u16 val;
513
	int err;
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	/* Wait until the previous operation is completed */
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	err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
	if (err)
		return err;
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	/* Set the Update bit to trigger a write operation */
	val = BIT(15) | update;

	return mv88e6xxx_write(chip, addr, reg, val);
}

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static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
527
				    int link, int speed, int duplex, int pause,
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				    phy_interface_t mode)
{
	int err;

	if (!chip->info->ops->port_set_link)
		return 0;

	/* Port's MAC control must not be changed unless the link is down */
	err = chip->info->ops->port_set_link(chip, port, 0);
	if (err)
		return err;

	if (chip->info->ops->port_set_speed) {
		err = chip->info->ops->port_set_speed(chip, port, speed);
		if (err && err != -EOPNOTSUPP)
			goto restore_link;
	}

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	if (chip->info->ops->port_set_pause) {
		err = chip->info->ops->port_set_pause(chip, port, pause);
		if (err)
			goto restore_link;
	}

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	if (chip->info->ops->port_set_duplex) {
		err = chip->info->ops->port_set_duplex(chip, port, duplex);
		if (err && err != -EOPNOTSUPP)
			goto restore_link;
	}

	if (chip->info->ops->port_set_rgmii_delay) {
		err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
		if (err && err != -EOPNOTSUPP)
			goto restore_link;
	}

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	if (chip->info->ops->port_set_cmode) {
		err = chip->info->ops->port_set_cmode(chip, port, mode);
		if (err && err != -EOPNOTSUPP)
			goto restore_link;
	}

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	err = 0;
restore_link:
	if (chip->info->ops->port_set_link(chip, port, link))
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		dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
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	return err;
}

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/* We expect the switch to perform auto negotiation if there is a real
 * phy. However, in the case of a fixed link phy, we force the port
 * settings from the fixed link settings.
 */
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static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
				  struct phy_device *phydev)
584
{
V
Vivien Didelot 已提交
585
	struct mv88e6xxx_chip *chip = ds->priv;
586
	int err;
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	if (!phy_is_pseudo_fixed_link(phydev))
		return;

591
	mutex_lock(&chip->reg_lock);
592
	err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
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				       phydev->duplex, phydev->pause,
				       phydev->interface);
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	mutex_unlock(&chip->reg_lock);
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	if (err && err != -EOPNOTSUPP)
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		dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
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}

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static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port,
				       unsigned long *mask,
				       struct phylink_link_state *state)
{
	if (!phy_interface_mode_is_8023z(state->interface)) {
		/* 10M and 100M are only supported in non-802.3z mode */
		phylink_set(mask, 10baseT_Half);
		phylink_set(mask, 10baseT_Full);
		phylink_set(mask, 100baseT_Half);
		phylink_set(mask, 100baseT_Full);
	}
}

static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port,
				       unsigned long *mask,
				       struct phylink_link_state *state)
{
	/* FIXME: if the port is in 1000Base-X mode, then it only supports
	 * 1000M FD speeds.  In this case, CMODE will indicate 5.
	 */
	phylink_set(mask, 1000baseT_Full);
	phylink_set(mask, 1000baseX_Full);

	mv88e6065_phylink_validate(chip, port, mask, state);
}

static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port,
				       unsigned long *mask,
				       struct phylink_link_state *state)
{
	/* No ethtool bits for 200Mbps */
	phylink_set(mask, 1000baseT_Full);
	phylink_set(mask, 1000baseX_Full);

	mv88e6065_phylink_validate(chip, port, mask, state);
}

static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port,
				       unsigned long *mask,
				       struct phylink_link_state *state)
{
	if (port >= 9)
		phylink_set(mask, 2500baseX_Full);

	/* No ethtool bits for 200Mbps */
	phylink_set(mask, 1000baseT_Full);
	phylink_set(mask, 1000baseX_Full);

	mv88e6065_phylink_validate(chip, port, mask, state);
}

static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
					unsigned long *mask,
					struct phylink_link_state *state)
{
	if (port >= 9) {
		phylink_set(mask, 10000baseT_Full);
		phylink_set(mask, 10000baseKR_Full);
	}

	mv88e6390_phylink_validate(chip, port, mask, state);
}

664 665 666 667
static void mv88e6xxx_validate(struct dsa_switch *ds, int port,
			       unsigned long *supported,
			       struct phylink_link_state *state)
{
668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686
	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
	struct mv88e6xxx_chip *chip = ds->priv;

	/* Allow all the expected bits */
	phylink_set(mask, Autoneg);
	phylink_set(mask, Pause);
	phylink_set_port_modes(mask);

	if (chip->info->ops->phylink_validate)
		chip->info->ops->phylink_validate(chip, port, mask, state);

	bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
	bitmap_and(state->advertising, state->advertising, mask,
		   __ETHTOOL_LINK_MODE_MASK_NBITS);

	/* We can only operate at 2500BaseX or 1000BaseX.  If requested
	 * to advertise both, only report advertising at 2500BaseX.
	 */
	phylink_helper_basex_speed(state);
687 688 689 690 691 692 693 694 695
}

static int mv88e6xxx_link_state(struct dsa_switch *ds, int port,
				struct phylink_link_state *state)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int err;

	mutex_lock(&chip->reg_lock);
696 697 698 699
	if (chip->info->ops->port_link_state)
		err = chip->info->ops->port_link_state(chip, port, state);
	else
		err = -EOPNOTSUPP;
700 701 702 703 704 705 706 707 708 709
	mutex_unlock(&chip->reg_lock);

	return err;
}

static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
				 unsigned int mode,
				 const struct phylink_link_state *state)
{
	struct mv88e6xxx_chip *chip = ds->priv;
710
	int speed, duplex, link, pause, err;
711 712 713 714 715 716 717 718 719 720 721 722 723

	if (mode == MLO_AN_PHY)
		return;

	if (mode == MLO_AN_FIXED) {
		link = LINK_FORCED_UP;
		speed = state->speed;
		duplex = state->duplex;
	} else {
		speed = SPEED_UNFORCED;
		duplex = DUPLEX_UNFORCED;
		link = LINK_UNFORCED;
	}
724
	pause = !!phylink_test(state->advertising, Pause);
725 726

	mutex_lock(&chip->reg_lock);
727
	err = mv88e6xxx_port_setup_mac(chip, port, link, speed, duplex, pause,
728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763
				       state->interface);
	mutex_unlock(&chip->reg_lock);

	if (err && err != -EOPNOTSUPP)
		dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
}

static void mv88e6xxx_mac_link_force(struct dsa_switch *ds, int port, int link)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int err;

	mutex_lock(&chip->reg_lock);
	err = chip->info->ops->port_set_link(chip, port, link);
	mutex_unlock(&chip->reg_lock);

	if (err)
		dev_err(chip->dev, "p%d: failed to force MAC link\n", port);
}

static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
				    unsigned int mode,
				    phy_interface_t interface)
{
	if (mode == MLO_AN_FIXED)
		mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_DOWN);
}

static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
				  unsigned int mode, phy_interface_t interface,
				  struct phy_device *phydev)
{
	if (mode == MLO_AN_FIXED)
		mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_UP);
}

764
static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
765
{
766 767
	if (!chip->info->ops->stats_snapshot)
		return -EOPNOTSUPP;
768

769
	return chip->info->ops->stats_snapshot(chip, port);
770 771
}

772
static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831
	{ "in_good_octets",		8, 0x00, STATS_TYPE_BANK0, },
	{ "in_bad_octets",		4, 0x02, STATS_TYPE_BANK0, },
	{ "in_unicast",			4, 0x04, STATS_TYPE_BANK0, },
	{ "in_broadcasts",		4, 0x06, STATS_TYPE_BANK0, },
	{ "in_multicasts",		4, 0x07, STATS_TYPE_BANK0, },
	{ "in_pause",			4, 0x16, STATS_TYPE_BANK0, },
	{ "in_undersize",		4, 0x18, STATS_TYPE_BANK0, },
	{ "in_fragments",		4, 0x19, STATS_TYPE_BANK0, },
	{ "in_oversize",		4, 0x1a, STATS_TYPE_BANK0, },
	{ "in_jabber",			4, 0x1b, STATS_TYPE_BANK0, },
	{ "in_rx_error",		4, 0x1c, STATS_TYPE_BANK0, },
	{ "in_fcs_error",		4, 0x1d, STATS_TYPE_BANK0, },
	{ "out_octets",			8, 0x0e, STATS_TYPE_BANK0, },
	{ "out_unicast",		4, 0x10, STATS_TYPE_BANK0, },
	{ "out_broadcasts",		4, 0x13, STATS_TYPE_BANK0, },
	{ "out_multicasts",		4, 0x12, STATS_TYPE_BANK0, },
	{ "out_pause",			4, 0x15, STATS_TYPE_BANK0, },
	{ "excessive",			4, 0x11, STATS_TYPE_BANK0, },
	{ "collisions",			4, 0x1e, STATS_TYPE_BANK0, },
	{ "deferred",			4, 0x05, STATS_TYPE_BANK0, },
	{ "single",			4, 0x14, STATS_TYPE_BANK0, },
	{ "multiple",			4, 0x17, STATS_TYPE_BANK0, },
	{ "out_fcs_error",		4, 0x03, STATS_TYPE_BANK0, },
	{ "late",			4, 0x1f, STATS_TYPE_BANK0, },
	{ "hist_64bytes",		4, 0x08, STATS_TYPE_BANK0, },
	{ "hist_65_127bytes",		4, 0x09, STATS_TYPE_BANK0, },
	{ "hist_128_255bytes",		4, 0x0a, STATS_TYPE_BANK0, },
	{ "hist_256_511bytes",		4, 0x0b, STATS_TYPE_BANK0, },
	{ "hist_512_1023bytes",		4, 0x0c, STATS_TYPE_BANK0, },
	{ "hist_1024_max_bytes",	4, 0x0d, STATS_TYPE_BANK0, },
	{ "sw_in_discards",		4, 0x10, STATS_TYPE_PORT, },
	{ "sw_in_filtered",		2, 0x12, STATS_TYPE_PORT, },
	{ "sw_out_filtered",		2, 0x13, STATS_TYPE_PORT, },
	{ "in_discards",		4, 0x00, STATS_TYPE_BANK1, },
	{ "in_filtered",		4, 0x01, STATS_TYPE_BANK1, },
	{ "in_accepted",		4, 0x02, STATS_TYPE_BANK1, },
	{ "in_bad_accepted",		4, 0x03, STATS_TYPE_BANK1, },
	{ "in_good_avb_class_a",	4, 0x04, STATS_TYPE_BANK1, },
	{ "in_good_avb_class_b",	4, 0x05, STATS_TYPE_BANK1, },
	{ "in_bad_avb_class_a",		4, 0x06, STATS_TYPE_BANK1, },
	{ "in_bad_avb_class_b",		4, 0x07, STATS_TYPE_BANK1, },
	{ "tcam_counter_0",		4, 0x08, STATS_TYPE_BANK1, },
	{ "tcam_counter_1",		4, 0x09, STATS_TYPE_BANK1, },
	{ "tcam_counter_2",		4, 0x0a, STATS_TYPE_BANK1, },
	{ "tcam_counter_3",		4, 0x0b, STATS_TYPE_BANK1, },
	{ "in_da_unknown",		4, 0x0e, STATS_TYPE_BANK1, },
	{ "in_management",		4, 0x0f, STATS_TYPE_BANK1, },
	{ "out_queue_0",		4, 0x10, STATS_TYPE_BANK1, },
	{ "out_queue_1",		4, 0x11, STATS_TYPE_BANK1, },
	{ "out_queue_2",		4, 0x12, STATS_TYPE_BANK1, },
	{ "out_queue_3",		4, 0x13, STATS_TYPE_BANK1, },
	{ "out_queue_4",		4, 0x14, STATS_TYPE_BANK1, },
	{ "out_queue_5",		4, 0x15, STATS_TYPE_BANK1, },
	{ "out_queue_6",		4, 0x16, STATS_TYPE_BANK1, },
	{ "out_queue_7",		4, 0x17, STATS_TYPE_BANK1, },
	{ "out_cut_through",		4, 0x18, STATS_TYPE_BANK1, },
	{ "out_octets_a",		4, 0x1a, STATS_TYPE_BANK1, },
	{ "out_octets_b",		4, 0x1b, STATS_TYPE_BANK1, },
	{ "out_management",		4, 0x1f, STATS_TYPE_BANK1, },
832 833
};

834
static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
835
					    struct mv88e6xxx_hw_stat *s,
836 837
					    int port, u16 bank1_select,
					    u16 histogram)
838 839 840
{
	u32 low;
	u32 high = 0;
841
	u16 reg = 0;
842
	int err;
843 844
	u64 value;

845
	switch (s->type) {
846
	case STATS_TYPE_PORT:
847 848
		err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
		if (err)
849
			return U64_MAX;
850

851
		low = reg;
852
		if (s->size == 4) {
853 854
			err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
			if (err)
855
				return U64_MAX;
856
			high = reg;
857
		}
858
		break;
859
	case STATS_TYPE_BANK1:
860
		reg = bank1_select;
861 862
		/* fall through */
	case STATS_TYPE_BANK0:
863
		reg |= s->reg | histogram;
864
		mv88e6xxx_g1_stats_read(chip, reg, &low);
865
		if (s->size == 8)
866
			mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
867 868
		break;
	default:
869
		return U64_MAX;
870 871 872 873 874
	}
	value = (((u64)high) << 16) | low;
	return value;
}

875 876
static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
				       uint8_t *data, int types)
877
{
878 879
	struct mv88e6xxx_hw_stat *stat;
	int i, j;
880

881 882
	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
		stat = &mv88e6xxx_hw_stats[i];
883
		if (stat->type & types) {
884 885 886 887
			memcpy(data + j * ETH_GSTRING_LEN, stat->string,
			       ETH_GSTRING_LEN);
			j++;
		}
888
	}
889 890

	return j;
891 892
}

893 894
static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
				       uint8_t *data)
895
{
896 897
	return mv88e6xxx_stats_get_strings(chip, data,
					   STATS_TYPE_BANK0 | STATS_TYPE_PORT);
898 899
}

900 901
static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
				       uint8_t *data)
902
{
903 904
	return mv88e6xxx_stats_get_strings(chip, data,
					   STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
905 906
}

907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924
static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
	"atu_member_violation",
	"atu_miss_violation",
	"atu_full_violation",
	"vtu_member_violation",
	"vtu_miss_violation",
};

static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
{
	unsigned int i;

	for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
		strlcpy(data + i * ETH_GSTRING_LEN,
			mv88e6xxx_atu_vtu_stats_strings[i],
			ETH_GSTRING_LEN);
}

925
static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
926
				  u32 stringset, uint8_t *data)
927
{
V
Vivien Didelot 已提交
928
	struct mv88e6xxx_chip *chip = ds->priv;
929
	int count = 0;
930

931 932 933
	if (stringset != ETH_SS_STATS)
		return;

934 935
	mutex_lock(&chip->reg_lock);

936
	if (chip->info->ops->stats_get_strings)
937 938 939 940
		count = chip->info->ops->stats_get_strings(chip, data);

	if (chip->info->ops->serdes_get_strings) {
		data += count * ETH_GSTRING_LEN;
941
		count = chip->info->ops->serdes_get_strings(chip, port, data);
942
	}
943

944 945 946
	data += count * ETH_GSTRING_LEN;
	mv88e6xxx_atu_vtu_get_strings(data);

947
	mutex_unlock(&chip->reg_lock);
948 949 950 951 952
}

static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
					  int types)
{
953 954 955 956 957
	struct mv88e6xxx_hw_stat *stat;
	int i, j;

	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
		stat = &mv88e6xxx_hw_stats[i];
958
		if (stat->type & types)
959 960 961
			j++;
	}
	return j;
962 963
}

964 965 966 967 968 969 970 971 972 973 974 975
static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
{
	return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
					      STATS_TYPE_PORT);
}

static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
{
	return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
					      STATS_TYPE_BANK1);
}

976
static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
977 978
{
	struct mv88e6xxx_chip *chip = ds->priv;
979 980
	int serdes_count = 0;
	int count = 0;
981

982 983 984
	if (sset != ETH_SS_STATS)
		return 0;

985
	mutex_lock(&chip->reg_lock);
986
	if (chip->info->ops->stats_get_sset_count)
987 988 989 990 991 992 993
		count = chip->info->ops->stats_get_sset_count(chip);
	if (count < 0)
		goto out;

	if (chip->info->ops->serdes_get_sset_count)
		serdes_count = chip->info->ops->serdes_get_sset_count(chip,
								      port);
994
	if (serdes_count < 0) {
995
		count = serdes_count;
996 997 998 999 1000
		goto out;
	}
	count += serdes_count;
	count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);

1001
out:
1002
	mutex_unlock(&chip->reg_lock);
1003

1004
	return count;
1005 1006
}

1007 1008 1009
static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
				     uint64_t *data, int types,
				     u16 bank1_select, u16 histogram)
1010 1011 1012 1013 1014 1015 1016
{
	struct mv88e6xxx_hw_stat *stat;
	int i, j;

	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
		stat = &mv88e6xxx_hw_stats[i];
		if (stat->type & types) {
1017
			mutex_lock(&chip->reg_lock);
1018 1019 1020
			data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
							      bank1_select,
							      histogram);
1021 1022
			mutex_unlock(&chip->reg_lock);

1023 1024 1025
			j++;
		}
	}
1026
	return j;
1027 1028
}

1029 1030
static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
				     uint64_t *data)
1031 1032
{
	return mv88e6xxx_stats_get_stats(chip, port, data,
1033
					 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
1034
					 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1035 1036
}

1037 1038
static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
				     uint64_t *data)
1039 1040
{
	return mv88e6xxx_stats_get_stats(chip, port, data,
1041
					 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1042 1043
					 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
					 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1044 1045
}

1046 1047
static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
				     uint64_t *data)
1048 1049 1050
{
	return mv88e6xxx_stats_get_stats(chip, port, data,
					 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1051 1052
					 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
					 0);
1053 1054
}

1055 1056 1057 1058 1059 1060 1061 1062 1063 1064
static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
					uint64_t *data)
{
	*data++ = chip->ports[port].atu_member_violation;
	*data++ = chip->ports[port].atu_miss_violation;
	*data++ = chip->ports[port].atu_full_violation;
	*data++ = chip->ports[port].vtu_member_violation;
	*data++ = chip->ports[port].vtu_miss_violation;
}

1065 1066 1067
static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
				uint64_t *data)
{
1068 1069
	int count = 0;

1070
	if (chip->info->ops->stats_get_stats)
1071 1072
		count = chip->info->ops->stats_get_stats(chip, port, data);

1073
	mutex_lock(&chip->reg_lock);
1074 1075
	if (chip->info->ops->serdes_get_stats) {
		data += count;
1076
		count = chip->info->ops->serdes_get_stats(chip, port, data);
1077
	}
1078 1079 1080
	data += count;
	mv88e6xxx_atu_vtu_get_stats(chip, port, data);
	mutex_unlock(&chip->reg_lock);
1081 1082
}

1083 1084
static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
					uint64_t *data)
1085
{
V
Vivien Didelot 已提交
1086
	struct mv88e6xxx_chip *chip = ds->priv;
1087 1088
	int ret;

1089
	mutex_lock(&chip->reg_lock);
1090

1091
	ret = mv88e6xxx_stats_snapshot(chip, port);
1092 1093 1094
	mutex_unlock(&chip->reg_lock);

	if (ret < 0)
1095
		return;
1096 1097

	mv88e6xxx_get_stats(chip, port, data);
1098

1099 1100
}

1101
static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1102 1103 1104 1105
{
	return 32 * sizeof(u16);
}

1106 1107
static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
			       struct ethtool_regs *regs, void *_p)
1108
{
V
Vivien Didelot 已提交
1109
	struct mv88e6xxx_chip *chip = ds->priv;
1110 1111
	int err;
	u16 reg;
1112 1113 1114 1115 1116 1117 1118
	u16 *p = _p;
	int i;

	regs->version = 0;

	memset(p, 0xff, 32 * sizeof(u16));

1119
	mutex_lock(&chip->reg_lock);
1120

1121 1122
	for (i = 0; i < 32; i++) {

1123 1124 1125
		err = mv88e6xxx_port_read(chip, port, i, &reg);
		if (!err)
			p[i] = reg;
1126
	}
1127

1128
	mutex_unlock(&chip->reg_lock);
1129 1130
}

V
Vivien Didelot 已提交
1131 1132
static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
				 struct ethtool_eee *e)
1133
{
1134 1135
	/* Nothing to do on the port's MAC */
	return 0;
1136 1137
}

V
Vivien Didelot 已提交
1138 1139
static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
				 struct ethtool_eee *e)
1140
{
1141 1142
	/* Nothing to do on the port's MAC */
	return 0;
1143 1144
}

1145
static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1146
{
1147 1148 1149
	struct dsa_switch *ds = NULL;
	struct net_device *br;
	u16 pvlan;
1150 1151
	int i;

1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171
	if (dev < DSA_MAX_SWITCHES)
		ds = chip->ds->dst->ds[dev];

	/* Prevent frames from unknown switch or port */
	if (!ds || port >= ds->num_ports)
		return 0;

	/* Frames from DSA links and CPU ports can egress any local port */
	if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
		return mv88e6xxx_port_mask(chip);

	br = ds->ports[port].bridge_dev;
	pvlan = 0;

	/* Frames from user ports can egress any local DSA links and CPU ports,
	 * as well as any local member of their bridge group.
	 */
	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
		if (dsa_is_cpu_port(chip->ds, i) ||
		    dsa_is_dsa_port(chip->ds, i) ||
V
Vivien Didelot 已提交
1172
		    (br && dsa_to_port(chip->ds, i)->bridge_dev == br))
1173 1174 1175 1176 1177
			pvlan |= BIT(i);

	return pvlan;
}

1178
static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1179 1180
{
	u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1181 1182 1183

	/* prevent frames from going back out of the port they came in on */
	output_ports &= ~BIT(port);
1184

1185
	return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1186 1187
}

1188 1189
static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
					 u8 state)
1190
{
V
Vivien Didelot 已提交
1191
	struct mv88e6xxx_chip *chip = ds->priv;
1192
	int err;
1193

1194
	mutex_lock(&chip->reg_lock);
1195
	err = mv88e6xxx_port_set_state(chip, port, state);
1196
	mutex_unlock(&chip->reg_lock);
1197 1198

	if (err)
1199
		dev_err(ds->dev, "p%d: failed to update state\n", port);
1200 1201
}

1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220
static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
{
	int err;

	if (chip->info->ops->ieee_pri_map) {
		err = chip->info->ops->ieee_pri_map(chip);
		if (err)
			return err;
	}

	if (chip->info->ops->ip_pri_map) {
		err = chip->info->ops->ip_pri_map(chip);
		if (err)
			return err;
	}

	return 0;
}

1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240
static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
{
	int target, port;
	int err;

	if (!chip->info->global2_addr)
		return 0;

	/* Initialize the routing port to the 32 possible target devices */
	for (target = 0; target < 32; target++) {
		port = 0x1f;
		if (target < DSA_MAX_SWITCHES)
			if (chip->ds->rtable[target] != DSA_RTABLE_NONE)
				port = chip->ds->rtable[target];

		err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
		if (err)
			return err;
	}

1241 1242 1243 1244 1245 1246 1247
	if (chip->info->ops->set_cascade_port) {
		port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
		err = chip->info->ops->set_cascade_port(chip, port);
		if (err)
			return err;
	}

1248 1249 1250 1251
	err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
	if (err)
		return err;

1252 1253 1254
	return 0;
}

1255 1256 1257 1258 1259 1260 1261 1262 1263
static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
{
	/* Clear all trunk masks and mapping */
	if (chip->info->global2_addr)
		return mv88e6xxx_g2_trunk_clear(chip);

	return 0;
}

1264 1265 1266 1267 1268 1269 1270 1271
static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->rmu_disable)
		return chip->info->ops->rmu_disable(chip);

	return 0;
}

1272 1273 1274 1275 1276 1277 1278 1279
static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->pot_clear)
		return chip->info->ops->pot_clear(chip);

	return 0;
}

1280 1281 1282 1283 1284 1285 1286 1287
static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->mgmt_rsvd2cpu)
		return chip->info->ops->mgmt_rsvd2cpu(chip);

	return 0;
}

1288 1289
static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
{
1290 1291
	int err;

1292 1293 1294 1295
	err = mv88e6xxx_g1_atu_flush(chip, 0, true);
	if (err)
		return err;

1296 1297 1298 1299
	err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
	if (err)
		return err;

1300 1301 1302
	return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
}

1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322
static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
{
	int port;
	int err;

	if (!chip->info->ops->irl_init_all)
		return 0;

	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
		/* Disable ingress rate limiting by resetting all per port
		 * ingress rate limit resources to their initial state.
		 */
		err = chip->info->ops->irl_init_all(chip, port);
		if (err)
			return err;
	}

	return 0;
}

1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335
static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->set_switch_mac) {
		u8 addr[ETH_ALEN];

		eth_random_addr(addr);

		return chip->info->ops->set_switch_mac(chip, addr);
	}

	return 0;
}

1336 1337 1338 1339 1340 1341 1342 1343 1344
static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
{
	u16 pvlan = 0;

	if (!mv88e6xxx_has_pvt(chip))
		return -EOPNOTSUPP;

	/* Skip the local source device, which uses in-chip port VLAN */
	if (dev != chip->ds->index)
1345
		pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1346 1347 1348 1349

	return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
}

1350 1351
static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
{
1352 1353 1354
	int dev, port;
	int err;

1355 1356 1357 1358 1359 1360
	if (!mv88e6xxx_has_pvt(chip))
		return 0;

	/* Clear 5 Bit Port for usage with Marvell Link Street devices:
	 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
	 */
1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373
	err = mv88e6xxx_g2_misc_4_bit_port(chip);
	if (err)
		return err;

	for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
		for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
			err = mv88e6xxx_pvt_map(chip, dev, port);
			if (err)
				return err;
		}
	}

	return 0;
1374 1375
}

1376 1377 1378 1379 1380 1381
static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int err;

	mutex_lock(&chip->reg_lock);
1382
	err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
1383 1384 1385
	mutex_unlock(&chip->reg_lock);

	if (err)
1386
		dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
1387 1388
}

1389 1390 1391 1392 1393 1394 1395 1396
static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
{
	if (!chip->info->max_vid)
		return 0;

	return mv88e6xxx_g1_vtu_flush(chip);
}

1397 1398 1399 1400 1401 1402 1403 1404 1405
static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
				 struct mv88e6xxx_vtu_entry *entry)
{
	if (!chip->info->ops->vtu_getnext)
		return -EOPNOTSUPP;

	return chip->info->ops->vtu_getnext(chip, entry);
}

1406 1407 1408 1409 1410 1411 1412 1413 1414
static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
				   struct mv88e6xxx_vtu_entry *entry)
{
	if (!chip->info->ops->vtu_loadpurge)
		return -EOPNOTSUPP;

	return chip->info->ops->vtu_loadpurge(chip, entry);
}

1415
static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1416 1417
{
	DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1418 1419 1420
	struct mv88e6xxx_vtu_entry vlan = {
		.vid = chip->info->max_vid,
	};
1421
	int i, err;
1422 1423 1424

	bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);

1425
	/* Set every FID bit used by the (un)bridged ports */
1426
	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1427
		err = mv88e6xxx_port_get_fid(chip, i, fid);
1428 1429 1430 1431 1432 1433
		if (err)
			return err;

		set_bit(*fid, fid_bitmap);
	}

1434 1435
	/* Set every FID bit used by the VLAN entries */
	do {
1436
		err = mv88e6xxx_vtu_getnext(chip, &vlan);
1437 1438 1439 1440 1441 1442 1443
		if (err)
			return err;

		if (!vlan.valid)
			break;

		set_bit(vlan.fid, fid_bitmap);
1444
	} while (vlan.vid < chip->info->max_vid);
1445 1446 1447 1448 1449

	/* The reset value 0x000 is used to indicate that multiple address
	 * databases are not needed. Return the next positive available.
	 */
	*fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1450
	if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1451 1452 1453
		return -ENOSPC;

	/* Clear the database */
1454
	return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1455 1456
}

1457 1458
static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
			     struct mv88e6xxx_vtu_entry *entry, bool new)
1459 1460 1461 1462 1463 1464
{
	int err;

	if (!vid)
		return -EINVAL;

1465 1466
	entry->vid = vid - 1;
	entry->valid = false;
1467

1468
	err = mv88e6xxx_vtu_getnext(chip, entry);
1469 1470 1471
	if (err)
		return err;

1472 1473
	if (entry->vid == vid && entry->valid)
		return 0;
1474

1475 1476 1477 1478 1479 1480 1481 1482
	if (new) {
		int i;

		/* Initialize a fresh VLAN entry */
		memset(entry, 0, sizeof(*entry));
		entry->valid = true;
		entry->vid = vid;

1483
		/* Exclude all ports */
1484
		for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1485
			entry->member[i] =
1486
				MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1487 1488

		return mv88e6xxx_atu_new(chip, &entry->fid);
1489 1490
	}

1491 1492
	/* switchdev expects -EOPNOTSUPP to honor software VLANs */
	return -EOPNOTSUPP;
1493 1494
}

1495 1496 1497
static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
					u16 vid_begin, u16 vid_end)
{
V
Vivien Didelot 已提交
1498
	struct mv88e6xxx_chip *chip = ds->priv;
1499 1500 1501
	struct mv88e6xxx_vtu_entry vlan = {
		.vid = vid_begin - 1,
	};
1502 1503
	int i, err;

1504 1505 1506 1507
	/* DSA and CPU ports have to be members of multiple vlans */
	if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
		return 0;

1508 1509 1510
	if (!vid_begin)
		return -EOPNOTSUPP;

1511
	mutex_lock(&chip->reg_lock);
1512 1513

	do {
1514
		err = mv88e6xxx_vtu_getnext(chip, &vlan);
1515 1516 1517 1518 1519 1520 1521 1522 1523
		if (err)
			goto unlock;

		if (!vlan.valid)
			break;

		if (vlan.vid > vid_end)
			break;

1524
		for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1525 1526 1527
			if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
				continue;

1528
			if (!ds->ports[i].slave)
1529 1530
				continue;

1531
			if (vlan.member[i] ==
1532
			    MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1533 1534
				continue;

V
Vivien Didelot 已提交
1535
			if (dsa_to_port(ds, i)->bridge_dev ==
1536
			    ds->ports[port].bridge_dev)
1537 1538
				break; /* same bridge, check next VLAN */

V
Vivien Didelot 已提交
1539
			if (!dsa_to_port(ds, i)->bridge_dev)
1540 1541
				continue;

1542 1543
			dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
				port, vlan.vid, i,
V
Vivien Didelot 已提交
1544
				netdev_name(dsa_to_port(ds, i)->bridge_dev));
1545 1546 1547 1548 1549 1550
			err = -EOPNOTSUPP;
			goto unlock;
		}
	} while (vlan.vid < vid_end);

unlock:
1551
	mutex_unlock(&chip->reg_lock);
1552 1553 1554 1555

	return err;
}

1556 1557
static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
					 bool vlan_filtering)
1558
{
V
Vivien Didelot 已提交
1559
	struct mv88e6xxx_chip *chip = ds->priv;
1560 1561
	u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
		MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1562
	int err;
1563

1564
	if (!chip->info->max_vid)
1565 1566
		return -EOPNOTSUPP;

1567
	mutex_lock(&chip->reg_lock);
1568
	err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1569
	mutex_unlock(&chip->reg_lock);
1570

1571
	return err;
1572 1573
}

1574 1575
static int
mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1576
			    const struct switchdev_obj_port_vlan *vlan)
1577
{
V
Vivien Didelot 已提交
1578
	struct mv88e6xxx_chip *chip = ds->priv;
1579 1580
	int err;

1581
	if (!chip->info->max_vid)
1582 1583
		return -EOPNOTSUPP;

1584 1585 1586 1587 1588 1589 1590 1591
	/* If the requested port doesn't belong to the same bridge as the VLAN
	 * members, do not support it (yet) and fallback to software VLAN.
	 */
	err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
					   vlan->vid_end);
	if (err)
		return err;

1592 1593 1594 1595 1596 1597
	/* We don't need any dynamic resource from the kernel (yet),
	 * so skip the prepare phase.
	 */
	return 0;
}

1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641
static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
					const unsigned char *addr, u16 vid,
					u8 state)
{
	struct mv88e6xxx_vtu_entry vlan;
	struct mv88e6xxx_atu_entry entry;
	int err;

	/* Null VLAN ID corresponds to the port private database */
	if (vid == 0)
		err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
	else
		err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
	if (err)
		return err;

	entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
	ether_addr_copy(entry.mac, addr);
	eth_addr_dec(entry.mac);

	err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
	if (err)
		return err;

	/* Initialize a fresh ATU entry if it isn't found */
	if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED ||
	    !ether_addr_equal(entry.mac, addr)) {
		memset(&entry, 0, sizeof(entry));
		ether_addr_copy(entry.mac, addr);
	}

	/* Purge the ATU entry only if no port is using it anymore */
	if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
		entry.portvec &= ~BIT(port);
		if (!entry.portvec)
			entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
	} else {
		entry.portvec |= BIT(port);
		entry.state = state;
	}

	return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
}

1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664
static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
					u16 vid)
{
	const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
	u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;

	return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
}

static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
{
	int port;
	int err;

	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
		err = mv88e6xxx_port_add_broadcast(chip, port, vid);
		if (err)
			return err;
	}

	return 0;
}

1665
static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1666
				    u16 vid, u8 member)
1667
{
1668
	struct mv88e6xxx_vtu_entry vlan;
1669 1670
	int err;

1671
	err = mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1672
	if (err)
1673
		return err;
1674

1675
	vlan.member[port] = member;
1676

1677 1678 1679 1680 1681
	err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
	if (err)
		return err;

	return mv88e6xxx_broadcast_setup(chip, vid);
1682 1683
}

1684
static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1685
				    const struct switchdev_obj_port_vlan *vlan)
1686
{
V
Vivien Didelot 已提交
1687
	struct mv88e6xxx_chip *chip = ds->priv;
1688 1689
	bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
	bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1690
	u8 member;
1691 1692
	u16 vid;

1693
	if (!chip->info->max_vid)
1694 1695
		return;

1696
	if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1697
		member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
1698
	else if (untagged)
1699
		member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
1700
	else
1701
		member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
1702

1703
	mutex_lock(&chip->reg_lock);
1704

1705
	for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1706
		if (_mv88e6xxx_port_vlan_add(chip, port, vid, member))
1707 1708
			dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
				vid, untagged ? 'u' : 't');
1709

1710
	if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
1711 1712
		dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
			vlan->vid_end);
1713

1714
	mutex_unlock(&chip->reg_lock);
1715 1716
}

1717
static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1718
				    int port, u16 vid)
1719
{
1720
	struct mv88e6xxx_vtu_entry vlan;
1721 1722
	int i, err;

1723
	err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1724
	if (err)
1725
		return err;
1726

1727
	/* Tell switchdev if this VLAN is handled in software */
1728
	if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1729
		return -EOPNOTSUPP;
1730

1731
	vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1732 1733

	/* keep the VLAN unless all ports are excluded */
1734
	vlan.valid = false;
1735
	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1736 1737
		if (vlan.member[i] !=
		    MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1738
			vlan.valid = true;
1739 1740 1741 1742
			break;
		}
	}

1743
	err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1744 1745 1746
	if (err)
		return err;

1747
	return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
1748 1749
}

1750 1751
static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
				   const struct switchdev_obj_port_vlan *vlan)
1752
{
V
Vivien Didelot 已提交
1753
	struct mv88e6xxx_chip *chip = ds->priv;
1754 1755 1756
	u16 pvid, vid;
	int err = 0;

1757
	if (!chip->info->max_vid)
1758 1759
		return -EOPNOTSUPP;

1760
	mutex_lock(&chip->reg_lock);
1761

1762
	err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1763 1764 1765
	if (err)
		goto unlock;

1766
	for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1767
		err = _mv88e6xxx_port_vlan_del(chip, port, vid);
1768 1769 1770 1771
		if (err)
			goto unlock;

		if (vid == pvid) {
1772
			err = mv88e6xxx_port_set_pvid(chip, port, 0);
1773 1774 1775 1776 1777
			if (err)
				goto unlock;
		}
	}

1778
unlock:
1779
	mutex_unlock(&chip->reg_lock);
1780 1781 1782 1783

	return err;
}

1784 1785
static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
				  const unsigned char *addr, u16 vid)
1786
{
V
Vivien Didelot 已提交
1787
	struct mv88e6xxx_chip *chip = ds->priv;
1788
	int err;
1789

1790
	mutex_lock(&chip->reg_lock);
1791 1792
	err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
					   MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1793
	mutex_unlock(&chip->reg_lock);
1794 1795

	return err;
1796 1797
}

1798
static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1799
				  const unsigned char *addr, u16 vid)
1800
{
V
Vivien Didelot 已提交
1801
	struct mv88e6xxx_chip *chip = ds->priv;
1802
	int err;
1803

1804
	mutex_lock(&chip->reg_lock);
1805
	err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1806
					   MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
1807
	mutex_unlock(&chip->reg_lock);
1808

1809
	return err;
1810 1811
}

1812 1813
static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
				      u16 fid, u16 vid, int port,
1814
				      dsa_fdb_dump_cb_t *cb, void *data)
1815
{
1816
	struct mv88e6xxx_atu_entry addr;
1817
	bool is_static;
1818 1819
	int err;

1820
	addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1821
	eth_broadcast_addr(addr.mac);
1822 1823

	do {
1824
		mutex_lock(&chip->reg_lock);
1825
		err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
1826
		mutex_unlock(&chip->reg_lock);
1827
		if (err)
1828
			return err;
1829

1830
		if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED)
1831 1832
			break;

1833
		if (addr.trunk || (addr.portvec & BIT(port)) == 0)
1834 1835
			continue;

1836 1837
		if (!is_unicast_ether_addr(addr.mac))
			continue;
1838

1839 1840 1841
		is_static = (addr.state ==
			     MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
		err = cb(addr.mac, vid, is_static, data);
1842 1843
		if (err)
			return err;
1844 1845 1846 1847 1848
	} while (!is_broadcast_ether_addr(addr.mac));

	return err;
}

1849
static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
1850
				  dsa_fdb_dump_cb_t *cb, void *data)
1851
{
1852
	struct mv88e6xxx_vtu_entry vlan = {
1853
		.vid = chip->info->max_vid,
1854
	};
1855
	u16 fid;
1856 1857
	int err;

1858
	/* Dump port's default Filtering Information Database (VLAN ID 0) */
1859
	mutex_lock(&chip->reg_lock);
1860
	err = mv88e6xxx_port_get_fid(chip, port, &fid);
1861 1862
	mutex_unlock(&chip->reg_lock);

1863
	if (err)
1864
		return err;
1865

1866
	err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
1867
	if (err)
1868
		return err;
1869

1870
	/* Dump VLANs' Filtering Information Databases */
1871
	do {
1872
		mutex_lock(&chip->reg_lock);
1873
		err = mv88e6xxx_vtu_getnext(chip, &vlan);
1874
		mutex_unlock(&chip->reg_lock);
1875
		if (err)
1876
			return err;
1877 1878 1879 1880

		if (!vlan.valid)
			break;

1881
		err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
1882
						 cb, data);
1883
		if (err)
1884
			return err;
1885
	} while (vlan.vid < chip->info->max_vid);
1886

1887 1888 1889 1890
	return err;
}

static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
1891
				   dsa_fdb_dump_cb_t *cb, void *data)
1892
{
V
Vivien Didelot 已提交
1893
	struct mv88e6xxx_chip *chip = ds->priv;
1894

1895
	return mv88e6xxx_port_db_dump(chip, port, cb, data);
1896 1897
}

1898 1899
static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
				struct net_device *br)
1900
{
1901
	struct dsa_switch *ds;
1902
	int port;
1903
	int dev;
1904
	int err;
1905

1906 1907 1908 1909
	/* Remap the Port VLAN of each local bridge group member */
	for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
		if (chip->ds->ports[port].bridge_dev == br) {
			err = mv88e6xxx_port_vlan_map(chip, port);
1910
			if (err)
1911
				return err;
1912 1913 1914
		}
	}

1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932
	if (!mv88e6xxx_has_pvt(chip))
		return 0;

	/* Remap the Port VLAN of each cross-chip bridge group member */
	for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) {
		ds = chip->ds->dst->ds[dev];
		if (!ds)
			break;

		for (port = 0; port < ds->num_ports; ++port) {
			if (ds->ports[port].bridge_dev == br) {
				err = mv88e6xxx_pvt_map(chip, dev, port);
				if (err)
					return err;
			}
		}
	}

1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943
	return 0;
}

static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
				      struct net_device *br)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int err;

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_bridge_map(chip, br);
1944
	mutex_unlock(&chip->reg_lock);
1945

1946
	return err;
1947 1948
}

1949 1950
static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
					struct net_device *br)
1951
{
V
Vivien Didelot 已提交
1952
	struct mv88e6xxx_chip *chip = ds->priv;
1953

1954
	mutex_lock(&chip->reg_lock);
1955 1956 1957
	if (mv88e6xxx_bridge_map(chip, br) ||
	    mv88e6xxx_port_vlan_map(chip, port))
		dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
1958
	mutex_unlock(&chip->reg_lock);
1959 1960
}

1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990
static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
					   int port, struct net_device *br)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int err;

	if (!mv88e6xxx_has_pvt(chip))
		return 0;

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_pvt_map(chip, dev, port);
	mutex_unlock(&chip->reg_lock);

	return err;
}

static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
					     int port, struct net_device *br)
{
	struct mv88e6xxx_chip *chip = ds->priv;

	if (!mv88e6xxx_has_pvt(chip))
		return;

	mutex_lock(&chip->reg_lock);
	if (mv88e6xxx_pvt_map(chip, dev, port))
		dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
	mutex_unlock(&chip->reg_lock);
}

1991 1992 1993 1994 1995 1996 1997 1998
static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->reset)
		return chip->info->ops->reset(chip);

	return 0;
}

1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011
static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
{
	struct gpio_desc *gpiod = chip->reset;

	/* If there is a GPIO connected to the reset pin, toggle it */
	if (gpiod) {
		gpiod_set_value_cansleep(gpiod, 1);
		usleep_range(10000, 20000);
		gpiod_set_value_cansleep(gpiod, 0);
		usleep_range(10000, 20000);
	}
}

2012
static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
2013
{
2014
	int i, err;
2015

2016
	/* Set all ports to the Disabled state */
2017
	for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2018
		err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
2019 2020
		if (err)
			return err;
2021 2022
	}

2023 2024 2025
	/* Wait for transmit queues to drain,
	 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
	 */
2026 2027
	usleep_range(2000, 4000);

2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038
	return 0;
}

static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
{
	int err;

	err = mv88e6xxx_disable_ports(chip);
	if (err)
		return err;

2039
	mv88e6xxx_hardware_reset(chip);
2040

2041
	return mv88e6xxx_software_reset(chip);
2042 2043
}

2044
static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
2045 2046
				   enum mv88e6xxx_frame_mode frame,
				   enum mv88e6xxx_egress_mode egress, u16 etype)
2047 2048 2049
{
	int err;

2050 2051 2052 2053
	if (!chip->info->ops->port_set_frame_mode)
		return -EOPNOTSUPP;

	err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
2054 2055 2056
	if (err)
		return err;

2057 2058 2059 2060 2061 2062 2063 2064
	err = chip->info->ops->port_set_frame_mode(chip, port, frame);
	if (err)
		return err;

	if (chip->info->ops->port_set_ether_type)
		return chip->info->ops->port_set_ether_type(chip, port, etype);

	return 0;
2065 2066
}

2067
static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
2068
{
2069
	return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
2070
				       MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2071
				       MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2072
}
2073

2074 2075 2076
static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
{
	return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
2077
				       MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2078
				       MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2079
}
2080

2081 2082 2083 2084
static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
{
	return mv88e6xxx_set_port_mode(chip, port,
				       MV88E6XXX_FRAME_MODE_ETHERTYPE,
2085 2086
				       MV88E6XXX_EGRESS_MODE_ETHERTYPE,
				       ETH_P_EDSA);
2087
}
2088

2089 2090 2091 2092
static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
{
	if (dsa_is_dsa_port(chip->ds, port))
		return mv88e6xxx_set_port_mode_dsa(chip, port);
2093

2094
	if (dsa_is_user_port(chip->ds, port))
2095
		return mv88e6xxx_set_port_mode_normal(chip, port);
2096

2097 2098 2099
	/* Setup CPU port mode depending on its supported tag format */
	if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
		return mv88e6xxx_set_port_mode_dsa(chip, port);
2100

2101 2102
	if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
		return mv88e6xxx_set_port_mode_edsa(chip, port);
2103

2104
	return -EINVAL;
2105 2106
}

2107
static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
2108
{
2109
	bool message = dsa_is_dsa_port(chip->ds, port);
2110

2111
	return mv88e6xxx_port_set_message_port(chip, port, message);
2112
}
2113

2114
static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
2115
{
2116 2117
	struct dsa_switch *ds = chip->ds;
	bool flood;
2118

2119
	/* Upstream ports flood frames with unknown unicast or multicast DA */
2120
	flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port);
2121 2122 2123
	if (chip->info->ops->port_set_egress_floods)
		return chip->info->ops->port_set_egress_floods(chip, port,
							       flood, flood);
2124

2125
	return 0;
2126 2127
}

2128 2129 2130
static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
				  bool on)
{
2131 2132
	if (chip->info->ops->serdes_power)
		return chip->info->ops->serdes_power(chip, port, on);
2133

2134
	return 0;
2135 2136
}

2137 2138 2139 2140 2141 2142
static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
{
	struct dsa_switch *ds = chip->ds;
	int upstream_port;
	int err;

2143
	upstream_port = dsa_upstream_port(ds, port);
2144 2145 2146 2147 2148 2149 2150
	if (chip->info->ops->port_set_upstream_port) {
		err = chip->info->ops->port_set_upstream_port(chip, port,
							      upstream_port);
		if (err)
			return err;
	}

2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166
	if (port == upstream_port) {
		if (chip->info->ops->set_cpu_port) {
			err = chip->info->ops->set_cpu_port(chip,
							    upstream_port);
			if (err)
				return err;
		}

		if (chip->info->ops->set_egress_port) {
			err = chip->info->ops->set_egress_port(chip,
							       upstream_port);
			if (err)
				return err;
		}
	}

2167 2168 2169
	return 0;
}

2170
static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2171
{
2172
	struct dsa_switch *ds = chip->ds;
2173
	int err;
2174
	u16 reg;
2175

2176 2177 2178 2179 2180 2181 2182
	/* MAC Forcing register: don't force link, speed, duplex or flow control
	 * state to any particular values on physical ports, but force the CPU
	 * port and all DSA ports to their maximum bandwidth and full duplex.
	 */
	if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
		err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
					       SPEED_MAX, DUPLEX_FULL,
2183
					       PAUSE_OFF,
2184 2185 2186 2187
					       PHY_INTERFACE_MODE_NA);
	else
		err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
					       SPEED_UNFORCED, DUPLEX_UNFORCED,
2188
					       PAUSE_ON,
2189 2190 2191
					       PHY_INTERFACE_MODE_NA);
	if (err)
		return err;
2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206

	/* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
	 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
	 * tunneling, determine priority by looking at 802.1p and IP
	 * priority fields (IP prio has precedence), and set STP state
	 * to Forwarding.
	 *
	 * If this is the CPU link, use DSA or EDSA tagging depending
	 * on which tagging mode was configured.
	 *
	 * If this is a link to another switch, use DSA tagging mode.
	 *
	 * If this is the upstream port for this switch, enable
	 * forwarding of unknown unicasts and multicasts.
	 */
2207 2208 2209 2210
	reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
		MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
		MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
2211 2212
	if (err)
		return err;
2213

2214
	err = mv88e6xxx_setup_port_mode(chip, port);
2215 2216
	if (err)
		return err;
2217

2218
	err = mv88e6xxx_setup_egress_floods(chip, port);
2219 2220 2221
	if (err)
		return err;

2222 2223 2224
	/* Enable the SERDES interface for DSA and CPU ports. Normal
	 * ports SERDES are enabled when the port is enabled, thus
	 * saving a bit of power.
2225
	 */
2226 2227 2228 2229 2230
	if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) {
		err = mv88e6xxx_serdes_power(chip, port, true);
		if (err)
			return err;
	}
2231

2232
	/* Port Control 2: don't force a good FCS, set the maximum frame size to
2233
	 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2234 2235 2236
	 * untagged frames on this port, do a destination address lookup on all
	 * received packets as usual, disable ARP mirroring and don't send a
	 * copy of all transmitted/received frames on this port to the CPU.
2237
	 */
2238 2239 2240
	err = mv88e6xxx_port_set_map_da(chip, port);
	if (err)
		return err;
2241

2242 2243 2244
	err = mv88e6xxx_setup_upstream_port(chip, port);
	if (err)
		return err;
2245

2246
	err = mv88e6xxx_port_set_8021q_mode(chip, port,
2247
				MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
2248 2249 2250
	if (err)
		return err;

2251 2252
	if (chip->info->ops->port_set_jumbo_size) {
		err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
2253 2254 2255 2256
		if (err)
			return err;
	}

2257 2258 2259 2260 2261
	/* Port Association Vector: when learning source addresses
	 * of packets, add the address to the address database using
	 * a port bitmap that has only the bit for this port set and
	 * the other bits clear.
	 */
2262
	reg = 1 << port;
2263 2264
	/* Disable learning for CPU port */
	if (dsa_is_cpu_port(ds, port))
2265
		reg = 0;
2266

2267 2268
	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
				   reg);
2269 2270
	if (err)
		return err;
2271 2272

	/* Egress rate control 2: disable egress rate control. */
2273 2274
	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
				   0x0000);
2275 2276
	if (err)
		return err;
2277

2278 2279
	if (chip->info->ops->port_pause_limit) {
		err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
2280 2281
		if (err)
			return err;
2282
	}
2283

2284 2285 2286 2287 2288 2289
	if (chip->info->ops->port_disable_learn_limit) {
		err = chip->info->ops->port_disable_learn_limit(chip, port);
		if (err)
			return err;
	}

2290 2291
	if (chip->info->ops->port_disable_pri_override) {
		err = chip->info->ops->port_disable_pri_override(chip, port);
2292 2293
		if (err)
			return err;
2294
	}
2295

2296 2297
	if (chip->info->ops->port_tag_remap) {
		err = chip->info->ops->port_tag_remap(chip, port);
2298 2299
		if (err)
			return err;
2300 2301
	}

2302 2303
	if (chip->info->ops->port_egress_rate_limiting) {
		err = chip->info->ops->port_egress_rate_limiting(chip, port);
2304 2305
		if (err)
			return err;
2306 2307
	}

2308
	err = mv88e6xxx_setup_message_port(chip, port);
2309 2310
	if (err)
		return err;
2311

2312
	/* Port based VLAN map: give each port the same default address
2313 2314
	 * database, and allow bidirectional communication between the
	 * CPU and DSA port(s), and the other ports.
2315
	 */
2316
	err = mv88e6xxx_port_set_fid(chip, port, 0);
2317 2318
	if (err)
		return err;
2319

2320
	err = mv88e6xxx_port_vlan_map(chip, port);
2321 2322
	if (err)
		return err;
2323 2324 2325 2326

	/* Default VLAN ID and priority: don't set a default VLAN
	 * ID, and set the default packet priority to zero.
	 */
2327
	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
2328 2329
}

2330 2331 2332 2333
static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
				 struct phy_device *phydev)
{
	struct mv88e6xxx_chip *chip = ds->priv;
2334
	int err;
2335 2336

	mutex_lock(&chip->reg_lock);
2337
	err = mv88e6xxx_serdes_power(chip, port, true);
2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348
	mutex_unlock(&chip->reg_lock);

	return err;
}

static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port,
				   struct phy_device *phydev)
{
	struct mv88e6xxx_chip *chip = ds->priv;

	mutex_lock(&chip->reg_lock);
2349 2350
	if (mv88e6xxx_serdes_power(chip, port, false))
		dev_err(chip->dev, "failed to power off SERDES\n");
2351 2352 2353
	mutex_unlock(&chip->reg_lock);
}

2354 2355 2356
static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
				     unsigned int ageing_time)
{
V
Vivien Didelot 已提交
2357
	struct mv88e6xxx_chip *chip = ds->priv;
2358 2359 2360
	int err;

	mutex_lock(&chip->reg_lock);
2361
	err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2362 2363 2364 2365 2366
	mutex_unlock(&chip->reg_lock);

	return err;
}

2367
static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
2368
{
2369
	int err;
2370

2371
	/* Initialize the statistics unit */
2372 2373 2374 2375 2376
	if (chip->info->ops->stats_set_histogram) {
		err = chip->info->ops->stats_set_histogram(chip);
		if (err)
			return err;
	}
2377

2378
	return mv88e6xxx_g1_stats_clear(chip);
2379 2380
}

2381
static int mv88e6xxx_setup(struct dsa_switch *ds)
2382
{
V
Vivien Didelot 已提交
2383
	struct mv88e6xxx_chip *chip = ds->priv;
2384
	int err;
2385 2386
	int i;

2387
	chip->ds = ds;
2388
	ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
2389

2390
	mutex_lock(&chip->reg_lock);
2391

2392
	/* Setup Switch Port Registers */
2393
	for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2394 2395 2396
		if (dsa_is_unused_port(ds, i))
			continue;

2397 2398 2399 2400 2401
		err = mv88e6xxx_setup_port(chip, i);
		if (err)
			goto unlock;
	}

2402 2403 2404 2405
	err = mv88e6xxx_irl_setup(chip);
	if (err)
		goto unlock;

2406 2407 2408 2409
	err = mv88e6xxx_mac_setup(chip);
	if (err)
		goto unlock;

2410 2411 2412 2413
	err = mv88e6xxx_phy_setup(chip);
	if (err)
		goto unlock;

2414 2415 2416 2417
	err = mv88e6xxx_vtu_setup(chip);
	if (err)
		goto unlock;

2418 2419 2420 2421
	err = mv88e6xxx_pvt_setup(chip);
	if (err)
		goto unlock;

2422 2423 2424 2425
	err = mv88e6xxx_atu_setup(chip);
	if (err)
		goto unlock;

2426 2427 2428 2429
	err = mv88e6xxx_broadcast_setup(chip, 0);
	if (err)
		goto unlock;

2430 2431 2432 2433
	err = mv88e6xxx_pot_setup(chip);
	if (err)
		goto unlock;

2434 2435 2436 2437
	err = mv88e6xxx_rmu_setup(chip);
	if (err)
		goto unlock;

2438 2439 2440
	err = mv88e6xxx_rsvd2cpu_setup(chip);
	if (err)
		goto unlock;
2441

2442 2443 2444 2445
	err = mv88e6xxx_trunk_setup(chip);
	if (err)
		goto unlock;

2446 2447 2448 2449
	err = mv88e6xxx_devmap_setup(chip);
	if (err)
		goto unlock;

2450 2451 2452 2453
	err = mv88e6xxx_pri_setup(chip);
	if (err)
		goto unlock;

2454
	/* Setup PTP Hardware Clock and timestamping */
2455 2456 2457 2458
	if (chip->info->ptp_support) {
		err = mv88e6xxx_ptp_setup(chip);
		if (err)
			goto unlock;
2459 2460 2461 2462

		err = mv88e6xxx_hwtstamp_setup(chip);
		if (err)
			goto unlock;
2463 2464
	}

2465 2466 2467 2468
	err = mv88e6xxx_stats_setup(chip);
	if (err)
		goto unlock;

2469
unlock:
2470
	mutex_unlock(&chip->reg_lock);
2471

2472
	return err;
2473 2474
}

2475
static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
2476
{
2477 2478
	struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
	struct mv88e6xxx_chip *chip = mdio_bus->chip;
2479 2480
	u16 val;
	int err;
2481

2482 2483 2484
	if (!chip->info->ops->phy_read)
		return -EOPNOTSUPP;

2485
	mutex_lock(&chip->reg_lock);
2486
	err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
2487
	mutex_unlock(&chip->reg_lock);
2488

2489 2490 2491 2492 2493
	if (reg == MII_PHYSID2) {
		/* Some internal PHYS don't have a model number.  Use
		 * the mv88e6390 family model number instead.
		 */
		if (!(val & 0x3f0))
2494
			val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
2495 2496
	}

2497
	return err ? err : val;
2498 2499
}

2500
static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
2501
{
2502 2503
	struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
	struct mv88e6xxx_chip *chip = mdio_bus->chip;
2504
	int err;
2505

2506 2507 2508
	if (!chip->info->ops->phy_write)
		return -EOPNOTSUPP;

2509
	mutex_lock(&chip->reg_lock);
2510
	err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
2511
	mutex_unlock(&chip->reg_lock);
2512 2513

	return err;
2514 2515
}

2516
static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
2517 2518
				   struct device_node *np,
				   bool external)
2519 2520
{
	static int index;
2521
	struct mv88e6xxx_mdio_bus *mdio_bus;
2522 2523 2524
	struct mii_bus *bus;
	int err;

2525 2526 2527 2528 2529 2530 2531 2532 2533
	if (external) {
		mutex_lock(&chip->reg_lock);
		err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
		mutex_unlock(&chip->reg_lock);

		if (err)
			return err;
	}

2534
	bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
2535 2536 2537
	if (!bus)
		return -ENOMEM;

2538
	mdio_bus = bus->priv;
2539
	mdio_bus->bus = bus;
2540
	mdio_bus->chip = chip;
2541 2542
	INIT_LIST_HEAD(&mdio_bus->list);
	mdio_bus->external = external;
2543

2544 2545
	if (np) {
		bus->name = np->full_name;
2546
		snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
2547 2548 2549 2550 2551 2552 2553
	} else {
		bus->name = "mv88e6xxx SMI";
		snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
	}

	bus->read = mv88e6xxx_mdio_read;
	bus->write = mv88e6xxx_mdio_write;
2554
	bus->parent = chip->dev;
2555

2556 2557 2558 2559 2560 2561
	if (!external) {
		err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
		if (err)
			return err;
	}

2562
	err = of_mdiobus_register(bus, np);
2563
	if (err) {
2564
		dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
2565
		mv88e6xxx_g2_irq_mdio_free(chip, bus);
2566
		return err;
2567
	}
2568 2569 2570 2571 2572

	if (external)
		list_add_tail(&mdio_bus->list, &chip->mdios);
	else
		list_add(&mdio_bus->list, &chip->mdios);
2573 2574

	return 0;
2575
}
2576

2577 2578 2579 2580 2581
static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
	{ .compatible = "marvell,mv88e6xxx-mdio-external",
	  .data = (void *)true },
	{ },
};
2582

2583 2584 2585 2586 2587 2588 2589 2590 2591
static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)

{
	struct mv88e6xxx_mdio_bus *mdio_bus;
	struct mii_bus *bus;

	list_for_each_entry(mdio_bus, &chip->mdios, list) {
		bus = mdio_bus->bus;

2592 2593 2594
		if (!mdio_bus->external)
			mv88e6xxx_g2_irq_mdio_free(chip, bus);

2595 2596 2597 2598
		mdiobus_unregister(bus);
	}
}

2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622
static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
				    struct device_node *np)
{
	const struct of_device_id *match;
	struct device_node *child;
	int err;

	/* Always register one mdio bus for the internal/default mdio
	 * bus. This maybe represented in the device tree, but is
	 * optional.
	 */
	child = of_get_child_by_name(np, "mdio");
	err = mv88e6xxx_mdio_register(chip, child, false);
	if (err)
		return err;

	/* Walk the device tree, and see if there are any other nodes
	 * which say they are compatible with the external mdio
	 * bus.
	 */
	for_each_available_child_of_node(np, child) {
		match = of_match_node(mv88e6xxx_mdio_external_match, child);
		if (match) {
			err = mv88e6xxx_mdio_register(chip, child, true);
2623 2624
			if (err) {
				mv88e6xxx_mdios_unregister(chip);
2625
				return err;
2626
			}
2627 2628 2629 2630
		}
	}

	return 0;
2631 2632
}

2633 2634
static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
{
V
Vivien Didelot 已提交
2635
	struct mv88e6xxx_chip *chip = ds->priv;
2636 2637 2638 2639 2640 2641 2642

	return chip->eeprom_len;
}

static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
				struct ethtool_eeprom *eeprom, u8 *data)
{
V
Vivien Didelot 已提交
2643
	struct mv88e6xxx_chip *chip = ds->priv;
2644 2645
	int err;

2646 2647
	if (!chip->info->ops->get_eeprom)
		return -EOPNOTSUPP;
2648

2649 2650
	mutex_lock(&chip->reg_lock);
	err = chip->info->ops->get_eeprom(chip, eeprom, data);
2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663
	mutex_unlock(&chip->reg_lock);

	if (err)
		return err;

	eeprom->magic = 0xc3ec4951;

	return 0;
}

static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
				struct ethtool_eeprom *eeprom, u8 *data)
{
V
Vivien Didelot 已提交
2664
	struct mv88e6xxx_chip *chip = ds->priv;
2665 2666
	int err;

2667 2668 2669
	if (!chip->info->ops->set_eeprom)
		return -EOPNOTSUPP;

2670 2671 2672 2673
	if (eeprom->magic != 0xc3ec4951)
		return -EINVAL;

	mutex_lock(&chip->reg_lock);
2674
	err = chip->info->ops->set_eeprom(chip, eeprom, data);
2675 2676 2677 2678 2679
	mutex_unlock(&chip->reg_lock);

	return err;
}

2680
static const struct mv88e6xxx_ops mv88e6085_ops = {
2681
	/* MV88E6XXX_FAMILY_6097 */
2682 2683
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2684
	.irl_init_all = mv88e6352_g2_irl_init_all,
2685
	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2686 2687
	.phy_read = mv88e6185_phy_ppu_read,
	.phy_write = mv88e6185_phy_ppu_write,
2688
	.port_set_link = mv88e6xxx_port_set_link,
2689
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2690
	.port_set_speed = mv88e6185_port_set_speed,
2691
	.port_tag_remap = mv88e6095_port_tag_remap,
2692
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2693
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2694
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2695
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2696
	.port_pause_limit = mv88e6097_port_pause_limit,
2697
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2698
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2699
	.port_link_state = mv88e6352_port_link_state,
2700
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2701
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2702 2703
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2704
	.stats_get_stats = mv88e6095_stats_get_stats,
2705 2706
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2707
	.watchdog_ops = &mv88e6097_watchdog_ops,
2708
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2709
	.pot_clear = mv88e6xxx_g2_pot_clear,
2710 2711
	.ppu_enable = mv88e6185_g1_ppu_enable,
	.ppu_disable = mv88e6185_g1_ppu_disable,
2712
	.reset = mv88e6185_g1_reset,
2713
	.rmu_disable = mv88e6085_g1_rmu_disable,
2714
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2715
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2716
	.phylink_validate = mv88e6185_phylink_validate,
2717 2718 2719
};

static const struct mv88e6xxx_ops mv88e6095_ops = {
2720
	/* MV88E6XXX_FAMILY_6095 */
2721 2722
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2723
	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2724 2725
	.phy_read = mv88e6185_phy_ppu_read,
	.phy_write = mv88e6185_phy_ppu_write,
2726
	.port_set_link = mv88e6xxx_port_set_link,
2727
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2728
	.port_set_speed = mv88e6185_port_set_speed,
2729
	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
2730
	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
2731
	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
2732
	.port_link_state = mv88e6185_port_link_state,
2733
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2734
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2735 2736
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2737
	.stats_get_stats = mv88e6095_stats_get_stats,
2738
	.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2739 2740
	.ppu_enable = mv88e6185_g1_ppu_enable,
	.ppu_disable = mv88e6185_g1_ppu_disable,
2741
	.reset = mv88e6185_g1_reset,
2742
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
2743
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2744
	.phylink_validate = mv88e6185_phylink_validate,
2745 2746
};

2747
static const struct mv88e6xxx_ops mv88e6097_ops = {
2748
	/* MV88E6XXX_FAMILY_6097 */
2749 2750
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2751
	.irl_init_all = mv88e6352_g2_irl_init_all,
2752 2753 2754 2755 2756 2757
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_speed = mv88e6185_port_set_speed,
2758
	.port_tag_remap = mv88e6095_port_tag_remap,
2759
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2760
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2761
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2762
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2763
	.port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2764
	.port_pause_limit = mv88e6097_port_pause_limit,
2765
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2766
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2767
	.port_link_state = mv88e6352_port_link_state,
2768
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2769
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2770 2771 2772
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
	.stats_get_stats = mv88e6095_stats_get_stats,
2773 2774
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2775
	.watchdog_ops = &mv88e6097_watchdog_ops,
2776
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2777
	.pot_clear = mv88e6xxx_g2_pot_clear,
2778
	.reset = mv88e6352_g1_reset,
2779
	.rmu_disable = mv88e6085_g1_rmu_disable,
2780
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2781
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2782
	.phylink_validate = mv88e6185_phylink_validate,
2783 2784
};

2785
static const struct mv88e6xxx_ops mv88e6123_ops = {
2786
	/* MV88E6XXX_FAMILY_6165 */
2787 2788
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2789
	.irl_init_all = mv88e6352_g2_irl_init_all,
2790
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2791 2792
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2793
	.port_set_link = mv88e6xxx_port_set_link,
2794
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2795
	.port_set_speed = mv88e6185_port_set_speed,
2796
	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
2797
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2798
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2799
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2800
	.port_link_state = mv88e6352_port_link_state,
2801
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2802
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2803 2804
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2805
	.stats_get_stats = mv88e6095_stats_get_stats,
2806 2807
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2808
	.watchdog_ops = &mv88e6097_watchdog_ops,
2809
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2810
	.pot_clear = mv88e6xxx_g2_pot_clear,
2811
	.reset = mv88e6352_g1_reset,
2812
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2813
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2814
	.phylink_validate = mv88e6185_phylink_validate,
2815 2816 2817
};

static const struct mv88e6xxx_ops mv88e6131_ops = {
2818
	/* MV88E6XXX_FAMILY_6185 */
2819 2820
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2821
	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2822 2823
	.phy_read = mv88e6185_phy_ppu_read,
	.phy_write = mv88e6185_phy_ppu_write,
2824
	.port_set_link = mv88e6xxx_port_set_link,
2825
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2826
	.port_set_speed = mv88e6185_port_set_speed,
2827
	.port_tag_remap = mv88e6095_port_tag_remap,
2828
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2829
	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
2830
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2831
	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
2832
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2833
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2834
	.port_pause_limit = mv88e6097_port_pause_limit,
2835
	.port_set_pause = mv88e6185_port_set_pause,
2836
	.port_link_state = mv88e6352_port_link_state,
2837
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2838
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2839 2840
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2841
	.stats_get_stats = mv88e6095_stats_get_stats,
2842 2843
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2844
	.watchdog_ops = &mv88e6097_watchdog_ops,
2845
	.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2846
	.ppu_enable = mv88e6185_g1_ppu_enable,
2847
	.set_cascade_port = mv88e6185_g1_set_cascade_port,
2848
	.ppu_disable = mv88e6185_g1_ppu_disable,
2849
	.reset = mv88e6185_g1_reset,
2850
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
2851
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2852
	.phylink_validate = mv88e6185_phylink_validate,
2853 2854
};

2855 2856
static const struct mv88e6xxx_ops mv88e6141_ops = {
	/* MV88E6XXX_FAMILY_6341 */
2857 2858
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2859
	.irl_init_all = mv88e6352_g2_irl_init_all,
2860 2861 2862 2863 2864 2865 2866 2867 2868 2869 2870 2871 2872
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
	.port_tag_remap = mv88e6095_port_tag_remap,
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2873
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2874
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2875
	.port_pause_limit = mv88e6097_port_pause_limit,
2876 2877
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2878
	.port_link_state = mv88e6352_port_link_state,
2879
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
2880
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2881 2882 2883
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
	.stats_get_stats = mv88e6390_stats_get_stats,
2884 2885
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
2886 2887
	.watchdog_ops = &mv88e6390_watchdog_ops,
	.mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
2888
	.pot_clear = mv88e6xxx_g2_pot_clear,
2889
	.reset = mv88e6352_g1_reset,
2890
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2891
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2892
	.serdes_power = mv88e6341_serdes_power,
2893
	.gpio_ops = &mv88e6352_gpio_ops,
2894
	.phylink_validate = mv88e6390_phylink_validate,
2895 2896
};

2897
static const struct mv88e6xxx_ops mv88e6161_ops = {
2898
	/* MV88E6XXX_FAMILY_6165 */
2899 2900
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2901
	.irl_init_all = mv88e6352_g2_irl_init_all,
2902
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2903 2904
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2905
	.port_set_link = mv88e6xxx_port_set_link,
2906
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2907
	.port_set_speed = mv88e6185_port_set_speed,
2908
	.port_tag_remap = mv88e6095_port_tag_remap,
2909
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2910
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2911
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2912
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2913
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2914
	.port_pause_limit = mv88e6097_port_pause_limit,
2915
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2916
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2917
	.port_link_state = mv88e6352_port_link_state,
2918
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2919
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2920 2921
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2922
	.stats_get_stats = mv88e6095_stats_get_stats,
2923 2924
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2925
	.watchdog_ops = &mv88e6097_watchdog_ops,
2926
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2927
	.pot_clear = mv88e6xxx_g2_pot_clear,
2928
	.reset = mv88e6352_g1_reset,
2929
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2930
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2931
	.avb_ops = &mv88e6165_avb_ops,
2932
	.ptp_ops = &mv88e6165_ptp_ops,
2933
	.phylink_validate = mv88e6185_phylink_validate,
2934 2935 2936
};

static const struct mv88e6xxx_ops mv88e6165_ops = {
2937
	/* MV88E6XXX_FAMILY_6165 */
2938 2939
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2940
	.irl_init_all = mv88e6352_g2_irl_init_all,
2941
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2942 2943
	.phy_read = mv88e6165_phy_read,
	.phy_write = mv88e6165_phy_write,
2944
	.port_set_link = mv88e6xxx_port_set_link,
2945
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2946
	.port_set_speed = mv88e6185_port_set_speed,
2947
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2948
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2949
	.port_link_state = mv88e6352_port_link_state,
2950
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2951
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2952 2953
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2954
	.stats_get_stats = mv88e6095_stats_get_stats,
2955 2956
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2957
	.watchdog_ops = &mv88e6097_watchdog_ops,
2958
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2959
	.pot_clear = mv88e6xxx_g2_pot_clear,
2960
	.reset = mv88e6352_g1_reset,
2961
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2962
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2963
	.avb_ops = &mv88e6165_avb_ops,
2964
	.ptp_ops = &mv88e6165_ptp_ops,
2965
	.phylink_validate = mv88e6185_phylink_validate,
2966 2967 2968
};

static const struct mv88e6xxx_ops mv88e6171_ops = {
2969
	/* MV88E6XXX_FAMILY_6351 */
2970 2971
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2972
	.irl_init_all = mv88e6352_g2_irl_init_all,
2973
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2974 2975
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2976
	.port_set_link = mv88e6xxx_port_set_link,
2977
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2978
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2979
	.port_set_speed = mv88e6185_port_set_speed,
2980
	.port_tag_remap = mv88e6095_port_tag_remap,
2981
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2982
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2983
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2984
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2985
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2986
	.port_pause_limit = mv88e6097_port_pause_limit,
2987
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2988
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2989
	.port_link_state = mv88e6352_port_link_state,
2990
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2991
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2992 2993
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2994
	.stats_get_stats = mv88e6095_stats_get_stats,
2995 2996
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2997
	.watchdog_ops = &mv88e6097_watchdog_ops,
2998
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2999
	.pot_clear = mv88e6xxx_g2_pot_clear,
3000
	.reset = mv88e6352_g1_reset,
3001
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3002
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3003
	.phylink_validate = mv88e6185_phylink_validate,
3004 3005 3006
};

static const struct mv88e6xxx_ops mv88e6172_ops = {
3007
	/* MV88E6XXX_FAMILY_6352 */
3008 3009
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3010
	.irl_init_all = mv88e6352_g2_irl_init_all,
3011 3012
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
3013
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3014 3015
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3016
	.port_set_link = mv88e6xxx_port_set_link,
3017
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3018
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3019
	.port_set_speed = mv88e6352_port_set_speed,
3020
	.port_tag_remap = mv88e6095_port_tag_remap,
3021
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3022
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3023
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3024
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3025
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3026
	.port_pause_limit = mv88e6097_port_pause_limit,
3027
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3028
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3029
	.port_link_state = mv88e6352_port_link_state,
3030
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3031
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3032 3033
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
3034
	.stats_get_stats = mv88e6095_stats_get_stats,
3035 3036
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3037
	.watchdog_ops = &mv88e6097_watchdog_ops,
3038
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3039
	.pot_clear = mv88e6xxx_g2_pot_clear,
3040
	.reset = mv88e6352_g1_reset,
3041
	.rmu_disable = mv88e6352_g1_rmu_disable,
3042
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3043
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3044
	.serdes_power = mv88e6352_serdes_power,
3045
	.gpio_ops = &mv88e6352_gpio_ops,
3046
	.phylink_validate = mv88e6352_phylink_validate,
3047 3048 3049
};

static const struct mv88e6xxx_ops mv88e6175_ops = {
3050
	/* MV88E6XXX_FAMILY_6351 */
3051 3052
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3053
	.irl_init_all = mv88e6352_g2_irl_init_all,
3054
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3055 3056
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3057
	.port_set_link = mv88e6xxx_port_set_link,
3058
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3059
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3060
	.port_set_speed = mv88e6185_port_set_speed,
3061
	.port_tag_remap = mv88e6095_port_tag_remap,
3062
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3063
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3064
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3065
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3066
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3067
	.port_pause_limit = mv88e6097_port_pause_limit,
3068
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3069
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3070
	.port_link_state = mv88e6352_port_link_state,
3071
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3072
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3073 3074
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
3075
	.stats_get_stats = mv88e6095_stats_get_stats,
3076 3077
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3078
	.watchdog_ops = &mv88e6097_watchdog_ops,
3079
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3080
	.pot_clear = mv88e6xxx_g2_pot_clear,
3081
	.reset = mv88e6352_g1_reset,
3082
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3083
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3084
	.phylink_validate = mv88e6185_phylink_validate,
3085 3086 3087
};

static const struct mv88e6xxx_ops mv88e6176_ops = {
3088
	/* MV88E6XXX_FAMILY_6352 */
3089 3090
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3091
	.irl_init_all = mv88e6352_g2_irl_init_all,
3092 3093
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
3094
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3095 3096
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3097
	.port_set_link = mv88e6xxx_port_set_link,
3098
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3099
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3100
	.port_set_speed = mv88e6352_port_set_speed,
3101
	.port_tag_remap = mv88e6095_port_tag_remap,
3102
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3103
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3104
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3105
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3106
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3107
	.port_pause_limit = mv88e6097_port_pause_limit,
3108
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3109
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3110
	.port_link_state = mv88e6352_port_link_state,
3111
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3112
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3113 3114
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
3115
	.stats_get_stats = mv88e6095_stats_get_stats,
3116 3117
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3118
	.watchdog_ops = &mv88e6097_watchdog_ops,
3119
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3120
	.pot_clear = mv88e6xxx_g2_pot_clear,
3121
	.reset = mv88e6352_g1_reset,
3122
	.rmu_disable = mv88e6352_g1_rmu_disable,
3123
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3124
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3125
	.serdes_power = mv88e6352_serdes_power,
3126
	.gpio_ops = &mv88e6352_gpio_ops,
3127
	.phylink_validate = mv88e6352_phylink_validate,
3128 3129 3130
};

static const struct mv88e6xxx_ops mv88e6185_ops = {
3131
	/* MV88E6XXX_FAMILY_6185 */
3132 3133
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3134
	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3135 3136
	.phy_read = mv88e6185_phy_ppu_read,
	.phy_write = mv88e6185_phy_ppu_write,
3137
	.port_set_link = mv88e6xxx_port_set_link,
3138
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3139
	.port_set_speed = mv88e6185_port_set_speed,
3140
	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
3141
	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
3142
	.port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3143
	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
3144
	.port_set_pause = mv88e6185_port_set_pause,
3145
	.port_link_state = mv88e6185_port_link_state,
3146
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3147
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3148 3149
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
3150
	.stats_get_stats = mv88e6095_stats_get_stats,
3151 3152
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3153
	.watchdog_ops = &mv88e6097_watchdog_ops,
3154
	.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3155
	.set_cascade_port = mv88e6185_g1_set_cascade_port,
3156 3157
	.ppu_enable = mv88e6185_g1_ppu_enable,
	.ppu_disable = mv88e6185_g1_ppu_disable,
3158
	.reset = mv88e6185_g1_reset,
3159
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
3160
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3161
	.phylink_validate = mv88e6185_phylink_validate,
3162 3163
};

3164
static const struct mv88e6xxx_ops mv88e6190_ops = {
3165
	/* MV88E6XXX_FAMILY_6390 */
3166
	.irl_init_all = mv88e6390_g2_irl_init_all,
3167 3168
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3169 3170 3171 3172 3173 3174 3175
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
3176
	.port_tag_remap = mv88e6390_port_tag_remap,
3177
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3178
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3179
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3180
	.port_pause_limit = mv88e6390_port_pause_limit,
3181
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3182
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3183
	.port_link_state = mv88e6352_port_link_state,
3184
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3185
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3186 3187
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3188
	.stats_get_stats = mv88e6390_stats_get_stats,
3189 3190
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3191
	.watchdog_ops = &mv88e6390_watchdog_ops,
3192
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3193
	.pot_clear = mv88e6xxx_g2_pot_clear,
3194
	.reset = mv88e6352_g1_reset,
3195
	.rmu_disable = mv88e6390_g1_rmu_disable,
3196 3197
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3198
	.serdes_power = mv88e6390_serdes_power,
3199
	.gpio_ops = &mv88e6352_gpio_ops,
3200
	.phylink_validate = mv88e6390_phylink_validate,
3201 3202 3203
};

static const struct mv88e6xxx_ops mv88e6190x_ops = {
3204
	/* MV88E6XXX_FAMILY_6390 */
3205
	.irl_init_all = mv88e6390_g2_irl_init_all,
3206 3207
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3208 3209 3210 3211 3212 3213 3214
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390x_port_set_speed,
3215
	.port_tag_remap = mv88e6390_port_tag_remap,
3216
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3217
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3218
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3219
	.port_pause_limit = mv88e6390_port_pause_limit,
3220
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3221
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3222
	.port_link_state = mv88e6352_port_link_state,
3223
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3224
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3225 3226
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3227
	.stats_get_stats = mv88e6390_stats_get_stats,
3228 3229
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3230
	.watchdog_ops = &mv88e6390_watchdog_ops,
3231
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3232
	.pot_clear = mv88e6xxx_g2_pot_clear,
3233
	.reset = mv88e6352_g1_reset,
3234
	.rmu_disable = mv88e6390_g1_rmu_disable,
3235 3236
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3237
	.serdes_power = mv88e6390_serdes_power,
3238
	.gpio_ops = &mv88e6352_gpio_ops,
3239
	.phylink_validate = mv88e6390x_phylink_validate,
3240 3241 3242
};

static const struct mv88e6xxx_ops mv88e6191_ops = {
3243
	/* MV88E6XXX_FAMILY_6390 */
3244
	.irl_init_all = mv88e6390_g2_irl_init_all,
3245 3246
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3247 3248 3249 3250 3251 3252 3253
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
3254
	.port_tag_remap = mv88e6390_port_tag_remap,
3255
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3256
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3257
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3258
	.port_pause_limit = mv88e6390_port_pause_limit,
3259
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3260
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3261
	.port_link_state = mv88e6352_port_link_state,
3262
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3263
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3264 3265
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3266
	.stats_get_stats = mv88e6390_stats_get_stats,
3267 3268
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3269
	.watchdog_ops = &mv88e6390_watchdog_ops,
3270
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3271
	.pot_clear = mv88e6xxx_g2_pot_clear,
3272
	.reset = mv88e6352_g1_reset,
3273
	.rmu_disable = mv88e6390_g1_rmu_disable,
3274 3275
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3276
	.serdes_power = mv88e6390_serdes_power,
3277 3278
	.avb_ops = &mv88e6390_avb_ops,
	.ptp_ops = &mv88e6352_ptp_ops,
3279
	.phylink_validate = mv88e6390_phylink_validate,
3280 3281
};

3282
static const struct mv88e6xxx_ops mv88e6240_ops = {
3283
	/* MV88E6XXX_FAMILY_6352 */
3284 3285
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3286
	.irl_init_all = mv88e6352_g2_irl_init_all,
3287 3288
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
3289
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3290 3291
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3292
	.port_set_link = mv88e6xxx_port_set_link,
3293
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3294
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3295
	.port_set_speed = mv88e6352_port_set_speed,
3296
	.port_tag_remap = mv88e6095_port_tag_remap,
3297
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3298
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3299
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3300
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3301
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3302
	.port_pause_limit = mv88e6097_port_pause_limit,
3303
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3304
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3305
	.port_link_state = mv88e6352_port_link_state,
3306
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3307
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3308 3309
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
3310
	.stats_get_stats = mv88e6095_stats_get_stats,
3311 3312
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3313
	.watchdog_ops = &mv88e6097_watchdog_ops,
3314
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3315
	.pot_clear = mv88e6xxx_g2_pot_clear,
3316
	.reset = mv88e6352_g1_reset,
3317
	.rmu_disable = mv88e6352_g1_rmu_disable,
3318
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3319
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3320
	.serdes_power = mv88e6352_serdes_power,
3321
	.gpio_ops = &mv88e6352_gpio_ops,
3322
	.avb_ops = &mv88e6352_avb_ops,
3323
	.ptp_ops = &mv88e6352_ptp_ops,
3324
	.phylink_validate = mv88e6352_phylink_validate,
3325 3326
};

3327
static const struct mv88e6xxx_ops mv88e6290_ops = {
3328
	/* MV88E6XXX_FAMILY_6390 */
3329
	.irl_init_all = mv88e6390_g2_irl_init_all,
3330 3331
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3332 3333 3334 3335 3336 3337 3338
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
3339
	.port_tag_remap = mv88e6390_port_tag_remap,
3340
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3341
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3342
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3343
	.port_pause_limit = mv88e6390_port_pause_limit,
3344
	.port_set_cmode = mv88e6390x_port_set_cmode,
3345
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3346
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3347
	.port_link_state = mv88e6352_port_link_state,
3348
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3349
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3350 3351
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3352
	.stats_get_stats = mv88e6390_stats_get_stats,
3353 3354
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3355
	.watchdog_ops = &mv88e6390_watchdog_ops,
3356
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3357
	.pot_clear = mv88e6xxx_g2_pot_clear,
3358
	.reset = mv88e6352_g1_reset,
3359
	.rmu_disable = mv88e6390_g1_rmu_disable,
3360 3361
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3362
	.serdes_power = mv88e6390_serdes_power,
3363
	.gpio_ops = &mv88e6352_gpio_ops,
3364
	.avb_ops = &mv88e6390_avb_ops,
3365
	.ptp_ops = &mv88e6352_ptp_ops,
3366
	.phylink_validate = mv88e6390_phylink_validate,
3367 3368
};

3369
static const struct mv88e6xxx_ops mv88e6320_ops = {
3370
	/* MV88E6XXX_FAMILY_6320 */
3371 3372
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3373
	.irl_init_all = mv88e6352_g2_irl_init_all,
3374 3375
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
3376
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3377 3378
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3379
	.port_set_link = mv88e6xxx_port_set_link,
3380
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3381
	.port_set_speed = mv88e6185_port_set_speed,
3382
	.port_tag_remap = mv88e6095_port_tag_remap,
3383
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3384
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3385
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3386
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3387
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3388
	.port_pause_limit = mv88e6097_port_pause_limit,
3389
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3390
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3391
	.port_link_state = mv88e6352_port_link_state,
3392
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3393
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3394 3395
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3396
	.stats_get_stats = mv88e6320_stats_get_stats,
3397 3398
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3399
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3400
	.pot_clear = mv88e6xxx_g2_pot_clear,
3401
	.reset = mv88e6352_g1_reset,
3402
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
3403
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3404
	.gpio_ops = &mv88e6352_gpio_ops,
3405
	.avb_ops = &mv88e6352_avb_ops,
3406
	.ptp_ops = &mv88e6352_ptp_ops,
3407
	.phylink_validate = mv88e6185_phylink_validate,
3408 3409 3410
};

static const struct mv88e6xxx_ops mv88e6321_ops = {
3411
	/* MV88E6XXX_FAMILY_6320 */
3412 3413
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3414
	.irl_init_all = mv88e6352_g2_irl_init_all,
3415 3416
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
3417
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3418 3419
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3420
	.port_set_link = mv88e6xxx_port_set_link,
3421
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3422
	.port_set_speed = mv88e6185_port_set_speed,
3423
	.port_tag_remap = mv88e6095_port_tag_remap,
3424
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3425
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3426
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3427
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3428
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3429
	.port_pause_limit = mv88e6097_port_pause_limit,
3430
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3431
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3432
	.port_link_state = mv88e6352_port_link_state,
3433
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3434
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3435 3436
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3437
	.stats_get_stats = mv88e6320_stats_get_stats,
3438 3439
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3440
	.reset = mv88e6352_g1_reset,
3441
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
3442
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3443
	.gpio_ops = &mv88e6352_gpio_ops,
3444
	.avb_ops = &mv88e6352_avb_ops,
3445
	.ptp_ops = &mv88e6352_ptp_ops,
3446
	.phylink_validate = mv88e6185_phylink_validate,
3447 3448
};

3449 3450
static const struct mv88e6xxx_ops mv88e6341_ops = {
	/* MV88E6XXX_FAMILY_6341 */
3451 3452
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3453
	.irl_init_all = mv88e6352_g2_irl_init_all,
3454 3455 3456 3457 3458 3459 3460 3461 3462 3463 3464 3465 3466
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
	.port_tag_remap = mv88e6095_port_tag_remap,
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3467
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3468
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3469
	.port_pause_limit = mv88e6097_port_pause_limit,
3470 3471
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3472
	.port_link_state = mv88e6352_port_link_state,
3473
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3474
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3475 3476 3477
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
	.stats_get_stats = mv88e6390_stats_get_stats,
3478 3479
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3480 3481
	.watchdog_ops = &mv88e6390_watchdog_ops,
	.mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
3482
	.pot_clear = mv88e6xxx_g2_pot_clear,
3483
	.reset = mv88e6352_g1_reset,
3484
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3485
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3486
	.serdes_power = mv88e6341_serdes_power,
3487
	.gpio_ops = &mv88e6352_gpio_ops,
3488
	.avb_ops = &mv88e6390_avb_ops,
3489
	.ptp_ops = &mv88e6352_ptp_ops,
3490
	.phylink_validate = mv88e6390_phylink_validate,
3491 3492
};

3493
static const struct mv88e6xxx_ops mv88e6350_ops = {
3494
	/* MV88E6XXX_FAMILY_6351 */
3495 3496
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3497
	.irl_init_all = mv88e6352_g2_irl_init_all,
3498
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3499 3500
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3501
	.port_set_link = mv88e6xxx_port_set_link,
3502
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3503
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3504
	.port_set_speed = mv88e6185_port_set_speed,
3505
	.port_tag_remap = mv88e6095_port_tag_remap,
3506
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3507
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3508
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3509
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3510
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3511
	.port_pause_limit = mv88e6097_port_pause_limit,
3512
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3513
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3514
	.port_link_state = mv88e6352_port_link_state,
3515
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3516
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3517 3518
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
3519
	.stats_get_stats = mv88e6095_stats_get_stats,
3520 3521
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3522
	.watchdog_ops = &mv88e6097_watchdog_ops,
3523
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3524
	.pot_clear = mv88e6xxx_g2_pot_clear,
3525
	.reset = mv88e6352_g1_reset,
3526
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3527
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3528
	.phylink_validate = mv88e6185_phylink_validate,
3529 3530 3531
};

static const struct mv88e6xxx_ops mv88e6351_ops = {
3532
	/* MV88E6XXX_FAMILY_6351 */
3533 3534
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3535
	.irl_init_all = mv88e6352_g2_irl_init_all,
3536
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3537 3538
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3539
	.port_set_link = mv88e6xxx_port_set_link,
3540
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3541
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3542
	.port_set_speed = mv88e6185_port_set_speed,
3543
	.port_tag_remap = mv88e6095_port_tag_remap,
3544
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3545
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3546
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3547
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3548
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3549
	.port_pause_limit = mv88e6097_port_pause_limit,
3550
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3551
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3552
	.port_link_state = mv88e6352_port_link_state,
3553
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3554
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3555 3556
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
3557
	.stats_get_stats = mv88e6095_stats_get_stats,
3558 3559
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3560
	.watchdog_ops = &mv88e6097_watchdog_ops,
3561
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3562
	.pot_clear = mv88e6xxx_g2_pot_clear,
3563
	.reset = mv88e6352_g1_reset,
3564
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3565
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3566
	.avb_ops = &mv88e6352_avb_ops,
3567
	.ptp_ops = &mv88e6352_ptp_ops,
3568
	.phylink_validate = mv88e6185_phylink_validate,
3569 3570 3571
};

static const struct mv88e6xxx_ops mv88e6352_ops = {
3572
	/* MV88E6XXX_FAMILY_6352 */
3573 3574
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3575
	.irl_init_all = mv88e6352_g2_irl_init_all,
3576 3577
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
3578
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3579 3580
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3581
	.port_set_link = mv88e6xxx_port_set_link,
3582
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3583
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3584
	.port_set_speed = mv88e6352_port_set_speed,
3585
	.port_tag_remap = mv88e6095_port_tag_remap,
3586
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3587
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3588
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3589
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3590
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3591
	.port_pause_limit = mv88e6097_port_pause_limit,
3592
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3593
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3594
	.port_link_state = mv88e6352_port_link_state,
3595
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3596
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3597 3598
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
3599
	.stats_get_stats = mv88e6095_stats_get_stats,
3600 3601
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3602
	.watchdog_ops = &mv88e6097_watchdog_ops,
3603
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3604
	.pot_clear = mv88e6xxx_g2_pot_clear,
3605
	.reset = mv88e6352_g1_reset,
3606
	.rmu_disable = mv88e6352_g1_rmu_disable,
3607
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3608
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3609
	.serdes_power = mv88e6352_serdes_power,
3610
	.gpio_ops = &mv88e6352_gpio_ops,
3611
	.avb_ops = &mv88e6352_avb_ops,
3612
	.ptp_ops = &mv88e6352_ptp_ops,
3613 3614 3615
	.serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
	.serdes_get_strings = mv88e6352_serdes_get_strings,
	.serdes_get_stats = mv88e6352_serdes_get_stats,
3616
	.phylink_validate = mv88e6352_phylink_validate,
3617 3618
};

3619
static const struct mv88e6xxx_ops mv88e6390_ops = {
3620
	/* MV88E6XXX_FAMILY_6390 */
3621
	.irl_init_all = mv88e6390_g2_irl_init_all,
3622 3623
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3624 3625 3626 3627 3628 3629 3630
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
3631
	.port_tag_remap = mv88e6390_port_tag_remap,
3632
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3633
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3634
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3635
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3636
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3637
	.port_pause_limit = mv88e6390_port_pause_limit,
3638
	.port_set_cmode = mv88e6390x_port_set_cmode,
3639
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3640
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3641
	.port_link_state = mv88e6352_port_link_state,
3642
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3643
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3644 3645
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3646
	.stats_get_stats = mv88e6390_stats_get_stats,
3647 3648
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3649
	.watchdog_ops = &mv88e6390_watchdog_ops,
3650
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3651
	.pot_clear = mv88e6xxx_g2_pot_clear,
3652
	.reset = mv88e6352_g1_reset,
3653
	.rmu_disable = mv88e6390_g1_rmu_disable,
3654 3655
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3656
	.serdes_power = mv88e6390_serdes_power,
3657
	.gpio_ops = &mv88e6352_gpio_ops,
3658
	.avb_ops = &mv88e6390_avb_ops,
3659
	.ptp_ops = &mv88e6352_ptp_ops,
3660
	.phylink_validate = mv88e6390_phylink_validate,
3661 3662 3663
};

static const struct mv88e6xxx_ops mv88e6390x_ops = {
3664
	/* MV88E6XXX_FAMILY_6390 */
3665
	.irl_init_all = mv88e6390_g2_irl_init_all,
3666 3667
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3668 3669 3670 3671 3672 3673 3674
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390x_port_set_speed,
3675
	.port_tag_remap = mv88e6390_port_tag_remap,
3676
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3677
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3678
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3679
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3680
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3681
	.port_pause_limit = mv88e6390_port_pause_limit,
3682
	.port_set_cmode = mv88e6390x_port_set_cmode,
3683
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3684
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3685
	.port_link_state = mv88e6352_port_link_state,
3686
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3687
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3688 3689
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3690
	.stats_get_stats = mv88e6390_stats_get_stats,
3691 3692
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3693
	.watchdog_ops = &mv88e6390_watchdog_ops,
3694
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3695
	.pot_clear = mv88e6xxx_g2_pot_clear,
3696
	.reset = mv88e6352_g1_reset,
3697
	.rmu_disable = mv88e6390_g1_rmu_disable,
3698 3699
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3700
	.serdes_power = mv88e6390_serdes_power,
3701
	.gpio_ops = &mv88e6352_gpio_ops,
3702
	.avb_ops = &mv88e6390_avb_ops,
3703
	.ptp_ops = &mv88e6352_ptp_ops,
3704
	.phylink_validate = mv88e6390x_phylink_validate,
3705 3706
};

3707 3708
static const struct mv88e6xxx_info mv88e6xxx_table[] = {
	[MV88E6085] = {
3709
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
3710 3711 3712 3713
		.family = MV88E6XXX_FAMILY_6097,
		.name = "Marvell 88E6085",
		.num_databases = 4096,
		.num_ports = 10,
3714
		.num_internal_phys = 5,
3715
		.max_vid = 4095,
3716
		.port_base_addr = 0x10,
3717
		.phy_base_addr = 0x0,
3718
		.global1_addr = 0x1b,
3719
		.global2_addr = 0x1c,
3720
		.age_time_coeff = 15000,
3721
		.g1_irqs = 8,
3722
		.g2_irqs = 10,
3723
		.atu_move_port_mask = 0xf,
3724
		.pvt = true,
3725
		.multi_chip = true,
3726
		.tag_protocol = DSA_TAG_PROTO_DSA,
3727
		.ops = &mv88e6085_ops,
3728 3729 3730
	},

	[MV88E6095] = {
3731
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
3732 3733 3734 3735
		.family = MV88E6XXX_FAMILY_6095,
		.name = "Marvell 88E6095/88E6095F",
		.num_databases = 256,
		.num_ports = 11,
3736
		.num_internal_phys = 0,
3737
		.max_vid = 4095,
3738
		.port_base_addr = 0x10,
3739
		.phy_base_addr = 0x0,
3740
		.global1_addr = 0x1b,
3741
		.global2_addr = 0x1c,
3742
		.age_time_coeff = 15000,
3743
		.g1_irqs = 8,
3744
		.atu_move_port_mask = 0xf,
3745
		.multi_chip = true,
3746
		.tag_protocol = DSA_TAG_PROTO_DSA,
3747
		.ops = &mv88e6095_ops,
3748 3749
	},

3750
	[MV88E6097] = {
3751
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
3752 3753 3754 3755
		.family = MV88E6XXX_FAMILY_6097,
		.name = "Marvell 88E6097/88E6097F",
		.num_databases = 4096,
		.num_ports = 11,
3756
		.num_internal_phys = 8,
3757
		.max_vid = 4095,
3758
		.port_base_addr = 0x10,
3759
		.phy_base_addr = 0x0,
3760
		.global1_addr = 0x1b,
3761
		.global2_addr = 0x1c,
3762
		.age_time_coeff = 15000,
3763
		.g1_irqs = 8,
3764
		.g2_irqs = 10,
3765
		.atu_move_port_mask = 0xf,
3766
		.pvt = true,
3767
		.multi_chip = true,
3768
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3769 3770 3771
		.ops = &mv88e6097_ops,
	},

3772
	[MV88E6123] = {
3773
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
3774 3775 3776 3777
		.family = MV88E6XXX_FAMILY_6165,
		.name = "Marvell 88E6123",
		.num_databases = 4096,
		.num_ports = 3,
3778
		.num_internal_phys = 5,
3779
		.max_vid = 4095,
3780
		.port_base_addr = 0x10,
3781
		.phy_base_addr = 0x0,
3782
		.global1_addr = 0x1b,
3783
		.global2_addr = 0x1c,
3784
		.age_time_coeff = 15000,
3785
		.g1_irqs = 9,
3786
		.g2_irqs = 10,
3787
		.atu_move_port_mask = 0xf,
3788
		.pvt = true,
3789
		.multi_chip = true,
3790
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3791
		.ops = &mv88e6123_ops,
3792 3793 3794
	},

	[MV88E6131] = {
3795
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
3796 3797 3798 3799
		.family = MV88E6XXX_FAMILY_6185,
		.name = "Marvell 88E6131",
		.num_databases = 256,
		.num_ports = 8,
3800
		.num_internal_phys = 0,
3801
		.max_vid = 4095,
3802
		.port_base_addr = 0x10,
3803
		.phy_base_addr = 0x0,
3804
		.global1_addr = 0x1b,
3805
		.global2_addr = 0x1c,
3806
		.age_time_coeff = 15000,
3807
		.g1_irqs = 9,
3808
		.atu_move_port_mask = 0xf,
3809
		.multi_chip = true,
3810
		.tag_protocol = DSA_TAG_PROTO_DSA,
3811
		.ops = &mv88e6131_ops,
3812 3813
	},

3814
	[MV88E6141] = {
3815
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
3816
		.family = MV88E6XXX_FAMILY_6341,
3817
		.name = "Marvell 88E6141",
3818 3819
		.num_databases = 4096,
		.num_ports = 6,
3820
		.num_internal_phys = 5,
3821
		.num_gpio = 11,
3822
		.max_vid = 4095,
3823
		.port_base_addr = 0x10,
3824
		.phy_base_addr = 0x10,
3825
		.global1_addr = 0x1b,
3826
		.global2_addr = 0x1c,
3827 3828
		.age_time_coeff = 3750,
		.atu_move_port_mask = 0x1f,
3829
		.g1_irqs = 9,
3830
		.g2_irqs = 10,
3831
		.pvt = true,
3832
		.multi_chip = true,
3833 3834 3835 3836
		.tag_protocol = DSA_TAG_PROTO_EDSA,
		.ops = &mv88e6141_ops,
	},

3837
	[MV88E6161] = {
3838
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
3839 3840 3841 3842
		.family = MV88E6XXX_FAMILY_6165,
		.name = "Marvell 88E6161",
		.num_databases = 4096,
		.num_ports = 6,
3843
		.num_internal_phys = 5,
3844
		.max_vid = 4095,
3845
		.port_base_addr = 0x10,
3846
		.phy_base_addr = 0x0,
3847
		.global1_addr = 0x1b,
3848
		.global2_addr = 0x1c,
3849
		.age_time_coeff = 15000,
3850
		.g1_irqs = 9,
3851
		.g2_irqs = 10,
3852
		.atu_move_port_mask = 0xf,
3853
		.pvt = true,
3854
		.multi_chip = true,
3855
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3856
		.ptp_support = true,
3857
		.ops = &mv88e6161_ops,
3858 3859 3860
	},

	[MV88E6165] = {
3861
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
3862 3863 3864 3865
		.family = MV88E6XXX_FAMILY_6165,
		.name = "Marvell 88E6165",
		.num_databases = 4096,
		.num_ports = 6,
3866
		.num_internal_phys = 0,
3867
		.max_vid = 4095,
3868
		.port_base_addr = 0x10,
3869
		.phy_base_addr = 0x0,
3870
		.global1_addr = 0x1b,
3871
		.global2_addr = 0x1c,
3872
		.age_time_coeff = 15000,
3873
		.g1_irqs = 9,
3874
		.g2_irqs = 10,
3875
		.atu_move_port_mask = 0xf,
3876
		.pvt = true,
3877
		.multi_chip = true,
3878
		.tag_protocol = DSA_TAG_PROTO_DSA,
3879
		.ptp_support = true,
3880
		.ops = &mv88e6165_ops,
3881 3882 3883
	},

	[MV88E6171] = {
3884
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
3885 3886 3887 3888
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6171",
		.num_databases = 4096,
		.num_ports = 7,
3889
		.num_internal_phys = 5,
3890
		.max_vid = 4095,
3891
		.port_base_addr = 0x10,
3892
		.phy_base_addr = 0x0,
3893
		.global1_addr = 0x1b,
3894
		.global2_addr = 0x1c,
3895
		.age_time_coeff = 15000,
3896
		.g1_irqs = 9,
3897
		.g2_irqs = 10,
3898
		.atu_move_port_mask = 0xf,
3899
		.pvt = true,
3900
		.multi_chip = true,
3901
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3902
		.ops = &mv88e6171_ops,
3903 3904 3905
	},

	[MV88E6172] = {
3906
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
3907 3908 3909 3910
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6172",
		.num_databases = 4096,
		.num_ports = 7,
3911
		.num_internal_phys = 5,
3912
		.num_gpio = 15,
3913
		.max_vid = 4095,
3914
		.port_base_addr = 0x10,
3915
		.phy_base_addr = 0x0,
3916
		.global1_addr = 0x1b,
3917
		.global2_addr = 0x1c,
3918
		.age_time_coeff = 15000,
3919
		.g1_irqs = 9,
3920
		.g2_irqs = 10,
3921
		.atu_move_port_mask = 0xf,
3922
		.pvt = true,
3923
		.multi_chip = true,
3924
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3925
		.ops = &mv88e6172_ops,
3926 3927 3928
	},

	[MV88E6175] = {
3929
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
3930 3931 3932 3933
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6175",
		.num_databases = 4096,
		.num_ports = 7,
3934
		.num_internal_phys = 5,
3935
		.max_vid = 4095,
3936
		.port_base_addr = 0x10,
3937
		.phy_base_addr = 0x0,
3938
		.global1_addr = 0x1b,
3939
		.global2_addr = 0x1c,
3940
		.age_time_coeff = 15000,
3941
		.g1_irqs = 9,
3942
		.g2_irqs = 10,
3943
		.atu_move_port_mask = 0xf,
3944
		.pvt = true,
3945
		.multi_chip = true,
3946
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3947
		.ops = &mv88e6175_ops,
3948 3949 3950
	},

	[MV88E6176] = {
3951
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
3952 3953 3954 3955
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6176",
		.num_databases = 4096,
		.num_ports = 7,
3956
		.num_internal_phys = 5,
3957
		.num_gpio = 15,
3958
		.max_vid = 4095,
3959
		.port_base_addr = 0x10,
3960
		.phy_base_addr = 0x0,
3961
		.global1_addr = 0x1b,
3962
		.global2_addr = 0x1c,
3963
		.age_time_coeff = 15000,
3964
		.g1_irqs = 9,
3965
		.g2_irqs = 10,
3966
		.atu_move_port_mask = 0xf,
3967
		.pvt = true,
3968
		.multi_chip = true,
3969
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3970
		.ops = &mv88e6176_ops,
3971 3972 3973
	},

	[MV88E6185] = {
3974
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
3975 3976 3977 3978
		.family = MV88E6XXX_FAMILY_6185,
		.name = "Marvell 88E6185",
		.num_databases = 256,
		.num_ports = 10,
3979
		.num_internal_phys = 0,
3980
		.max_vid = 4095,
3981
		.port_base_addr = 0x10,
3982
		.phy_base_addr = 0x0,
3983
		.global1_addr = 0x1b,
3984
		.global2_addr = 0x1c,
3985
		.age_time_coeff = 15000,
3986
		.g1_irqs = 8,
3987
		.atu_move_port_mask = 0xf,
3988
		.multi_chip = true,
3989
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3990
		.ops = &mv88e6185_ops,
3991 3992
	},

3993
	[MV88E6190] = {
3994
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
3995 3996 3997 3998
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6190",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3999
		.num_internal_phys = 11,
4000
		.num_gpio = 16,
4001
		.max_vid = 8191,
4002
		.port_base_addr = 0x0,
4003
		.phy_base_addr = 0x0,
4004
		.global1_addr = 0x1b,
4005
		.global2_addr = 0x1c,
4006
		.tag_protocol = DSA_TAG_PROTO_DSA,
4007
		.age_time_coeff = 3750,
4008
		.g1_irqs = 9,
4009
		.g2_irqs = 14,
4010
		.pvt = true,
4011
		.multi_chip = true,
4012
		.atu_move_port_mask = 0x1f,
4013 4014 4015 4016
		.ops = &mv88e6190_ops,
	},

	[MV88E6190X] = {
4017
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
4018 4019 4020 4021
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6190X",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
4022
		.num_internal_phys = 11,
4023
		.num_gpio = 16,
4024
		.max_vid = 8191,
4025
		.port_base_addr = 0x0,
4026
		.phy_base_addr = 0x0,
4027
		.global1_addr = 0x1b,
4028
		.global2_addr = 0x1c,
4029
		.age_time_coeff = 3750,
4030
		.g1_irqs = 9,
4031
		.g2_irqs = 14,
4032
		.atu_move_port_mask = 0x1f,
4033
		.pvt = true,
4034
		.multi_chip = true,
4035
		.tag_protocol = DSA_TAG_PROTO_DSA,
4036 4037 4038 4039
		.ops = &mv88e6190x_ops,
	},

	[MV88E6191] = {
4040
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
4041 4042 4043 4044
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6191",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
4045
		.num_internal_phys = 11,
4046
		.max_vid = 8191,
4047
		.port_base_addr = 0x0,
4048
		.phy_base_addr = 0x0,
4049
		.global1_addr = 0x1b,
4050
		.global2_addr = 0x1c,
4051
		.age_time_coeff = 3750,
4052
		.g1_irqs = 9,
4053
		.g2_irqs = 14,
4054
		.atu_move_port_mask = 0x1f,
4055
		.pvt = true,
4056
		.multi_chip = true,
4057
		.tag_protocol = DSA_TAG_PROTO_DSA,
4058
		.ptp_support = true,
4059
		.ops = &mv88e6191_ops,
4060 4061
	},

4062
	[MV88E6240] = {
4063
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
4064 4065 4066 4067
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6240",
		.num_databases = 4096,
		.num_ports = 7,
4068
		.num_internal_phys = 5,
4069
		.num_gpio = 15,
4070
		.max_vid = 4095,
4071
		.port_base_addr = 0x10,
4072
		.phy_base_addr = 0x0,
4073
		.global1_addr = 0x1b,
4074
		.global2_addr = 0x1c,
4075
		.age_time_coeff = 15000,
4076
		.g1_irqs = 9,
4077
		.g2_irqs = 10,
4078
		.atu_move_port_mask = 0xf,
4079
		.pvt = true,
4080
		.multi_chip = true,
4081
		.tag_protocol = DSA_TAG_PROTO_EDSA,
4082
		.ptp_support = true,
4083
		.ops = &mv88e6240_ops,
4084 4085
	},

4086
	[MV88E6290] = {
4087
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
4088 4089 4090 4091
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6290",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
4092
		.num_internal_phys = 11,
4093
		.num_gpio = 16,
4094
		.max_vid = 8191,
4095
		.port_base_addr = 0x0,
4096
		.phy_base_addr = 0x0,
4097
		.global1_addr = 0x1b,
4098
		.global2_addr = 0x1c,
4099
		.age_time_coeff = 3750,
4100
		.g1_irqs = 9,
4101
		.g2_irqs = 14,
4102
		.atu_move_port_mask = 0x1f,
4103
		.pvt = true,
4104
		.multi_chip = true,
4105
		.tag_protocol = DSA_TAG_PROTO_DSA,
4106
		.ptp_support = true,
4107 4108 4109
		.ops = &mv88e6290_ops,
	},

4110
	[MV88E6320] = {
4111
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
4112 4113 4114 4115
		.family = MV88E6XXX_FAMILY_6320,
		.name = "Marvell 88E6320",
		.num_databases = 4096,
		.num_ports = 7,
4116
		.num_internal_phys = 5,
4117
		.num_gpio = 15,
4118
		.max_vid = 4095,
4119
		.port_base_addr = 0x10,
4120
		.phy_base_addr = 0x0,
4121
		.global1_addr = 0x1b,
4122
		.global2_addr = 0x1c,
4123
		.age_time_coeff = 15000,
4124
		.g1_irqs = 8,
4125
		.g2_irqs = 10,
4126
		.atu_move_port_mask = 0xf,
4127
		.pvt = true,
4128
		.multi_chip = true,
4129
		.tag_protocol = DSA_TAG_PROTO_EDSA,
4130
		.ptp_support = true,
4131
		.ops = &mv88e6320_ops,
4132 4133 4134
	},

	[MV88E6321] = {
4135
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
4136 4137 4138 4139
		.family = MV88E6XXX_FAMILY_6320,
		.name = "Marvell 88E6321",
		.num_databases = 4096,
		.num_ports = 7,
4140
		.num_internal_phys = 5,
4141
		.num_gpio = 15,
4142
		.max_vid = 4095,
4143
		.port_base_addr = 0x10,
4144
		.phy_base_addr = 0x0,
4145
		.global1_addr = 0x1b,
4146
		.global2_addr = 0x1c,
4147
		.age_time_coeff = 15000,
4148
		.g1_irqs = 8,
4149
		.g2_irqs = 10,
4150
		.atu_move_port_mask = 0xf,
4151
		.multi_chip = true,
4152
		.tag_protocol = DSA_TAG_PROTO_EDSA,
4153
		.ptp_support = true,
4154
		.ops = &mv88e6321_ops,
4155 4156
	},

4157
	[MV88E6341] = {
4158
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
4159 4160 4161
		.family = MV88E6XXX_FAMILY_6341,
		.name = "Marvell 88E6341",
		.num_databases = 4096,
4162
		.num_internal_phys = 5,
4163
		.num_ports = 6,
4164
		.num_gpio = 11,
4165
		.max_vid = 4095,
4166
		.port_base_addr = 0x10,
4167
		.phy_base_addr = 0x10,
4168
		.global1_addr = 0x1b,
4169
		.global2_addr = 0x1c,
4170
		.age_time_coeff = 3750,
4171
		.atu_move_port_mask = 0x1f,
4172
		.g1_irqs = 9,
4173
		.g2_irqs = 10,
4174
		.pvt = true,
4175
		.multi_chip = true,
4176
		.tag_protocol = DSA_TAG_PROTO_EDSA,
4177
		.ptp_support = true,
4178 4179 4180
		.ops = &mv88e6341_ops,
	},

4181
	[MV88E6350] = {
4182
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
4183 4184 4185 4186
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6350",
		.num_databases = 4096,
		.num_ports = 7,
4187
		.num_internal_phys = 5,
4188
		.max_vid = 4095,
4189
		.port_base_addr = 0x10,
4190
		.phy_base_addr = 0x0,
4191
		.global1_addr = 0x1b,
4192
		.global2_addr = 0x1c,
4193
		.age_time_coeff = 15000,
4194
		.g1_irqs = 9,
4195
		.g2_irqs = 10,
4196
		.atu_move_port_mask = 0xf,
4197
		.pvt = true,
4198
		.multi_chip = true,
4199
		.tag_protocol = DSA_TAG_PROTO_EDSA,
4200
		.ops = &mv88e6350_ops,
4201 4202 4203
	},

	[MV88E6351] = {
4204
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
4205 4206 4207 4208
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6351",
		.num_databases = 4096,
		.num_ports = 7,
4209
		.num_internal_phys = 5,
4210
		.max_vid = 4095,
4211
		.port_base_addr = 0x10,
4212
		.phy_base_addr = 0x0,
4213
		.global1_addr = 0x1b,
4214
		.global2_addr = 0x1c,
4215
		.age_time_coeff = 15000,
4216
		.g1_irqs = 9,
4217
		.g2_irqs = 10,
4218
		.atu_move_port_mask = 0xf,
4219
		.pvt = true,
4220
		.multi_chip = true,
4221
		.tag_protocol = DSA_TAG_PROTO_EDSA,
4222
		.ops = &mv88e6351_ops,
4223 4224 4225
	},

	[MV88E6352] = {
4226
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
4227 4228 4229 4230
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6352",
		.num_databases = 4096,
		.num_ports = 7,
4231
		.num_internal_phys = 5,
4232
		.num_gpio = 15,
4233
		.max_vid = 4095,
4234
		.port_base_addr = 0x10,
4235
		.phy_base_addr = 0x0,
4236
		.global1_addr = 0x1b,
4237
		.global2_addr = 0x1c,
4238
		.age_time_coeff = 15000,
4239
		.g1_irqs = 9,
4240
		.g2_irqs = 10,
4241
		.atu_move_port_mask = 0xf,
4242
		.pvt = true,
4243
		.multi_chip = true,
4244
		.tag_protocol = DSA_TAG_PROTO_EDSA,
4245
		.ptp_support = true,
4246
		.ops = &mv88e6352_ops,
4247
	},
4248
	[MV88E6390] = {
4249
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
4250 4251 4252 4253
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6390",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
4254
		.num_internal_phys = 11,
4255
		.num_gpio = 16,
4256
		.max_vid = 8191,
4257
		.port_base_addr = 0x0,
4258
		.phy_base_addr = 0x0,
4259
		.global1_addr = 0x1b,
4260
		.global2_addr = 0x1c,
4261
		.age_time_coeff = 3750,
4262
		.g1_irqs = 9,
4263
		.g2_irqs = 14,
4264
		.atu_move_port_mask = 0x1f,
4265
		.pvt = true,
4266
		.multi_chip = true,
4267
		.tag_protocol = DSA_TAG_PROTO_DSA,
4268
		.ptp_support = true,
4269 4270 4271
		.ops = &mv88e6390_ops,
	},
	[MV88E6390X] = {
4272
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
4273 4274 4275 4276
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6390X",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
4277
		.num_internal_phys = 11,
4278
		.num_gpio = 16,
4279
		.max_vid = 8191,
4280
		.port_base_addr = 0x0,
4281
		.phy_base_addr = 0x0,
4282
		.global1_addr = 0x1b,
4283
		.global2_addr = 0x1c,
4284
		.age_time_coeff = 3750,
4285
		.g1_irqs = 9,
4286
		.g2_irqs = 14,
4287
		.atu_move_port_mask = 0x1f,
4288
		.pvt = true,
4289
		.multi_chip = true,
4290
		.tag_protocol = DSA_TAG_PROTO_DSA,
4291
		.ptp_support = true,
4292 4293
		.ops = &mv88e6390x_ops,
	},
4294 4295
};

4296
static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
4297
{
4298
	int i;
4299

4300 4301 4302
	for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
		if (mv88e6xxx_table[i].prod_num == prod_num)
			return &mv88e6xxx_table[i];
4303 4304 4305 4306

	return NULL;
}

4307
static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
4308 4309
{
	const struct mv88e6xxx_info *info;
4310 4311 4312
	unsigned int prod_num, rev;
	u16 id;
	int err;
4313

4314
	mutex_lock(&chip->reg_lock);
4315
	err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
4316 4317 4318
	mutex_unlock(&chip->reg_lock);
	if (err)
		return err;
4319

4320 4321
	prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
	rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
4322 4323 4324 4325 4326

	info = mv88e6xxx_lookup_info(prod_num);
	if (!info)
		return -ENODEV;

4327
	/* Update the compatible info with the probed one */
4328
	chip->info = info;
4329

4330 4331 4332 4333
	err = mv88e6xxx_g2_require(chip);
	if (err)
		return err;

4334 4335
	dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
		 chip->info->prod_num, chip->info->name, rev);
4336 4337 4338 4339

	return 0;
}

4340
static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
4341
{
4342
	struct mv88e6xxx_chip *chip;
4343

4344 4345
	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
	if (!chip)
4346 4347
		return NULL;

4348
	chip->dev = dev;
4349

4350
	mutex_init(&chip->reg_lock);
4351
	INIT_LIST_HEAD(&chip->mdios);
4352

4353
	return chip;
4354 4355
}

4356
static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4357 4358
			      struct mii_bus *bus, int sw_addr)
{
4359
	if (sw_addr == 0)
4360
		chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
4361
	else if (chip->info->multi_chip)
4362
		chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
4363 4364 4365
	else
		return -EINVAL;

4366 4367
	chip->bus = bus;
	chip->sw_addr = sw_addr;
4368 4369 4370 4371

	return 0;
}

4372 4373
static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
							int port)
4374
{
V
Vivien Didelot 已提交
4375
	struct mv88e6xxx_chip *chip = ds->priv;
4376

4377
	return chip->info->tag_protocol;
4378 4379
}

4380
#if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
4381 4382 4383
static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
				       struct device *host_dev, int sw_addr,
				       void **priv)
4384
{
4385
	struct mv88e6xxx_chip *chip;
4386
	struct mii_bus *bus;
4387
	int err;
4388

4389
	bus = dsa_host_dev_to_mii_bus(host_dev);
4390 4391 4392
	if (!bus)
		return NULL;

4393 4394
	chip = mv88e6xxx_alloc_chip(dsa_dev);
	if (!chip)
4395 4396
		return NULL;

4397
	/* Legacy SMI probing will only support chips similar to 88E6085 */
4398
	chip->info = &mv88e6xxx_table[MV88E6085];
4399

4400
	err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4401 4402 4403
	if (err)
		goto free;

4404
	err = mv88e6xxx_detect(chip);
4405
	if (err)
4406
		goto free;
4407

4408 4409 4410 4411 4412 4413
	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_switch_reset(chip);
	mutex_unlock(&chip->reg_lock);
	if (err)
		goto free;

4414 4415
	mv88e6xxx_phy_init(chip);

4416
	err = mv88e6xxx_mdios_register(chip, NULL);
4417
	if (err)
4418
		goto free;
4419

4420
	*priv = chip;
4421

4422
	return chip->info->name;
4423
free:
4424
	devm_kfree(dsa_dev, chip);
4425 4426

	return NULL;
4427
}
4428
#endif
4429

4430
static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
4431
				      const struct switchdev_obj_port_mdb *mdb)
4432 4433 4434 4435 4436 4437 4438 4439 4440
{
	/* We don't need any dynamic resource from the kernel (yet),
	 * so skip the prepare phase.
	 */

	return 0;
}

static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
4441
				   const struct switchdev_obj_port_mdb *mdb)
4442
{
V
Vivien Didelot 已提交
4443
	struct mv88e6xxx_chip *chip = ds->priv;
4444 4445 4446

	mutex_lock(&chip->reg_lock);
	if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4447
					 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
4448 4449
		dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
			port);
4450 4451 4452 4453 4454 4455
	mutex_unlock(&chip->reg_lock);
}

static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
				  const struct switchdev_obj_port_mdb *mdb)
{
V
Vivien Didelot 已提交
4456
	struct mv88e6xxx_chip *chip = ds->priv;
4457 4458 4459 4460
	int err;

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4461
					   MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
4462 4463 4464 4465 4466
	mutex_unlock(&chip->reg_lock);

	return err;
}

4467
static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
4468
#if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
4469
	.probe			= mv88e6xxx_drv_probe,
4470
#endif
4471
	.get_tag_protocol	= mv88e6xxx_get_tag_protocol,
4472 4473
	.setup			= mv88e6xxx_setup,
	.adjust_link		= mv88e6xxx_adjust_link,
4474 4475 4476 4477 4478
	.phylink_validate	= mv88e6xxx_validate,
	.phylink_mac_link_state	= mv88e6xxx_link_state,
	.phylink_mac_config	= mv88e6xxx_mac_config,
	.phylink_mac_link_down	= mv88e6xxx_mac_link_down,
	.phylink_mac_link_up	= mv88e6xxx_mac_link_up,
4479 4480 4481
	.get_strings		= mv88e6xxx_get_strings,
	.get_ethtool_stats	= mv88e6xxx_get_ethtool_stats,
	.get_sset_count		= mv88e6xxx_get_sset_count,
4482 4483
	.port_enable		= mv88e6xxx_port_enable,
	.port_disable		= mv88e6xxx_port_disable,
V
Vivien Didelot 已提交
4484 4485
	.get_mac_eee		= mv88e6xxx_get_mac_eee,
	.set_mac_eee		= mv88e6xxx_set_mac_eee,
4486
	.get_eeprom_len		= mv88e6xxx_get_eeprom_len,
4487 4488 4489 4490
	.get_eeprom		= mv88e6xxx_get_eeprom,
	.set_eeprom		= mv88e6xxx_set_eeprom,
	.get_regs_len		= mv88e6xxx_get_regs_len,
	.get_regs		= mv88e6xxx_get_regs,
4491
	.set_ageing_time	= mv88e6xxx_set_ageing_time,
4492 4493 4494
	.port_bridge_join	= mv88e6xxx_port_bridge_join,
	.port_bridge_leave	= mv88e6xxx_port_bridge_leave,
	.port_stp_state_set	= mv88e6xxx_port_stp_state_set,
4495
	.port_fast_age		= mv88e6xxx_port_fast_age,
4496 4497 4498 4499 4500 4501 4502
	.port_vlan_filtering	= mv88e6xxx_port_vlan_filtering,
	.port_vlan_prepare	= mv88e6xxx_port_vlan_prepare,
	.port_vlan_add		= mv88e6xxx_port_vlan_add,
	.port_vlan_del		= mv88e6xxx_port_vlan_del,
	.port_fdb_add           = mv88e6xxx_port_fdb_add,
	.port_fdb_del           = mv88e6xxx_port_fdb_del,
	.port_fdb_dump          = mv88e6xxx_port_fdb_dump,
4503 4504 4505
	.port_mdb_prepare       = mv88e6xxx_port_mdb_prepare,
	.port_mdb_add           = mv88e6xxx_port_mdb_add,
	.port_mdb_del           = mv88e6xxx_port_mdb_del,
4506 4507
	.crosschip_bridge_join	= mv88e6xxx_crosschip_bridge_join,
	.crosschip_bridge_leave	= mv88e6xxx_crosschip_bridge_leave,
4508 4509 4510 4511 4512
	.port_hwtstamp_set	= mv88e6xxx_port_hwtstamp_set,
	.port_hwtstamp_get	= mv88e6xxx_port_hwtstamp_get,
	.port_txtstamp		= mv88e6xxx_port_txtstamp,
	.port_rxtstamp		= mv88e6xxx_port_rxtstamp,
	.get_ts_info		= mv88e6xxx_get_ts_info,
4513 4514
};

4515 4516 4517 4518
static struct dsa_switch_driver mv88e6xxx_switch_drv = {
	.ops			= &mv88e6xxx_switch_ops,
};

4519
static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
4520
{
4521
	struct device *dev = chip->dev;
4522 4523
	struct dsa_switch *ds;

4524
	ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip));
4525 4526 4527
	if (!ds)
		return -ENOMEM;

4528
	ds->priv = chip;
4529
	ds->dev = dev;
4530
	ds->ops = &mv88e6xxx_switch_ops;
4531 4532
	ds->ageing_time_min = chip->info->age_time_coeff;
	ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
4533 4534 4535

	dev_set_drvdata(dev, ds);

4536
	return dsa_register_switch(ds);
4537 4538
}

4539
static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
4540
{
4541
	dsa_unregister_switch(chip->ds);
4542 4543
}

4544 4545 4546 4547 4548 4549 4550 4551 4552 4553 4554 4555 4556
static const void *pdata_device_get_match_data(struct device *dev)
{
	const struct of_device_id *matches = dev->driver->of_match_table;
	const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;

	for (; matches->name[0] || matches->type[0] || matches->compatible[0];
	     matches++) {
		if (!strcmp(pdata->compatible, matches->compatible))
			return matches->data;
	}
	return NULL;
}

4557
static int mv88e6xxx_probe(struct mdio_device *mdiodev)
4558
{
4559
	struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
4560
	const struct mv88e6xxx_info *compat_info = NULL;
4561
	struct device *dev = &mdiodev->dev;
4562
	struct device_node *np = dev->of_node;
4563
	struct mv88e6xxx_chip *chip;
4564
	int port;
4565
	int err;
4566

4567 4568 4569
	if (!np && !pdata)
		return -EINVAL;

4570 4571 4572 4573 4574 4575 4576 4577 4578 4579 4580 4581 4582 4583 4584 4585 4586 4587 4588
	if (np)
		compat_info = of_device_get_match_data(dev);

	if (pdata) {
		compat_info = pdata_device_get_match_data(dev);

		if (!pdata->netdev)
			return -EINVAL;

		for (port = 0; port < DSA_MAX_PORTS; port++) {
			if (!(pdata->enabled_ports & (1 << port)))
				continue;
			if (strcmp(pdata->cd.port_names[port], "cpu"))
				continue;
			pdata->cd.netdev[port] = &pdata->netdev->dev;
			break;
		}
	}

4589 4590 4591
	if (!compat_info)
		return -EINVAL;

4592
	chip = mv88e6xxx_alloc_chip(dev);
4593 4594 4595 4596
	if (!chip) {
		err = -ENOMEM;
		goto out;
	}
4597

4598
	chip->info = compat_info;
4599

4600
	err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4601
	if (err)
4602
		goto out;
4603

4604
	chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4605 4606 4607 4608
	if (IS_ERR(chip->reset)) {
		err = PTR_ERR(chip->reset);
		goto out;
	}
4609

4610
	err = mv88e6xxx_detect(chip);
4611
	if (err)
4612
		goto out;
4613

4614 4615
	mv88e6xxx_phy_init(chip);

4616 4617 4618 4619 4620 4621 4622
	if (chip->info->ops->get_eeprom) {
		if (np)
			of_property_read_u32(np, "eeprom-length",
					     &chip->eeprom_len);
		else
			chip->eeprom_len = pdata->eeprom_len;
	}
4623

4624 4625 4626 4627 4628 4629 4630 4631 4632 4633 4634 4635
	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_switch_reset(chip);
	mutex_unlock(&chip->reg_lock);
	if (err)
		goto out;

	chip->irq = of_irq_get(np, 0);
	if (chip->irq == -EPROBE_DEFER) {
		err = chip->irq;
		goto out;
	}

4636
	/* Has to be performed before the MDIO bus is created, because
4637
	 * the PHYs will link their interrupts to these interrupt
4638 4639 4640 4641
	 * controllers
	 */
	mutex_lock(&chip->reg_lock);
	if (chip->irq > 0)
4642
		err = mv88e6xxx_g1_irq_setup(chip);
4643 4644 4645
	else
		err = mv88e6xxx_irq_poll_setup(chip);
	mutex_unlock(&chip->reg_lock);
4646

4647 4648
	if (err)
		goto out;
4649

4650 4651
	if (chip->info->g2_irqs > 0) {
		err = mv88e6xxx_g2_irq_setup(chip);
4652
		if (err)
4653
			goto out_g1_irq;
4654 4655
	}

4656 4657 4658 4659 4660 4661 4662 4663
	err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
	if (err)
		goto out_g2_irq;

	err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
	if (err)
		goto out_g1_atu_prob_irq;

4664
	err = mv88e6xxx_mdios_register(chip, np);
4665
	if (err)
4666
		goto out_g1_vtu_prob_irq;
4667

4668
	err = mv88e6xxx_register_switch(chip);
4669 4670
	if (err)
		goto out_mdio;
4671

4672
	return 0;
4673 4674

out_mdio:
4675
	mv88e6xxx_mdios_unregister(chip);
4676
out_g1_vtu_prob_irq:
4677
	mv88e6xxx_g1_vtu_prob_irq_free(chip);
4678
out_g1_atu_prob_irq:
4679
	mv88e6xxx_g1_atu_prob_irq_free(chip);
4680
out_g2_irq:
4681
	if (chip->info->g2_irqs > 0)
4682 4683
		mv88e6xxx_g2_irq_free(chip);
out_g1_irq:
4684
	if (chip->irq > 0)
4685
		mv88e6xxx_g1_irq_free(chip);
4686 4687
	else
		mv88e6xxx_irq_poll_free(chip);
4688
out:
4689 4690 4691
	if (pdata)
		dev_put(pdata->netdev);

4692
	return err;
4693
}
4694 4695 4696 4697

static void mv88e6xxx_remove(struct mdio_device *mdiodev)
{
	struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
V
Vivien Didelot 已提交
4698
	struct mv88e6xxx_chip *chip = ds->priv;
4699

4700 4701
	if (chip->info->ptp_support) {
		mv88e6xxx_hwtstamp_free(chip);
4702
		mv88e6xxx_ptp_free(chip);
4703
	}
4704

4705
	mv88e6xxx_phy_destroy(chip);
4706
	mv88e6xxx_unregister_switch(chip);
4707
	mv88e6xxx_mdios_unregister(chip);
4708

4709 4710 4711 4712 4713 4714 4715
	mv88e6xxx_g1_vtu_prob_irq_free(chip);
	mv88e6xxx_g1_atu_prob_irq_free(chip);

	if (chip->info->g2_irqs > 0)
		mv88e6xxx_g2_irq_free(chip);

	if (chip->irq > 0)
4716
		mv88e6xxx_g1_irq_free(chip);
4717 4718
	else
		mv88e6xxx_irq_poll_free(chip);
4719 4720 4721
}

static const struct of_device_id mv88e6xxx_of_match[] = {
4722 4723 4724 4725
	{
		.compatible = "marvell,mv88e6085",
		.data = &mv88e6xxx_table[MV88E6085],
	},
4726 4727 4728 4729
	{
		.compatible = "marvell,mv88e6190",
		.data = &mv88e6xxx_table[MV88E6190],
	},
4730 4731 4732 4733 4734 4735 4736 4737 4738 4739 4740 4741 4742 4743 4744 4745
	{ /* sentinel */ },
};

MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);

static struct mdio_driver mv88e6xxx_driver = {
	.probe	= mv88e6xxx_probe,
	.remove = mv88e6xxx_remove,
	.mdiodrv.driver = {
		.name = "mv88e6085",
		.of_match_table = mv88e6xxx_of_match,
	},
};

static int __init mv88e6xxx_init(void)
{
4746
	register_switch_driver(&mv88e6xxx_switch_drv);
4747 4748
	return mdio_driver_register(&mv88e6xxx_driver);
}
4749 4750 4751 4752
module_init(mv88e6xxx_init);

static void __exit mv88e6xxx_cleanup(void)
{
4753
	mdio_driver_unregister(&mv88e6xxx_driver);
4754
	unregister_switch_driver(&mv88e6xxx_switch_drv);
4755 4756
}
module_exit(mv88e6xxx_cleanup);
4757 4758 4759 4760

MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
MODULE_LICENSE("GPL");