chip.c 113.8 KB
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/*
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 * Marvell 88e6xxx Ethernet switch single-chip support
 *
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 * Copyright (c) 2008 Marvell Semiconductor
 *
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 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
 *
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 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
 *	Vivien Didelot <vivien.didelot@savoirfairelinux.com>
 *
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 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

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#include <linux/delay.h>
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#include <linux/etherdevice.h>
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#include <linux/ethtool.h>
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#include <linux/if_bridge.h>
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#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
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#include <linux/jiffies.h>
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#include <linux/list.h>
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#include <linux/mdio.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/of_mdio.h>
31
#include <linux/netdevice.h>
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#include <linux/gpio/consumer.h>
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#include <linux/phy.h>
34
#include <net/dsa.h>
35

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#include "chip.h"
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#include "global1.h"
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#include "global2.h"
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#include "phy.h"
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#include "port.h"
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#include "serdes.h"
42

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static void assert_reg_lock(struct mv88e6xxx_chip *chip)
44
{
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	if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
		dev_err(chip->dev, "Switch registers lock not held!\n");
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		dump_stack();
	}
}

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/* The switch ADDR[4:1] configuration pins define the chip SMI device address
 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
 *
 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
 * is the only device connected to the SMI master. In this mode it responds to
 * all 32 possible SMI addresses, and thus maps directly the internal devices.
 *
 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
 * multiple devices to share the SMI interface. In this mode it responds to only
 * 2 registers, used to indirectly access the internal SMI devices.
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 */
62

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static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
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			      int addr, int reg, u16 *val)
{
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	if (!chip->smi_ops)
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		return -EOPNOTSUPP;

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	return chip->smi_ops->read(chip, addr, reg, val);
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}

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static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
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			       int addr, int reg, u16 val)
{
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	if (!chip->smi_ops)
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		return -EOPNOTSUPP;

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	return chip->smi_ops->write(chip, addr, reg, val);
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}

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static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
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					  int addr, int reg, u16 *val)
{
	int ret;

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	ret = mdiobus_read_nested(chip->bus, addr, reg);
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	if (ret < 0)
		return ret;

	*val = ret & 0xffff;

	return 0;
}

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static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
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					   int addr, int reg, u16 val)
{
	int ret;

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	ret = mdiobus_write_nested(chip->bus, addr, reg, val);
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	if (ret < 0)
		return ret;

	return 0;
}

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static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
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	.read = mv88e6xxx_smi_single_chip_read,
	.write = mv88e6xxx_smi_single_chip_write,
};

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static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
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{
	int ret;
	int i;

	for (i = 0; i < 16; i++) {
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		ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
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		if (ret < 0)
			return ret;

122
		if ((ret & SMI_CMD_BUSY) == 0)
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			return 0;
	}

	return -ETIMEDOUT;
}

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static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
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					 int addr, int reg, u16 *val)
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{
	int ret;

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	/* Wait for the bus to become free. */
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	ret = mv88e6xxx_smi_multi_chip_wait(chip);
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	if (ret < 0)
		return ret;

139
	/* Transmit the read command. */
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	ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
141
				   SMI_CMD_OP_22_READ | (addr << 5) | reg);
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	if (ret < 0)
		return ret;

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	/* Wait for the read command to complete. */
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	ret = mv88e6xxx_smi_multi_chip_wait(chip);
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	if (ret < 0)
		return ret;

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	/* Read the data. */
151
	ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
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	if (ret < 0)
		return ret;

155
	*val = ret & 0xffff;
156

157
	return 0;
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}

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static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
161
					  int addr, int reg, u16 val)
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{
	int ret;

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	/* Wait for the bus to become free. */
166
	ret = mv88e6xxx_smi_multi_chip_wait(chip);
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	if (ret < 0)
		return ret;

170
	/* Transmit the data to write. */
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	ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
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	if (ret < 0)
		return ret;

175
	/* Transmit the write command. */
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	ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
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				   SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
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	if (ret < 0)
		return ret;

181
	/* Wait for the write command to complete. */
182
	ret = mv88e6xxx_smi_multi_chip_wait(chip);
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	if (ret < 0)
		return ret;

	return 0;
}

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static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
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	.read = mv88e6xxx_smi_multi_chip_read,
	.write = mv88e6xxx_smi_multi_chip_write,
};

194
int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
195 196 197
{
	int err;

198
	assert_reg_lock(chip);
199

200
	err = mv88e6xxx_smi_read(chip, addr, reg, val);
201 202 203
	if (err)
		return err;

204
	dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
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		addr, reg, *val);

	return 0;
}

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int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
211
{
212 213
	int err;

214
	assert_reg_lock(chip);
215

216
	err = mv88e6xxx_smi_write(chip, addr, reg, val);
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	if (err)
		return err;

220
	dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
221 222
		addr, reg, val);

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	return 0;
}

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struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
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{
	struct mv88e6xxx_mdio_bus *mdio_bus;

	mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
				    list);
	if (!mdio_bus)
		return NULL;

	return mdio_bus->bus;
}

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static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
{
	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int n = d->hwirq;

	chip->g1_irq.masked |= (1 << n);
}

static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
{
	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int n = d->hwirq;

	chip->g1_irq.masked &= ~(1 << n);
}

static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
{
	struct mv88e6xxx_chip *chip = dev_id;
	unsigned int nhandled = 0;
	unsigned int sub_irq;
	unsigned int n;
	u16 reg;
	int err;

	mutex_lock(&chip->reg_lock);
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	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
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	mutex_unlock(&chip->reg_lock);

	if (err)
		goto out;

	for (n = 0; n < chip->g1_irq.nirqs; ++n) {
		if (reg & (1 << n)) {
			sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
			handle_nested_irq(sub_irq);
			++nhandled;
		}
	}
out:
	return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
}

static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
{
	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);

	mutex_lock(&chip->reg_lock);
}

static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
{
	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
	u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
	u16 reg;
	int err;

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	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
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	if (err)
		goto out;

	reg &= ~mask;
	reg |= (~chip->g1_irq.masked & mask);

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	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
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	if (err)
		goto out;

out:
	mutex_unlock(&chip->reg_lock);
}

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static const struct irq_chip mv88e6xxx_g1_irq_chip = {
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	.name			= "mv88e6xxx-g1",
	.irq_mask		= mv88e6xxx_g1_irq_mask,
	.irq_unmask		= mv88e6xxx_g1_irq_unmask,
	.irq_bus_lock		= mv88e6xxx_g1_irq_bus_lock,
	.irq_bus_sync_unlock	= mv88e6xxx_g1_irq_bus_sync_unlock,
};

static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
				       unsigned int irq,
				       irq_hw_number_t hwirq)
{
	struct mv88e6xxx_chip *chip = d->host_data;

	irq_set_chip_data(irq, d->host_data);
	irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
	irq_set_noprobe(irq);

	return 0;
}

static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
	.map	= mv88e6xxx_g1_irq_domain_map,
	.xlate	= irq_domain_xlate_twocell,
};

static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
{
	int irq, virq;
339 340
	u16 mask;

341
	mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
342
	mask |= GENMASK(chip->g1_irq.nirqs, 0);
343
	mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
344 345

	free_irq(chip->irq, chip);
346

347
	for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
348
		virq = irq_find_mapping(chip->g1_irq.domain, irq);
349 350 351
		irq_dispose_mapping(virq);
	}

352
	irq_domain_remove(chip->g1_irq.domain);
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}

static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
{
357 358
	int err, irq, virq;
	u16 reg, mask;
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	chip->g1_irq.nirqs = chip->info->g1_irqs;
	chip->g1_irq.domain = irq_domain_add_simple(
		NULL, chip->g1_irq.nirqs, 0,
		&mv88e6xxx_g1_irq_domain_ops, chip);
	if (!chip->g1_irq.domain)
		return -ENOMEM;

	for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
		irq_create_mapping(chip->g1_irq.domain, irq);

	chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
	chip->g1_irq.masked = ~0;

373
	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
374
	if (err)
375
		goto out_mapping;
376

377
	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
378

379
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
380
	if (err)
381
		goto out_disable;
382 383

	/* Reading the interrupt status clears (most of) them */
384
	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
385
	if (err)
386
		goto out_disable;
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	err = request_threaded_irq(chip->irq, NULL,
				   mv88e6xxx_g1_irq_thread_fn,
				   IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
				   dev_name(chip->dev), chip);
	if (err)
393
		goto out_disable;
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	return 0;

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out_disable:
	mask |= GENMASK(chip->g1_irq.nirqs, 0);
399
	mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
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out_mapping:
	for (irq = 0; irq < 16; irq++) {
		virq = irq_find_mapping(chip->g1_irq.domain, irq);
		irq_dispose_mapping(virq);
	}

	irq_domain_remove(chip->g1_irq.domain);
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	return err;
}

412
int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
413
{
414
	int i;
415

416
	for (i = 0; i < 16; i++) {
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		u16 val;
		int err;

		err = mv88e6xxx_read(chip, addr, reg, &val);
		if (err)
			return err;

		if (!(val & mask))
			return 0;

		usleep_range(1000, 2000);
	}

430
	dev_err(chip->dev, "Timeout while waiting for switch\n");
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	return -ETIMEDOUT;
}

434
/* Indirect write to single pointer-data register with an Update bit */
435
int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
436 437
{
	u16 val;
438
	int err;
439 440

	/* Wait until the previous operation is completed */
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	err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
	if (err)
		return err;
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	/* Set the Update bit to trigger a write operation */
	val = BIT(15) | update;

	return mv88e6xxx_write(chip, addr, reg, val);
}

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static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
				    int link, int speed, int duplex,
				    phy_interface_t mode)
{
	int err;

	if (!chip->info->ops->port_set_link)
		return 0;

	/* Port's MAC control must not be changed unless the link is down */
	err = chip->info->ops->port_set_link(chip, port, 0);
	if (err)
		return err;

	if (chip->info->ops->port_set_speed) {
		err = chip->info->ops->port_set_speed(chip, port, speed);
		if (err && err != -EOPNOTSUPP)
			goto restore_link;
	}

	if (chip->info->ops->port_set_duplex) {
		err = chip->info->ops->port_set_duplex(chip, port, duplex);
		if (err && err != -EOPNOTSUPP)
			goto restore_link;
	}

	if (chip->info->ops->port_set_rgmii_delay) {
		err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
		if (err && err != -EOPNOTSUPP)
			goto restore_link;
	}

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	if (chip->info->ops->port_set_cmode) {
		err = chip->info->ops->port_set_cmode(chip, port, mode);
		if (err && err != -EOPNOTSUPP)
			goto restore_link;
	}

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	err = 0;
restore_link:
	if (chip->info->ops->port_set_link(chip, port, link))
492
		dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
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	return err;
}

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/* We expect the switch to perform auto negotiation if there is a real
 * phy. However, in the case of a fixed link phy, we force the port
 * settings from the fixed link settings.
 */
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static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
				  struct phy_device *phydev)
503
{
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	struct mv88e6xxx_chip *chip = ds->priv;
505
	int err;
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	if (!phy_is_pseudo_fixed_link(phydev))
		return;

510
	mutex_lock(&chip->reg_lock);
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	err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
				       phydev->duplex, phydev->interface);
513
	mutex_unlock(&chip->reg_lock);
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	if (err && err != -EOPNOTSUPP)
516
		dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
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}

519
static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
520
{
521 522
	if (!chip->info->ops->stats_snapshot)
		return -EOPNOTSUPP;
523

524
	return chip->info->ops->stats_snapshot(chip, port);
525 526
}

527
static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
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	{ "in_good_octets",		8, 0x00, STATS_TYPE_BANK0, },
	{ "in_bad_octets",		4, 0x02, STATS_TYPE_BANK0, },
	{ "in_unicast",			4, 0x04, STATS_TYPE_BANK0, },
	{ "in_broadcasts",		4, 0x06, STATS_TYPE_BANK0, },
	{ "in_multicasts",		4, 0x07, STATS_TYPE_BANK0, },
	{ "in_pause",			4, 0x16, STATS_TYPE_BANK0, },
	{ "in_undersize",		4, 0x18, STATS_TYPE_BANK0, },
	{ "in_fragments",		4, 0x19, STATS_TYPE_BANK0, },
	{ "in_oversize",		4, 0x1a, STATS_TYPE_BANK0, },
	{ "in_jabber",			4, 0x1b, STATS_TYPE_BANK0, },
	{ "in_rx_error",		4, 0x1c, STATS_TYPE_BANK0, },
	{ "in_fcs_error",		4, 0x1d, STATS_TYPE_BANK0, },
	{ "out_octets",			8, 0x0e, STATS_TYPE_BANK0, },
	{ "out_unicast",		4, 0x10, STATS_TYPE_BANK0, },
	{ "out_broadcasts",		4, 0x13, STATS_TYPE_BANK0, },
	{ "out_multicasts",		4, 0x12, STATS_TYPE_BANK0, },
	{ "out_pause",			4, 0x15, STATS_TYPE_BANK0, },
	{ "excessive",			4, 0x11, STATS_TYPE_BANK0, },
	{ "collisions",			4, 0x1e, STATS_TYPE_BANK0, },
	{ "deferred",			4, 0x05, STATS_TYPE_BANK0, },
	{ "single",			4, 0x14, STATS_TYPE_BANK0, },
	{ "multiple",			4, 0x17, STATS_TYPE_BANK0, },
	{ "out_fcs_error",		4, 0x03, STATS_TYPE_BANK0, },
	{ "late",			4, 0x1f, STATS_TYPE_BANK0, },
	{ "hist_64bytes",		4, 0x08, STATS_TYPE_BANK0, },
	{ "hist_65_127bytes",		4, 0x09, STATS_TYPE_BANK0, },
	{ "hist_128_255bytes",		4, 0x0a, STATS_TYPE_BANK0, },
	{ "hist_256_511bytes",		4, 0x0b, STATS_TYPE_BANK0, },
	{ "hist_512_1023bytes",		4, 0x0c, STATS_TYPE_BANK0, },
	{ "hist_1024_max_bytes",	4, 0x0d, STATS_TYPE_BANK0, },
	{ "sw_in_discards",		4, 0x10, STATS_TYPE_PORT, },
	{ "sw_in_filtered",		2, 0x12, STATS_TYPE_PORT, },
	{ "sw_out_filtered",		2, 0x13, STATS_TYPE_PORT, },
	{ "in_discards",		4, 0x00, STATS_TYPE_BANK1, },
	{ "in_filtered",		4, 0x01, STATS_TYPE_BANK1, },
	{ "in_accepted",		4, 0x02, STATS_TYPE_BANK1, },
	{ "in_bad_accepted",		4, 0x03, STATS_TYPE_BANK1, },
	{ "in_good_avb_class_a",	4, 0x04, STATS_TYPE_BANK1, },
	{ "in_good_avb_class_b",	4, 0x05, STATS_TYPE_BANK1, },
	{ "in_bad_avb_class_a",		4, 0x06, STATS_TYPE_BANK1, },
	{ "in_bad_avb_class_b",		4, 0x07, STATS_TYPE_BANK1, },
	{ "tcam_counter_0",		4, 0x08, STATS_TYPE_BANK1, },
	{ "tcam_counter_1",		4, 0x09, STATS_TYPE_BANK1, },
	{ "tcam_counter_2",		4, 0x0a, STATS_TYPE_BANK1, },
	{ "tcam_counter_3",		4, 0x0b, STATS_TYPE_BANK1, },
	{ "in_da_unknown",		4, 0x0e, STATS_TYPE_BANK1, },
	{ "in_management",		4, 0x0f, STATS_TYPE_BANK1, },
	{ "out_queue_0",		4, 0x10, STATS_TYPE_BANK1, },
	{ "out_queue_1",		4, 0x11, STATS_TYPE_BANK1, },
	{ "out_queue_2",		4, 0x12, STATS_TYPE_BANK1, },
	{ "out_queue_3",		4, 0x13, STATS_TYPE_BANK1, },
	{ "out_queue_4",		4, 0x14, STATS_TYPE_BANK1, },
	{ "out_queue_5",		4, 0x15, STATS_TYPE_BANK1, },
	{ "out_queue_6",		4, 0x16, STATS_TYPE_BANK1, },
	{ "out_queue_7",		4, 0x17, STATS_TYPE_BANK1, },
	{ "out_cut_through",		4, 0x18, STATS_TYPE_BANK1, },
	{ "out_octets_a",		4, 0x1a, STATS_TYPE_BANK1, },
	{ "out_octets_b",		4, 0x1b, STATS_TYPE_BANK1, },
	{ "out_management",		4, 0x1f, STATS_TYPE_BANK1, },
587 588
};

589
static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
590
					    struct mv88e6xxx_hw_stat *s,
591 592
					    int port, u16 bank1_select,
					    u16 histogram)
593 594 595
{
	u32 low;
	u32 high = 0;
596
	u16 reg = 0;
597
	int err;
598 599
	u64 value;

600
	switch (s->type) {
601
	case STATS_TYPE_PORT:
602 603
		err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
		if (err)
604 605
			return UINT64_MAX;

606
		low = reg;
607
		if (s->sizeof_stat == 4) {
608 609
			err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
			if (err)
610
				return UINT64_MAX;
611
			high = reg;
612
		}
613
		break;
614
	case STATS_TYPE_BANK1:
615
		reg = bank1_select;
616 617
		/* fall through */
	case STATS_TYPE_BANK0:
618
		reg |= s->reg | histogram;
619
		mv88e6xxx_g1_stats_read(chip, reg, &low);
620
		if (s->sizeof_stat == 8)
621
			mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
622 623 624
		break;
	default:
		return UINT64_MAX;
625 626 627 628 629
	}
	value = (((u64)high) << 16) | low;
	return value;
}

630 631
static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
					uint8_t *data, int types)
632
{
633 634
	struct mv88e6xxx_hw_stat *stat;
	int i, j;
635

636 637
	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
		stat = &mv88e6xxx_hw_stats[i];
638
		if (stat->type & types) {
639 640 641 642
			memcpy(data + j * ETH_GSTRING_LEN, stat->string,
			       ETH_GSTRING_LEN);
			j++;
		}
643
	}
644 645
}

646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661
static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
					uint8_t *data)
{
	mv88e6xxx_stats_get_strings(chip, data,
				    STATS_TYPE_BANK0 | STATS_TYPE_PORT);
}

static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
					uint8_t *data)
{
	mv88e6xxx_stats_get_strings(chip, data,
				    STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
}

static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
				  uint8_t *data)
662
{
V
Vivien Didelot 已提交
663
	struct mv88e6xxx_chip *chip = ds->priv;
664 665 666 667 668 669 670 671

	if (chip->info->ops->stats_get_strings)
		chip->info->ops->stats_get_strings(chip, data);
}

static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
					  int types)
{
672 673 674 675 676
	struct mv88e6xxx_hw_stat *stat;
	int i, j;

	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
		stat = &mv88e6xxx_hw_stats[i];
677
		if (stat->type & types)
678 679 680
			j++;
	}
	return j;
681 682
}

683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704
static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
{
	return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
					      STATS_TYPE_PORT);
}

static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
{
	return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
					      STATS_TYPE_BANK1);
}

static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
{
	struct mv88e6xxx_chip *chip = ds->priv;

	if (chip->info->ops->stats_get_sset_count)
		return chip->info->ops->stats_get_sset_count(chip);

	return 0;
}

705
static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
706 707
				      uint64_t *data, int types,
				      u16 bank1_select, u16 histogram)
708 709 710 711 712 713 714
{
	struct mv88e6xxx_hw_stat *stat;
	int i, j;

	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
		stat = &mv88e6xxx_hw_stats[i];
		if (stat->type & types) {
715 716 717
			data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
							      bank1_select,
							      histogram);
718 719 720 721 722 723 724 725 726
			j++;
		}
	}
}

static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
				      uint64_t *data)
{
	return mv88e6xxx_stats_get_stats(chip, port, data,
727
					 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
728
					 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
729 730 731 732 733 734
}

static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
				      uint64_t *data)
{
	return mv88e6xxx_stats_get_stats(chip, port, data,
735
					 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
736 737
					 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
					 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
738 739 740 741 742 743 744
}

static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
				      uint64_t *data)
{
	return mv88e6xxx_stats_get_stats(chip, port, data,
					 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
745 746
					 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
					 0);
747 748 749 750 751 752 753 754 755
}

static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
				uint64_t *data)
{
	if (chip->info->ops->stats_get_stats)
		chip->info->ops->stats_get_stats(chip, port, data);
}

756 757
static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
					uint64_t *data)
758
{
V
Vivien Didelot 已提交
759
	struct mv88e6xxx_chip *chip = ds->priv;
760 761
	int ret;

762
	mutex_lock(&chip->reg_lock);
763

764
	ret = mv88e6xxx_stats_snapshot(chip, port);
765
	if (ret < 0) {
766
		mutex_unlock(&chip->reg_lock);
767 768
		return;
	}
769 770

	mv88e6xxx_get_stats(chip, port, data);
771

772
	mutex_unlock(&chip->reg_lock);
773 774
}

775 776 777 778 779 780 781 782
static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->stats_set_histogram)
		return chip->info->ops->stats_set_histogram(chip);

	return 0;
}

783
static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
784 785 786 787
{
	return 32 * sizeof(u16);
}

788 789
static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
			       struct ethtool_regs *regs, void *_p)
790
{
V
Vivien Didelot 已提交
791
	struct mv88e6xxx_chip *chip = ds->priv;
792 793
	int err;
	u16 reg;
794 795 796 797 798 799 800
	u16 *p = _p;
	int i;

	regs->version = 0;

	memset(p, 0xff, 32 * sizeof(u16));

801
	mutex_lock(&chip->reg_lock);
802

803 804
	for (i = 0; i < 32; i++) {

805 806 807
		err = mv88e6xxx_port_read(chip, port, i, &reg);
		if (!err)
			p[i] = reg;
808
	}
809

810
	mutex_unlock(&chip->reg_lock);
811 812
}

V
Vivien Didelot 已提交
813 814
static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
				 struct ethtool_eee *e)
815
{
816 817
	/* Nothing to do on the port's MAC */
	return 0;
818 819
}

V
Vivien Didelot 已提交
820 821
static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
				 struct ethtool_eee *e)
822
{
823 824
	/* Nothing to do on the port's MAC */
	return 0;
825 826
}

827
static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
828
{
829 830 831
	struct dsa_switch *ds = NULL;
	struct net_device *br;
	u16 pvlan;
832 833
	int i;

834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853
	if (dev < DSA_MAX_SWITCHES)
		ds = chip->ds->dst->ds[dev];

	/* Prevent frames from unknown switch or port */
	if (!ds || port >= ds->num_ports)
		return 0;

	/* Frames from DSA links and CPU ports can egress any local port */
	if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
		return mv88e6xxx_port_mask(chip);

	br = ds->ports[port].bridge_dev;
	pvlan = 0;

	/* Frames from user ports can egress any local DSA links and CPU ports,
	 * as well as any local member of their bridge group.
	 */
	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
		if (dsa_is_cpu_port(chip->ds, i) ||
		    dsa_is_dsa_port(chip->ds, i) ||
V
Vivien Didelot 已提交
854
		    (br && dsa_to_port(chip->ds, i)->bridge_dev == br))
855 856 857 858 859
			pvlan |= BIT(i);

	return pvlan;
}

860
static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
861 862
{
	u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
863 864 865

	/* prevent frames from going back out of the port they came in on */
	output_ports &= ~BIT(port);
866

867
	return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
868 869
}

870 871
static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
					 u8 state)
872
{
V
Vivien Didelot 已提交
873
	struct mv88e6xxx_chip *chip = ds->priv;
874
	int err;
875

876
	mutex_lock(&chip->reg_lock);
877
	err = mv88e6xxx_port_set_state(chip, port, state);
878
	mutex_unlock(&chip->reg_lock);
879 880

	if (err)
881
		dev_err(ds->dev, "p%d: failed to update state\n", port);
882 883
}

884 885 886 887 888 889 890 891
static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->pot_clear)
		return chip->info->ops->pot_clear(chip);

	return 0;
}

892 893 894 895 896 897 898 899
static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->mgmt_rsvd2cpu)
		return chip->info->ops->mgmt_rsvd2cpu(chip);

	return 0;
}

900 901
static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
{
902 903
	int err;

904 905 906 907
	err = mv88e6xxx_g1_atu_flush(chip, 0, true);
	if (err)
		return err;

908 909 910 911
	err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
	if (err)
		return err;

912 913 914
	return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
}

915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934
static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
{
	int port;
	int err;

	if (!chip->info->ops->irl_init_all)
		return 0;

	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
		/* Disable ingress rate limiting by resetting all per port
		 * ingress rate limit resources to their initial state.
		 */
		err = chip->info->ops->irl_init_all(chip, port);
		if (err)
			return err;
	}

	return 0;
}

935 936 937 938 939 940 941 942 943 944 945 946 947
static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->set_switch_mac) {
		u8 addr[ETH_ALEN];

		eth_random_addr(addr);

		return chip->info->ops->set_switch_mac(chip, addr);
	}

	return 0;
}

948 949 950 951 952 953 954 955 956
static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
{
	u16 pvlan = 0;

	if (!mv88e6xxx_has_pvt(chip))
		return -EOPNOTSUPP;

	/* Skip the local source device, which uses in-chip port VLAN */
	if (dev != chip->ds->index)
957
		pvlan = mv88e6xxx_port_vlan(chip, dev, port);
958 959 960 961

	return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
}

962 963
static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
{
964 965 966
	int dev, port;
	int err;

967 968 969 970 971 972
	if (!mv88e6xxx_has_pvt(chip))
		return 0;

	/* Clear 5 Bit Port for usage with Marvell Link Street devices:
	 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
	 */
973 974 975 976 977 978 979 980 981 982 983 984 985
	err = mv88e6xxx_g2_misc_4_bit_port(chip);
	if (err)
		return err;

	for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
		for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
			err = mv88e6xxx_pvt_map(chip, dev, port);
			if (err)
				return err;
		}
	}

	return 0;
986 987
}

988 989 990 991 992 993
static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int err;

	mutex_lock(&chip->reg_lock);
994
	err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
995 996 997
	mutex_unlock(&chip->reg_lock);

	if (err)
998
		dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
999 1000
}

1001 1002 1003 1004 1005 1006 1007 1008
static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
{
	if (!chip->info->max_vid)
		return 0;

	return mv88e6xxx_g1_vtu_flush(chip);
}

1009 1010 1011 1012 1013 1014 1015 1016 1017
static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
				 struct mv88e6xxx_vtu_entry *entry)
{
	if (!chip->info->ops->vtu_getnext)
		return -EOPNOTSUPP;

	return chip->info->ops->vtu_getnext(chip, entry);
}

1018 1019 1020 1021 1022 1023 1024 1025 1026
static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
				   struct mv88e6xxx_vtu_entry *entry)
{
	if (!chip->info->ops->vtu_loadpurge)
		return -EOPNOTSUPP;

	return chip->info->ops->vtu_loadpurge(chip, entry);
}

1027
static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1028 1029
{
	DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1030 1031 1032
	struct mv88e6xxx_vtu_entry vlan = {
		.vid = chip->info->max_vid,
	};
1033
	int i, err;
1034 1035 1036

	bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);

1037
	/* Set every FID bit used by the (un)bridged ports */
1038
	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1039
		err = mv88e6xxx_port_get_fid(chip, i, fid);
1040 1041 1042 1043 1044 1045
		if (err)
			return err;

		set_bit(*fid, fid_bitmap);
	}

1046 1047
	/* Set every FID bit used by the VLAN entries */
	do {
1048
		err = mv88e6xxx_vtu_getnext(chip, &vlan);
1049 1050 1051 1052 1053 1054 1055
		if (err)
			return err;

		if (!vlan.valid)
			break;

		set_bit(vlan.fid, fid_bitmap);
1056
	} while (vlan.vid < chip->info->max_vid);
1057 1058 1059 1060 1061

	/* The reset value 0x000 is used to indicate that multiple address
	 * databases are not needed. Return the next positive available.
	 */
	*fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1062
	if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1063 1064 1065
		return -ENOSPC;

	/* Clear the database */
1066
	return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1067 1068
}

1069 1070
static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
			     struct mv88e6xxx_vtu_entry *entry, bool new)
1071 1072 1073 1074 1075 1076
{
	int err;

	if (!vid)
		return -EINVAL;

1077 1078
	entry->vid = vid - 1;
	entry->valid = false;
1079

1080
	err = mv88e6xxx_vtu_getnext(chip, entry);
1081 1082 1083
	if (err)
		return err;

1084 1085
	if (entry->vid == vid && entry->valid)
		return 0;
1086

1087 1088 1089 1090 1091 1092 1093 1094
	if (new) {
		int i;

		/* Initialize a fresh VLAN entry */
		memset(entry, 0, sizeof(*entry));
		entry->valid = true;
		entry->vid = vid;

1095
		/* Exclude all ports */
1096
		for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1097
			entry->member[i] =
1098
				MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1099 1100

		return mv88e6xxx_atu_new(chip, &entry->fid);
1101 1102
	}

1103 1104
	/* switchdev expects -EOPNOTSUPP to honor software VLANs */
	return -EOPNOTSUPP;
1105 1106
}

1107 1108 1109
static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
					u16 vid_begin, u16 vid_end)
{
V
Vivien Didelot 已提交
1110
	struct mv88e6xxx_chip *chip = ds->priv;
1111 1112 1113
	struct mv88e6xxx_vtu_entry vlan = {
		.vid = vid_begin - 1,
	};
1114 1115
	int i, err;

1116 1117 1118 1119
	/* DSA and CPU ports have to be members of multiple vlans */
	if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
		return 0;

1120 1121 1122
	if (!vid_begin)
		return -EOPNOTSUPP;

1123
	mutex_lock(&chip->reg_lock);
1124 1125

	do {
1126
		err = mv88e6xxx_vtu_getnext(chip, &vlan);
1127 1128 1129 1130 1131 1132 1133 1134 1135
		if (err)
			goto unlock;

		if (!vlan.valid)
			break;

		if (vlan.vid > vid_end)
			break;

1136
		for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1137 1138 1139
			if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
				continue;

1140
			if (!ds->ports[i].slave)
1141 1142
				continue;

1143
			if (vlan.member[i] ==
1144
			    MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1145 1146
				continue;

V
Vivien Didelot 已提交
1147
			if (dsa_to_port(ds, i)->bridge_dev ==
1148
			    ds->ports[port].bridge_dev)
1149 1150
				break; /* same bridge, check next VLAN */

V
Vivien Didelot 已提交
1151
			if (!dsa_to_port(ds, i)->bridge_dev)
1152 1153
				continue;

1154 1155
			dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
				port, vlan.vid, i,
V
Vivien Didelot 已提交
1156
				netdev_name(dsa_to_port(ds, i)->bridge_dev));
1157 1158 1159 1160 1161 1162
			err = -EOPNOTSUPP;
			goto unlock;
		}
	} while (vlan.vid < vid_end);

unlock:
1163
	mutex_unlock(&chip->reg_lock);
1164 1165 1166 1167

	return err;
}

1168 1169
static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
					 bool vlan_filtering)
1170
{
V
Vivien Didelot 已提交
1171
	struct mv88e6xxx_chip *chip = ds->priv;
1172 1173
	u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
		MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1174
	int err;
1175

1176
	if (!chip->info->max_vid)
1177 1178
		return -EOPNOTSUPP;

1179
	mutex_lock(&chip->reg_lock);
1180
	err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1181
	mutex_unlock(&chip->reg_lock);
1182

1183
	return err;
1184 1185
}

1186 1187 1188 1189
static int
mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
			    const struct switchdev_obj_port_vlan *vlan,
			    struct switchdev_trans *trans)
1190
{
V
Vivien Didelot 已提交
1191
	struct mv88e6xxx_chip *chip = ds->priv;
1192 1193
	int err;

1194
	if (!chip->info->max_vid)
1195 1196
		return -EOPNOTSUPP;

1197 1198 1199 1200 1201 1202 1203 1204
	/* If the requested port doesn't belong to the same bridge as the VLAN
	 * members, do not support it (yet) and fallback to software VLAN.
	 */
	err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
					   vlan->vid_end);
	if (err)
		return err;

1205 1206 1207 1208 1209 1210
	/* We don't need any dynamic resource from the kernel (yet),
	 * so skip the prepare phase.
	 */
	return 0;
}

1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254
static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
					const unsigned char *addr, u16 vid,
					u8 state)
{
	struct mv88e6xxx_vtu_entry vlan;
	struct mv88e6xxx_atu_entry entry;
	int err;

	/* Null VLAN ID corresponds to the port private database */
	if (vid == 0)
		err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
	else
		err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
	if (err)
		return err;

	entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
	ether_addr_copy(entry.mac, addr);
	eth_addr_dec(entry.mac);

	err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
	if (err)
		return err;

	/* Initialize a fresh ATU entry if it isn't found */
	if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED ||
	    !ether_addr_equal(entry.mac, addr)) {
		memset(&entry, 0, sizeof(entry));
		ether_addr_copy(entry.mac, addr);
	}

	/* Purge the ATU entry only if no port is using it anymore */
	if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
		entry.portvec &= ~BIT(port);
		if (!entry.portvec)
			entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
	} else {
		entry.portvec |= BIT(port);
		entry.state = state;
	}

	return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
}

1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277
static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
					u16 vid)
{
	const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
	u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;

	return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
}

static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
{
	int port;
	int err;

	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
		err = mv88e6xxx_port_add_broadcast(chip, port, vid);
		if (err)
			return err;
	}

	return 0;
}

1278
static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1279
				    u16 vid, u8 member)
1280
{
1281
	struct mv88e6xxx_vtu_entry vlan;
1282 1283
	int err;

1284
	err = mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1285
	if (err)
1286
		return err;
1287

1288
	vlan.member[port] = member;
1289

1290 1291 1292 1293 1294
	err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
	if (err)
		return err;

	return mv88e6xxx_broadcast_setup(chip, vid);
1295 1296
}

1297 1298 1299
static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
				    const struct switchdev_obj_port_vlan *vlan,
				    struct switchdev_trans *trans)
1300
{
V
Vivien Didelot 已提交
1301
	struct mv88e6xxx_chip *chip = ds->priv;
1302 1303
	bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
	bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1304
	u8 member;
1305 1306
	u16 vid;

1307
	if (!chip->info->max_vid)
1308 1309
		return;

1310
	if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1311
		member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
1312
	else if (untagged)
1313
		member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
1314
	else
1315
		member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
1316

1317
	mutex_lock(&chip->reg_lock);
1318

1319
	for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1320
		if (_mv88e6xxx_port_vlan_add(chip, port, vid, member))
1321 1322
			dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
				vid, untagged ? 'u' : 't');
1323

1324
	if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
1325 1326
		dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
			vlan->vid_end);
1327

1328
	mutex_unlock(&chip->reg_lock);
1329 1330
}

1331
static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1332
				    int port, u16 vid)
1333
{
1334
	struct mv88e6xxx_vtu_entry vlan;
1335 1336
	int i, err;

1337
	err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1338
	if (err)
1339
		return err;
1340

1341
	/* Tell switchdev if this VLAN is handled in software */
1342
	if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1343
		return -EOPNOTSUPP;
1344

1345
	vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1346 1347

	/* keep the VLAN unless all ports are excluded */
1348
	vlan.valid = false;
1349
	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1350 1351
		if (vlan.member[i] !=
		    MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1352
			vlan.valid = true;
1353 1354 1355 1356
			break;
		}
	}

1357
	err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1358 1359 1360
	if (err)
		return err;

1361
	return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
1362 1363
}

1364 1365
static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
				   const struct switchdev_obj_port_vlan *vlan)
1366
{
V
Vivien Didelot 已提交
1367
	struct mv88e6xxx_chip *chip = ds->priv;
1368 1369 1370
	u16 pvid, vid;
	int err = 0;

1371
	if (!chip->info->max_vid)
1372 1373
		return -EOPNOTSUPP;

1374
	mutex_lock(&chip->reg_lock);
1375

1376
	err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1377 1378 1379
	if (err)
		goto unlock;

1380
	for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1381
		err = _mv88e6xxx_port_vlan_del(chip, port, vid);
1382 1383 1384 1385
		if (err)
			goto unlock;

		if (vid == pvid) {
1386
			err = mv88e6xxx_port_set_pvid(chip, port, 0);
1387 1388 1389 1390 1391
			if (err)
				goto unlock;
		}
	}

1392
unlock:
1393
	mutex_unlock(&chip->reg_lock);
1394 1395 1396 1397

	return err;
}

1398 1399
static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
				  const unsigned char *addr, u16 vid)
1400
{
V
Vivien Didelot 已提交
1401
	struct mv88e6xxx_chip *chip = ds->priv;
1402
	int err;
1403

1404
	mutex_lock(&chip->reg_lock);
1405 1406
	err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
					   MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1407
	mutex_unlock(&chip->reg_lock);
1408 1409

	return err;
1410 1411
}

1412
static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1413
				  const unsigned char *addr, u16 vid)
1414
{
V
Vivien Didelot 已提交
1415
	struct mv88e6xxx_chip *chip = ds->priv;
1416
	int err;
1417

1418
	mutex_lock(&chip->reg_lock);
1419
	err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1420
					   MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
1421
	mutex_unlock(&chip->reg_lock);
1422

1423
	return err;
1424 1425
}

1426 1427
static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
				      u16 fid, u16 vid, int port,
1428
				      dsa_fdb_dump_cb_t *cb, void *data)
1429
{
1430
	struct mv88e6xxx_atu_entry addr;
1431
	bool is_static;
1432 1433
	int err;

1434
	addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1435
	eth_broadcast_addr(addr.mac);
1436 1437

	do {
1438
		err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
1439
		if (err)
1440
			return err;
1441

1442
		if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED)
1443 1444
			break;

1445
		if (addr.trunk || (addr.portvec & BIT(port)) == 0)
1446 1447
			continue;

1448 1449
		if (!is_unicast_ether_addr(addr.mac))
			continue;
1450

1451 1452 1453
		is_static = (addr.state ==
			     MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
		err = cb(addr.mac, vid, is_static, data);
1454 1455
		if (err)
			return err;
1456 1457 1458 1459 1460
	} while (!is_broadcast_ether_addr(addr.mac));

	return err;
}

1461
static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
1462
				  dsa_fdb_dump_cb_t *cb, void *data)
1463
{
1464
	struct mv88e6xxx_vtu_entry vlan = {
1465
		.vid = chip->info->max_vid,
1466
	};
1467
	u16 fid;
1468 1469
	int err;

1470
	/* Dump port's default Filtering Information Database (VLAN ID 0) */
1471
	err = mv88e6xxx_port_get_fid(chip, port, &fid);
1472
	if (err)
1473
		return err;
1474

1475
	err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
1476
	if (err)
1477
		return err;
1478

1479
	/* Dump VLANs' Filtering Information Databases */
1480
	do {
1481
		err = mv88e6xxx_vtu_getnext(chip, &vlan);
1482
		if (err)
1483
			return err;
1484 1485 1486 1487

		if (!vlan.valid)
			break;

1488
		err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
1489
						 cb, data);
1490
		if (err)
1491
			return err;
1492
	} while (vlan.vid < chip->info->max_vid);
1493

1494 1495 1496 1497
	return err;
}

static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
1498
				   dsa_fdb_dump_cb_t *cb, void *data)
1499
{
V
Vivien Didelot 已提交
1500
	struct mv88e6xxx_chip *chip = ds->priv;
1501 1502 1503
	int err;

	mutex_lock(&chip->reg_lock);
1504
	err = mv88e6xxx_port_db_dump(chip, port, cb, data);
1505
	mutex_unlock(&chip->reg_lock);
1506 1507 1508 1509

	return err;
}

1510 1511
static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
				struct net_device *br)
1512
{
1513
	struct dsa_switch *ds;
1514
	int port;
1515
	int dev;
1516
	int err;
1517

1518 1519 1520 1521
	/* Remap the Port VLAN of each local bridge group member */
	for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
		if (chip->ds->ports[port].bridge_dev == br) {
			err = mv88e6xxx_port_vlan_map(chip, port);
1522
			if (err)
1523
				return err;
1524 1525 1526
		}
	}

1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544
	if (!mv88e6xxx_has_pvt(chip))
		return 0;

	/* Remap the Port VLAN of each cross-chip bridge group member */
	for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) {
		ds = chip->ds->dst->ds[dev];
		if (!ds)
			break;

		for (port = 0; port < ds->num_ports; ++port) {
			if (ds->ports[port].bridge_dev == br) {
				err = mv88e6xxx_pvt_map(chip, dev, port);
				if (err)
					return err;
			}
		}
	}

1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555
	return 0;
}

static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
				      struct net_device *br)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int err;

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_bridge_map(chip, br);
1556
	mutex_unlock(&chip->reg_lock);
1557

1558
	return err;
1559 1560
}

1561 1562
static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
					struct net_device *br)
1563
{
V
Vivien Didelot 已提交
1564
	struct mv88e6xxx_chip *chip = ds->priv;
1565

1566
	mutex_lock(&chip->reg_lock);
1567 1568 1569
	if (mv88e6xxx_bridge_map(chip, br) ||
	    mv88e6xxx_port_vlan_map(chip, port))
		dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
1570
	mutex_unlock(&chip->reg_lock);
1571 1572
}

1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602
static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
					   int port, struct net_device *br)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int err;

	if (!mv88e6xxx_has_pvt(chip))
		return 0;

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_pvt_map(chip, dev, port);
	mutex_unlock(&chip->reg_lock);

	return err;
}

static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
					     int port, struct net_device *br)
{
	struct mv88e6xxx_chip *chip = ds->priv;

	if (!mv88e6xxx_has_pvt(chip))
		return;

	mutex_lock(&chip->reg_lock);
	if (mv88e6xxx_pvt_map(chip, dev, port))
		dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
	mutex_unlock(&chip->reg_lock);
}

1603 1604 1605 1606 1607 1608 1609 1610
static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->reset)
		return chip->info->ops->reset(chip);

	return 0;
}

1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623
static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
{
	struct gpio_desc *gpiod = chip->reset;

	/* If there is a GPIO connected to the reset pin, toggle it */
	if (gpiod) {
		gpiod_set_value_cansleep(gpiod, 1);
		usleep_range(10000, 20000);
		gpiod_set_value_cansleep(gpiod, 0);
		usleep_range(10000, 20000);
	}
}

1624
static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
1625
{
1626
	int i, err;
1627

1628
	/* Set all ports to the Disabled state */
1629
	for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
1630
		err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
1631 1632
		if (err)
			return err;
1633 1634
	}

1635 1636 1637
	/* Wait for transmit queues to drain,
	 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
	 */
1638 1639
	usleep_range(2000, 4000);

1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650
	return 0;
}

static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
{
	int err;

	err = mv88e6xxx_disable_ports(chip);
	if (err)
		return err;

1651
	mv88e6xxx_hardware_reset(chip);
1652

1653
	return mv88e6xxx_software_reset(chip);
1654 1655
}

1656
static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
1657 1658
				   enum mv88e6xxx_frame_mode frame,
				   enum mv88e6xxx_egress_mode egress, u16 etype)
1659 1660 1661
{
	int err;

1662 1663 1664 1665
	if (!chip->info->ops->port_set_frame_mode)
		return -EOPNOTSUPP;

	err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
1666 1667 1668
	if (err)
		return err;

1669 1670 1671 1672 1673 1674 1675 1676
	err = chip->info->ops->port_set_frame_mode(chip, port, frame);
	if (err)
		return err;

	if (chip->info->ops->port_set_ether_type)
		return chip->info->ops->port_set_ether_type(chip, port, etype);

	return 0;
1677 1678
}

1679
static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
1680
{
1681
	return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
1682
				       MV88E6XXX_EGRESS_MODE_UNMODIFIED,
1683
				       MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
1684
}
1685

1686 1687 1688
static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
{
	return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
1689
				       MV88E6XXX_EGRESS_MODE_UNMODIFIED,
1690
				       MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
1691
}
1692

1693 1694 1695 1696
static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
{
	return mv88e6xxx_set_port_mode(chip, port,
				       MV88E6XXX_FRAME_MODE_ETHERTYPE,
1697 1698
				       MV88E6XXX_EGRESS_MODE_ETHERTYPE,
				       ETH_P_EDSA);
1699
}
1700

1701 1702 1703 1704
static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
{
	if (dsa_is_dsa_port(chip->ds, port))
		return mv88e6xxx_set_port_mode_dsa(chip, port);
1705

1706
	if (dsa_is_user_port(chip->ds, port))
1707
		return mv88e6xxx_set_port_mode_normal(chip, port);
1708

1709 1710 1711
	/* Setup CPU port mode depending on its supported tag format */
	if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
		return mv88e6xxx_set_port_mode_dsa(chip, port);
1712

1713 1714
	if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
		return mv88e6xxx_set_port_mode_edsa(chip, port);
1715

1716
	return -EINVAL;
1717 1718
}

1719
static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
1720
{
1721
	bool message = dsa_is_dsa_port(chip->ds, port);
1722

1723
	return mv88e6xxx_port_set_message_port(chip, port, message);
1724
}
1725

1726
static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
1727
{
1728
	bool flood = port == dsa_upstream_port(chip->ds);
1729

1730 1731 1732 1733
	/* Upstream ports flood frames with unknown unicast or multicast DA */
	if (chip->info->ops->port_set_egress_floods)
		return chip->info->ops->port_set_egress_floods(chip, port,
							       flood, flood);
1734

1735
	return 0;
1736 1737
}

1738 1739 1740
static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
				  bool on)
{
1741 1742
	if (chip->info->ops->serdes_power)
		return chip->info->ops->serdes_power(chip, port, on);
1743

1744
	return 0;
1745 1746
}

1747
static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
1748
{
1749
	struct dsa_switch *ds = chip->ds;
1750
	int err;
1751
	u16 reg;
1752

1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766
	/* MAC Forcing register: don't force link, speed, duplex or flow control
	 * state to any particular values on physical ports, but force the CPU
	 * port and all DSA ports to their maximum bandwidth and full duplex.
	 */
	if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
		err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
					       SPEED_MAX, DUPLEX_FULL,
					       PHY_INTERFACE_MODE_NA);
	else
		err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
					       SPEED_UNFORCED, DUPLEX_UNFORCED,
					       PHY_INTERFACE_MODE_NA);
	if (err)
		return err;
1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781

	/* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
	 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
	 * tunneling, determine priority by looking at 802.1p and IP
	 * priority fields (IP prio has precedence), and set STP state
	 * to Forwarding.
	 *
	 * If this is the CPU link, use DSA or EDSA tagging depending
	 * on which tagging mode was configured.
	 *
	 * If this is a link to another switch, use DSA tagging mode.
	 *
	 * If this is the upstream port for this switch, enable
	 * forwarding of unknown unicasts and multicasts.
	 */
1782 1783 1784 1785
	reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
		MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
		MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
1786 1787
	if (err)
		return err;
1788

1789
	err = mv88e6xxx_setup_port_mode(chip, port);
1790 1791
	if (err)
		return err;
1792

1793
	err = mv88e6xxx_setup_egress_floods(chip, port);
1794 1795 1796
	if (err)
		return err;

1797 1798 1799
	/* Enable the SERDES interface for DSA and CPU ports. Normal
	 * ports SERDES are enabled when the port is enabled, thus
	 * saving a bit of power.
1800
	 */
1801 1802 1803 1804 1805
	if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) {
		err = mv88e6xxx_serdes_power(chip, port, true);
		if (err)
			return err;
	}
1806

1807
	/* Port Control 2: don't force a good FCS, set the maximum frame size to
1808
	 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
1809 1810 1811
	 * untagged frames on this port, do a destination address lookup on all
	 * received packets as usual, disable ARP mirroring and don't send a
	 * copy of all transmitted/received frames on this port to the CPU.
1812
	 */
1813 1814 1815
	err = mv88e6xxx_port_set_map_da(chip, port);
	if (err)
		return err;
1816

1817 1818 1819 1820
	reg = 0;
	if (chip->info->ops->port_set_upstream_port) {
		err = chip->info->ops->port_set_upstream_port(
			chip, port, dsa_upstream_port(ds));
1821 1822
		if (err)
			return err;
1823 1824
	}

1825
	err = mv88e6xxx_port_set_8021q_mode(chip, port,
1826
				MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
1827 1828 1829
	if (err)
		return err;

1830 1831
	if (chip->info->ops->port_set_jumbo_size) {
		err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
1832 1833 1834 1835
		if (err)
			return err;
	}

1836 1837 1838 1839 1840
	/* Port Association Vector: when learning source addresses
	 * of packets, add the address to the address database using
	 * a port bitmap that has only the bit for this port set and
	 * the other bits clear.
	 */
1841
	reg = 1 << port;
1842 1843
	/* Disable learning for CPU port */
	if (dsa_is_cpu_port(ds, port))
1844
		reg = 0;
1845

1846 1847
	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
				   reg);
1848 1849
	if (err)
		return err;
1850 1851

	/* Egress rate control 2: disable egress rate control. */
1852 1853
	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
				   0x0000);
1854 1855
	if (err)
		return err;
1856

1857 1858
	if (chip->info->ops->port_pause_limit) {
		err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
1859 1860
		if (err)
			return err;
1861
	}
1862

1863 1864 1865 1866 1867 1868
	if (chip->info->ops->port_disable_learn_limit) {
		err = chip->info->ops->port_disable_learn_limit(chip, port);
		if (err)
			return err;
	}

1869 1870
	if (chip->info->ops->port_disable_pri_override) {
		err = chip->info->ops->port_disable_pri_override(chip, port);
1871 1872
		if (err)
			return err;
1873
	}
1874

1875 1876
	if (chip->info->ops->port_tag_remap) {
		err = chip->info->ops->port_tag_remap(chip, port);
1877 1878
		if (err)
			return err;
1879 1880
	}

1881 1882
	if (chip->info->ops->port_egress_rate_limiting) {
		err = chip->info->ops->port_egress_rate_limiting(chip, port);
1883 1884
		if (err)
			return err;
1885 1886
	}

1887
	err = mv88e6xxx_setup_message_port(chip, port);
1888 1889
	if (err)
		return err;
1890

1891
	/* Port based VLAN map: give each port the same default address
1892 1893
	 * database, and allow bidirectional communication between the
	 * CPU and DSA port(s), and the other ports.
1894
	 */
1895
	err = mv88e6xxx_port_set_fid(chip, port, 0);
1896 1897
	if (err)
		return err;
1898

1899
	err = mv88e6xxx_port_vlan_map(chip, port);
1900 1901
	if (err)
		return err;
1902 1903 1904 1905

	/* Default VLAN ID and priority: don't set a default VLAN
	 * ID, and set the default packet priority to zero.
	 */
1906
	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
1907 1908
}

1909 1910 1911 1912
static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
				 struct phy_device *phydev)
{
	struct mv88e6xxx_chip *chip = ds->priv;
1913
	int err;
1914 1915

	mutex_lock(&chip->reg_lock);
1916
	err = mv88e6xxx_serdes_power(chip, port, true);
1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927
	mutex_unlock(&chip->reg_lock);

	return err;
}

static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port,
				   struct phy_device *phydev)
{
	struct mv88e6xxx_chip *chip = ds->priv;

	mutex_lock(&chip->reg_lock);
1928 1929
	if (mv88e6xxx_serdes_power(chip, port, false))
		dev_err(chip->dev, "failed to power off SERDES\n");
1930 1931 1932
	mutex_unlock(&chip->reg_lock);
}

1933 1934 1935
static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
				     unsigned int ageing_time)
{
V
Vivien Didelot 已提交
1936
	struct mv88e6xxx_chip *chip = ds->priv;
1937 1938 1939
	int err;

	mutex_lock(&chip->reg_lock);
1940
	err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
1941 1942 1943 1944 1945
	mutex_unlock(&chip->reg_lock);

	return err;
}

1946
static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
1947
{
1948
	struct dsa_switch *ds = chip->ds;
1949
	u32 upstream_port = dsa_upstream_port(ds);
1950
	int err;
1951

1952 1953
	if (chip->info->ops->set_cpu_port) {
		err = chip->info->ops->set_cpu_port(chip, upstream_port);
1954 1955 1956 1957
		if (err)
			return err;
	}

1958 1959
	if (chip->info->ops->set_egress_port) {
		err = chip->info->ops->set_egress_port(chip, upstream_port);
1960 1961 1962
		if (err)
			return err;
	}
1963

1964
	/* Disable remote management, and set the switch's DSA device number. */
1965 1966
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2,
				 MV88E6XXX_G1_CTL2_MULTIPLE_CASCADE |
1967
				 (ds->index & 0x1f));
1968 1969 1970
	if (err)
		return err;

1971
	/* Configure the IP ToS mapping registers. */
1972
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000);
1973
	if (err)
1974
		return err;
1975
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000);
1976
	if (err)
1977
		return err;
1978
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555);
1979
	if (err)
1980
		return err;
1981
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555);
1982
	if (err)
1983
		return err;
1984
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa);
1985
	if (err)
1986
		return err;
1987
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa);
1988
	if (err)
1989
		return err;
1990
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff);
1991
	if (err)
1992
		return err;
1993
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff);
1994
	if (err)
1995
		return err;
1996 1997

	/* Configure the IEEE 802.1p priority mapping register. */
1998
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41);
1999
	if (err)
2000
		return err;
2001

2002 2003 2004 2005 2006
	/* Initialize the statistics unit */
	err = mv88e6xxx_stats_set_histogram(chip);
	if (err)
		return err;

2007
	return mv88e6xxx_g1_stats_clear(chip);
2008 2009
}

2010
static int mv88e6xxx_setup(struct dsa_switch *ds)
2011
{
V
Vivien Didelot 已提交
2012
	struct mv88e6xxx_chip *chip = ds->priv;
2013
	int err;
2014 2015
	int i;

2016
	chip->ds = ds;
2017
	ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
2018

2019
	mutex_lock(&chip->reg_lock);
2020

2021
	/* Setup Switch Port Registers */
2022
	for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2023 2024 2025
		if (dsa_is_unused_port(ds, i))
			continue;

2026 2027 2028 2029 2030 2031 2032
		err = mv88e6xxx_setup_port(chip, i);
		if (err)
			goto unlock;
	}

	/* Setup Switch Global 1 Registers */
	err = mv88e6xxx_g1_setup(chip);
2033 2034 2035
	if (err)
		goto unlock;

2036
	/* Setup Switch Global 2 Registers */
2037
	if (chip->info->global2_addr) {
2038
		err = mv88e6xxx_g2_setup(chip);
2039 2040 2041
		if (err)
			goto unlock;
	}
2042

2043 2044 2045 2046
	err = mv88e6xxx_irl_setup(chip);
	if (err)
		goto unlock;

2047 2048 2049 2050
	err = mv88e6xxx_mac_setup(chip);
	if (err)
		goto unlock;

2051 2052 2053 2054
	err = mv88e6xxx_phy_setup(chip);
	if (err)
		goto unlock;

2055 2056 2057 2058
	err = mv88e6xxx_vtu_setup(chip);
	if (err)
		goto unlock;

2059 2060 2061 2062
	err = mv88e6xxx_pvt_setup(chip);
	if (err)
		goto unlock;

2063 2064 2065 2066
	err = mv88e6xxx_atu_setup(chip);
	if (err)
		goto unlock;

2067 2068 2069 2070
	err = mv88e6xxx_broadcast_setup(chip, 0);
	if (err)
		goto unlock;

2071 2072 2073 2074
	err = mv88e6xxx_pot_setup(chip);
	if (err)
		goto unlock;

2075 2076 2077
	err = mv88e6xxx_rsvd2cpu_setup(chip);
	if (err)
		goto unlock;
2078

2079
unlock:
2080
	mutex_unlock(&chip->reg_lock);
2081

2082
	return err;
2083 2084
}

2085
static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
2086
{
2087 2088
	struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
	struct mv88e6xxx_chip *chip = mdio_bus->chip;
2089 2090
	u16 val;
	int err;
2091

2092 2093 2094
	if (!chip->info->ops->phy_read)
		return -EOPNOTSUPP;

2095
	mutex_lock(&chip->reg_lock);
2096
	err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
2097
	mutex_unlock(&chip->reg_lock);
2098

2099 2100 2101 2102 2103
	if (reg == MII_PHYSID2) {
		/* Some internal PHYS don't have a model number.  Use
		 * the mv88e6390 family model number instead.
		 */
		if (!(val & 0x3f0))
2104
			val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
2105 2106
	}

2107
	return err ? err : val;
2108 2109
}

2110
static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
2111
{
2112 2113
	struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
	struct mv88e6xxx_chip *chip = mdio_bus->chip;
2114
	int err;
2115

2116 2117 2118
	if (!chip->info->ops->phy_write)
		return -EOPNOTSUPP;

2119
	mutex_lock(&chip->reg_lock);
2120
	err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
2121
	mutex_unlock(&chip->reg_lock);
2122 2123

	return err;
2124 2125
}

2126
static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
2127 2128
				   struct device_node *np,
				   bool external)
2129 2130
{
	static int index;
2131
	struct mv88e6xxx_mdio_bus *mdio_bus;
2132 2133 2134
	struct mii_bus *bus;
	int err;

2135
	bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
2136 2137 2138
	if (!bus)
		return -ENOMEM;

2139
	mdio_bus = bus->priv;
2140
	mdio_bus->bus = bus;
2141
	mdio_bus->chip = chip;
2142 2143
	INIT_LIST_HEAD(&mdio_bus->list);
	mdio_bus->external = external;
2144

2145 2146
	if (np) {
		bus->name = np->full_name;
2147
		snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
2148 2149 2150 2151 2152 2153 2154
	} else {
		bus->name = "mv88e6xxx SMI";
		snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
	}

	bus->read = mv88e6xxx_mdio_read;
	bus->write = mv88e6xxx_mdio_write;
2155
	bus->parent = chip->dev;
2156

2157 2158
	if (np)
		err = of_mdiobus_register(bus, np);
2159 2160 2161
	else
		err = mdiobus_register(bus);
	if (err) {
2162
		dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
2163
		return err;
2164
	}
2165 2166 2167 2168 2169

	if (external)
		list_add_tail(&mdio_bus->list, &chip->mdios);
	else
		list_add(&mdio_bus->list, &chip->mdios);
2170 2171

	return 0;
2172
}
2173

2174 2175 2176 2177 2178
static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
	{ .compatible = "marvell,mv88e6xxx-mdio-external",
	  .data = (void *)true },
	{ },
};
2179

2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209
static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
				    struct device_node *np)
{
	const struct of_device_id *match;
	struct device_node *child;
	int err;

	/* Always register one mdio bus for the internal/default mdio
	 * bus. This maybe represented in the device tree, but is
	 * optional.
	 */
	child = of_get_child_by_name(np, "mdio");
	err = mv88e6xxx_mdio_register(chip, child, false);
	if (err)
		return err;

	/* Walk the device tree, and see if there are any other nodes
	 * which say they are compatible with the external mdio
	 * bus.
	 */
	for_each_available_child_of_node(np, child) {
		match = of_match_node(mv88e6xxx_mdio_external_match, child);
		if (match) {
			err = mv88e6xxx_mdio_register(chip, child, true);
			if (err)
				return err;
		}
	}

	return 0;
2210 2211
}

2212
static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
2213 2214

{
2215 2216
	struct mv88e6xxx_mdio_bus *mdio_bus;
	struct mii_bus *bus;
2217

2218 2219
	list_for_each_entry(mdio_bus, &chip->mdios, list) {
		bus = mdio_bus->bus;
2220

2221 2222
		mdiobus_unregister(bus);
	}
2223 2224
}

2225 2226
static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
{
V
Vivien Didelot 已提交
2227
	struct mv88e6xxx_chip *chip = ds->priv;
2228 2229 2230 2231 2232 2233 2234

	return chip->eeprom_len;
}

static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
				struct ethtool_eeprom *eeprom, u8 *data)
{
V
Vivien Didelot 已提交
2235
	struct mv88e6xxx_chip *chip = ds->priv;
2236 2237
	int err;

2238 2239
	if (!chip->info->ops->get_eeprom)
		return -EOPNOTSUPP;
2240

2241 2242
	mutex_lock(&chip->reg_lock);
	err = chip->info->ops->get_eeprom(chip, eeprom, data);
2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255
	mutex_unlock(&chip->reg_lock);

	if (err)
		return err;

	eeprom->magic = 0xc3ec4951;

	return 0;
}

static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
				struct ethtool_eeprom *eeprom, u8 *data)
{
V
Vivien Didelot 已提交
2256
	struct mv88e6xxx_chip *chip = ds->priv;
2257 2258
	int err;

2259 2260 2261
	if (!chip->info->ops->set_eeprom)
		return -EOPNOTSUPP;

2262 2263 2264 2265
	if (eeprom->magic != 0xc3ec4951)
		return -EINVAL;

	mutex_lock(&chip->reg_lock);
2266
	err = chip->info->ops->set_eeprom(chip, eeprom, data);
2267 2268 2269 2270 2271
	mutex_unlock(&chip->reg_lock);

	return err;
}

2272
static const struct mv88e6xxx_ops mv88e6085_ops = {
2273
	/* MV88E6XXX_FAMILY_6097 */
2274
	.irl_init_all = mv88e6352_g2_irl_init_all,
2275
	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2276 2277
	.phy_read = mv88e6185_phy_ppu_read,
	.phy_write = mv88e6185_phy_ppu_write,
2278
	.port_set_link = mv88e6xxx_port_set_link,
2279
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2280
	.port_set_speed = mv88e6185_port_set_speed,
2281
	.port_tag_remap = mv88e6095_port_tag_remap,
2282
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2283
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2284
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2285
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2286
	.port_pause_limit = mv88e6097_port_pause_limit,
2287
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2288
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2289
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2290
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2291 2292
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2293
	.stats_get_stats = mv88e6095_stats_get_stats,
2294 2295
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2296
	.watchdog_ops = &mv88e6097_watchdog_ops,
2297
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2298
	.pot_clear = mv88e6xxx_g2_pot_clear,
2299 2300
	.ppu_enable = mv88e6185_g1_ppu_enable,
	.ppu_disable = mv88e6185_g1_ppu_disable,
2301
	.reset = mv88e6185_g1_reset,
2302
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2303
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2304 2305 2306
};

static const struct mv88e6xxx_ops mv88e6095_ops = {
2307
	/* MV88E6XXX_FAMILY_6095 */
2308
	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2309 2310
	.phy_read = mv88e6185_phy_ppu_read,
	.phy_write = mv88e6185_phy_ppu_write,
2311
	.port_set_link = mv88e6xxx_port_set_link,
2312
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2313
	.port_set_speed = mv88e6185_port_set_speed,
2314
	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
2315
	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
2316
	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
2317
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2318
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2319 2320
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2321
	.stats_get_stats = mv88e6095_stats_get_stats,
2322
	.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2323 2324
	.ppu_enable = mv88e6185_g1_ppu_enable,
	.ppu_disable = mv88e6185_g1_ppu_disable,
2325
	.reset = mv88e6185_g1_reset,
2326
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
2327
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2328 2329
};

2330
static const struct mv88e6xxx_ops mv88e6097_ops = {
2331
	/* MV88E6XXX_FAMILY_6097 */
2332
	.irl_init_all = mv88e6352_g2_irl_init_all,
2333 2334 2335 2336 2337 2338
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_speed = mv88e6185_port_set_speed,
2339
	.port_tag_remap = mv88e6095_port_tag_remap,
2340
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2341
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2342
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2343
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2344
	.port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2345
	.port_pause_limit = mv88e6097_port_pause_limit,
2346
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2347
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2348
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2349
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2350 2351 2352
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
	.stats_get_stats = mv88e6095_stats_get_stats,
2353 2354
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2355
	.watchdog_ops = &mv88e6097_watchdog_ops,
2356
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2357
	.pot_clear = mv88e6xxx_g2_pot_clear,
2358
	.reset = mv88e6352_g1_reset,
2359
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2360
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2361 2362
};

2363
static const struct mv88e6xxx_ops mv88e6123_ops = {
2364
	/* MV88E6XXX_FAMILY_6165 */
2365
	.irl_init_all = mv88e6352_g2_irl_init_all,
2366
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2367 2368
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2369
	.port_set_link = mv88e6xxx_port_set_link,
2370
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2371
	.port_set_speed = mv88e6185_port_set_speed,
2372
	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
2373
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2374
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2375
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2376
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2377
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2378 2379
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2380
	.stats_get_stats = mv88e6095_stats_get_stats,
2381 2382
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2383
	.watchdog_ops = &mv88e6097_watchdog_ops,
2384
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2385
	.pot_clear = mv88e6xxx_g2_pot_clear,
2386
	.reset = mv88e6352_g1_reset,
2387
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2388
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2389 2390 2391
};

static const struct mv88e6xxx_ops mv88e6131_ops = {
2392
	/* MV88E6XXX_FAMILY_6185 */
2393
	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2394 2395
	.phy_read = mv88e6185_phy_ppu_read,
	.phy_write = mv88e6185_phy_ppu_write,
2396
	.port_set_link = mv88e6xxx_port_set_link,
2397
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2398
	.port_set_speed = mv88e6185_port_set_speed,
2399
	.port_tag_remap = mv88e6095_port_tag_remap,
2400
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2401
	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
2402
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2403
	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
2404
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2405
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2406
	.port_pause_limit = mv88e6097_port_pause_limit,
2407
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2408
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2409 2410
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2411
	.stats_get_stats = mv88e6095_stats_get_stats,
2412 2413
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2414
	.watchdog_ops = &mv88e6097_watchdog_ops,
2415
	.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2416 2417
	.ppu_enable = mv88e6185_g1_ppu_enable,
	.ppu_disable = mv88e6185_g1_ppu_disable,
2418
	.reset = mv88e6185_g1_reset,
2419
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
2420
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2421 2422
};

2423 2424
static const struct mv88e6xxx_ops mv88e6141_ops = {
	/* MV88E6XXX_FAMILY_6341 */
2425
	.irl_init_all = mv88e6352_g2_irl_init_all,
2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
	.port_tag_remap = mv88e6095_port_tag_remap,
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2439
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2440
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2441
	.port_pause_limit = mv88e6097_port_pause_limit,
2442 2443 2444
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
2445
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2446 2447 2448
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
	.stats_get_stats = mv88e6390_stats_get_stats,
2449 2450
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
2451 2452
	.watchdog_ops = &mv88e6390_watchdog_ops,
	.mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
2453
	.pot_clear = mv88e6xxx_g2_pot_clear,
2454
	.reset = mv88e6352_g1_reset,
2455
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2456
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2457 2458
};

2459
static const struct mv88e6xxx_ops mv88e6161_ops = {
2460
	/* MV88E6XXX_FAMILY_6165 */
2461
	.irl_init_all = mv88e6352_g2_irl_init_all,
2462
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2463 2464
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2465
	.port_set_link = mv88e6xxx_port_set_link,
2466
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2467
	.port_set_speed = mv88e6185_port_set_speed,
2468
	.port_tag_remap = mv88e6095_port_tag_remap,
2469
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2470
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2471
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2472
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2473
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2474
	.port_pause_limit = mv88e6097_port_pause_limit,
2475
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2476
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2477
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2478
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2479 2480
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2481
	.stats_get_stats = mv88e6095_stats_get_stats,
2482 2483
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2484
	.watchdog_ops = &mv88e6097_watchdog_ops,
2485
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2486
	.pot_clear = mv88e6xxx_g2_pot_clear,
2487
	.reset = mv88e6352_g1_reset,
2488
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2489
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2490 2491 2492
};

static const struct mv88e6xxx_ops mv88e6165_ops = {
2493
	/* MV88E6XXX_FAMILY_6165 */
2494
	.irl_init_all = mv88e6352_g2_irl_init_all,
2495
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2496 2497
	.phy_read = mv88e6165_phy_read,
	.phy_write = mv88e6165_phy_write,
2498
	.port_set_link = mv88e6xxx_port_set_link,
2499
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2500
	.port_set_speed = mv88e6185_port_set_speed,
2501
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2502
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2503
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2504
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2505 2506
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2507
	.stats_get_stats = mv88e6095_stats_get_stats,
2508 2509
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2510
	.watchdog_ops = &mv88e6097_watchdog_ops,
2511
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2512
	.pot_clear = mv88e6xxx_g2_pot_clear,
2513
	.reset = mv88e6352_g1_reset,
2514
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2515
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2516 2517 2518
};

static const struct mv88e6xxx_ops mv88e6171_ops = {
2519
	/* MV88E6XXX_FAMILY_6351 */
2520
	.irl_init_all = mv88e6352_g2_irl_init_all,
2521
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2522 2523
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2524
	.port_set_link = mv88e6xxx_port_set_link,
2525
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2526
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2527
	.port_set_speed = mv88e6185_port_set_speed,
2528
	.port_tag_remap = mv88e6095_port_tag_remap,
2529
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2530
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2531
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2532
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2533
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2534
	.port_pause_limit = mv88e6097_port_pause_limit,
2535
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2536
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2537
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2538
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2539 2540
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2541
	.stats_get_stats = mv88e6095_stats_get_stats,
2542 2543
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2544
	.watchdog_ops = &mv88e6097_watchdog_ops,
2545
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2546
	.pot_clear = mv88e6xxx_g2_pot_clear,
2547
	.reset = mv88e6352_g1_reset,
2548
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2549
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2550 2551 2552
};

static const struct mv88e6xxx_ops mv88e6172_ops = {
2553
	/* MV88E6XXX_FAMILY_6352 */
2554
	.irl_init_all = mv88e6352_g2_irl_init_all,
2555 2556
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
2557
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2558 2559
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2560
	.port_set_link = mv88e6xxx_port_set_link,
2561
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2562
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2563
	.port_set_speed = mv88e6352_port_set_speed,
2564
	.port_tag_remap = mv88e6095_port_tag_remap,
2565
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2566
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2567
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2568
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2569
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2570
	.port_pause_limit = mv88e6097_port_pause_limit,
2571
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2572
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2573
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2574
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2575 2576
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2577
	.stats_get_stats = mv88e6095_stats_get_stats,
2578 2579
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2580
	.watchdog_ops = &mv88e6097_watchdog_ops,
2581
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2582
	.pot_clear = mv88e6xxx_g2_pot_clear,
2583
	.reset = mv88e6352_g1_reset,
2584
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2585
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2586
	.serdes_power = mv88e6352_serdes_power,
2587 2588 2589
};

static const struct mv88e6xxx_ops mv88e6175_ops = {
2590
	/* MV88E6XXX_FAMILY_6351 */
2591
	.irl_init_all = mv88e6352_g2_irl_init_all,
2592
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2593 2594
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2595
	.port_set_link = mv88e6xxx_port_set_link,
2596
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2597
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2598
	.port_set_speed = mv88e6185_port_set_speed,
2599
	.port_tag_remap = mv88e6095_port_tag_remap,
2600
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2601
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2602
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2603
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2604
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2605
	.port_pause_limit = mv88e6097_port_pause_limit,
2606
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2607
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2608
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2609
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2610 2611
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2612
	.stats_get_stats = mv88e6095_stats_get_stats,
2613 2614
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2615
	.watchdog_ops = &mv88e6097_watchdog_ops,
2616
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2617
	.pot_clear = mv88e6xxx_g2_pot_clear,
2618
	.reset = mv88e6352_g1_reset,
2619
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2620
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2621 2622 2623
};

static const struct mv88e6xxx_ops mv88e6176_ops = {
2624
	/* MV88E6XXX_FAMILY_6352 */
2625
	.irl_init_all = mv88e6352_g2_irl_init_all,
2626 2627
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
2628
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2629 2630
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2631
	.port_set_link = mv88e6xxx_port_set_link,
2632
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2633
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2634
	.port_set_speed = mv88e6352_port_set_speed,
2635
	.port_tag_remap = mv88e6095_port_tag_remap,
2636
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2637
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2638
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2639
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2640
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2641
	.port_pause_limit = mv88e6097_port_pause_limit,
2642
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2643
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2644
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2645
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2646 2647
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2648
	.stats_get_stats = mv88e6095_stats_get_stats,
2649 2650
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2651
	.watchdog_ops = &mv88e6097_watchdog_ops,
2652
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2653
	.pot_clear = mv88e6xxx_g2_pot_clear,
2654
	.reset = mv88e6352_g1_reset,
2655
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2656
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2657
	.serdes_power = mv88e6352_serdes_power,
2658 2659 2660
};

static const struct mv88e6xxx_ops mv88e6185_ops = {
2661
	/* MV88E6XXX_FAMILY_6185 */
2662
	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2663 2664
	.phy_read = mv88e6185_phy_ppu_read,
	.phy_write = mv88e6185_phy_ppu_write,
2665
	.port_set_link = mv88e6xxx_port_set_link,
2666
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2667
	.port_set_speed = mv88e6185_port_set_speed,
2668
	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
2669
	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
2670
	.port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2671
	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
2672
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2673
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2674 2675
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2676
	.stats_get_stats = mv88e6095_stats_get_stats,
2677 2678
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2679
	.watchdog_ops = &mv88e6097_watchdog_ops,
2680
	.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2681 2682
	.ppu_enable = mv88e6185_g1_ppu_enable,
	.ppu_disable = mv88e6185_g1_ppu_disable,
2683
	.reset = mv88e6185_g1_reset,
2684
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
2685
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2686 2687
};

2688
static const struct mv88e6xxx_ops mv88e6190_ops = {
2689
	/* MV88E6XXX_FAMILY_6390 */
2690
	.irl_init_all = mv88e6390_g2_irl_init_all,
2691 2692
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
2693 2694 2695 2696 2697 2698 2699
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
2700
	.port_tag_remap = mv88e6390_port_tag_remap,
2701
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2702
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2703
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2704
	.port_pause_limit = mv88e6390_port_pause_limit,
2705
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2706
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2707
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
2708
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2709 2710
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
2711
	.stats_get_stats = mv88e6390_stats_get_stats,
2712 2713
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
2714
	.watchdog_ops = &mv88e6390_watchdog_ops,
2715
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2716
	.pot_clear = mv88e6xxx_g2_pot_clear,
2717
	.reset = mv88e6352_g1_reset,
2718 2719
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2720
	.serdes_power = mv88e6390_serdes_power,
2721 2722 2723
};

static const struct mv88e6xxx_ops mv88e6190x_ops = {
2724
	/* MV88E6XXX_FAMILY_6390 */
2725
	.irl_init_all = mv88e6390_g2_irl_init_all,
2726 2727
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
2728 2729 2730 2731 2732 2733 2734
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390x_port_set_speed,
2735
	.port_tag_remap = mv88e6390_port_tag_remap,
2736
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2737
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2738
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2739
	.port_pause_limit = mv88e6390_port_pause_limit,
2740
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2741
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2742
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
2743
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2744 2745
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
2746
	.stats_get_stats = mv88e6390_stats_get_stats,
2747 2748
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
2749
	.watchdog_ops = &mv88e6390_watchdog_ops,
2750
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2751
	.pot_clear = mv88e6xxx_g2_pot_clear,
2752
	.reset = mv88e6352_g1_reset,
2753 2754
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2755
	.serdes_power = mv88e6390_serdes_power,
2756 2757 2758
};

static const struct mv88e6xxx_ops mv88e6191_ops = {
2759
	/* MV88E6XXX_FAMILY_6390 */
2760
	.irl_init_all = mv88e6390_g2_irl_init_all,
2761 2762
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
2763 2764 2765 2766 2767 2768 2769
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
2770
	.port_tag_remap = mv88e6390_port_tag_remap,
2771
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2772
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2773
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2774
	.port_pause_limit = mv88e6390_port_pause_limit,
2775
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2776
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2777
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
2778
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2779 2780
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
2781
	.stats_get_stats = mv88e6390_stats_get_stats,
2782 2783
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
2784
	.watchdog_ops = &mv88e6390_watchdog_ops,
2785
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2786
	.pot_clear = mv88e6xxx_g2_pot_clear,
2787
	.reset = mv88e6352_g1_reset,
2788 2789
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2790
	.serdes_power = mv88e6390_serdes_power,
2791 2792
};

2793
static const struct mv88e6xxx_ops mv88e6240_ops = {
2794
	/* MV88E6XXX_FAMILY_6352 */
2795
	.irl_init_all = mv88e6352_g2_irl_init_all,
2796 2797
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
2798
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2799 2800
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2801
	.port_set_link = mv88e6xxx_port_set_link,
2802
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2803
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2804
	.port_set_speed = mv88e6352_port_set_speed,
2805
	.port_tag_remap = mv88e6095_port_tag_remap,
2806
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2807
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2808
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2809
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2810
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2811
	.port_pause_limit = mv88e6097_port_pause_limit,
2812
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2813
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2814
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2815
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2816 2817
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2818
	.stats_get_stats = mv88e6095_stats_get_stats,
2819 2820
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2821
	.watchdog_ops = &mv88e6097_watchdog_ops,
2822
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2823
	.pot_clear = mv88e6xxx_g2_pot_clear,
2824
	.reset = mv88e6352_g1_reset,
2825
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2826
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2827
	.serdes_power = mv88e6352_serdes_power,
2828 2829
};

2830
static const struct mv88e6xxx_ops mv88e6290_ops = {
2831
	/* MV88E6XXX_FAMILY_6390 */
2832
	.irl_init_all = mv88e6390_g2_irl_init_all,
2833 2834
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
2835 2836 2837 2838 2839 2840 2841
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
2842
	.port_tag_remap = mv88e6390_port_tag_remap,
2843
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2844
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2845
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2846
	.port_pause_limit = mv88e6390_port_pause_limit,
2847
	.port_set_cmode = mv88e6390x_port_set_cmode,
2848
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2849
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2850
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
2851
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2852 2853
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
2854
	.stats_get_stats = mv88e6390_stats_get_stats,
2855 2856
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
2857
	.watchdog_ops = &mv88e6390_watchdog_ops,
2858
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2859
	.pot_clear = mv88e6xxx_g2_pot_clear,
2860
	.reset = mv88e6352_g1_reset,
2861 2862
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2863
	.serdes_power = mv88e6390_serdes_power,
2864 2865
};

2866
static const struct mv88e6xxx_ops mv88e6320_ops = {
2867
	/* MV88E6XXX_FAMILY_6320 */
2868
	.irl_init_all = mv88e6352_g2_irl_init_all,
2869 2870
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
2871
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2872 2873
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2874
	.port_set_link = mv88e6xxx_port_set_link,
2875
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2876
	.port_set_speed = mv88e6185_port_set_speed,
2877
	.port_tag_remap = mv88e6095_port_tag_remap,
2878
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2879
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2880
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2881
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2882
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2883
	.port_pause_limit = mv88e6097_port_pause_limit,
2884
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2885
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2886
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2887
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2888 2889
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
2890
	.stats_get_stats = mv88e6320_stats_get_stats,
2891 2892
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2893
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2894
	.pot_clear = mv88e6xxx_g2_pot_clear,
2895
	.reset = mv88e6352_g1_reset,
2896
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
2897
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2898 2899 2900
};

static const struct mv88e6xxx_ops mv88e6321_ops = {
2901
	/* MV88E6XXX_FAMILY_6320 */
2902
	.irl_init_all = mv88e6352_g2_irl_init_all,
2903 2904
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
2905
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2906 2907
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2908
	.port_set_link = mv88e6xxx_port_set_link,
2909
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2910
	.port_set_speed = mv88e6185_port_set_speed,
2911
	.port_tag_remap = mv88e6095_port_tag_remap,
2912
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2913
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2914
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2915
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2916
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2917
	.port_pause_limit = mv88e6097_port_pause_limit,
2918
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2919
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2920
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2921
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2922 2923
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
2924
	.stats_get_stats = mv88e6320_stats_get_stats,
2925 2926
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2927
	.reset = mv88e6352_g1_reset,
2928
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
2929
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2930 2931
};

2932 2933
static const struct mv88e6xxx_ops mv88e6341_ops = {
	/* MV88E6XXX_FAMILY_6341 */
2934
	.irl_init_all = mv88e6352_g2_irl_init_all,
2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
	.port_tag_remap = mv88e6095_port_tag_remap,
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2948
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2949
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2950
	.port_pause_limit = mv88e6097_port_pause_limit,
2951 2952 2953
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
2954
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2955 2956 2957
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
	.stats_get_stats = mv88e6390_stats_get_stats,
2958 2959
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
2960 2961
	.watchdog_ops = &mv88e6390_watchdog_ops,
	.mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
2962
	.pot_clear = mv88e6xxx_g2_pot_clear,
2963
	.reset = mv88e6352_g1_reset,
2964
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2965
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2966 2967
};

2968
static const struct mv88e6xxx_ops mv88e6350_ops = {
2969
	/* MV88E6XXX_FAMILY_6351 */
2970
	.irl_init_all = mv88e6352_g2_irl_init_all,
2971
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2972 2973
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2974
	.port_set_link = mv88e6xxx_port_set_link,
2975
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2976
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2977
	.port_set_speed = mv88e6185_port_set_speed,
2978
	.port_tag_remap = mv88e6095_port_tag_remap,
2979
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2980
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2981
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2982
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2983
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2984
	.port_pause_limit = mv88e6097_port_pause_limit,
2985
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2986
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2987
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2988
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2989 2990
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2991
	.stats_get_stats = mv88e6095_stats_get_stats,
2992 2993
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2994
	.watchdog_ops = &mv88e6097_watchdog_ops,
2995
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2996
	.pot_clear = mv88e6xxx_g2_pot_clear,
2997
	.reset = mv88e6352_g1_reset,
2998
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2999
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3000 3001 3002
};

static const struct mv88e6xxx_ops mv88e6351_ops = {
3003
	/* MV88E6XXX_FAMILY_6351 */
3004
	.irl_init_all = mv88e6352_g2_irl_init_all,
3005
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3006 3007
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3008
	.port_set_link = mv88e6xxx_port_set_link,
3009
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3010
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3011
	.port_set_speed = mv88e6185_port_set_speed,
3012
	.port_tag_remap = mv88e6095_port_tag_remap,
3013
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3014
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3015
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3016
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3017
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3018
	.port_pause_limit = mv88e6097_port_pause_limit,
3019
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3020
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3021
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3022
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3023 3024
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
3025
	.stats_get_stats = mv88e6095_stats_get_stats,
3026 3027
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3028
	.watchdog_ops = &mv88e6097_watchdog_ops,
3029
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3030
	.pot_clear = mv88e6xxx_g2_pot_clear,
3031
	.reset = mv88e6352_g1_reset,
3032
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3033
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3034 3035 3036
};

static const struct mv88e6xxx_ops mv88e6352_ops = {
3037
	/* MV88E6XXX_FAMILY_6352 */
3038
	.irl_init_all = mv88e6352_g2_irl_init_all,
3039 3040
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
3041
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3042 3043
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3044
	.port_set_link = mv88e6xxx_port_set_link,
3045
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3046
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3047
	.port_set_speed = mv88e6352_port_set_speed,
3048
	.port_tag_remap = mv88e6095_port_tag_remap,
3049
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3050
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3051
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3052
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3053
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3054
	.port_pause_limit = mv88e6097_port_pause_limit,
3055
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3056
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3057
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3058
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3059 3060
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
3061
	.stats_get_stats = mv88e6095_stats_get_stats,
3062 3063
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3064
	.watchdog_ops = &mv88e6097_watchdog_ops,
3065
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3066
	.pot_clear = mv88e6xxx_g2_pot_clear,
3067
	.reset = mv88e6352_g1_reset,
3068
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3069
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3070
	.serdes_power = mv88e6352_serdes_power,
3071 3072
};

3073
static const struct mv88e6xxx_ops mv88e6390_ops = {
3074
	/* MV88E6XXX_FAMILY_6390 */
3075
	.irl_init_all = mv88e6390_g2_irl_init_all,
3076 3077
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3078 3079 3080 3081 3082 3083 3084
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
3085
	.port_tag_remap = mv88e6390_port_tag_remap,
3086
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3087
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3088
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3089
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3090
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3091
	.port_pause_limit = mv88e6390_port_pause_limit,
3092
	.port_set_cmode = mv88e6390x_port_set_cmode,
3093
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3094
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3095
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3096
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3097 3098
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3099
	.stats_get_stats = mv88e6390_stats_get_stats,
3100 3101
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3102
	.watchdog_ops = &mv88e6390_watchdog_ops,
3103
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3104
	.pot_clear = mv88e6xxx_g2_pot_clear,
3105
	.reset = mv88e6352_g1_reset,
3106 3107
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3108
	.serdes_power = mv88e6390_serdes_power,
3109 3110 3111
};

static const struct mv88e6xxx_ops mv88e6390x_ops = {
3112
	/* MV88E6XXX_FAMILY_6390 */
3113
	.irl_init_all = mv88e6390_g2_irl_init_all,
3114 3115
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3116 3117 3118 3119 3120 3121 3122
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390x_port_set_speed,
3123
	.port_tag_remap = mv88e6390_port_tag_remap,
3124
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3125
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3126
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3127
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3128
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3129
	.port_pause_limit = mv88e6390_port_pause_limit,
3130
	.port_set_cmode = mv88e6390x_port_set_cmode,
3131
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3132
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3133
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3134
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3135 3136
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3137
	.stats_get_stats = mv88e6390_stats_get_stats,
3138 3139
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3140
	.watchdog_ops = &mv88e6390_watchdog_ops,
3141
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3142
	.pot_clear = mv88e6xxx_g2_pot_clear,
3143
	.reset = mv88e6352_g1_reset,
3144 3145
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3146
	.serdes_power = mv88e6390_serdes_power,
3147 3148
};

3149 3150
static const struct mv88e6xxx_info mv88e6xxx_table[] = {
	[MV88E6085] = {
3151
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
3152 3153 3154 3155
		.family = MV88E6XXX_FAMILY_6097,
		.name = "Marvell 88E6085",
		.num_databases = 4096,
		.num_ports = 10,
3156
		.max_vid = 4095,
3157
		.port_base_addr = 0x10,
3158
		.global1_addr = 0x1b,
3159
		.global2_addr = 0x1c,
3160
		.age_time_coeff = 15000,
3161
		.g1_irqs = 8,
3162
		.g2_irqs = 10,
3163
		.atu_move_port_mask = 0xf,
3164
		.pvt = true,
3165
		.multi_chip = true,
3166
		.tag_protocol = DSA_TAG_PROTO_DSA,
3167
		.ops = &mv88e6085_ops,
3168 3169 3170
	},

	[MV88E6095] = {
3171
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
3172 3173 3174 3175
		.family = MV88E6XXX_FAMILY_6095,
		.name = "Marvell 88E6095/88E6095F",
		.num_databases = 256,
		.num_ports = 11,
3176
		.max_vid = 4095,
3177
		.port_base_addr = 0x10,
3178
		.global1_addr = 0x1b,
3179
		.global2_addr = 0x1c,
3180
		.age_time_coeff = 15000,
3181
		.g1_irqs = 8,
3182
		.atu_move_port_mask = 0xf,
3183
		.multi_chip = true,
3184
		.tag_protocol = DSA_TAG_PROTO_DSA,
3185
		.ops = &mv88e6095_ops,
3186 3187
	},

3188
	[MV88E6097] = {
3189
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
3190 3191 3192 3193
		.family = MV88E6XXX_FAMILY_6097,
		.name = "Marvell 88E6097/88E6097F",
		.num_databases = 4096,
		.num_ports = 11,
3194
		.max_vid = 4095,
3195 3196
		.port_base_addr = 0x10,
		.global1_addr = 0x1b,
3197
		.global2_addr = 0x1c,
3198
		.age_time_coeff = 15000,
3199
		.g1_irqs = 8,
3200
		.g2_irqs = 10,
3201
		.atu_move_port_mask = 0xf,
3202
		.pvt = true,
3203
		.multi_chip = true,
3204
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3205 3206 3207
		.ops = &mv88e6097_ops,
	},

3208
	[MV88E6123] = {
3209
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
3210 3211 3212 3213
		.family = MV88E6XXX_FAMILY_6165,
		.name = "Marvell 88E6123",
		.num_databases = 4096,
		.num_ports = 3,
3214
		.max_vid = 4095,
3215
		.port_base_addr = 0x10,
3216
		.global1_addr = 0x1b,
3217
		.global2_addr = 0x1c,
3218
		.age_time_coeff = 15000,
3219
		.g1_irqs = 9,
3220
		.g2_irqs = 10,
3221
		.atu_move_port_mask = 0xf,
3222
		.pvt = true,
3223
		.multi_chip = true,
3224
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3225
		.ops = &mv88e6123_ops,
3226 3227 3228
	},

	[MV88E6131] = {
3229
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
3230 3231 3232 3233
		.family = MV88E6XXX_FAMILY_6185,
		.name = "Marvell 88E6131",
		.num_databases = 256,
		.num_ports = 8,
3234
		.max_vid = 4095,
3235
		.port_base_addr = 0x10,
3236
		.global1_addr = 0x1b,
3237
		.global2_addr = 0x1c,
3238
		.age_time_coeff = 15000,
3239
		.g1_irqs = 9,
3240
		.atu_move_port_mask = 0xf,
3241
		.multi_chip = true,
3242
		.tag_protocol = DSA_TAG_PROTO_DSA,
3243
		.ops = &mv88e6131_ops,
3244 3245
	},

3246
	[MV88E6141] = {
3247
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
3248 3249 3250 3251
		.family = MV88E6XXX_FAMILY_6341,
		.name = "Marvell 88E6341",
		.num_databases = 4096,
		.num_ports = 6,
3252
		.max_vid = 4095,
3253 3254
		.port_base_addr = 0x10,
		.global1_addr = 0x1b,
3255
		.global2_addr = 0x1c,
3256 3257
		.age_time_coeff = 3750,
		.atu_move_port_mask = 0x1f,
3258
		.g2_irqs = 10,
3259
		.pvt = true,
3260
		.multi_chip = true,
3261 3262 3263 3264
		.tag_protocol = DSA_TAG_PROTO_EDSA,
		.ops = &mv88e6141_ops,
	},

3265
	[MV88E6161] = {
3266
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
3267 3268 3269 3270
		.family = MV88E6XXX_FAMILY_6165,
		.name = "Marvell 88E6161",
		.num_databases = 4096,
		.num_ports = 6,
3271
		.max_vid = 4095,
3272
		.port_base_addr = 0x10,
3273
		.global1_addr = 0x1b,
3274
		.global2_addr = 0x1c,
3275
		.age_time_coeff = 15000,
3276
		.g1_irqs = 9,
3277
		.g2_irqs = 10,
3278
		.atu_move_port_mask = 0xf,
3279
		.pvt = true,
3280
		.multi_chip = true,
3281
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3282
		.ops = &mv88e6161_ops,
3283 3284 3285
	},

	[MV88E6165] = {
3286
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
3287 3288 3289 3290
		.family = MV88E6XXX_FAMILY_6165,
		.name = "Marvell 88E6165",
		.num_databases = 4096,
		.num_ports = 6,
3291
		.max_vid = 4095,
3292
		.port_base_addr = 0x10,
3293
		.global1_addr = 0x1b,
3294
		.global2_addr = 0x1c,
3295
		.age_time_coeff = 15000,
3296
		.g1_irqs = 9,
3297
		.g2_irqs = 10,
3298
		.atu_move_port_mask = 0xf,
3299
		.pvt = true,
3300
		.multi_chip = true,
3301
		.tag_protocol = DSA_TAG_PROTO_DSA,
3302
		.ops = &mv88e6165_ops,
3303 3304 3305
	},

	[MV88E6171] = {
3306
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
3307 3308 3309 3310
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6171",
		.num_databases = 4096,
		.num_ports = 7,
3311
		.max_vid = 4095,
3312
		.port_base_addr = 0x10,
3313
		.global1_addr = 0x1b,
3314
		.global2_addr = 0x1c,
3315
		.age_time_coeff = 15000,
3316
		.g1_irqs = 9,
3317
		.g2_irqs = 10,
3318
		.atu_move_port_mask = 0xf,
3319
		.pvt = true,
3320
		.multi_chip = true,
3321
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3322
		.ops = &mv88e6171_ops,
3323 3324 3325
	},

	[MV88E6172] = {
3326
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
3327 3328 3329 3330
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6172",
		.num_databases = 4096,
		.num_ports = 7,
3331
		.max_vid = 4095,
3332
		.port_base_addr = 0x10,
3333
		.global1_addr = 0x1b,
3334
		.global2_addr = 0x1c,
3335
		.age_time_coeff = 15000,
3336
		.g1_irqs = 9,
3337
		.g2_irqs = 10,
3338
		.atu_move_port_mask = 0xf,
3339
		.pvt = true,
3340
		.multi_chip = true,
3341
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3342
		.ops = &mv88e6172_ops,
3343 3344 3345
	},

	[MV88E6175] = {
3346
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
3347 3348 3349 3350
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6175",
		.num_databases = 4096,
		.num_ports = 7,
3351
		.max_vid = 4095,
3352
		.port_base_addr = 0x10,
3353
		.global1_addr = 0x1b,
3354
		.global2_addr = 0x1c,
3355
		.age_time_coeff = 15000,
3356
		.g1_irqs = 9,
3357
		.g2_irqs = 10,
3358
		.atu_move_port_mask = 0xf,
3359
		.pvt = true,
3360
		.multi_chip = true,
3361
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3362
		.ops = &mv88e6175_ops,
3363 3364 3365
	},

	[MV88E6176] = {
3366
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
3367 3368 3369 3370
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6176",
		.num_databases = 4096,
		.num_ports = 7,
3371
		.max_vid = 4095,
3372
		.port_base_addr = 0x10,
3373
		.global1_addr = 0x1b,
3374
		.global2_addr = 0x1c,
3375
		.age_time_coeff = 15000,
3376
		.g1_irqs = 9,
3377
		.g2_irqs = 10,
3378
		.atu_move_port_mask = 0xf,
3379
		.pvt = true,
3380
		.multi_chip = true,
3381
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3382
		.ops = &mv88e6176_ops,
3383 3384 3385
	},

	[MV88E6185] = {
3386
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
3387 3388 3389 3390
		.family = MV88E6XXX_FAMILY_6185,
		.name = "Marvell 88E6185",
		.num_databases = 256,
		.num_ports = 10,
3391
		.max_vid = 4095,
3392
		.port_base_addr = 0x10,
3393
		.global1_addr = 0x1b,
3394
		.global2_addr = 0x1c,
3395
		.age_time_coeff = 15000,
3396
		.g1_irqs = 8,
3397
		.atu_move_port_mask = 0xf,
3398
		.multi_chip = true,
3399
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3400
		.ops = &mv88e6185_ops,
3401 3402
	},

3403
	[MV88E6190] = {
3404
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
3405 3406 3407 3408
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6190",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3409
		.max_vid = 8191,
3410 3411
		.port_base_addr = 0x0,
		.global1_addr = 0x1b,
3412
		.global2_addr = 0x1c,
3413
		.tag_protocol = DSA_TAG_PROTO_DSA,
3414
		.age_time_coeff = 3750,
3415
		.g1_irqs = 9,
3416
		.g2_irqs = 14,
3417
		.pvt = true,
3418
		.multi_chip = true,
3419
		.atu_move_port_mask = 0x1f,
3420 3421 3422 3423
		.ops = &mv88e6190_ops,
	},

	[MV88E6190X] = {
3424
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
3425 3426 3427 3428
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6190X",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3429
		.max_vid = 8191,
3430 3431
		.port_base_addr = 0x0,
		.global1_addr = 0x1b,
3432
		.global2_addr = 0x1c,
3433
		.age_time_coeff = 3750,
3434
		.g1_irqs = 9,
3435
		.g2_irqs = 14,
3436
		.atu_move_port_mask = 0x1f,
3437
		.pvt = true,
3438
		.multi_chip = true,
3439
		.tag_protocol = DSA_TAG_PROTO_DSA,
3440 3441 3442 3443
		.ops = &mv88e6190x_ops,
	},

	[MV88E6191] = {
3444
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
3445 3446 3447 3448
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6191",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3449
		.max_vid = 8191,
3450 3451
		.port_base_addr = 0x0,
		.global1_addr = 0x1b,
3452
		.global2_addr = 0x1c,
3453
		.age_time_coeff = 3750,
3454
		.g1_irqs = 9,
3455
		.g2_irqs = 14,
3456
		.atu_move_port_mask = 0x1f,
3457
		.pvt = true,
3458
		.multi_chip = true,
3459
		.tag_protocol = DSA_TAG_PROTO_DSA,
3460
		.ops = &mv88e6191_ops,
3461 3462
	},

3463
	[MV88E6240] = {
3464
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
3465 3466 3467 3468
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6240",
		.num_databases = 4096,
		.num_ports = 7,
3469
		.max_vid = 4095,
3470
		.port_base_addr = 0x10,
3471
		.global1_addr = 0x1b,
3472
		.global2_addr = 0x1c,
3473
		.age_time_coeff = 15000,
3474
		.g1_irqs = 9,
3475
		.g2_irqs = 10,
3476
		.atu_move_port_mask = 0xf,
3477
		.pvt = true,
3478
		.multi_chip = true,
3479
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3480
		.ops = &mv88e6240_ops,
3481 3482
	},

3483
	[MV88E6290] = {
3484
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
3485 3486 3487 3488
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6290",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3489
		.max_vid = 8191,
3490 3491
		.port_base_addr = 0x0,
		.global1_addr = 0x1b,
3492
		.global2_addr = 0x1c,
3493
		.age_time_coeff = 3750,
3494
		.g1_irqs = 9,
3495
		.g2_irqs = 14,
3496
		.atu_move_port_mask = 0x1f,
3497
		.pvt = true,
3498
		.multi_chip = true,
3499
		.tag_protocol = DSA_TAG_PROTO_DSA,
3500 3501 3502
		.ops = &mv88e6290_ops,
	},

3503
	[MV88E6320] = {
3504
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
3505 3506 3507 3508
		.family = MV88E6XXX_FAMILY_6320,
		.name = "Marvell 88E6320",
		.num_databases = 4096,
		.num_ports = 7,
3509
		.max_vid = 4095,
3510
		.port_base_addr = 0x10,
3511
		.global1_addr = 0x1b,
3512
		.global2_addr = 0x1c,
3513
		.age_time_coeff = 15000,
3514
		.g1_irqs = 8,
3515
		.atu_move_port_mask = 0xf,
3516
		.pvt = true,
3517
		.multi_chip = true,
3518
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3519
		.ops = &mv88e6320_ops,
3520 3521 3522
	},

	[MV88E6321] = {
3523
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
3524 3525 3526 3527
		.family = MV88E6XXX_FAMILY_6320,
		.name = "Marvell 88E6321",
		.num_databases = 4096,
		.num_ports = 7,
3528
		.max_vid = 4095,
3529
		.port_base_addr = 0x10,
3530
		.global1_addr = 0x1b,
3531
		.global2_addr = 0x1c,
3532
		.age_time_coeff = 15000,
3533
		.g1_irqs = 8,
3534
		.atu_move_port_mask = 0xf,
3535
		.multi_chip = true,
3536
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3537
		.ops = &mv88e6321_ops,
3538 3539
	},

3540
	[MV88E6341] = {
3541
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3542 3543 3544 3545
		.family = MV88E6XXX_FAMILY_6341,
		.name = "Marvell 88E6341",
		.num_databases = 4096,
		.num_ports = 6,
3546
		.max_vid = 4095,
3547 3548
		.port_base_addr = 0x10,
		.global1_addr = 0x1b,
3549
		.global2_addr = 0x1c,
3550
		.age_time_coeff = 3750,
3551
		.atu_move_port_mask = 0x1f,
3552
		.g2_irqs = 10,
3553
		.pvt = true,
3554
		.multi_chip = true,
3555 3556 3557 3558
		.tag_protocol = DSA_TAG_PROTO_EDSA,
		.ops = &mv88e6341_ops,
	},

3559
	[MV88E6350] = {
3560
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
3561 3562 3563 3564
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6350",
		.num_databases = 4096,
		.num_ports = 7,
3565
		.max_vid = 4095,
3566
		.port_base_addr = 0x10,
3567
		.global1_addr = 0x1b,
3568
		.global2_addr = 0x1c,
3569
		.age_time_coeff = 15000,
3570
		.g1_irqs = 9,
3571
		.g2_irqs = 10,
3572
		.atu_move_port_mask = 0xf,
3573
		.pvt = true,
3574
		.multi_chip = true,
3575
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3576
		.ops = &mv88e6350_ops,
3577 3578 3579
	},

	[MV88E6351] = {
3580
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
3581 3582 3583 3584
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6351",
		.num_databases = 4096,
		.num_ports = 7,
3585
		.max_vid = 4095,
3586
		.port_base_addr = 0x10,
3587
		.global1_addr = 0x1b,
3588
		.global2_addr = 0x1c,
3589
		.age_time_coeff = 15000,
3590
		.g1_irqs = 9,
3591
		.g2_irqs = 10,
3592
		.atu_move_port_mask = 0xf,
3593
		.pvt = true,
3594
		.multi_chip = true,
3595
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3596
		.ops = &mv88e6351_ops,
3597 3598 3599
	},

	[MV88E6352] = {
3600
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
3601 3602 3603 3604
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6352",
		.num_databases = 4096,
		.num_ports = 7,
3605
		.max_vid = 4095,
3606
		.port_base_addr = 0x10,
3607
		.global1_addr = 0x1b,
3608
		.global2_addr = 0x1c,
3609
		.age_time_coeff = 15000,
3610
		.g1_irqs = 9,
3611
		.g2_irqs = 10,
3612
		.atu_move_port_mask = 0xf,
3613
		.pvt = true,
3614
		.multi_chip = true,
3615
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3616
		.ops = &mv88e6352_ops,
3617
	},
3618
	[MV88E6390] = {
3619
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
3620 3621 3622 3623
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6390",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3624
		.max_vid = 8191,
3625 3626
		.port_base_addr = 0x0,
		.global1_addr = 0x1b,
3627
		.global2_addr = 0x1c,
3628
		.age_time_coeff = 3750,
3629
		.g1_irqs = 9,
3630
		.g2_irqs = 14,
3631
		.atu_move_port_mask = 0x1f,
3632
		.pvt = true,
3633
		.multi_chip = true,
3634
		.tag_protocol = DSA_TAG_PROTO_DSA,
3635 3636 3637
		.ops = &mv88e6390_ops,
	},
	[MV88E6390X] = {
3638
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
3639 3640 3641 3642
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6390X",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3643
		.max_vid = 8191,
3644 3645
		.port_base_addr = 0x0,
		.global1_addr = 0x1b,
3646
		.global2_addr = 0x1c,
3647
		.age_time_coeff = 3750,
3648
		.g1_irqs = 9,
3649
		.g2_irqs = 14,
3650
		.atu_move_port_mask = 0x1f,
3651
		.pvt = true,
3652
		.multi_chip = true,
3653
		.tag_protocol = DSA_TAG_PROTO_DSA,
3654 3655
		.ops = &mv88e6390x_ops,
	},
3656 3657
};

3658
static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
3659
{
3660
	int i;
3661

3662 3663 3664
	for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
		if (mv88e6xxx_table[i].prod_num == prod_num)
			return &mv88e6xxx_table[i];
3665 3666 3667 3668

	return NULL;
}

3669
static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
3670 3671
{
	const struct mv88e6xxx_info *info;
3672 3673 3674
	unsigned int prod_num, rev;
	u16 id;
	int err;
3675

3676
	mutex_lock(&chip->reg_lock);
3677
	err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
3678 3679 3680
	mutex_unlock(&chip->reg_lock);
	if (err)
		return err;
3681

3682 3683
	prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
	rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
3684 3685 3686 3687 3688

	info = mv88e6xxx_lookup_info(prod_num);
	if (!info)
		return -ENODEV;

3689
	/* Update the compatible info with the probed one */
3690
	chip->info = info;
3691

3692 3693 3694 3695
	err = mv88e6xxx_g2_require(chip);
	if (err)
		return err;

3696 3697
	dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
		 chip->info->prod_num, chip->info->name, rev);
3698 3699 3700 3701

	return 0;
}

3702
static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
3703
{
3704
	struct mv88e6xxx_chip *chip;
3705

3706 3707
	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
	if (!chip)
3708 3709
		return NULL;

3710
	chip->dev = dev;
3711

3712
	mutex_init(&chip->reg_lock);
3713
	INIT_LIST_HEAD(&chip->mdios);
3714

3715
	return chip;
3716 3717
}

3718
static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
3719 3720
			      struct mii_bus *bus, int sw_addr)
{
3721
	if (sw_addr == 0)
3722
		chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
3723
	else if (chip->info->multi_chip)
3724
		chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
3725 3726 3727
	else
		return -EINVAL;

3728 3729
	chip->bus = bus;
	chip->sw_addr = sw_addr;
3730 3731 3732 3733

	return 0;
}

3734 3735
static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
							int port)
3736
{
V
Vivien Didelot 已提交
3737
	struct mv88e6xxx_chip *chip = ds->priv;
3738

3739
	return chip->info->tag_protocol;
3740 3741
}

3742 3743 3744
static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
				       struct device *host_dev, int sw_addr,
				       void **priv)
3745
{
3746
	struct mv88e6xxx_chip *chip;
3747
	struct mii_bus *bus;
3748
	int err;
3749

3750
	bus = dsa_host_dev_to_mii_bus(host_dev);
3751 3752 3753
	if (!bus)
		return NULL;

3754 3755
	chip = mv88e6xxx_alloc_chip(dsa_dev);
	if (!chip)
3756 3757
		return NULL;

3758
	/* Legacy SMI probing will only support chips similar to 88E6085 */
3759
	chip->info = &mv88e6xxx_table[MV88E6085];
3760

3761
	err = mv88e6xxx_smi_init(chip, bus, sw_addr);
3762 3763 3764
	if (err)
		goto free;

3765
	err = mv88e6xxx_detect(chip);
3766
	if (err)
3767
		goto free;
3768

3769 3770 3771 3772 3773 3774
	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_switch_reset(chip);
	mutex_unlock(&chip->reg_lock);
	if (err)
		goto free;

3775 3776
	mv88e6xxx_phy_init(chip);

3777
	err = mv88e6xxx_mdios_register(chip, NULL);
3778
	if (err)
3779
		goto free;
3780

3781
	*priv = chip;
3782

3783
	return chip->info->name;
3784
free:
3785
	devm_kfree(dsa_dev, chip);
3786 3787

	return NULL;
3788 3789
}

3790 3791 3792 3793 3794 3795 3796 3797 3798 3799 3800 3801 3802 3803 3804
static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
				      const struct switchdev_obj_port_mdb *mdb,
				      struct switchdev_trans *trans)
{
	/* We don't need any dynamic resource from the kernel (yet),
	 * so skip the prepare phase.
	 */

	return 0;
}

static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
				   const struct switchdev_obj_port_mdb *mdb,
				   struct switchdev_trans *trans)
{
V
Vivien Didelot 已提交
3805
	struct mv88e6xxx_chip *chip = ds->priv;
3806 3807 3808

	mutex_lock(&chip->reg_lock);
	if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3809
					 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
3810 3811
		dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
			port);
3812 3813 3814 3815 3816 3817
	mutex_unlock(&chip->reg_lock);
}

static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
				  const struct switchdev_obj_port_mdb *mdb)
{
V
Vivien Didelot 已提交
3818
	struct mv88e6xxx_chip *chip = ds->priv;
3819 3820 3821 3822
	int err;

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3823
					   MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
3824 3825 3826 3827 3828
	mutex_unlock(&chip->reg_lock);

	return err;
}

3829
static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
3830
	.probe			= mv88e6xxx_drv_probe,
3831
	.get_tag_protocol	= mv88e6xxx_get_tag_protocol,
3832 3833 3834 3835 3836
	.setup			= mv88e6xxx_setup,
	.adjust_link		= mv88e6xxx_adjust_link,
	.get_strings		= mv88e6xxx_get_strings,
	.get_ethtool_stats	= mv88e6xxx_get_ethtool_stats,
	.get_sset_count		= mv88e6xxx_get_sset_count,
3837 3838
	.port_enable		= mv88e6xxx_port_enable,
	.port_disable		= mv88e6xxx_port_disable,
V
Vivien Didelot 已提交
3839 3840
	.get_mac_eee		= mv88e6xxx_get_mac_eee,
	.set_mac_eee		= mv88e6xxx_set_mac_eee,
3841
	.get_eeprom_len		= mv88e6xxx_get_eeprom_len,
3842 3843 3844 3845
	.get_eeprom		= mv88e6xxx_get_eeprom,
	.set_eeprom		= mv88e6xxx_set_eeprom,
	.get_regs_len		= mv88e6xxx_get_regs_len,
	.get_regs		= mv88e6xxx_get_regs,
3846
	.set_ageing_time	= mv88e6xxx_set_ageing_time,
3847 3848 3849
	.port_bridge_join	= mv88e6xxx_port_bridge_join,
	.port_bridge_leave	= mv88e6xxx_port_bridge_leave,
	.port_stp_state_set	= mv88e6xxx_port_stp_state_set,
3850
	.port_fast_age		= mv88e6xxx_port_fast_age,
3851 3852 3853 3854 3855 3856 3857
	.port_vlan_filtering	= mv88e6xxx_port_vlan_filtering,
	.port_vlan_prepare	= mv88e6xxx_port_vlan_prepare,
	.port_vlan_add		= mv88e6xxx_port_vlan_add,
	.port_vlan_del		= mv88e6xxx_port_vlan_del,
	.port_fdb_add           = mv88e6xxx_port_fdb_add,
	.port_fdb_del           = mv88e6xxx_port_fdb_del,
	.port_fdb_dump          = mv88e6xxx_port_fdb_dump,
3858 3859 3860
	.port_mdb_prepare       = mv88e6xxx_port_mdb_prepare,
	.port_mdb_add           = mv88e6xxx_port_mdb_add,
	.port_mdb_del           = mv88e6xxx_port_mdb_del,
3861 3862
	.crosschip_bridge_join	= mv88e6xxx_crosschip_bridge_join,
	.crosschip_bridge_leave	= mv88e6xxx_crosschip_bridge_leave,
3863 3864
};

3865 3866 3867 3868
static struct dsa_switch_driver mv88e6xxx_switch_drv = {
	.ops			= &mv88e6xxx_switch_ops,
};

3869
static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
3870
{
3871
	struct device *dev = chip->dev;
3872 3873
	struct dsa_switch *ds;

3874
	ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip));
3875 3876 3877
	if (!ds)
		return -ENOMEM;

3878
	ds->priv = chip;
3879
	ds->ops = &mv88e6xxx_switch_ops;
3880 3881
	ds->ageing_time_min = chip->info->age_time_coeff;
	ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
3882 3883 3884

	dev_set_drvdata(dev, ds);

3885
	return dsa_register_switch(ds);
3886 3887
}

3888
static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
3889
{
3890
	dsa_unregister_switch(chip->ds);
3891 3892
}

3893
static int mv88e6xxx_probe(struct mdio_device *mdiodev)
3894
{
3895
	struct device *dev = &mdiodev->dev;
3896
	struct device_node *np = dev->of_node;
3897
	const struct mv88e6xxx_info *compat_info;
3898
	struct mv88e6xxx_chip *chip;
3899
	u32 eeprom_len;
3900
	int err;
3901

3902 3903 3904 3905
	compat_info = of_device_get_match_data(dev);
	if (!compat_info)
		return -EINVAL;

3906 3907
	chip = mv88e6xxx_alloc_chip(dev);
	if (!chip)
3908 3909
		return -ENOMEM;

3910
	chip->info = compat_info;
3911

3912
	err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
3913 3914
	if (err)
		return err;
3915

3916 3917 3918 3919
	chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
	if (IS_ERR(chip->reset))
		return PTR_ERR(chip->reset);

3920
	err = mv88e6xxx_detect(chip);
3921 3922
	if (err)
		return err;
3923

3924 3925
	mv88e6xxx_phy_init(chip);

3926
	if (chip->info->ops->get_eeprom &&
3927
	    !of_property_read_u32(np, "eeprom-length", &eeprom_len))
3928
		chip->eeprom_len = eeprom_len;
3929

3930 3931 3932 3933 3934 3935 3936 3937 3938 3939 3940 3941 3942 3943 3944 3945 3946 3947 3948 3949 3950 3951 3952 3953
	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_switch_reset(chip);
	mutex_unlock(&chip->reg_lock);
	if (err)
		goto out;

	chip->irq = of_irq_get(np, 0);
	if (chip->irq == -EPROBE_DEFER) {
		err = chip->irq;
		goto out;
	}

	if (chip->irq > 0) {
		/* Has to be performed before the MDIO bus is created,
		 * because the PHYs will link there interrupts to these
		 * interrupt controllers
		 */
		mutex_lock(&chip->reg_lock);
		err = mv88e6xxx_g1_irq_setup(chip);
		mutex_unlock(&chip->reg_lock);

		if (err)
			goto out;

3954
		if (chip->info->g2_irqs > 0) {
3955 3956 3957 3958 3959 3960
			err = mv88e6xxx_g2_irq_setup(chip);
			if (err)
				goto out_g1_irq;
		}
	}

3961
	err = mv88e6xxx_mdios_register(chip, np);
3962
	if (err)
3963
		goto out_g2_irq;
3964

3965
	err = mv88e6xxx_register_switch(chip);
3966 3967
	if (err)
		goto out_mdio;
3968

3969
	return 0;
3970 3971

out_mdio:
3972
	mv88e6xxx_mdios_unregister(chip);
3973
out_g2_irq:
3974
	if (chip->info->g2_irqs > 0 && chip->irq > 0)
3975 3976
		mv88e6xxx_g2_irq_free(chip);
out_g1_irq:
3977 3978
	if (chip->irq > 0) {
		mutex_lock(&chip->reg_lock);
3979
		mv88e6xxx_g1_irq_free(chip);
3980 3981
		mutex_unlock(&chip->reg_lock);
	}
3982 3983
out:
	return err;
3984
}
3985 3986 3987 3988

static void mv88e6xxx_remove(struct mdio_device *mdiodev)
{
	struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
V
Vivien Didelot 已提交
3989
	struct mv88e6xxx_chip *chip = ds->priv;
3990

3991
	mv88e6xxx_phy_destroy(chip);
3992
	mv88e6xxx_unregister_switch(chip);
3993
	mv88e6xxx_mdios_unregister(chip);
3994

3995
	if (chip->irq > 0) {
3996
		if (chip->info->g2_irqs > 0)
3997
			mv88e6xxx_g2_irq_free(chip);
3998
		mutex_lock(&chip->reg_lock);
3999
		mv88e6xxx_g1_irq_free(chip);
4000
		mutex_unlock(&chip->reg_lock);
4001
	}
4002 4003 4004
}

static const struct of_device_id mv88e6xxx_of_match[] = {
4005 4006 4007 4008
	{
		.compatible = "marvell,mv88e6085",
		.data = &mv88e6xxx_table[MV88E6085],
	},
4009 4010 4011 4012
	{
		.compatible = "marvell,mv88e6190",
		.data = &mv88e6xxx_table[MV88E6190],
	},
4013 4014 4015 4016 4017 4018 4019 4020 4021 4022 4023 4024 4025 4026 4027 4028
	{ /* sentinel */ },
};

MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);

static struct mdio_driver mv88e6xxx_driver = {
	.probe	= mv88e6xxx_probe,
	.remove = mv88e6xxx_remove,
	.mdiodrv.driver = {
		.name = "mv88e6085",
		.of_match_table = mv88e6xxx_of_match,
	},
};

static int __init mv88e6xxx_init(void)
{
4029
	register_switch_driver(&mv88e6xxx_switch_drv);
4030 4031
	return mdio_driver_register(&mv88e6xxx_driver);
}
4032 4033 4034 4035
module_init(mv88e6xxx_init);

static void __exit mv88e6xxx_cleanup(void)
{
4036
	mdio_driver_unregister(&mv88e6xxx_driver);
4037
	unregister_switch_driver(&mv88e6xxx_switch_drv);
4038 4039
}
module_exit(mv88e6xxx_cleanup);
4040 4041 4042 4043

MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
MODULE_LICENSE("GPL");