chip.c 119.8 KB
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/*
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 * Marvell 88e6xxx Ethernet switch single-chip support
 *
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 * Copyright (c) 2008 Marvell Semiconductor
 *
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 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
 *
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 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
 *	Vivien Didelot <vivien.didelot@savoirfairelinux.com>
 *
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 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

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#include <linux/delay.h>
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#include <linux/etherdevice.h>
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#include <linux/ethtool.h>
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#include <linux/if_bridge.h>
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#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
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#include <linux/jiffies.h>
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#include <linux/list.h>
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#include <linux/mdio.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/of_mdio.h>
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#include <linux/netdevice.h>
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#include <linux/gpio/consumer.h>
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#include <linux/phy.h>
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#include <net/dsa.h>
35

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#include "chip.h"
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#include "global1.h"
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#include "global2.h"
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#include "hwtstamp.h"
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#include "phy.h"
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#include "port.h"
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#include "ptp.h"
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#include "serdes.h"
44

45
static void assert_reg_lock(struct mv88e6xxx_chip *chip)
46
{
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	if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
		dev_err(chip->dev, "Switch registers lock not held!\n");
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		dump_stack();
	}
}

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/* The switch ADDR[4:1] configuration pins define the chip SMI device address
 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
 *
 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
 * is the only device connected to the SMI master. In this mode it responds to
 * all 32 possible SMI addresses, and thus maps directly the internal devices.
 *
 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
 * multiple devices to share the SMI interface. In this mode it responds to only
 * 2 registers, used to indirectly access the internal SMI devices.
63
 */
64

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static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
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			      int addr, int reg, u16 *val)
{
68
	if (!chip->smi_ops)
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		return -EOPNOTSUPP;

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	return chip->smi_ops->read(chip, addr, reg, val);
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}

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static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
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			       int addr, int reg, u16 val)
{
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	if (!chip->smi_ops)
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		return -EOPNOTSUPP;

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	return chip->smi_ops->write(chip, addr, reg, val);
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}

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static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
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					  int addr, int reg, u16 *val)
{
	int ret;

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	ret = mdiobus_read_nested(chip->bus, addr, reg);
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	if (ret < 0)
		return ret;

	*val = ret & 0xffff;

	return 0;
}

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static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
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					   int addr, int reg, u16 val)
{
	int ret;

102
	ret = mdiobus_write_nested(chip->bus, addr, reg, val);
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	if (ret < 0)
		return ret;

	return 0;
}

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static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
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	.read = mv88e6xxx_smi_single_chip_read,
	.write = mv88e6xxx_smi_single_chip_write,
};

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static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
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{
	int ret;
	int i;

	for (i = 0; i < 16; i++) {
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		ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
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		if (ret < 0)
			return ret;

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		if ((ret & SMI_CMD_BUSY) == 0)
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			return 0;
	}

	return -ETIMEDOUT;
}

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static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
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					 int addr, int reg, u16 *val)
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{
	int ret;

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	/* Wait for the bus to become free. */
137
	ret = mv88e6xxx_smi_multi_chip_wait(chip);
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	if (ret < 0)
		return ret;

141
	/* Transmit the read command. */
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	ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
143
				   SMI_CMD_OP_22_READ | (addr << 5) | reg);
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	if (ret < 0)
		return ret;

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	/* Wait for the read command to complete. */
148
	ret = mv88e6xxx_smi_multi_chip_wait(chip);
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	if (ret < 0)
		return ret;

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	/* Read the data. */
153
	ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
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	if (ret < 0)
		return ret;

157
	*val = ret & 0xffff;
158

159
	return 0;
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}

162
static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
163
					  int addr, int reg, u16 val)
164 165 166
{
	int ret;

167
	/* Wait for the bus to become free. */
168
	ret = mv88e6xxx_smi_multi_chip_wait(chip);
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	if (ret < 0)
		return ret;

172
	/* Transmit the data to write. */
173
	ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
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	if (ret < 0)
		return ret;

177
	/* Transmit the write command. */
178
	ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
179
				   SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
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	if (ret < 0)
		return ret;

183
	/* Wait for the write command to complete. */
184
	ret = mv88e6xxx_smi_multi_chip_wait(chip);
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	if (ret < 0)
		return ret;

	return 0;
}

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static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
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	.read = mv88e6xxx_smi_multi_chip_read,
	.write = mv88e6xxx_smi_multi_chip_write,
};

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int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
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{
	int err;

200
	assert_reg_lock(chip);
201

202
	err = mv88e6xxx_smi_read(chip, addr, reg, val);
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	if (err)
		return err;

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	dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
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		addr, reg, *val);

	return 0;
}

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int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
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{
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	int err;

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	assert_reg_lock(chip);
217

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	err = mv88e6xxx_smi_write(chip, addr, reg, val);
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	if (err)
		return err;

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	dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
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		addr, reg, val);

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	return 0;
}

228
struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
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{
	struct mv88e6xxx_mdio_bus *mdio_bus;

	mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
				    list);
	if (!mdio_bus)
		return NULL;

	return mdio_bus->bus;
}

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static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
{
	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int n = d->hwirq;

	chip->g1_irq.masked |= (1 << n);
}

static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
{
	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int n = d->hwirq;

	chip->g1_irq.masked &= ~(1 << n);
}

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static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
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{
	unsigned int nhandled = 0;
	unsigned int sub_irq;
	unsigned int n;
	u16 reg;
	int err;

	mutex_lock(&chip->reg_lock);
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	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
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	mutex_unlock(&chip->reg_lock);

	if (err)
		goto out;

	for (n = 0; n < chip->g1_irq.nirqs; ++n) {
		if (reg & (1 << n)) {
			sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
			handle_nested_irq(sub_irq);
			++nhandled;
		}
	}
out:
	return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
}

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static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
{
	struct mv88e6xxx_chip *chip = dev_id;

	return mv88e6xxx_g1_irq_thread_work(chip);
}

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static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
{
	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);

	mutex_lock(&chip->reg_lock);
}

static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
{
	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
	u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
	u16 reg;
	int err;

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	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
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	if (err)
		goto out;

	reg &= ~mask;
	reg |= (~chip->g1_irq.masked & mask);

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	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
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	if (err)
		goto out;

out:
	mutex_unlock(&chip->reg_lock);
}

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static const struct irq_chip mv88e6xxx_g1_irq_chip = {
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	.name			= "mv88e6xxx-g1",
	.irq_mask		= mv88e6xxx_g1_irq_mask,
	.irq_unmask		= mv88e6xxx_g1_irq_unmask,
	.irq_bus_lock		= mv88e6xxx_g1_irq_bus_lock,
	.irq_bus_sync_unlock	= mv88e6xxx_g1_irq_bus_sync_unlock,
};

static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
				       unsigned int irq,
				       irq_hw_number_t hwirq)
{
	struct mv88e6xxx_chip *chip = d->host_data;

	irq_set_chip_data(irq, d->host_data);
	irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
	irq_set_noprobe(irq);

	return 0;
}

static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
	.map	= mv88e6xxx_g1_irq_domain_map,
	.xlate	= irq_domain_xlate_twocell,
};

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static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
345 346
{
	int irq, virq;
347 348
	u16 mask;

349
	mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
350
	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
351
	mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
352

353
	for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
354
		virq = irq_find_mapping(chip->g1_irq.domain, irq);
355 356 357
		irq_dispose_mapping(virq);
	}

358
	irq_domain_remove(chip->g1_irq.domain);
359 360
}

361 362
static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
{
363
	mv88e6xxx_g1_irq_free_common(chip);
364 365 366 367 368

	free_irq(chip->irq, chip);
}

static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
369
{
370 371
	int err, irq, virq;
	u16 reg, mask;
372 373 374 375 376 377 378 379 380 381 382 383 384 385

	chip->g1_irq.nirqs = chip->info->g1_irqs;
	chip->g1_irq.domain = irq_domain_add_simple(
		NULL, chip->g1_irq.nirqs, 0,
		&mv88e6xxx_g1_irq_domain_ops, chip);
	if (!chip->g1_irq.domain)
		return -ENOMEM;

	for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
		irq_create_mapping(chip->g1_irq.domain, irq);

	chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
	chip->g1_irq.masked = ~0;

386
	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
387
	if (err)
388
		goto out_mapping;
389

390
	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
391

392
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
393
	if (err)
394
		goto out_disable;
395 396

	/* Reading the interrupt status clears (most of) them */
397
	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
398
	if (err)
399
		goto out_disable;
400 401 402

	return 0;

403
out_disable:
404
	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
405
	mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
406 407 408 409 410 411 412 413

out_mapping:
	for (irq = 0; irq < 16; irq++) {
		virq = irq_find_mapping(chip->g1_irq.domain, irq);
		irq_dispose_mapping(virq);
	}

	irq_domain_remove(chip->g1_irq.domain);
414 415 416 417

	return err;
}

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static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
{
	int err;

	err = mv88e6xxx_g1_irq_setup_common(chip);
	if (err)
		return err;

	err = request_threaded_irq(chip->irq, NULL,
				   mv88e6xxx_g1_irq_thread_fn,
428
				   IRQF_ONESHOT,
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				   dev_name(chip->dev), chip);
	if (err)
		mv88e6xxx_g1_irq_free_common(chip);

	return err;
}

static void mv88e6xxx_irq_poll(struct kthread_work *work)
{
	struct mv88e6xxx_chip *chip = container_of(work,
						   struct mv88e6xxx_chip,
						   irq_poll_work.work);
	mv88e6xxx_g1_irq_thread_work(chip);

	kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
				   msecs_to_jiffies(100));
}

static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
{
	int err;

	err = mv88e6xxx_g1_irq_setup_common(chip);
	if (err)
		return err;

	kthread_init_delayed_work(&chip->irq_poll_work,
				  mv88e6xxx_irq_poll);

	chip->kworker = kthread_create_worker(0, dev_name(chip->dev));
	if (IS_ERR(chip->kworker))
		return PTR_ERR(chip->kworker);

	kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
				   msecs_to_jiffies(100));

	return 0;
}

static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
{
470 471
	mv88e6xxx_g1_irq_free_common(chip);

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	kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
	kthread_destroy_worker(chip->kworker);
}

476
int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
477
{
478
	int i;
479

480
	for (i = 0; i < 16; i++) {
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		u16 val;
		int err;

		err = mv88e6xxx_read(chip, addr, reg, &val);
		if (err)
			return err;

		if (!(val & mask))
			return 0;

		usleep_range(1000, 2000);
	}

494
	dev_err(chip->dev, "Timeout while waiting for switch\n");
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	return -ETIMEDOUT;
}

498
/* Indirect write to single pointer-data register with an Update bit */
499
int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
500 501
{
	u16 val;
502
	int err;
503 504

	/* Wait until the previous operation is completed */
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	err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
	if (err)
		return err;
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	/* Set the Update bit to trigger a write operation */
	val = BIT(15) | update;

	return mv88e6xxx_write(chip, addr, reg, val);
}

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static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
				    int link, int speed, int duplex,
				    phy_interface_t mode)
{
	int err;

	if (!chip->info->ops->port_set_link)
		return 0;

	/* Port's MAC control must not be changed unless the link is down */
	err = chip->info->ops->port_set_link(chip, port, 0);
	if (err)
		return err;

	if (chip->info->ops->port_set_speed) {
		err = chip->info->ops->port_set_speed(chip, port, speed);
		if (err && err != -EOPNOTSUPP)
			goto restore_link;
	}

	if (chip->info->ops->port_set_duplex) {
		err = chip->info->ops->port_set_duplex(chip, port, duplex);
		if (err && err != -EOPNOTSUPP)
			goto restore_link;
	}

	if (chip->info->ops->port_set_rgmii_delay) {
		err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
		if (err && err != -EOPNOTSUPP)
			goto restore_link;
	}

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	if (chip->info->ops->port_set_cmode) {
		err = chip->info->ops->port_set_cmode(chip, port, mode);
		if (err && err != -EOPNOTSUPP)
			goto restore_link;
	}

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	err = 0;
restore_link:
	if (chip->info->ops->port_set_link(chip, port, link))
556
		dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
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	return err;
}

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/* We expect the switch to perform auto negotiation if there is a real
 * phy. However, in the case of a fixed link phy, we force the port
 * settings from the fixed link settings.
 */
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static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
				  struct phy_device *phydev)
567
{
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Vivien Didelot 已提交
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	struct mv88e6xxx_chip *chip = ds->priv;
569
	int err;
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	if (!phy_is_pseudo_fixed_link(phydev))
		return;

574
	mutex_lock(&chip->reg_lock);
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	err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
				       phydev->duplex, phydev->interface);
577
	mutex_unlock(&chip->reg_lock);
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	if (err && err != -EOPNOTSUPP)
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		dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
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}

583
static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
584
{
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	if (!chip->info->ops->stats_snapshot)
		return -EOPNOTSUPP;
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588
	return chip->info->ops->stats_snapshot(chip, port);
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}

591
static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
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	{ "in_good_octets",		8, 0x00, STATS_TYPE_BANK0, },
	{ "in_bad_octets",		4, 0x02, STATS_TYPE_BANK0, },
	{ "in_unicast",			4, 0x04, STATS_TYPE_BANK0, },
	{ "in_broadcasts",		4, 0x06, STATS_TYPE_BANK0, },
	{ "in_multicasts",		4, 0x07, STATS_TYPE_BANK0, },
	{ "in_pause",			4, 0x16, STATS_TYPE_BANK0, },
	{ "in_undersize",		4, 0x18, STATS_TYPE_BANK0, },
	{ "in_fragments",		4, 0x19, STATS_TYPE_BANK0, },
	{ "in_oversize",		4, 0x1a, STATS_TYPE_BANK0, },
	{ "in_jabber",			4, 0x1b, STATS_TYPE_BANK0, },
	{ "in_rx_error",		4, 0x1c, STATS_TYPE_BANK0, },
	{ "in_fcs_error",		4, 0x1d, STATS_TYPE_BANK0, },
	{ "out_octets",			8, 0x0e, STATS_TYPE_BANK0, },
	{ "out_unicast",		4, 0x10, STATS_TYPE_BANK0, },
	{ "out_broadcasts",		4, 0x13, STATS_TYPE_BANK0, },
	{ "out_multicasts",		4, 0x12, STATS_TYPE_BANK0, },
	{ "out_pause",			4, 0x15, STATS_TYPE_BANK0, },
	{ "excessive",			4, 0x11, STATS_TYPE_BANK0, },
	{ "collisions",			4, 0x1e, STATS_TYPE_BANK0, },
	{ "deferred",			4, 0x05, STATS_TYPE_BANK0, },
	{ "single",			4, 0x14, STATS_TYPE_BANK0, },
	{ "multiple",			4, 0x17, STATS_TYPE_BANK0, },
	{ "out_fcs_error",		4, 0x03, STATS_TYPE_BANK0, },
	{ "late",			4, 0x1f, STATS_TYPE_BANK0, },
	{ "hist_64bytes",		4, 0x08, STATS_TYPE_BANK0, },
	{ "hist_65_127bytes",		4, 0x09, STATS_TYPE_BANK0, },
	{ "hist_128_255bytes",		4, 0x0a, STATS_TYPE_BANK0, },
	{ "hist_256_511bytes",		4, 0x0b, STATS_TYPE_BANK0, },
	{ "hist_512_1023bytes",		4, 0x0c, STATS_TYPE_BANK0, },
	{ "hist_1024_max_bytes",	4, 0x0d, STATS_TYPE_BANK0, },
	{ "sw_in_discards",		4, 0x10, STATS_TYPE_PORT, },
	{ "sw_in_filtered",		2, 0x12, STATS_TYPE_PORT, },
	{ "sw_out_filtered",		2, 0x13, STATS_TYPE_PORT, },
	{ "in_discards",		4, 0x00, STATS_TYPE_BANK1, },
	{ "in_filtered",		4, 0x01, STATS_TYPE_BANK1, },
	{ "in_accepted",		4, 0x02, STATS_TYPE_BANK1, },
	{ "in_bad_accepted",		4, 0x03, STATS_TYPE_BANK1, },
	{ "in_good_avb_class_a",	4, 0x04, STATS_TYPE_BANK1, },
	{ "in_good_avb_class_b",	4, 0x05, STATS_TYPE_BANK1, },
	{ "in_bad_avb_class_a",		4, 0x06, STATS_TYPE_BANK1, },
	{ "in_bad_avb_class_b",		4, 0x07, STATS_TYPE_BANK1, },
	{ "tcam_counter_0",		4, 0x08, STATS_TYPE_BANK1, },
	{ "tcam_counter_1",		4, 0x09, STATS_TYPE_BANK1, },
	{ "tcam_counter_2",		4, 0x0a, STATS_TYPE_BANK1, },
	{ "tcam_counter_3",		4, 0x0b, STATS_TYPE_BANK1, },
	{ "in_da_unknown",		4, 0x0e, STATS_TYPE_BANK1, },
	{ "in_management",		4, 0x0f, STATS_TYPE_BANK1, },
	{ "out_queue_0",		4, 0x10, STATS_TYPE_BANK1, },
	{ "out_queue_1",		4, 0x11, STATS_TYPE_BANK1, },
	{ "out_queue_2",		4, 0x12, STATS_TYPE_BANK1, },
	{ "out_queue_3",		4, 0x13, STATS_TYPE_BANK1, },
	{ "out_queue_4",		4, 0x14, STATS_TYPE_BANK1, },
	{ "out_queue_5",		4, 0x15, STATS_TYPE_BANK1, },
	{ "out_queue_6",		4, 0x16, STATS_TYPE_BANK1, },
	{ "out_queue_7",		4, 0x17, STATS_TYPE_BANK1, },
	{ "out_cut_through",		4, 0x18, STATS_TYPE_BANK1, },
	{ "out_octets_a",		4, 0x1a, STATS_TYPE_BANK1, },
	{ "out_octets_b",		4, 0x1b, STATS_TYPE_BANK1, },
	{ "out_management",		4, 0x1f, STATS_TYPE_BANK1, },
651 652
};

653
static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
654
					    struct mv88e6xxx_hw_stat *s,
655 656
					    int port, u16 bank1_select,
					    u16 histogram)
657 658 659
{
	u32 low;
	u32 high = 0;
660
	u16 reg = 0;
661
	int err;
662 663
	u64 value;

664
	switch (s->type) {
665
	case STATS_TYPE_PORT:
666 667
		err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
		if (err)
668 669
			return UINT64_MAX;

670
		low = reg;
671
		if (s->size == 4) {
672 673
			err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
			if (err)
674
				return UINT64_MAX;
675
			high = reg;
676
		}
677
		break;
678
	case STATS_TYPE_BANK1:
679
		reg = bank1_select;
680 681
		/* fall through */
	case STATS_TYPE_BANK0:
682
		reg |= s->reg | histogram;
683
		mv88e6xxx_g1_stats_read(chip, reg, &low);
684
		if (s->size == 8)
685
			mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
686 687 688
		break;
	default:
		return UINT64_MAX;
689 690 691 692 693
	}
	value = (((u64)high) << 16) | low;
	return value;
}

694 695
static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
				       uint8_t *data, int types)
696
{
697 698
	struct mv88e6xxx_hw_stat *stat;
	int i, j;
699

700 701
	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
		stat = &mv88e6xxx_hw_stats[i];
702
		if (stat->type & types) {
703 704 705 706
			memcpy(data + j * ETH_GSTRING_LEN, stat->string,
			       ETH_GSTRING_LEN);
			j++;
		}
707
	}
708 709

	return j;
710 711
}

712 713
static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
				       uint8_t *data)
714
{
715 716
	return mv88e6xxx_stats_get_strings(chip, data,
					   STATS_TYPE_BANK0 | STATS_TYPE_PORT);
717 718
}

719 720
static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
				       uint8_t *data)
721
{
722 723
	return mv88e6xxx_stats_get_strings(chip, data,
					   STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
724 725 726 727
}

static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
				  uint8_t *data)
728
{
V
Vivien Didelot 已提交
729
	struct mv88e6xxx_chip *chip = ds->priv;
730
	int count = 0;
731

732 733
	mutex_lock(&chip->reg_lock);

734
	if (chip->info->ops->stats_get_strings)
735 736 737 738 739 740
		count = chip->info->ops->stats_get_strings(chip, data);

	if (chip->info->ops->serdes_get_strings) {
		data += count * ETH_GSTRING_LEN;
		chip->info->ops->serdes_get_strings(chip, port, data);
	}
741 742

	mutex_unlock(&chip->reg_lock);
743 744 745 746 747
}

static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
					  int types)
{
748 749 750 751 752
	struct mv88e6xxx_hw_stat *stat;
	int i, j;

	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
		stat = &mv88e6xxx_hw_stats[i];
753
		if (stat->type & types)
754 755 756
			j++;
	}
	return j;
757 758
}

759 760 761 762 763 764 765 766 767 768 769 770
static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
{
	return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
					      STATS_TYPE_PORT);
}

static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
{
	return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
					      STATS_TYPE_BANK1);
}

771
static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port)
772 773
{
	struct mv88e6xxx_chip *chip = ds->priv;
774 775
	int serdes_count = 0;
	int count = 0;
776

777
	mutex_lock(&chip->reg_lock);
778
	if (chip->info->ops->stats_get_sset_count)
779 780 781 782 783 784 785 786 787 788 789 790
		count = chip->info->ops->stats_get_sset_count(chip);
	if (count < 0)
		goto out;

	if (chip->info->ops->serdes_get_sset_count)
		serdes_count = chip->info->ops->serdes_get_sset_count(chip,
								      port);
	if (serdes_count < 0)
		count = serdes_count;
	else
		count += serdes_count;
out:
791
	mutex_unlock(&chip->reg_lock);
792

793
	return count;
794 795
}

796 797 798
static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
				     uint64_t *data, int types,
				     u16 bank1_select, u16 histogram)
799 800 801 802 803 804 805
{
	struct mv88e6xxx_hw_stat *stat;
	int i, j;

	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
		stat = &mv88e6xxx_hw_stats[i];
		if (stat->type & types) {
806
			mutex_lock(&chip->reg_lock);
807 808 809
			data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
							      bank1_select,
							      histogram);
810 811
			mutex_unlock(&chip->reg_lock);

812 813 814
			j++;
		}
	}
815
	return j;
816 817
}

818 819
static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
				     uint64_t *data)
820 821
{
	return mv88e6xxx_stats_get_stats(chip, port, data,
822
					 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
823
					 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
824 825
}

826 827
static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
				     uint64_t *data)
828 829
{
	return mv88e6xxx_stats_get_stats(chip, port, data,
830
					 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
831 832
					 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
					 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
833 834
}

835 836
static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
				     uint64_t *data)
837 838 839
{
	return mv88e6xxx_stats_get_stats(chip, port, data,
					 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
840 841
					 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
					 0);
842 843 844 845 846
}

static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
				uint64_t *data)
{
847 848
	int count = 0;

849
	if (chip->info->ops->stats_get_stats)
850 851 852 853
		count = chip->info->ops->stats_get_stats(chip, port, data);

	if (chip->info->ops->serdes_get_stats) {
		data += count;
854
		mutex_lock(&chip->reg_lock);
855
		chip->info->ops->serdes_get_stats(chip, port, data);
856
		mutex_unlock(&chip->reg_lock);
857
	}
858 859
}

860 861
static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
					uint64_t *data)
862
{
V
Vivien Didelot 已提交
863
	struct mv88e6xxx_chip *chip = ds->priv;
864 865
	int ret;

866
	mutex_lock(&chip->reg_lock);
867

868
	ret = mv88e6xxx_stats_snapshot(chip, port);
869 870 871
	mutex_unlock(&chip->reg_lock);

	if (ret < 0)
872
		return;
873 874

	mv88e6xxx_get_stats(chip, port, data);
875

876 877
}

878 879 880 881 882 883 884 885
static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->stats_set_histogram)
		return chip->info->ops->stats_set_histogram(chip);

	return 0;
}

886
static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
887 888 889 890
{
	return 32 * sizeof(u16);
}

891 892
static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
			       struct ethtool_regs *regs, void *_p)
893
{
V
Vivien Didelot 已提交
894
	struct mv88e6xxx_chip *chip = ds->priv;
895 896
	int err;
	u16 reg;
897 898 899 900 901 902 903
	u16 *p = _p;
	int i;

	regs->version = 0;

	memset(p, 0xff, 32 * sizeof(u16));

904
	mutex_lock(&chip->reg_lock);
905

906 907
	for (i = 0; i < 32; i++) {

908 909 910
		err = mv88e6xxx_port_read(chip, port, i, &reg);
		if (!err)
			p[i] = reg;
911
	}
912

913
	mutex_unlock(&chip->reg_lock);
914 915
}

V
Vivien Didelot 已提交
916 917
static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
				 struct ethtool_eee *e)
918
{
919 920
	/* Nothing to do on the port's MAC */
	return 0;
921 922
}

V
Vivien Didelot 已提交
923 924
static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
				 struct ethtool_eee *e)
925
{
926 927
	/* Nothing to do on the port's MAC */
	return 0;
928 929
}

930
static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
931
{
932 933 934
	struct dsa_switch *ds = NULL;
	struct net_device *br;
	u16 pvlan;
935 936
	int i;

937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956
	if (dev < DSA_MAX_SWITCHES)
		ds = chip->ds->dst->ds[dev];

	/* Prevent frames from unknown switch or port */
	if (!ds || port >= ds->num_ports)
		return 0;

	/* Frames from DSA links and CPU ports can egress any local port */
	if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
		return mv88e6xxx_port_mask(chip);

	br = ds->ports[port].bridge_dev;
	pvlan = 0;

	/* Frames from user ports can egress any local DSA links and CPU ports,
	 * as well as any local member of their bridge group.
	 */
	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
		if (dsa_is_cpu_port(chip->ds, i) ||
		    dsa_is_dsa_port(chip->ds, i) ||
V
Vivien Didelot 已提交
957
		    (br && dsa_to_port(chip->ds, i)->bridge_dev == br))
958 959 960 961 962
			pvlan |= BIT(i);

	return pvlan;
}

963
static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
964 965
{
	u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
966 967 968

	/* prevent frames from going back out of the port they came in on */
	output_ports &= ~BIT(port);
969

970
	return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
971 972
}

973 974
static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
					 u8 state)
975
{
V
Vivien Didelot 已提交
976
	struct mv88e6xxx_chip *chip = ds->priv;
977
	int err;
978

979
	mutex_lock(&chip->reg_lock);
980
	err = mv88e6xxx_port_set_state(chip, port, state);
981
	mutex_unlock(&chip->reg_lock);
982 983

	if (err)
984
		dev_err(ds->dev, "p%d: failed to update state\n", port);
985 986
}

987 988 989 990 991 992 993 994
static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->pot_clear)
		return chip->info->ops->pot_clear(chip);

	return 0;
}

995 996 997 998 999 1000 1001 1002
static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->mgmt_rsvd2cpu)
		return chip->info->ops->mgmt_rsvd2cpu(chip);

	return 0;
}

1003 1004
static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
{
1005 1006
	int err;

1007 1008 1009 1010
	err = mv88e6xxx_g1_atu_flush(chip, 0, true);
	if (err)
		return err;

1011 1012 1013 1014
	err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
	if (err)
		return err;

1015 1016 1017
	return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
}

1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037
static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
{
	int port;
	int err;

	if (!chip->info->ops->irl_init_all)
		return 0;

	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
		/* Disable ingress rate limiting by resetting all per port
		 * ingress rate limit resources to their initial state.
		 */
		err = chip->info->ops->irl_init_all(chip, port);
		if (err)
			return err;
	}

	return 0;
}

1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050
static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->set_switch_mac) {
		u8 addr[ETH_ALEN];

		eth_random_addr(addr);

		return chip->info->ops->set_switch_mac(chip, addr);
	}

	return 0;
}

1051 1052 1053 1054 1055 1056 1057 1058 1059
static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
{
	u16 pvlan = 0;

	if (!mv88e6xxx_has_pvt(chip))
		return -EOPNOTSUPP;

	/* Skip the local source device, which uses in-chip port VLAN */
	if (dev != chip->ds->index)
1060
		pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1061 1062 1063 1064

	return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
}

1065 1066
static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
{
1067 1068 1069
	int dev, port;
	int err;

1070 1071 1072 1073 1074 1075
	if (!mv88e6xxx_has_pvt(chip))
		return 0;

	/* Clear 5 Bit Port for usage with Marvell Link Street devices:
	 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
	 */
1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088
	err = mv88e6xxx_g2_misc_4_bit_port(chip);
	if (err)
		return err;

	for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
		for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
			err = mv88e6xxx_pvt_map(chip, dev, port);
			if (err)
				return err;
		}
	}

	return 0;
1089 1090
}

1091 1092 1093 1094 1095 1096
static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int err;

	mutex_lock(&chip->reg_lock);
1097
	err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
1098 1099 1100
	mutex_unlock(&chip->reg_lock);

	if (err)
1101
		dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
1102 1103
}

1104 1105 1106 1107 1108 1109 1110 1111
static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
{
	if (!chip->info->max_vid)
		return 0;

	return mv88e6xxx_g1_vtu_flush(chip);
}

1112 1113 1114 1115 1116 1117 1118 1119 1120
static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
				 struct mv88e6xxx_vtu_entry *entry)
{
	if (!chip->info->ops->vtu_getnext)
		return -EOPNOTSUPP;

	return chip->info->ops->vtu_getnext(chip, entry);
}

1121 1122 1123 1124 1125 1126 1127 1128 1129
static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
				   struct mv88e6xxx_vtu_entry *entry)
{
	if (!chip->info->ops->vtu_loadpurge)
		return -EOPNOTSUPP;

	return chip->info->ops->vtu_loadpurge(chip, entry);
}

1130
static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1131 1132
{
	DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1133 1134 1135
	struct mv88e6xxx_vtu_entry vlan = {
		.vid = chip->info->max_vid,
	};
1136
	int i, err;
1137 1138 1139

	bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);

1140
	/* Set every FID bit used by the (un)bridged ports */
1141
	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1142
		err = mv88e6xxx_port_get_fid(chip, i, fid);
1143 1144 1145 1146 1147 1148
		if (err)
			return err;

		set_bit(*fid, fid_bitmap);
	}

1149 1150
	/* Set every FID bit used by the VLAN entries */
	do {
1151
		err = mv88e6xxx_vtu_getnext(chip, &vlan);
1152 1153 1154 1155 1156 1157 1158
		if (err)
			return err;

		if (!vlan.valid)
			break;

		set_bit(vlan.fid, fid_bitmap);
1159
	} while (vlan.vid < chip->info->max_vid);
1160 1161 1162 1163 1164

	/* The reset value 0x000 is used to indicate that multiple address
	 * databases are not needed. Return the next positive available.
	 */
	*fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1165
	if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1166 1167 1168
		return -ENOSPC;

	/* Clear the database */
1169
	return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1170 1171
}

1172 1173
static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
			     struct mv88e6xxx_vtu_entry *entry, bool new)
1174 1175 1176 1177 1178 1179
{
	int err;

	if (!vid)
		return -EINVAL;

1180 1181
	entry->vid = vid - 1;
	entry->valid = false;
1182

1183
	err = mv88e6xxx_vtu_getnext(chip, entry);
1184 1185 1186
	if (err)
		return err;

1187 1188
	if (entry->vid == vid && entry->valid)
		return 0;
1189

1190 1191 1192 1193 1194 1195 1196 1197
	if (new) {
		int i;

		/* Initialize a fresh VLAN entry */
		memset(entry, 0, sizeof(*entry));
		entry->valid = true;
		entry->vid = vid;

1198
		/* Exclude all ports */
1199
		for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1200
			entry->member[i] =
1201
				MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1202 1203

		return mv88e6xxx_atu_new(chip, &entry->fid);
1204 1205
	}

1206 1207
	/* switchdev expects -EOPNOTSUPP to honor software VLANs */
	return -EOPNOTSUPP;
1208 1209
}

1210 1211 1212
static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
					u16 vid_begin, u16 vid_end)
{
V
Vivien Didelot 已提交
1213
	struct mv88e6xxx_chip *chip = ds->priv;
1214 1215 1216
	struct mv88e6xxx_vtu_entry vlan = {
		.vid = vid_begin - 1,
	};
1217 1218
	int i, err;

1219 1220 1221 1222
	/* DSA and CPU ports have to be members of multiple vlans */
	if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
		return 0;

1223 1224 1225
	if (!vid_begin)
		return -EOPNOTSUPP;

1226
	mutex_lock(&chip->reg_lock);
1227 1228

	do {
1229
		err = mv88e6xxx_vtu_getnext(chip, &vlan);
1230 1231 1232 1233 1234 1235 1236 1237 1238
		if (err)
			goto unlock;

		if (!vlan.valid)
			break;

		if (vlan.vid > vid_end)
			break;

1239
		for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1240 1241 1242
			if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
				continue;

1243
			if (!ds->ports[i].slave)
1244 1245
				continue;

1246
			if (vlan.member[i] ==
1247
			    MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1248 1249
				continue;

V
Vivien Didelot 已提交
1250
			if (dsa_to_port(ds, i)->bridge_dev ==
1251
			    ds->ports[port].bridge_dev)
1252 1253
				break; /* same bridge, check next VLAN */

V
Vivien Didelot 已提交
1254
			if (!dsa_to_port(ds, i)->bridge_dev)
1255 1256
				continue;

1257 1258
			dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
				port, vlan.vid, i,
V
Vivien Didelot 已提交
1259
				netdev_name(dsa_to_port(ds, i)->bridge_dev));
1260 1261 1262 1263 1264 1265
			err = -EOPNOTSUPP;
			goto unlock;
		}
	} while (vlan.vid < vid_end);

unlock:
1266
	mutex_unlock(&chip->reg_lock);
1267 1268 1269 1270

	return err;
}

1271 1272
static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
					 bool vlan_filtering)
1273
{
V
Vivien Didelot 已提交
1274
	struct mv88e6xxx_chip *chip = ds->priv;
1275 1276
	u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
		MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1277
	int err;
1278

1279
	if (!chip->info->max_vid)
1280 1281
		return -EOPNOTSUPP;

1282
	mutex_lock(&chip->reg_lock);
1283
	err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1284
	mutex_unlock(&chip->reg_lock);
1285

1286
	return err;
1287 1288
}

1289 1290
static int
mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1291
			    const struct switchdev_obj_port_vlan *vlan)
1292
{
V
Vivien Didelot 已提交
1293
	struct mv88e6xxx_chip *chip = ds->priv;
1294 1295
	int err;

1296
	if (!chip->info->max_vid)
1297 1298
		return -EOPNOTSUPP;

1299 1300 1301 1302 1303 1304 1305 1306
	/* If the requested port doesn't belong to the same bridge as the VLAN
	 * members, do not support it (yet) and fallback to software VLAN.
	 */
	err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
					   vlan->vid_end);
	if (err)
		return err;

1307 1308 1309 1310 1311 1312
	/* We don't need any dynamic resource from the kernel (yet),
	 * so skip the prepare phase.
	 */
	return 0;
}

1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356
static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
					const unsigned char *addr, u16 vid,
					u8 state)
{
	struct mv88e6xxx_vtu_entry vlan;
	struct mv88e6xxx_atu_entry entry;
	int err;

	/* Null VLAN ID corresponds to the port private database */
	if (vid == 0)
		err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
	else
		err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
	if (err)
		return err;

	entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
	ether_addr_copy(entry.mac, addr);
	eth_addr_dec(entry.mac);

	err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
	if (err)
		return err;

	/* Initialize a fresh ATU entry if it isn't found */
	if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED ||
	    !ether_addr_equal(entry.mac, addr)) {
		memset(&entry, 0, sizeof(entry));
		ether_addr_copy(entry.mac, addr);
	}

	/* Purge the ATU entry only if no port is using it anymore */
	if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
		entry.portvec &= ~BIT(port);
		if (!entry.portvec)
			entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
	} else {
		entry.portvec |= BIT(port);
		entry.state = state;
	}

	return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
}

1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379
static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
					u16 vid)
{
	const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
	u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;

	return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
}

static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
{
	int port;
	int err;

	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
		err = mv88e6xxx_port_add_broadcast(chip, port, vid);
		if (err)
			return err;
	}

	return 0;
}

1380
static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1381
				    u16 vid, u8 member)
1382
{
1383
	struct mv88e6xxx_vtu_entry vlan;
1384 1385
	int err;

1386
	err = mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1387
	if (err)
1388
		return err;
1389

1390
	vlan.member[port] = member;
1391

1392 1393 1394 1395 1396
	err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
	if (err)
		return err;

	return mv88e6xxx_broadcast_setup(chip, vid);
1397 1398
}

1399
static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1400
				    const struct switchdev_obj_port_vlan *vlan)
1401
{
V
Vivien Didelot 已提交
1402
	struct mv88e6xxx_chip *chip = ds->priv;
1403 1404
	bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
	bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1405
	u8 member;
1406 1407
	u16 vid;

1408
	if (!chip->info->max_vid)
1409 1410
		return;

1411
	if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1412
		member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
1413
	else if (untagged)
1414
		member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
1415
	else
1416
		member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
1417

1418
	mutex_lock(&chip->reg_lock);
1419

1420
	for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1421
		if (_mv88e6xxx_port_vlan_add(chip, port, vid, member))
1422 1423
			dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
				vid, untagged ? 'u' : 't');
1424

1425
	if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
1426 1427
		dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
			vlan->vid_end);
1428

1429
	mutex_unlock(&chip->reg_lock);
1430 1431
}

1432
static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1433
				    int port, u16 vid)
1434
{
1435
	struct mv88e6xxx_vtu_entry vlan;
1436 1437
	int i, err;

1438
	err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1439
	if (err)
1440
		return err;
1441

1442
	/* Tell switchdev if this VLAN is handled in software */
1443
	if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1444
		return -EOPNOTSUPP;
1445

1446
	vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1447 1448

	/* keep the VLAN unless all ports are excluded */
1449
	vlan.valid = false;
1450
	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1451 1452
		if (vlan.member[i] !=
		    MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1453
			vlan.valid = true;
1454 1455 1456 1457
			break;
		}
	}

1458
	err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1459 1460 1461
	if (err)
		return err;

1462
	return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
1463 1464
}

1465 1466
static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
				   const struct switchdev_obj_port_vlan *vlan)
1467
{
V
Vivien Didelot 已提交
1468
	struct mv88e6xxx_chip *chip = ds->priv;
1469 1470 1471
	u16 pvid, vid;
	int err = 0;

1472
	if (!chip->info->max_vid)
1473 1474
		return -EOPNOTSUPP;

1475
	mutex_lock(&chip->reg_lock);
1476

1477
	err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1478 1479 1480
	if (err)
		goto unlock;

1481
	for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1482
		err = _mv88e6xxx_port_vlan_del(chip, port, vid);
1483 1484 1485 1486
		if (err)
			goto unlock;

		if (vid == pvid) {
1487
			err = mv88e6xxx_port_set_pvid(chip, port, 0);
1488 1489 1490 1491 1492
			if (err)
				goto unlock;
		}
	}

1493
unlock:
1494
	mutex_unlock(&chip->reg_lock);
1495 1496 1497 1498

	return err;
}

1499 1500
static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
				  const unsigned char *addr, u16 vid)
1501
{
V
Vivien Didelot 已提交
1502
	struct mv88e6xxx_chip *chip = ds->priv;
1503
	int err;
1504

1505
	mutex_lock(&chip->reg_lock);
1506 1507
	err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
					   MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1508
	mutex_unlock(&chip->reg_lock);
1509 1510

	return err;
1511 1512
}

1513
static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1514
				  const unsigned char *addr, u16 vid)
1515
{
V
Vivien Didelot 已提交
1516
	struct mv88e6xxx_chip *chip = ds->priv;
1517
	int err;
1518

1519
	mutex_lock(&chip->reg_lock);
1520
	err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1521
					   MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
1522
	mutex_unlock(&chip->reg_lock);
1523

1524
	return err;
1525 1526
}

1527 1528
static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
				      u16 fid, u16 vid, int port,
1529
				      dsa_fdb_dump_cb_t *cb, void *data)
1530
{
1531
	struct mv88e6xxx_atu_entry addr;
1532
	bool is_static;
1533 1534
	int err;

1535
	addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1536
	eth_broadcast_addr(addr.mac);
1537 1538

	do {
1539
		mutex_lock(&chip->reg_lock);
1540
		err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
1541
		mutex_unlock(&chip->reg_lock);
1542
		if (err)
1543
			return err;
1544

1545
		if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED)
1546 1547
			break;

1548
		if (addr.trunk || (addr.portvec & BIT(port)) == 0)
1549 1550
			continue;

1551 1552
		if (!is_unicast_ether_addr(addr.mac))
			continue;
1553

1554 1555 1556
		is_static = (addr.state ==
			     MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
		err = cb(addr.mac, vid, is_static, data);
1557 1558
		if (err)
			return err;
1559 1560 1561 1562 1563
	} while (!is_broadcast_ether_addr(addr.mac));

	return err;
}

1564
static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
1565
				  dsa_fdb_dump_cb_t *cb, void *data)
1566
{
1567
	struct mv88e6xxx_vtu_entry vlan = {
1568
		.vid = chip->info->max_vid,
1569
	};
1570
	u16 fid;
1571 1572
	int err;

1573
	/* Dump port's default Filtering Information Database (VLAN ID 0) */
1574
	mutex_lock(&chip->reg_lock);
1575
	err = mv88e6xxx_port_get_fid(chip, port, &fid);
1576 1577
	mutex_unlock(&chip->reg_lock);

1578
	if (err)
1579
		return err;
1580

1581
	err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
1582
	if (err)
1583
		return err;
1584

1585
	/* Dump VLANs' Filtering Information Databases */
1586
	do {
1587
		mutex_lock(&chip->reg_lock);
1588
		err = mv88e6xxx_vtu_getnext(chip, &vlan);
1589
		mutex_unlock(&chip->reg_lock);
1590
		if (err)
1591
			return err;
1592 1593 1594 1595

		if (!vlan.valid)
			break;

1596
		err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
1597
						 cb, data);
1598
		if (err)
1599
			return err;
1600
	} while (vlan.vid < chip->info->max_vid);
1601

1602 1603 1604 1605
	return err;
}

static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
1606
				   dsa_fdb_dump_cb_t *cb, void *data)
1607
{
V
Vivien Didelot 已提交
1608
	struct mv88e6xxx_chip *chip = ds->priv;
1609

1610
	return mv88e6xxx_port_db_dump(chip, port, cb, data);
1611 1612
}

1613 1614
static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
				struct net_device *br)
1615
{
1616
	struct dsa_switch *ds;
1617
	int port;
1618
	int dev;
1619
	int err;
1620

1621 1622 1623 1624
	/* Remap the Port VLAN of each local bridge group member */
	for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
		if (chip->ds->ports[port].bridge_dev == br) {
			err = mv88e6xxx_port_vlan_map(chip, port);
1625
			if (err)
1626
				return err;
1627 1628 1629
		}
	}

1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647
	if (!mv88e6xxx_has_pvt(chip))
		return 0;

	/* Remap the Port VLAN of each cross-chip bridge group member */
	for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) {
		ds = chip->ds->dst->ds[dev];
		if (!ds)
			break;

		for (port = 0; port < ds->num_ports; ++port) {
			if (ds->ports[port].bridge_dev == br) {
				err = mv88e6xxx_pvt_map(chip, dev, port);
				if (err)
					return err;
			}
		}
	}

1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658
	return 0;
}

static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
				      struct net_device *br)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int err;

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_bridge_map(chip, br);
1659
	mutex_unlock(&chip->reg_lock);
1660

1661
	return err;
1662 1663
}

1664 1665
static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
					struct net_device *br)
1666
{
V
Vivien Didelot 已提交
1667
	struct mv88e6xxx_chip *chip = ds->priv;
1668

1669
	mutex_lock(&chip->reg_lock);
1670 1671 1672
	if (mv88e6xxx_bridge_map(chip, br) ||
	    mv88e6xxx_port_vlan_map(chip, port))
		dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
1673
	mutex_unlock(&chip->reg_lock);
1674 1675
}

1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705
static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
					   int port, struct net_device *br)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int err;

	if (!mv88e6xxx_has_pvt(chip))
		return 0;

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_pvt_map(chip, dev, port);
	mutex_unlock(&chip->reg_lock);

	return err;
}

static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
					     int port, struct net_device *br)
{
	struct mv88e6xxx_chip *chip = ds->priv;

	if (!mv88e6xxx_has_pvt(chip))
		return;

	mutex_lock(&chip->reg_lock);
	if (mv88e6xxx_pvt_map(chip, dev, port))
		dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
	mutex_unlock(&chip->reg_lock);
}

1706 1707 1708 1709 1710 1711 1712 1713
static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->reset)
		return chip->info->ops->reset(chip);

	return 0;
}

1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726
static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
{
	struct gpio_desc *gpiod = chip->reset;

	/* If there is a GPIO connected to the reset pin, toggle it */
	if (gpiod) {
		gpiod_set_value_cansleep(gpiod, 1);
		usleep_range(10000, 20000);
		gpiod_set_value_cansleep(gpiod, 0);
		usleep_range(10000, 20000);
	}
}

1727
static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
1728
{
1729
	int i, err;
1730

1731
	/* Set all ports to the Disabled state */
1732
	for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
1733
		err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
1734 1735
		if (err)
			return err;
1736 1737
	}

1738 1739 1740
	/* Wait for transmit queues to drain,
	 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
	 */
1741 1742
	usleep_range(2000, 4000);

1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753
	return 0;
}

static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
{
	int err;

	err = mv88e6xxx_disable_ports(chip);
	if (err)
		return err;

1754
	mv88e6xxx_hardware_reset(chip);
1755

1756
	return mv88e6xxx_software_reset(chip);
1757 1758
}

1759
static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
1760 1761
				   enum mv88e6xxx_frame_mode frame,
				   enum mv88e6xxx_egress_mode egress, u16 etype)
1762 1763 1764
{
	int err;

1765 1766 1767 1768
	if (!chip->info->ops->port_set_frame_mode)
		return -EOPNOTSUPP;

	err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
1769 1770 1771
	if (err)
		return err;

1772 1773 1774 1775 1776 1777 1778 1779
	err = chip->info->ops->port_set_frame_mode(chip, port, frame);
	if (err)
		return err;

	if (chip->info->ops->port_set_ether_type)
		return chip->info->ops->port_set_ether_type(chip, port, etype);

	return 0;
1780 1781
}

1782
static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
1783
{
1784
	return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
1785
				       MV88E6XXX_EGRESS_MODE_UNMODIFIED,
1786
				       MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
1787
}
1788

1789 1790 1791
static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
{
	return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
1792
				       MV88E6XXX_EGRESS_MODE_UNMODIFIED,
1793
				       MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
1794
}
1795

1796 1797 1798 1799
static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
{
	return mv88e6xxx_set_port_mode(chip, port,
				       MV88E6XXX_FRAME_MODE_ETHERTYPE,
1800 1801
				       MV88E6XXX_EGRESS_MODE_ETHERTYPE,
				       ETH_P_EDSA);
1802
}
1803

1804 1805 1806 1807
static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
{
	if (dsa_is_dsa_port(chip->ds, port))
		return mv88e6xxx_set_port_mode_dsa(chip, port);
1808

1809
	if (dsa_is_user_port(chip->ds, port))
1810
		return mv88e6xxx_set_port_mode_normal(chip, port);
1811

1812 1813 1814
	/* Setup CPU port mode depending on its supported tag format */
	if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
		return mv88e6xxx_set_port_mode_dsa(chip, port);
1815

1816 1817
	if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
		return mv88e6xxx_set_port_mode_edsa(chip, port);
1818

1819
	return -EINVAL;
1820 1821
}

1822
static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
1823
{
1824
	bool message = dsa_is_dsa_port(chip->ds, port);
1825

1826
	return mv88e6xxx_port_set_message_port(chip, port, message);
1827
}
1828

1829
static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
1830
{
1831 1832
	struct dsa_switch *ds = chip->ds;
	bool flood;
1833

1834
	/* Upstream ports flood frames with unknown unicast or multicast DA */
1835
	flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port);
1836 1837 1838
	if (chip->info->ops->port_set_egress_floods)
		return chip->info->ops->port_set_egress_floods(chip, port,
							       flood, flood);
1839

1840
	return 0;
1841 1842
}

1843 1844 1845
static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
				  bool on)
{
1846 1847
	if (chip->info->ops->serdes_power)
		return chip->info->ops->serdes_power(chip, port, on);
1848

1849
	return 0;
1850 1851
}

1852 1853 1854 1855 1856 1857
static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
{
	struct dsa_switch *ds = chip->ds;
	int upstream_port;
	int err;

1858
	upstream_port = dsa_upstream_port(ds, port);
1859 1860 1861 1862 1863 1864 1865
	if (chip->info->ops->port_set_upstream_port) {
		err = chip->info->ops->port_set_upstream_port(chip, port,
							      upstream_port);
		if (err)
			return err;
	}

1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881
	if (port == upstream_port) {
		if (chip->info->ops->set_cpu_port) {
			err = chip->info->ops->set_cpu_port(chip,
							    upstream_port);
			if (err)
				return err;
		}

		if (chip->info->ops->set_egress_port) {
			err = chip->info->ops->set_egress_port(chip,
							       upstream_port);
			if (err)
				return err;
		}
	}

1882 1883 1884
	return 0;
}

1885
static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
1886
{
1887
	struct dsa_switch *ds = chip->ds;
1888
	int err;
1889
	u16 reg;
1890

1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904
	/* MAC Forcing register: don't force link, speed, duplex or flow control
	 * state to any particular values on physical ports, but force the CPU
	 * port and all DSA ports to their maximum bandwidth and full duplex.
	 */
	if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
		err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
					       SPEED_MAX, DUPLEX_FULL,
					       PHY_INTERFACE_MODE_NA);
	else
		err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
					       SPEED_UNFORCED, DUPLEX_UNFORCED,
					       PHY_INTERFACE_MODE_NA);
	if (err)
		return err;
1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919

	/* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
	 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
	 * tunneling, determine priority by looking at 802.1p and IP
	 * priority fields (IP prio has precedence), and set STP state
	 * to Forwarding.
	 *
	 * If this is the CPU link, use DSA or EDSA tagging depending
	 * on which tagging mode was configured.
	 *
	 * If this is a link to another switch, use DSA tagging mode.
	 *
	 * If this is the upstream port for this switch, enable
	 * forwarding of unknown unicasts and multicasts.
	 */
1920 1921 1922 1923
	reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
		MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
		MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
1924 1925
	if (err)
		return err;
1926

1927
	err = mv88e6xxx_setup_port_mode(chip, port);
1928 1929
	if (err)
		return err;
1930

1931
	err = mv88e6xxx_setup_egress_floods(chip, port);
1932 1933 1934
	if (err)
		return err;

1935 1936 1937
	/* Enable the SERDES interface for DSA and CPU ports. Normal
	 * ports SERDES are enabled when the port is enabled, thus
	 * saving a bit of power.
1938
	 */
1939 1940 1941 1942 1943
	if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) {
		err = mv88e6xxx_serdes_power(chip, port, true);
		if (err)
			return err;
	}
1944

1945
	/* Port Control 2: don't force a good FCS, set the maximum frame size to
1946
	 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
1947 1948 1949
	 * untagged frames on this port, do a destination address lookup on all
	 * received packets as usual, disable ARP mirroring and don't send a
	 * copy of all transmitted/received frames on this port to the CPU.
1950
	 */
1951 1952 1953
	err = mv88e6xxx_port_set_map_da(chip, port);
	if (err)
		return err;
1954

1955 1956 1957
	err = mv88e6xxx_setup_upstream_port(chip, port);
	if (err)
		return err;
1958

1959
	err = mv88e6xxx_port_set_8021q_mode(chip, port,
1960
				MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
1961 1962 1963
	if (err)
		return err;

1964 1965
	if (chip->info->ops->port_set_jumbo_size) {
		err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
1966 1967 1968 1969
		if (err)
			return err;
	}

1970 1971 1972 1973 1974
	/* Port Association Vector: when learning source addresses
	 * of packets, add the address to the address database using
	 * a port bitmap that has only the bit for this port set and
	 * the other bits clear.
	 */
1975
	reg = 1 << port;
1976 1977
	/* Disable learning for CPU port */
	if (dsa_is_cpu_port(ds, port))
1978
		reg = 0;
1979

1980 1981
	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
				   reg);
1982 1983
	if (err)
		return err;
1984 1985

	/* Egress rate control 2: disable egress rate control. */
1986 1987
	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
				   0x0000);
1988 1989
	if (err)
		return err;
1990

1991 1992
	if (chip->info->ops->port_pause_limit) {
		err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
1993 1994
		if (err)
			return err;
1995
	}
1996

1997 1998 1999 2000 2001 2002
	if (chip->info->ops->port_disable_learn_limit) {
		err = chip->info->ops->port_disable_learn_limit(chip, port);
		if (err)
			return err;
	}

2003 2004
	if (chip->info->ops->port_disable_pri_override) {
		err = chip->info->ops->port_disable_pri_override(chip, port);
2005 2006
		if (err)
			return err;
2007
	}
2008

2009 2010
	if (chip->info->ops->port_tag_remap) {
		err = chip->info->ops->port_tag_remap(chip, port);
2011 2012
		if (err)
			return err;
2013 2014
	}

2015 2016
	if (chip->info->ops->port_egress_rate_limiting) {
		err = chip->info->ops->port_egress_rate_limiting(chip, port);
2017 2018
		if (err)
			return err;
2019 2020
	}

2021
	err = mv88e6xxx_setup_message_port(chip, port);
2022 2023
	if (err)
		return err;
2024

2025
	/* Port based VLAN map: give each port the same default address
2026 2027
	 * database, and allow bidirectional communication between the
	 * CPU and DSA port(s), and the other ports.
2028
	 */
2029
	err = mv88e6xxx_port_set_fid(chip, port, 0);
2030 2031
	if (err)
		return err;
2032

2033
	err = mv88e6xxx_port_vlan_map(chip, port);
2034 2035
	if (err)
		return err;
2036 2037 2038 2039

	/* Default VLAN ID and priority: don't set a default VLAN
	 * ID, and set the default packet priority to zero.
	 */
2040
	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
2041 2042
}

2043 2044 2045 2046
static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
				 struct phy_device *phydev)
{
	struct mv88e6xxx_chip *chip = ds->priv;
2047
	int err;
2048 2049

	mutex_lock(&chip->reg_lock);
2050
	err = mv88e6xxx_serdes_power(chip, port, true);
2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061
	mutex_unlock(&chip->reg_lock);

	return err;
}

static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port,
				   struct phy_device *phydev)
{
	struct mv88e6xxx_chip *chip = ds->priv;

	mutex_lock(&chip->reg_lock);
2062 2063
	if (mv88e6xxx_serdes_power(chip, port, false))
		dev_err(chip->dev, "failed to power off SERDES\n");
2064 2065 2066
	mutex_unlock(&chip->reg_lock);
}

2067 2068 2069
static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
				     unsigned int ageing_time)
{
V
Vivien Didelot 已提交
2070
	struct mv88e6xxx_chip *chip = ds->priv;
2071 2072 2073
	int err;

	mutex_lock(&chip->reg_lock);
2074
	err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2075 2076 2077 2078 2079
	mutex_unlock(&chip->reg_lock);

	return err;
}

2080
static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
2081
{
2082
	struct dsa_switch *ds = chip->ds;
2083
	int err;
2084

2085
	/* Disable remote management, and set the switch's DSA device number. */
2086 2087
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2,
				 MV88E6XXX_G1_CTL2_MULTIPLE_CASCADE |
2088
				 (ds->index & 0x1f));
2089 2090 2091
	if (err)
		return err;

2092
	/* Configure the IP ToS mapping registers. */
2093
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000);
2094
	if (err)
2095
		return err;
2096
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000);
2097
	if (err)
2098
		return err;
2099
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555);
2100
	if (err)
2101
		return err;
2102
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555);
2103
	if (err)
2104
		return err;
2105
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa);
2106
	if (err)
2107
		return err;
2108
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa);
2109
	if (err)
2110
		return err;
2111
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff);
2112
	if (err)
2113
		return err;
2114
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff);
2115
	if (err)
2116
		return err;
2117 2118

	/* Configure the IEEE 802.1p priority mapping register. */
2119
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41);
2120
	if (err)
2121
		return err;
2122

2123 2124 2125 2126 2127
	/* Initialize the statistics unit */
	err = mv88e6xxx_stats_set_histogram(chip);
	if (err)
		return err;

2128
	return mv88e6xxx_g1_stats_clear(chip);
2129 2130
}

2131
static int mv88e6xxx_setup(struct dsa_switch *ds)
2132
{
V
Vivien Didelot 已提交
2133
	struct mv88e6xxx_chip *chip = ds->priv;
2134
	int err;
2135 2136
	int i;

2137
	chip->ds = ds;
2138
	ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
2139

2140
	mutex_lock(&chip->reg_lock);
2141

2142
	/* Setup Switch Port Registers */
2143
	for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2144 2145 2146
		if (dsa_is_unused_port(ds, i))
			continue;

2147 2148 2149 2150 2151 2152 2153
		err = mv88e6xxx_setup_port(chip, i);
		if (err)
			goto unlock;
	}

	/* Setup Switch Global 1 Registers */
	err = mv88e6xxx_g1_setup(chip);
2154 2155 2156
	if (err)
		goto unlock;

2157
	/* Setup Switch Global 2 Registers */
2158
	if (chip->info->global2_addr) {
2159
		err = mv88e6xxx_g2_setup(chip);
2160 2161 2162
		if (err)
			goto unlock;
	}
2163

2164 2165 2166 2167
	err = mv88e6xxx_irl_setup(chip);
	if (err)
		goto unlock;

2168 2169 2170 2171
	err = mv88e6xxx_mac_setup(chip);
	if (err)
		goto unlock;

2172 2173 2174 2175
	err = mv88e6xxx_phy_setup(chip);
	if (err)
		goto unlock;

2176 2177 2178 2179
	err = mv88e6xxx_vtu_setup(chip);
	if (err)
		goto unlock;

2180 2181 2182 2183
	err = mv88e6xxx_pvt_setup(chip);
	if (err)
		goto unlock;

2184 2185 2186 2187
	err = mv88e6xxx_atu_setup(chip);
	if (err)
		goto unlock;

2188 2189 2190 2191
	err = mv88e6xxx_broadcast_setup(chip, 0);
	if (err)
		goto unlock;

2192 2193 2194 2195
	err = mv88e6xxx_pot_setup(chip);
	if (err)
		goto unlock;

2196 2197 2198
	err = mv88e6xxx_rsvd2cpu_setup(chip);
	if (err)
		goto unlock;
2199

2200
	/* Setup PTP Hardware Clock and timestamping */
2201 2202 2203 2204
	if (chip->info->ptp_support) {
		err = mv88e6xxx_ptp_setup(chip);
		if (err)
			goto unlock;
2205 2206 2207 2208

		err = mv88e6xxx_hwtstamp_setup(chip);
		if (err)
			goto unlock;
2209 2210
	}

2211
unlock:
2212
	mutex_unlock(&chip->reg_lock);
2213

2214
	return err;
2215 2216
}

2217
static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
2218
{
2219 2220
	struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
	struct mv88e6xxx_chip *chip = mdio_bus->chip;
2221 2222
	u16 val;
	int err;
2223

2224 2225 2226
	if (!chip->info->ops->phy_read)
		return -EOPNOTSUPP;

2227
	mutex_lock(&chip->reg_lock);
2228
	err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
2229
	mutex_unlock(&chip->reg_lock);
2230

2231 2232 2233 2234 2235
	if (reg == MII_PHYSID2) {
		/* Some internal PHYS don't have a model number.  Use
		 * the mv88e6390 family model number instead.
		 */
		if (!(val & 0x3f0))
2236
			val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
2237 2238
	}

2239
	return err ? err : val;
2240 2241
}

2242
static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
2243
{
2244 2245
	struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
	struct mv88e6xxx_chip *chip = mdio_bus->chip;
2246
	int err;
2247

2248 2249 2250
	if (!chip->info->ops->phy_write)
		return -EOPNOTSUPP;

2251
	mutex_lock(&chip->reg_lock);
2252
	err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
2253
	mutex_unlock(&chip->reg_lock);
2254 2255

	return err;
2256 2257
}

2258
static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
2259 2260
				   struct device_node *np,
				   bool external)
2261 2262
{
	static int index;
2263
	struct mv88e6xxx_mdio_bus *mdio_bus;
2264 2265 2266
	struct mii_bus *bus;
	int err;

2267 2268 2269 2270 2271 2272 2273 2274 2275
	if (external) {
		mutex_lock(&chip->reg_lock);
		err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
		mutex_unlock(&chip->reg_lock);

		if (err)
			return err;
	}

2276
	bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
2277 2278 2279
	if (!bus)
		return -ENOMEM;

2280
	mdio_bus = bus->priv;
2281
	mdio_bus->bus = bus;
2282
	mdio_bus->chip = chip;
2283 2284
	INIT_LIST_HEAD(&mdio_bus->list);
	mdio_bus->external = external;
2285

2286 2287
	if (np) {
		bus->name = np->full_name;
2288
		snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
2289 2290 2291 2292 2293 2294 2295
	} else {
		bus->name = "mv88e6xxx SMI";
		snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
	}

	bus->read = mv88e6xxx_mdio_read;
	bus->write = mv88e6xxx_mdio_write;
2296
	bus->parent = chip->dev;
2297

2298 2299 2300 2301 2302 2303
	if (!external) {
		err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
		if (err)
			return err;
	}

2304 2305
	if (np)
		err = of_mdiobus_register(bus, np);
2306 2307 2308
	else
		err = mdiobus_register(bus);
	if (err) {
2309
		dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
2310
		mv88e6xxx_g2_irq_mdio_free(chip, bus);
2311
		return err;
2312
	}
2313 2314 2315 2316 2317

	if (external)
		list_add_tail(&mdio_bus->list, &chip->mdios);
	else
		list_add(&mdio_bus->list, &chip->mdios);
2318 2319

	return 0;
2320
}
2321

2322 2323 2324 2325 2326
static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
	{ .compatible = "marvell,mv88e6xxx-mdio-external",
	  .data = (void *)true },
	{ },
};
2327

2328 2329 2330 2331 2332 2333 2334 2335 2336
static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)

{
	struct mv88e6xxx_mdio_bus *mdio_bus;
	struct mii_bus *bus;

	list_for_each_entry(mdio_bus, &chip->mdios, list) {
		bus = mdio_bus->bus;

2337 2338 2339
		if (!mdio_bus->external)
			mv88e6xxx_g2_irq_mdio_free(chip, bus);

2340 2341 2342 2343
		mdiobus_unregister(bus);
	}
}

2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367
static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
				    struct device_node *np)
{
	const struct of_device_id *match;
	struct device_node *child;
	int err;

	/* Always register one mdio bus for the internal/default mdio
	 * bus. This maybe represented in the device tree, but is
	 * optional.
	 */
	child = of_get_child_by_name(np, "mdio");
	err = mv88e6xxx_mdio_register(chip, child, false);
	if (err)
		return err;

	/* Walk the device tree, and see if there are any other nodes
	 * which say they are compatible with the external mdio
	 * bus.
	 */
	for_each_available_child_of_node(np, child) {
		match = of_match_node(mv88e6xxx_mdio_external_match, child);
		if (match) {
			err = mv88e6xxx_mdio_register(chip, child, true);
2368 2369
			if (err) {
				mv88e6xxx_mdios_unregister(chip);
2370
				return err;
2371
			}
2372 2373 2374 2375
		}
	}

	return 0;
2376 2377
}

2378 2379
static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
{
V
Vivien Didelot 已提交
2380
	struct mv88e6xxx_chip *chip = ds->priv;
2381 2382 2383 2384 2385 2386 2387

	return chip->eeprom_len;
}

static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
				struct ethtool_eeprom *eeprom, u8 *data)
{
V
Vivien Didelot 已提交
2388
	struct mv88e6xxx_chip *chip = ds->priv;
2389 2390
	int err;

2391 2392
	if (!chip->info->ops->get_eeprom)
		return -EOPNOTSUPP;
2393

2394 2395
	mutex_lock(&chip->reg_lock);
	err = chip->info->ops->get_eeprom(chip, eeprom, data);
2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408
	mutex_unlock(&chip->reg_lock);

	if (err)
		return err;

	eeprom->magic = 0xc3ec4951;

	return 0;
}

static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
				struct ethtool_eeprom *eeprom, u8 *data)
{
V
Vivien Didelot 已提交
2409
	struct mv88e6xxx_chip *chip = ds->priv;
2410 2411
	int err;

2412 2413 2414
	if (!chip->info->ops->set_eeprom)
		return -EOPNOTSUPP;

2415 2416 2417 2418
	if (eeprom->magic != 0xc3ec4951)
		return -EINVAL;

	mutex_lock(&chip->reg_lock);
2419
	err = chip->info->ops->set_eeprom(chip, eeprom, data);
2420 2421 2422 2423 2424
	mutex_unlock(&chip->reg_lock);

	return err;
}

2425
static const struct mv88e6xxx_ops mv88e6085_ops = {
2426
	/* MV88E6XXX_FAMILY_6097 */
2427
	.irl_init_all = mv88e6352_g2_irl_init_all,
2428
	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2429 2430
	.phy_read = mv88e6185_phy_ppu_read,
	.phy_write = mv88e6185_phy_ppu_write,
2431
	.port_set_link = mv88e6xxx_port_set_link,
2432
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2433
	.port_set_speed = mv88e6185_port_set_speed,
2434
	.port_tag_remap = mv88e6095_port_tag_remap,
2435
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2436
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2437
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2438
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2439
	.port_pause_limit = mv88e6097_port_pause_limit,
2440
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2441
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2442
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2443
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2444 2445
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2446
	.stats_get_stats = mv88e6095_stats_get_stats,
2447 2448
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2449
	.watchdog_ops = &mv88e6097_watchdog_ops,
2450
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2451
	.pot_clear = mv88e6xxx_g2_pot_clear,
2452 2453
	.ppu_enable = mv88e6185_g1_ppu_enable,
	.ppu_disable = mv88e6185_g1_ppu_disable,
2454
	.reset = mv88e6185_g1_reset,
2455
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2456
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2457 2458 2459
};

static const struct mv88e6xxx_ops mv88e6095_ops = {
2460
	/* MV88E6XXX_FAMILY_6095 */
2461
	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2462 2463
	.phy_read = mv88e6185_phy_ppu_read,
	.phy_write = mv88e6185_phy_ppu_write,
2464
	.port_set_link = mv88e6xxx_port_set_link,
2465
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2466
	.port_set_speed = mv88e6185_port_set_speed,
2467
	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
2468
	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
2469
	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
2470
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2471
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2472 2473
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2474
	.stats_get_stats = mv88e6095_stats_get_stats,
2475
	.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2476 2477
	.ppu_enable = mv88e6185_g1_ppu_enable,
	.ppu_disable = mv88e6185_g1_ppu_disable,
2478
	.reset = mv88e6185_g1_reset,
2479
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
2480
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2481 2482
};

2483
static const struct mv88e6xxx_ops mv88e6097_ops = {
2484
	/* MV88E6XXX_FAMILY_6097 */
2485
	.irl_init_all = mv88e6352_g2_irl_init_all,
2486 2487 2488 2489 2490 2491
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_speed = mv88e6185_port_set_speed,
2492
	.port_tag_remap = mv88e6095_port_tag_remap,
2493
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2494
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2495
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2496
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2497
	.port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2498
	.port_pause_limit = mv88e6097_port_pause_limit,
2499
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2500
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2501
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2502
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2503 2504 2505
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
	.stats_get_stats = mv88e6095_stats_get_stats,
2506 2507
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2508
	.watchdog_ops = &mv88e6097_watchdog_ops,
2509
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2510
	.pot_clear = mv88e6xxx_g2_pot_clear,
2511
	.reset = mv88e6352_g1_reset,
2512
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2513
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2514 2515
};

2516
static const struct mv88e6xxx_ops mv88e6123_ops = {
2517
	/* MV88E6XXX_FAMILY_6165 */
2518
	.irl_init_all = mv88e6352_g2_irl_init_all,
2519
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2520 2521
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2522
	.port_set_link = mv88e6xxx_port_set_link,
2523
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2524
	.port_set_speed = mv88e6185_port_set_speed,
2525
	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
2526
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2527
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2528
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2529
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2530
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2531 2532
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2533
	.stats_get_stats = mv88e6095_stats_get_stats,
2534 2535
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2536
	.watchdog_ops = &mv88e6097_watchdog_ops,
2537
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2538
	.pot_clear = mv88e6xxx_g2_pot_clear,
2539
	.reset = mv88e6352_g1_reset,
2540
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2541
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2542 2543 2544
};

static const struct mv88e6xxx_ops mv88e6131_ops = {
2545
	/* MV88E6XXX_FAMILY_6185 */
2546
	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2547 2548
	.phy_read = mv88e6185_phy_ppu_read,
	.phy_write = mv88e6185_phy_ppu_write,
2549
	.port_set_link = mv88e6xxx_port_set_link,
2550
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2551
	.port_set_speed = mv88e6185_port_set_speed,
2552
	.port_tag_remap = mv88e6095_port_tag_remap,
2553
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2554
	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
2555
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2556
	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
2557
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2558
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2559
	.port_pause_limit = mv88e6097_port_pause_limit,
2560
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2561
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2562 2563
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2564
	.stats_get_stats = mv88e6095_stats_get_stats,
2565 2566
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2567
	.watchdog_ops = &mv88e6097_watchdog_ops,
2568
	.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2569 2570
	.ppu_enable = mv88e6185_g1_ppu_enable,
	.ppu_disable = mv88e6185_g1_ppu_disable,
2571
	.reset = mv88e6185_g1_reset,
2572
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
2573
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2574 2575
};

2576 2577
static const struct mv88e6xxx_ops mv88e6141_ops = {
	/* MV88E6XXX_FAMILY_6341 */
2578
	.irl_init_all = mv88e6352_g2_irl_init_all,
2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
	.port_tag_remap = mv88e6095_port_tag_remap,
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2592
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2593
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2594
	.port_pause_limit = mv88e6097_port_pause_limit,
2595 2596 2597
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
2598
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2599 2600 2601
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
	.stats_get_stats = mv88e6390_stats_get_stats,
2602 2603
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
2604 2605
	.watchdog_ops = &mv88e6390_watchdog_ops,
	.mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
2606
	.pot_clear = mv88e6xxx_g2_pot_clear,
2607
	.reset = mv88e6352_g1_reset,
2608
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2609
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2610
	.gpio_ops = &mv88e6352_gpio_ops,
2611 2612
};

2613
static const struct mv88e6xxx_ops mv88e6161_ops = {
2614
	/* MV88E6XXX_FAMILY_6165 */
2615
	.irl_init_all = mv88e6352_g2_irl_init_all,
2616
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2617 2618
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2619
	.port_set_link = mv88e6xxx_port_set_link,
2620
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2621
	.port_set_speed = mv88e6185_port_set_speed,
2622
	.port_tag_remap = mv88e6095_port_tag_remap,
2623
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2624
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2625
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2626
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2627
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2628
	.port_pause_limit = mv88e6097_port_pause_limit,
2629
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2630
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2631
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2632
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2633 2634
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2635
	.stats_get_stats = mv88e6095_stats_get_stats,
2636 2637
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2638
	.watchdog_ops = &mv88e6097_watchdog_ops,
2639
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2640
	.pot_clear = mv88e6xxx_g2_pot_clear,
2641
	.reset = mv88e6352_g1_reset,
2642
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2643
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2644 2645 2646
};

static const struct mv88e6xxx_ops mv88e6165_ops = {
2647
	/* MV88E6XXX_FAMILY_6165 */
2648
	.irl_init_all = mv88e6352_g2_irl_init_all,
2649
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2650 2651
	.phy_read = mv88e6165_phy_read,
	.phy_write = mv88e6165_phy_write,
2652
	.port_set_link = mv88e6xxx_port_set_link,
2653
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2654
	.port_set_speed = mv88e6185_port_set_speed,
2655
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2656
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2657
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2658
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2659 2660
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2661
	.stats_get_stats = mv88e6095_stats_get_stats,
2662 2663
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2664
	.watchdog_ops = &mv88e6097_watchdog_ops,
2665
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2666
	.pot_clear = mv88e6xxx_g2_pot_clear,
2667
	.reset = mv88e6352_g1_reset,
2668
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2669
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2670 2671 2672
};

static const struct mv88e6xxx_ops mv88e6171_ops = {
2673
	/* MV88E6XXX_FAMILY_6351 */
2674
	.irl_init_all = mv88e6352_g2_irl_init_all,
2675
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2676 2677
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2678
	.port_set_link = mv88e6xxx_port_set_link,
2679
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2680
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2681
	.port_set_speed = mv88e6185_port_set_speed,
2682
	.port_tag_remap = mv88e6095_port_tag_remap,
2683
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2684
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2685
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2686
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2687
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2688
	.port_pause_limit = mv88e6097_port_pause_limit,
2689
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2690
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2691
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2692
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2693 2694
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2695
	.stats_get_stats = mv88e6095_stats_get_stats,
2696 2697
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2698
	.watchdog_ops = &mv88e6097_watchdog_ops,
2699
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2700
	.pot_clear = mv88e6xxx_g2_pot_clear,
2701
	.reset = mv88e6352_g1_reset,
2702
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2703
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2704 2705 2706
};

static const struct mv88e6xxx_ops mv88e6172_ops = {
2707
	/* MV88E6XXX_FAMILY_6352 */
2708
	.irl_init_all = mv88e6352_g2_irl_init_all,
2709 2710
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
2711
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2712 2713
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2714
	.port_set_link = mv88e6xxx_port_set_link,
2715
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2716
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2717
	.port_set_speed = mv88e6352_port_set_speed,
2718
	.port_tag_remap = mv88e6095_port_tag_remap,
2719
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2720
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2721
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2722
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2723
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2724
	.port_pause_limit = mv88e6097_port_pause_limit,
2725
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2726
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2727
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2728
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2729 2730
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2731
	.stats_get_stats = mv88e6095_stats_get_stats,
2732 2733
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2734
	.watchdog_ops = &mv88e6097_watchdog_ops,
2735
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2736
	.pot_clear = mv88e6xxx_g2_pot_clear,
2737
	.reset = mv88e6352_g1_reset,
2738
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2739
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2740
	.serdes_power = mv88e6352_serdes_power,
2741
	.gpio_ops = &mv88e6352_gpio_ops,
2742 2743 2744
};

static const struct mv88e6xxx_ops mv88e6175_ops = {
2745
	/* MV88E6XXX_FAMILY_6351 */
2746
	.irl_init_all = mv88e6352_g2_irl_init_all,
2747
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2748 2749
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2750
	.port_set_link = mv88e6xxx_port_set_link,
2751
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2752
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2753
	.port_set_speed = mv88e6185_port_set_speed,
2754
	.port_tag_remap = mv88e6095_port_tag_remap,
2755
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2756
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2757
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2758
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2759
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2760
	.port_pause_limit = mv88e6097_port_pause_limit,
2761
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2762
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2763
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2764
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2765 2766
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2767
	.stats_get_stats = mv88e6095_stats_get_stats,
2768 2769
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2770
	.watchdog_ops = &mv88e6097_watchdog_ops,
2771
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2772
	.pot_clear = mv88e6xxx_g2_pot_clear,
2773
	.reset = mv88e6352_g1_reset,
2774
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2775
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2776 2777 2778
};

static const struct mv88e6xxx_ops mv88e6176_ops = {
2779
	/* MV88E6XXX_FAMILY_6352 */
2780
	.irl_init_all = mv88e6352_g2_irl_init_all,
2781 2782
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
2783
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2784 2785
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2786
	.port_set_link = mv88e6xxx_port_set_link,
2787
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2788
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2789
	.port_set_speed = mv88e6352_port_set_speed,
2790
	.port_tag_remap = mv88e6095_port_tag_remap,
2791
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2792
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2793
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2794
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2795
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2796
	.port_pause_limit = mv88e6097_port_pause_limit,
2797
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2798
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2799
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2800
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2801 2802
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2803
	.stats_get_stats = mv88e6095_stats_get_stats,
2804 2805
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2806
	.watchdog_ops = &mv88e6097_watchdog_ops,
2807
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2808
	.pot_clear = mv88e6xxx_g2_pot_clear,
2809
	.reset = mv88e6352_g1_reset,
2810
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2811
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2812
	.serdes_power = mv88e6352_serdes_power,
2813
	.gpio_ops = &mv88e6352_gpio_ops,
2814 2815 2816
};

static const struct mv88e6xxx_ops mv88e6185_ops = {
2817
	/* MV88E6XXX_FAMILY_6185 */
2818
	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2819 2820
	.phy_read = mv88e6185_phy_ppu_read,
	.phy_write = mv88e6185_phy_ppu_write,
2821
	.port_set_link = mv88e6xxx_port_set_link,
2822
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2823
	.port_set_speed = mv88e6185_port_set_speed,
2824
	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
2825
	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
2826
	.port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2827
	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
2828
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2829
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2830 2831
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2832
	.stats_get_stats = mv88e6095_stats_get_stats,
2833 2834
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2835
	.watchdog_ops = &mv88e6097_watchdog_ops,
2836
	.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2837 2838
	.ppu_enable = mv88e6185_g1_ppu_enable,
	.ppu_disable = mv88e6185_g1_ppu_disable,
2839
	.reset = mv88e6185_g1_reset,
2840
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
2841
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2842 2843
};

2844
static const struct mv88e6xxx_ops mv88e6190_ops = {
2845
	/* MV88E6XXX_FAMILY_6390 */
2846
	.irl_init_all = mv88e6390_g2_irl_init_all,
2847 2848
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
2849 2850 2851 2852 2853 2854 2855
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
2856
	.port_tag_remap = mv88e6390_port_tag_remap,
2857
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2858
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2859
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2860
	.port_pause_limit = mv88e6390_port_pause_limit,
2861
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2862
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2863
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
2864
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2865 2866
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
2867
	.stats_get_stats = mv88e6390_stats_get_stats,
2868 2869
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
2870
	.watchdog_ops = &mv88e6390_watchdog_ops,
2871
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2872
	.pot_clear = mv88e6xxx_g2_pot_clear,
2873
	.reset = mv88e6352_g1_reset,
2874 2875
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2876
	.serdes_power = mv88e6390_serdes_power,
2877
	.gpio_ops = &mv88e6352_gpio_ops,
2878 2879 2880
};

static const struct mv88e6xxx_ops mv88e6190x_ops = {
2881
	/* MV88E6XXX_FAMILY_6390 */
2882
	.irl_init_all = mv88e6390_g2_irl_init_all,
2883 2884
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
2885 2886 2887 2888 2889 2890 2891
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390x_port_set_speed,
2892
	.port_tag_remap = mv88e6390_port_tag_remap,
2893
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2894
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2895
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2896
	.port_pause_limit = mv88e6390_port_pause_limit,
2897
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2898
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2899
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
2900
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2901 2902
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
2903
	.stats_get_stats = mv88e6390_stats_get_stats,
2904 2905
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
2906
	.watchdog_ops = &mv88e6390_watchdog_ops,
2907
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2908
	.pot_clear = mv88e6xxx_g2_pot_clear,
2909
	.reset = mv88e6352_g1_reset,
2910 2911
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2912
	.serdes_power = mv88e6390_serdes_power,
2913
	.gpio_ops = &mv88e6352_gpio_ops,
2914 2915 2916
};

static const struct mv88e6xxx_ops mv88e6191_ops = {
2917
	/* MV88E6XXX_FAMILY_6390 */
2918
	.irl_init_all = mv88e6390_g2_irl_init_all,
2919 2920
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
2921 2922 2923 2924 2925 2926 2927
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
2928
	.port_tag_remap = mv88e6390_port_tag_remap,
2929
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2930
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2931
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2932
	.port_pause_limit = mv88e6390_port_pause_limit,
2933
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2934
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2935
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
2936
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2937 2938
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
2939
	.stats_get_stats = mv88e6390_stats_get_stats,
2940 2941
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
2942
	.watchdog_ops = &mv88e6390_watchdog_ops,
2943
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2944
	.pot_clear = mv88e6xxx_g2_pot_clear,
2945
	.reset = mv88e6352_g1_reset,
2946 2947
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2948
	.serdes_power = mv88e6390_serdes_power,
2949 2950
};

2951
static const struct mv88e6xxx_ops mv88e6240_ops = {
2952
	/* MV88E6XXX_FAMILY_6352 */
2953
	.irl_init_all = mv88e6352_g2_irl_init_all,
2954 2955
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
2956
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2957 2958
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2959
	.port_set_link = mv88e6xxx_port_set_link,
2960
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2961
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2962
	.port_set_speed = mv88e6352_port_set_speed,
2963
	.port_tag_remap = mv88e6095_port_tag_remap,
2964
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2965
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2966
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2967
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2968
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2969
	.port_pause_limit = mv88e6097_port_pause_limit,
2970
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2971
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2972
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2973
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2974 2975
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2976
	.stats_get_stats = mv88e6095_stats_get_stats,
2977 2978
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2979
	.watchdog_ops = &mv88e6097_watchdog_ops,
2980
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2981
	.pot_clear = mv88e6xxx_g2_pot_clear,
2982
	.reset = mv88e6352_g1_reset,
2983
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2984
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2985
	.serdes_power = mv88e6352_serdes_power,
2986
	.gpio_ops = &mv88e6352_gpio_ops,
2987
	.avb_ops = &mv88e6352_avb_ops,
2988 2989
};

2990
static const struct mv88e6xxx_ops mv88e6290_ops = {
2991
	/* MV88E6XXX_FAMILY_6390 */
2992
	.irl_init_all = mv88e6390_g2_irl_init_all,
2993 2994
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
2995 2996 2997 2998 2999 3000 3001
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
3002
	.port_tag_remap = mv88e6390_port_tag_remap,
3003
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3004
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3005
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3006
	.port_pause_limit = mv88e6390_port_pause_limit,
3007
	.port_set_cmode = mv88e6390x_port_set_cmode,
3008
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3009
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3010
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3011
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3012 3013
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3014
	.stats_get_stats = mv88e6390_stats_get_stats,
3015 3016
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3017
	.watchdog_ops = &mv88e6390_watchdog_ops,
3018
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3019
	.pot_clear = mv88e6xxx_g2_pot_clear,
3020
	.reset = mv88e6352_g1_reset,
3021 3022
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3023
	.serdes_power = mv88e6390_serdes_power,
3024
	.gpio_ops = &mv88e6352_gpio_ops,
3025
	.avb_ops = &mv88e6390_avb_ops,
3026 3027
};

3028
static const struct mv88e6xxx_ops mv88e6320_ops = {
3029
	/* MV88E6XXX_FAMILY_6320 */
3030
	.irl_init_all = mv88e6352_g2_irl_init_all,
3031 3032
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
3033
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3034 3035
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3036
	.port_set_link = mv88e6xxx_port_set_link,
3037
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3038
	.port_set_speed = mv88e6185_port_set_speed,
3039
	.port_tag_remap = mv88e6095_port_tag_remap,
3040
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3041
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3042
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3043
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3044
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3045
	.port_pause_limit = mv88e6097_port_pause_limit,
3046
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3047
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3048
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3049
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3050 3051
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3052
	.stats_get_stats = mv88e6320_stats_get_stats,
3053 3054
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3055
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3056
	.pot_clear = mv88e6xxx_g2_pot_clear,
3057
	.reset = mv88e6352_g1_reset,
3058
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
3059
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3060
	.gpio_ops = &mv88e6352_gpio_ops,
3061
	.avb_ops = &mv88e6352_avb_ops,
3062 3063 3064
};

static const struct mv88e6xxx_ops mv88e6321_ops = {
3065
	/* MV88E6XXX_FAMILY_6320 */
3066
	.irl_init_all = mv88e6352_g2_irl_init_all,
3067 3068
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
3069
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3070 3071
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3072
	.port_set_link = mv88e6xxx_port_set_link,
3073
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3074
	.port_set_speed = mv88e6185_port_set_speed,
3075
	.port_tag_remap = mv88e6095_port_tag_remap,
3076
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3077
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3078
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3079
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3080
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3081
	.port_pause_limit = mv88e6097_port_pause_limit,
3082
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3083
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3084
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3085
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3086 3087
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3088
	.stats_get_stats = mv88e6320_stats_get_stats,
3089 3090
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3091
	.reset = mv88e6352_g1_reset,
3092
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
3093
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3094
	.gpio_ops = &mv88e6352_gpio_ops,
3095
	.avb_ops = &mv88e6352_avb_ops,
3096 3097
};

3098 3099
static const struct mv88e6xxx_ops mv88e6341_ops = {
	/* MV88E6XXX_FAMILY_6341 */
3100
	.irl_init_all = mv88e6352_g2_irl_init_all,
3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111 3112 3113
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
	.port_tag_remap = mv88e6095_port_tag_remap,
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3114
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3115
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3116
	.port_pause_limit = mv88e6097_port_pause_limit,
3117 3118 3119
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3120
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3121 3122 3123
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
	.stats_get_stats = mv88e6390_stats_get_stats,
3124 3125
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3126 3127
	.watchdog_ops = &mv88e6390_watchdog_ops,
	.mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
3128
	.pot_clear = mv88e6xxx_g2_pot_clear,
3129
	.reset = mv88e6352_g1_reset,
3130
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3131
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3132
	.gpio_ops = &mv88e6352_gpio_ops,
3133
	.avb_ops = &mv88e6390_avb_ops,
3134 3135
};

3136
static const struct mv88e6xxx_ops mv88e6350_ops = {
3137
	/* MV88E6XXX_FAMILY_6351 */
3138
	.irl_init_all = mv88e6352_g2_irl_init_all,
3139
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3140 3141
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3142
	.port_set_link = mv88e6xxx_port_set_link,
3143
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3144
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3145
	.port_set_speed = mv88e6185_port_set_speed,
3146
	.port_tag_remap = mv88e6095_port_tag_remap,
3147
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3148
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3149
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3150
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3151
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3152
	.port_pause_limit = mv88e6097_port_pause_limit,
3153
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3154
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3155
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3156
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3157 3158
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
3159
	.stats_get_stats = mv88e6095_stats_get_stats,
3160 3161
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3162
	.watchdog_ops = &mv88e6097_watchdog_ops,
3163
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3164
	.pot_clear = mv88e6xxx_g2_pot_clear,
3165
	.reset = mv88e6352_g1_reset,
3166
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3167
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3168 3169 3170
};

static const struct mv88e6xxx_ops mv88e6351_ops = {
3171
	/* MV88E6XXX_FAMILY_6351 */
3172
	.irl_init_all = mv88e6352_g2_irl_init_all,
3173
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3174 3175
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3176
	.port_set_link = mv88e6xxx_port_set_link,
3177
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3178
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3179
	.port_set_speed = mv88e6185_port_set_speed,
3180
	.port_tag_remap = mv88e6095_port_tag_remap,
3181
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3182
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3183
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3184
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3185
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3186
	.port_pause_limit = mv88e6097_port_pause_limit,
3187
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3188
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3189
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3190
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3191 3192
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
3193
	.stats_get_stats = mv88e6095_stats_get_stats,
3194 3195
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3196
	.watchdog_ops = &mv88e6097_watchdog_ops,
3197
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3198
	.pot_clear = mv88e6xxx_g2_pot_clear,
3199
	.reset = mv88e6352_g1_reset,
3200
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3201
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3202
	.avb_ops = &mv88e6352_avb_ops,
3203 3204 3205
};

static const struct mv88e6xxx_ops mv88e6352_ops = {
3206
	/* MV88E6XXX_FAMILY_6352 */
3207
	.irl_init_all = mv88e6352_g2_irl_init_all,
3208 3209
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
3210
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3211 3212
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3213
	.port_set_link = mv88e6xxx_port_set_link,
3214
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3215
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3216
	.port_set_speed = mv88e6352_port_set_speed,
3217
	.port_tag_remap = mv88e6095_port_tag_remap,
3218
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3219
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3220
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3221
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3222
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3223
	.port_pause_limit = mv88e6097_port_pause_limit,
3224
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3225
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3226
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3227
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3228 3229
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
3230
	.stats_get_stats = mv88e6095_stats_get_stats,
3231 3232
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3233
	.watchdog_ops = &mv88e6097_watchdog_ops,
3234
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3235
	.pot_clear = mv88e6xxx_g2_pot_clear,
3236
	.reset = mv88e6352_g1_reset,
3237
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3238
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3239
	.serdes_power = mv88e6352_serdes_power,
3240
	.gpio_ops = &mv88e6352_gpio_ops,
3241
	.avb_ops = &mv88e6352_avb_ops,
3242 3243 3244
	.serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
	.serdes_get_strings = mv88e6352_serdes_get_strings,
	.serdes_get_stats = mv88e6352_serdes_get_stats,
3245 3246
};

3247
static const struct mv88e6xxx_ops mv88e6390_ops = {
3248
	/* MV88E6XXX_FAMILY_6390 */
3249
	.irl_init_all = mv88e6390_g2_irl_init_all,
3250 3251
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3252 3253 3254 3255 3256 3257 3258
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
3259
	.port_tag_remap = mv88e6390_port_tag_remap,
3260
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3261
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3262
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3263
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3264
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3265
	.port_pause_limit = mv88e6390_port_pause_limit,
3266
	.port_set_cmode = mv88e6390x_port_set_cmode,
3267
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3268
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3269
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3270
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3271 3272
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3273
	.stats_get_stats = mv88e6390_stats_get_stats,
3274 3275
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3276
	.watchdog_ops = &mv88e6390_watchdog_ops,
3277
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3278
	.pot_clear = mv88e6xxx_g2_pot_clear,
3279
	.reset = mv88e6352_g1_reset,
3280 3281
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3282
	.serdes_power = mv88e6390_serdes_power,
3283
	.gpio_ops = &mv88e6352_gpio_ops,
3284
	.avb_ops = &mv88e6390_avb_ops,
3285 3286 3287
};

static const struct mv88e6xxx_ops mv88e6390x_ops = {
3288
	/* MV88E6XXX_FAMILY_6390 */
3289
	.irl_init_all = mv88e6390_g2_irl_init_all,
3290 3291
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3292 3293 3294 3295 3296 3297 3298
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390x_port_set_speed,
3299
	.port_tag_remap = mv88e6390_port_tag_remap,
3300
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3301
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3302
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3303
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3304
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3305
	.port_pause_limit = mv88e6390_port_pause_limit,
3306
	.port_set_cmode = mv88e6390x_port_set_cmode,
3307
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3308
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3309
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3310
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3311 3312
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3313
	.stats_get_stats = mv88e6390_stats_get_stats,
3314 3315
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3316
	.watchdog_ops = &mv88e6390_watchdog_ops,
3317
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3318
	.pot_clear = mv88e6xxx_g2_pot_clear,
3319
	.reset = mv88e6352_g1_reset,
3320 3321
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3322
	.serdes_power = mv88e6390_serdes_power,
3323
	.gpio_ops = &mv88e6352_gpio_ops,
3324
	.avb_ops = &mv88e6390_avb_ops,
3325 3326
};

3327 3328
static const struct mv88e6xxx_info mv88e6xxx_table[] = {
	[MV88E6085] = {
3329
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
3330 3331 3332 3333
		.family = MV88E6XXX_FAMILY_6097,
		.name = "Marvell 88E6085",
		.num_databases = 4096,
		.num_ports = 10,
3334
		.num_internal_phys = 5,
3335
		.max_vid = 4095,
3336
		.port_base_addr = 0x10,
3337
		.global1_addr = 0x1b,
3338
		.global2_addr = 0x1c,
3339
		.age_time_coeff = 15000,
3340
		.g1_irqs = 8,
3341
		.g2_irqs = 10,
3342
		.atu_move_port_mask = 0xf,
3343
		.pvt = true,
3344
		.multi_chip = true,
3345
		.tag_protocol = DSA_TAG_PROTO_DSA,
3346
		.ops = &mv88e6085_ops,
3347 3348 3349
	},

	[MV88E6095] = {
3350
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
3351 3352 3353 3354
		.family = MV88E6XXX_FAMILY_6095,
		.name = "Marvell 88E6095/88E6095F",
		.num_databases = 256,
		.num_ports = 11,
3355
		.num_internal_phys = 0,
3356
		.max_vid = 4095,
3357
		.port_base_addr = 0x10,
3358
		.global1_addr = 0x1b,
3359
		.global2_addr = 0x1c,
3360
		.age_time_coeff = 15000,
3361
		.g1_irqs = 8,
3362
		.atu_move_port_mask = 0xf,
3363
		.multi_chip = true,
3364
		.tag_protocol = DSA_TAG_PROTO_DSA,
3365
		.ops = &mv88e6095_ops,
3366 3367
	},

3368
	[MV88E6097] = {
3369
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
3370 3371 3372 3373
		.family = MV88E6XXX_FAMILY_6097,
		.name = "Marvell 88E6097/88E6097F",
		.num_databases = 4096,
		.num_ports = 11,
3374
		.num_internal_phys = 8,
3375
		.max_vid = 4095,
3376 3377
		.port_base_addr = 0x10,
		.global1_addr = 0x1b,
3378
		.global2_addr = 0x1c,
3379
		.age_time_coeff = 15000,
3380
		.g1_irqs = 8,
3381
		.g2_irqs = 10,
3382
		.atu_move_port_mask = 0xf,
3383
		.pvt = true,
3384
		.multi_chip = true,
3385
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3386 3387 3388
		.ops = &mv88e6097_ops,
	},

3389
	[MV88E6123] = {
3390
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
3391 3392 3393 3394
		.family = MV88E6XXX_FAMILY_6165,
		.name = "Marvell 88E6123",
		.num_databases = 4096,
		.num_ports = 3,
3395
		.num_internal_phys = 5,
3396
		.max_vid = 4095,
3397
		.port_base_addr = 0x10,
3398
		.global1_addr = 0x1b,
3399
		.global2_addr = 0x1c,
3400
		.age_time_coeff = 15000,
3401
		.g1_irqs = 9,
3402
		.g2_irqs = 10,
3403
		.atu_move_port_mask = 0xf,
3404
		.pvt = true,
3405
		.multi_chip = true,
3406
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3407
		.ops = &mv88e6123_ops,
3408 3409 3410
	},

	[MV88E6131] = {
3411
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
3412 3413 3414 3415
		.family = MV88E6XXX_FAMILY_6185,
		.name = "Marvell 88E6131",
		.num_databases = 256,
		.num_ports = 8,
3416
		.num_internal_phys = 0,
3417
		.max_vid = 4095,
3418
		.port_base_addr = 0x10,
3419
		.global1_addr = 0x1b,
3420
		.global2_addr = 0x1c,
3421
		.age_time_coeff = 15000,
3422
		.g1_irqs = 9,
3423
		.atu_move_port_mask = 0xf,
3424
		.multi_chip = true,
3425
		.tag_protocol = DSA_TAG_PROTO_DSA,
3426
		.ops = &mv88e6131_ops,
3427 3428
	},

3429
	[MV88E6141] = {
3430
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
3431
		.family = MV88E6XXX_FAMILY_6341,
3432
		.name = "Marvell 88E6141",
3433 3434
		.num_databases = 4096,
		.num_ports = 6,
3435
		.num_internal_phys = 5,
3436
		.num_gpio = 11,
3437
		.max_vid = 4095,
3438 3439
		.port_base_addr = 0x10,
		.global1_addr = 0x1b,
3440
		.global2_addr = 0x1c,
3441 3442
		.age_time_coeff = 3750,
		.atu_move_port_mask = 0x1f,
3443
		.g1_irqs = 9,
3444
		.g2_irqs = 10,
3445
		.pvt = true,
3446
		.multi_chip = true,
3447 3448 3449 3450
		.tag_protocol = DSA_TAG_PROTO_EDSA,
		.ops = &mv88e6141_ops,
	},

3451
	[MV88E6161] = {
3452
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
3453 3454 3455 3456
		.family = MV88E6XXX_FAMILY_6165,
		.name = "Marvell 88E6161",
		.num_databases = 4096,
		.num_ports = 6,
3457
		.num_internal_phys = 5,
3458
		.max_vid = 4095,
3459
		.port_base_addr = 0x10,
3460
		.global1_addr = 0x1b,
3461
		.global2_addr = 0x1c,
3462
		.age_time_coeff = 15000,
3463
		.g1_irqs = 9,
3464
		.g2_irqs = 10,
3465
		.atu_move_port_mask = 0xf,
3466
		.pvt = true,
3467
		.multi_chip = true,
3468
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3469
		.ops = &mv88e6161_ops,
3470 3471 3472
	},

	[MV88E6165] = {
3473
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
3474 3475 3476 3477
		.family = MV88E6XXX_FAMILY_6165,
		.name = "Marvell 88E6165",
		.num_databases = 4096,
		.num_ports = 6,
3478
		.num_internal_phys = 0,
3479
		.max_vid = 4095,
3480
		.port_base_addr = 0x10,
3481
		.global1_addr = 0x1b,
3482
		.global2_addr = 0x1c,
3483
		.age_time_coeff = 15000,
3484
		.g1_irqs = 9,
3485
		.g2_irqs = 10,
3486
		.atu_move_port_mask = 0xf,
3487
		.pvt = true,
3488
		.multi_chip = true,
3489
		.tag_protocol = DSA_TAG_PROTO_DSA,
3490
		.ops = &mv88e6165_ops,
3491 3492 3493
	},

	[MV88E6171] = {
3494
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
3495 3496 3497 3498
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6171",
		.num_databases = 4096,
		.num_ports = 7,
3499
		.num_internal_phys = 5,
3500
		.max_vid = 4095,
3501
		.port_base_addr = 0x10,
3502
		.global1_addr = 0x1b,
3503
		.global2_addr = 0x1c,
3504
		.age_time_coeff = 15000,
3505
		.g1_irqs = 9,
3506
		.g2_irqs = 10,
3507
		.atu_move_port_mask = 0xf,
3508
		.pvt = true,
3509
		.multi_chip = true,
3510
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3511
		.ops = &mv88e6171_ops,
3512 3513 3514
	},

	[MV88E6172] = {
3515
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
3516 3517 3518 3519
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6172",
		.num_databases = 4096,
		.num_ports = 7,
3520
		.num_internal_phys = 5,
3521
		.num_gpio = 15,
3522
		.max_vid = 4095,
3523
		.port_base_addr = 0x10,
3524
		.global1_addr = 0x1b,
3525
		.global2_addr = 0x1c,
3526
		.age_time_coeff = 15000,
3527
		.g1_irqs = 9,
3528
		.g2_irqs = 10,
3529
		.atu_move_port_mask = 0xf,
3530
		.pvt = true,
3531
		.multi_chip = true,
3532
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3533
		.ops = &mv88e6172_ops,
3534 3535 3536
	},

	[MV88E6175] = {
3537
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
3538 3539 3540 3541
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6175",
		.num_databases = 4096,
		.num_ports = 7,
3542
		.num_internal_phys = 5,
3543
		.max_vid = 4095,
3544
		.port_base_addr = 0x10,
3545
		.global1_addr = 0x1b,
3546
		.global2_addr = 0x1c,
3547
		.age_time_coeff = 15000,
3548
		.g1_irqs = 9,
3549
		.g2_irqs = 10,
3550
		.atu_move_port_mask = 0xf,
3551
		.pvt = true,
3552
		.multi_chip = true,
3553
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3554
		.ops = &mv88e6175_ops,
3555 3556 3557
	},

	[MV88E6176] = {
3558
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
3559 3560 3561 3562
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6176",
		.num_databases = 4096,
		.num_ports = 7,
3563
		.num_internal_phys = 5,
3564
		.num_gpio = 15,
3565
		.max_vid = 4095,
3566
		.port_base_addr = 0x10,
3567
		.global1_addr = 0x1b,
3568
		.global2_addr = 0x1c,
3569
		.age_time_coeff = 15000,
3570
		.g1_irqs = 9,
3571
		.g2_irqs = 10,
3572
		.atu_move_port_mask = 0xf,
3573
		.pvt = true,
3574
		.multi_chip = true,
3575
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3576
		.ops = &mv88e6176_ops,
3577 3578 3579
	},

	[MV88E6185] = {
3580
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
3581 3582 3583 3584
		.family = MV88E6XXX_FAMILY_6185,
		.name = "Marvell 88E6185",
		.num_databases = 256,
		.num_ports = 10,
3585
		.num_internal_phys = 0,
3586
		.max_vid = 4095,
3587
		.port_base_addr = 0x10,
3588
		.global1_addr = 0x1b,
3589
		.global2_addr = 0x1c,
3590
		.age_time_coeff = 15000,
3591
		.g1_irqs = 8,
3592
		.atu_move_port_mask = 0xf,
3593
		.multi_chip = true,
3594
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3595
		.ops = &mv88e6185_ops,
3596 3597
	},

3598
	[MV88E6190] = {
3599
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
3600 3601 3602 3603
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6190",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3604
		.num_internal_phys = 11,
3605
		.num_gpio = 16,
3606
		.max_vid = 8191,
3607 3608
		.port_base_addr = 0x0,
		.global1_addr = 0x1b,
3609
		.global2_addr = 0x1c,
3610
		.tag_protocol = DSA_TAG_PROTO_DSA,
3611
		.age_time_coeff = 3750,
3612
		.g1_irqs = 9,
3613
		.g2_irqs = 14,
3614
		.pvt = true,
3615
		.multi_chip = true,
3616
		.atu_move_port_mask = 0x1f,
3617 3618 3619 3620
		.ops = &mv88e6190_ops,
	},

	[MV88E6190X] = {
3621
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
3622 3623 3624 3625
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6190X",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3626
		.num_internal_phys = 11,
3627
		.num_gpio = 16,
3628
		.max_vid = 8191,
3629 3630
		.port_base_addr = 0x0,
		.global1_addr = 0x1b,
3631
		.global2_addr = 0x1c,
3632
		.age_time_coeff = 3750,
3633
		.g1_irqs = 9,
3634
		.g2_irqs = 14,
3635
		.atu_move_port_mask = 0x1f,
3636
		.pvt = true,
3637
		.multi_chip = true,
3638
		.tag_protocol = DSA_TAG_PROTO_DSA,
3639 3640 3641 3642
		.ops = &mv88e6190x_ops,
	},

	[MV88E6191] = {
3643
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
3644 3645 3646 3647
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6191",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3648
		.num_internal_phys = 11,
3649
		.max_vid = 8191,
3650 3651
		.port_base_addr = 0x0,
		.global1_addr = 0x1b,
3652
		.global2_addr = 0x1c,
3653
		.age_time_coeff = 3750,
3654
		.g1_irqs = 9,
3655
		.g2_irqs = 14,
3656
		.atu_move_port_mask = 0x1f,
3657
		.pvt = true,
3658
		.multi_chip = true,
3659
		.tag_protocol = DSA_TAG_PROTO_DSA,
3660
		.ptp_support = true,
3661
		.ops = &mv88e6191_ops,
3662 3663
	},

3664
	[MV88E6240] = {
3665
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
3666 3667 3668 3669
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6240",
		.num_databases = 4096,
		.num_ports = 7,
3670
		.num_internal_phys = 5,
3671
		.num_gpio = 15,
3672
		.max_vid = 4095,
3673
		.port_base_addr = 0x10,
3674
		.global1_addr = 0x1b,
3675
		.global2_addr = 0x1c,
3676
		.age_time_coeff = 15000,
3677
		.g1_irqs = 9,
3678
		.g2_irqs = 10,
3679
		.atu_move_port_mask = 0xf,
3680
		.pvt = true,
3681
		.multi_chip = true,
3682
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3683
		.ptp_support = true,
3684
		.ops = &mv88e6240_ops,
3685 3686
	},

3687
	[MV88E6290] = {
3688
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
3689 3690 3691 3692
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6290",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3693
		.num_internal_phys = 11,
3694
		.num_gpio = 16,
3695
		.max_vid = 8191,
3696 3697
		.port_base_addr = 0x0,
		.global1_addr = 0x1b,
3698
		.global2_addr = 0x1c,
3699
		.age_time_coeff = 3750,
3700
		.g1_irqs = 9,
3701
		.g2_irqs = 14,
3702
		.atu_move_port_mask = 0x1f,
3703
		.pvt = true,
3704
		.multi_chip = true,
3705
		.tag_protocol = DSA_TAG_PROTO_DSA,
3706
		.ptp_support = true,
3707 3708 3709
		.ops = &mv88e6290_ops,
	},

3710
	[MV88E6320] = {
3711
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
3712 3713 3714 3715
		.family = MV88E6XXX_FAMILY_6320,
		.name = "Marvell 88E6320",
		.num_databases = 4096,
		.num_ports = 7,
3716
		.num_internal_phys = 5,
3717
		.num_gpio = 15,
3718
		.max_vid = 4095,
3719
		.port_base_addr = 0x10,
3720
		.global1_addr = 0x1b,
3721
		.global2_addr = 0x1c,
3722
		.age_time_coeff = 15000,
3723
		.g1_irqs = 8,
3724
		.g2_irqs = 10,
3725
		.atu_move_port_mask = 0xf,
3726
		.pvt = true,
3727
		.multi_chip = true,
3728
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3729
		.ptp_support = true,
3730
		.ops = &mv88e6320_ops,
3731 3732 3733
	},

	[MV88E6321] = {
3734
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
3735 3736 3737 3738
		.family = MV88E6XXX_FAMILY_6320,
		.name = "Marvell 88E6321",
		.num_databases = 4096,
		.num_ports = 7,
3739
		.num_internal_phys = 5,
3740
		.num_gpio = 15,
3741
		.max_vid = 4095,
3742
		.port_base_addr = 0x10,
3743
		.global1_addr = 0x1b,
3744
		.global2_addr = 0x1c,
3745
		.age_time_coeff = 15000,
3746
		.g1_irqs = 8,
3747
		.g2_irqs = 10,
3748
		.atu_move_port_mask = 0xf,
3749
		.multi_chip = true,
3750
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3751
		.ptp_support = true,
3752
		.ops = &mv88e6321_ops,
3753 3754
	},

3755
	[MV88E6341] = {
3756
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3757 3758 3759
		.family = MV88E6XXX_FAMILY_6341,
		.name = "Marvell 88E6341",
		.num_databases = 4096,
3760
		.num_internal_phys = 5,
3761
		.num_ports = 6,
3762
		.num_gpio = 11,
3763
		.max_vid = 4095,
3764 3765
		.port_base_addr = 0x10,
		.global1_addr = 0x1b,
3766
		.global2_addr = 0x1c,
3767
		.age_time_coeff = 3750,
3768
		.atu_move_port_mask = 0x1f,
3769
		.g1_irqs = 9,
3770
		.g2_irqs = 10,
3771
		.pvt = true,
3772
		.multi_chip = true,
3773
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3774
		.ptp_support = true,
3775 3776 3777
		.ops = &mv88e6341_ops,
	},

3778
	[MV88E6350] = {
3779
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
3780 3781 3782 3783
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6350",
		.num_databases = 4096,
		.num_ports = 7,
3784
		.num_internal_phys = 5,
3785
		.max_vid = 4095,
3786
		.port_base_addr = 0x10,
3787
		.global1_addr = 0x1b,
3788
		.global2_addr = 0x1c,
3789
		.age_time_coeff = 15000,
3790
		.g1_irqs = 9,
3791
		.g2_irqs = 10,
3792
		.atu_move_port_mask = 0xf,
3793
		.pvt = true,
3794
		.multi_chip = true,
3795
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3796
		.ops = &mv88e6350_ops,
3797 3798 3799
	},

	[MV88E6351] = {
3800
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
3801 3802 3803 3804
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6351",
		.num_databases = 4096,
		.num_ports = 7,
3805
		.num_internal_phys = 5,
3806
		.max_vid = 4095,
3807
		.port_base_addr = 0x10,
3808
		.global1_addr = 0x1b,
3809
		.global2_addr = 0x1c,
3810
		.age_time_coeff = 15000,
3811
		.g1_irqs = 9,
3812
		.g2_irqs = 10,
3813
		.atu_move_port_mask = 0xf,
3814
		.pvt = true,
3815
		.multi_chip = true,
3816
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3817
		.ops = &mv88e6351_ops,
3818 3819 3820
	},

	[MV88E6352] = {
3821
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
3822 3823 3824 3825
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6352",
		.num_databases = 4096,
		.num_ports = 7,
3826
		.num_internal_phys = 5,
3827
		.num_gpio = 15,
3828
		.max_vid = 4095,
3829
		.port_base_addr = 0x10,
3830
		.global1_addr = 0x1b,
3831
		.global2_addr = 0x1c,
3832
		.age_time_coeff = 15000,
3833
		.g1_irqs = 9,
3834
		.g2_irqs = 10,
3835
		.atu_move_port_mask = 0xf,
3836
		.pvt = true,
3837
		.multi_chip = true,
3838
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3839
		.ptp_support = true,
3840
		.ops = &mv88e6352_ops,
3841
	},
3842
	[MV88E6390] = {
3843
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
3844 3845 3846 3847
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6390",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3848
		.num_internal_phys = 11,
3849
		.num_gpio = 16,
3850
		.max_vid = 8191,
3851 3852
		.port_base_addr = 0x0,
		.global1_addr = 0x1b,
3853
		.global2_addr = 0x1c,
3854
		.age_time_coeff = 3750,
3855
		.g1_irqs = 9,
3856
		.g2_irqs = 14,
3857
		.atu_move_port_mask = 0x1f,
3858
		.pvt = true,
3859
		.multi_chip = true,
3860
		.tag_protocol = DSA_TAG_PROTO_DSA,
3861
		.ptp_support = true,
3862 3863 3864
		.ops = &mv88e6390_ops,
	},
	[MV88E6390X] = {
3865
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
3866 3867 3868 3869
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6390X",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3870
		.num_internal_phys = 11,
3871
		.num_gpio = 16,
3872
		.max_vid = 8191,
3873 3874
		.port_base_addr = 0x0,
		.global1_addr = 0x1b,
3875
		.global2_addr = 0x1c,
3876
		.age_time_coeff = 3750,
3877
		.g1_irqs = 9,
3878
		.g2_irqs = 14,
3879
		.atu_move_port_mask = 0x1f,
3880
		.pvt = true,
3881
		.multi_chip = true,
3882
		.tag_protocol = DSA_TAG_PROTO_DSA,
3883
		.ptp_support = true,
3884 3885
		.ops = &mv88e6390x_ops,
	},
3886 3887
};

3888
static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
3889
{
3890
	int i;
3891

3892 3893 3894
	for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
		if (mv88e6xxx_table[i].prod_num == prod_num)
			return &mv88e6xxx_table[i];
3895 3896 3897 3898

	return NULL;
}

3899
static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
3900 3901
{
	const struct mv88e6xxx_info *info;
3902 3903 3904
	unsigned int prod_num, rev;
	u16 id;
	int err;
3905

3906
	mutex_lock(&chip->reg_lock);
3907
	err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
3908 3909 3910
	mutex_unlock(&chip->reg_lock);
	if (err)
		return err;
3911

3912 3913
	prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
	rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
3914 3915 3916 3917 3918

	info = mv88e6xxx_lookup_info(prod_num);
	if (!info)
		return -ENODEV;

3919
	/* Update the compatible info with the probed one */
3920
	chip->info = info;
3921

3922 3923 3924 3925
	err = mv88e6xxx_g2_require(chip);
	if (err)
		return err;

3926 3927
	dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
		 chip->info->prod_num, chip->info->name, rev);
3928 3929 3930 3931

	return 0;
}

3932
static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
3933
{
3934
	struct mv88e6xxx_chip *chip;
3935

3936 3937
	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
	if (!chip)
3938 3939
		return NULL;

3940
	chip->dev = dev;
3941

3942
	mutex_init(&chip->reg_lock);
3943
	INIT_LIST_HEAD(&chip->mdios);
3944

3945
	return chip;
3946 3947
}

3948
static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
3949 3950
			      struct mii_bus *bus, int sw_addr)
{
3951
	if (sw_addr == 0)
3952
		chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
3953
	else if (chip->info->multi_chip)
3954
		chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
3955 3956 3957
	else
		return -EINVAL;

3958 3959
	chip->bus = bus;
	chip->sw_addr = sw_addr;
3960 3961 3962 3963

	return 0;
}

3964 3965
static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
							int port)
3966
{
V
Vivien Didelot 已提交
3967
	struct mv88e6xxx_chip *chip = ds->priv;
3968

3969
	return chip->info->tag_protocol;
3970 3971
}

3972
#if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
3973 3974 3975
static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
				       struct device *host_dev, int sw_addr,
				       void **priv)
3976
{
3977
	struct mv88e6xxx_chip *chip;
3978
	struct mii_bus *bus;
3979
	int err;
3980

3981
	bus = dsa_host_dev_to_mii_bus(host_dev);
3982 3983 3984
	if (!bus)
		return NULL;

3985 3986
	chip = mv88e6xxx_alloc_chip(dsa_dev);
	if (!chip)
3987 3988
		return NULL;

3989
	/* Legacy SMI probing will only support chips similar to 88E6085 */
3990
	chip->info = &mv88e6xxx_table[MV88E6085];
3991

3992
	err = mv88e6xxx_smi_init(chip, bus, sw_addr);
3993 3994 3995
	if (err)
		goto free;

3996
	err = mv88e6xxx_detect(chip);
3997
	if (err)
3998
		goto free;
3999

4000 4001 4002 4003 4004 4005
	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_switch_reset(chip);
	mutex_unlock(&chip->reg_lock);
	if (err)
		goto free;

4006 4007
	mv88e6xxx_phy_init(chip);

4008
	err = mv88e6xxx_mdios_register(chip, NULL);
4009
	if (err)
4010
		goto free;
4011

4012
	*priv = chip;
4013

4014
	return chip->info->name;
4015
free:
4016
	devm_kfree(dsa_dev, chip);
4017 4018

	return NULL;
4019
}
4020
#endif
4021

4022
static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
4023
				      const struct switchdev_obj_port_mdb *mdb)
4024 4025 4026 4027 4028 4029 4030 4031 4032
{
	/* We don't need any dynamic resource from the kernel (yet),
	 * so skip the prepare phase.
	 */

	return 0;
}

static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
4033
				   const struct switchdev_obj_port_mdb *mdb)
4034
{
V
Vivien Didelot 已提交
4035
	struct mv88e6xxx_chip *chip = ds->priv;
4036 4037 4038

	mutex_lock(&chip->reg_lock);
	if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4039
					 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
4040 4041
		dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
			port);
4042 4043 4044 4045 4046 4047
	mutex_unlock(&chip->reg_lock);
}

static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
				  const struct switchdev_obj_port_mdb *mdb)
{
V
Vivien Didelot 已提交
4048
	struct mv88e6xxx_chip *chip = ds->priv;
4049 4050 4051 4052
	int err;

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4053
					   MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
4054 4055 4056 4057 4058
	mutex_unlock(&chip->reg_lock);

	return err;
}

4059
static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
4060
#if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
4061
	.probe			= mv88e6xxx_drv_probe,
4062
#endif
4063
	.get_tag_protocol	= mv88e6xxx_get_tag_protocol,
4064 4065 4066 4067 4068
	.setup			= mv88e6xxx_setup,
	.adjust_link		= mv88e6xxx_adjust_link,
	.get_strings		= mv88e6xxx_get_strings,
	.get_ethtool_stats	= mv88e6xxx_get_ethtool_stats,
	.get_sset_count		= mv88e6xxx_get_sset_count,
4069 4070
	.port_enable		= mv88e6xxx_port_enable,
	.port_disable		= mv88e6xxx_port_disable,
V
Vivien Didelot 已提交
4071 4072
	.get_mac_eee		= mv88e6xxx_get_mac_eee,
	.set_mac_eee		= mv88e6xxx_set_mac_eee,
4073
	.get_eeprom_len		= mv88e6xxx_get_eeprom_len,
4074 4075 4076 4077
	.get_eeprom		= mv88e6xxx_get_eeprom,
	.set_eeprom		= mv88e6xxx_set_eeprom,
	.get_regs_len		= mv88e6xxx_get_regs_len,
	.get_regs		= mv88e6xxx_get_regs,
4078
	.set_ageing_time	= mv88e6xxx_set_ageing_time,
4079 4080 4081
	.port_bridge_join	= mv88e6xxx_port_bridge_join,
	.port_bridge_leave	= mv88e6xxx_port_bridge_leave,
	.port_stp_state_set	= mv88e6xxx_port_stp_state_set,
4082
	.port_fast_age		= mv88e6xxx_port_fast_age,
4083 4084 4085 4086 4087 4088 4089
	.port_vlan_filtering	= mv88e6xxx_port_vlan_filtering,
	.port_vlan_prepare	= mv88e6xxx_port_vlan_prepare,
	.port_vlan_add		= mv88e6xxx_port_vlan_add,
	.port_vlan_del		= mv88e6xxx_port_vlan_del,
	.port_fdb_add           = mv88e6xxx_port_fdb_add,
	.port_fdb_del           = mv88e6xxx_port_fdb_del,
	.port_fdb_dump          = mv88e6xxx_port_fdb_dump,
4090 4091 4092
	.port_mdb_prepare       = mv88e6xxx_port_mdb_prepare,
	.port_mdb_add           = mv88e6xxx_port_mdb_add,
	.port_mdb_del           = mv88e6xxx_port_mdb_del,
4093 4094
	.crosschip_bridge_join	= mv88e6xxx_crosschip_bridge_join,
	.crosschip_bridge_leave	= mv88e6xxx_crosschip_bridge_leave,
4095 4096 4097 4098 4099
	.port_hwtstamp_set	= mv88e6xxx_port_hwtstamp_set,
	.port_hwtstamp_get	= mv88e6xxx_port_hwtstamp_get,
	.port_txtstamp		= mv88e6xxx_port_txtstamp,
	.port_rxtstamp		= mv88e6xxx_port_rxtstamp,
	.get_ts_info		= mv88e6xxx_get_ts_info,
4100 4101
};

4102 4103 4104 4105
static struct dsa_switch_driver mv88e6xxx_switch_drv = {
	.ops			= &mv88e6xxx_switch_ops,
};

4106
static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
4107
{
4108
	struct device *dev = chip->dev;
4109 4110
	struct dsa_switch *ds;

4111
	ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip));
4112 4113 4114
	if (!ds)
		return -ENOMEM;

4115
	ds->priv = chip;
4116
	ds->ops = &mv88e6xxx_switch_ops;
4117 4118
	ds->ageing_time_min = chip->info->age_time_coeff;
	ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
4119 4120 4121

	dev_set_drvdata(dev, ds);

4122
	return dsa_register_switch(ds);
4123 4124
}

4125
static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
4126
{
4127
	dsa_unregister_switch(chip->ds);
4128 4129
}

4130
static int mv88e6xxx_probe(struct mdio_device *mdiodev)
4131
{
4132
	struct device *dev = &mdiodev->dev;
4133
	struct device_node *np = dev->of_node;
4134
	const struct mv88e6xxx_info *compat_info;
4135
	struct mv88e6xxx_chip *chip;
4136
	u32 eeprom_len;
4137
	int err;
4138

4139 4140 4141 4142
	compat_info = of_device_get_match_data(dev);
	if (!compat_info)
		return -EINVAL;

4143 4144
	chip = mv88e6xxx_alloc_chip(dev);
	if (!chip)
4145 4146
		return -ENOMEM;

4147
	chip->info = compat_info;
4148

4149
	err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4150 4151
	if (err)
		return err;
4152

4153 4154 4155 4156
	chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
	if (IS_ERR(chip->reset))
		return PTR_ERR(chip->reset);

4157
	err = mv88e6xxx_detect(chip);
4158 4159
	if (err)
		return err;
4160

4161 4162
	mv88e6xxx_phy_init(chip);

4163
	if (chip->info->ops->get_eeprom &&
4164
	    !of_property_read_u32(np, "eeprom-length", &eeprom_len))
4165
		chip->eeprom_len = eeprom_len;
4166

4167 4168 4169 4170 4171 4172 4173 4174 4175 4176 4177 4178
	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_switch_reset(chip);
	mutex_unlock(&chip->reg_lock);
	if (err)
		goto out;

	chip->irq = of_irq_get(np, 0);
	if (chip->irq == -EPROBE_DEFER) {
		err = chip->irq;
		goto out;
	}

4179
	/* Has to be performed before the MDIO bus is created, because
4180
	 * the PHYs will link their interrupts to these interrupt
4181 4182 4183 4184
	 * controllers
	 */
	mutex_lock(&chip->reg_lock);
	if (chip->irq > 0)
4185
		err = mv88e6xxx_g1_irq_setup(chip);
4186 4187 4188
	else
		err = mv88e6xxx_irq_poll_setup(chip);
	mutex_unlock(&chip->reg_lock);
4189

4190 4191
	if (err)
		goto out;
4192

4193 4194
	if (chip->info->g2_irqs > 0) {
		err = mv88e6xxx_g2_irq_setup(chip);
4195
		if (err)
4196
			goto out_g1_irq;
4197 4198
	}

4199 4200 4201 4202 4203 4204 4205 4206
	err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
	if (err)
		goto out_g2_irq;

	err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
	if (err)
		goto out_g1_atu_prob_irq;

4207
	err = mv88e6xxx_mdios_register(chip, np);
4208
	if (err)
4209
		goto out_g1_vtu_prob_irq;
4210

4211
	err = mv88e6xxx_register_switch(chip);
4212 4213
	if (err)
		goto out_mdio;
4214

4215
	return 0;
4216 4217

out_mdio:
4218
	mv88e6xxx_mdios_unregister(chip);
4219
out_g1_vtu_prob_irq:
4220
	mv88e6xxx_g1_vtu_prob_irq_free(chip);
4221
out_g1_atu_prob_irq:
4222
	mv88e6xxx_g1_atu_prob_irq_free(chip);
4223
out_g2_irq:
4224
	if (chip->info->g2_irqs > 0)
4225 4226
		mv88e6xxx_g2_irq_free(chip);
out_g1_irq:
4227 4228
	mutex_lock(&chip->reg_lock);
	if (chip->irq > 0)
4229
		mv88e6xxx_g1_irq_free(chip);
4230 4231 4232
	else
		mv88e6xxx_irq_poll_free(chip);
	mutex_unlock(&chip->reg_lock);
4233 4234
out:
	return err;
4235
}
4236 4237 4238 4239

static void mv88e6xxx_remove(struct mdio_device *mdiodev)
{
	struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
V
Vivien Didelot 已提交
4240
	struct mv88e6xxx_chip *chip = ds->priv;
4241

4242 4243
	if (chip->info->ptp_support) {
		mv88e6xxx_hwtstamp_free(chip);
4244
		mv88e6xxx_ptp_free(chip);
4245
	}
4246

4247
	mv88e6xxx_phy_destroy(chip);
4248
	mv88e6xxx_unregister_switch(chip);
4249
	mv88e6xxx_mdios_unregister(chip);
4250

4251 4252 4253 4254 4255 4256 4257 4258
	mv88e6xxx_g1_vtu_prob_irq_free(chip);
	mv88e6xxx_g1_atu_prob_irq_free(chip);

	if (chip->info->g2_irqs > 0)
		mv88e6xxx_g2_irq_free(chip);

	mutex_lock(&chip->reg_lock);
	if (chip->irq > 0)
4259
		mv88e6xxx_g1_irq_free(chip);
4260 4261 4262
	else
		mv88e6xxx_irq_poll_free(chip);
	mutex_unlock(&chip->reg_lock);
4263 4264 4265
}

static const struct of_device_id mv88e6xxx_of_match[] = {
4266 4267 4268 4269
	{
		.compatible = "marvell,mv88e6085",
		.data = &mv88e6xxx_table[MV88E6085],
	},
4270 4271 4272 4273
	{
		.compatible = "marvell,mv88e6190",
		.data = &mv88e6xxx_table[MV88E6190],
	},
4274 4275 4276 4277 4278 4279 4280 4281 4282 4283 4284 4285 4286 4287 4288 4289
	{ /* sentinel */ },
};

MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);

static struct mdio_driver mv88e6xxx_driver = {
	.probe	= mv88e6xxx_probe,
	.remove = mv88e6xxx_remove,
	.mdiodrv.driver = {
		.name = "mv88e6085",
		.of_match_table = mv88e6xxx_of_match,
	},
};

static int __init mv88e6xxx_init(void)
{
4290
	register_switch_driver(&mv88e6xxx_switch_drv);
4291 4292
	return mdio_driver_register(&mv88e6xxx_driver);
}
4293 4294 4295 4296
module_init(mv88e6xxx_init);

static void __exit mv88e6xxx_cleanup(void)
{
4297
	mdio_driver_unregister(&mv88e6xxx_driver);
4298
	unregister_switch_driver(&mv88e6xxx_switch_drv);
4299 4300
}
module_exit(mv88e6xxx_cleanup);
4301 4302 4303 4304

MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
MODULE_LICENSE("GPL");