chip.c 119.6 KB
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/*
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 * Marvell 88e6xxx Ethernet switch single-chip support
 *
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 * Copyright (c) 2008 Marvell Semiconductor
 *
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 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
 *
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 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
 *	Vivien Didelot <vivien.didelot@savoirfairelinux.com>
 *
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 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

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#include <linux/delay.h>
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#include <linux/etherdevice.h>
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#include <linux/ethtool.h>
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#include <linux/if_bridge.h>
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#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
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#include <linux/jiffies.h>
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#include <linux/list.h>
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#include <linux/mdio.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/of_mdio.h>
31
#include <linux/netdevice.h>
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#include <linux/gpio/consumer.h>
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#include <linux/phy.h>
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#include <net/dsa.h>
35

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#include "chip.h"
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#include "global1.h"
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#include "global2.h"
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#include "hwtstamp.h"
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#include "phy.h"
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#include "port.h"
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#include "ptp.h"
43
#include "serdes.h"
44

45
static void assert_reg_lock(struct mv88e6xxx_chip *chip)
46
{
47 48
	if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
		dev_err(chip->dev, "Switch registers lock not held!\n");
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		dump_stack();
	}
}

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/* The switch ADDR[4:1] configuration pins define the chip SMI device address
 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
 *
 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
 * is the only device connected to the SMI master. In this mode it responds to
 * all 32 possible SMI addresses, and thus maps directly the internal devices.
 *
 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
 * multiple devices to share the SMI interface. In this mode it responds to only
 * 2 registers, used to indirectly access the internal SMI devices.
63
 */
64

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static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
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			      int addr, int reg, u16 *val)
{
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	if (!chip->smi_ops)
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		return -EOPNOTSUPP;

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	return chip->smi_ops->read(chip, addr, reg, val);
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}

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static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
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			       int addr, int reg, u16 val)
{
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	if (!chip->smi_ops)
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		return -EOPNOTSUPP;

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	return chip->smi_ops->write(chip, addr, reg, val);
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}

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static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
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					  int addr, int reg, u16 *val)
{
	int ret;

88
	ret = mdiobus_read_nested(chip->bus, addr, reg);
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	if (ret < 0)
		return ret;

	*val = ret & 0xffff;

	return 0;
}

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static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
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					   int addr, int reg, u16 val)
{
	int ret;

102
	ret = mdiobus_write_nested(chip->bus, addr, reg, val);
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	if (ret < 0)
		return ret;

	return 0;
}

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static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
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	.read = mv88e6xxx_smi_single_chip_read,
	.write = mv88e6xxx_smi_single_chip_write,
};

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static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
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{
	int ret;
	int i;

	for (i = 0; i < 16; i++) {
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		ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
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		if (ret < 0)
			return ret;

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		if ((ret & SMI_CMD_BUSY) == 0)
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			return 0;
	}

	return -ETIMEDOUT;
}

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static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
132
					 int addr, int reg, u16 *val)
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{
	int ret;

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	/* Wait for the bus to become free. */
137
	ret = mv88e6xxx_smi_multi_chip_wait(chip);
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	if (ret < 0)
		return ret;

141
	/* Transmit the read command. */
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	ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
143
				   SMI_CMD_OP_22_READ | (addr << 5) | reg);
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	if (ret < 0)
		return ret;

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	/* Wait for the read command to complete. */
148
	ret = mv88e6xxx_smi_multi_chip_wait(chip);
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	if (ret < 0)
		return ret;

152
	/* Read the data. */
153
	ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
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	if (ret < 0)
		return ret;

157
	*val = ret & 0xffff;
158

159
	return 0;
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}

162
static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
163
					  int addr, int reg, u16 val)
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{
	int ret;

167
	/* Wait for the bus to become free. */
168
	ret = mv88e6xxx_smi_multi_chip_wait(chip);
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	if (ret < 0)
		return ret;

172
	/* Transmit the data to write. */
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	ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
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	if (ret < 0)
		return ret;

177
	/* Transmit the write command. */
178
	ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
179
				   SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
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	if (ret < 0)
		return ret;

183
	/* Wait for the write command to complete. */
184
	ret = mv88e6xxx_smi_multi_chip_wait(chip);
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	if (ret < 0)
		return ret;

	return 0;
}

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static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
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	.read = mv88e6xxx_smi_multi_chip_read,
	.write = mv88e6xxx_smi_multi_chip_write,
};

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int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
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{
	int err;

200
	assert_reg_lock(chip);
201

202
	err = mv88e6xxx_smi_read(chip, addr, reg, val);
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	if (err)
		return err;

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	dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
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		addr, reg, *val);

	return 0;
}

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int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
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{
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	int err;

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	assert_reg_lock(chip);
217

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	err = mv88e6xxx_smi_write(chip, addr, reg, val);
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	if (err)
		return err;

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	dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
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		addr, reg, val);

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	return 0;
}

228
struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
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{
	struct mv88e6xxx_mdio_bus *mdio_bus;

	mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
				    list);
	if (!mdio_bus)
		return NULL;

	return mdio_bus->bus;
}

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static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
{
	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int n = d->hwirq;

	chip->g1_irq.masked |= (1 << n);
}

static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
{
	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int n = d->hwirq;

	chip->g1_irq.masked &= ~(1 << n);
}

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static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
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{
	unsigned int nhandled = 0;
	unsigned int sub_irq;
	unsigned int n;
	u16 reg;
	int err;

	mutex_lock(&chip->reg_lock);
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	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
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	mutex_unlock(&chip->reg_lock);

	if (err)
		goto out;

	for (n = 0; n < chip->g1_irq.nirqs; ++n) {
		if (reg & (1 << n)) {
			sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
			handle_nested_irq(sub_irq);
			++nhandled;
		}
	}
out:
	return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
}

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static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
{
	struct mv88e6xxx_chip *chip = dev_id;

	return mv88e6xxx_g1_irq_thread_work(chip);
}

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static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
{
	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);

	mutex_lock(&chip->reg_lock);
}

static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
{
	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
	u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
	u16 reg;
	int err;

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	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
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	if (err)
		goto out;

	reg &= ~mask;
	reg |= (~chip->g1_irq.masked & mask);

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	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
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	if (err)
		goto out;

out:
	mutex_unlock(&chip->reg_lock);
}

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static const struct irq_chip mv88e6xxx_g1_irq_chip = {
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	.name			= "mv88e6xxx-g1",
	.irq_mask		= mv88e6xxx_g1_irq_mask,
	.irq_unmask		= mv88e6xxx_g1_irq_unmask,
	.irq_bus_lock		= mv88e6xxx_g1_irq_bus_lock,
	.irq_bus_sync_unlock	= mv88e6xxx_g1_irq_bus_sync_unlock,
};

static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
				       unsigned int irq,
				       irq_hw_number_t hwirq)
{
	struct mv88e6xxx_chip *chip = d->host_data;

	irq_set_chip_data(irq, d->host_data);
	irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
	irq_set_noprobe(irq);

	return 0;
}

static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
	.map	= mv88e6xxx_g1_irq_domain_map,
	.xlate	= irq_domain_xlate_twocell,
};

344
static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
345 346
{
	int irq, virq;
347 348
	u16 mask;

349
	mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
350
	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
351
	mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
352

353
	for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
354
		virq = irq_find_mapping(chip->g1_irq.domain, irq);
355 356 357
		irq_dispose_mapping(virq);
	}

358
	irq_domain_remove(chip->g1_irq.domain);
359 360
}

361 362
static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
{
363
	mv88e6xxx_g1_irq_free_common(chip);
364 365 366 367 368

	free_irq(chip->irq, chip);
}

static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
369
{
370 371
	int err, irq, virq;
	u16 reg, mask;
372 373 374 375 376 377 378 379 380 381 382 383 384 385

	chip->g1_irq.nirqs = chip->info->g1_irqs;
	chip->g1_irq.domain = irq_domain_add_simple(
		NULL, chip->g1_irq.nirqs, 0,
		&mv88e6xxx_g1_irq_domain_ops, chip);
	if (!chip->g1_irq.domain)
		return -ENOMEM;

	for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
		irq_create_mapping(chip->g1_irq.domain, irq);

	chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
	chip->g1_irq.masked = ~0;

386
	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
387
	if (err)
388
		goto out_mapping;
389

390
	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
391

392
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
393
	if (err)
394
		goto out_disable;
395 396

	/* Reading the interrupt status clears (most of) them */
397
	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
398
	if (err)
399
		goto out_disable;
400 401 402

	return 0;

403
out_disable:
404
	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
405
	mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
406 407 408 409 410 411 412 413

out_mapping:
	for (irq = 0; irq < 16; irq++) {
		virq = irq_find_mapping(chip->g1_irq.domain, irq);
		irq_dispose_mapping(virq);
	}

	irq_domain_remove(chip->g1_irq.domain);
414 415 416 417

	return err;
}

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static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
{
	int err;

	err = mv88e6xxx_g1_irq_setup_common(chip);
	if (err)
		return err;

	err = request_threaded_irq(chip->irq, NULL,
				   mv88e6xxx_g1_irq_thread_fn,
				   IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
				   dev_name(chip->dev), chip);
	if (err)
		mv88e6xxx_g1_irq_free_common(chip);

	return err;
}

static void mv88e6xxx_irq_poll(struct kthread_work *work)
{
	struct mv88e6xxx_chip *chip = container_of(work,
						   struct mv88e6xxx_chip,
						   irq_poll_work.work);
	mv88e6xxx_g1_irq_thread_work(chip);

	kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
				   msecs_to_jiffies(100));
}

static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
{
	int err;

	err = mv88e6xxx_g1_irq_setup_common(chip);
	if (err)
		return err;

	kthread_init_delayed_work(&chip->irq_poll_work,
				  mv88e6xxx_irq_poll);

	chip->kworker = kthread_create_worker(0, dev_name(chip->dev));
	if (IS_ERR(chip->kworker))
		return PTR_ERR(chip->kworker);

	kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
				   msecs_to_jiffies(100));

	return 0;
}

static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
{
	kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
	kthread_destroy_worker(chip->kworker);
}

474
int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
475
{
476
	int i;
477

478
	for (i = 0; i < 16; i++) {
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		u16 val;
		int err;

		err = mv88e6xxx_read(chip, addr, reg, &val);
		if (err)
			return err;

		if (!(val & mask))
			return 0;

		usleep_range(1000, 2000);
	}

492
	dev_err(chip->dev, "Timeout while waiting for switch\n");
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	return -ETIMEDOUT;
}

496
/* Indirect write to single pointer-data register with an Update bit */
497
int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
498 499
{
	u16 val;
500
	int err;
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	/* Wait until the previous operation is completed */
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	err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
	if (err)
		return err;
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	/* Set the Update bit to trigger a write operation */
	val = BIT(15) | update;

	return mv88e6xxx_write(chip, addr, reg, val);
}

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static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
				    int link, int speed, int duplex,
				    phy_interface_t mode)
{
	int err;

	if (!chip->info->ops->port_set_link)
		return 0;

	/* Port's MAC control must not be changed unless the link is down */
	err = chip->info->ops->port_set_link(chip, port, 0);
	if (err)
		return err;

	if (chip->info->ops->port_set_speed) {
		err = chip->info->ops->port_set_speed(chip, port, speed);
		if (err && err != -EOPNOTSUPP)
			goto restore_link;
	}

	if (chip->info->ops->port_set_duplex) {
		err = chip->info->ops->port_set_duplex(chip, port, duplex);
		if (err && err != -EOPNOTSUPP)
			goto restore_link;
	}

	if (chip->info->ops->port_set_rgmii_delay) {
		err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
		if (err && err != -EOPNOTSUPP)
			goto restore_link;
	}

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	if (chip->info->ops->port_set_cmode) {
		err = chip->info->ops->port_set_cmode(chip, port, mode);
		if (err && err != -EOPNOTSUPP)
			goto restore_link;
	}

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	err = 0;
restore_link:
	if (chip->info->ops->port_set_link(chip, port, link))
554
		dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
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	return err;
}

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/* We expect the switch to perform auto negotiation if there is a real
 * phy. However, in the case of a fixed link phy, we force the port
 * settings from the fixed link settings.
 */
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static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
				  struct phy_device *phydev)
565
{
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Vivien Didelot 已提交
566
	struct mv88e6xxx_chip *chip = ds->priv;
567
	int err;
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	if (!phy_is_pseudo_fixed_link(phydev))
		return;

572
	mutex_lock(&chip->reg_lock);
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	err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
				       phydev->duplex, phydev->interface);
575
	mutex_unlock(&chip->reg_lock);
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	if (err && err != -EOPNOTSUPP)
578
		dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
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}

581
static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
582
{
583 584
	if (!chip->info->ops->stats_snapshot)
		return -EOPNOTSUPP;
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586
	return chip->info->ops->stats_snapshot(chip, port);
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}

589
static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
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	{ "in_good_octets",		8, 0x00, STATS_TYPE_BANK0, },
	{ "in_bad_octets",		4, 0x02, STATS_TYPE_BANK0, },
	{ "in_unicast",			4, 0x04, STATS_TYPE_BANK0, },
	{ "in_broadcasts",		4, 0x06, STATS_TYPE_BANK0, },
	{ "in_multicasts",		4, 0x07, STATS_TYPE_BANK0, },
	{ "in_pause",			4, 0x16, STATS_TYPE_BANK0, },
	{ "in_undersize",		4, 0x18, STATS_TYPE_BANK0, },
	{ "in_fragments",		4, 0x19, STATS_TYPE_BANK0, },
	{ "in_oversize",		4, 0x1a, STATS_TYPE_BANK0, },
	{ "in_jabber",			4, 0x1b, STATS_TYPE_BANK0, },
	{ "in_rx_error",		4, 0x1c, STATS_TYPE_BANK0, },
	{ "in_fcs_error",		4, 0x1d, STATS_TYPE_BANK0, },
	{ "out_octets",			8, 0x0e, STATS_TYPE_BANK0, },
	{ "out_unicast",		4, 0x10, STATS_TYPE_BANK0, },
	{ "out_broadcasts",		4, 0x13, STATS_TYPE_BANK0, },
	{ "out_multicasts",		4, 0x12, STATS_TYPE_BANK0, },
	{ "out_pause",			4, 0x15, STATS_TYPE_BANK0, },
	{ "excessive",			4, 0x11, STATS_TYPE_BANK0, },
	{ "collisions",			4, 0x1e, STATS_TYPE_BANK0, },
	{ "deferred",			4, 0x05, STATS_TYPE_BANK0, },
	{ "single",			4, 0x14, STATS_TYPE_BANK0, },
	{ "multiple",			4, 0x17, STATS_TYPE_BANK0, },
	{ "out_fcs_error",		4, 0x03, STATS_TYPE_BANK0, },
	{ "late",			4, 0x1f, STATS_TYPE_BANK0, },
	{ "hist_64bytes",		4, 0x08, STATS_TYPE_BANK0, },
	{ "hist_65_127bytes",		4, 0x09, STATS_TYPE_BANK0, },
	{ "hist_128_255bytes",		4, 0x0a, STATS_TYPE_BANK0, },
	{ "hist_256_511bytes",		4, 0x0b, STATS_TYPE_BANK0, },
	{ "hist_512_1023bytes",		4, 0x0c, STATS_TYPE_BANK0, },
	{ "hist_1024_max_bytes",	4, 0x0d, STATS_TYPE_BANK0, },
	{ "sw_in_discards",		4, 0x10, STATS_TYPE_PORT, },
	{ "sw_in_filtered",		2, 0x12, STATS_TYPE_PORT, },
	{ "sw_out_filtered",		2, 0x13, STATS_TYPE_PORT, },
	{ "in_discards",		4, 0x00, STATS_TYPE_BANK1, },
	{ "in_filtered",		4, 0x01, STATS_TYPE_BANK1, },
	{ "in_accepted",		4, 0x02, STATS_TYPE_BANK1, },
	{ "in_bad_accepted",		4, 0x03, STATS_TYPE_BANK1, },
	{ "in_good_avb_class_a",	4, 0x04, STATS_TYPE_BANK1, },
	{ "in_good_avb_class_b",	4, 0x05, STATS_TYPE_BANK1, },
	{ "in_bad_avb_class_a",		4, 0x06, STATS_TYPE_BANK1, },
	{ "in_bad_avb_class_b",		4, 0x07, STATS_TYPE_BANK1, },
	{ "tcam_counter_0",		4, 0x08, STATS_TYPE_BANK1, },
	{ "tcam_counter_1",		4, 0x09, STATS_TYPE_BANK1, },
	{ "tcam_counter_2",		4, 0x0a, STATS_TYPE_BANK1, },
	{ "tcam_counter_3",		4, 0x0b, STATS_TYPE_BANK1, },
	{ "in_da_unknown",		4, 0x0e, STATS_TYPE_BANK1, },
	{ "in_management",		4, 0x0f, STATS_TYPE_BANK1, },
	{ "out_queue_0",		4, 0x10, STATS_TYPE_BANK1, },
	{ "out_queue_1",		4, 0x11, STATS_TYPE_BANK1, },
	{ "out_queue_2",		4, 0x12, STATS_TYPE_BANK1, },
	{ "out_queue_3",		4, 0x13, STATS_TYPE_BANK1, },
	{ "out_queue_4",		4, 0x14, STATS_TYPE_BANK1, },
	{ "out_queue_5",		4, 0x15, STATS_TYPE_BANK1, },
	{ "out_queue_6",		4, 0x16, STATS_TYPE_BANK1, },
	{ "out_queue_7",		4, 0x17, STATS_TYPE_BANK1, },
	{ "out_cut_through",		4, 0x18, STATS_TYPE_BANK1, },
	{ "out_octets_a",		4, 0x1a, STATS_TYPE_BANK1, },
	{ "out_octets_b",		4, 0x1b, STATS_TYPE_BANK1, },
	{ "out_management",		4, 0x1f, STATS_TYPE_BANK1, },
649 650
};

651
static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
652
					    struct mv88e6xxx_hw_stat *s,
653 654
					    int port, u16 bank1_select,
					    u16 histogram)
655 656 657
{
	u32 low;
	u32 high = 0;
658
	u16 reg = 0;
659
	int err;
660 661
	u64 value;

662
	switch (s->type) {
663
	case STATS_TYPE_PORT:
664 665
		err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
		if (err)
666 667
			return UINT64_MAX;

668
		low = reg;
669
		if (s->size == 4) {
670 671
			err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
			if (err)
672
				return UINT64_MAX;
673
			high = reg;
674
		}
675
		break;
676
	case STATS_TYPE_BANK1:
677
		reg = bank1_select;
678 679
		/* fall through */
	case STATS_TYPE_BANK0:
680
		reg |= s->reg | histogram;
681
		mv88e6xxx_g1_stats_read(chip, reg, &low);
682
		if (s->size == 8)
683
			mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
684 685 686
		break;
	default:
		return UINT64_MAX;
687 688 689 690 691
	}
	value = (((u64)high) << 16) | low;
	return value;
}

692 693
static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
				       uint8_t *data, int types)
694
{
695 696
	struct mv88e6xxx_hw_stat *stat;
	int i, j;
697

698 699
	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
		stat = &mv88e6xxx_hw_stats[i];
700
		if (stat->type & types) {
701 702 703 704
			memcpy(data + j * ETH_GSTRING_LEN, stat->string,
			       ETH_GSTRING_LEN);
			j++;
		}
705
	}
706 707

	return j;
708 709
}

710 711
static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
				       uint8_t *data)
712
{
713 714
	return mv88e6xxx_stats_get_strings(chip, data,
					   STATS_TYPE_BANK0 | STATS_TYPE_PORT);
715 716
}

717 718
static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
				       uint8_t *data)
719
{
720 721
	return mv88e6xxx_stats_get_strings(chip, data,
					   STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
722 723 724 725
}

static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
				  uint8_t *data)
726
{
V
Vivien Didelot 已提交
727
	struct mv88e6xxx_chip *chip = ds->priv;
728
	int count = 0;
729

730 731
	mutex_lock(&chip->reg_lock);

732
	if (chip->info->ops->stats_get_strings)
733 734 735 736 737 738
		count = chip->info->ops->stats_get_strings(chip, data);

	if (chip->info->ops->serdes_get_strings) {
		data += count * ETH_GSTRING_LEN;
		chip->info->ops->serdes_get_strings(chip, port, data);
	}
739 740

	mutex_unlock(&chip->reg_lock);
741 742 743 744 745
}

static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
					  int types)
{
746 747 748 749 750
	struct mv88e6xxx_hw_stat *stat;
	int i, j;

	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
		stat = &mv88e6xxx_hw_stats[i];
751
		if (stat->type & types)
752 753 754
			j++;
	}
	return j;
755 756
}

757 758 759 760 761 762 763 764 765 766 767 768
static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
{
	return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
					      STATS_TYPE_PORT);
}

static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
{
	return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
					      STATS_TYPE_BANK1);
}

769
static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port)
770 771
{
	struct mv88e6xxx_chip *chip = ds->priv;
772 773
	int serdes_count = 0;
	int count = 0;
774

775
	mutex_lock(&chip->reg_lock);
776
	if (chip->info->ops->stats_get_sset_count)
777 778 779 780 781 782 783 784 785 786 787 788
		count = chip->info->ops->stats_get_sset_count(chip);
	if (count < 0)
		goto out;

	if (chip->info->ops->serdes_get_sset_count)
		serdes_count = chip->info->ops->serdes_get_sset_count(chip,
								      port);
	if (serdes_count < 0)
		count = serdes_count;
	else
		count += serdes_count;
out:
789
	mutex_unlock(&chip->reg_lock);
790

791
	return count;
792 793
}

794 795 796
static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
				     uint64_t *data, int types,
				     u16 bank1_select, u16 histogram)
797 798 799 800 801 802 803
{
	struct mv88e6xxx_hw_stat *stat;
	int i, j;

	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
		stat = &mv88e6xxx_hw_stats[i];
		if (stat->type & types) {
804
			mutex_lock(&chip->reg_lock);
805 806 807
			data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
							      bank1_select,
							      histogram);
808 809
			mutex_unlock(&chip->reg_lock);

810 811 812
			j++;
		}
	}
813
	return j;
814 815
}

816 817
static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
				     uint64_t *data)
818 819
{
	return mv88e6xxx_stats_get_stats(chip, port, data,
820
					 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
821
					 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
822 823
}

824 825
static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
				     uint64_t *data)
826 827
{
	return mv88e6xxx_stats_get_stats(chip, port, data,
828
					 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
829 830
					 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
					 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
831 832
}

833 834
static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
				     uint64_t *data)
835 836 837
{
	return mv88e6xxx_stats_get_stats(chip, port, data,
					 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
838 839
					 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
					 0);
840 841 842 843 844
}

static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
				uint64_t *data)
{
845 846
	int count = 0;

847
	if (chip->info->ops->stats_get_stats)
848 849 850 851
		count = chip->info->ops->stats_get_stats(chip, port, data);

	if (chip->info->ops->serdes_get_stats) {
		data += count;
852
		mutex_lock(&chip->reg_lock);
853
		chip->info->ops->serdes_get_stats(chip, port, data);
854
		mutex_unlock(&chip->reg_lock);
855
	}
856 857
}

858 859
static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
					uint64_t *data)
860
{
V
Vivien Didelot 已提交
861
	struct mv88e6xxx_chip *chip = ds->priv;
862 863
	int ret;

864
	mutex_lock(&chip->reg_lock);
865

866
	ret = mv88e6xxx_stats_snapshot(chip, port);
867 868 869
	mutex_unlock(&chip->reg_lock);

	if (ret < 0)
870
		return;
871 872

	mv88e6xxx_get_stats(chip, port, data);
873

874 875
}

876 877 878 879 880 881 882 883
static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->stats_set_histogram)
		return chip->info->ops->stats_set_histogram(chip);

	return 0;
}

884
static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
885 886 887 888
{
	return 32 * sizeof(u16);
}

889 890
static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
			       struct ethtool_regs *regs, void *_p)
891
{
V
Vivien Didelot 已提交
892
	struct mv88e6xxx_chip *chip = ds->priv;
893 894
	int err;
	u16 reg;
895 896 897 898 899 900 901
	u16 *p = _p;
	int i;

	regs->version = 0;

	memset(p, 0xff, 32 * sizeof(u16));

902
	mutex_lock(&chip->reg_lock);
903

904 905
	for (i = 0; i < 32; i++) {

906 907 908
		err = mv88e6xxx_port_read(chip, port, i, &reg);
		if (!err)
			p[i] = reg;
909
	}
910

911
	mutex_unlock(&chip->reg_lock);
912 913
}

V
Vivien Didelot 已提交
914 915
static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
				 struct ethtool_eee *e)
916
{
917 918
	/* Nothing to do on the port's MAC */
	return 0;
919 920
}

V
Vivien Didelot 已提交
921 922
static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
				 struct ethtool_eee *e)
923
{
924 925
	/* Nothing to do on the port's MAC */
	return 0;
926 927
}

928
static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
929
{
930 931 932
	struct dsa_switch *ds = NULL;
	struct net_device *br;
	u16 pvlan;
933 934
	int i;

935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954
	if (dev < DSA_MAX_SWITCHES)
		ds = chip->ds->dst->ds[dev];

	/* Prevent frames from unknown switch or port */
	if (!ds || port >= ds->num_ports)
		return 0;

	/* Frames from DSA links and CPU ports can egress any local port */
	if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
		return mv88e6xxx_port_mask(chip);

	br = ds->ports[port].bridge_dev;
	pvlan = 0;

	/* Frames from user ports can egress any local DSA links and CPU ports,
	 * as well as any local member of their bridge group.
	 */
	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
		if (dsa_is_cpu_port(chip->ds, i) ||
		    dsa_is_dsa_port(chip->ds, i) ||
V
Vivien Didelot 已提交
955
		    (br && dsa_to_port(chip->ds, i)->bridge_dev == br))
956 957 958 959 960
			pvlan |= BIT(i);

	return pvlan;
}

961
static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
962 963
{
	u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
964 965 966

	/* prevent frames from going back out of the port they came in on */
	output_ports &= ~BIT(port);
967

968
	return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
969 970
}

971 972
static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
					 u8 state)
973
{
V
Vivien Didelot 已提交
974
	struct mv88e6xxx_chip *chip = ds->priv;
975
	int err;
976

977
	mutex_lock(&chip->reg_lock);
978
	err = mv88e6xxx_port_set_state(chip, port, state);
979
	mutex_unlock(&chip->reg_lock);
980 981

	if (err)
982
		dev_err(ds->dev, "p%d: failed to update state\n", port);
983 984
}

985 986 987 988 989 990 991 992
static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->pot_clear)
		return chip->info->ops->pot_clear(chip);

	return 0;
}

993 994 995 996 997 998 999 1000
static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->mgmt_rsvd2cpu)
		return chip->info->ops->mgmt_rsvd2cpu(chip);

	return 0;
}

1001 1002
static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
{
1003 1004
	int err;

1005 1006 1007 1008
	err = mv88e6xxx_g1_atu_flush(chip, 0, true);
	if (err)
		return err;

1009 1010 1011 1012
	err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
	if (err)
		return err;

1013 1014 1015
	return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
}

1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035
static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
{
	int port;
	int err;

	if (!chip->info->ops->irl_init_all)
		return 0;

	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
		/* Disable ingress rate limiting by resetting all per port
		 * ingress rate limit resources to their initial state.
		 */
		err = chip->info->ops->irl_init_all(chip, port);
		if (err)
			return err;
	}

	return 0;
}

1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048
static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->set_switch_mac) {
		u8 addr[ETH_ALEN];

		eth_random_addr(addr);

		return chip->info->ops->set_switch_mac(chip, addr);
	}

	return 0;
}

1049 1050 1051 1052 1053 1054 1055 1056 1057
static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
{
	u16 pvlan = 0;

	if (!mv88e6xxx_has_pvt(chip))
		return -EOPNOTSUPP;

	/* Skip the local source device, which uses in-chip port VLAN */
	if (dev != chip->ds->index)
1058
		pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1059 1060 1061 1062

	return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
}

1063 1064
static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
{
1065 1066 1067
	int dev, port;
	int err;

1068 1069 1070 1071 1072 1073
	if (!mv88e6xxx_has_pvt(chip))
		return 0;

	/* Clear 5 Bit Port for usage with Marvell Link Street devices:
	 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
	 */
1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086
	err = mv88e6xxx_g2_misc_4_bit_port(chip);
	if (err)
		return err;

	for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
		for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
			err = mv88e6xxx_pvt_map(chip, dev, port);
			if (err)
				return err;
		}
	}

	return 0;
1087 1088
}

1089 1090 1091 1092 1093 1094
static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int err;

	mutex_lock(&chip->reg_lock);
1095
	err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
1096 1097 1098
	mutex_unlock(&chip->reg_lock);

	if (err)
1099
		dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
1100 1101
}

1102 1103 1104 1105 1106 1107 1108 1109
static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
{
	if (!chip->info->max_vid)
		return 0;

	return mv88e6xxx_g1_vtu_flush(chip);
}

1110 1111 1112 1113 1114 1115 1116 1117 1118
static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
				 struct mv88e6xxx_vtu_entry *entry)
{
	if (!chip->info->ops->vtu_getnext)
		return -EOPNOTSUPP;

	return chip->info->ops->vtu_getnext(chip, entry);
}

1119 1120 1121 1122 1123 1124 1125 1126 1127
static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
				   struct mv88e6xxx_vtu_entry *entry)
{
	if (!chip->info->ops->vtu_loadpurge)
		return -EOPNOTSUPP;

	return chip->info->ops->vtu_loadpurge(chip, entry);
}

1128
static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1129 1130
{
	DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1131 1132 1133
	struct mv88e6xxx_vtu_entry vlan = {
		.vid = chip->info->max_vid,
	};
1134
	int i, err;
1135 1136 1137

	bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);

1138
	/* Set every FID bit used by the (un)bridged ports */
1139
	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1140
		err = mv88e6xxx_port_get_fid(chip, i, fid);
1141 1142 1143 1144 1145 1146
		if (err)
			return err;

		set_bit(*fid, fid_bitmap);
	}

1147 1148
	/* Set every FID bit used by the VLAN entries */
	do {
1149
		err = mv88e6xxx_vtu_getnext(chip, &vlan);
1150 1151 1152 1153 1154 1155 1156
		if (err)
			return err;

		if (!vlan.valid)
			break;

		set_bit(vlan.fid, fid_bitmap);
1157
	} while (vlan.vid < chip->info->max_vid);
1158 1159 1160 1161 1162

	/* The reset value 0x000 is used to indicate that multiple address
	 * databases are not needed. Return the next positive available.
	 */
	*fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1163
	if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1164 1165 1166
		return -ENOSPC;

	/* Clear the database */
1167
	return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1168 1169
}

1170 1171
static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
			     struct mv88e6xxx_vtu_entry *entry, bool new)
1172 1173 1174 1175 1176 1177
{
	int err;

	if (!vid)
		return -EINVAL;

1178 1179
	entry->vid = vid - 1;
	entry->valid = false;
1180

1181
	err = mv88e6xxx_vtu_getnext(chip, entry);
1182 1183 1184
	if (err)
		return err;

1185 1186
	if (entry->vid == vid && entry->valid)
		return 0;
1187

1188 1189 1190 1191 1192 1193 1194 1195
	if (new) {
		int i;

		/* Initialize a fresh VLAN entry */
		memset(entry, 0, sizeof(*entry));
		entry->valid = true;
		entry->vid = vid;

1196
		/* Exclude all ports */
1197
		for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1198
			entry->member[i] =
1199
				MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1200 1201

		return mv88e6xxx_atu_new(chip, &entry->fid);
1202 1203
	}

1204 1205
	/* switchdev expects -EOPNOTSUPP to honor software VLANs */
	return -EOPNOTSUPP;
1206 1207
}

1208 1209 1210
static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
					u16 vid_begin, u16 vid_end)
{
V
Vivien Didelot 已提交
1211
	struct mv88e6xxx_chip *chip = ds->priv;
1212 1213 1214
	struct mv88e6xxx_vtu_entry vlan = {
		.vid = vid_begin - 1,
	};
1215 1216
	int i, err;

1217 1218 1219 1220
	/* DSA and CPU ports have to be members of multiple vlans */
	if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
		return 0;

1221 1222 1223
	if (!vid_begin)
		return -EOPNOTSUPP;

1224
	mutex_lock(&chip->reg_lock);
1225 1226

	do {
1227
		err = mv88e6xxx_vtu_getnext(chip, &vlan);
1228 1229 1230 1231 1232 1233 1234 1235 1236
		if (err)
			goto unlock;

		if (!vlan.valid)
			break;

		if (vlan.vid > vid_end)
			break;

1237
		for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1238 1239 1240
			if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
				continue;

1241
			if (!ds->ports[i].slave)
1242 1243
				continue;

1244
			if (vlan.member[i] ==
1245
			    MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1246 1247
				continue;

V
Vivien Didelot 已提交
1248
			if (dsa_to_port(ds, i)->bridge_dev ==
1249
			    ds->ports[port].bridge_dev)
1250 1251
				break; /* same bridge, check next VLAN */

V
Vivien Didelot 已提交
1252
			if (!dsa_to_port(ds, i)->bridge_dev)
1253 1254
				continue;

1255 1256
			dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
				port, vlan.vid, i,
V
Vivien Didelot 已提交
1257
				netdev_name(dsa_to_port(ds, i)->bridge_dev));
1258 1259 1260 1261 1262 1263
			err = -EOPNOTSUPP;
			goto unlock;
		}
	} while (vlan.vid < vid_end);

unlock:
1264
	mutex_unlock(&chip->reg_lock);
1265 1266 1267 1268

	return err;
}

1269 1270
static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
					 bool vlan_filtering)
1271
{
V
Vivien Didelot 已提交
1272
	struct mv88e6xxx_chip *chip = ds->priv;
1273 1274
	u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
		MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1275
	int err;
1276

1277
	if (!chip->info->max_vid)
1278 1279
		return -EOPNOTSUPP;

1280
	mutex_lock(&chip->reg_lock);
1281
	err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1282
	mutex_unlock(&chip->reg_lock);
1283

1284
	return err;
1285 1286
}

1287 1288
static int
mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1289
			    const struct switchdev_obj_port_vlan *vlan)
1290
{
V
Vivien Didelot 已提交
1291
	struct mv88e6xxx_chip *chip = ds->priv;
1292 1293
	int err;

1294
	if (!chip->info->max_vid)
1295 1296
		return -EOPNOTSUPP;

1297 1298 1299 1300 1301 1302 1303 1304
	/* If the requested port doesn't belong to the same bridge as the VLAN
	 * members, do not support it (yet) and fallback to software VLAN.
	 */
	err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
					   vlan->vid_end);
	if (err)
		return err;

1305 1306 1307 1308 1309 1310
	/* We don't need any dynamic resource from the kernel (yet),
	 * so skip the prepare phase.
	 */
	return 0;
}

1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354
static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
					const unsigned char *addr, u16 vid,
					u8 state)
{
	struct mv88e6xxx_vtu_entry vlan;
	struct mv88e6xxx_atu_entry entry;
	int err;

	/* Null VLAN ID corresponds to the port private database */
	if (vid == 0)
		err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
	else
		err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
	if (err)
		return err;

	entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
	ether_addr_copy(entry.mac, addr);
	eth_addr_dec(entry.mac);

	err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
	if (err)
		return err;

	/* Initialize a fresh ATU entry if it isn't found */
	if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED ||
	    !ether_addr_equal(entry.mac, addr)) {
		memset(&entry, 0, sizeof(entry));
		ether_addr_copy(entry.mac, addr);
	}

	/* Purge the ATU entry only if no port is using it anymore */
	if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
		entry.portvec &= ~BIT(port);
		if (!entry.portvec)
			entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
	} else {
		entry.portvec |= BIT(port);
		entry.state = state;
	}

	return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
}

1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377
static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
					u16 vid)
{
	const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
	u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;

	return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
}

static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
{
	int port;
	int err;

	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
		err = mv88e6xxx_port_add_broadcast(chip, port, vid);
		if (err)
			return err;
	}

	return 0;
}

1378
static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1379
				    u16 vid, u8 member)
1380
{
1381
	struct mv88e6xxx_vtu_entry vlan;
1382 1383
	int err;

1384
	err = mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1385
	if (err)
1386
		return err;
1387

1388
	vlan.member[port] = member;
1389

1390 1391 1392 1393 1394
	err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
	if (err)
		return err;

	return mv88e6xxx_broadcast_setup(chip, vid);
1395 1396
}

1397
static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1398
				    const struct switchdev_obj_port_vlan *vlan)
1399
{
V
Vivien Didelot 已提交
1400
	struct mv88e6xxx_chip *chip = ds->priv;
1401 1402
	bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
	bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1403
	u8 member;
1404 1405
	u16 vid;

1406
	if (!chip->info->max_vid)
1407 1408
		return;

1409
	if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1410
		member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
1411
	else if (untagged)
1412
		member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
1413
	else
1414
		member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
1415

1416
	mutex_lock(&chip->reg_lock);
1417

1418
	for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1419
		if (_mv88e6xxx_port_vlan_add(chip, port, vid, member))
1420 1421
			dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
				vid, untagged ? 'u' : 't');
1422

1423
	if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
1424 1425
		dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
			vlan->vid_end);
1426

1427
	mutex_unlock(&chip->reg_lock);
1428 1429
}

1430
static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1431
				    int port, u16 vid)
1432
{
1433
	struct mv88e6xxx_vtu_entry vlan;
1434 1435
	int i, err;

1436
	err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1437
	if (err)
1438
		return err;
1439

1440
	/* Tell switchdev if this VLAN is handled in software */
1441
	if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1442
		return -EOPNOTSUPP;
1443

1444
	vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1445 1446

	/* keep the VLAN unless all ports are excluded */
1447
	vlan.valid = false;
1448
	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1449 1450
		if (vlan.member[i] !=
		    MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1451
			vlan.valid = true;
1452 1453 1454 1455
			break;
		}
	}

1456
	err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1457 1458 1459
	if (err)
		return err;

1460
	return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
1461 1462
}

1463 1464
static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
				   const struct switchdev_obj_port_vlan *vlan)
1465
{
V
Vivien Didelot 已提交
1466
	struct mv88e6xxx_chip *chip = ds->priv;
1467 1468 1469
	u16 pvid, vid;
	int err = 0;

1470
	if (!chip->info->max_vid)
1471 1472
		return -EOPNOTSUPP;

1473
	mutex_lock(&chip->reg_lock);
1474

1475
	err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1476 1477 1478
	if (err)
		goto unlock;

1479
	for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1480
		err = _mv88e6xxx_port_vlan_del(chip, port, vid);
1481 1482 1483 1484
		if (err)
			goto unlock;

		if (vid == pvid) {
1485
			err = mv88e6xxx_port_set_pvid(chip, port, 0);
1486 1487 1488 1489 1490
			if (err)
				goto unlock;
		}
	}

1491
unlock:
1492
	mutex_unlock(&chip->reg_lock);
1493 1494 1495 1496

	return err;
}

1497 1498
static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
				  const unsigned char *addr, u16 vid)
1499
{
V
Vivien Didelot 已提交
1500
	struct mv88e6xxx_chip *chip = ds->priv;
1501
	int err;
1502

1503
	mutex_lock(&chip->reg_lock);
1504 1505
	err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
					   MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1506
	mutex_unlock(&chip->reg_lock);
1507 1508

	return err;
1509 1510
}

1511
static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1512
				  const unsigned char *addr, u16 vid)
1513
{
V
Vivien Didelot 已提交
1514
	struct mv88e6xxx_chip *chip = ds->priv;
1515
	int err;
1516

1517
	mutex_lock(&chip->reg_lock);
1518
	err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1519
					   MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
1520
	mutex_unlock(&chip->reg_lock);
1521

1522
	return err;
1523 1524
}

1525 1526
static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
				      u16 fid, u16 vid, int port,
1527
				      dsa_fdb_dump_cb_t *cb, void *data)
1528
{
1529
	struct mv88e6xxx_atu_entry addr;
1530
	bool is_static;
1531 1532
	int err;

1533
	addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1534
	eth_broadcast_addr(addr.mac);
1535 1536

	do {
1537
		mutex_lock(&chip->reg_lock);
1538
		err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
1539
		mutex_unlock(&chip->reg_lock);
1540
		if (err)
1541
			return err;
1542

1543
		if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED)
1544 1545
			break;

1546
		if (addr.trunk || (addr.portvec & BIT(port)) == 0)
1547 1548
			continue;

1549 1550
		if (!is_unicast_ether_addr(addr.mac))
			continue;
1551

1552 1553 1554
		is_static = (addr.state ==
			     MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
		err = cb(addr.mac, vid, is_static, data);
1555 1556
		if (err)
			return err;
1557 1558 1559 1560 1561
	} while (!is_broadcast_ether_addr(addr.mac));

	return err;
}

1562
static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
1563
				  dsa_fdb_dump_cb_t *cb, void *data)
1564
{
1565
	struct mv88e6xxx_vtu_entry vlan = {
1566
		.vid = chip->info->max_vid,
1567
	};
1568
	u16 fid;
1569 1570
	int err;

1571
	/* Dump port's default Filtering Information Database (VLAN ID 0) */
1572
	mutex_lock(&chip->reg_lock);
1573
	err = mv88e6xxx_port_get_fid(chip, port, &fid);
1574 1575
	mutex_unlock(&chip->reg_lock);

1576
	if (err)
1577
		return err;
1578

1579
	err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
1580
	if (err)
1581
		return err;
1582

1583
	/* Dump VLANs' Filtering Information Databases */
1584
	do {
1585
		mutex_lock(&chip->reg_lock);
1586
		err = mv88e6xxx_vtu_getnext(chip, &vlan);
1587
		mutex_unlock(&chip->reg_lock);
1588
		if (err)
1589
			return err;
1590 1591 1592 1593

		if (!vlan.valid)
			break;

1594
		err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
1595
						 cb, data);
1596
		if (err)
1597
			return err;
1598
	} while (vlan.vid < chip->info->max_vid);
1599

1600 1601 1602 1603
	return err;
}

static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
1604
				   dsa_fdb_dump_cb_t *cb, void *data)
1605
{
V
Vivien Didelot 已提交
1606
	struct mv88e6xxx_chip *chip = ds->priv;
1607

1608
	return mv88e6xxx_port_db_dump(chip, port, cb, data);
1609 1610
}

1611 1612
static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
				struct net_device *br)
1613
{
1614
	struct dsa_switch *ds;
1615
	int port;
1616
	int dev;
1617
	int err;
1618

1619 1620 1621 1622
	/* Remap the Port VLAN of each local bridge group member */
	for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
		if (chip->ds->ports[port].bridge_dev == br) {
			err = mv88e6xxx_port_vlan_map(chip, port);
1623
			if (err)
1624
				return err;
1625 1626 1627
		}
	}

1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645
	if (!mv88e6xxx_has_pvt(chip))
		return 0;

	/* Remap the Port VLAN of each cross-chip bridge group member */
	for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) {
		ds = chip->ds->dst->ds[dev];
		if (!ds)
			break;

		for (port = 0; port < ds->num_ports; ++port) {
			if (ds->ports[port].bridge_dev == br) {
				err = mv88e6xxx_pvt_map(chip, dev, port);
				if (err)
					return err;
			}
		}
	}

1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656
	return 0;
}

static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
				      struct net_device *br)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int err;

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_bridge_map(chip, br);
1657
	mutex_unlock(&chip->reg_lock);
1658

1659
	return err;
1660 1661
}

1662 1663
static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
					struct net_device *br)
1664
{
V
Vivien Didelot 已提交
1665
	struct mv88e6xxx_chip *chip = ds->priv;
1666

1667
	mutex_lock(&chip->reg_lock);
1668 1669 1670
	if (mv88e6xxx_bridge_map(chip, br) ||
	    mv88e6xxx_port_vlan_map(chip, port))
		dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
1671
	mutex_unlock(&chip->reg_lock);
1672 1673
}

1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703
static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
					   int port, struct net_device *br)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int err;

	if (!mv88e6xxx_has_pvt(chip))
		return 0;

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_pvt_map(chip, dev, port);
	mutex_unlock(&chip->reg_lock);

	return err;
}

static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
					     int port, struct net_device *br)
{
	struct mv88e6xxx_chip *chip = ds->priv;

	if (!mv88e6xxx_has_pvt(chip))
		return;

	mutex_lock(&chip->reg_lock);
	if (mv88e6xxx_pvt_map(chip, dev, port))
		dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
	mutex_unlock(&chip->reg_lock);
}

1704 1705 1706 1707 1708 1709 1710 1711
static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->reset)
		return chip->info->ops->reset(chip);

	return 0;
}

1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724
static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
{
	struct gpio_desc *gpiod = chip->reset;

	/* If there is a GPIO connected to the reset pin, toggle it */
	if (gpiod) {
		gpiod_set_value_cansleep(gpiod, 1);
		usleep_range(10000, 20000);
		gpiod_set_value_cansleep(gpiod, 0);
		usleep_range(10000, 20000);
	}
}

1725
static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
1726
{
1727
	int i, err;
1728

1729
	/* Set all ports to the Disabled state */
1730
	for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
1731
		err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
1732 1733
		if (err)
			return err;
1734 1735
	}

1736 1737 1738
	/* Wait for transmit queues to drain,
	 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
	 */
1739 1740
	usleep_range(2000, 4000);

1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751
	return 0;
}

static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
{
	int err;

	err = mv88e6xxx_disable_ports(chip);
	if (err)
		return err;

1752
	mv88e6xxx_hardware_reset(chip);
1753

1754
	return mv88e6xxx_software_reset(chip);
1755 1756
}

1757
static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
1758 1759
				   enum mv88e6xxx_frame_mode frame,
				   enum mv88e6xxx_egress_mode egress, u16 etype)
1760 1761 1762
{
	int err;

1763 1764 1765 1766
	if (!chip->info->ops->port_set_frame_mode)
		return -EOPNOTSUPP;

	err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
1767 1768 1769
	if (err)
		return err;

1770 1771 1772 1773 1774 1775 1776 1777
	err = chip->info->ops->port_set_frame_mode(chip, port, frame);
	if (err)
		return err;

	if (chip->info->ops->port_set_ether_type)
		return chip->info->ops->port_set_ether_type(chip, port, etype);

	return 0;
1778 1779
}

1780
static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
1781
{
1782
	return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
1783
				       MV88E6XXX_EGRESS_MODE_UNMODIFIED,
1784
				       MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
1785
}
1786

1787 1788 1789
static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
{
	return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
1790
				       MV88E6XXX_EGRESS_MODE_UNMODIFIED,
1791
				       MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
1792
}
1793

1794 1795 1796 1797
static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
{
	return mv88e6xxx_set_port_mode(chip, port,
				       MV88E6XXX_FRAME_MODE_ETHERTYPE,
1798 1799
				       MV88E6XXX_EGRESS_MODE_ETHERTYPE,
				       ETH_P_EDSA);
1800
}
1801

1802 1803 1804 1805
static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
{
	if (dsa_is_dsa_port(chip->ds, port))
		return mv88e6xxx_set_port_mode_dsa(chip, port);
1806

1807
	if (dsa_is_user_port(chip->ds, port))
1808
		return mv88e6xxx_set_port_mode_normal(chip, port);
1809

1810 1811 1812
	/* Setup CPU port mode depending on its supported tag format */
	if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
		return mv88e6xxx_set_port_mode_dsa(chip, port);
1813

1814 1815
	if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
		return mv88e6xxx_set_port_mode_edsa(chip, port);
1816

1817
	return -EINVAL;
1818 1819
}

1820
static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
1821
{
1822
	bool message = dsa_is_dsa_port(chip->ds, port);
1823

1824
	return mv88e6xxx_port_set_message_port(chip, port, message);
1825
}
1826

1827
static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
1828
{
1829 1830
	struct dsa_switch *ds = chip->ds;
	bool flood;
1831

1832
	/* Upstream ports flood frames with unknown unicast or multicast DA */
1833
	flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port);
1834 1835 1836
	if (chip->info->ops->port_set_egress_floods)
		return chip->info->ops->port_set_egress_floods(chip, port,
							       flood, flood);
1837

1838
	return 0;
1839 1840
}

1841 1842 1843
static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
				  bool on)
{
1844 1845
	if (chip->info->ops->serdes_power)
		return chip->info->ops->serdes_power(chip, port, on);
1846

1847
	return 0;
1848 1849
}

1850 1851 1852 1853 1854 1855
static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
{
	struct dsa_switch *ds = chip->ds;
	int upstream_port;
	int err;

1856
	upstream_port = dsa_upstream_port(ds, port);
1857 1858 1859 1860 1861 1862 1863
	if (chip->info->ops->port_set_upstream_port) {
		err = chip->info->ops->port_set_upstream_port(chip, port,
							      upstream_port);
		if (err)
			return err;
	}

1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879
	if (port == upstream_port) {
		if (chip->info->ops->set_cpu_port) {
			err = chip->info->ops->set_cpu_port(chip,
							    upstream_port);
			if (err)
				return err;
		}

		if (chip->info->ops->set_egress_port) {
			err = chip->info->ops->set_egress_port(chip,
							       upstream_port);
			if (err)
				return err;
		}
	}

1880 1881 1882
	return 0;
}

1883
static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
1884
{
1885
	struct dsa_switch *ds = chip->ds;
1886
	int err;
1887
	u16 reg;
1888

1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902
	/* MAC Forcing register: don't force link, speed, duplex or flow control
	 * state to any particular values on physical ports, but force the CPU
	 * port and all DSA ports to their maximum bandwidth and full duplex.
	 */
	if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
		err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
					       SPEED_MAX, DUPLEX_FULL,
					       PHY_INTERFACE_MODE_NA);
	else
		err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
					       SPEED_UNFORCED, DUPLEX_UNFORCED,
					       PHY_INTERFACE_MODE_NA);
	if (err)
		return err;
1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917

	/* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
	 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
	 * tunneling, determine priority by looking at 802.1p and IP
	 * priority fields (IP prio has precedence), and set STP state
	 * to Forwarding.
	 *
	 * If this is the CPU link, use DSA or EDSA tagging depending
	 * on which tagging mode was configured.
	 *
	 * If this is a link to another switch, use DSA tagging mode.
	 *
	 * If this is the upstream port for this switch, enable
	 * forwarding of unknown unicasts and multicasts.
	 */
1918 1919 1920 1921
	reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
		MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
		MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
1922 1923
	if (err)
		return err;
1924

1925
	err = mv88e6xxx_setup_port_mode(chip, port);
1926 1927
	if (err)
		return err;
1928

1929
	err = mv88e6xxx_setup_egress_floods(chip, port);
1930 1931 1932
	if (err)
		return err;

1933 1934 1935
	/* Enable the SERDES interface for DSA and CPU ports. Normal
	 * ports SERDES are enabled when the port is enabled, thus
	 * saving a bit of power.
1936
	 */
1937 1938 1939 1940 1941
	if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) {
		err = mv88e6xxx_serdes_power(chip, port, true);
		if (err)
			return err;
	}
1942

1943
	/* Port Control 2: don't force a good FCS, set the maximum frame size to
1944
	 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
1945 1946 1947
	 * untagged frames on this port, do a destination address lookup on all
	 * received packets as usual, disable ARP mirroring and don't send a
	 * copy of all transmitted/received frames on this port to the CPU.
1948
	 */
1949 1950 1951
	err = mv88e6xxx_port_set_map_da(chip, port);
	if (err)
		return err;
1952

1953 1954 1955
	err = mv88e6xxx_setup_upstream_port(chip, port);
	if (err)
		return err;
1956

1957
	err = mv88e6xxx_port_set_8021q_mode(chip, port,
1958
				MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
1959 1960 1961
	if (err)
		return err;

1962 1963
	if (chip->info->ops->port_set_jumbo_size) {
		err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
1964 1965 1966 1967
		if (err)
			return err;
	}

1968 1969 1970 1971 1972
	/* Port Association Vector: when learning source addresses
	 * of packets, add the address to the address database using
	 * a port bitmap that has only the bit for this port set and
	 * the other bits clear.
	 */
1973
	reg = 1 << port;
1974 1975
	/* Disable learning for CPU port */
	if (dsa_is_cpu_port(ds, port))
1976
		reg = 0;
1977

1978 1979
	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
				   reg);
1980 1981
	if (err)
		return err;
1982 1983

	/* Egress rate control 2: disable egress rate control. */
1984 1985
	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
				   0x0000);
1986 1987
	if (err)
		return err;
1988

1989 1990
	if (chip->info->ops->port_pause_limit) {
		err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
1991 1992
		if (err)
			return err;
1993
	}
1994

1995 1996 1997 1998 1999 2000
	if (chip->info->ops->port_disable_learn_limit) {
		err = chip->info->ops->port_disable_learn_limit(chip, port);
		if (err)
			return err;
	}

2001 2002
	if (chip->info->ops->port_disable_pri_override) {
		err = chip->info->ops->port_disable_pri_override(chip, port);
2003 2004
		if (err)
			return err;
2005
	}
2006

2007 2008
	if (chip->info->ops->port_tag_remap) {
		err = chip->info->ops->port_tag_remap(chip, port);
2009 2010
		if (err)
			return err;
2011 2012
	}

2013 2014
	if (chip->info->ops->port_egress_rate_limiting) {
		err = chip->info->ops->port_egress_rate_limiting(chip, port);
2015 2016
		if (err)
			return err;
2017 2018
	}

2019
	err = mv88e6xxx_setup_message_port(chip, port);
2020 2021
	if (err)
		return err;
2022

2023
	/* Port based VLAN map: give each port the same default address
2024 2025
	 * database, and allow bidirectional communication between the
	 * CPU and DSA port(s), and the other ports.
2026
	 */
2027
	err = mv88e6xxx_port_set_fid(chip, port, 0);
2028 2029
	if (err)
		return err;
2030

2031
	err = mv88e6xxx_port_vlan_map(chip, port);
2032 2033
	if (err)
		return err;
2034 2035 2036 2037

	/* Default VLAN ID and priority: don't set a default VLAN
	 * ID, and set the default packet priority to zero.
	 */
2038
	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
2039 2040
}

2041 2042 2043 2044
static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
				 struct phy_device *phydev)
{
	struct mv88e6xxx_chip *chip = ds->priv;
2045
	int err;
2046 2047

	mutex_lock(&chip->reg_lock);
2048
	err = mv88e6xxx_serdes_power(chip, port, true);
2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059
	mutex_unlock(&chip->reg_lock);

	return err;
}

static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port,
				   struct phy_device *phydev)
{
	struct mv88e6xxx_chip *chip = ds->priv;

	mutex_lock(&chip->reg_lock);
2060 2061
	if (mv88e6xxx_serdes_power(chip, port, false))
		dev_err(chip->dev, "failed to power off SERDES\n");
2062 2063 2064
	mutex_unlock(&chip->reg_lock);
}

2065 2066 2067
static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
				     unsigned int ageing_time)
{
V
Vivien Didelot 已提交
2068
	struct mv88e6xxx_chip *chip = ds->priv;
2069 2070 2071
	int err;

	mutex_lock(&chip->reg_lock);
2072
	err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2073 2074 2075 2076 2077
	mutex_unlock(&chip->reg_lock);

	return err;
}

2078
static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
2079
{
2080
	struct dsa_switch *ds = chip->ds;
2081
	int err;
2082

2083
	/* Disable remote management, and set the switch's DSA device number. */
2084 2085
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2,
				 MV88E6XXX_G1_CTL2_MULTIPLE_CASCADE |
2086
				 (ds->index & 0x1f));
2087 2088 2089
	if (err)
		return err;

2090
	/* Configure the IP ToS mapping registers. */
2091
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000);
2092
	if (err)
2093
		return err;
2094
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000);
2095
	if (err)
2096
		return err;
2097
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555);
2098
	if (err)
2099
		return err;
2100
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555);
2101
	if (err)
2102
		return err;
2103
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa);
2104
	if (err)
2105
		return err;
2106
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa);
2107
	if (err)
2108
		return err;
2109
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff);
2110
	if (err)
2111
		return err;
2112
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff);
2113
	if (err)
2114
		return err;
2115 2116

	/* Configure the IEEE 802.1p priority mapping register. */
2117
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41);
2118
	if (err)
2119
		return err;
2120

2121 2122 2123 2124 2125
	/* Initialize the statistics unit */
	err = mv88e6xxx_stats_set_histogram(chip);
	if (err)
		return err;

2126
	return mv88e6xxx_g1_stats_clear(chip);
2127 2128
}

2129
static int mv88e6xxx_setup(struct dsa_switch *ds)
2130
{
V
Vivien Didelot 已提交
2131
	struct mv88e6xxx_chip *chip = ds->priv;
2132
	int err;
2133 2134
	int i;

2135
	chip->ds = ds;
2136
	ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
2137

2138
	mutex_lock(&chip->reg_lock);
2139

2140
	/* Setup Switch Port Registers */
2141
	for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2142 2143 2144
		if (dsa_is_unused_port(ds, i))
			continue;

2145 2146 2147 2148 2149 2150 2151
		err = mv88e6xxx_setup_port(chip, i);
		if (err)
			goto unlock;
	}

	/* Setup Switch Global 1 Registers */
	err = mv88e6xxx_g1_setup(chip);
2152 2153 2154
	if (err)
		goto unlock;

2155
	/* Setup Switch Global 2 Registers */
2156
	if (chip->info->global2_addr) {
2157
		err = mv88e6xxx_g2_setup(chip);
2158 2159 2160
		if (err)
			goto unlock;
	}
2161

2162 2163 2164 2165
	err = mv88e6xxx_irl_setup(chip);
	if (err)
		goto unlock;

2166 2167 2168 2169
	err = mv88e6xxx_mac_setup(chip);
	if (err)
		goto unlock;

2170 2171 2172 2173
	err = mv88e6xxx_phy_setup(chip);
	if (err)
		goto unlock;

2174 2175 2176 2177
	err = mv88e6xxx_vtu_setup(chip);
	if (err)
		goto unlock;

2178 2179 2180 2181
	err = mv88e6xxx_pvt_setup(chip);
	if (err)
		goto unlock;

2182 2183 2184 2185
	err = mv88e6xxx_atu_setup(chip);
	if (err)
		goto unlock;

2186 2187 2188 2189
	err = mv88e6xxx_broadcast_setup(chip, 0);
	if (err)
		goto unlock;

2190 2191 2192 2193
	err = mv88e6xxx_pot_setup(chip);
	if (err)
		goto unlock;

2194 2195 2196
	err = mv88e6xxx_rsvd2cpu_setup(chip);
	if (err)
		goto unlock;
2197

2198
	/* Setup PTP Hardware Clock and timestamping */
2199 2200 2201 2202
	if (chip->info->ptp_support) {
		err = mv88e6xxx_ptp_setup(chip);
		if (err)
			goto unlock;
2203 2204 2205 2206

		err = mv88e6xxx_hwtstamp_setup(chip);
		if (err)
			goto unlock;
2207 2208
	}

2209
unlock:
2210
	mutex_unlock(&chip->reg_lock);
2211

2212
	return err;
2213 2214
}

2215
static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
2216
{
2217 2218
	struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
	struct mv88e6xxx_chip *chip = mdio_bus->chip;
2219 2220
	u16 val;
	int err;
2221

2222 2223 2224
	if (!chip->info->ops->phy_read)
		return -EOPNOTSUPP;

2225
	mutex_lock(&chip->reg_lock);
2226
	err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
2227
	mutex_unlock(&chip->reg_lock);
2228

2229 2230 2231 2232 2233
	if (reg == MII_PHYSID2) {
		/* Some internal PHYS don't have a model number.  Use
		 * the mv88e6390 family model number instead.
		 */
		if (!(val & 0x3f0))
2234
			val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
2235 2236
	}

2237
	return err ? err : val;
2238 2239
}

2240
static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
2241
{
2242 2243
	struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
	struct mv88e6xxx_chip *chip = mdio_bus->chip;
2244
	int err;
2245

2246 2247 2248
	if (!chip->info->ops->phy_write)
		return -EOPNOTSUPP;

2249
	mutex_lock(&chip->reg_lock);
2250
	err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
2251
	mutex_unlock(&chip->reg_lock);
2252 2253

	return err;
2254 2255
}

2256
static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
2257 2258
				   struct device_node *np,
				   bool external)
2259 2260
{
	static int index;
2261
	struct mv88e6xxx_mdio_bus *mdio_bus;
2262 2263 2264
	struct mii_bus *bus;
	int err;

2265 2266 2267 2268 2269 2270 2271 2272 2273
	if (external) {
		mutex_lock(&chip->reg_lock);
		err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
		mutex_unlock(&chip->reg_lock);

		if (err)
			return err;
	}

2274
	bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
2275 2276 2277
	if (!bus)
		return -ENOMEM;

2278
	mdio_bus = bus->priv;
2279
	mdio_bus->bus = bus;
2280
	mdio_bus->chip = chip;
2281 2282
	INIT_LIST_HEAD(&mdio_bus->list);
	mdio_bus->external = external;
2283

2284 2285
	if (np) {
		bus->name = np->full_name;
2286
		snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
2287 2288 2289 2290 2291 2292 2293
	} else {
		bus->name = "mv88e6xxx SMI";
		snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
	}

	bus->read = mv88e6xxx_mdio_read;
	bus->write = mv88e6xxx_mdio_write;
2294
	bus->parent = chip->dev;
2295

2296 2297
	if (np)
		err = of_mdiobus_register(bus, np);
2298 2299 2300
	else
		err = mdiobus_register(bus);
	if (err) {
2301
		dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
2302
		return err;
2303
	}
2304 2305 2306 2307 2308

	if (external)
		list_add_tail(&mdio_bus->list, &chip->mdios);
	else
		list_add(&mdio_bus->list, &chip->mdios);
2309 2310

	return 0;
2311
}
2312

2313 2314 2315 2316 2317
static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
	{ .compatible = "marvell,mv88e6xxx-mdio-external",
	  .data = (void *)true },
	{ },
};
2318

2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331
static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)

{
	struct mv88e6xxx_mdio_bus *mdio_bus;
	struct mii_bus *bus;

	list_for_each_entry(mdio_bus, &chip->mdios, list) {
		bus = mdio_bus->bus;

		mdiobus_unregister(bus);
	}
}

2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355
static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
				    struct device_node *np)
{
	const struct of_device_id *match;
	struct device_node *child;
	int err;

	/* Always register one mdio bus for the internal/default mdio
	 * bus. This maybe represented in the device tree, but is
	 * optional.
	 */
	child = of_get_child_by_name(np, "mdio");
	err = mv88e6xxx_mdio_register(chip, child, false);
	if (err)
		return err;

	/* Walk the device tree, and see if there are any other nodes
	 * which say they are compatible with the external mdio
	 * bus.
	 */
	for_each_available_child_of_node(np, child) {
		match = of_match_node(mv88e6xxx_mdio_external_match, child);
		if (match) {
			err = mv88e6xxx_mdio_register(chip, child, true);
2356 2357
			if (err) {
				mv88e6xxx_mdios_unregister(chip);
2358
				return err;
2359
			}
2360 2361 2362 2363
		}
	}

	return 0;
2364 2365
}

2366 2367
static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
{
V
Vivien Didelot 已提交
2368
	struct mv88e6xxx_chip *chip = ds->priv;
2369 2370 2371 2372 2373 2374 2375

	return chip->eeprom_len;
}

static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
				struct ethtool_eeprom *eeprom, u8 *data)
{
V
Vivien Didelot 已提交
2376
	struct mv88e6xxx_chip *chip = ds->priv;
2377 2378
	int err;

2379 2380
	if (!chip->info->ops->get_eeprom)
		return -EOPNOTSUPP;
2381

2382 2383
	mutex_lock(&chip->reg_lock);
	err = chip->info->ops->get_eeprom(chip, eeprom, data);
2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396
	mutex_unlock(&chip->reg_lock);

	if (err)
		return err;

	eeprom->magic = 0xc3ec4951;

	return 0;
}

static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
				struct ethtool_eeprom *eeprom, u8 *data)
{
V
Vivien Didelot 已提交
2397
	struct mv88e6xxx_chip *chip = ds->priv;
2398 2399
	int err;

2400 2401 2402
	if (!chip->info->ops->set_eeprom)
		return -EOPNOTSUPP;

2403 2404 2405 2406
	if (eeprom->magic != 0xc3ec4951)
		return -EINVAL;

	mutex_lock(&chip->reg_lock);
2407
	err = chip->info->ops->set_eeprom(chip, eeprom, data);
2408 2409 2410 2411 2412
	mutex_unlock(&chip->reg_lock);

	return err;
}

2413
static const struct mv88e6xxx_ops mv88e6085_ops = {
2414
	/* MV88E6XXX_FAMILY_6097 */
2415
	.irl_init_all = mv88e6352_g2_irl_init_all,
2416
	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2417 2418
	.phy_read = mv88e6185_phy_ppu_read,
	.phy_write = mv88e6185_phy_ppu_write,
2419
	.port_set_link = mv88e6xxx_port_set_link,
2420
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2421
	.port_set_speed = mv88e6185_port_set_speed,
2422
	.port_tag_remap = mv88e6095_port_tag_remap,
2423
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2424
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2425
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2426
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2427
	.port_pause_limit = mv88e6097_port_pause_limit,
2428
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2429
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2430
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2431
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2432 2433
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2434
	.stats_get_stats = mv88e6095_stats_get_stats,
2435 2436
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2437
	.watchdog_ops = &mv88e6097_watchdog_ops,
2438
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2439
	.pot_clear = mv88e6xxx_g2_pot_clear,
2440 2441
	.ppu_enable = mv88e6185_g1_ppu_enable,
	.ppu_disable = mv88e6185_g1_ppu_disable,
2442
	.reset = mv88e6185_g1_reset,
2443
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2444
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2445 2446 2447
};

static const struct mv88e6xxx_ops mv88e6095_ops = {
2448
	/* MV88E6XXX_FAMILY_6095 */
2449
	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2450 2451
	.phy_read = mv88e6185_phy_ppu_read,
	.phy_write = mv88e6185_phy_ppu_write,
2452
	.port_set_link = mv88e6xxx_port_set_link,
2453
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2454
	.port_set_speed = mv88e6185_port_set_speed,
2455
	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
2456
	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
2457
	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
2458
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2459
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2460 2461
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2462
	.stats_get_stats = mv88e6095_stats_get_stats,
2463
	.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2464 2465
	.ppu_enable = mv88e6185_g1_ppu_enable,
	.ppu_disable = mv88e6185_g1_ppu_disable,
2466
	.reset = mv88e6185_g1_reset,
2467
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
2468
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2469 2470
};

2471
static const struct mv88e6xxx_ops mv88e6097_ops = {
2472
	/* MV88E6XXX_FAMILY_6097 */
2473
	.irl_init_all = mv88e6352_g2_irl_init_all,
2474 2475 2476 2477 2478 2479
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_speed = mv88e6185_port_set_speed,
2480
	.port_tag_remap = mv88e6095_port_tag_remap,
2481
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2482
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2483
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2484
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2485
	.port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2486
	.port_pause_limit = mv88e6097_port_pause_limit,
2487
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2488
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2489
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2490
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2491 2492 2493
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
	.stats_get_stats = mv88e6095_stats_get_stats,
2494 2495
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2496
	.watchdog_ops = &mv88e6097_watchdog_ops,
2497
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2498
	.pot_clear = mv88e6xxx_g2_pot_clear,
2499
	.reset = mv88e6352_g1_reset,
2500
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2501
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2502 2503
};

2504
static const struct mv88e6xxx_ops mv88e6123_ops = {
2505
	/* MV88E6XXX_FAMILY_6165 */
2506
	.irl_init_all = mv88e6352_g2_irl_init_all,
2507
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2508 2509
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2510
	.port_set_link = mv88e6xxx_port_set_link,
2511
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2512
	.port_set_speed = mv88e6185_port_set_speed,
2513
	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
2514
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2515
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2516
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2517
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2518
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2519 2520
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2521
	.stats_get_stats = mv88e6095_stats_get_stats,
2522 2523
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2524
	.watchdog_ops = &mv88e6097_watchdog_ops,
2525
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2526
	.pot_clear = mv88e6xxx_g2_pot_clear,
2527
	.reset = mv88e6352_g1_reset,
2528
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2529
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2530 2531 2532
};

static const struct mv88e6xxx_ops mv88e6131_ops = {
2533
	/* MV88E6XXX_FAMILY_6185 */
2534
	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2535 2536
	.phy_read = mv88e6185_phy_ppu_read,
	.phy_write = mv88e6185_phy_ppu_write,
2537
	.port_set_link = mv88e6xxx_port_set_link,
2538
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2539
	.port_set_speed = mv88e6185_port_set_speed,
2540
	.port_tag_remap = mv88e6095_port_tag_remap,
2541
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2542
	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
2543
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2544
	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
2545
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2546
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2547
	.port_pause_limit = mv88e6097_port_pause_limit,
2548
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2549
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2550 2551
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2552
	.stats_get_stats = mv88e6095_stats_get_stats,
2553 2554
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2555
	.watchdog_ops = &mv88e6097_watchdog_ops,
2556
	.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2557 2558
	.ppu_enable = mv88e6185_g1_ppu_enable,
	.ppu_disable = mv88e6185_g1_ppu_disable,
2559
	.reset = mv88e6185_g1_reset,
2560
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
2561
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2562 2563
};

2564 2565
static const struct mv88e6xxx_ops mv88e6141_ops = {
	/* MV88E6XXX_FAMILY_6341 */
2566
	.irl_init_all = mv88e6352_g2_irl_init_all,
2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
	.port_tag_remap = mv88e6095_port_tag_remap,
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2580
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2581
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2582
	.port_pause_limit = mv88e6097_port_pause_limit,
2583 2584 2585
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
2586
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2587 2588 2589
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
	.stats_get_stats = mv88e6390_stats_get_stats,
2590 2591
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
2592 2593
	.watchdog_ops = &mv88e6390_watchdog_ops,
	.mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
2594
	.pot_clear = mv88e6xxx_g2_pot_clear,
2595
	.reset = mv88e6352_g1_reset,
2596
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2597
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2598
	.gpio_ops = &mv88e6352_gpio_ops,
2599 2600
};

2601
static const struct mv88e6xxx_ops mv88e6161_ops = {
2602
	/* MV88E6XXX_FAMILY_6165 */
2603
	.irl_init_all = mv88e6352_g2_irl_init_all,
2604
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2605 2606
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2607
	.port_set_link = mv88e6xxx_port_set_link,
2608
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2609
	.port_set_speed = mv88e6185_port_set_speed,
2610
	.port_tag_remap = mv88e6095_port_tag_remap,
2611
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2612
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2613
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2614
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2615
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2616
	.port_pause_limit = mv88e6097_port_pause_limit,
2617
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2618
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2619
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2620
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2621 2622
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2623
	.stats_get_stats = mv88e6095_stats_get_stats,
2624 2625
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2626
	.watchdog_ops = &mv88e6097_watchdog_ops,
2627
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2628
	.pot_clear = mv88e6xxx_g2_pot_clear,
2629
	.reset = mv88e6352_g1_reset,
2630
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2631
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2632 2633 2634
};

static const struct mv88e6xxx_ops mv88e6165_ops = {
2635
	/* MV88E6XXX_FAMILY_6165 */
2636
	.irl_init_all = mv88e6352_g2_irl_init_all,
2637
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2638 2639
	.phy_read = mv88e6165_phy_read,
	.phy_write = mv88e6165_phy_write,
2640
	.port_set_link = mv88e6xxx_port_set_link,
2641
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2642
	.port_set_speed = mv88e6185_port_set_speed,
2643
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2644
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2645
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2646
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2647 2648
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2649
	.stats_get_stats = mv88e6095_stats_get_stats,
2650 2651
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2652
	.watchdog_ops = &mv88e6097_watchdog_ops,
2653
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2654
	.pot_clear = mv88e6xxx_g2_pot_clear,
2655
	.reset = mv88e6352_g1_reset,
2656
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2657
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2658 2659 2660
};

static const struct mv88e6xxx_ops mv88e6171_ops = {
2661
	/* MV88E6XXX_FAMILY_6351 */
2662
	.irl_init_all = mv88e6352_g2_irl_init_all,
2663
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2664 2665
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2666
	.port_set_link = mv88e6xxx_port_set_link,
2667
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2668
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2669
	.port_set_speed = mv88e6185_port_set_speed,
2670
	.port_tag_remap = mv88e6095_port_tag_remap,
2671
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2672
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2673
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2674
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2675
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2676
	.port_pause_limit = mv88e6097_port_pause_limit,
2677
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2678
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2679
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2680
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2681 2682
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2683
	.stats_get_stats = mv88e6095_stats_get_stats,
2684 2685
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2686
	.watchdog_ops = &mv88e6097_watchdog_ops,
2687
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2688
	.pot_clear = mv88e6xxx_g2_pot_clear,
2689
	.reset = mv88e6352_g1_reset,
2690
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2691
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2692 2693 2694
};

static const struct mv88e6xxx_ops mv88e6172_ops = {
2695
	/* MV88E6XXX_FAMILY_6352 */
2696
	.irl_init_all = mv88e6352_g2_irl_init_all,
2697 2698
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
2699
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2700 2701
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2702
	.port_set_link = mv88e6xxx_port_set_link,
2703
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2704
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2705
	.port_set_speed = mv88e6352_port_set_speed,
2706
	.port_tag_remap = mv88e6095_port_tag_remap,
2707
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2708
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2709
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2710
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2711
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2712
	.port_pause_limit = mv88e6097_port_pause_limit,
2713
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2714
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2715
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2716
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2717 2718
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2719
	.stats_get_stats = mv88e6095_stats_get_stats,
2720 2721
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2722
	.watchdog_ops = &mv88e6097_watchdog_ops,
2723
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2724
	.pot_clear = mv88e6xxx_g2_pot_clear,
2725
	.reset = mv88e6352_g1_reset,
2726
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2727
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2728
	.serdes_power = mv88e6352_serdes_power,
2729
	.gpio_ops = &mv88e6352_gpio_ops,
2730 2731 2732
};

static const struct mv88e6xxx_ops mv88e6175_ops = {
2733
	/* MV88E6XXX_FAMILY_6351 */
2734
	.irl_init_all = mv88e6352_g2_irl_init_all,
2735
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2736 2737
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2738
	.port_set_link = mv88e6xxx_port_set_link,
2739
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2740
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2741
	.port_set_speed = mv88e6185_port_set_speed,
2742
	.port_tag_remap = mv88e6095_port_tag_remap,
2743
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2744
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2745
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2746
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2747
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2748
	.port_pause_limit = mv88e6097_port_pause_limit,
2749
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2750
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2751
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2752
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2753 2754
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2755
	.stats_get_stats = mv88e6095_stats_get_stats,
2756 2757
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2758
	.watchdog_ops = &mv88e6097_watchdog_ops,
2759
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2760
	.pot_clear = mv88e6xxx_g2_pot_clear,
2761
	.reset = mv88e6352_g1_reset,
2762
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2763
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2764 2765 2766
};

static const struct mv88e6xxx_ops mv88e6176_ops = {
2767
	/* MV88E6XXX_FAMILY_6352 */
2768
	.irl_init_all = mv88e6352_g2_irl_init_all,
2769 2770
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
2771
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2772 2773
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2774
	.port_set_link = mv88e6xxx_port_set_link,
2775
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2776
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2777
	.port_set_speed = mv88e6352_port_set_speed,
2778
	.port_tag_remap = mv88e6095_port_tag_remap,
2779
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2780
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2781
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2782
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2783
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2784
	.port_pause_limit = mv88e6097_port_pause_limit,
2785
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2786
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2787
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2788
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2789 2790
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2791
	.stats_get_stats = mv88e6095_stats_get_stats,
2792 2793
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2794
	.watchdog_ops = &mv88e6097_watchdog_ops,
2795
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2796
	.pot_clear = mv88e6xxx_g2_pot_clear,
2797
	.reset = mv88e6352_g1_reset,
2798
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2799
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2800
	.serdes_power = mv88e6352_serdes_power,
2801
	.gpio_ops = &mv88e6352_gpio_ops,
2802 2803 2804
};

static const struct mv88e6xxx_ops mv88e6185_ops = {
2805
	/* MV88E6XXX_FAMILY_6185 */
2806
	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2807 2808
	.phy_read = mv88e6185_phy_ppu_read,
	.phy_write = mv88e6185_phy_ppu_write,
2809
	.port_set_link = mv88e6xxx_port_set_link,
2810
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2811
	.port_set_speed = mv88e6185_port_set_speed,
2812
	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
2813
	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
2814
	.port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2815
	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
2816
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2817
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2818 2819
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2820
	.stats_get_stats = mv88e6095_stats_get_stats,
2821 2822
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2823
	.watchdog_ops = &mv88e6097_watchdog_ops,
2824
	.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2825 2826
	.ppu_enable = mv88e6185_g1_ppu_enable,
	.ppu_disable = mv88e6185_g1_ppu_disable,
2827
	.reset = mv88e6185_g1_reset,
2828
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
2829
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2830 2831
};

2832
static const struct mv88e6xxx_ops mv88e6190_ops = {
2833
	/* MV88E6XXX_FAMILY_6390 */
2834
	.irl_init_all = mv88e6390_g2_irl_init_all,
2835 2836
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
2837 2838 2839 2840 2841 2842 2843
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
2844
	.port_tag_remap = mv88e6390_port_tag_remap,
2845
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2846
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2847
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2848
	.port_pause_limit = mv88e6390_port_pause_limit,
2849
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2850
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2851
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
2852
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2853 2854
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
2855
	.stats_get_stats = mv88e6390_stats_get_stats,
2856 2857
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
2858
	.watchdog_ops = &mv88e6390_watchdog_ops,
2859
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2860
	.pot_clear = mv88e6xxx_g2_pot_clear,
2861
	.reset = mv88e6352_g1_reset,
2862 2863
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2864
	.serdes_power = mv88e6390_serdes_power,
2865
	.gpio_ops = &mv88e6352_gpio_ops,
2866 2867 2868
};

static const struct mv88e6xxx_ops mv88e6190x_ops = {
2869
	/* MV88E6XXX_FAMILY_6390 */
2870
	.irl_init_all = mv88e6390_g2_irl_init_all,
2871 2872
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
2873 2874 2875 2876 2877 2878 2879
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390x_port_set_speed,
2880
	.port_tag_remap = mv88e6390_port_tag_remap,
2881
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2882
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2883
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2884
	.port_pause_limit = mv88e6390_port_pause_limit,
2885
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2886
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2887
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
2888
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2889 2890
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
2891
	.stats_get_stats = mv88e6390_stats_get_stats,
2892 2893
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
2894
	.watchdog_ops = &mv88e6390_watchdog_ops,
2895
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2896
	.pot_clear = mv88e6xxx_g2_pot_clear,
2897
	.reset = mv88e6352_g1_reset,
2898 2899
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2900
	.serdes_power = mv88e6390_serdes_power,
2901
	.gpio_ops = &mv88e6352_gpio_ops,
2902 2903 2904
};

static const struct mv88e6xxx_ops mv88e6191_ops = {
2905
	/* MV88E6XXX_FAMILY_6390 */
2906
	.irl_init_all = mv88e6390_g2_irl_init_all,
2907 2908
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
2909 2910 2911 2912 2913 2914 2915
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
2916
	.port_tag_remap = mv88e6390_port_tag_remap,
2917
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2918
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2919
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2920
	.port_pause_limit = mv88e6390_port_pause_limit,
2921
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2922
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2923
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
2924
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2925 2926
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
2927
	.stats_get_stats = mv88e6390_stats_get_stats,
2928 2929
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
2930
	.watchdog_ops = &mv88e6390_watchdog_ops,
2931
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2932
	.pot_clear = mv88e6xxx_g2_pot_clear,
2933
	.reset = mv88e6352_g1_reset,
2934 2935
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2936
	.serdes_power = mv88e6390_serdes_power,
2937 2938
};

2939
static const struct mv88e6xxx_ops mv88e6240_ops = {
2940
	/* MV88E6XXX_FAMILY_6352 */
2941
	.irl_init_all = mv88e6352_g2_irl_init_all,
2942 2943
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
2944
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2945 2946
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2947
	.port_set_link = mv88e6xxx_port_set_link,
2948
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2949
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2950
	.port_set_speed = mv88e6352_port_set_speed,
2951
	.port_tag_remap = mv88e6095_port_tag_remap,
2952
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2953
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2954
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2955
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2956
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2957
	.port_pause_limit = mv88e6097_port_pause_limit,
2958
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2959
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2960
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2961
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2962 2963
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2964
	.stats_get_stats = mv88e6095_stats_get_stats,
2965 2966
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2967
	.watchdog_ops = &mv88e6097_watchdog_ops,
2968
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2969
	.pot_clear = mv88e6xxx_g2_pot_clear,
2970
	.reset = mv88e6352_g1_reset,
2971
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2972
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2973
	.serdes_power = mv88e6352_serdes_power,
2974
	.gpio_ops = &mv88e6352_gpio_ops,
2975
	.avb_ops = &mv88e6352_avb_ops,
2976 2977
};

2978
static const struct mv88e6xxx_ops mv88e6290_ops = {
2979
	/* MV88E6XXX_FAMILY_6390 */
2980
	.irl_init_all = mv88e6390_g2_irl_init_all,
2981 2982
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
2983 2984 2985 2986 2987 2988 2989
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
2990
	.port_tag_remap = mv88e6390_port_tag_remap,
2991
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2992
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2993
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2994
	.port_pause_limit = mv88e6390_port_pause_limit,
2995
	.port_set_cmode = mv88e6390x_port_set_cmode,
2996
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2997
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2998
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
2999
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3000 3001
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3002
	.stats_get_stats = mv88e6390_stats_get_stats,
3003 3004
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3005
	.watchdog_ops = &mv88e6390_watchdog_ops,
3006
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3007
	.pot_clear = mv88e6xxx_g2_pot_clear,
3008
	.reset = mv88e6352_g1_reset,
3009 3010
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3011
	.serdes_power = mv88e6390_serdes_power,
3012
	.gpio_ops = &mv88e6352_gpio_ops,
3013
	.avb_ops = &mv88e6390_avb_ops,
3014 3015
};

3016
static const struct mv88e6xxx_ops mv88e6320_ops = {
3017
	/* MV88E6XXX_FAMILY_6320 */
3018
	.irl_init_all = mv88e6352_g2_irl_init_all,
3019 3020
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
3021
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3022 3023
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3024
	.port_set_link = mv88e6xxx_port_set_link,
3025
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3026
	.port_set_speed = mv88e6185_port_set_speed,
3027
	.port_tag_remap = mv88e6095_port_tag_remap,
3028
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3029
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3030
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3031
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3032
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3033
	.port_pause_limit = mv88e6097_port_pause_limit,
3034
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3035
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3036
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3037
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3038 3039
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3040
	.stats_get_stats = mv88e6320_stats_get_stats,
3041 3042
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3043
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3044
	.pot_clear = mv88e6xxx_g2_pot_clear,
3045
	.reset = mv88e6352_g1_reset,
3046
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
3047
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3048
	.gpio_ops = &mv88e6352_gpio_ops,
3049
	.avb_ops = &mv88e6352_avb_ops,
3050 3051 3052
};

static const struct mv88e6xxx_ops mv88e6321_ops = {
3053
	/* MV88E6XXX_FAMILY_6320 */
3054
	.irl_init_all = mv88e6352_g2_irl_init_all,
3055 3056
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
3057
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3058 3059
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3060
	.port_set_link = mv88e6xxx_port_set_link,
3061
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3062
	.port_set_speed = mv88e6185_port_set_speed,
3063
	.port_tag_remap = mv88e6095_port_tag_remap,
3064
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3065
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3066
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3067
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3068
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3069
	.port_pause_limit = mv88e6097_port_pause_limit,
3070
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3071
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3072
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3073
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3074 3075
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3076
	.stats_get_stats = mv88e6320_stats_get_stats,
3077 3078
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3079
	.reset = mv88e6352_g1_reset,
3080
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
3081
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3082
	.gpio_ops = &mv88e6352_gpio_ops,
3083
	.avb_ops = &mv88e6352_avb_ops,
3084 3085
};

3086 3087
static const struct mv88e6xxx_ops mv88e6341_ops = {
	/* MV88E6XXX_FAMILY_6341 */
3088
	.irl_init_all = mv88e6352_g2_irl_init_all,
3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099 3100 3101
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
	.port_tag_remap = mv88e6095_port_tag_remap,
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3102
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3103
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3104
	.port_pause_limit = mv88e6097_port_pause_limit,
3105 3106 3107
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3108
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3109 3110 3111
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
	.stats_get_stats = mv88e6390_stats_get_stats,
3112 3113
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3114 3115
	.watchdog_ops = &mv88e6390_watchdog_ops,
	.mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
3116
	.pot_clear = mv88e6xxx_g2_pot_clear,
3117
	.reset = mv88e6352_g1_reset,
3118
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3119
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3120
	.gpio_ops = &mv88e6352_gpio_ops,
3121
	.avb_ops = &mv88e6390_avb_ops,
3122 3123
};

3124
static const struct mv88e6xxx_ops mv88e6350_ops = {
3125
	/* MV88E6XXX_FAMILY_6351 */
3126
	.irl_init_all = mv88e6352_g2_irl_init_all,
3127
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3128 3129
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3130
	.port_set_link = mv88e6xxx_port_set_link,
3131
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3132
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3133
	.port_set_speed = mv88e6185_port_set_speed,
3134
	.port_tag_remap = mv88e6095_port_tag_remap,
3135
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3136
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3137
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3138
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3139
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3140
	.port_pause_limit = mv88e6097_port_pause_limit,
3141
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3142
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3143
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3144
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3145 3146
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
3147
	.stats_get_stats = mv88e6095_stats_get_stats,
3148 3149
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3150
	.watchdog_ops = &mv88e6097_watchdog_ops,
3151
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3152
	.pot_clear = mv88e6xxx_g2_pot_clear,
3153
	.reset = mv88e6352_g1_reset,
3154
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3155
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3156 3157 3158
};

static const struct mv88e6xxx_ops mv88e6351_ops = {
3159
	/* MV88E6XXX_FAMILY_6351 */
3160
	.irl_init_all = mv88e6352_g2_irl_init_all,
3161
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3162 3163
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3164
	.port_set_link = mv88e6xxx_port_set_link,
3165
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3166
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3167
	.port_set_speed = mv88e6185_port_set_speed,
3168
	.port_tag_remap = mv88e6095_port_tag_remap,
3169
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3170
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3171
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3172
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3173
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3174
	.port_pause_limit = mv88e6097_port_pause_limit,
3175
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3176
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3177
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3178
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3179 3180
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
3181
	.stats_get_stats = mv88e6095_stats_get_stats,
3182 3183
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3184
	.watchdog_ops = &mv88e6097_watchdog_ops,
3185
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3186
	.pot_clear = mv88e6xxx_g2_pot_clear,
3187
	.reset = mv88e6352_g1_reset,
3188
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3189
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3190
	.avb_ops = &mv88e6352_avb_ops,
3191 3192 3193
};

static const struct mv88e6xxx_ops mv88e6352_ops = {
3194
	/* MV88E6XXX_FAMILY_6352 */
3195
	.irl_init_all = mv88e6352_g2_irl_init_all,
3196 3197
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
3198
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3199 3200
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3201
	.port_set_link = mv88e6xxx_port_set_link,
3202
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3203
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3204
	.port_set_speed = mv88e6352_port_set_speed,
3205
	.port_tag_remap = mv88e6095_port_tag_remap,
3206
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3207
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3208
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3209
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3210
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3211
	.port_pause_limit = mv88e6097_port_pause_limit,
3212
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3213
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3214
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3215
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3216 3217
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
3218
	.stats_get_stats = mv88e6095_stats_get_stats,
3219 3220
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3221
	.watchdog_ops = &mv88e6097_watchdog_ops,
3222
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3223
	.pot_clear = mv88e6xxx_g2_pot_clear,
3224
	.reset = mv88e6352_g1_reset,
3225
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3226
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3227
	.serdes_power = mv88e6352_serdes_power,
3228
	.gpio_ops = &mv88e6352_gpio_ops,
3229
	.avb_ops = &mv88e6352_avb_ops,
3230 3231 3232
	.serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
	.serdes_get_strings = mv88e6352_serdes_get_strings,
	.serdes_get_stats = mv88e6352_serdes_get_stats,
3233 3234
};

3235
static const struct mv88e6xxx_ops mv88e6390_ops = {
3236
	/* MV88E6XXX_FAMILY_6390 */
3237
	.irl_init_all = mv88e6390_g2_irl_init_all,
3238 3239
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3240 3241 3242 3243 3244 3245 3246
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
3247
	.port_tag_remap = mv88e6390_port_tag_remap,
3248
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3249
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3250
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3251
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3252
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3253
	.port_pause_limit = mv88e6390_port_pause_limit,
3254
	.port_set_cmode = mv88e6390x_port_set_cmode,
3255
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3256
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3257
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3258
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3259 3260
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3261
	.stats_get_stats = mv88e6390_stats_get_stats,
3262 3263
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3264
	.watchdog_ops = &mv88e6390_watchdog_ops,
3265
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3266
	.pot_clear = mv88e6xxx_g2_pot_clear,
3267
	.reset = mv88e6352_g1_reset,
3268 3269
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3270
	.serdes_power = mv88e6390_serdes_power,
3271
	.gpio_ops = &mv88e6352_gpio_ops,
3272
	.avb_ops = &mv88e6390_avb_ops,
3273 3274 3275
};

static const struct mv88e6xxx_ops mv88e6390x_ops = {
3276
	/* MV88E6XXX_FAMILY_6390 */
3277
	.irl_init_all = mv88e6390_g2_irl_init_all,
3278 3279
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3280 3281 3282 3283 3284 3285 3286
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390x_port_set_speed,
3287
	.port_tag_remap = mv88e6390_port_tag_remap,
3288
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3289
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3290
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3291
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3292
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3293
	.port_pause_limit = mv88e6390_port_pause_limit,
3294
	.port_set_cmode = mv88e6390x_port_set_cmode,
3295
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3296
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3297
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3298
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3299 3300
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3301
	.stats_get_stats = mv88e6390_stats_get_stats,
3302 3303
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3304
	.watchdog_ops = &mv88e6390_watchdog_ops,
3305
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3306
	.pot_clear = mv88e6xxx_g2_pot_clear,
3307
	.reset = mv88e6352_g1_reset,
3308 3309
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3310
	.serdes_power = mv88e6390_serdes_power,
3311
	.gpio_ops = &mv88e6352_gpio_ops,
3312
	.avb_ops = &mv88e6390_avb_ops,
3313 3314
};

3315 3316
static const struct mv88e6xxx_info mv88e6xxx_table[] = {
	[MV88E6085] = {
3317
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
3318 3319 3320 3321
		.family = MV88E6XXX_FAMILY_6097,
		.name = "Marvell 88E6085",
		.num_databases = 4096,
		.num_ports = 10,
3322
		.num_internal_phys = 5,
3323
		.max_vid = 4095,
3324
		.port_base_addr = 0x10,
3325
		.global1_addr = 0x1b,
3326
		.global2_addr = 0x1c,
3327
		.age_time_coeff = 15000,
3328
		.g1_irqs = 8,
3329
		.g2_irqs = 10,
3330
		.atu_move_port_mask = 0xf,
3331
		.pvt = true,
3332
		.multi_chip = true,
3333
		.tag_protocol = DSA_TAG_PROTO_DSA,
3334
		.ops = &mv88e6085_ops,
3335 3336 3337
	},

	[MV88E6095] = {
3338
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
3339 3340 3341 3342
		.family = MV88E6XXX_FAMILY_6095,
		.name = "Marvell 88E6095/88E6095F",
		.num_databases = 256,
		.num_ports = 11,
3343
		.num_internal_phys = 0,
3344
		.max_vid = 4095,
3345
		.port_base_addr = 0x10,
3346
		.global1_addr = 0x1b,
3347
		.global2_addr = 0x1c,
3348
		.age_time_coeff = 15000,
3349
		.g1_irqs = 8,
3350
		.atu_move_port_mask = 0xf,
3351
		.multi_chip = true,
3352
		.tag_protocol = DSA_TAG_PROTO_DSA,
3353
		.ops = &mv88e6095_ops,
3354 3355
	},

3356
	[MV88E6097] = {
3357
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
3358 3359 3360 3361
		.family = MV88E6XXX_FAMILY_6097,
		.name = "Marvell 88E6097/88E6097F",
		.num_databases = 4096,
		.num_ports = 11,
3362
		.num_internal_phys = 8,
3363
		.max_vid = 4095,
3364 3365
		.port_base_addr = 0x10,
		.global1_addr = 0x1b,
3366
		.global2_addr = 0x1c,
3367
		.age_time_coeff = 15000,
3368
		.g1_irqs = 8,
3369
		.g2_irqs = 10,
3370
		.atu_move_port_mask = 0xf,
3371
		.pvt = true,
3372
		.multi_chip = true,
3373
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3374 3375 3376
		.ops = &mv88e6097_ops,
	},

3377
	[MV88E6123] = {
3378
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
3379 3380 3381 3382
		.family = MV88E6XXX_FAMILY_6165,
		.name = "Marvell 88E6123",
		.num_databases = 4096,
		.num_ports = 3,
3383
		.num_internal_phys = 5,
3384
		.max_vid = 4095,
3385
		.port_base_addr = 0x10,
3386
		.global1_addr = 0x1b,
3387
		.global2_addr = 0x1c,
3388
		.age_time_coeff = 15000,
3389
		.g1_irqs = 9,
3390
		.g2_irqs = 10,
3391
		.atu_move_port_mask = 0xf,
3392
		.pvt = true,
3393
		.multi_chip = true,
3394
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3395
		.ops = &mv88e6123_ops,
3396 3397 3398
	},

	[MV88E6131] = {
3399
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
3400 3401 3402 3403
		.family = MV88E6XXX_FAMILY_6185,
		.name = "Marvell 88E6131",
		.num_databases = 256,
		.num_ports = 8,
3404
		.num_internal_phys = 0,
3405
		.max_vid = 4095,
3406
		.port_base_addr = 0x10,
3407
		.global1_addr = 0x1b,
3408
		.global2_addr = 0x1c,
3409
		.age_time_coeff = 15000,
3410
		.g1_irqs = 9,
3411
		.atu_move_port_mask = 0xf,
3412
		.multi_chip = true,
3413
		.tag_protocol = DSA_TAG_PROTO_DSA,
3414
		.ops = &mv88e6131_ops,
3415 3416
	},

3417
	[MV88E6141] = {
3418
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
3419 3420 3421 3422
		.family = MV88E6XXX_FAMILY_6341,
		.name = "Marvell 88E6341",
		.num_databases = 4096,
		.num_ports = 6,
3423
		.num_internal_phys = 5,
3424
		.num_gpio = 11,
3425
		.max_vid = 4095,
3426 3427
		.port_base_addr = 0x10,
		.global1_addr = 0x1b,
3428
		.global2_addr = 0x1c,
3429 3430
		.age_time_coeff = 3750,
		.atu_move_port_mask = 0x1f,
3431
		.g1_irqs = 9,
3432
		.g2_irqs = 10,
3433
		.pvt = true,
3434
		.multi_chip = true,
3435 3436 3437 3438
		.tag_protocol = DSA_TAG_PROTO_EDSA,
		.ops = &mv88e6141_ops,
	},

3439
	[MV88E6161] = {
3440
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
3441 3442 3443 3444
		.family = MV88E6XXX_FAMILY_6165,
		.name = "Marvell 88E6161",
		.num_databases = 4096,
		.num_ports = 6,
3445
		.num_internal_phys = 5,
3446
		.max_vid = 4095,
3447
		.port_base_addr = 0x10,
3448
		.global1_addr = 0x1b,
3449
		.global2_addr = 0x1c,
3450
		.age_time_coeff = 15000,
3451
		.g1_irqs = 9,
3452
		.g2_irqs = 10,
3453
		.atu_move_port_mask = 0xf,
3454
		.pvt = true,
3455
		.multi_chip = true,
3456
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3457
		.ops = &mv88e6161_ops,
3458 3459 3460
	},

	[MV88E6165] = {
3461
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
3462 3463 3464 3465
		.family = MV88E6XXX_FAMILY_6165,
		.name = "Marvell 88E6165",
		.num_databases = 4096,
		.num_ports = 6,
3466
		.num_internal_phys = 0,
3467
		.max_vid = 4095,
3468
		.port_base_addr = 0x10,
3469
		.global1_addr = 0x1b,
3470
		.global2_addr = 0x1c,
3471
		.age_time_coeff = 15000,
3472
		.g1_irqs = 9,
3473
		.g2_irqs = 10,
3474
		.atu_move_port_mask = 0xf,
3475
		.pvt = true,
3476
		.multi_chip = true,
3477
		.tag_protocol = DSA_TAG_PROTO_DSA,
3478
		.ops = &mv88e6165_ops,
3479 3480 3481
	},

	[MV88E6171] = {
3482
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
3483 3484 3485 3486
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6171",
		.num_databases = 4096,
		.num_ports = 7,
3487
		.num_internal_phys = 5,
3488
		.max_vid = 4095,
3489
		.port_base_addr = 0x10,
3490
		.global1_addr = 0x1b,
3491
		.global2_addr = 0x1c,
3492
		.age_time_coeff = 15000,
3493
		.g1_irqs = 9,
3494
		.g2_irqs = 10,
3495
		.atu_move_port_mask = 0xf,
3496
		.pvt = true,
3497
		.multi_chip = true,
3498
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3499
		.ops = &mv88e6171_ops,
3500 3501 3502
	},

	[MV88E6172] = {
3503
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
3504 3505 3506 3507
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6172",
		.num_databases = 4096,
		.num_ports = 7,
3508
		.num_internal_phys = 5,
3509
		.num_gpio = 15,
3510
		.max_vid = 4095,
3511
		.port_base_addr = 0x10,
3512
		.global1_addr = 0x1b,
3513
		.global2_addr = 0x1c,
3514
		.age_time_coeff = 15000,
3515
		.g1_irqs = 9,
3516
		.g2_irqs = 10,
3517
		.atu_move_port_mask = 0xf,
3518
		.pvt = true,
3519
		.multi_chip = true,
3520
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3521
		.ops = &mv88e6172_ops,
3522 3523 3524
	},

	[MV88E6175] = {
3525
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
3526 3527 3528 3529
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6175",
		.num_databases = 4096,
		.num_ports = 7,
3530
		.num_internal_phys = 5,
3531
		.max_vid = 4095,
3532
		.port_base_addr = 0x10,
3533
		.global1_addr = 0x1b,
3534
		.global2_addr = 0x1c,
3535
		.age_time_coeff = 15000,
3536
		.g1_irqs = 9,
3537
		.g2_irqs = 10,
3538
		.atu_move_port_mask = 0xf,
3539
		.pvt = true,
3540
		.multi_chip = true,
3541
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3542
		.ops = &mv88e6175_ops,
3543 3544 3545
	},

	[MV88E6176] = {
3546
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
3547 3548 3549 3550
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6176",
		.num_databases = 4096,
		.num_ports = 7,
3551
		.num_internal_phys = 5,
3552
		.num_gpio = 15,
3553
		.max_vid = 4095,
3554
		.port_base_addr = 0x10,
3555
		.global1_addr = 0x1b,
3556
		.global2_addr = 0x1c,
3557
		.age_time_coeff = 15000,
3558
		.g1_irqs = 9,
3559
		.g2_irqs = 10,
3560
		.atu_move_port_mask = 0xf,
3561
		.pvt = true,
3562
		.multi_chip = true,
3563
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3564
		.ops = &mv88e6176_ops,
3565 3566 3567
	},

	[MV88E6185] = {
3568
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
3569 3570 3571 3572
		.family = MV88E6XXX_FAMILY_6185,
		.name = "Marvell 88E6185",
		.num_databases = 256,
		.num_ports = 10,
3573
		.num_internal_phys = 0,
3574
		.max_vid = 4095,
3575
		.port_base_addr = 0x10,
3576
		.global1_addr = 0x1b,
3577
		.global2_addr = 0x1c,
3578
		.age_time_coeff = 15000,
3579
		.g1_irqs = 8,
3580
		.atu_move_port_mask = 0xf,
3581
		.multi_chip = true,
3582
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3583
		.ops = &mv88e6185_ops,
3584 3585
	},

3586
	[MV88E6190] = {
3587
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
3588 3589 3590 3591
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6190",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3592
		.num_internal_phys = 11,
3593
		.num_gpio = 16,
3594
		.max_vid = 8191,
3595 3596
		.port_base_addr = 0x0,
		.global1_addr = 0x1b,
3597
		.global2_addr = 0x1c,
3598
		.tag_protocol = DSA_TAG_PROTO_DSA,
3599
		.age_time_coeff = 3750,
3600
		.g1_irqs = 9,
3601
		.g2_irqs = 14,
3602
		.pvt = true,
3603
		.multi_chip = true,
3604
		.atu_move_port_mask = 0x1f,
3605 3606 3607 3608
		.ops = &mv88e6190_ops,
	},

	[MV88E6190X] = {
3609
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
3610 3611 3612 3613
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6190X",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3614
		.num_internal_phys = 11,
3615
		.num_gpio = 16,
3616
		.max_vid = 8191,
3617 3618
		.port_base_addr = 0x0,
		.global1_addr = 0x1b,
3619
		.global2_addr = 0x1c,
3620
		.age_time_coeff = 3750,
3621
		.g1_irqs = 9,
3622
		.g2_irqs = 14,
3623
		.atu_move_port_mask = 0x1f,
3624
		.pvt = true,
3625
		.multi_chip = true,
3626
		.tag_protocol = DSA_TAG_PROTO_DSA,
3627 3628 3629 3630
		.ops = &mv88e6190x_ops,
	},

	[MV88E6191] = {
3631
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
3632 3633 3634 3635
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6191",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3636
		.num_internal_phys = 11,
3637
		.max_vid = 8191,
3638 3639
		.port_base_addr = 0x0,
		.global1_addr = 0x1b,
3640
		.global2_addr = 0x1c,
3641
		.age_time_coeff = 3750,
3642
		.g1_irqs = 9,
3643
		.g2_irqs = 14,
3644
		.atu_move_port_mask = 0x1f,
3645
		.pvt = true,
3646
		.multi_chip = true,
3647
		.tag_protocol = DSA_TAG_PROTO_DSA,
3648
		.ptp_support = true,
3649
		.ops = &mv88e6191_ops,
3650 3651
	},

3652
	[MV88E6240] = {
3653
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
3654 3655 3656 3657
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6240",
		.num_databases = 4096,
		.num_ports = 7,
3658
		.num_internal_phys = 5,
3659
		.num_gpio = 15,
3660
		.max_vid = 4095,
3661
		.port_base_addr = 0x10,
3662
		.global1_addr = 0x1b,
3663
		.global2_addr = 0x1c,
3664
		.age_time_coeff = 15000,
3665
		.g1_irqs = 9,
3666
		.g2_irqs = 10,
3667
		.atu_move_port_mask = 0xf,
3668
		.pvt = true,
3669
		.multi_chip = true,
3670
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3671
		.ptp_support = true,
3672
		.ops = &mv88e6240_ops,
3673 3674
	},

3675
	[MV88E6290] = {
3676
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
3677 3678 3679 3680
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6290",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3681
		.num_internal_phys = 11,
3682
		.num_gpio = 16,
3683
		.max_vid = 8191,
3684 3685
		.port_base_addr = 0x0,
		.global1_addr = 0x1b,
3686
		.global2_addr = 0x1c,
3687
		.age_time_coeff = 3750,
3688
		.g1_irqs = 9,
3689
		.g2_irqs = 14,
3690
		.atu_move_port_mask = 0x1f,
3691
		.pvt = true,
3692
		.multi_chip = true,
3693
		.tag_protocol = DSA_TAG_PROTO_DSA,
3694
		.ptp_support = true,
3695 3696 3697
		.ops = &mv88e6290_ops,
	},

3698
	[MV88E6320] = {
3699
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
3700 3701 3702 3703
		.family = MV88E6XXX_FAMILY_6320,
		.name = "Marvell 88E6320",
		.num_databases = 4096,
		.num_ports = 7,
3704
		.num_internal_phys = 5,
3705
		.num_gpio = 15,
3706
		.max_vid = 4095,
3707
		.port_base_addr = 0x10,
3708
		.global1_addr = 0x1b,
3709
		.global2_addr = 0x1c,
3710
		.age_time_coeff = 15000,
3711
		.g1_irqs = 8,
3712
		.g2_irqs = 10,
3713
		.atu_move_port_mask = 0xf,
3714
		.pvt = true,
3715
		.multi_chip = true,
3716
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3717
		.ptp_support = true,
3718
		.ops = &mv88e6320_ops,
3719 3720 3721
	},

	[MV88E6321] = {
3722
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
3723 3724 3725 3726
		.family = MV88E6XXX_FAMILY_6320,
		.name = "Marvell 88E6321",
		.num_databases = 4096,
		.num_ports = 7,
3727
		.num_internal_phys = 5,
3728
		.num_gpio = 15,
3729
		.max_vid = 4095,
3730
		.port_base_addr = 0x10,
3731
		.global1_addr = 0x1b,
3732
		.global2_addr = 0x1c,
3733
		.age_time_coeff = 15000,
3734
		.g1_irqs = 8,
3735
		.g2_irqs = 10,
3736
		.atu_move_port_mask = 0xf,
3737
		.multi_chip = true,
3738
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3739
		.ptp_support = true,
3740
		.ops = &mv88e6321_ops,
3741 3742
	},

3743
	[MV88E6341] = {
3744
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3745 3746 3747
		.family = MV88E6XXX_FAMILY_6341,
		.name = "Marvell 88E6341",
		.num_databases = 4096,
3748
		.num_internal_phys = 5,
3749
		.num_ports = 6,
3750
		.num_gpio = 11,
3751
		.max_vid = 4095,
3752 3753
		.port_base_addr = 0x10,
		.global1_addr = 0x1b,
3754
		.global2_addr = 0x1c,
3755
		.age_time_coeff = 3750,
3756
		.atu_move_port_mask = 0x1f,
3757
		.g1_irqs = 9,
3758
		.g2_irqs = 10,
3759
		.pvt = true,
3760
		.multi_chip = true,
3761
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3762
		.ptp_support = true,
3763 3764 3765
		.ops = &mv88e6341_ops,
	},

3766
	[MV88E6350] = {
3767
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
3768 3769 3770 3771
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6350",
		.num_databases = 4096,
		.num_ports = 7,
3772
		.num_internal_phys = 5,
3773
		.max_vid = 4095,
3774
		.port_base_addr = 0x10,
3775
		.global1_addr = 0x1b,
3776
		.global2_addr = 0x1c,
3777
		.age_time_coeff = 15000,
3778
		.g1_irqs = 9,
3779
		.g2_irqs = 10,
3780
		.atu_move_port_mask = 0xf,
3781
		.pvt = true,
3782
		.multi_chip = true,
3783
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3784
		.ops = &mv88e6350_ops,
3785 3786 3787
	},

	[MV88E6351] = {
3788
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
3789 3790 3791 3792
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6351",
		.num_databases = 4096,
		.num_ports = 7,
3793
		.num_internal_phys = 5,
3794
		.max_vid = 4095,
3795
		.port_base_addr = 0x10,
3796
		.global1_addr = 0x1b,
3797
		.global2_addr = 0x1c,
3798
		.age_time_coeff = 15000,
3799
		.g1_irqs = 9,
3800
		.g2_irqs = 10,
3801
		.atu_move_port_mask = 0xf,
3802
		.pvt = true,
3803
		.multi_chip = true,
3804
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3805
		.ops = &mv88e6351_ops,
3806 3807 3808
	},

	[MV88E6352] = {
3809
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
3810 3811 3812 3813
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6352",
		.num_databases = 4096,
		.num_ports = 7,
3814
		.num_internal_phys = 5,
3815
		.num_gpio = 15,
3816
		.max_vid = 4095,
3817
		.port_base_addr = 0x10,
3818
		.global1_addr = 0x1b,
3819
		.global2_addr = 0x1c,
3820
		.age_time_coeff = 15000,
3821
		.g1_irqs = 9,
3822
		.g2_irqs = 10,
3823
		.atu_move_port_mask = 0xf,
3824
		.pvt = true,
3825
		.multi_chip = true,
3826
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3827
		.ptp_support = true,
3828
		.ops = &mv88e6352_ops,
3829
	},
3830
	[MV88E6390] = {
3831
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
3832 3833 3834 3835
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6390",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3836
		.num_internal_phys = 11,
3837
		.num_gpio = 16,
3838
		.max_vid = 8191,
3839 3840
		.port_base_addr = 0x0,
		.global1_addr = 0x1b,
3841
		.global2_addr = 0x1c,
3842
		.age_time_coeff = 3750,
3843
		.g1_irqs = 9,
3844
		.g2_irqs = 14,
3845
		.atu_move_port_mask = 0x1f,
3846
		.pvt = true,
3847
		.multi_chip = true,
3848
		.tag_protocol = DSA_TAG_PROTO_DSA,
3849
		.ptp_support = true,
3850 3851 3852
		.ops = &mv88e6390_ops,
	},
	[MV88E6390X] = {
3853
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
3854 3855 3856 3857
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6390X",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3858
		.num_internal_phys = 11,
3859
		.num_gpio = 16,
3860
		.max_vid = 8191,
3861 3862
		.port_base_addr = 0x0,
		.global1_addr = 0x1b,
3863
		.global2_addr = 0x1c,
3864
		.age_time_coeff = 3750,
3865
		.g1_irqs = 9,
3866
		.g2_irqs = 14,
3867
		.atu_move_port_mask = 0x1f,
3868
		.pvt = true,
3869
		.multi_chip = true,
3870
		.tag_protocol = DSA_TAG_PROTO_DSA,
3871
		.ptp_support = true,
3872 3873
		.ops = &mv88e6390x_ops,
	},
3874 3875
};

3876
static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
3877
{
3878
	int i;
3879

3880 3881 3882
	for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
		if (mv88e6xxx_table[i].prod_num == prod_num)
			return &mv88e6xxx_table[i];
3883 3884 3885 3886

	return NULL;
}

3887
static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
3888 3889
{
	const struct mv88e6xxx_info *info;
3890 3891 3892
	unsigned int prod_num, rev;
	u16 id;
	int err;
3893

3894
	mutex_lock(&chip->reg_lock);
3895
	err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
3896 3897 3898
	mutex_unlock(&chip->reg_lock);
	if (err)
		return err;
3899

3900 3901
	prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
	rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
3902 3903 3904 3905 3906

	info = mv88e6xxx_lookup_info(prod_num);
	if (!info)
		return -ENODEV;

3907
	/* Update the compatible info with the probed one */
3908
	chip->info = info;
3909

3910 3911 3912 3913
	err = mv88e6xxx_g2_require(chip);
	if (err)
		return err;

3914 3915
	dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
		 chip->info->prod_num, chip->info->name, rev);
3916 3917 3918 3919

	return 0;
}

3920
static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
3921
{
3922
	struct mv88e6xxx_chip *chip;
3923

3924 3925
	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
	if (!chip)
3926 3927
		return NULL;

3928
	chip->dev = dev;
3929

3930
	mutex_init(&chip->reg_lock);
3931
	INIT_LIST_HEAD(&chip->mdios);
3932

3933
	return chip;
3934 3935
}

3936
static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
3937 3938
			      struct mii_bus *bus, int sw_addr)
{
3939
	if (sw_addr == 0)
3940
		chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
3941
	else if (chip->info->multi_chip)
3942
		chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
3943 3944 3945
	else
		return -EINVAL;

3946 3947
	chip->bus = bus;
	chip->sw_addr = sw_addr;
3948 3949 3950 3951

	return 0;
}

3952 3953
static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
							int port)
3954
{
V
Vivien Didelot 已提交
3955
	struct mv88e6xxx_chip *chip = ds->priv;
3956

3957
	return chip->info->tag_protocol;
3958 3959
}

3960
#if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
3961 3962 3963
static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
				       struct device *host_dev, int sw_addr,
				       void **priv)
3964
{
3965
	struct mv88e6xxx_chip *chip;
3966
	struct mii_bus *bus;
3967
	int err;
3968

3969
	bus = dsa_host_dev_to_mii_bus(host_dev);
3970 3971 3972
	if (!bus)
		return NULL;

3973 3974
	chip = mv88e6xxx_alloc_chip(dsa_dev);
	if (!chip)
3975 3976
		return NULL;

3977
	/* Legacy SMI probing will only support chips similar to 88E6085 */
3978
	chip->info = &mv88e6xxx_table[MV88E6085];
3979

3980
	err = mv88e6xxx_smi_init(chip, bus, sw_addr);
3981 3982 3983
	if (err)
		goto free;

3984
	err = mv88e6xxx_detect(chip);
3985
	if (err)
3986
		goto free;
3987

3988 3989 3990 3991 3992 3993
	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_switch_reset(chip);
	mutex_unlock(&chip->reg_lock);
	if (err)
		goto free;

3994 3995
	mv88e6xxx_phy_init(chip);

3996
	err = mv88e6xxx_mdios_register(chip, NULL);
3997
	if (err)
3998
		goto free;
3999

4000
	*priv = chip;
4001

4002
	return chip->info->name;
4003
free:
4004
	devm_kfree(dsa_dev, chip);
4005 4006

	return NULL;
4007
}
4008
#endif
4009

4010
static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
4011
				      const struct switchdev_obj_port_mdb *mdb)
4012 4013 4014 4015 4016 4017 4018 4019 4020
{
	/* We don't need any dynamic resource from the kernel (yet),
	 * so skip the prepare phase.
	 */

	return 0;
}

static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
4021
				   const struct switchdev_obj_port_mdb *mdb)
4022
{
V
Vivien Didelot 已提交
4023
	struct mv88e6xxx_chip *chip = ds->priv;
4024 4025 4026

	mutex_lock(&chip->reg_lock);
	if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4027
					 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
4028 4029
		dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
			port);
4030 4031 4032 4033 4034 4035
	mutex_unlock(&chip->reg_lock);
}

static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
				  const struct switchdev_obj_port_mdb *mdb)
{
V
Vivien Didelot 已提交
4036
	struct mv88e6xxx_chip *chip = ds->priv;
4037 4038 4039 4040
	int err;

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4041
					   MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
4042 4043 4044 4045 4046
	mutex_unlock(&chip->reg_lock);

	return err;
}

4047
static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
4048
#if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
4049
	.probe			= mv88e6xxx_drv_probe,
4050
#endif
4051
	.get_tag_protocol	= mv88e6xxx_get_tag_protocol,
4052 4053 4054 4055 4056
	.setup			= mv88e6xxx_setup,
	.adjust_link		= mv88e6xxx_adjust_link,
	.get_strings		= mv88e6xxx_get_strings,
	.get_ethtool_stats	= mv88e6xxx_get_ethtool_stats,
	.get_sset_count		= mv88e6xxx_get_sset_count,
4057 4058
	.port_enable		= mv88e6xxx_port_enable,
	.port_disable		= mv88e6xxx_port_disable,
V
Vivien Didelot 已提交
4059 4060
	.get_mac_eee		= mv88e6xxx_get_mac_eee,
	.set_mac_eee		= mv88e6xxx_set_mac_eee,
4061
	.get_eeprom_len		= mv88e6xxx_get_eeprom_len,
4062 4063 4064 4065
	.get_eeprom		= mv88e6xxx_get_eeprom,
	.set_eeprom		= mv88e6xxx_set_eeprom,
	.get_regs_len		= mv88e6xxx_get_regs_len,
	.get_regs		= mv88e6xxx_get_regs,
4066
	.set_ageing_time	= mv88e6xxx_set_ageing_time,
4067 4068 4069
	.port_bridge_join	= mv88e6xxx_port_bridge_join,
	.port_bridge_leave	= mv88e6xxx_port_bridge_leave,
	.port_stp_state_set	= mv88e6xxx_port_stp_state_set,
4070
	.port_fast_age		= mv88e6xxx_port_fast_age,
4071 4072 4073 4074 4075 4076 4077
	.port_vlan_filtering	= mv88e6xxx_port_vlan_filtering,
	.port_vlan_prepare	= mv88e6xxx_port_vlan_prepare,
	.port_vlan_add		= mv88e6xxx_port_vlan_add,
	.port_vlan_del		= mv88e6xxx_port_vlan_del,
	.port_fdb_add           = mv88e6xxx_port_fdb_add,
	.port_fdb_del           = mv88e6xxx_port_fdb_del,
	.port_fdb_dump          = mv88e6xxx_port_fdb_dump,
4078 4079 4080
	.port_mdb_prepare       = mv88e6xxx_port_mdb_prepare,
	.port_mdb_add           = mv88e6xxx_port_mdb_add,
	.port_mdb_del           = mv88e6xxx_port_mdb_del,
4081 4082
	.crosschip_bridge_join	= mv88e6xxx_crosschip_bridge_join,
	.crosschip_bridge_leave	= mv88e6xxx_crosschip_bridge_leave,
4083 4084 4085 4086 4087
	.port_hwtstamp_set	= mv88e6xxx_port_hwtstamp_set,
	.port_hwtstamp_get	= mv88e6xxx_port_hwtstamp_get,
	.port_txtstamp		= mv88e6xxx_port_txtstamp,
	.port_rxtstamp		= mv88e6xxx_port_rxtstamp,
	.get_ts_info		= mv88e6xxx_get_ts_info,
4088 4089
};

4090 4091 4092 4093
static struct dsa_switch_driver mv88e6xxx_switch_drv = {
	.ops			= &mv88e6xxx_switch_ops,
};

4094
static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
4095
{
4096
	struct device *dev = chip->dev;
4097 4098
	struct dsa_switch *ds;

4099
	ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip));
4100 4101 4102
	if (!ds)
		return -ENOMEM;

4103
	ds->priv = chip;
4104
	ds->ops = &mv88e6xxx_switch_ops;
4105 4106
	ds->ageing_time_min = chip->info->age_time_coeff;
	ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
4107 4108 4109

	dev_set_drvdata(dev, ds);

4110
	return dsa_register_switch(ds);
4111 4112
}

4113
static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
4114
{
4115
	dsa_unregister_switch(chip->ds);
4116 4117
}

4118
static int mv88e6xxx_probe(struct mdio_device *mdiodev)
4119
{
4120
	struct device *dev = &mdiodev->dev;
4121
	struct device_node *np = dev->of_node;
4122
	const struct mv88e6xxx_info *compat_info;
4123
	struct mv88e6xxx_chip *chip;
4124
	u32 eeprom_len;
4125
	int err;
4126

4127 4128 4129 4130
	compat_info = of_device_get_match_data(dev);
	if (!compat_info)
		return -EINVAL;

4131 4132
	chip = mv88e6xxx_alloc_chip(dev);
	if (!chip)
4133 4134
		return -ENOMEM;

4135
	chip->info = compat_info;
4136

4137
	err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4138 4139
	if (err)
		return err;
4140

4141 4142 4143 4144
	chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
	if (IS_ERR(chip->reset))
		return PTR_ERR(chip->reset);

4145
	err = mv88e6xxx_detect(chip);
4146 4147
	if (err)
		return err;
4148

4149 4150
	mv88e6xxx_phy_init(chip);

4151
	if (chip->info->ops->get_eeprom &&
4152
	    !of_property_read_u32(np, "eeprom-length", &eeprom_len))
4153
		chip->eeprom_len = eeprom_len;
4154

4155 4156 4157 4158 4159 4160 4161 4162 4163 4164 4165 4166
	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_switch_reset(chip);
	mutex_unlock(&chip->reg_lock);
	if (err)
		goto out;

	chip->irq = of_irq_get(np, 0);
	if (chip->irq == -EPROBE_DEFER) {
		err = chip->irq;
		goto out;
	}

4167 4168 4169 4170 4171 4172
	/* Has to be performed before the MDIO bus is created, because
	 * the PHYs will link there interrupts to these interrupt
	 * controllers
	 */
	mutex_lock(&chip->reg_lock);
	if (chip->irq > 0)
4173
		err = mv88e6xxx_g1_irq_setup(chip);
4174 4175 4176
	else
		err = mv88e6xxx_irq_poll_setup(chip);
	mutex_unlock(&chip->reg_lock);
4177

4178 4179
	if (err)
		goto out;
4180

4181 4182
	if (chip->info->g2_irqs > 0) {
		err = mv88e6xxx_g2_irq_setup(chip);
4183
		if (err)
4184
			goto out_g1_irq;
4185 4186
	}

4187 4188 4189 4190 4191 4192 4193 4194
	err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
	if (err)
		goto out_g2_irq;

	err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
	if (err)
		goto out_g1_atu_prob_irq;

4195
	err = mv88e6xxx_mdios_register(chip, np);
4196
	if (err)
4197
		goto out_g1_vtu_prob_irq;
4198

4199
	err = mv88e6xxx_register_switch(chip);
4200 4201
	if (err)
		goto out_mdio;
4202

4203
	return 0;
4204 4205

out_mdio:
4206
	mv88e6xxx_mdios_unregister(chip);
4207
out_g1_vtu_prob_irq:
4208
	mv88e6xxx_g1_vtu_prob_irq_free(chip);
4209
out_g1_atu_prob_irq:
4210
	mv88e6xxx_g1_atu_prob_irq_free(chip);
4211
out_g2_irq:
4212
	if (chip->info->g2_irqs > 0)
4213 4214
		mv88e6xxx_g2_irq_free(chip);
out_g1_irq:
4215 4216
	mutex_lock(&chip->reg_lock);
	if (chip->irq > 0)
4217
		mv88e6xxx_g1_irq_free(chip);
4218 4219 4220
	else
		mv88e6xxx_irq_poll_free(chip);
	mutex_unlock(&chip->reg_lock);
4221 4222
out:
	return err;
4223
}
4224 4225 4226 4227

static void mv88e6xxx_remove(struct mdio_device *mdiodev)
{
	struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
V
Vivien Didelot 已提交
4228
	struct mv88e6xxx_chip *chip = ds->priv;
4229

4230 4231
	if (chip->info->ptp_support) {
		mv88e6xxx_hwtstamp_free(chip);
4232
		mv88e6xxx_ptp_free(chip);
4233
	}
4234

4235
	mv88e6xxx_phy_destroy(chip);
4236
	mv88e6xxx_unregister_switch(chip);
4237
	mv88e6xxx_mdios_unregister(chip);
4238

4239 4240 4241 4242 4243 4244 4245 4246
	mv88e6xxx_g1_vtu_prob_irq_free(chip);
	mv88e6xxx_g1_atu_prob_irq_free(chip);

	if (chip->info->g2_irqs > 0)
		mv88e6xxx_g2_irq_free(chip);

	mutex_lock(&chip->reg_lock);
	if (chip->irq > 0)
4247
		mv88e6xxx_g1_irq_free(chip);
4248 4249 4250
	else
		mv88e6xxx_irq_poll_free(chip);
	mutex_unlock(&chip->reg_lock);
4251 4252 4253
}

static const struct of_device_id mv88e6xxx_of_match[] = {
4254 4255 4256 4257
	{
		.compatible = "marvell,mv88e6085",
		.data = &mv88e6xxx_table[MV88E6085],
	},
4258 4259 4260 4261
	{
		.compatible = "marvell,mv88e6190",
		.data = &mv88e6xxx_table[MV88E6190],
	},
4262 4263 4264 4265 4266 4267 4268 4269 4270 4271 4272 4273 4274 4275 4276 4277
	{ /* sentinel */ },
};

MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);

static struct mdio_driver mv88e6xxx_driver = {
	.probe	= mv88e6xxx_probe,
	.remove = mv88e6xxx_remove,
	.mdiodrv.driver = {
		.name = "mv88e6085",
		.of_match_table = mv88e6xxx_of_match,
	},
};

static int __init mv88e6xxx_init(void)
{
4278
	register_switch_driver(&mv88e6xxx_switch_drv);
4279 4280
	return mdio_driver_register(&mv88e6xxx_driver);
}
4281 4282 4283 4284
module_init(mv88e6xxx_init);

static void __exit mv88e6xxx_cleanup(void)
{
4285
	mdio_driver_unregister(&mv88e6xxx_driver);
4286
	unregister_switch_driver(&mv88e6xxx_switch_drv);
4287 4288
}
module_exit(mv88e6xxx_cleanup);
4289 4290 4291 4292

MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
MODULE_LICENSE("GPL");