chip.c 126.3 KB
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/*
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 * Marvell 88e6xxx Ethernet switch single-chip support
 *
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 * Copyright (c) 2008 Marvell Semiconductor
 *
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 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
 *
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 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
 *	Vivien Didelot <vivien.didelot@savoirfairelinux.com>
 *
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 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

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#include <linux/delay.h>
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#include <linux/etherdevice.h>
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#include <linux/ethtool.h>
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#include <linux/if_bridge.h>
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#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
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#include <linux/jiffies.h>
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#include <linux/list.h>
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#include <linux/mdio.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/of_mdio.h>
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#include <linux/netdevice.h>
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#include <linux/gpio/consumer.h>
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#include <linux/phy.h>
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#include <linux/phylink.h>
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#include <net/dsa.h>
36

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#include "chip.h"
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#include "global1.h"
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#include "global2.h"
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#include "hwtstamp.h"
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#include "phy.h"
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#include "port.h"
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#include "ptp.h"
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#include "serdes.h"
45

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static void assert_reg_lock(struct mv88e6xxx_chip *chip)
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{
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	if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
		dev_err(chip->dev, "Switch registers lock not held!\n");
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		dump_stack();
	}
}

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/* The switch ADDR[4:1] configuration pins define the chip SMI device address
 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
 *
 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
 * is the only device connected to the SMI master. In this mode it responds to
 * all 32 possible SMI addresses, and thus maps directly the internal devices.
 *
 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
 * multiple devices to share the SMI interface. In this mode it responds to only
 * 2 registers, used to indirectly access the internal SMI devices.
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 */
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static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
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			      int addr, int reg, u16 *val)
{
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	if (!chip->smi_ops)
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		return -EOPNOTSUPP;

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	return chip->smi_ops->read(chip, addr, reg, val);
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}

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static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
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			       int addr, int reg, u16 val)
{
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	if (!chip->smi_ops)
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		return -EOPNOTSUPP;

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	return chip->smi_ops->write(chip, addr, reg, val);
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}

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static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
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					  int addr, int reg, u16 *val)
{
	int ret;

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	ret = mdiobus_read_nested(chip->bus, addr, reg);
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	if (ret < 0)
		return ret;

	*val = ret & 0xffff;

	return 0;
}

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static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
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					   int addr, int reg, u16 val)
{
	int ret;

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	ret = mdiobus_write_nested(chip->bus, addr, reg, val);
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	if (ret < 0)
		return ret;

	return 0;
}

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static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
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	.read = mv88e6xxx_smi_single_chip_read,
	.write = mv88e6xxx_smi_single_chip_write,
};

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static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
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{
	int ret;
	int i;

	for (i = 0; i < 16; i++) {
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		ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
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		if (ret < 0)
			return ret;

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		if ((ret & SMI_CMD_BUSY) == 0)
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			return 0;
	}

	return -ETIMEDOUT;
}

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static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
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					 int addr, int reg, u16 *val)
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{
	int ret;

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	/* Wait for the bus to become free. */
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	ret = mv88e6xxx_smi_multi_chip_wait(chip);
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	if (ret < 0)
		return ret;

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	/* Transmit the read command. */
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	ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
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				   SMI_CMD_OP_22_READ | (addr << 5) | reg);
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	if (ret < 0)
		return ret;

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	/* Wait for the read command to complete. */
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	ret = mv88e6xxx_smi_multi_chip_wait(chip);
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	if (ret < 0)
		return ret;

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	/* Read the data. */
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	ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
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	if (ret < 0)
		return ret;

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	*val = ret & 0xffff;
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	return 0;
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}

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static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
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					  int addr, int reg, u16 val)
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{
	int ret;

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	/* Wait for the bus to become free. */
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	ret = mv88e6xxx_smi_multi_chip_wait(chip);
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	if (ret < 0)
		return ret;

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	/* Transmit the data to write. */
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	ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
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	if (ret < 0)
		return ret;

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	/* Transmit the write command. */
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	ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
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				   SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
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	if (ret < 0)
		return ret;

184
	/* Wait for the write command to complete. */
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	ret = mv88e6xxx_smi_multi_chip_wait(chip);
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	if (ret < 0)
		return ret;

	return 0;
}

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static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
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	.read = mv88e6xxx_smi_multi_chip_read,
	.write = mv88e6xxx_smi_multi_chip_write,
};

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int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
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{
	int err;

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	assert_reg_lock(chip);
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	err = mv88e6xxx_smi_read(chip, addr, reg, val);
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	if (err)
		return err;

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	dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
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		addr, reg, *val);

	return 0;
}

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int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
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{
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	int err;

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	assert_reg_lock(chip);
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	err = mv88e6xxx_smi_write(chip, addr, reg, val);
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	if (err)
		return err;

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	dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
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		addr, reg, val);

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	return 0;
}

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struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
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{
	struct mv88e6xxx_mdio_bus *mdio_bus;

	mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
				    list);
	if (!mdio_bus)
		return NULL;

	return mdio_bus->bus;
}

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static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
{
	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int n = d->hwirq;

	chip->g1_irq.masked |= (1 << n);
}

static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
{
	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int n = d->hwirq;

	chip->g1_irq.masked &= ~(1 << n);
}

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static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
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{
	unsigned int nhandled = 0;
	unsigned int sub_irq;
	unsigned int n;
	u16 reg;
	int err;

	mutex_lock(&chip->reg_lock);
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	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
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	mutex_unlock(&chip->reg_lock);

	if (err)
		goto out;

	for (n = 0; n < chip->g1_irq.nirqs; ++n) {
		if (reg & (1 << n)) {
			sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
			handle_nested_irq(sub_irq);
			++nhandled;
		}
	}
out:
	return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
}

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static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
{
	struct mv88e6xxx_chip *chip = dev_id;

	return mv88e6xxx_g1_irq_thread_work(chip);
}

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static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
{
	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);

	mutex_lock(&chip->reg_lock);
}

static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
{
	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
	u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
	u16 reg;
	int err;

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	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
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	if (err)
		goto out;

	reg &= ~mask;
	reg |= (~chip->g1_irq.masked & mask);

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	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
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	if (err)
		goto out;

out:
	mutex_unlock(&chip->reg_lock);
}

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static const struct irq_chip mv88e6xxx_g1_irq_chip = {
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	.name			= "mv88e6xxx-g1",
	.irq_mask		= mv88e6xxx_g1_irq_mask,
	.irq_unmask		= mv88e6xxx_g1_irq_unmask,
	.irq_bus_lock		= mv88e6xxx_g1_irq_bus_lock,
	.irq_bus_sync_unlock	= mv88e6xxx_g1_irq_bus_sync_unlock,
};

static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
				       unsigned int irq,
				       irq_hw_number_t hwirq)
{
	struct mv88e6xxx_chip *chip = d->host_data;

	irq_set_chip_data(irq, d->host_data);
	irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
	irq_set_noprobe(irq);

	return 0;
}

static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
	.map	= mv88e6xxx_g1_irq_domain_map,
	.xlate	= irq_domain_xlate_twocell,
};

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static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
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{
	int irq, virq;
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	u16 mask;

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	mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
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	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
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	mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
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354
	for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
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		virq = irq_find_mapping(chip->g1_irq.domain, irq);
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		irq_dispose_mapping(virq);
	}

359
	irq_domain_remove(chip->g1_irq.domain);
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}

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static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
{
364
	mv88e6xxx_g1_irq_free_common(chip);
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	free_irq(chip->irq, chip);
}

static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
370
{
371 372
	int err, irq, virq;
	u16 reg, mask;
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	chip->g1_irq.nirqs = chip->info->g1_irqs;
	chip->g1_irq.domain = irq_domain_add_simple(
		NULL, chip->g1_irq.nirqs, 0,
		&mv88e6xxx_g1_irq_domain_ops, chip);
	if (!chip->g1_irq.domain)
		return -ENOMEM;

	for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
		irq_create_mapping(chip->g1_irq.domain, irq);

	chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
	chip->g1_irq.masked = ~0;

387
	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
388
	if (err)
389
		goto out_mapping;
390

391
	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
392

393
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
394
	if (err)
395
		goto out_disable;
396 397

	/* Reading the interrupt status clears (most of) them */
398
	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
399
	if (err)
400
		goto out_disable;
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	return 0;

404
out_disable:
405
	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
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	mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
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out_mapping:
	for (irq = 0; irq < 16; irq++) {
		virq = irq_find_mapping(chip->g1_irq.domain, irq);
		irq_dispose_mapping(virq);
	}

	irq_domain_remove(chip->g1_irq.domain);
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	return err;
}

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static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
{
	int err;

	err = mv88e6xxx_g1_irq_setup_common(chip);
	if (err)
		return err;

	err = request_threaded_irq(chip->irq, NULL,
				   mv88e6xxx_g1_irq_thread_fn,
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				   IRQF_ONESHOT,
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				   dev_name(chip->dev), chip);
	if (err)
		mv88e6xxx_g1_irq_free_common(chip);

	return err;
}

static void mv88e6xxx_irq_poll(struct kthread_work *work)
{
	struct mv88e6xxx_chip *chip = container_of(work,
						   struct mv88e6xxx_chip,
						   irq_poll_work.work);
	mv88e6xxx_g1_irq_thread_work(chip);

	kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
				   msecs_to_jiffies(100));
}

static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
{
	int err;

	err = mv88e6xxx_g1_irq_setup_common(chip);
	if (err)
		return err;

	kthread_init_delayed_work(&chip->irq_poll_work,
				  mv88e6xxx_irq_poll);

	chip->kworker = kthread_create_worker(0, dev_name(chip->dev));
	if (IS_ERR(chip->kworker))
		return PTR_ERR(chip->kworker);

	kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
				   msecs_to_jiffies(100));

	return 0;
}

static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
{
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	mv88e6xxx_g1_irq_free_common(chip);

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	kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
	kthread_destroy_worker(chip->kworker);
}

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int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
478
{
479
	int i;
480

481
	for (i = 0; i < 16; i++) {
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		u16 val;
		int err;

		err = mv88e6xxx_read(chip, addr, reg, &val);
		if (err)
			return err;

		if (!(val & mask))
			return 0;

		usleep_range(1000, 2000);
	}

495
	dev_err(chip->dev, "Timeout while waiting for switch\n");
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	return -ETIMEDOUT;
}

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/* Indirect write to single pointer-data register with an Update bit */
500
int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
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{
	u16 val;
503
	int err;
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	/* Wait until the previous operation is completed */
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	err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
	if (err)
		return err;
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	/* Set the Update bit to trigger a write operation */
	val = BIT(15) | update;

	return mv88e6xxx_write(chip, addr, reg, val);
}

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static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
				    int link, int speed, int duplex,
				    phy_interface_t mode)
{
	int err;

	if (!chip->info->ops->port_set_link)
		return 0;

	/* Port's MAC control must not be changed unless the link is down */
	err = chip->info->ops->port_set_link(chip, port, 0);
	if (err)
		return err;

	if (chip->info->ops->port_set_speed) {
		err = chip->info->ops->port_set_speed(chip, port, speed);
		if (err && err != -EOPNOTSUPP)
			goto restore_link;
	}

	if (chip->info->ops->port_set_duplex) {
		err = chip->info->ops->port_set_duplex(chip, port, duplex);
		if (err && err != -EOPNOTSUPP)
			goto restore_link;
	}

	if (chip->info->ops->port_set_rgmii_delay) {
		err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
		if (err && err != -EOPNOTSUPP)
			goto restore_link;
	}

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	if (chip->info->ops->port_set_cmode) {
		err = chip->info->ops->port_set_cmode(chip, port, mode);
		if (err && err != -EOPNOTSUPP)
			goto restore_link;
	}

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	err = 0;
restore_link:
	if (chip->info->ops->port_set_link(chip, port, link))
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		dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
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	return err;
}

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/* We expect the switch to perform auto negotiation if there is a real
 * phy. However, in the case of a fixed link phy, we force the port
 * settings from the fixed link settings.
 */
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static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
				  struct phy_device *phydev)
568
{
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Vivien Didelot 已提交
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	struct mv88e6xxx_chip *chip = ds->priv;
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	int err;
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	if (!phy_is_pseudo_fixed_link(phydev))
		return;

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	mutex_lock(&chip->reg_lock);
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	err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
				       phydev->duplex, phydev->interface);
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	mutex_unlock(&chip->reg_lock);
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	if (err && err != -EOPNOTSUPP)
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		dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
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}

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static void mv88e6xxx_validate(struct dsa_switch *ds, int port,
			       unsigned long *supported,
			       struct phylink_link_state *state)
{
}

static int mv88e6xxx_link_state(struct dsa_switch *ds, int port,
				struct phylink_link_state *state)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int err;

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_port_link_state(chip, port, state);
	mutex_unlock(&chip->reg_lock);

	return err;
}

static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
				 unsigned int mode,
				 const struct phylink_link_state *state)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int speed, duplex, link, err;

	if (mode == MLO_AN_PHY)
		return;

	if (mode == MLO_AN_FIXED) {
		link = LINK_FORCED_UP;
		speed = state->speed;
		duplex = state->duplex;
	} else {
		speed = SPEED_UNFORCED;
		duplex = DUPLEX_UNFORCED;
		link = LINK_UNFORCED;
	}

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_port_setup_mac(chip, port, link, speed, duplex,
				       state->interface);
	mutex_unlock(&chip->reg_lock);

	if (err && err != -EOPNOTSUPP)
		dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
}

static void mv88e6xxx_mac_link_force(struct dsa_switch *ds, int port, int link)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int err;

	mutex_lock(&chip->reg_lock);
	err = chip->info->ops->port_set_link(chip, port, link);
	mutex_unlock(&chip->reg_lock);

	if (err)
		dev_err(chip->dev, "p%d: failed to force MAC link\n", port);
}

static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
				    unsigned int mode,
				    phy_interface_t interface)
{
	if (mode == MLO_AN_FIXED)
		mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_DOWN);
}

static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
				  unsigned int mode, phy_interface_t interface,
				  struct phy_device *phydev)
{
	if (mode == MLO_AN_FIXED)
		mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_UP);
}

661
static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
662
{
663 664
	if (!chip->info->ops->stats_snapshot)
		return -EOPNOTSUPP;
665

666
	return chip->info->ops->stats_snapshot(chip, port);
667 668
}

669
static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728
	{ "in_good_octets",		8, 0x00, STATS_TYPE_BANK0, },
	{ "in_bad_octets",		4, 0x02, STATS_TYPE_BANK0, },
	{ "in_unicast",			4, 0x04, STATS_TYPE_BANK0, },
	{ "in_broadcasts",		4, 0x06, STATS_TYPE_BANK0, },
	{ "in_multicasts",		4, 0x07, STATS_TYPE_BANK0, },
	{ "in_pause",			4, 0x16, STATS_TYPE_BANK0, },
	{ "in_undersize",		4, 0x18, STATS_TYPE_BANK0, },
	{ "in_fragments",		4, 0x19, STATS_TYPE_BANK0, },
	{ "in_oversize",		4, 0x1a, STATS_TYPE_BANK0, },
	{ "in_jabber",			4, 0x1b, STATS_TYPE_BANK0, },
	{ "in_rx_error",		4, 0x1c, STATS_TYPE_BANK0, },
	{ "in_fcs_error",		4, 0x1d, STATS_TYPE_BANK0, },
	{ "out_octets",			8, 0x0e, STATS_TYPE_BANK0, },
	{ "out_unicast",		4, 0x10, STATS_TYPE_BANK0, },
	{ "out_broadcasts",		4, 0x13, STATS_TYPE_BANK0, },
	{ "out_multicasts",		4, 0x12, STATS_TYPE_BANK0, },
	{ "out_pause",			4, 0x15, STATS_TYPE_BANK0, },
	{ "excessive",			4, 0x11, STATS_TYPE_BANK0, },
	{ "collisions",			4, 0x1e, STATS_TYPE_BANK0, },
	{ "deferred",			4, 0x05, STATS_TYPE_BANK0, },
	{ "single",			4, 0x14, STATS_TYPE_BANK0, },
	{ "multiple",			4, 0x17, STATS_TYPE_BANK0, },
	{ "out_fcs_error",		4, 0x03, STATS_TYPE_BANK0, },
	{ "late",			4, 0x1f, STATS_TYPE_BANK0, },
	{ "hist_64bytes",		4, 0x08, STATS_TYPE_BANK0, },
	{ "hist_65_127bytes",		4, 0x09, STATS_TYPE_BANK0, },
	{ "hist_128_255bytes",		4, 0x0a, STATS_TYPE_BANK0, },
	{ "hist_256_511bytes",		4, 0x0b, STATS_TYPE_BANK0, },
	{ "hist_512_1023bytes",		4, 0x0c, STATS_TYPE_BANK0, },
	{ "hist_1024_max_bytes",	4, 0x0d, STATS_TYPE_BANK0, },
	{ "sw_in_discards",		4, 0x10, STATS_TYPE_PORT, },
	{ "sw_in_filtered",		2, 0x12, STATS_TYPE_PORT, },
	{ "sw_out_filtered",		2, 0x13, STATS_TYPE_PORT, },
	{ "in_discards",		4, 0x00, STATS_TYPE_BANK1, },
	{ "in_filtered",		4, 0x01, STATS_TYPE_BANK1, },
	{ "in_accepted",		4, 0x02, STATS_TYPE_BANK1, },
	{ "in_bad_accepted",		4, 0x03, STATS_TYPE_BANK1, },
	{ "in_good_avb_class_a",	4, 0x04, STATS_TYPE_BANK1, },
	{ "in_good_avb_class_b",	4, 0x05, STATS_TYPE_BANK1, },
	{ "in_bad_avb_class_a",		4, 0x06, STATS_TYPE_BANK1, },
	{ "in_bad_avb_class_b",		4, 0x07, STATS_TYPE_BANK1, },
	{ "tcam_counter_0",		4, 0x08, STATS_TYPE_BANK1, },
	{ "tcam_counter_1",		4, 0x09, STATS_TYPE_BANK1, },
	{ "tcam_counter_2",		4, 0x0a, STATS_TYPE_BANK1, },
	{ "tcam_counter_3",		4, 0x0b, STATS_TYPE_BANK1, },
	{ "in_da_unknown",		4, 0x0e, STATS_TYPE_BANK1, },
	{ "in_management",		4, 0x0f, STATS_TYPE_BANK1, },
	{ "out_queue_0",		4, 0x10, STATS_TYPE_BANK1, },
	{ "out_queue_1",		4, 0x11, STATS_TYPE_BANK1, },
	{ "out_queue_2",		4, 0x12, STATS_TYPE_BANK1, },
	{ "out_queue_3",		4, 0x13, STATS_TYPE_BANK1, },
	{ "out_queue_4",		4, 0x14, STATS_TYPE_BANK1, },
	{ "out_queue_5",		4, 0x15, STATS_TYPE_BANK1, },
	{ "out_queue_6",		4, 0x16, STATS_TYPE_BANK1, },
	{ "out_queue_7",		4, 0x17, STATS_TYPE_BANK1, },
	{ "out_cut_through",		4, 0x18, STATS_TYPE_BANK1, },
	{ "out_octets_a",		4, 0x1a, STATS_TYPE_BANK1, },
	{ "out_octets_b",		4, 0x1b, STATS_TYPE_BANK1, },
	{ "out_management",		4, 0x1f, STATS_TYPE_BANK1, },
729 730
};

731
static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
732
					    struct mv88e6xxx_hw_stat *s,
733 734
					    int port, u16 bank1_select,
					    u16 histogram)
735 736 737
{
	u32 low;
	u32 high = 0;
738
	u16 reg = 0;
739
	int err;
740 741
	u64 value;

742
	switch (s->type) {
743
	case STATS_TYPE_PORT:
744 745
		err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
		if (err)
746
			return U64_MAX;
747

748
		low = reg;
749
		if (s->size == 4) {
750 751
			err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
			if (err)
752
				return U64_MAX;
753
			high = reg;
754
		}
755
		break;
756
	case STATS_TYPE_BANK1:
757
		reg = bank1_select;
758 759
		/* fall through */
	case STATS_TYPE_BANK0:
760
		reg |= s->reg | histogram;
761
		mv88e6xxx_g1_stats_read(chip, reg, &low);
762
		if (s->size == 8)
763
			mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
764 765
		break;
	default:
766
		return U64_MAX;
767 768 769 770 771
	}
	value = (((u64)high) << 16) | low;
	return value;
}

772 773
static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
				       uint8_t *data, int types)
774
{
775 776
	struct mv88e6xxx_hw_stat *stat;
	int i, j;
777

778 779
	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
		stat = &mv88e6xxx_hw_stats[i];
780
		if (stat->type & types) {
781 782 783 784
			memcpy(data + j * ETH_GSTRING_LEN, stat->string,
			       ETH_GSTRING_LEN);
			j++;
		}
785
	}
786 787

	return j;
788 789
}

790 791
static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
				       uint8_t *data)
792
{
793 794
	return mv88e6xxx_stats_get_strings(chip, data,
					   STATS_TYPE_BANK0 | STATS_TYPE_PORT);
795 796
}

797 798
static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
				       uint8_t *data)
799
{
800 801
	return mv88e6xxx_stats_get_strings(chip, data,
					   STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
802 803
}

804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821
static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
	"atu_member_violation",
	"atu_miss_violation",
	"atu_full_violation",
	"vtu_member_violation",
	"vtu_miss_violation",
};

static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
{
	unsigned int i;

	for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
		strlcpy(data + i * ETH_GSTRING_LEN,
			mv88e6xxx_atu_vtu_stats_strings[i],
			ETH_GSTRING_LEN);
}

822
static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
823
				  u32 stringset, uint8_t *data)
824
{
V
Vivien Didelot 已提交
825
	struct mv88e6xxx_chip *chip = ds->priv;
826
	int count = 0;
827

828 829 830
	if (stringset != ETH_SS_STATS)
		return;

831 832
	mutex_lock(&chip->reg_lock);

833
	if (chip->info->ops->stats_get_strings)
834 835 836 837
		count = chip->info->ops->stats_get_strings(chip, data);

	if (chip->info->ops->serdes_get_strings) {
		data += count * ETH_GSTRING_LEN;
838
		count = chip->info->ops->serdes_get_strings(chip, port, data);
839
	}
840

841 842 843
	data += count * ETH_GSTRING_LEN;
	mv88e6xxx_atu_vtu_get_strings(data);

844
	mutex_unlock(&chip->reg_lock);
845 846 847 848 849
}

static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
					  int types)
{
850 851 852 853 854
	struct mv88e6xxx_hw_stat *stat;
	int i, j;

	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
		stat = &mv88e6xxx_hw_stats[i];
855
		if (stat->type & types)
856 857 858
			j++;
	}
	return j;
859 860
}

861 862 863 864 865 866 867 868 869 870 871 872
static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
{
	return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
					      STATS_TYPE_PORT);
}

static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
{
	return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
					      STATS_TYPE_BANK1);
}

873
static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
874 875
{
	struct mv88e6xxx_chip *chip = ds->priv;
876 877
	int serdes_count = 0;
	int count = 0;
878

879 880 881
	if (sset != ETH_SS_STATS)
		return 0;

882
	mutex_lock(&chip->reg_lock);
883
	if (chip->info->ops->stats_get_sset_count)
884 885 886 887 888 889 890
		count = chip->info->ops->stats_get_sset_count(chip);
	if (count < 0)
		goto out;

	if (chip->info->ops->serdes_get_sset_count)
		serdes_count = chip->info->ops->serdes_get_sset_count(chip,
								      port);
891
	if (serdes_count < 0) {
892
		count = serdes_count;
893 894 895 896 897
		goto out;
	}
	count += serdes_count;
	count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);

898
out:
899
	mutex_unlock(&chip->reg_lock);
900

901
	return count;
902 903
}

904 905 906
static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
				     uint64_t *data, int types,
				     u16 bank1_select, u16 histogram)
907 908 909 910 911 912 913
{
	struct mv88e6xxx_hw_stat *stat;
	int i, j;

	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
		stat = &mv88e6xxx_hw_stats[i];
		if (stat->type & types) {
914
			mutex_lock(&chip->reg_lock);
915 916 917
			data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
							      bank1_select,
							      histogram);
918 919
			mutex_unlock(&chip->reg_lock);

920 921 922
			j++;
		}
	}
923
	return j;
924 925
}

926 927
static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
				     uint64_t *data)
928 929
{
	return mv88e6xxx_stats_get_stats(chip, port, data,
930
					 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
931
					 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
932 933
}

934 935
static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
				     uint64_t *data)
936 937
{
	return mv88e6xxx_stats_get_stats(chip, port, data,
938
					 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
939 940
					 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
					 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
941 942
}

943 944
static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
				     uint64_t *data)
945 946 947
{
	return mv88e6xxx_stats_get_stats(chip, port, data,
					 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
948 949
					 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
					 0);
950 951
}

952 953 954 955 956 957 958 959 960 961
static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
					uint64_t *data)
{
	*data++ = chip->ports[port].atu_member_violation;
	*data++ = chip->ports[port].atu_miss_violation;
	*data++ = chip->ports[port].atu_full_violation;
	*data++ = chip->ports[port].vtu_member_violation;
	*data++ = chip->ports[port].vtu_miss_violation;
}

962 963 964
static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
				uint64_t *data)
{
965 966
	int count = 0;

967
	if (chip->info->ops->stats_get_stats)
968 969
		count = chip->info->ops->stats_get_stats(chip, port, data);

970
	mutex_lock(&chip->reg_lock);
971 972
	if (chip->info->ops->serdes_get_stats) {
		data += count;
973
		count = chip->info->ops->serdes_get_stats(chip, port, data);
974
	}
975 976 977
	data += count;
	mv88e6xxx_atu_vtu_get_stats(chip, port, data);
	mutex_unlock(&chip->reg_lock);
978 979
}

980 981
static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
					uint64_t *data)
982
{
V
Vivien Didelot 已提交
983
	struct mv88e6xxx_chip *chip = ds->priv;
984 985
	int ret;

986
	mutex_lock(&chip->reg_lock);
987

988
	ret = mv88e6xxx_stats_snapshot(chip, port);
989 990 991
	mutex_unlock(&chip->reg_lock);

	if (ret < 0)
992
		return;
993 994

	mv88e6xxx_get_stats(chip, port, data);
995

996 997
}

998 999 1000 1001 1002 1003 1004 1005
static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->stats_set_histogram)
		return chip->info->ops->stats_set_histogram(chip);

	return 0;
}

1006
static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1007 1008 1009 1010
{
	return 32 * sizeof(u16);
}

1011 1012
static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
			       struct ethtool_regs *regs, void *_p)
1013
{
V
Vivien Didelot 已提交
1014
	struct mv88e6xxx_chip *chip = ds->priv;
1015 1016
	int err;
	u16 reg;
1017 1018 1019 1020 1021 1022 1023
	u16 *p = _p;
	int i;

	regs->version = 0;

	memset(p, 0xff, 32 * sizeof(u16));

1024
	mutex_lock(&chip->reg_lock);
1025

1026 1027
	for (i = 0; i < 32; i++) {

1028 1029 1030
		err = mv88e6xxx_port_read(chip, port, i, &reg);
		if (!err)
			p[i] = reg;
1031
	}
1032

1033
	mutex_unlock(&chip->reg_lock);
1034 1035
}

V
Vivien Didelot 已提交
1036 1037
static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
				 struct ethtool_eee *e)
1038
{
1039 1040
	/* Nothing to do on the port's MAC */
	return 0;
1041 1042
}

V
Vivien Didelot 已提交
1043 1044
static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
				 struct ethtool_eee *e)
1045
{
1046 1047
	/* Nothing to do on the port's MAC */
	return 0;
1048 1049
}

1050
static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1051
{
1052 1053 1054
	struct dsa_switch *ds = NULL;
	struct net_device *br;
	u16 pvlan;
1055 1056
	int i;

1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076
	if (dev < DSA_MAX_SWITCHES)
		ds = chip->ds->dst->ds[dev];

	/* Prevent frames from unknown switch or port */
	if (!ds || port >= ds->num_ports)
		return 0;

	/* Frames from DSA links and CPU ports can egress any local port */
	if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
		return mv88e6xxx_port_mask(chip);

	br = ds->ports[port].bridge_dev;
	pvlan = 0;

	/* Frames from user ports can egress any local DSA links and CPU ports,
	 * as well as any local member of their bridge group.
	 */
	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
		if (dsa_is_cpu_port(chip->ds, i) ||
		    dsa_is_dsa_port(chip->ds, i) ||
V
Vivien Didelot 已提交
1077
		    (br && dsa_to_port(chip->ds, i)->bridge_dev == br))
1078 1079 1080 1081 1082
			pvlan |= BIT(i);

	return pvlan;
}

1083
static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1084 1085
{
	u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1086 1087 1088

	/* prevent frames from going back out of the port they came in on */
	output_ports &= ~BIT(port);
1089

1090
	return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1091 1092
}

1093 1094
static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
					 u8 state)
1095
{
V
Vivien Didelot 已提交
1096
	struct mv88e6xxx_chip *chip = ds->priv;
1097
	int err;
1098

1099
	mutex_lock(&chip->reg_lock);
1100
	err = mv88e6xxx_port_set_state(chip, port, state);
1101
	mutex_unlock(&chip->reg_lock);
1102 1103

	if (err)
1104
		dev_err(ds->dev, "p%d: failed to update state\n", port);
1105 1106
}

1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125
static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
{
	int err;

	if (chip->info->ops->ieee_pri_map) {
		err = chip->info->ops->ieee_pri_map(chip);
		if (err)
			return err;
	}

	if (chip->info->ops->ip_pri_map) {
		err = chip->info->ops->ip_pri_map(chip);
		if (err)
			return err;
	}

	return 0;
}

1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145
static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
{
	int target, port;
	int err;

	if (!chip->info->global2_addr)
		return 0;

	/* Initialize the routing port to the 32 possible target devices */
	for (target = 0; target < 32; target++) {
		port = 0x1f;
		if (target < DSA_MAX_SWITCHES)
			if (chip->ds->rtable[target] != DSA_RTABLE_NONE)
				port = chip->ds->rtable[target];

		err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
		if (err)
			return err;
	}

1146 1147 1148 1149 1150 1151 1152
	if (chip->info->ops->set_cascade_port) {
		port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
		err = chip->info->ops->set_cascade_port(chip, port);
		if (err)
			return err;
	}

1153 1154 1155 1156
	err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
	if (err)
		return err;

1157 1158 1159
	return 0;
}

1160 1161 1162 1163 1164 1165 1166 1167 1168
static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
{
	/* Clear all trunk masks and mapping */
	if (chip->info->global2_addr)
		return mv88e6xxx_g2_trunk_clear(chip);

	return 0;
}

1169 1170 1171 1172 1173 1174 1175 1176
static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->rmu_disable)
		return chip->info->ops->rmu_disable(chip);

	return 0;
}

1177 1178 1179 1180 1181 1182 1183 1184
static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->pot_clear)
		return chip->info->ops->pot_clear(chip);

	return 0;
}

1185 1186 1187 1188 1189 1190 1191 1192
static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->mgmt_rsvd2cpu)
		return chip->info->ops->mgmt_rsvd2cpu(chip);

	return 0;
}

1193 1194
static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
{
1195 1196
	int err;

1197 1198 1199 1200
	err = mv88e6xxx_g1_atu_flush(chip, 0, true);
	if (err)
		return err;

1201 1202 1203 1204
	err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
	if (err)
		return err;

1205 1206 1207
	return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
}

1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227
static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
{
	int port;
	int err;

	if (!chip->info->ops->irl_init_all)
		return 0;

	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
		/* Disable ingress rate limiting by resetting all per port
		 * ingress rate limit resources to their initial state.
		 */
		err = chip->info->ops->irl_init_all(chip, port);
		if (err)
			return err;
	}

	return 0;
}

1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240
static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->set_switch_mac) {
		u8 addr[ETH_ALEN];

		eth_random_addr(addr);

		return chip->info->ops->set_switch_mac(chip, addr);
	}

	return 0;
}

1241 1242 1243 1244 1245 1246 1247 1248 1249
static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
{
	u16 pvlan = 0;

	if (!mv88e6xxx_has_pvt(chip))
		return -EOPNOTSUPP;

	/* Skip the local source device, which uses in-chip port VLAN */
	if (dev != chip->ds->index)
1250
		pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1251 1252 1253 1254

	return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
}

1255 1256
static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
{
1257 1258 1259
	int dev, port;
	int err;

1260 1261 1262 1263 1264 1265
	if (!mv88e6xxx_has_pvt(chip))
		return 0;

	/* Clear 5 Bit Port for usage with Marvell Link Street devices:
	 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
	 */
1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278
	err = mv88e6xxx_g2_misc_4_bit_port(chip);
	if (err)
		return err;

	for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
		for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
			err = mv88e6xxx_pvt_map(chip, dev, port);
			if (err)
				return err;
		}
	}

	return 0;
1279 1280
}

1281 1282 1283 1284 1285 1286
static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int err;

	mutex_lock(&chip->reg_lock);
1287
	err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
1288 1289 1290
	mutex_unlock(&chip->reg_lock);

	if (err)
1291
		dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
1292 1293
}

1294 1295 1296 1297 1298 1299 1300 1301
static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
{
	if (!chip->info->max_vid)
		return 0;

	return mv88e6xxx_g1_vtu_flush(chip);
}

1302 1303 1304 1305 1306 1307 1308 1309 1310
static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
				 struct mv88e6xxx_vtu_entry *entry)
{
	if (!chip->info->ops->vtu_getnext)
		return -EOPNOTSUPP;

	return chip->info->ops->vtu_getnext(chip, entry);
}

1311 1312 1313 1314 1315 1316 1317 1318 1319
static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
				   struct mv88e6xxx_vtu_entry *entry)
{
	if (!chip->info->ops->vtu_loadpurge)
		return -EOPNOTSUPP;

	return chip->info->ops->vtu_loadpurge(chip, entry);
}

1320
static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1321 1322
{
	DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1323 1324 1325
	struct mv88e6xxx_vtu_entry vlan = {
		.vid = chip->info->max_vid,
	};
1326
	int i, err;
1327 1328 1329

	bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);

1330
	/* Set every FID bit used by the (un)bridged ports */
1331
	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1332
		err = mv88e6xxx_port_get_fid(chip, i, fid);
1333 1334 1335 1336 1337 1338
		if (err)
			return err;

		set_bit(*fid, fid_bitmap);
	}

1339 1340
	/* Set every FID bit used by the VLAN entries */
	do {
1341
		err = mv88e6xxx_vtu_getnext(chip, &vlan);
1342 1343 1344 1345 1346 1347 1348
		if (err)
			return err;

		if (!vlan.valid)
			break;

		set_bit(vlan.fid, fid_bitmap);
1349
	} while (vlan.vid < chip->info->max_vid);
1350 1351 1352 1353 1354

	/* The reset value 0x000 is used to indicate that multiple address
	 * databases are not needed. Return the next positive available.
	 */
	*fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1355
	if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1356 1357 1358
		return -ENOSPC;

	/* Clear the database */
1359
	return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1360 1361
}

1362 1363
static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
			     struct mv88e6xxx_vtu_entry *entry, bool new)
1364 1365 1366 1367 1368 1369
{
	int err;

	if (!vid)
		return -EINVAL;

1370 1371
	entry->vid = vid - 1;
	entry->valid = false;
1372

1373
	err = mv88e6xxx_vtu_getnext(chip, entry);
1374 1375 1376
	if (err)
		return err;

1377 1378
	if (entry->vid == vid && entry->valid)
		return 0;
1379

1380 1381 1382 1383 1384 1385 1386 1387
	if (new) {
		int i;

		/* Initialize a fresh VLAN entry */
		memset(entry, 0, sizeof(*entry));
		entry->valid = true;
		entry->vid = vid;

1388
		/* Exclude all ports */
1389
		for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1390
			entry->member[i] =
1391
				MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1392 1393

		return mv88e6xxx_atu_new(chip, &entry->fid);
1394 1395
	}

1396 1397
	/* switchdev expects -EOPNOTSUPP to honor software VLANs */
	return -EOPNOTSUPP;
1398 1399
}

1400 1401 1402
static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
					u16 vid_begin, u16 vid_end)
{
V
Vivien Didelot 已提交
1403
	struct mv88e6xxx_chip *chip = ds->priv;
1404 1405 1406
	struct mv88e6xxx_vtu_entry vlan = {
		.vid = vid_begin - 1,
	};
1407 1408
	int i, err;

1409 1410 1411 1412
	/* DSA and CPU ports have to be members of multiple vlans */
	if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
		return 0;

1413 1414 1415
	if (!vid_begin)
		return -EOPNOTSUPP;

1416
	mutex_lock(&chip->reg_lock);
1417 1418

	do {
1419
		err = mv88e6xxx_vtu_getnext(chip, &vlan);
1420 1421 1422 1423 1424 1425 1426 1427 1428
		if (err)
			goto unlock;

		if (!vlan.valid)
			break;

		if (vlan.vid > vid_end)
			break;

1429
		for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1430 1431 1432
			if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
				continue;

1433
			if (!ds->ports[i].slave)
1434 1435
				continue;

1436
			if (vlan.member[i] ==
1437
			    MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1438 1439
				continue;

V
Vivien Didelot 已提交
1440
			if (dsa_to_port(ds, i)->bridge_dev ==
1441
			    ds->ports[port].bridge_dev)
1442 1443
				break; /* same bridge, check next VLAN */

V
Vivien Didelot 已提交
1444
			if (!dsa_to_port(ds, i)->bridge_dev)
1445 1446
				continue;

1447 1448
			dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
				port, vlan.vid, i,
V
Vivien Didelot 已提交
1449
				netdev_name(dsa_to_port(ds, i)->bridge_dev));
1450 1451 1452 1453 1454 1455
			err = -EOPNOTSUPP;
			goto unlock;
		}
	} while (vlan.vid < vid_end);

unlock:
1456
	mutex_unlock(&chip->reg_lock);
1457 1458 1459 1460

	return err;
}

1461 1462
static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
					 bool vlan_filtering)
1463
{
V
Vivien Didelot 已提交
1464
	struct mv88e6xxx_chip *chip = ds->priv;
1465 1466
	u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
		MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1467
	int err;
1468

1469
	if (!chip->info->max_vid)
1470 1471
		return -EOPNOTSUPP;

1472
	mutex_lock(&chip->reg_lock);
1473
	err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1474
	mutex_unlock(&chip->reg_lock);
1475

1476
	return err;
1477 1478
}

1479 1480
static int
mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1481
			    const struct switchdev_obj_port_vlan *vlan)
1482
{
V
Vivien Didelot 已提交
1483
	struct mv88e6xxx_chip *chip = ds->priv;
1484 1485
	int err;

1486
	if (!chip->info->max_vid)
1487 1488
		return -EOPNOTSUPP;

1489 1490 1491 1492 1493 1494 1495 1496
	/* If the requested port doesn't belong to the same bridge as the VLAN
	 * members, do not support it (yet) and fallback to software VLAN.
	 */
	err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
					   vlan->vid_end);
	if (err)
		return err;

1497 1498 1499 1500 1501 1502
	/* We don't need any dynamic resource from the kernel (yet),
	 * so skip the prepare phase.
	 */
	return 0;
}

1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546
static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
					const unsigned char *addr, u16 vid,
					u8 state)
{
	struct mv88e6xxx_vtu_entry vlan;
	struct mv88e6xxx_atu_entry entry;
	int err;

	/* Null VLAN ID corresponds to the port private database */
	if (vid == 0)
		err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
	else
		err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
	if (err)
		return err;

	entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
	ether_addr_copy(entry.mac, addr);
	eth_addr_dec(entry.mac);

	err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
	if (err)
		return err;

	/* Initialize a fresh ATU entry if it isn't found */
	if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED ||
	    !ether_addr_equal(entry.mac, addr)) {
		memset(&entry, 0, sizeof(entry));
		ether_addr_copy(entry.mac, addr);
	}

	/* Purge the ATU entry only if no port is using it anymore */
	if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
		entry.portvec &= ~BIT(port);
		if (!entry.portvec)
			entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
	} else {
		entry.portvec |= BIT(port);
		entry.state = state;
	}

	return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
}

1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569
static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
					u16 vid)
{
	const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
	u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;

	return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
}

static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
{
	int port;
	int err;

	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
		err = mv88e6xxx_port_add_broadcast(chip, port, vid);
		if (err)
			return err;
	}

	return 0;
}

1570
static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1571
				    u16 vid, u8 member)
1572
{
1573
	struct mv88e6xxx_vtu_entry vlan;
1574 1575
	int err;

1576
	err = mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1577
	if (err)
1578
		return err;
1579

1580
	vlan.member[port] = member;
1581

1582 1583 1584 1585 1586
	err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
	if (err)
		return err;

	return mv88e6xxx_broadcast_setup(chip, vid);
1587 1588
}

1589
static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1590
				    const struct switchdev_obj_port_vlan *vlan)
1591
{
V
Vivien Didelot 已提交
1592
	struct mv88e6xxx_chip *chip = ds->priv;
1593 1594
	bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
	bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1595
	u8 member;
1596 1597
	u16 vid;

1598
	if (!chip->info->max_vid)
1599 1600
		return;

1601
	if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1602
		member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
1603
	else if (untagged)
1604
		member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
1605
	else
1606
		member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
1607

1608
	mutex_lock(&chip->reg_lock);
1609

1610
	for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1611
		if (_mv88e6xxx_port_vlan_add(chip, port, vid, member))
1612 1613
			dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
				vid, untagged ? 'u' : 't');
1614

1615
	if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
1616 1617
		dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
			vlan->vid_end);
1618

1619
	mutex_unlock(&chip->reg_lock);
1620 1621
}

1622
static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1623
				    int port, u16 vid)
1624
{
1625
	struct mv88e6xxx_vtu_entry vlan;
1626 1627
	int i, err;

1628
	err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1629
	if (err)
1630
		return err;
1631

1632
	/* Tell switchdev if this VLAN is handled in software */
1633
	if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1634
		return -EOPNOTSUPP;
1635

1636
	vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1637 1638

	/* keep the VLAN unless all ports are excluded */
1639
	vlan.valid = false;
1640
	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1641 1642
		if (vlan.member[i] !=
		    MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1643
			vlan.valid = true;
1644 1645 1646 1647
			break;
		}
	}

1648
	err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1649 1650 1651
	if (err)
		return err;

1652
	return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
1653 1654
}

1655 1656
static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
				   const struct switchdev_obj_port_vlan *vlan)
1657
{
V
Vivien Didelot 已提交
1658
	struct mv88e6xxx_chip *chip = ds->priv;
1659 1660 1661
	u16 pvid, vid;
	int err = 0;

1662
	if (!chip->info->max_vid)
1663 1664
		return -EOPNOTSUPP;

1665
	mutex_lock(&chip->reg_lock);
1666

1667
	err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1668 1669 1670
	if (err)
		goto unlock;

1671
	for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1672
		err = _mv88e6xxx_port_vlan_del(chip, port, vid);
1673 1674 1675 1676
		if (err)
			goto unlock;

		if (vid == pvid) {
1677
			err = mv88e6xxx_port_set_pvid(chip, port, 0);
1678 1679 1680 1681 1682
			if (err)
				goto unlock;
		}
	}

1683
unlock:
1684
	mutex_unlock(&chip->reg_lock);
1685 1686 1687 1688

	return err;
}

1689 1690
static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
				  const unsigned char *addr, u16 vid)
1691
{
V
Vivien Didelot 已提交
1692
	struct mv88e6xxx_chip *chip = ds->priv;
1693
	int err;
1694

1695
	mutex_lock(&chip->reg_lock);
1696 1697
	err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
					   MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1698
	mutex_unlock(&chip->reg_lock);
1699 1700

	return err;
1701 1702
}

1703
static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1704
				  const unsigned char *addr, u16 vid)
1705
{
V
Vivien Didelot 已提交
1706
	struct mv88e6xxx_chip *chip = ds->priv;
1707
	int err;
1708

1709
	mutex_lock(&chip->reg_lock);
1710
	err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1711
					   MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
1712
	mutex_unlock(&chip->reg_lock);
1713

1714
	return err;
1715 1716
}

1717 1718
static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
				      u16 fid, u16 vid, int port,
1719
				      dsa_fdb_dump_cb_t *cb, void *data)
1720
{
1721
	struct mv88e6xxx_atu_entry addr;
1722
	bool is_static;
1723 1724
	int err;

1725
	addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1726
	eth_broadcast_addr(addr.mac);
1727 1728

	do {
1729
		mutex_lock(&chip->reg_lock);
1730
		err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
1731
		mutex_unlock(&chip->reg_lock);
1732
		if (err)
1733
			return err;
1734

1735
		if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED)
1736 1737
			break;

1738
		if (addr.trunk || (addr.portvec & BIT(port)) == 0)
1739 1740
			continue;

1741 1742
		if (!is_unicast_ether_addr(addr.mac))
			continue;
1743

1744 1745 1746
		is_static = (addr.state ==
			     MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
		err = cb(addr.mac, vid, is_static, data);
1747 1748
		if (err)
			return err;
1749 1750 1751 1752 1753
	} while (!is_broadcast_ether_addr(addr.mac));

	return err;
}

1754
static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
1755
				  dsa_fdb_dump_cb_t *cb, void *data)
1756
{
1757
	struct mv88e6xxx_vtu_entry vlan = {
1758
		.vid = chip->info->max_vid,
1759
	};
1760
	u16 fid;
1761 1762
	int err;

1763
	/* Dump port's default Filtering Information Database (VLAN ID 0) */
1764
	mutex_lock(&chip->reg_lock);
1765
	err = mv88e6xxx_port_get_fid(chip, port, &fid);
1766 1767
	mutex_unlock(&chip->reg_lock);

1768
	if (err)
1769
		return err;
1770

1771
	err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
1772
	if (err)
1773
		return err;
1774

1775
	/* Dump VLANs' Filtering Information Databases */
1776
	do {
1777
		mutex_lock(&chip->reg_lock);
1778
		err = mv88e6xxx_vtu_getnext(chip, &vlan);
1779
		mutex_unlock(&chip->reg_lock);
1780
		if (err)
1781
			return err;
1782 1783 1784 1785

		if (!vlan.valid)
			break;

1786
		err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
1787
						 cb, data);
1788
		if (err)
1789
			return err;
1790
	} while (vlan.vid < chip->info->max_vid);
1791

1792 1793 1794 1795
	return err;
}

static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
1796
				   dsa_fdb_dump_cb_t *cb, void *data)
1797
{
V
Vivien Didelot 已提交
1798
	struct mv88e6xxx_chip *chip = ds->priv;
1799

1800
	return mv88e6xxx_port_db_dump(chip, port, cb, data);
1801 1802
}

1803 1804
static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
				struct net_device *br)
1805
{
1806
	struct dsa_switch *ds;
1807
	int port;
1808
	int dev;
1809
	int err;
1810

1811 1812 1813 1814
	/* Remap the Port VLAN of each local bridge group member */
	for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
		if (chip->ds->ports[port].bridge_dev == br) {
			err = mv88e6xxx_port_vlan_map(chip, port);
1815
			if (err)
1816
				return err;
1817 1818 1819
		}
	}

1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837
	if (!mv88e6xxx_has_pvt(chip))
		return 0;

	/* Remap the Port VLAN of each cross-chip bridge group member */
	for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) {
		ds = chip->ds->dst->ds[dev];
		if (!ds)
			break;

		for (port = 0; port < ds->num_ports; ++port) {
			if (ds->ports[port].bridge_dev == br) {
				err = mv88e6xxx_pvt_map(chip, dev, port);
				if (err)
					return err;
			}
		}
	}

1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848
	return 0;
}

static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
				      struct net_device *br)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int err;

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_bridge_map(chip, br);
1849
	mutex_unlock(&chip->reg_lock);
1850

1851
	return err;
1852 1853
}

1854 1855
static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
					struct net_device *br)
1856
{
V
Vivien Didelot 已提交
1857
	struct mv88e6xxx_chip *chip = ds->priv;
1858

1859
	mutex_lock(&chip->reg_lock);
1860 1861 1862
	if (mv88e6xxx_bridge_map(chip, br) ||
	    mv88e6xxx_port_vlan_map(chip, port))
		dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
1863
	mutex_unlock(&chip->reg_lock);
1864 1865
}

1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895
static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
					   int port, struct net_device *br)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int err;

	if (!mv88e6xxx_has_pvt(chip))
		return 0;

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_pvt_map(chip, dev, port);
	mutex_unlock(&chip->reg_lock);

	return err;
}

static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
					     int port, struct net_device *br)
{
	struct mv88e6xxx_chip *chip = ds->priv;

	if (!mv88e6xxx_has_pvt(chip))
		return;

	mutex_lock(&chip->reg_lock);
	if (mv88e6xxx_pvt_map(chip, dev, port))
		dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
	mutex_unlock(&chip->reg_lock);
}

1896 1897 1898 1899 1900 1901 1902 1903
static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->reset)
		return chip->info->ops->reset(chip);

	return 0;
}

1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916
static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
{
	struct gpio_desc *gpiod = chip->reset;

	/* If there is a GPIO connected to the reset pin, toggle it */
	if (gpiod) {
		gpiod_set_value_cansleep(gpiod, 1);
		usleep_range(10000, 20000);
		gpiod_set_value_cansleep(gpiod, 0);
		usleep_range(10000, 20000);
	}
}

1917
static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
1918
{
1919
	int i, err;
1920

1921
	/* Set all ports to the Disabled state */
1922
	for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
1923
		err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
1924 1925
		if (err)
			return err;
1926 1927
	}

1928 1929 1930
	/* Wait for transmit queues to drain,
	 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
	 */
1931 1932
	usleep_range(2000, 4000);

1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943
	return 0;
}

static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
{
	int err;

	err = mv88e6xxx_disable_ports(chip);
	if (err)
		return err;

1944
	mv88e6xxx_hardware_reset(chip);
1945

1946
	return mv88e6xxx_software_reset(chip);
1947 1948
}

1949
static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
1950 1951
				   enum mv88e6xxx_frame_mode frame,
				   enum mv88e6xxx_egress_mode egress, u16 etype)
1952 1953 1954
{
	int err;

1955 1956 1957 1958
	if (!chip->info->ops->port_set_frame_mode)
		return -EOPNOTSUPP;

	err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
1959 1960 1961
	if (err)
		return err;

1962 1963 1964 1965 1966 1967 1968 1969
	err = chip->info->ops->port_set_frame_mode(chip, port, frame);
	if (err)
		return err;

	if (chip->info->ops->port_set_ether_type)
		return chip->info->ops->port_set_ether_type(chip, port, etype);

	return 0;
1970 1971
}

1972
static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
1973
{
1974
	return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
1975
				       MV88E6XXX_EGRESS_MODE_UNMODIFIED,
1976
				       MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
1977
}
1978

1979 1980 1981
static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
{
	return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
1982
				       MV88E6XXX_EGRESS_MODE_UNMODIFIED,
1983
				       MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
1984
}
1985

1986 1987 1988 1989
static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
{
	return mv88e6xxx_set_port_mode(chip, port,
				       MV88E6XXX_FRAME_MODE_ETHERTYPE,
1990 1991
				       MV88E6XXX_EGRESS_MODE_ETHERTYPE,
				       ETH_P_EDSA);
1992
}
1993

1994 1995 1996 1997
static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
{
	if (dsa_is_dsa_port(chip->ds, port))
		return mv88e6xxx_set_port_mode_dsa(chip, port);
1998

1999
	if (dsa_is_user_port(chip->ds, port))
2000
		return mv88e6xxx_set_port_mode_normal(chip, port);
2001

2002 2003 2004
	/* Setup CPU port mode depending on its supported tag format */
	if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
		return mv88e6xxx_set_port_mode_dsa(chip, port);
2005

2006 2007
	if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
		return mv88e6xxx_set_port_mode_edsa(chip, port);
2008

2009
	return -EINVAL;
2010 2011
}

2012
static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
2013
{
2014
	bool message = dsa_is_dsa_port(chip->ds, port);
2015

2016
	return mv88e6xxx_port_set_message_port(chip, port, message);
2017
}
2018

2019
static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
2020
{
2021 2022
	struct dsa_switch *ds = chip->ds;
	bool flood;
2023

2024
	/* Upstream ports flood frames with unknown unicast or multicast DA */
2025
	flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port);
2026 2027 2028
	if (chip->info->ops->port_set_egress_floods)
		return chip->info->ops->port_set_egress_floods(chip, port,
							       flood, flood);
2029

2030
	return 0;
2031 2032
}

2033 2034 2035
static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
				  bool on)
{
2036 2037
	if (chip->info->ops->serdes_power)
		return chip->info->ops->serdes_power(chip, port, on);
2038

2039
	return 0;
2040 2041
}

2042 2043 2044 2045 2046 2047
static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
{
	struct dsa_switch *ds = chip->ds;
	int upstream_port;
	int err;

2048
	upstream_port = dsa_upstream_port(ds, port);
2049 2050 2051 2052 2053 2054 2055
	if (chip->info->ops->port_set_upstream_port) {
		err = chip->info->ops->port_set_upstream_port(chip, port,
							      upstream_port);
		if (err)
			return err;
	}

2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071
	if (port == upstream_port) {
		if (chip->info->ops->set_cpu_port) {
			err = chip->info->ops->set_cpu_port(chip,
							    upstream_port);
			if (err)
				return err;
		}

		if (chip->info->ops->set_egress_port) {
			err = chip->info->ops->set_egress_port(chip,
							       upstream_port);
			if (err)
				return err;
		}
	}

2072 2073 2074
	return 0;
}

2075
static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2076
{
2077
	struct dsa_switch *ds = chip->ds;
2078
	int err;
2079
	u16 reg;
2080

2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094
	/* MAC Forcing register: don't force link, speed, duplex or flow control
	 * state to any particular values on physical ports, but force the CPU
	 * port and all DSA ports to their maximum bandwidth and full duplex.
	 */
	if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
		err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
					       SPEED_MAX, DUPLEX_FULL,
					       PHY_INTERFACE_MODE_NA);
	else
		err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
					       SPEED_UNFORCED, DUPLEX_UNFORCED,
					       PHY_INTERFACE_MODE_NA);
	if (err)
		return err;
2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109

	/* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
	 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
	 * tunneling, determine priority by looking at 802.1p and IP
	 * priority fields (IP prio has precedence), and set STP state
	 * to Forwarding.
	 *
	 * If this is the CPU link, use DSA or EDSA tagging depending
	 * on which tagging mode was configured.
	 *
	 * If this is a link to another switch, use DSA tagging mode.
	 *
	 * If this is the upstream port for this switch, enable
	 * forwarding of unknown unicasts and multicasts.
	 */
2110 2111 2112 2113
	reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
		MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
		MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
2114 2115
	if (err)
		return err;
2116

2117
	err = mv88e6xxx_setup_port_mode(chip, port);
2118 2119
	if (err)
		return err;
2120

2121
	err = mv88e6xxx_setup_egress_floods(chip, port);
2122 2123 2124
	if (err)
		return err;

2125 2126 2127
	/* Enable the SERDES interface for DSA and CPU ports. Normal
	 * ports SERDES are enabled when the port is enabled, thus
	 * saving a bit of power.
2128
	 */
2129 2130 2131 2132 2133
	if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) {
		err = mv88e6xxx_serdes_power(chip, port, true);
		if (err)
			return err;
	}
2134

2135
	/* Port Control 2: don't force a good FCS, set the maximum frame size to
2136
	 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2137 2138 2139
	 * untagged frames on this port, do a destination address lookup on all
	 * received packets as usual, disable ARP mirroring and don't send a
	 * copy of all transmitted/received frames on this port to the CPU.
2140
	 */
2141 2142 2143
	err = mv88e6xxx_port_set_map_da(chip, port);
	if (err)
		return err;
2144

2145 2146 2147
	err = mv88e6xxx_setup_upstream_port(chip, port);
	if (err)
		return err;
2148

2149
	err = mv88e6xxx_port_set_8021q_mode(chip, port,
2150
				MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
2151 2152 2153
	if (err)
		return err;

2154 2155
	if (chip->info->ops->port_set_jumbo_size) {
		err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
2156 2157 2158 2159
		if (err)
			return err;
	}

2160 2161 2162 2163 2164
	/* Port Association Vector: when learning source addresses
	 * of packets, add the address to the address database using
	 * a port bitmap that has only the bit for this port set and
	 * the other bits clear.
	 */
2165
	reg = 1 << port;
2166 2167
	/* Disable learning for CPU port */
	if (dsa_is_cpu_port(ds, port))
2168
		reg = 0;
2169

2170 2171
	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
				   reg);
2172 2173
	if (err)
		return err;
2174 2175

	/* Egress rate control 2: disable egress rate control. */
2176 2177
	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
				   0x0000);
2178 2179
	if (err)
		return err;
2180

2181 2182
	if (chip->info->ops->port_pause_limit) {
		err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
2183 2184
		if (err)
			return err;
2185
	}
2186

2187 2188 2189 2190 2191 2192
	if (chip->info->ops->port_disable_learn_limit) {
		err = chip->info->ops->port_disable_learn_limit(chip, port);
		if (err)
			return err;
	}

2193 2194
	if (chip->info->ops->port_disable_pri_override) {
		err = chip->info->ops->port_disable_pri_override(chip, port);
2195 2196
		if (err)
			return err;
2197
	}
2198

2199 2200
	if (chip->info->ops->port_tag_remap) {
		err = chip->info->ops->port_tag_remap(chip, port);
2201 2202
		if (err)
			return err;
2203 2204
	}

2205 2206
	if (chip->info->ops->port_egress_rate_limiting) {
		err = chip->info->ops->port_egress_rate_limiting(chip, port);
2207 2208
		if (err)
			return err;
2209 2210
	}

2211
	err = mv88e6xxx_setup_message_port(chip, port);
2212 2213
	if (err)
		return err;
2214

2215
	/* Port based VLAN map: give each port the same default address
2216 2217
	 * database, and allow bidirectional communication between the
	 * CPU and DSA port(s), and the other ports.
2218
	 */
2219
	err = mv88e6xxx_port_set_fid(chip, port, 0);
2220 2221
	if (err)
		return err;
2222

2223
	err = mv88e6xxx_port_vlan_map(chip, port);
2224 2225
	if (err)
		return err;
2226 2227 2228 2229

	/* Default VLAN ID and priority: don't set a default VLAN
	 * ID, and set the default packet priority to zero.
	 */
2230
	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
2231 2232
}

2233 2234 2235 2236
static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
				 struct phy_device *phydev)
{
	struct mv88e6xxx_chip *chip = ds->priv;
2237
	int err;
2238 2239

	mutex_lock(&chip->reg_lock);
2240
	err = mv88e6xxx_serdes_power(chip, port, true);
2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251
	mutex_unlock(&chip->reg_lock);

	return err;
}

static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port,
				   struct phy_device *phydev)
{
	struct mv88e6xxx_chip *chip = ds->priv;

	mutex_lock(&chip->reg_lock);
2252 2253
	if (mv88e6xxx_serdes_power(chip, port, false))
		dev_err(chip->dev, "failed to power off SERDES\n");
2254 2255 2256
	mutex_unlock(&chip->reg_lock);
}

2257 2258 2259
static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
				     unsigned int ageing_time)
{
V
Vivien Didelot 已提交
2260
	struct mv88e6xxx_chip *chip = ds->priv;
2261 2262 2263
	int err;

	mutex_lock(&chip->reg_lock);
2264
	err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2265 2266 2267 2268 2269
	mutex_unlock(&chip->reg_lock);

	return err;
}

2270
static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
2271
{
2272
	int err;
2273

2274 2275 2276 2277 2278
	/* Initialize the statistics unit */
	err = mv88e6xxx_stats_set_histogram(chip);
	if (err)
		return err;

2279
	return mv88e6xxx_g1_stats_clear(chip);
2280 2281
}

2282
static int mv88e6xxx_setup(struct dsa_switch *ds)
2283
{
V
Vivien Didelot 已提交
2284
	struct mv88e6xxx_chip *chip = ds->priv;
2285
	int err;
2286 2287
	int i;

2288
	chip->ds = ds;
2289
	ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
2290

2291
	mutex_lock(&chip->reg_lock);
2292

2293
	/* Setup Switch Port Registers */
2294
	for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2295 2296 2297
		if (dsa_is_unused_port(ds, i))
			continue;

2298 2299 2300 2301 2302 2303 2304
		err = mv88e6xxx_setup_port(chip, i);
		if (err)
			goto unlock;
	}

	/* Setup Switch Global 1 Registers */
	err = mv88e6xxx_g1_setup(chip);
2305 2306 2307
	if (err)
		goto unlock;

2308 2309 2310 2311
	err = mv88e6xxx_irl_setup(chip);
	if (err)
		goto unlock;

2312 2313 2314 2315
	err = mv88e6xxx_mac_setup(chip);
	if (err)
		goto unlock;

2316 2317 2318 2319
	err = mv88e6xxx_phy_setup(chip);
	if (err)
		goto unlock;

2320 2321 2322 2323
	err = mv88e6xxx_vtu_setup(chip);
	if (err)
		goto unlock;

2324 2325 2326 2327
	err = mv88e6xxx_pvt_setup(chip);
	if (err)
		goto unlock;

2328 2329 2330 2331
	err = mv88e6xxx_atu_setup(chip);
	if (err)
		goto unlock;

2332 2333 2334 2335
	err = mv88e6xxx_broadcast_setup(chip, 0);
	if (err)
		goto unlock;

2336 2337 2338 2339
	err = mv88e6xxx_pot_setup(chip);
	if (err)
		goto unlock;

2340 2341 2342 2343
	err = mv88e6xxx_rmu_setup(chip);
	if (err)
		goto unlock;

2344 2345 2346
	err = mv88e6xxx_rsvd2cpu_setup(chip);
	if (err)
		goto unlock;
2347

2348 2349 2350 2351
	err = mv88e6xxx_trunk_setup(chip);
	if (err)
		goto unlock;

2352 2353 2354 2355
	err = mv88e6xxx_devmap_setup(chip);
	if (err)
		goto unlock;

2356 2357 2358 2359
	err = mv88e6xxx_pri_setup(chip);
	if (err)
		goto unlock;

2360
	/* Setup PTP Hardware Clock and timestamping */
2361 2362 2363 2364
	if (chip->info->ptp_support) {
		err = mv88e6xxx_ptp_setup(chip);
		if (err)
			goto unlock;
2365 2366 2367 2368

		err = mv88e6xxx_hwtstamp_setup(chip);
		if (err)
			goto unlock;
2369 2370
	}

2371
unlock:
2372
	mutex_unlock(&chip->reg_lock);
2373

2374
	return err;
2375 2376
}

2377
static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
2378
{
2379 2380
	struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
	struct mv88e6xxx_chip *chip = mdio_bus->chip;
2381 2382
	u16 val;
	int err;
2383

2384 2385 2386
	if (!chip->info->ops->phy_read)
		return -EOPNOTSUPP;

2387
	mutex_lock(&chip->reg_lock);
2388
	err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
2389
	mutex_unlock(&chip->reg_lock);
2390

2391 2392 2393 2394 2395
	if (reg == MII_PHYSID2) {
		/* Some internal PHYS don't have a model number.  Use
		 * the mv88e6390 family model number instead.
		 */
		if (!(val & 0x3f0))
2396
			val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
2397 2398
	}

2399
	return err ? err : val;
2400 2401
}

2402
static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
2403
{
2404 2405
	struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
	struct mv88e6xxx_chip *chip = mdio_bus->chip;
2406
	int err;
2407

2408 2409 2410
	if (!chip->info->ops->phy_write)
		return -EOPNOTSUPP;

2411
	mutex_lock(&chip->reg_lock);
2412
	err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
2413
	mutex_unlock(&chip->reg_lock);
2414 2415

	return err;
2416 2417
}

2418
static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
2419 2420
				   struct device_node *np,
				   bool external)
2421 2422
{
	static int index;
2423
	struct mv88e6xxx_mdio_bus *mdio_bus;
2424 2425 2426
	struct mii_bus *bus;
	int err;

2427 2428 2429 2430 2431 2432 2433 2434 2435
	if (external) {
		mutex_lock(&chip->reg_lock);
		err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
		mutex_unlock(&chip->reg_lock);

		if (err)
			return err;
	}

2436
	bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
2437 2438 2439
	if (!bus)
		return -ENOMEM;

2440
	mdio_bus = bus->priv;
2441
	mdio_bus->bus = bus;
2442
	mdio_bus->chip = chip;
2443 2444
	INIT_LIST_HEAD(&mdio_bus->list);
	mdio_bus->external = external;
2445

2446 2447
	if (np) {
		bus->name = np->full_name;
2448
		snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
2449 2450 2451 2452 2453 2454 2455
	} else {
		bus->name = "mv88e6xxx SMI";
		snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
	}

	bus->read = mv88e6xxx_mdio_read;
	bus->write = mv88e6xxx_mdio_write;
2456
	bus->parent = chip->dev;
2457

2458 2459 2460 2461 2462 2463
	if (!external) {
		err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
		if (err)
			return err;
	}

2464 2465
	if (np)
		err = of_mdiobus_register(bus, np);
2466 2467 2468
	else
		err = mdiobus_register(bus);
	if (err) {
2469
		dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
2470
		mv88e6xxx_g2_irq_mdio_free(chip, bus);
2471
		return err;
2472
	}
2473 2474 2475 2476 2477

	if (external)
		list_add_tail(&mdio_bus->list, &chip->mdios);
	else
		list_add(&mdio_bus->list, &chip->mdios);
2478 2479

	return 0;
2480
}
2481

2482 2483 2484 2485 2486
static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
	{ .compatible = "marvell,mv88e6xxx-mdio-external",
	  .data = (void *)true },
	{ },
};
2487

2488 2489 2490 2491 2492 2493 2494 2495 2496
static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)

{
	struct mv88e6xxx_mdio_bus *mdio_bus;
	struct mii_bus *bus;

	list_for_each_entry(mdio_bus, &chip->mdios, list) {
		bus = mdio_bus->bus;

2497 2498 2499
		if (!mdio_bus->external)
			mv88e6xxx_g2_irq_mdio_free(chip, bus);

2500 2501 2502 2503
		mdiobus_unregister(bus);
	}
}

2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527
static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
				    struct device_node *np)
{
	const struct of_device_id *match;
	struct device_node *child;
	int err;

	/* Always register one mdio bus for the internal/default mdio
	 * bus. This maybe represented in the device tree, but is
	 * optional.
	 */
	child = of_get_child_by_name(np, "mdio");
	err = mv88e6xxx_mdio_register(chip, child, false);
	if (err)
		return err;

	/* Walk the device tree, and see if there are any other nodes
	 * which say they are compatible with the external mdio
	 * bus.
	 */
	for_each_available_child_of_node(np, child) {
		match = of_match_node(mv88e6xxx_mdio_external_match, child);
		if (match) {
			err = mv88e6xxx_mdio_register(chip, child, true);
2528 2529
			if (err) {
				mv88e6xxx_mdios_unregister(chip);
2530
				return err;
2531
			}
2532 2533 2534 2535
		}
	}

	return 0;
2536 2537
}

2538 2539
static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
{
V
Vivien Didelot 已提交
2540
	struct mv88e6xxx_chip *chip = ds->priv;
2541 2542 2543 2544 2545 2546 2547

	return chip->eeprom_len;
}

static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
				struct ethtool_eeprom *eeprom, u8 *data)
{
V
Vivien Didelot 已提交
2548
	struct mv88e6xxx_chip *chip = ds->priv;
2549 2550
	int err;

2551 2552
	if (!chip->info->ops->get_eeprom)
		return -EOPNOTSUPP;
2553

2554 2555
	mutex_lock(&chip->reg_lock);
	err = chip->info->ops->get_eeprom(chip, eeprom, data);
2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568
	mutex_unlock(&chip->reg_lock);

	if (err)
		return err;

	eeprom->magic = 0xc3ec4951;

	return 0;
}

static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
				struct ethtool_eeprom *eeprom, u8 *data)
{
V
Vivien Didelot 已提交
2569
	struct mv88e6xxx_chip *chip = ds->priv;
2570 2571
	int err;

2572 2573 2574
	if (!chip->info->ops->set_eeprom)
		return -EOPNOTSUPP;

2575 2576 2577 2578
	if (eeprom->magic != 0xc3ec4951)
		return -EINVAL;

	mutex_lock(&chip->reg_lock);
2579
	err = chip->info->ops->set_eeprom(chip, eeprom, data);
2580 2581 2582 2583 2584
	mutex_unlock(&chip->reg_lock);

	return err;
}

2585
static const struct mv88e6xxx_ops mv88e6085_ops = {
2586
	/* MV88E6XXX_FAMILY_6097 */
2587 2588
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2589
	.irl_init_all = mv88e6352_g2_irl_init_all,
2590
	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2591 2592
	.phy_read = mv88e6185_phy_ppu_read,
	.phy_write = mv88e6185_phy_ppu_write,
2593
	.port_set_link = mv88e6xxx_port_set_link,
2594
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2595
	.port_set_speed = mv88e6185_port_set_speed,
2596
	.port_tag_remap = mv88e6095_port_tag_remap,
2597
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2598
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2599
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2600
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2601
	.port_pause_limit = mv88e6097_port_pause_limit,
2602
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2603
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2604
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2605
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2606 2607
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2608
	.stats_get_stats = mv88e6095_stats_get_stats,
2609 2610
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2611
	.watchdog_ops = &mv88e6097_watchdog_ops,
2612
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2613
	.pot_clear = mv88e6xxx_g2_pot_clear,
2614 2615
	.ppu_enable = mv88e6185_g1_ppu_enable,
	.ppu_disable = mv88e6185_g1_ppu_disable,
2616
	.reset = mv88e6185_g1_reset,
2617
	.rmu_disable = mv88e6085_g1_rmu_disable,
2618
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2619
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2620
	.serdes_power = mv88e6341_serdes_power,
2621 2622 2623
};

static const struct mv88e6xxx_ops mv88e6095_ops = {
2624
	/* MV88E6XXX_FAMILY_6095 */
2625 2626
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2627
	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2628 2629
	.phy_read = mv88e6185_phy_ppu_read,
	.phy_write = mv88e6185_phy_ppu_write,
2630
	.port_set_link = mv88e6xxx_port_set_link,
2631
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2632
	.port_set_speed = mv88e6185_port_set_speed,
2633
	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
2634
	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
2635
	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
2636
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2637
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2638 2639
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2640
	.stats_get_stats = mv88e6095_stats_get_stats,
2641
	.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2642 2643
	.ppu_enable = mv88e6185_g1_ppu_enable,
	.ppu_disable = mv88e6185_g1_ppu_disable,
2644
	.reset = mv88e6185_g1_reset,
2645
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
2646
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2647 2648
};

2649
static const struct mv88e6xxx_ops mv88e6097_ops = {
2650
	/* MV88E6XXX_FAMILY_6097 */
2651 2652
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2653
	.irl_init_all = mv88e6352_g2_irl_init_all,
2654 2655 2656 2657 2658 2659
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_speed = mv88e6185_port_set_speed,
2660
	.port_tag_remap = mv88e6095_port_tag_remap,
2661
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2662
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2663
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2664
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2665
	.port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2666
	.port_pause_limit = mv88e6097_port_pause_limit,
2667
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2668
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2669
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2670
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2671 2672 2673
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
	.stats_get_stats = mv88e6095_stats_get_stats,
2674 2675
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2676
	.watchdog_ops = &mv88e6097_watchdog_ops,
2677
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2678
	.pot_clear = mv88e6xxx_g2_pot_clear,
2679
	.reset = mv88e6352_g1_reset,
2680
	.rmu_disable = mv88e6085_g1_rmu_disable,
2681
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2682
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2683 2684
};

2685
static const struct mv88e6xxx_ops mv88e6123_ops = {
2686
	/* MV88E6XXX_FAMILY_6165 */
2687 2688
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2689
	.irl_init_all = mv88e6352_g2_irl_init_all,
2690
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2691 2692
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2693
	.port_set_link = mv88e6xxx_port_set_link,
2694
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2695
	.port_set_speed = mv88e6185_port_set_speed,
2696
	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
2697
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2698
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2699
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2700
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2701
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2702 2703
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2704
	.stats_get_stats = mv88e6095_stats_get_stats,
2705 2706
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2707
	.watchdog_ops = &mv88e6097_watchdog_ops,
2708
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2709
	.pot_clear = mv88e6xxx_g2_pot_clear,
2710
	.reset = mv88e6352_g1_reset,
2711
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2712
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2713 2714 2715
};

static const struct mv88e6xxx_ops mv88e6131_ops = {
2716
	/* MV88E6XXX_FAMILY_6185 */
2717 2718
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2719
	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2720 2721
	.phy_read = mv88e6185_phy_ppu_read,
	.phy_write = mv88e6185_phy_ppu_write,
2722
	.port_set_link = mv88e6xxx_port_set_link,
2723
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2724
	.port_set_speed = mv88e6185_port_set_speed,
2725
	.port_tag_remap = mv88e6095_port_tag_remap,
2726
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2727
	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
2728
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2729
	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
2730
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2731
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2732
	.port_pause_limit = mv88e6097_port_pause_limit,
2733
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2734
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2735 2736
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2737
	.stats_get_stats = mv88e6095_stats_get_stats,
2738 2739
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2740
	.watchdog_ops = &mv88e6097_watchdog_ops,
2741
	.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2742
	.ppu_enable = mv88e6185_g1_ppu_enable,
2743
	.set_cascade_port = mv88e6185_g1_set_cascade_port,
2744
	.ppu_disable = mv88e6185_g1_ppu_disable,
2745
	.reset = mv88e6185_g1_reset,
2746
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
2747
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2748 2749
};

2750 2751
static const struct mv88e6xxx_ops mv88e6141_ops = {
	/* MV88E6XXX_FAMILY_6341 */
2752 2753
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2754
	.irl_init_all = mv88e6352_g2_irl_init_all,
2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
	.port_tag_remap = mv88e6095_port_tag_remap,
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2768
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2769
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2770
	.port_pause_limit = mv88e6097_port_pause_limit,
2771 2772 2773
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
2774
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2775 2776 2777
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
	.stats_get_stats = mv88e6390_stats_get_stats,
2778 2779
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
2780 2781
	.watchdog_ops = &mv88e6390_watchdog_ops,
	.mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
2782
	.pot_clear = mv88e6xxx_g2_pot_clear,
2783
	.reset = mv88e6352_g1_reset,
2784
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2785
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2786
	.gpio_ops = &mv88e6352_gpio_ops,
2787 2788
};

2789
static const struct mv88e6xxx_ops mv88e6161_ops = {
2790
	/* MV88E6XXX_FAMILY_6165 */
2791 2792
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2793
	.irl_init_all = mv88e6352_g2_irl_init_all,
2794
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2795 2796
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2797
	.port_set_link = mv88e6xxx_port_set_link,
2798
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2799
	.port_set_speed = mv88e6185_port_set_speed,
2800
	.port_tag_remap = mv88e6095_port_tag_remap,
2801
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2802
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2803
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2804
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2805
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2806
	.port_pause_limit = mv88e6097_port_pause_limit,
2807
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2808
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2809
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2810
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2811 2812
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2813
	.stats_get_stats = mv88e6095_stats_get_stats,
2814 2815
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2816
	.watchdog_ops = &mv88e6097_watchdog_ops,
2817
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2818
	.pot_clear = mv88e6xxx_g2_pot_clear,
2819
	.reset = mv88e6352_g1_reset,
2820
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2821
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2822 2823 2824
};

static const struct mv88e6xxx_ops mv88e6165_ops = {
2825
	/* MV88E6XXX_FAMILY_6165 */
2826 2827
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2828
	.irl_init_all = mv88e6352_g2_irl_init_all,
2829
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2830 2831
	.phy_read = mv88e6165_phy_read,
	.phy_write = mv88e6165_phy_write,
2832
	.port_set_link = mv88e6xxx_port_set_link,
2833
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2834
	.port_set_speed = mv88e6185_port_set_speed,
2835
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2836
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2837
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2838
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2839 2840
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2841
	.stats_get_stats = mv88e6095_stats_get_stats,
2842 2843
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2844
	.watchdog_ops = &mv88e6097_watchdog_ops,
2845
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2846
	.pot_clear = mv88e6xxx_g2_pot_clear,
2847
	.reset = mv88e6352_g1_reset,
2848
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2849
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2850 2851 2852
};

static const struct mv88e6xxx_ops mv88e6171_ops = {
2853
	/* MV88E6XXX_FAMILY_6351 */
2854 2855
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2856
	.irl_init_all = mv88e6352_g2_irl_init_all,
2857
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2858 2859
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2860
	.port_set_link = mv88e6xxx_port_set_link,
2861
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2862
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2863
	.port_set_speed = mv88e6185_port_set_speed,
2864
	.port_tag_remap = mv88e6095_port_tag_remap,
2865
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2866
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2867
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2868
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2869
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2870
	.port_pause_limit = mv88e6097_port_pause_limit,
2871
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2872
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2873
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2874
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2875 2876
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2877
	.stats_get_stats = mv88e6095_stats_get_stats,
2878 2879
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2880
	.watchdog_ops = &mv88e6097_watchdog_ops,
2881
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2882
	.pot_clear = mv88e6xxx_g2_pot_clear,
2883
	.reset = mv88e6352_g1_reset,
2884
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2885
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2886 2887 2888
};

static const struct mv88e6xxx_ops mv88e6172_ops = {
2889
	/* MV88E6XXX_FAMILY_6352 */
2890 2891
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2892
	.irl_init_all = mv88e6352_g2_irl_init_all,
2893 2894
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
2895
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2896 2897
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2898
	.port_set_link = mv88e6xxx_port_set_link,
2899
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2900
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2901
	.port_set_speed = mv88e6352_port_set_speed,
2902
	.port_tag_remap = mv88e6095_port_tag_remap,
2903
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2904
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2905
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2906
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2907
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2908
	.port_pause_limit = mv88e6097_port_pause_limit,
2909
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2910
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2911
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2912
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2913 2914
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2915
	.stats_get_stats = mv88e6095_stats_get_stats,
2916 2917
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2918
	.watchdog_ops = &mv88e6097_watchdog_ops,
2919
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2920
	.pot_clear = mv88e6xxx_g2_pot_clear,
2921
	.reset = mv88e6352_g1_reset,
2922
	.rmu_disable = mv88e6352_g1_rmu_disable,
2923
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2924
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2925
	.serdes_power = mv88e6352_serdes_power,
2926
	.gpio_ops = &mv88e6352_gpio_ops,
2927 2928 2929
};

static const struct mv88e6xxx_ops mv88e6175_ops = {
2930
	/* MV88E6XXX_FAMILY_6351 */
2931 2932
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2933
	.irl_init_all = mv88e6352_g2_irl_init_all,
2934
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2935 2936
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2937
	.port_set_link = mv88e6xxx_port_set_link,
2938
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2939
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2940
	.port_set_speed = mv88e6185_port_set_speed,
2941
	.port_tag_remap = mv88e6095_port_tag_remap,
2942
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2943
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2944
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2945
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2946
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2947
	.port_pause_limit = mv88e6097_port_pause_limit,
2948
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2949
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2950
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2951
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2952 2953
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2954
	.stats_get_stats = mv88e6095_stats_get_stats,
2955 2956
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2957
	.watchdog_ops = &mv88e6097_watchdog_ops,
2958
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2959
	.pot_clear = mv88e6xxx_g2_pot_clear,
2960
	.reset = mv88e6352_g1_reset,
2961
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2962
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2963
	.serdes_power = mv88e6341_serdes_power,
2964 2965 2966
};

static const struct mv88e6xxx_ops mv88e6176_ops = {
2967
	/* MV88E6XXX_FAMILY_6352 */
2968 2969
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2970
	.irl_init_all = mv88e6352_g2_irl_init_all,
2971 2972
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
2973
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2974 2975
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2976
	.port_set_link = mv88e6xxx_port_set_link,
2977
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2978
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2979
	.port_set_speed = mv88e6352_port_set_speed,
2980
	.port_tag_remap = mv88e6095_port_tag_remap,
2981
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2982
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2983
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2984
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2985
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2986
	.port_pause_limit = mv88e6097_port_pause_limit,
2987
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2988
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2989
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2990
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2991 2992
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2993
	.stats_get_stats = mv88e6095_stats_get_stats,
2994 2995
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2996
	.watchdog_ops = &mv88e6097_watchdog_ops,
2997
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2998
	.pot_clear = mv88e6xxx_g2_pot_clear,
2999
	.reset = mv88e6352_g1_reset,
3000
	.rmu_disable = mv88e6352_g1_rmu_disable,
3001
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3002
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3003
	.serdes_power = mv88e6352_serdes_power,
3004
	.gpio_ops = &mv88e6352_gpio_ops,
3005 3006 3007
};

static const struct mv88e6xxx_ops mv88e6185_ops = {
3008
	/* MV88E6XXX_FAMILY_6185 */
3009 3010
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3011
	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3012 3013
	.phy_read = mv88e6185_phy_ppu_read,
	.phy_write = mv88e6185_phy_ppu_write,
3014
	.port_set_link = mv88e6xxx_port_set_link,
3015
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3016
	.port_set_speed = mv88e6185_port_set_speed,
3017
	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
3018
	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
3019
	.port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3020
	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
3021
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3022
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3023 3024
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
3025
	.stats_get_stats = mv88e6095_stats_get_stats,
3026 3027
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3028
	.watchdog_ops = &mv88e6097_watchdog_ops,
3029
	.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3030
	.set_cascade_port = mv88e6185_g1_set_cascade_port,
3031 3032
	.ppu_enable = mv88e6185_g1_ppu_enable,
	.ppu_disable = mv88e6185_g1_ppu_disable,
3033
	.reset = mv88e6185_g1_reset,
3034
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
3035
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3036 3037
};

3038
static const struct mv88e6xxx_ops mv88e6190_ops = {
3039
	/* MV88E6XXX_FAMILY_6390 */
3040
	.irl_init_all = mv88e6390_g2_irl_init_all,
3041 3042
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3043 3044 3045 3046 3047 3048 3049
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
3050
	.port_tag_remap = mv88e6390_port_tag_remap,
3051
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3052
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3053
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3054
	.port_pause_limit = mv88e6390_port_pause_limit,
3055
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3056
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3057
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3058
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3059 3060
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3061
	.stats_get_stats = mv88e6390_stats_get_stats,
3062 3063
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3064
	.watchdog_ops = &mv88e6390_watchdog_ops,
3065
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3066
	.pot_clear = mv88e6xxx_g2_pot_clear,
3067
	.reset = mv88e6352_g1_reset,
3068
	.rmu_disable = mv88e6390_g1_rmu_disable,
3069 3070
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3071
	.serdes_power = mv88e6390_serdes_power,
3072
	.gpio_ops = &mv88e6352_gpio_ops,
3073 3074 3075
};

static const struct mv88e6xxx_ops mv88e6190x_ops = {
3076
	/* MV88E6XXX_FAMILY_6390 */
3077
	.irl_init_all = mv88e6390_g2_irl_init_all,
3078 3079
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3080 3081 3082 3083 3084 3085 3086
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390x_port_set_speed,
3087
	.port_tag_remap = mv88e6390_port_tag_remap,
3088
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3089
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3090
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3091
	.port_pause_limit = mv88e6390_port_pause_limit,
3092
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3093
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3094
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3095
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3096 3097
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3098
	.stats_get_stats = mv88e6390_stats_get_stats,
3099 3100
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3101
	.watchdog_ops = &mv88e6390_watchdog_ops,
3102
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3103
	.pot_clear = mv88e6xxx_g2_pot_clear,
3104
	.reset = mv88e6352_g1_reset,
3105
	.rmu_disable = mv88e6390_g1_rmu_disable,
3106 3107
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3108
	.serdes_power = mv88e6390_serdes_power,
3109
	.gpio_ops = &mv88e6352_gpio_ops,
3110 3111 3112
};

static const struct mv88e6xxx_ops mv88e6191_ops = {
3113
	/* MV88E6XXX_FAMILY_6390 */
3114
	.irl_init_all = mv88e6390_g2_irl_init_all,
3115 3116
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3117 3118 3119 3120 3121 3122 3123
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
3124
	.port_tag_remap = mv88e6390_port_tag_remap,
3125
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3126
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3127
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3128
	.port_pause_limit = mv88e6390_port_pause_limit,
3129
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3130
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3131
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3132
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3133 3134
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3135
	.stats_get_stats = mv88e6390_stats_get_stats,
3136 3137
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3138
	.watchdog_ops = &mv88e6390_watchdog_ops,
3139
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3140
	.pot_clear = mv88e6xxx_g2_pot_clear,
3141
	.reset = mv88e6352_g1_reset,
3142
	.rmu_disable = mv88e6390_g1_rmu_disable,
3143 3144
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3145
	.serdes_power = mv88e6390_serdes_power,
3146 3147
};

3148
static const struct mv88e6xxx_ops mv88e6240_ops = {
3149
	/* MV88E6XXX_FAMILY_6352 */
3150 3151
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3152
	.irl_init_all = mv88e6352_g2_irl_init_all,
3153 3154
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
3155
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3156 3157
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3158
	.port_set_link = mv88e6xxx_port_set_link,
3159
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3160
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3161
	.port_set_speed = mv88e6352_port_set_speed,
3162
	.port_tag_remap = mv88e6095_port_tag_remap,
3163
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3164
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3165
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3166
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3167
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3168
	.port_pause_limit = mv88e6097_port_pause_limit,
3169
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3170
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3171
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3172
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3173 3174
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
3175
	.stats_get_stats = mv88e6095_stats_get_stats,
3176 3177
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3178
	.watchdog_ops = &mv88e6097_watchdog_ops,
3179
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3180
	.pot_clear = mv88e6xxx_g2_pot_clear,
3181
	.reset = mv88e6352_g1_reset,
3182
	.rmu_disable = mv88e6352_g1_rmu_disable,
3183
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3184
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3185
	.serdes_power = mv88e6352_serdes_power,
3186
	.gpio_ops = &mv88e6352_gpio_ops,
3187
	.avb_ops = &mv88e6352_avb_ops,
3188 3189
};

3190
static const struct mv88e6xxx_ops mv88e6290_ops = {
3191
	/* MV88E6XXX_FAMILY_6390 */
3192
	.irl_init_all = mv88e6390_g2_irl_init_all,
3193 3194
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3195 3196 3197 3198 3199 3200 3201
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
3202
	.port_tag_remap = mv88e6390_port_tag_remap,
3203
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3204
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3205
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3206
	.port_pause_limit = mv88e6390_port_pause_limit,
3207
	.port_set_cmode = mv88e6390x_port_set_cmode,
3208
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3209
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3210
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3211
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3212 3213
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3214
	.stats_get_stats = mv88e6390_stats_get_stats,
3215 3216
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3217
	.watchdog_ops = &mv88e6390_watchdog_ops,
3218
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3219
	.pot_clear = mv88e6xxx_g2_pot_clear,
3220
	.reset = mv88e6352_g1_reset,
3221
	.rmu_disable = mv88e6390_g1_rmu_disable,
3222 3223
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3224
	.serdes_power = mv88e6390_serdes_power,
3225
	.gpio_ops = &mv88e6352_gpio_ops,
3226
	.avb_ops = &mv88e6390_avb_ops,
3227 3228
};

3229
static const struct mv88e6xxx_ops mv88e6320_ops = {
3230
	/* MV88E6XXX_FAMILY_6320 */
3231 3232
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3233
	.irl_init_all = mv88e6352_g2_irl_init_all,
3234 3235
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
3236
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3237 3238
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3239
	.port_set_link = mv88e6xxx_port_set_link,
3240
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3241
	.port_set_speed = mv88e6185_port_set_speed,
3242
	.port_tag_remap = mv88e6095_port_tag_remap,
3243
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3244
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3245
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3246
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3247
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3248
	.port_pause_limit = mv88e6097_port_pause_limit,
3249
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3250
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3251
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3252
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3253 3254
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3255
	.stats_get_stats = mv88e6320_stats_get_stats,
3256 3257
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3258
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3259
	.pot_clear = mv88e6xxx_g2_pot_clear,
3260
	.reset = mv88e6352_g1_reset,
3261
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
3262
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3263
	.gpio_ops = &mv88e6352_gpio_ops,
3264
	.avb_ops = &mv88e6352_avb_ops,
3265 3266 3267
};

static const struct mv88e6xxx_ops mv88e6321_ops = {
3268
	/* MV88E6XXX_FAMILY_6320 */
3269 3270
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3271
	.irl_init_all = mv88e6352_g2_irl_init_all,
3272 3273
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
3274
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3275 3276
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3277
	.port_set_link = mv88e6xxx_port_set_link,
3278
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3279
	.port_set_speed = mv88e6185_port_set_speed,
3280
	.port_tag_remap = mv88e6095_port_tag_remap,
3281
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3282
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3283
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3284
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3285
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3286
	.port_pause_limit = mv88e6097_port_pause_limit,
3287
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3288
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3289
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3290
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3291 3292
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3293
	.stats_get_stats = mv88e6320_stats_get_stats,
3294 3295
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3296
	.reset = mv88e6352_g1_reset,
3297
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
3298
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3299
	.gpio_ops = &mv88e6352_gpio_ops,
3300
	.avb_ops = &mv88e6352_avb_ops,
3301 3302
};

3303 3304
static const struct mv88e6xxx_ops mv88e6341_ops = {
	/* MV88E6XXX_FAMILY_6341 */
3305 3306
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3307
	.irl_init_all = mv88e6352_g2_irl_init_all,
3308 3309 3310 3311 3312 3313 3314 3315 3316 3317 3318 3319 3320
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
	.port_tag_remap = mv88e6095_port_tag_remap,
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3321
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3322
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3323
	.port_pause_limit = mv88e6097_port_pause_limit,
3324 3325 3326
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3327
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3328 3329 3330
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
	.stats_get_stats = mv88e6390_stats_get_stats,
3331 3332
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3333 3334
	.watchdog_ops = &mv88e6390_watchdog_ops,
	.mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
3335
	.pot_clear = mv88e6xxx_g2_pot_clear,
3336
	.reset = mv88e6352_g1_reset,
3337
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3338
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3339
	.gpio_ops = &mv88e6352_gpio_ops,
3340
	.avb_ops = &mv88e6390_avb_ops,
3341 3342
};

3343
static const struct mv88e6xxx_ops mv88e6350_ops = {
3344
	/* MV88E6XXX_FAMILY_6351 */
3345 3346
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3347
	.irl_init_all = mv88e6352_g2_irl_init_all,
3348
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3349 3350
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3351
	.port_set_link = mv88e6xxx_port_set_link,
3352
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3353
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3354
	.port_set_speed = mv88e6185_port_set_speed,
3355
	.port_tag_remap = mv88e6095_port_tag_remap,
3356
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3357
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3358
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3359
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3360
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3361
	.port_pause_limit = mv88e6097_port_pause_limit,
3362
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3363
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3364
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3365
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3366 3367
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
3368
	.stats_get_stats = mv88e6095_stats_get_stats,
3369 3370
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3371
	.watchdog_ops = &mv88e6097_watchdog_ops,
3372
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3373
	.pot_clear = mv88e6xxx_g2_pot_clear,
3374
	.reset = mv88e6352_g1_reset,
3375
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3376
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3377 3378 3379
};

static const struct mv88e6xxx_ops mv88e6351_ops = {
3380
	/* MV88E6XXX_FAMILY_6351 */
3381 3382
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3383
	.irl_init_all = mv88e6352_g2_irl_init_all,
3384
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3385 3386
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3387
	.port_set_link = mv88e6xxx_port_set_link,
3388
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3389
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3390
	.port_set_speed = mv88e6185_port_set_speed,
3391
	.port_tag_remap = mv88e6095_port_tag_remap,
3392
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3393
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3394
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3395
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3396
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3397
	.port_pause_limit = mv88e6097_port_pause_limit,
3398
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3399
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3400
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3401
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3402 3403
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
3404
	.stats_get_stats = mv88e6095_stats_get_stats,
3405 3406
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3407
	.watchdog_ops = &mv88e6097_watchdog_ops,
3408
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3409
	.pot_clear = mv88e6xxx_g2_pot_clear,
3410
	.reset = mv88e6352_g1_reset,
3411
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3412
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3413
	.avb_ops = &mv88e6352_avb_ops,
3414 3415 3416
};

static const struct mv88e6xxx_ops mv88e6352_ops = {
3417
	/* MV88E6XXX_FAMILY_6352 */
3418 3419
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3420
	.irl_init_all = mv88e6352_g2_irl_init_all,
3421 3422
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
3423
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3424 3425
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3426
	.port_set_link = mv88e6xxx_port_set_link,
3427
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3428
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3429
	.port_set_speed = mv88e6352_port_set_speed,
3430
	.port_tag_remap = mv88e6095_port_tag_remap,
3431
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3432
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3433
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3434
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3435
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3436
	.port_pause_limit = mv88e6097_port_pause_limit,
3437
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3438
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3439
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3440
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3441 3442
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
3443
	.stats_get_stats = mv88e6095_stats_get_stats,
3444 3445
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3446
	.watchdog_ops = &mv88e6097_watchdog_ops,
3447
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3448
	.pot_clear = mv88e6xxx_g2_pot_clear,
3449
	.reset = mv88e6352_g1_reset,
3450
	.rmu_disable = mv88e6352_g1_rmu_disable,
3451
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3452
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3453
	.serdes_power = mv88e6352_serdes_power,
3454
	.gpio_ops = &mv88e6352_gpio_ops,
3455
	.avb_ops = &mv88e6352_avb_ops,
3456 3457 3458
	.serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
	.serdes_get_strings = mv88e6352_serdes_get_strings,
	.serdes_get_stats = mv88e6352_serdes_get_stats,
3459 3460
};

3461
static const struct mv88e6xxx_ops mv88e6390_ops = {
3462
	/* MV88E6XXX_FAMILY_6390 */
3463
	.irl_init_all = mv88e6390_g2_irl_init_all,
3464 3465
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3466 3467 3468 3469 3470 3471 3472
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
3473
	.port_tag_remap = mv88e6390_port_tag_remap,
3474
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3475
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3476
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3477
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3478
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3479
	.port_pause_limit = mv88e6390_port_pause_limit,
3480
	.port_set_cmode = mv88e6390x_port_set_cmode,
3481
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3482
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3483
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3484
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3485 3486
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3487
	.stats_get_stats = mv88e6390_stats_get_stats,
3488 3489
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3490
	.watchdog_ops = &mv88e6390_watchdog_ops,
3491
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3492
	.pot_clear = mv88e6xxx_g2_pot_clear,
3493
	.reset = mv88e6352_g1_reset,
3494
	.rmu_disable = mv88e6390_g1_rmu_disable,
3495 3496
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3497
	.serdes_power = mv88e6390_serdes_power,
3498
	.gpio_ops = &mv88e6352_gpio_ops,
3499
	.avb_ops = &mv88e6390_avb_ops,
3500 3501 3502
};

static const struct mv88e6xxx_ops mv88e6390x_ops = {
3503
	/* MV88E6XXX_FAMILY_6390 */
3504
	.irl_init_all = mv88e6390_g2_irl_init_all,
3505 3506
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3507 3508 3509 3510 3511 3512 3513
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390x_port_set_speed,
3514
	.port_tag_remap = mv88e6390_port_tag_remap,
3515
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3516
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3517
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3518
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3519
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3520
	.port_pause_limit = mv88e6390_port_pause_limit,
3521
	.port_set_cmode = mv88e6390x_port_set_cmode,
3522
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3523
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3524
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3525
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3526 3527
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3528
	.stats_get_stats = mv88e6390_stats_get_stats,
3529 3530
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3531
	.watchdog_ops = &mv88e6390_watchdog_ops,
3532
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3533
	.pot_clear = mv88e6xxx_g2_pot_clear,
3534
	.reset = mv88e6352_g1_reset,
3535
	.rmu_disable = mv88e6390_g1_rmu_disable,
3536 3537
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3538
	.serdes_power = mv88e6390_serdes_power,
3539
	.gpio_ops = &mv88e6352_gpio_ops,
3540
	.avb_ops = &mv88e6390_avb_ops,
3541 3542
};

3543 3544
static const struct mv88e6xxx_info mv88e6xxx_table[] = {
	[MV88E6085] = {
3545
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
3546 3547 3548 3549
		.family = MV88E6XXX_FAMILY_6097,
		.name = "Marvell 88E6085",
		.num_databases = 4096,
		.num_ports = 10,
3550
		.num_internal_phys = 5,
3551
		.max_vid = 4095,
3552
		.port_base_addr = 0x10,
3553
		.phy_base_addr = 0x0,
3554
		.global1_addr = 0x1b,
3555
		.global2_addr = 0x1c,
3556
		.age_time_coeff = 15000,
3557
		.g1_irqs = 8,
3558
		.g2_irqs = 10,
3559
		.atu_move_port_mask = 0xf,
3560
		.pvt = true,
3561
		.multi_chip = true,
3562
		.tag_protocol = DSA_TAG_PROTO_DSA,
3563
		.ops = &mv88e6085_ops,
3564 3565 3566
	},

	[MV88E6095] = {
3567
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
3568 3569 3570 3571
		.family = MV88E6XXX_FAMILY_6095,
		.name = "Marvell 88E6095/88E6095F",
		.num_databases = 256,
		.num_ports = 11,
3572
		.num_internal_phys = 0,
3573
		.max_vid = 4095,
3574
		.port_base_addr = 0x10,
3575
		.phy_base_addr = 0x0,
3576
		.global1_addr = 0x1b,
3577
		.global2_addr = 0x1c,
3578
		.age_time_coeff = 15000,
3579
		.g1_irqs = 8,
3580
		.atu_move_port_mask = 0xf,
3581
		.multi_chip = true,
3582
		.tag_protocol = DSA_TAG_PROTO_DSA,
3583
		.ops = &mv88e6095_ops,
3584 3585
	},

3586
	[MV88E6097] = {
3587
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
3588 3589 3590 3591
		.family = MV88E6XXX_FAMILY_6097,
		.name = "Marvell 88E6097/88E6097F",
		.num_databases = 4096,
		.num_ports = 11,
3592
		.num_internal_phys = 8,
3593
		.max_vid = 4095,
3594
		.port_base_addr = 0x10,
3595
		.phy_base_addr = 0x0,
3596
		.global1_addr = 0x1b,
3597
		.global2_addr = 0x1c,
3598
		.age_time_coeff = 15000,
3599
		.g1_irqs = 8,
3600
		.g2_irqs = 10,
3601
		.atu_move_port_mask = 0xf,
3602
		.pvt = true,
3603
		.multi_chip = true,
3604
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3605 3606 3607
		.ops = &mv88e6097_ops,
	},

3608
	[MV88E6123] = {
3609
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
3610 3611 3612 3613
		.family = MV88E6XXX_FAMILY_6165,
		.name = "Marvell 88E6123",
		.num_databases = 4096,
		.num_ports = 3,
3614
		.num_internal_phys = 5,
3615
		.max_vid = 4095,
3616
		.port_base_addr = 0x10,
3617
		.phy_base_addr = 0x0,
3618
		.global1_addr = 0x1b,
3619
		.global2_addr = 0x1c,
3620
		.age_time_coeff = 15000,
3621
		.g1_irqs = 9,
3622
		.g2_irqs = 10,
3623
		.atu_move_port_mask = 0xf,
3624
		.pvt = true,
3625
		.multi_chip = true,
3626
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3627
		.ops = &mv88e6123_ops,
3628 3629 3630
	},

	[MV88E6131] = {
3631
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
3632 3633 3634 3635
		.family = MV88E6XXX_FAMILY_6185,
		.name = "Marvell 88E6131",
		.num_databases = 256,
		.num_ports = 8,
3636
		.num_internal_phys = 0,
3637
		.max_vid = 4095,
3638
		.port_base_addr = 0x10,
3639
		.phy_base_addr = 0x0,
3640
		.global1_addr = 0x1b,
3641
		.global2_addr = 0x1c,
3642
		.age_time_coeff = 15000,
3643
		.g1_irqs = 9,
3644
		.atu_move_port_mask = 0xf,
3645
		.multi_chip = true,
3646
		.tag_protocol = DSA_TAG_PROTO_DSA,
3647
		.ops = &mv88e6131_ops,
3648 3649
	},

3650
	[MV88E6141] = {
3651
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
3652
		.family = MV88E6XXX_FAMILY_6341,
3653
		.name = "Marvell 88E6141",
3654 3655
		.num_databases = 4096,
		.num_ports = 6,
3656
		.num_internal_phys = 5,
3657
		.num_gpio = 11,
3658
		.max_vid = 4095,
3659
		.port_base_addr = 0x10,
3660
		.phy_base_addr = 0x10,
3661
		.global1_addr = 0x1b,
3662
		.global2_addr = 0x1c,
3663 3664
		.age_time_coeff = 3750,
		.atu_move_port_mask = 0x1f,
3665
		.g1_irqs = 9,
3666
		.g2_irqs = 10,
3667
		.pvt = true,
3668
		.multi_chip = true,
3669 3670 3671 3672
		.tag_protocol = DSA_TAG_PROTO_EDSA,
		.ops = &mv88e6141_ops,
	},

3673
	[MV88E6161] = {
3674
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
3675 3676 3677 3678
		.family = MV88E6XXX_FAMILY_6165,
		.name = "Marvell 88E6161",
		.num_databases = 4096,
		.num_ports = 6,
3679
		.num_internal_phys = 5,
3680
		.max_vid = 4095,
3681
		.port_base_addr = 0x10,
3682
		.phy_base_addr = 0x0,
3683
		.global1_addr = 0x1b,
3684
		.global2_addr = 0x1c,
3685
		.age_time_coeff = 15000,
3686
		.g1_irqs = 9,
3687
		.g2_irqs = 10,
3688
		.atu_move_port_mask = 0xf,
3689
		.pvt = true,
3690
		.multi_chip = true,
3691
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3692
		.ops = &mv88e6161_ops,
3693 3694 3695
	},

	[MV88E6165] = {
3696
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
3697 3698 3699 3700
		.family = MV88E6XXX_FAMILY_6165,
		.name = "Marvell 88E6165",
		.num_databases = 4096,
		.num_ports = 6,
3701
		.num_internal_phys = 0,
3702
		.max_vid = 4095,
3703
		.port_base_addr = 0x10,
3704
		.phy_base_addr = 0x0,
3705
		.global1_addr = 0x1b,
3706
		.global2_addr = 0x1c,
3707
		.age_time_coeff = 15000,
3708
		.g1_irqs = 9,
3709
		.g2_irqs = 10,
3710
		.atu_move_port_mask = 0xf,
3711
		.pvt = true,
3712
		.multi_chip = true,
3713
		.tag_protocol = DSA_TAG_PROTO_DSA,
3714
		.ops = &mv88e6165_ops,
3715 3716 3717
	},

	[MV88E6171] = {
3718
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
3719 3720 3721 3722
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6171",
		.num_databases = 4096,
		.num_ports = 7,
3723
		.num_internal_phys = 5,
3724
		.max_vid = 4095,
3725
		.port_base_addr = 0x10,
3726
		.phy_base_addr = 0x0,
3727
		.global1_addr = 0x1b,
3728
		.global2_addr = 0x1c,
3729
		.age_time_coeff = 15000,
3730
		.g1_irqs = 9,
3731
		.g2_irqs = 10,
3732
		.atu_move_port_mask = 0xf,
3733
		.pvt = true,
3734
		.multi_chip = true,
3735
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3736
		.ops = &mv88e6171_ops,
3737 3738 3739
	},

	[MV88E6172] = {
3740
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
3741 3742 3743 3744
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6172",
		.num_databases = 4096,
		.num_ports = 7,
3745
		.num_internal_phys = 5,
3746
		.num_gpio = 15,
3747
		.max_vid = 4095,
3748
		.port_base_addr = 0x10,
3749
		.phy_base_addr = 0x0,
3750
		.global1_addr = 0x1b,
3751
		.global2_addr = 0x1c,
3752
		.age_time_coeff = 15000,
3753
		.g1_irqs = 9,
3754
		.g2_irqs = 10,
3755
		.atu_move_port_mask = 0xf,
3756
		.pvt = true,
3757
		.multi_chip = true,
3758
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3759
		.ops = &mv88e6172_ops,
3760 3761 3762
	},

	[MV88E6175] = {
3763
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
3764 3765 3766 3767
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6175",
		.num_databases = 4096,
		.num_ports = 7,
3768
		.num_internal_phys = 5,
3769
		.max_vid = 4095,
3770
		.port_base_addr = 0x10,
3771
		.phy_base_addr = 0x0,
3772
		.global1_addr = 0x1b,
3773
		.global2_addr = 0x1c,
3774
		.age_time_coeff = 15000,
3775
		.g1_irqs = 9,
3776
		.g2_irqs = 10,
3777
		.atu_move_port_mask = 0xf,
3778
		.pvt = true,
3779
		.multi_chip = true,
3780
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3781
		.ops = &mv88e6175_ops,
3782 3783 3784
	},

	[MV88E6176] = {
3785
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
3786 3787 3788 3789
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6176",
		.num_databases = 4096,
		.num_ports = 7,
3790
		.num_internal_phys = 5,
3791
		.num_gpio = 15,
3792
		.max_vid = 4095,
3793
		.port_base_addr = 0x10,
3794
		.phy_base_addr = 0x0,
3795
		.global1_addr = 0x1b,
3796
		.global2_addr = 0x1c,
3797
		.age_time_coeff = 15000,
3798
		.g1_irqs = 9,
3799
		.g2_irqs = 10,
3800
		.atu_move_port_mask = 0xf,
3801
		.pvt = true,
3802
		.multi_chip = true,
3803
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3804
		.ops = &mv88e6176_ops,
3805 3806 3807
	},

	[MV88E6185] = {
3808
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
3809 3810 3811 3812
		.family = MV88E6XXX_FAMILY_6185,
		.name = "Marvell 88E6185",
		.num_databases = 256,
		.num_ports = 10,
3813
		.num_internal_phys = 0,
3814
		.max_vid = 4095,
3815
		.port_base_addr = 0x10,
3816
		.phy_base_addr = 0x0,
3817
		.global1_addr = 0x1b,
3818
		.global2_addr = 0x1c,
3819
		.age_time_coeff = 15000,
3820
		.g1_irqs = 8,
3821
		.atu_move_port_mask = 0xf,
3822
		.multi_chip = true,
3823
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3824
		.ops = &mv88e6185_ops,
3825 3826
	},

3827
	[MV88E6190] = {
3828
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
3829 3830 3831 3832
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6190",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3833
		.num_internal_phys = 11,
3834
		.num_gpio = 16,
3835
		.max_vid = 8191,
3836
		.port_base_addr = 0x0,
3837
		.phy_base_addr = 0x0,
3838
		.global1_addr = 0x1b,
3839
		.global2_addr = 0x1c,
3840
		.tag_protocol = DSA_TAG_PROTO_DSA,
3841
		.age_time_coeff = 3750,
3842
		.g1_irqs = 9,
3843
		.g2_irqs = 14,
3844
		.pvt = true,
3845
		.multi_chip = true,
3846
		.atu_move_port_mask = 0x1f,
3847 3848 3849 3850
		.ops = &mv88e6190_ops,
	},

	[MV88E6190X] = {
3851
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
3852 3853 3854 3855
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6190X",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3856
		.num_internal_phys = 11,
3857
		.num_gpio = 16,
3858
		.max_vid = 8191,
3859
		.port_base_addr = 0x0,
3860
		.phy_base_addr = 0x0,
3861
		.global1_addr = 0x1b,
3862
		.global2_addr = 0x1c,
3863
		.age_time_coeff = 3750,
3864
		.g1_irqs = 9,
3865
		.g2_irqs = 14,
3866
		.atu_move_port_mask = 0x1f,
3867
		.pvt = true,
3868
		.multi_chip = true,
3869
		.tag_protocol = DSA_TAG_PROTO_DSA,
3870 3871 3872 3873
		.ops = &mv88e6190x_ops,
	},

	[MV88E6191] = {
3874
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
3875 3876 3877 3878
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6191",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3879
		.num_internal_phys = 11,
3880
		.max_vid = 8191,
3881
		.port_base_addr = 0x0,
3882
		.phy_base_addr = 0x0,
3883
		.global1_addr = 0x1b,
3884
		.global2_addr = 0x1c,
3885
		.age_time_coeff = 3750,
3886
		.g1_irqs = 9,
3887
		.g2_irqs = 14,
3888
		.atu_move_port_mask = 0x1f,
3889
		.pvt = true,
3890
		.multi_chip = true,
3891
		.tag_protocol = DSA_TAG_PROTO_DSA,
3892
		.ptp_support = true,
3893
		.ops = &mv88e6191_ops,
3894 3895
	},

3896
	[MV88E6240] = {
3897
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
3898 3899 3900 3901
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6240",
		.num_databases = 4096,
		.num_ports = 7,
3902
		.num_internal_phys = 5,
3903
		.num_gpio = 15,
3904
		.max_vid = 4095,
3905
		.port_base_addr = 0x10,
3906
		.phy_base_addr = 0x0,
3907
		.global1_addr = 0x1b,
3908
		.global2_addr = 0x1c,
3909
		.age_time_coeff = 15000,
3910
		.g1_irqs = 9,
3911
		.g2_irqs = 10,
3912
		.atu_move_port_mask = 0xf,
3913
		.pvt = true,
3914
		.multi_chip = true,
3915
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3916
		.ptp_support = true,
3917
		.ops = &mv88e6240_ops,
3918 3919
	},

3920
	[MV88E6290] = {
3921
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
3922 3923 3924 3925
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6290",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3926
		.num_internal_phys = 11,
3927
		.num_gpio = 16,
3928
		.max_vid = 8191,
3929
		.port_base_addr = 0x0,
3930
		.phy_base_addr = 0x0,
3931
		.global1_addr = 0x1b,
3932
		.global2_addr = 0x1c,
3933
		.age_time_coeff = 3750,
3934
		.g1_irqs = 9,
3935
		.g2_irqs = 14,
3936
		.atu_move_port_mask = 0x1f,
3937
		.pvt = true,
3938
		.multi_chip = true,
3939
		.tag_protocol = DSA_TAG_PROTO_DSA,
3940
		.ptp_support = true,
3941 3942 3943
		.ops = &mv88e6290_ops,
	},

3944
	[MV88E6320] = {
3945
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
3946 3947 3948 3949
		.family = MV88E6XXX_FAMILY_6320,
		.name = "Marvell 88E6320",
		.num_databases = 4096,
		.num_ports = 7,
3950
		.num_internal_phys = 5,
3951
		.num_gpio = 15,
3952
		.max_vid = 4095,
3953
		.port_base_addr = 0x10,
3954
		.phy_base_addr = 0x0,
3955
		.global1_addr = 0x1b,
3956
		.global2_addr = 0x1c,
3957
		.age_time_coeff = 15000,
3958
		.g1_irqs = 8,
3959
		.g2_irqs = 10,
3960
		.atu_move_port_mask = 0xf,
3961
		.pvt = true,
3962
		.multi_chip = true,
3963
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3964
		.ptp_support = true,
3965
		.ops = &mv88e6320_ops,
3966 3967 3968
	},

	[MV88E6321] = {
3969
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
3970 3971 3972 3973
		.family = MV88E6XXX_FAMILY_6320,
		.name = "Marvell 88E6321",
		.num_databases = 4096,
		.num_ports = 7,
3974
		.num_internal_phys = 5,
3975
		.num_gpio = 15,
3976
		.max_vid = 4095,
3977
		.port_base_addr = 0x10,
3978
		.phy_base_addr = 0x0,
3979
		.global1_addr = 0x1b,
3980
		.global2_addr = 0x1c,
3981
		.age_time_coeff = 15000,
3982
		.g1_irqs = 8,
3983
		.g2_irqs = 10,
3984
		.atu_move_port_mask = 0xf,
3985
		.multi_chip = true,
3986
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3987
		.ptp_support = true,
3988
		.ops = &mv88e6321_ops,
3989 3990
	},

3991
	[MV88E6341] = {
3992
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3993 3994 3995
		.family = MV88E6XXX_FAMILY_6341,
		.name = "Marvell 88E6341",
		.num_databases = 4096,
3996
		.num_internal_phys = 5,
3997
		.num_ports = 6,
3998
		.num_gpio = 11,
3999
		.max_vid = 4095,
4000
		.port_base_addr = 0x10,
4001
		.phy_base_addr = 0x10,
4002
		.global1_addr = 0x1b,
4003
		.global2_addr = 0x1c,
4004
		.age_time_coeff = 3750,
4005
		.atu_move_port_mask = 0x1f,
4006
		.g1_irqs = 9,
4007
		.g2_irqs = 10,
4008
		.pvt = true,
4009
		.multi_chip = true,
4010
		.tag_protocol = DSA_TAG_PROTO_EDSA,
4011
		.ptp_support = true,
4012 4013 4014
		.ops = &mv88e6341_ops,
	},

4015
	[MV88E6350] = {
4016
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
4017 4018 4019 4020
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6350",
		.num_databases = 4096,
		.num_ports = 7,
4021
		.num_internal_phys = 5,
4022
		.max_vid = 4095,
4023
		.port_base_addr = 0x10,
4024
		.phy_base_addr = 0x0,
4025
		.global1_addr = 0x1b,
4026
		.global2_addr = 0x1c,
4027
		.age_time_coeff = 15000,
4028
		.g1_irqs = 9,
4029
		.g2_irqs = 10,
4030
		.atu_move_port_mask = 0xf,
4031
		.pvt = true,
4032
		.multi_chip = true,
4033
		.tag_protocol = DSA_TAG_PROTO_EDSA,
4034
		.ops = &mv88e6350_ops,
4035 4036 4037
	},

	[MV88E6351] = {
4038
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
4039 4040 4041 4042
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6351",
		.num_databases = 4096,
		.num_ports = 7,
4043
		.num_internal_phys = 5,
4044
		.max_vid = 4095,
4045
		.port_base_addr = 0x10,
4046
		.phy_base_addr = 0x0,
4047
		.global1_addr = 0x1b,
4048
		.global2_addr = 0x1c,
4049
		.age_time_coeff = 15000,
4050
		.g1_irqs = 9,
4051
		.g2_irqs = 10,
4052
		.atu_move_port_mask = 0xf,
4053
		.pvt = true,
4054
		.multi_chip = true,
4055
		.tag_protocol = DSA_TAG_PROTO_EDSA,
4056
		.ops = &mv88e6351_ops,
4057 4058 4059
	},

	[MV88E6352] = {
4060
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
4061 4062 4063 4064
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6352",
		.num_databases = 4096,
		.num_ports = 7,
4065
		.num_internal_phys = 5,
4066
		.num_gpio = 15,
4067
		.max_vid = 4095,
4068
		.port_base_addr = 0x10,
4069
		.phy_base_addr = 0x0,
4070
		.global1_addr = 0x1b,
4071
		.global2_addr = 0x1c,
4072
		.age_time_coeff = 15000,
4073
		.g1_irqs = 9,
4074
		.g2_irqs = 10,
4075
		.atu_move_port_mask = 0xf,
4076
		.pvt = true,
4077
		.multi_chip = true,
4078
		.tag_protocol = DSA_TAG_PROTO_EDSA,
4079
		.ptp_support = true,
4080
		.ops = &mv88e6352_ops,
4081
	},
4082
	[MV88E6390] = {
4083
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
4084 4085 4086 4087
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6390",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
4088
		.num_internal_phys = 11,
4089
		.num_gpio = 16,
4090
		.max_vid = 8191,
4091
		.port_base_addr = 0x0,
4092
		.phy_base_addr = 0x0,
4093
		.global1_addr = 0x1b,
4094
		.global2_addr = 0x1c,
4095
		.age_time_coeff = 3750,
4096
		.g1_irqs = 9,
4097
		.g2_irqs = 14,
4098
		.atu_move_port_mask = 0x1f,
4099
		.pvt = true,
4100
		.multi_chip = true,
4101
		.tag_protocol = DSA_TAG_PROTO_DSA,
4102
		.ptp_support = true,
4103 4104 4105
		.ops = &mv88e6390_ops,
	},
	[MV88E6390X] = {
4106
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
4107 4108 4109 4110
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6390X",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
4111
		.num_internal_phys = 11,
4112
		.num_gpio = 16,
4113
		.max_vid = 8191,
4114
		.port_base_addr = 0x0,
4115
		.phy_base_addr = 0x0,
4116
		.global1_addr = 0x1b,
4117
		.global2_addr = 0x1c,
4118
		.age_time_coeff = 3750,
4119
		.g1_irqs = 9,
4120
		.g2_irqs = 14,
4121
		.atu_move_port_mask = 0x1f,
4122
		.pvt = true,
4123
		.multi_chip = true,
4124
		.tag_protocol = DSA_TAG_PROTO_DSA,
4125
		.ptp_support = true,
4126 4127
		.ops = &mv88e6390x_ops,
	},
4128 4129
};

4130
static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
4131
{
4132
	int i;
4133

4134 4135 4136
	for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
		if (mv88e6xxx_table[i].prod_num == prod_num)
			return &mv88e6xxx_table[i];
4137 4138 4139 4140

	return NULL;
}

4141
static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
4142 4143
{
	const struct mv88e6xxx_info *info;
4144 4145 4146
	unsigned int prod_num, rev;
	u16 id;
	int err;
4147

4148
	mutex_lock(&chip->reg_lock);
4149
	err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
4150 4151 4152
	mutex_unlock(&chip->reg_lock);
	if (err)
		return err;
4153

4154 4155
	prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
	rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
4156 4157 4158 4159 4160

	info = mv88e6xxx_lookup_info(prod_num);
	if (!info)
		return -ENODEV;

4161
	/* Update the compatible info with the probed one */
4162
	chip->info = info;
4163

4164 4165 4166 4167
	err = mv88e6xxx_g2_require(chip);
	if (err)
		return err;

4168 4169
	dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
		 chip->info->prod_num, chip->info->name, rev);
4170 4171 4172 4173

	return 0;
}

4174
static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
4175
{
4176
	struct mv88e6xxx_chip *chip;
4177

4178 4179
	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
	if (!chip)
4180 4181
		return NULL;

4182
	chip->dev = dev;
4183

4184
	mutex_init(&chip->reg_lock);
4185
	INIT_LIST_HEAD(&chip->mdios);
4186

4187
	return chip;
4188 4189
}

4190
static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4191 4192
			      struct mii_bus *bus, int sw_addr)
{
4193
	if (sw_addr == 0)
4194
		chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
4195
	else if (chip->info->multi_chip)
4196
		chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
4197 4198 4199
	else
		return -EINVAL;

4200 4201
	chip->bus = bus;
	chip->sw_addr = sw_addr;
4202 4203 4204 4205

	return 0;
}

4206 4207
static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
							int port)
4208
{
V
Vivien Didelot 已提交
4209
	struct mv88e6xxx_chip *chip = ds->priv;
4210

4211
	return chip->info->tag_protocol;
4212 4213
}

4214
#if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
4215 4216 4217
static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
				       struct device *host_dev, int sw_addr,
				       void **priv)
4218
{
4219
	struct mv88e6xxx_chip *chip;
4220
	struct mii_bus *bus;
4221
	int err;
4222

4223
	bus = dsa_host_dev_to_mii_bus(host_dev);
4224 4225 4226
	if (!bus)
		return NULL;

4227 4228
	chip = mv88e6xxx_alloc_chip(dsa_dev);
	if (!chip)
4229 4230
		return NULL;

4231
	/* Legacy SMI probing will only support chips similar to 88E6085 */
4232
	chip->info = &mv88e6xxx_table[MV88E6085];
4233

4234
	err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4235 4236 4237
	if (err)
		goto free;

4238
	err = mv88e6xxx_detect(chip);
4239
	if (err)
4240
		goto free;
4241

4242 4243 4244 4245 4246 4247
	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_switch_reset(chip);
	mutex_unlock(&chip->reg_lock);
	if (err)
		goto free;

4248 4249
	mv88e6xxx_phy_init(chip);

4250
	err = mv88e6xxx_mdios_register(chip, NULL);
4251
	if (err)
4252
		goto free;
4253

4254
	*priv = chip;
4255

4256
	return chip->info->name;
4257
free:
4258
	devm_kfree(dsa_dev, chip);
4259 4260

	return NULL;
4261
}
4262
#endif
4263

4264
static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
4265
				      const struct switchdev_obj_port_mdb *mdb)
4266 4267 4268 4269 4270 4271 4272 4273 4274
{
	/* We don't need any dynamic resource from the kernel (yet),
	 * so skip the prepare phase.
	 */

	return 0;
}

static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
4275
				   const struct switchdev_obj_port_mdb *mdb)
4276
{
V
Vivien Didelot 已提交
4277
	struct mv88e6xxx_chip *chip = ds->priv;
4278 4279 4280

	mutex_lock(&chip->reg_lock);
	if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4281
					 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
4282 4283
		dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
			port);
4284 4285 4286 4287 4288 4289
	mutex_unlock(&chip->reg_lock);
}

static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
				  const struct switchdev_obj_port_mdb *mdb)
{
V
Vivien Didelot 已提交
4290
	struct mv88e6xxx_chip *chip = ds->priv;
4291 4292 4293 4294
	int err;

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4295
					   MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
4296 4297 4298 4299 4300
	mutex_unlock(&chip->reg_lock);

	return err;
}

4301
static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
4302
#if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
4303
	.probe			= mv88e6xxx_drv_probe,
4304
#endif
4305
	.get_tag_protocol	= mv88e6xxx_get_tag_protocol,
4306 4307
	.setup			= mv88e6xxx_setup,
	.adjust_link		= mv88e6xxx_adjust_link,
4308 4309 4310 4311 4312
	.phylink_validate	= mv88e6xxx_validate,
	.phylink_mac_link_state	= mv88e6xxx_link_state,
	.phylink_mac_config	= mv88e6xxx_mac_config,
	.phylink_mac_link_down	= mv88e6xxx_mac_link_down,
	.phylink_mac_link_up	= mv88e6xxx_mac_link_up,
4313 4314 4315
	.get_strings		= mv88e6xxx_get_strings,
	.get_ethtool_stats	= mv88e6xxx_get_ethtool_stats,
	.get_sset_count		= mv88e6xxx_get_sset_count,
4316 4317
	.port_enable		= mv88e6xxx_port_enable,
	.port_disable		= mv88e6xxx_port_disable,
V
Vivien Didelot 已提交
4318 4319
	.get_mac_eee		= mv88e6xxx_get_mac_eee,
	.set_mac_eee		= mv88e6xxx_set_mac_eee,
4320
	.get_eeprom_len		= mv88e6xxx_get_eeprom_len,
4321 4322 4323 4324
	.get_eeprom		= mv88e6xxx_get_eeprom,
	.set_eeprom		= mv88e6xxx_set_eeprom,
	.get_regs_len		= mv88e6xxx_get_regs_len,
	.get_regs		= mv88e6xxx_get_regs,
4325
	.set_ageing_time	= mv88e6xxx_set_ageing_time,
4326 4327 4328
	.port_bridge_join	= mv88e6xxx_port_bridge_join,
	.port_bridge_leave	= mv88e6xxx_port_bridge_leave,
	.port_stp_state_set	= mv88e6xxx_port_stp_state_set,
4329
	.port_fast_age		= mv88e6xxx_port_fast_age,
4330 4331 4332 4333 4334 4335 4336
	.port_vlan_filtering	= mv88e6xxx_port_vlan_filtering,
	.port_vlan_prepare	= mv88e6xxx_port_vlan_prepare,
	.port_vlan_add		= mv88e6xxx_port_vlan_add,
	.port_vlan_del		= mv88e6xxx_port_vlan_del,
	.port_fdb_add           = mv88e6xxx_port_fdb_add,
	.port_fdb_del           = mv88e6xxx_port_fdb_del,
	.port_fdb_dump          = mv88e6xxx_port_fdb_dump,
4337 4338 4339
	.port_mdb_prepare       = mv88e6xxx_port_mdb_prepare,
	.port_mdb_add           = mv88e6xxx_port_mdb_add,
	.port_mdb_del           = mv88e6xxx_port_mdb_del,
4340 4341
	.crosschip_bridge_join	= mv88e6xxx_crosschip_bridge_join,
	.crosschip_bridge_leave	= mv88e6xxx_crosschip_bridge_leave,
4342 4343 4344 4345 4346
	.port_hwtstamp_set	= mv88e6xxx_port_hwtstamp_set,
	.port_hwtstamp_get	= mv88e6xxx_port_hwtstamp_get,
	.port_txtstamp		= mv88e6xxx_port_txtstamp,
	.port_rxtstamp		= mv88e6xxx_port_rxtstamp,
	.get_ts_info		= mv88e6xxx_get_ts_info,
4347 4348
};

4349 4350 4351 4352
static struct dsa_switch_driver mv88e6xxx_switch_drv = {
	.ops			= &mv88e6xxx_switch_ops,
};

4353
static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
4354
{
4355
	struct device *dev = chip->dev;
4356 4357
	struct dsa_switch *ds;

4358
	ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip));
4359 4360 4361
	if (!ds)
		return -ENOMEM;

4362
	ds->priv = chip;
4363
	ds->ops = &mv88e6xxx_switch_ops;
4364 4365
	ds->ageing_time_min = chip->info->age_time_coeff;
	ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
4366 4367 4368

	dev_set_drvdata(dev, ds);

4369
	return dsa_register_switch(ds);
4370 4371
}

4372
static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
4373
{
4374
	dsa_unregister_switch(chip->ds);
4375 4376
}

4377
static int mv88e6xxx_probe(struct mdio_device *mdiodev)
4378
{
4379
	struct device *dev = &mdiodev->dev;
4380
	struct device_node *np = dev->of_node;
4381
	const struct mv88e6xxx_info *compat_info;
4382
	struct mv88e6xxx_chip *chip;
4383
	u32 eeprom_len;
4384
	int err;
4385

4386 4387 4388 4389
	compat_info = of_device_get_match_data(dev);
	if (!compat_info)
		return -EINVAL;

4390 4391
	chip = mv88e6xxx_alloc_chip(dev);
	if (!chip)
4392 4393
		return -ENOMEM;

4394
	chip->info = compat_info;
4395

4396
	err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4397 4398
	if (err)
		return err;
4399

4400 4401 4402 4403
	chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
	if (IS_ERR(chip->reset))
		return PTR_ERR(chip->reset);

4404
	err = mv88e6xxx_detect(chip);
4405 4406
	if (err)
		return err;
4407

4408 4409
	mv88e6xxx_phy_init(chip);

4410
	if (chip->info->ops->get_eeprom &&
4411
	    !of_property_read_u32(np, "eeprom-length", &eeprom_len))
4412
		chip->eeprom_len = eeprom_len;
4413

4414 4415 4416 4417 4418 4419 4420 4421 4422 4423 4424 4425
	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_switch_reset(chip);
	mutex_unlock(&chip->reg_lock);
	if (err)
		goto out;

	chip->irq = of_irq_get(np, 0);
	if (chip->irq == -EPROBE_DEFER) {
		err = chip->irq;
		goto out;
	}

4426
	/* Has to be performed before the MDIO bus is created, because
4427
	 * the PHYs will link their interrupts to these interrupt
4428 4429 4430 4431
	 * controllers
	 */
	mutex_lock(&chip->reg_lock);
	if (chip->irq > 0)
4432
		err = mv88e6xxx_g1_irq_setup(chip);
4433 4434 4435
	else
		err = mv88e6xxx_irq_poll_setup(chip);
	mutex_unlock(&chip->reg_lock);
4436

4437 4438
	if (err)
		goto out;
4439

4440 4441
	if (chip->info->g2_irqs > 0) {
		err = mv88e6xxx_g2_irq_setup(chip);
4442
		if (err)
4443
			goto out_g1_irq;
4444 4445
	}

4446 4447 4448 4449 4450 4451 4452 4453
	err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
	if (err)
		goto out_g2_irq;

	err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
	if (err)
		goto out_g1_atu_prob_irq;

4454
	err = mv88e6xxx_mdios_register(chip, np);
4455
	if (err)
4456
		goto out_g1_vtu_prob_irq;
4457

4458
	err = mv88e6xxx_register_switch(chip);
4459 4460
	if (err)
		goto out_mdio;
4461

4462
	return 0;
4463 4464

out_mdio:
4465
	mv88e6xxx_mdios_unregister(chip);
4466
out_g1_vtu_prob_irq:
4467
	mv88e6xxx_g1_vtu_prob_irq_free(chip);
4468
out_g1_atu_prob_irq:
4469
	mv88e6xxx_g1_atu_prob_irq_free(chip);
4470
out_g2_irq:
4471
	if (chip->info->g2_irqs > 0)
4472 4473
		mv88e6xxx_g2_irq_free(chip);
out_g1_irq:
4474 4475
	mutex_lock(&chip->reg_lock);
	if (chip->irq > 0)
4476
		mv88e6xxx_g1_irq_free(chip);
4477 4478 4479
	else
		mv88e6xxx_irq_poll_free(chip);
	mutex_unlock(&chip->reg_lock);
4480 4481
out:
	return err;
4482
}
4483 4484 4485 4486

static void mv88e6xxx_remove(struct mdio_device *mdiodev)
{
	struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
V
Vivien Didelot 已提交
4487
	struct mv88e6xxx_chip *chip = ds->priv;
4488

4489 4490
	if (chip->info->ptp_support) {
		mv88e6xxx_hwtstamp_free(chip);
4491
		mv88e6xxx_ptp_free(chip);
4492
	}
4493

4494
	mv88e6xxx_phy_destroy(chip);
4495
	mv88e6xxx_unregister_switch(chip);
4496
	mv88e6xxx_mdios_unregister(chip);
4497

4498 4499 4500 4501 4502 4503 4504 4505
	mv88e6xxx_g1_vtu_prob_irq_free(chip);
	mv88e6xxx_g1_atu_prob_irq_free(chip);

	if (chip->info->g2_irqs > 0)
		mv88e6xxx_g2_irq_free(chip);

	mutex_lock(&chip->reg_lock);
	if (chip->irq > 0)
4506
		mv88e6xxx_g1_irq_free(chip);
4507 4508 4509
	else
		mv88e6xxx_irq_poll_free(chip);
	mutex_unlock(&chip->reg_lock);
4510 4511 4512
}

static const struct of_device_id mv88e6xxx_of_match[] = {
4513 4514 4515 4516
	{
		.compatible = "marvell,mv88e6085",
		.data = &mv88e6xxx_table[MV88E6085],
	},
4517 4518 4519 4520
	{
		.compatible = "marvell,mv88e6190",
		.data = &mv88e6xxx_table[MV88E6190],
	},
4521 4522 4523 4524 4525 4526 4527 4528 4529 4530 4531 4532 4533 4534 4535 4536
	{ /* sentinel */ },
};

MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);

static struct mdio_driver mv88e6xxx_driver = {
	.probe	= mv88e6xxx_probe,
	.remove = mv88e6xxx_remove,
	.mdiodrv.driver = {
		.name = "mv88e6085",
		.of_match_table = mv88e6xxx_of_match,
	},
};

static int __init mv88e6xxx_init(void)
{
4537
	register_switch_driver(&mv88e6xxx_switch_drv);
4538 4539
	return mdio_driver_register(&mv88e6xxx_driver);
}
4540 4541 4542 4543
module_init(mv88e6xxx_init);

static void __exit mv88e6xxx_cleanup(void)
{
4544
	mdio_driver_unregister(&mv88e6xxx_driver);
4545
	unregister_switch_driver(&mv88e6xxx_switch_drv);
4546 4547
}
module_exit(mv88e6xxx_cleanup);
4548 4549 4550 4551

MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
MODULE_LICENSE("GPL");