chip.c 126.1 KB
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/*
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 * Marvell 88e6xxx Ethernet switch single-chip support
 *
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 * Copyright (c) 2008 Marvell Semiconductor
 *
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 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
 *
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 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
 *	Vivien Didelot <vivien.didelot@savoirfairelinux.com>
 *
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 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

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#include <linux/delay.h>
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#include <linux/etherdevice.h>
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#include <linux/ethtool.h>
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#include <linux/if_bridge.h>
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#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
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#include <linux/jiffies.h>
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#include <linux/list.h>
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#include <linux/mdio.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/of_mdio.h>
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#include <linux/netdevice.h>
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#include <linux/gpio/consumer.h>
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#include <linux/phy.h>
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#include <linux/phylink.h>
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#include <net/dsa.h>
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#include "chip.h"
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#include "global1.h"
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#include "global2.h"
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#include "hwtstamp.h"
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#include "phy.h"
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#include "port.h"
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#include "ptp.h"
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#include "serdes.h"
45

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static void assert_reg_lock(struct mv88e6xxx_chip *chip)
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{
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	if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
		dev_err(chip->dev, "Switch registers lock not held!\n");
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		dump_stack();
	}
}

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/* The switch ADDR[4:1] configuration pins define the chip SMI device address
 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
 *
 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
 * is the only device connected to the SMI master. In this mode it responds to
 * all 32 possible SMI addresses, and thus maps directly the internal devices.
 *
 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
 * multiple devices to share the SMI interface. In this mode it responds to only
 * 2 registers, used to indirectly access the internal SMI devices.
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 */
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static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
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			      int addr, int reg, u16 *val)
{
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	if (!chip->smi_ops)
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		return -EOPNOTSUPP;

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	return chip->smi_ops->read(chip, addr, reg, val);
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}

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static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
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			       int addr, int reg, u16 val)
{
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	if (!chip->smi_ops)
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		return -EOPNOTSUPP;

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	return chip->smi_ops->write(chip, addr, reg, val);
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}

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static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
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					  int addr, int reg, u16 *val)
{
	int ret;

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	ret = mdiobus_read_nested(chip->bus, addr, reg);
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	if (ret < 0)
		return ret;

	*val = ret & 0xffff;

	return 0;
}

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static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
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					   int addr, int reg, u16 val)
{
	int ret;

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	ret = mdiobus_write_nested(chip->bus, addr, reg, val);
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	if (ret < 0)
		return ret;

	return 0;
}

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static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
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	.read = mv88e6xxx_smi_single_chip_read,
	.write = mv88e6xxx_smi_single_chip_write,
};

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static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
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{
	int ret;
	int i;

	for (i = 0; i < 16; i++) {
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		ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
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		if (ret < 0)
			return ret;

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		if ((ret & SMI_CMD_BUSY) == 0)
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			return 0;
	}

	return -ETIMEDOUT;
}

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static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
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					 int addr, int reg, u16 *val)
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{
	int ret;

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	/* Wait for the bus to become free. */
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	ret = mv88e6xxx_smi_multi_chip_wait(chip);
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	if (ret < 0)
		return ret;

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	/* Transmit the read command. */
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	ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
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				   SMI_CMD_OP_22_READ | (addr << 5) | reg);
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	if (ret < 0)
		return ret;

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	/* Wait for the read command to complete. */
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	ret = mv88e6xxx_smi_multi_chip_wait(chip);
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	if (ret < 0)
		return ret;

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	/* Read the data. */
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	ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
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	if (ret < 0)
		return ret;

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	*val = ret & 0xffff;
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	return 0;
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}

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static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
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					  int addr, int reg, u16 val)
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{
	int ret;

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	/* Wait for the bus to become free. */
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	ret = mv88e6xxx_smi_multi_chip_wait(chip);
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	if (ret < 0)
		return ret;

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	/* Transmit the data to write. */
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	ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
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	if (ret < 0)
		return ret;

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	/* Transmit the write command. */
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	ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
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				   SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
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	if (ret < 0)
		return ret;

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	/* Wait for the write command to complete. */
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	ret = mv88e6xxx_smi_multi_chip_wait(chip);
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	if (ret < 0)
		return ret;

	return 0;
}

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static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
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	.read = mv88e6xxx_smi_multi_chip_read,
	.write = mv88e6xxx_smi_multi_chip_write,
};

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int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
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{
	int err;

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	assert_reg_lock(chip);
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	err = mv88e6xxx_smi_read(chip, addr, reg, val);
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	if (err)
		return err;

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	dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
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		addr, reg, *val);

	return 0;
}

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int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
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{
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	int err;

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	assert_reg_lock(chip);
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	err = mv88e6xxx_smi_write(chip, addr, reg, val);
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	if (err)
		return err;

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	dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
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		addr, reg, val);

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	return 0;
}

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struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
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{
	struct mv88e6xxx_mdio_bus *mdio_bus;

	mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
				    list);
	if (!mdio_bus)
		return NULL;

	return mdio_bus->bus;
}

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static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
{
	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int n = d->hwirq;

	chip->g1_irq.masked |= (1 << n);
}

static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
{
	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int n = d->hwirq;

	chip->g1_irq.masked &= ~(1 << n);
}

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static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
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{
	unsigned int nhandled = 0;
	unsigned int sub_irq;
	unsigned int n;
	u16 reg;
	int err;

	mutex_lock(&chip->reg_lock);
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	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
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	mutex_unlock(&chip->reg_lock);

	if (err)
		goto out;

	for (n = 0; n < chip->g1_irq.nirqs; ++n) {
		if (reg & (1 << n)) {
			sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
			handle_nested_irq(sub_irq);
			++nhandled;
		}
	}
out:
	return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
}

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static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
{
	struct mv88e6xxx_chip *chip = dev_id;

	return mv88e6xxx_g1_irq_thread_work(chip);
}

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static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
{
	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);

	mutex_lock(&chip->reg_lock);
}

static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
{
	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
	u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
	u16 reg;
	int err;

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	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
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	if (err)
		goto out;

	reg &= ~mask;
	reg |= (~chip->g1_irq.masked & mask);

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	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
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	if (err)
		goto out;

out:
	mutex_unlock(&chip->reg_lock);
}

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static const struct irq_chip mv88e6xxx_g1_irq_chip = {
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	.name			= "mv88e6xxx-g1",
	.irq_mask		= mv88e6xxx_g1_irq_mask,
	.irq_unmask		= mv88e6xxx_g1_irq_unmask,
	.irq_bus_lock		= mv88e6xxx_g1_irq_bus_lock,
	.irq_bus_sync_unlock	= mv88e6xxx_g1_irq_bus_sync_unlock,
};

static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
				       unsigned int irq,
				       irq_hw_number_t hwirq)
{
	struct mv88e6xxx_chip *chip = d->host_data;

	irq_set_chip_data(irq, d->host_data);
	irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
	irq_set_noprobe(irq);

	return 0;
}

static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
	.map	= mv88e6xxx_g1_irq_domain_map,
	.xlate	= irq_domain_xlate_twocell,
};

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static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
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{
	int irq, virq;
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	u16 mask;

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	mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
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	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
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	mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
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354
	for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
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		virq = irq_find_mapping(chip->g1_irq.domain, irq);
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		irq_dispose_mapping(virq);
	}

359
	irq_domain_remove(chip->g1_irq.domain);
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}

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static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
{
364
	mv88e6xxx_g1_irq_free_common(chip);
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	free_irq(chip->irq, chip);
}

static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
370
{
371 372
	int err, irq, virq;
	u16 reg, mask;
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	chip->g1_irq.nirqs = chip->info->g1_irqs;
	chip->g1_irq.domain = irq_domain_add_simple(
		NULL, chip->g1_irq.nirqs, 0,
		&mv88e6xxx_g1_irq_domain_ops, chip);
	if (!chip->g1_irq.domain)
		return -ENOMEM;

	for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
		irq_create_mapping(chip->g1_irq.domain, irq);

	chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
	chip->g1_irq.masked = ~0;

387
	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
388
	if (err)
389
		goto out_mapping;
390

391
	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
392

393
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
394
	if (err)
395
		goto out_disable;
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	/* Reading the interrupt status clears (most of) them */
398
	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
399
	if (err)
400
		goto out_disable;
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	return 0;

404
out_disable:
405
	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
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	mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
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out_mapping:
	for (irq = 0; irq < 16; irq++) {
		virq = irq_find_mapping(chip->g1_irq.domain, irq);
		irq_dispose_mapping(virq);
	}

	irq_domain_remove(chip->g1_irq.domain);
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	return err;
}

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static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
{
	int err;

	err = mv88e6xxx_g1_irq_setup_common(chip);
	if (err)
		return err;

	err = request_threaded_irq(chip->irq, NULL,
				   mv88e6xxx_g1_irq_thread_fn,
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				   IRQF_ONESHOT,
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				   dev_name(chip->dev), chip);
	if (err)
		mv88e6xxx_g1_irq_free_common(chip);

	return err;
}

static void mv88e6xxx_irq_poll(struct kthread_work *work)
{
	struct mv88e6xxx_chip *chip = container_of(work,
						   struct mv88e6xxx_chip,
						   irq_poll_work.work);
	mv88e6xxx_g1_irq_thread_work(chip);

	kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
				   msecs_to_jiffies(100));
}

static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
{
	int err;

	err = mv88e6xxx_g1_irq_setup_common(chip);
	if (err)
		return err;

	kthread_init_delayed_work(&chip->irq_poll_work,
				  mv88e6xxx_irq_poll);

	chip->kworker = kthread_create_worker(0, dev_name(chip->dev));
	if (IS_ERR(chip->kworker))
		return PTR_ERR(chip->kworker);

	kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
				   msecs_to_jiffies(100));

	return 0;
}

static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
{
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	mv88e6xxx_g1_irq_free_common(chip);

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	kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
	kthread_destroy_worker(chip->kworker);
}

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int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
478
{
479
	int i;
480

481
	for (i = 0; i < 16; i++) {
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		u16 val;
		int err;

		err = mv88e6xxx_read(chip, addr, reg, &val);
		if (err)
			return err;

		if (!(val & mask))
			return 0;

		usleep_range(1000, 2000);
	}

495
	dev_err(chip->dev, "Timeout while waiting for switch\n");
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	return -ETIMEDOUT;
}

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/* Indirect write to single pointer-data register with an Update bit */
500
int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
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{
	u16 val;
503
	int err;
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	/* Wait until the previous operation is completed */
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	err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
	if (err)
		return err;
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	/* Set the Update bit to trigger a write operation */
	val = BIT(15) | update;

	return mv88e6xxx_write(chip, addr, reg, val);
}

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static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
				    int link, int speed, int duplex,
				    phy_interface_t mode)
{
	int err;

	if (!chip->info->ops->port_set_link)
		return 0;

	/* Port's MAC control must not be changed unless the link is down */
	err = chip->info->ops->port_set_link(chip, port, 0);
	if (err)
		return err;

	if (chip->info->ops->port_set_speed) {
		err = chip->info->ops->port_set_speed(chip, port, speed);
		if (err && err != -EOPNOTSUPP)
			goto restore_link;
	}

	if (chip->info->ops->port_set_duplex) {
		err = chip->info->ops->port_set_duplex(chip, port, duplex);
		if (err && err != -EOPNOTSUPP)
			goto restore_link;
	}

	if (chip->info->ops->port_set_rgmii_delay) {
		err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
		if (err && err != -EOPNOTSUPP)
			goto restore_link;
	}

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	if (chip->info->ops->port_set_cmode) {
		err = chip->info->ops->port_set_cmode(chip, port, mode);
		if (err && err != -EOPNOTSUPP)
			goto restore_link;
	}

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	err = 0;
restore_link:
	if (chip->info->ops->port_set_link(chip, port, link))
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		dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
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	return err;
}

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/* We expect the switch to perform auto negotiation if there is a real
 * phy. However, in the case of a fixed link phy, we force the port
 * settings from the fixed link settings.
 */
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static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
				  struct phy_device *phydev)
568
{
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Vivien Didelot 已提交
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	struct mv88e6xxx_chip *chip = ds->priv;
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	int err;
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	if (!phy_is_pseudo_fixed_link(phydev))
		return;

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	mutex_lock(&chip->reg_lock);
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	err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
				       phydev->duplex, phydev->interface);
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	mutex_unlock(&chip->reg_lock);
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	if (err && err != -EOPNOTSUPP)
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		dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
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}

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static void mv88e6xxx_validate(struct dsa_switch *ds, int port,
			       unsigned long *supported,
			       struct phylink_link_state *state)
{
}

static int mv88e6xxx_link_state(struct dsa_switch *ds, int port,
				struct phylink_link_state *state)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int err;

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_port_link_state(chip, port, state);
	mutex_unlock(&chip->reg_lock);

	return err;
}

static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
				 unsigned int mode,
				 const struct phylink_link_state *state)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int speed, duplex, link, err;

	if (mode == MLO_AN_PHY)
		return;

	if (mode == MLO_AN_FIXED) {
		link = LINK_FORCED_UP;
		speed = state->speed;
		duplex = state->duplex;
	} else {
		speed = SPEED_UNFORCED;
		duplex = DUPLEX_UNFORCED;
		link = LINK_UNFORCED;
	}

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_port_setup_mac(chip, port, link, speed, duplex,
				       state->interface);
	mutex_unlock(&chip->reg_lock);

	if (err && err != -EOPNOTSUPP)
		dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
}

static void mv88e6xxx_mac_link_force(struct dsa_switch *ds, int port, int link)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int err;

	mutex_lock(&chip->reg_lock);
	err = chip->info->ops->port_set_link(chip, port, link);
	mutex_unlock(&chip->reg_lock);

	if (err)
		dev_err(chip->dev, "p%d: failed to force MAC link\n", port);
}

static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
				    unsigned int mode,
				    phy_interface_t interface)
{
	if (mode == MLO_AN_FIXED)
		mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_DOWN);
}

static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
				  unsigned int mode, phy_interface_t interface,
				  struct phy_device *phydev)
{
	if (mode == MLO_AN_FIXED)
		mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_UP);
}

661
static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
662
{
663 664
	if (!chip->info->ops->stats_snapshot)
		return -EOPNOTSUPP;
665

666
	return chip->info->ops->stats_snapshot(chip, port);
667 668
}

669
static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728
	{ "in_good_octets",		8, 0x00, STATS_TYPE_BANK0, },
	{ "in_bad_octets",		4, 0x02, STATS_TYPE_BANK0, },
	{ "in_unicast",			4, 0x04, STATS_TYPE_BANK0, },
	{ "in_broadcasts",		4, 0x06, STATS_TYPE_BANK0, },
	{ "in_multicasts",		4, 0x07, STATS_TYPE_BANK0, },
	{ "in_pause",			4, 0x16, STATS_TYPE_BANK0, },
	{ "in_undersize",		4, 0x18, STATS_TYPE_BANK0, },
	{ "in_fragments",		4, 0x19, STATS_TYPE_BANK0, },
	{ "in_oversize",		4, 0x1a, STATS_TYPE_BANK0, },
	{ "in_jabber",			4, 0x1b, STATS_TYPE_BANK0, },
	{ "in_rx_error",		4, 0x1c, STATS_TYPE_BANK0, },
	{ "in_fcs_error",		4, 0x1d, STATS_TYPE_BANK0, },
	{ "out_octets",			8, 0x0e, STATS_TYPE_BANK0, },
	{ "out_unicast",		4, 0x10, STATS_TYPE_BANK0, },
	{ "out_broadcasts",		4, 0x13, STATS_TYPE_BANK0, },
	{ "out_multicasts",		4, 0x12, STATS_TYPE_BANK0, },
	{ "out_pause",			4, 0x15, STATS_TYPE_BANK0, },
	{ "excessive",			4, 0x11, STATS_TYPE_BANK0, },
	{ "collisions",			4, 0x1e, STATS_TYPE_BANK0, },
	{ "deferred",			4, 0x05, STATS_TYPE_BANK0, },
	{ "single",			4, 0x14, STATS_TYPE_BANK0, },
	{ "multiple",			4, 0x17, STATS_TYPE_BANK0, },
	{ "out_fcs_error",		4, 0x03, STATS_TYPE_BANK0, },
	{ "late",			4, 0x1f, STATS_TYPE_BANK0, },
	{ "hist_64bytes",		4, 0x08, STATS_TYPE_BANK0, },
	{ "hist_65_127bytes",		4, 0x09, STATS_TYPE_BANK0, },
	{ "hist_128_255bytes",		4, 0x0a, STATS_TYPE_BANK0, },
	{ "hist_256_511bytes",		4, 0x0b, STATS_TYPE_BANK0, },
	{ "hist_512_1023bytes",		4, 0x0c, STATS_TYPE_BANK0, },
	{ "hist_1024_max_bytes",	4, 0x0d, STATS_TYPE_BANK0, },
	{ "sw_in_discards",		4, 0x10, STATS_TYPE_PORT, },
	{ "sw_in_filtered",		2, 0x12, STATS_TYPE_PORT, },
	{ "sw_out_filtered",		2, 0x13, STATS_TYPE_PORT, },
	{ "in_discards",		4, 0x00, STATS_TYPE_BANK1, },
	{ "in_filtered",		4, 0x01, STATS_TYPE_BANK1, },
	{ "in_accepted",		4, 0x02, STATS_TYPE_BANK1, },
	{ "in_bad_accepted",		4, 0x03, STATS_TYPE_BANK1, },
	{ "in_good_avb_class_a",	4, 0x04, STATS_TYPE_BANK1, },
	{ "in_good_avb_class_b",	4, 0x05, STATS_TYPE_BANK1, },
	{ "in_bad_avb_class_a",		4, 0x06, STATS_TYPE_BANK1, },
	{ "in_bad_avb_class_b",		4, 0x07, STATS_TYPE_BANK1, },
	{ "tcam_counter_0",		4, 0x08, STATS_TYPE_BANK1, },
	{ "tcam_counter_1",		4, 0x09, STATS_TYPE_BANK1, },
	{ "tcam_counter_2",		4, 0x0a, STATS_TYPE_BANK1, },
	{ "tcam_counter_3",		4, 0x0b, STATS_TYPE_BANK1, },
	{ "in_da_unknown",		4, 0x0e, STATS_TYPE_BANK1, },
	{ "in_management",		4, 0x0f, STATS_TYPE_BANK1, },
	{ "out_queue_0",		4, 0x10, STATS_TYPE_BANK1, },
	{ "out_queue_1",		4, 0x11, STATS_TYPE_BANK1, },
	{ "out_queue_2",		4, 0x12, STATS_TYPE_BANK1, },
	{ "out_queue_3",		4, 0x13, STATS_TYPE_BANK1, },
	{ "out_queue_4",		4, 0x14, STATS_TYPE_BANK1, },
	{ "out_queue_5",		4, 0x15, STATS_TYPE_BANK1, },
	{ "out_queue_6",		4, 0x16, STATS_TYPE_BANK1, },
	{ "out_queue_7",		4, 0x17, STATS_TYPE_BANK1, },
	{ "out_cut_through",		4, 0x18, STATS_TYPE_BANK1, },
	{ "out_octets_a",		4, 0x1a, STATS_TYPE_BANK1, },
	{ "out_octets_b",		4, 0x1b, STATS_TYPE_BANK1, },
	{ "out_management",		4, 0x1f, STATS_TYPE_BANK1, },
729 730
};

731
static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
732
					    struct mv88e6xxx_hw_stat *s,
733 734
					    int port, u16 bank1_select,
					    u16 histogram)
735 736 737
{
	u32 low;
	u32 high = 0;
738
	u16 reg = 0;
739
	int err;
740 741
	u64 value;

742
	switch (s->type) {
743
	case STATS_TYPE_PORT:
744 745
		err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
		if (err)
746
			return U64_MAX;
747

748
		low = reg;
749
		if (s->size == 4) {
750 751
			err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
			if (err)
752
				return U64_MAX;
753
			high = reg;
754
		}
755
		break;
756
	case STATS_TYPE_BANK1:
757
		reg = bank1_select;
758 759
		/* fall through */
	case STATS_TYPE_BANK0:
760
		reg |= s->reg | histogram;
761
		mv88e6xxx_g1_stats_read(chip, reg, &low);
762
		if (s->size == 8)
763
			mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
764 765
		break;
	default:
766
		return U64_MAX;
767 768 769 770 771
	}
	value = (((u64)high) << 16) | low;
	return value;
}

772 773
static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
				       uint8_t *data, int types)
774
{
775 776
	struct mv88e6xxx_hw_stat *stat;
	int i, j;
777

778 779
	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
		stat = &mv88e6xxx_hw_stats[i];
780
		if (stat->type & types) {
781 782 783 784
			memcpy(data + j * ETH_GSTRING_LEN, stat->string,
			       ETH_GSTRING_LEN);
			j++;
		}
785
	}
786 787

	return j;
788 789
}

790 791
static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
				       uint8_t *data)
792
{
793 794
	return mv88e6xxx_stats_get_strings(chip, data,
					   STATS_TYPE_BANK0 | STATS_TYPE_PORT);
795 796
}

797 798
static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
				       uint8_t *data)
799
{
800 801
	return mv88e6xxx_stats_get_strings(chip, data,
					   STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
802 803
}

804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821
static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
	"atu_member_violation",
	"atu_miss_violation",
	"atu_full_violation",
	"vtu_member_violation",
	"vtu_miss_violation",
};

static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
{
	unsigned int i;

	for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
		strlcpy(data + i * ETH_GSTRING_LEN,
			mv88e6xxx_atu_vtu_stats_strings[i],
			ETH_GSTRING_LEN);
}

822
static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
823
				  u32 stringset, uint8_t *data)
824
{
V
Vivien Didelot 已提交
825
	struct mv88e6xxx_chip *chip = ds->priv;
826
	int count = 0;
827

828 829 830
	if (stringset != ETH_SS_STATS)
		return;

831 832
	mutex_lock(&chip->reg_lock);

833
	if (chip->info->ops->stats_get_strings)
834 835 836 837
		count = chip->info->ops->stats_get_strings(chip, data);

	if (chip->info->ops->serdes_get_strings) {
		data += count * ETH_GSTRING_LEN;
838
		count = chip->info->ops->serdes_get_strings(chip, port, data);
839
	}
840

841 842 843
	data += count * ETH_GSTRING_LEN;
	mv88e6xxx_atu_vtu_get_strings(data);

844
	mutex_unlock(&chip->reg_lock);
845 846 847 848 849
}

static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
					  int types)
{
850 851 852 853 854
	struct mv88e6xxx_hw_stat *stat;
	int i, j;

	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
		stat = &mv88e6xxx_hw_stats[i];
855
		if (stat->type & types)
856 857 858
			j++;
	}
	return j;
859 860
}

861 862 863 864 865 866 867 868 869 870 871 872
static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
{
	return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
					      STATS_TYPE_PORT);
}

static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
{
	return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
					      STATS_TYPE_BANK1);
}

873
static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
874 875
{
	struct mv88e6xxx_chip *chip = ds->priv;
876 877
	int serdes_count = 0;
	int count = 0;
878

879 880 881
	if (sset != ETH_SS_STATS)
		return 0;

882
	mutex_lock(&chip->reg_lock);
883
	if (chip->info->ops->stats_get_sset_count)
884 885 886 887 888 889 890
		count = chip->info->ops->stats_get_sset_count(chip);
	if (count < 0)
		goto out;

	if (chip->info->ops->serdes_get_sset_count)
		serdes_count = chip->info->ops->serdes_get_sset_count(chip,
								      port);
891
	if (serdes_count < 0) {
892
		count = serdes_count;
893 894 895 896 897
		goto out;
	}
	count += serdes_count;
	count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);

898
out:
899
	mutex_unlock(&chip->reg_lock);
900

901
	return count;
902 903
}

904 905 906
static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
				     uint64_t *data, int types,
				     u16 bank1_select, u16 histogram)
907 908 909 910 911 912 913
{
	struct mv88e6xxx_hw_stat *stat;
	int i, j;

	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
		stat = &mv88e6xxx_hw_stats[i];
		if (stat->type & types) {
914
			mutex_lock(&chip->reg_lock);
915 916 917
			data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
							      bank1_select,
							      histogram);
918 919
			mutex_unlock(&chip->reg_lock);

920 921 922
			j++;
		}
	}
923
	return j;
924 925
}

926 927
static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
				     uint64_t *data)
928 929
{
	return mv88e6xxx_stats_get_stats(chip, port, data,
930
					 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
931
					 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
932 933
}

934 935
static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
				     uint64_t *data)
936 937
{
	return mv88e6xxx_stats_get_stats(chip, port, data,
938
					 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
939 940
					 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
					 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
941 942
}

943 944
static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
				     uint64_t *data)
945 946 947
{
	return mv88e6xxx_stats_get_stats(chip, port, data,
					 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
948 949
					 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
					 0);
950 951
}

952 953 954 955 956 957 958 959 960 961
static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
					uint64_t *data)
{
	*data++ = chip->ports[port].atu_member_violation;
	*data++ = chip->ports[port].atu_miss_violation;
	*data++ = chip->ports[port].atu_full_violation;
	*data++ = chip->ports[port].vtu_member_violation;
	*data++ = chip->ports[port].vtu_miss_violation;
}

962 963 964
static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
				uint64_t *data)
{
965 966
	int count = 0;

967
	if (chip->info->ops->stats_get_stats)
968 969
		count = chip->info->ops->stats_get_stats(chip, port, data);

970
	mutex_lock(&chip->reg_lock);
971 972
	if (chip->info->ops->serdes_get_stats) {
		data += count;
973
		count = chip->info->ops->serdes_get_stats(chip, port, data);
974
	}
975 976 977
	data += count;
	mv88e6xxx_atu_vtu_get_stats(chip, port, data);
	mutex_unlock(&chip->reg_lock);
978 979
}

980 981
static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
					uint64_t *data)
982
{
V
Vivien Didelot 已提交
983
	struct mv88e6xxx_chip *chip = ds->priv;
984 985
	int ret;

986
	mutex_lock(&chip->reg_lock);
987

988
	ret = mv88e6xxx_stats_snapshot(chip, port);
989 990 991
	mutex_unlock(&chip->reg_lock);

	if (ret < 0)
992
		return;
993 994

	mv88e6xxx_get_stats(chip, port, data);
995

996 997
}

998
static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
999 1000 1001 1002
{
	return 32 * sizeof(u16);
}

1003 1004
static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
			       struct ethtool_regs *regs, void *_p)
1005
{
V
Vivien Didelot 已提交
1006
	struct mv88e6xxx_chip *chip = ds->priv;
1007 1008
	int err;
	u16 reg;
1009 1010 1011 1012 1013 1014 1015
	u16 *p = _p;
	int i;

	regs->version = 0;

	memset(p, 0xff, 32 * sizeof(u16));

1016
	mutex_lock(&chip->reg_lock);
1017

1018 1019
	for (i = 0; i < 32; i++) {

1020 1021 1022
		err = mv88e6xxx_port_read(chip, port, i, &reg);
		if (!err)
			p[i] = reg;
1023
	}
1024

1025
	mutex_unlock(&chip->reg_lock);
1026 1027
}

V
Vivien Didelot 已提交
1028 1029
static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
				 struct ethtool_eee *e)
1030
{
1031 1032
	/* Nothing to do on the port's MAC */
	return 0;
1033 1034
}

V
Vivien Didelot 已提交
1035 1036
static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
				 struct ethtool_eee *e)
1037
{
1038 1039
	/* Nothing to do on the port's MAC */
	return 0;
1040 1041
}

1042
static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1043
{
1044 1045 1046
	struct dsa_switch *ds = NULL;
	struct net_device *br;
	u16 pvlan;
1047 1048
	int i;

1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068
	if (dev < DSA_MAX_SWITCHES)
		ds = chip->ds->dst->ds[dev];

	/* Prevent frames from unknown switch or port */
	if (!ds || port >= ds->num_ports)
		return 0;

	/* Frames from DSA links and CPU ports can egress any local port */
	if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
		return mv88e6xxx_port_mask(chip);

	br = ds->ports[port].bridge_dev;
	pvlan = 0;

	/* Frames from user ports can egress any local DSA links and CPU ports,
	 * as well as any local member of their bridge group.
	 */
	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
		if (dsa_is_cpu_port(chip->ds, i) ||
		    dsa_is_dsa_port(chip->ds, i) ||
V
Vivien Didelot 已提交
1069
		    (br && dsa_to_port(chip->ds, i)->bridge_dev == br))
1070 1071 1072 1073 1074
			pvlan |= BIT(i);

	return pvlan;
}

1075
static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1076 1077
{
	u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1078 1079 1080

	/* prevent frames from going back out of the port they came in on */
	output_ports &= ~BIT(port);
1081

1082
	return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1083 1084
}

1085 1086
static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
					 u8 state)
1087
{
V
Vivien Didelot 已提交
1088
	struct mv88e6xxx_chip *chip = ds->priv;
1089
	int err;
1090

1091
	mutex_lock(&chip->reg_lock);
1092
	err = mv88e6xxx_port_set_state(chip, port, state);
1093
	mutex_unlock(&chip->reg_lock);
1094 1095

	if (err)
1096
		dev_err(ds->dev, "p%d: failed to update state\n", port);
1097 1098
}

1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117
static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
{
	int err;

	if (chip->info->ops->ieee_pri_map) {
		err = chip->info->ops->ieee_pri_map(chip);
		if (err)
			return err;
	}

	if (chip->info->ops->ip_pri_map) {
		err = chip->info->ops->ip_pri_map(chip);
		if (err)
			return err;
	}

	return 0;
}

1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137
static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
{
	int target, port;
	int err;

	if (!chip->info->global2_addr)
		return 0;

	/* Initialize the routing port to the 32 possible target devices */
	for (target = 0; target < 32; target++) {
		port = 0x1f;
		if (target < DSA_MAX_SWITCHES)
			if (chip->ds->rtable[target] != DSA_RTABLE_NONE)
				port = chip->ds->rtable[target];

		err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
		if (err)
			return err;
	}

1138 1139 1140 1141 1142 1143 1144
	if (chip->info->ops->set_cascade_port) {
		port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
		err = chip->info->ops->set_cascade_port(chip, port);
		if (err)
			return err;
	}

1145 1146 1147 1148
	err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
	if (err)
		return err;

1149 1150 1151
	return 0;
}

1152 1153 1154 1155 1156 1157 1158 1159 1160
static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
{
	/* Clear all trunk masks and mapping */
	if (chip->info->global2_addr)
		return mv88e6xxx_g2_trunk_clear(chip);

	return 0;
}

1161 1162 1163 1164 1165 1166 1167 1168
static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->rmu_disable)
		return chip->info->ops->rmu_disable(chip);

	return 0;
}

1169 1170 1171 1172 1173 1174 1175 1176
static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->pot_clear)
		return chip->info->ops->pot_clear(chip);

	return 0;
}

1177 1178 1179 1180 1181 1182 1183 1184
static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->mgmt_rsvd2cpu)
		return chip->info->ops->mgmt_rsvd2cpu(chip);

	return 0;
}

1185 1186
static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
{
1187 1188
	int err;

1189 1190 1191 1192
	err = mv88e6xxx_g1_atu_flush(chip, 0, true);
	if (err)
		return err;

1193 1194 1195 1196
	err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
	if (err)
		return err;

1197 1198 1199
	return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
}

1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219
static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
{
	int port;
	int err;

	if (!chip->info->ops->irl_init_all)
		return 0;

	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
		/* Disable ingress rate limiting by resetting all per port
		 * ingress rate limit resources to their initial state.
		 */
		err = chip->info->ops->irl_init_all(chip, port);
		if (err)
			return err;
	}

	return 0;
}

1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232
static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->set_switch_mac) {
		u8 addr[ETH_ALEN];

		eth_random_addr(addr);

		return chip->info->ops->set_switch_mac(chip, addr);
	}

	return 0;
}

1233 1234 1235 1236 1237 1238 1239 1240 1241
static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
{
	u16 pvlan = 0;

	if (!mv88e6xxx_has_pvt(chip))
		return -EOPNOTSUPP;

	/* Skip the local source device, which uses in-chip port VLAN */
	if (dev != chip->ds->index)
1242
		pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1243 1244 1245 1246

	return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
}

1247 1248
static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
{
1249 1250 1251
	int dev, port;
	int err;

1252 1253 1254 1255 1256 1257
	if (!mv88e6xxx_has_pvt(chip))
		return 0;

	/* Clear 5 Bit Port for usage with Marvell Link Street devices:
	 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
	 */
1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270
	err = mv88e6xxx_g2_misc_4_bit_port(chip);
	if (err)
		return err;

	for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
		for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
			err = mv88e6xxx_pvt_map(chip, dev, port);
			if (err)
				return err;
		}
	}

	return 0;
1271 1272
}

1273 1274 1275 1276 1277 1278
static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int err;

	mutex_lock(&chip->reg_lock);
1279
	err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
1280 1281 1282
	mutex_unlock(&chip->reg_lock);

	if (err)
1283
		dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
1284 1285
}

1286 1287 1288 1289 1290 1291 1292 1293
static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
{
	if (!chip->info->max_vid)
		return 0;

	return mv88e6xxx_g1_vtu_flush(chip);
}

1294 1295 1296 1297 1298 1299 1300 1301 1302
static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
				 struct mv88e6xxx_vtu_entry *entry)
{
	if (!chip->info->ops->vtu_getnext)
		return -EOPNOTSUPP;

	return chip->info->ops->vtu_getnext(chip, entry);
}

1303 1304 1305 1306 1307 1308 1309 1310 1311
static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
				   struct mv88e6xxx_vtu_entry *entry)
{
	if (!chip->info->ops->vtu_loadpurge)
		return -EOPNOTSUPP;

	return chip->info->ops->vtu_loadpurge(chip, entry);
}

1312
static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1313 1314
{
	DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1315 1316 1317
	struct mv88e6xxx_vtu_entry vlan = {
		.vid = chip->info->max_vid,
	};
1318
	int i, err;
1319 1320 1321

	bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);

1322
	/* Set every FID bit used by the (un)bridged ports */
1323
	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1324
		err = mv88e6xxx_port_get_fid(chip, i, fid);
1325 1326 1327 1328 1329 1330
		if (err)
			return err;

		set_bit(*fid, fid_bitmap);
	}

1331 1332
	/* Set every FID bit used by the VLAN entries */
	do {
1333
		err = mv88e6xxx_vtu_getnext(chip, &vlan);
1334 1335 1336 1337 1338 1339 1340
		if (err)
			return err;

		if (!vlan.valid)
			break;

		set_bit(vlan.fid, fid_bitmap);
1341
	} while (vlan.vid < chip->info->max_vid);
1342 1343 1344 1345 1346

	/* The reset value 0x000 is used to indicate that multiple address
	 * databases are not needed. Return the next positive available.
	 */
	*fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1347
	if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1348 1349 1350
		return -ENOSPC;

	/* Clear the database */
1351
	return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1352 1353
}

1354 1355
static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
			     struct mv88e6xxx_vtu_entry *entry, bool new)
1356 1357 1358 1359 1360 1361
{
	int err;

	if (!vid)
		return -EINVAL;

1362 1363
	entry->vid = vid - 1;
	entry->valid = false;
1364

1365
	err = mv88e6xxx_vtu_getnext(chip, entry);
1366 1367 1368
	if (err)
		return err;

1369 1370
	if (entry->vid == vid && entry->valid)
		return 0;
1371

1372 1373 1374 1375 1376 1377 1378 1379
	if (new) {
		int i;

		/* Initialize a fresh VLAN entry */
		memset(entry, 0, sizeof(*entry));
		entry->valid = true;
		entry->vid = vid;

1380
		/* Exclude all ports */
1381
		for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1382
			entry->member[i] =
1383
				MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1384 1385

		return mv88e6xxx_atu_new(chip, &entry->fid);
1386 1387
	}

1388 1389
	/* switchdev expects -EOPNOTSUPP to honor software VLANs */
	return -EOPNOTSUPP;
1390 1391
}

1392 1393 1394
static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
					u16 vid_begin, u16 vid_end)
{
V
Vivien Didelot 已提交
1395
	struct mv88e6xxx_chip *chip = ds->priv;
1396 1397 1398
	struct mv88e6xxx_vtu_entry vlan = {
		.vid = vid_begin - 1,
	};
1399 1400
	int i, err;

1401 1402 1403 1404
	/* DSA and CPU ports have to be members of multiple vlans */
	if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
		return 0;

1405 1406 1407
	if (!vid_begin)
		return -EOPNOTSUPP;

1408
	mutex_lock(&chip->reg_lock);
1409 1410

	do {
1411
		err = mv88e6xxx_vtu_getnext(chip, &vlan);
1412 1413 1414 1415 1416 1417 1418 1419 1420
		if (err)
			goto unlock;

		if (!vlan.valid)
			break;

		if (vlan.vid > vid_end)
			break;

1421
		for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1422 1423 1424
			if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
				continue;

1425
			if (!ds->ports[i].slave)
1426 1427
				continue;

1428
			if (vlan.member[i] ==
1429
			    MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1430 1431
				continue;

V
Vivien Didelot 已提交
1432
			if (dsa_to_port(ds, i)->bridge_dev ==
1433
			    ds->ports[port].bridge_dev)
1434 1435
				break; /* same bridge, check next VLAN */

V
Vivien Didelot 已提交
1436
			if (!dsa_to_port(ds, i)->bridge_dev)
1437 1438
				continue;

1439 1440
			dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
				port, vlan.vid, i,
V
Vivien Didelot 已提交
1441
				netdev_name(dsa_to_port(ds, i)->bridge_dev));
1442 1443 1444 1445 1446 1447
			err = -EOPNOTSUPP;
			goto unlock;
		}
	} while (vlan.vid < vid_end);

unlock:
1448
	mutex_unlock(&chip->reg_lock);
1449 1450 1451 1452

	return err;
}

1453 1454
static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
					 bool vlan_filtering)
1455
{
V
Vivien Didelot 已提交
1456
	struct mv88e6xxx_chip *chip = ds->priv;
1457 1458
	u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
		MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1459
	int err;
1460

1461
	if (!chip->info->max_vid)
1462 1463
		return -EOPNOTSUPP;

1464
	mutex_lock(&chip->reg_lock);
1465
	err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1466
	mutex_unlock(&chip->reg_lock);
1467

1468
	return err;
1469 1470
}

1471 1472
static int
mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1473
			    const struct switchdev_obj_port_vlan *vlan)
1474
{
V
Vivien Didelot 已提交
1475
	struct mv88e6xxx_chip *chip = ds->priv;
1476 1477
	int err;

1478
	if (!chip->info->max_vid)
1479 1480
		return -EOPNOTSUPP;

1481 1482 1483 1484 1485 1486 1487 1488
	/* If the requested port doesn't belong to the same bridge as the VLAN
	 * members, do not support it (yet) and fallback to software VLAN.
	 */
	err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
					   vlan->vid_end);
	if (err)
		return err;

1489 1490 1491 1492 1493 1494
	/* We don't need any dynamic resource from the kernel (yet),
	 * so skip the prepare phase.
	 */
	return 0;
}

1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538
static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
					const unsigned char *addr, u16 vid,
					u8 state)
{
	struct mv88e6xxx_vtu_entry vlan;
	struct mv88e6xxx_atu_entry entry;
	int err;

	/* Null VLAN ID corresponds to the port private database */
	if (vid == 0)
		err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
	else
		err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
	if (err)
		return err;

	entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
	ether_addr_copy(entry.mac, addr);
	eth_addr_dec(entry.mac);

	err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
	if (err)
		return err;

	/* Initialize a fresh ATU entry if it isn't found */
	if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED ||
	    !ether_addr_equal(entry.mac, addr)) {
		memset(&entry, 0, sizeof(entry));
		ether_addr_copy(entry.mac, addr);
	}

	/* Purge the ATU entry only if no port is using it anymore */
	if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
		entry.portvec &= ~BIT(port);
		if (!entry.portvec)
			entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
	} else {
		entry.portvec |= BIT(port);
		entry.state = state;
	}

	return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
}

1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561
static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
					u16 vid)
{
	const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
	u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;

	return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
}

static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
{
	int port;
	int err;

	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
		err = mv88e6xxx_port_add_broadcast(chip, port, vid);
		if (err)
			return err;
	}

	return 0;
}

1562
static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1563
				    u16 vid, u8 member)
1564
{
1565
	struct mv88e6xxx_vtu_entry vlan;
1566 1567
	int err;

1568
	err = mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1569
	if (err)
1570
		return err;
1571

1572
	vlan.member[port] = member;
1573

1574 1575 1576 1577 1578
	err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
	if (err)
		return err;

	return mv88e6xxx_broadcast_setup(chip, vid);
1579 1580
}

1581
static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1582
				    const struct switchdev_obj_port_vlan *vlan)
1583
{
V
Vivien Didelot 已提交
1584
	struct mv88e6xxx_chip *chip = ds->priv;
1585 1586
	bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
	bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1587
	u8 member;
1588 1589
	u16 vid;

1590
	if (!chip->info->max_vid)
1591 1592
		return;

1593
	if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1594
		member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
1595
	else if (untagged)
1596
		member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
1597
	else
1598
		member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
1599

1600
	mutex_lock(&chip->reg_lock);
1601

1602
	for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1603
		if (_mv88e6xxx_port_vlan_add(chip, port, vid, member))
1604 1605
			dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
				vid, untagged ? 'u' : 't');
1606

1607
	if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
1608 1609
		dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
			vlan->vid_end);
1610

1611
	mutex_unlock(&chip->reg_lock);
1612 1613
}

1614
static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1615
				    int port, u16 vid)
1616
{
1617
	struct mv88e6xxx_vtu_entry vlan;
1618 1619
	int i, err;

1620
	err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1621
	if (err)
1622
		return err;
1623

1624
	/* Tell switchdev if this VLAN is handled in software */
1625
	if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1626
		return -EOPNOTSUPP;
1627

1628
	vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1629 1630

	/* keep the VLAN unless all ports are excluded */
1631
	vlan.valid = false;
1632
	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1633 1634
		if (vlan.member[i] !=
		    MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1635
			vlan.valid = true;
1636 1637 1638 1639
			break;
		}
	}

1640
	err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1641 1642 1643
	if (err)
		return err;

1644
	return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
1645 1646
}

1647 1648
static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
				   const struct switchdev_obj_port_vlan *vlan)
1649
{
V
Vivien Didelot 已提交
1650
	struct mv88e6xxx_chip *chip = ds->priv;
1651 1652 1653
	u16 pvid, vid;
	int err = 0;

1654
	if (!chip->info->max_vid)
1655 1656
		return -EOPNOTSUPP;

1657
	mutex_lock(&chip->reg_lock);
1658

1659
	err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1660 1661 1662
	if (err)
		goto unlock;

1663
	for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1664
		err = _mv88e6xxx_port_vlan_del(chip, port, vid);
1665 1666 1667 1668
		if (err)
			goto unlock;

		if (vid == pvid) {
1669
			err = mv88e6xxx_port_set_pvid(chip, port, 0);
1670 1671 1672 1673 1674
			if (err)
				goto unlock;
		}
	}

1675
unlock:
1676
	mutex_unlock(&chip->reg_lock);
1677 1678 1679 1680

	return err;
}

1681 1682
static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
				  const unsigned char *addr, u16 vid)
1683
{
V
Vivien Didelot 已提交
1684
	struct mv88e6xxx_chip *chip = ds->priv;
1685
	int err;
1686

1687
	mutex_lock(&chip->reg_lock);
1688 1689
	err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
					   MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1690
	mutex_unlock(&chip->reg_lock);
1691 1692

	return err;
1693 1694
}

1695
static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1696
				  const unsigned char *addr, u16 vid)
1697
{
V
Vivien Didelot 已提交
1698
	struct mv88e6xxx_chip *chip = ds->priv;
1699
	int err;
1700

1701
	mutex_lock(&chip->reg_lock);
1702
	err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1703
					   MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
1704
	mutex_unlock(&chip->reg_lock);
1705

1706
	return err;
1707 1708
}

1709 1710
static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
				      u16 fid, u16 vid, int port,
1711
				      dsa_fdb_dump_cb_t *cb, void *data)
1712
{
1713
	struct mv88e6xxx_atu_entry addr;
1714
	bool is_static;
1715 1716
	int err;

1717
	addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1718
	eth_broadcast_addr(addr.mac);
1719 1720

	do {
1721
		mutex_lock(&chip->reg_lock);
1722
		err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
1723
		mutex_unlock(&chip->reg_lock);
1724
		if (err)
1725
			return err;
1726

1727
		if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED)
1728 1729
			break;

1730
		if (addr.trunk || (addr.portvec & BIT(port)) == 0)
1731 1732
			continue;

1733 1734
		if (!is_unicast_ether_addr(addr.mac))
			continue;
1735

1736 1737 1738
		is_static = (addr.state ==
			     MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
		err = cb(addr.mac, vid, is_static, data);
1739 1740
		if (err)
			return err;
1741 1742 1743 1744 1745
	} while (!is_broadcast_ether_addr(addr.mac));

	return err;
}

1746
static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
1747
				  dsa_fdb_dump_cb_t *cb, void *data)
1748
{
1749
	struct mv88e6xxx_vtu_entry vlan = {
1750
		.vid = chip->info->max_vid,
1751
	};
1752
	u16 fid;
1753 1754
	int err;

1755
	/* Dump port's default Filtering Information Database (VLAN ID 0) */
1756
	mutex_lock(&chip->reg_lock);
1757
	err = mv88e6xxx_port_get_fid(chip, port, &fid);
1758 1759
	mutex_unlock(&chip->reg_lock);

1760
	if (err)
1761
		return err;
1762

1763
	err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
1764
	if (err)
1765
		return err;
1766

1767
	/* Dump VLANs' Filtering Information Databases */
1768
	do {
1769
		mutex_lock(&chip->reg_lock);
1770
		err = mv88e6xxx_vtu_getnext(chip, &vlan);
1771
		mutex_unlock(&chip->reg_lock);
1772
		if (err)
1773
			return err;
1774 1775 1776 1777

		if (!vlan.valid)
			break;

1778
		err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
1779
						 cb, data);
1780
		if (err)
1781
			return err;
1782
	} while (vlan.vid < chip->info->max_vid);
1783

1784 1785 1786 1787
	return err;
}

static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
1788
				   dsa_fdb_dump_cb_t *cb, void *data)
1789
{
V
Vivien Didelot 已提交
1790
	struct mv88e6xxx_chip *chip = ds->priv;
1791

1792
	return mv88e6xxx_port_db_dump(chip, port, cb, data);
1793 1794
}

1795 1796
static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
				struct net_device *br)
1797
{
1798
	struct dsa_switch *ds;
1799
	int port;
1800
	int dev;
1801
	int err;
1802

1803 1804 1805 1806
	/* Remap the Port VLAN of each local bridge group member */
	for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
		if (chip->ds->ports[port].bridge_dev == br) {
			err = mv88e6xxx_port_vlan_map(chip, port);
1807
			if (err)
1808
				return err;
1809 1810 1811
		}
	}

1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829
	if (!mv88e6xxx_has_pvt(chip))
		return 0;

	/* Remap the Port VLAN of each cross-chip bridge group member */
	for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) {
		ds = chip->ds->dst->ds[dev];
		if (!ds)
			break;

		for (port = 0; port < ds->num_ports; ++port) {
			if (ds->ports[port].bridge_dev == br) {
				err = mv88e6xxx_pvt_map(chip, dev, port);
				if (err)
					return err;
			}
		}
	}

1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840
	return 0;
}

static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
				      struct net_device *br)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int err;

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_bridge_map(chip, br);
1841
	mutex_unlock(&chip->reg_lock);
1842

1843
	return err;
1844 1845
}

1846 1847
static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
					struct net_device *br)
1848
{
V
Vivien Didelot 已提交
1849
	struct mv88e6xxx_chip *chip = ds->priv;
1850

1851
	mutex_lock(&chip->reg_lock);
1852 1853 1854
	if (mv88e6xxx_bridge_map(chip, br) ||
	    mv88e6xxx_port_vlan_map(chip, port))
		dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
1855
	mutex_unlock(&chip->reg_lock);
1856 1857
}

1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887
static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
					   int port, struct net_device *br)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int err;

	if (!mv88e6xxx_has_pvt(chip))
		return 0;

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_pvt_map(chip, dev, port);
	mutex_unlock(&chip->reg_lock);

	return err;
}

static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
					     int port, struct net_device *br)
{
	struct mv88e6xxx_chip *chip = ds->priv;

	if (!mv88e6xxx_has_pvt(chip))
		return;

	mutex_lock(&chip->reg_lock);
	if (mv88e6xxx_pvt_map(chip, dev, port))
		dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
	mutex_unlock(&chip->reg_lock);
}

1888 1889 1890 1891 1892 1893 1894 1895
static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->reset)
		return chip->info->ops->reset(chip);

	return 0;
}

1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908
static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
{
	struct gpio_desc *gpiod = chip->reset;

	/* If there is a GPIO connected to the reset pin, toggle it */
	if (gpiod) {
		gpiod_set_value_cansleep(gpiod, 1);
		usleep_range(10000, 20000);
		gpiod_set_value_cansleep(gpiod, 0);
		usleep_range(10000, 20000);
	}
}

1909
static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
1910
{
1911
	int i, err;
1912

1913
	/* Set all ports to the Disabled state */
1914
	for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
1915
		err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
1916 1917
		if (err)
			return err;
1918 1919
	}

1920 1921 1922
	/* Wait for transmit queues to drain,
	 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
	 */
1923 1924
	usleep_range(2000, 4000);

1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935
	return 0;
}

static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
{
	int err;

	err = mv88e6xxx_disable_ports(chip);
	if (err)
		return err;

1936
	mv88e6xxx_hardware_reset(chip);
1937

1938
	return mv88e6xxx_software_reset(chip);
1939 1940
}

1941
static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
1942 1943
				   enum mv88e6xxx_frame_mode frame,
				   enum mv88e6xxx_egress_mode egress, u16 etype)
1944 1945 1946
{
	int err;

1947 1948 1949 1950
	if (!chip->info->ops->port_set_frame_mode)
		return -EOPNOTSUPP;

	err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
1951 1952 1953
	if (err)
		return err;

1954 1955 1956 1957 1958 1959 1960 1961
	err = chip->info->ops->port_set_frame_mode(chip, port, frame);
	if (err)
		return err;

	if (chip->info->ops->port_set_ether_type)
		return chip->info->ops->port_set_ether_type(chip, port, etype);

	return 0;
1962 1963
}

1964
static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
1965
{
1966
	return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
1967
				       MV88E6XXX_EGRESS_MODE_UNMODIFIED,
1968
				       MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
1969
}
1970

1971 1972 1973
static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
{
	return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
1974
				       MV88E6XXX_EGRESS_MODE_UNMODIFIED,
1975
				       MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
1976
}
1977

1978 1979 1980 1981
static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
{
	return mv88e6xxx_set_port_mode(chip, port,
				       MV88E6XXX_FRAME_MODE_ETHERTYPE,
1982 1983
				       MV88E6XXX_EGRESS_MODE_ETHERTYPE,
				       ETH_P_EDSA);
1984
}
1985

1986 1987 1988 1989
static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
{
	if (dsa_is_dsa_port(chip->ds, port))
		return mv88e6xxx_set_port_mode_dsa(chip, port);
1990

1991
	if (dsa_is_user_port(chip->ds, port))
1992
		return mv88e6xxx_set_port_mode_normal(chip, port);
1993

1994 1995 1996
	/* Setup CPU port mode depending on its supported tag format */
	if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
		return mv88e6xxx_set_port_mode_dsa(chip, port);
1997

1998 1999
	if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
		return mv88e6xxx_set_port_mode_edsa(chip, port);
2000

2001
	return -EINVAL;
2002 2003
}

2004
static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
2005
{
2006
	bool message = dsa_is_dsa_port(chip->ds, port);
2007

2008
	return mv88e6xxx_port_set_message_port(chip, port, message);
2009
}
2010

2011
static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
2012
{
2013 2014
	struct dsa_switch *ds = chip->ds;
	bool flood;
2015

2016
	/* Upstream ports flood frames with unknown unicast or multicast DA */
2017
	flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port);
2018 2019 2020
	if (chip->info->ops->port_set_egress_floods)
		return chip->info->ops->port_set_egress_floods(chip, port,
							       flood, flood);
2021

2022
	return 0;
2023 2024
}

2025 2026 2027
static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
				  bool on)
{
2028 2029
	if (chip->info->ops->serdes_power)
		return chip->info->ops->serdes_power(chip, port, on);
2030

2031
	return 0;
2032 2033
}

2034 2035 2036 2037 2038 2039
static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
{
	struct dsa_switch *ds = chip->ds;
	int upstream_port;
	int err;

2040
	upstream_port = dsa_upstream_port(ds, port);
2041 2042 2043 2044 2045 2046 2047
	if (chip->info->ops->port_set_upstream_port) {
		err = chip->info->ops->port_set_upstream_port(chip, port,
							      upstream_port);
		if (err)
			return err;
	}

2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063
	if (port == upstream_port) {
		if (chip->info->ops->set_cpu_port) {
			err = chip->info->ops->set_cpu_port(chip,
							    upstream_port);
			if (err)
				return err;
		}

		if (chip->info->ops->set_egress_port) {
			err = chip->info->ops->set_egress_port(chip,
							       upstream_port);
			if (err)
				return err;
		}
	}

2064 2065 2066
	return 0;
}

2067
static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2068
{
2069
	struct dsa_switch *ds = chip->ds;
2070
	int err;
2071
	u16 reg;
2072

2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086
	/* MAC Forcing register: don't force link, speed, duplex or flow control
	 * state to any particular values on physical ports, but force the CPU
	 * port and all DSA ports to their maximum bandwidth and full duplex.
	 */
	if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
		err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
					       SPEED_MAX, DUPLEX_FULL,
					       PHY_INTERFACE_MODE_NA);
	else
		err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
					       SPEED_UNFORCED, DUPLEX_UNFORCED,
					       PHY_INTERFACE_MODE_NA);
	if (err)
		return err;
2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101

	/* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
	 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
	 * tunneling, determine priority by looking at 802.1p and IP
	 * priority fields (IP prio has precedence), and set STP state
	 * to Forwarding.
	 *
	 * If this is the CPU link, use DSA or EDSA tagging depending
	 * on which tagging mode was configured.
	 *
	 * If this is a link to another switch, use DSA tagging mode.
	 *
	 * If this is the upstream port for this switch, enable
	 * forwarding of unknown unicasts and multicasts.
	 */
2102 2103 2104 2105
	reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
		MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
		MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
2106 2107
	if (err)
		return err;
2108

2109
	err = mv88e6xxx_setup_port_mode(chip, port);
2110 2111
	if (err)
		return err;
2112

2113
	err = mv88e6xxx_setup_egress_floods(chip, port);
2114 2115 2116
	if (err)
		return err;

2117 2118 2119
	/* Enable the SERDES interface for DSA and CPU ports. Normal
	 * ports SERDES are enabled when the port is enabled, thus
	 * saving a bit of power.
2120
	 */
2121 2122 2123 2124 2125
	if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) {
		err = mv88e6xxx_serdes_power(chip, port, true);
		if (err)
			return err;
	}
2126

2127
	/* Port Control 2: don't force a good FCS, set the maximum frame size to
2128
	 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2129 2130 2131
	 * untagged frames on this port, do a destination address lookup on all
	 * received packets as usual, disable ARP mirroring and don't send a
	 * copy of all transmitted/received frames on this port to the CPU.
2132
	 */
2133 2134 2135
	err = mv88e6xxx_port_set_map_da(chip, port);
	if (err)
		return err;
2136

2137 2138 2139
	err = mv88e6xxx_setup_upstream_port(chip, port);
	if (err)
		return err;
2140

2141
	err = mv88e6xxx_port_set_8021q_mode(chip, port,
2142
				MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
2143 2144 2145
	if (err)
		return err;

2146 2147
	if (chip->info->ops->port_set_jumbo_size) {
		err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
2148 2149 2150 2151
		if (err)
			return err;
	}

2152 2153 2154 2155 2156
	/* Port Association Vector: when learning source addresses
	 * of packets, add the address to the address database using
	 * a port bitmap that has only the bit for this port set and
	 * the other bits clear.
	 */
2157
	reg = 1 << port;
2158 2159
	/* Disable learning for CPU port */
	if (dsa_is_cpu_port(ds, port))
2160
		reg = 0;
2161

2162 2163
	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
				   reg);
2164 2165
	if (err)
		return err;
2166 2167

	/* Egress rate control 2: disable egress rate control. */
2168 2169
	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
				   0x0000);
2170 2171
	if (err)
		return err;
2172

2173 2174
	if (chip->info->ops->port_pause_limit) {
		err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
2175 2176
		if (err)
			return err;
2177
	}
2178

2179 2180 2181 2182 2183 2184
	if (chip->info->ops->port_disable_learn_limit) {
		err = chip->info->ops->port_disable_learn_limit(chip, port);
		if (err)
			return err;
	}

2185 2186
	if (chip->info->ops->port_disable_pri_override) {
		err = chip->info->ops->port_disable_pri_override(chip, port);
2187 2188
		if (err)
			return err;
2189
	}
2190

2191 2192
	if (chip->info->ops->port_tag_remap) {
		err = chip->info->ops->port_tag_remap(chip, port);
2193 2194
		if (err)
			return err;
2195 2196
	}

2197 2198
	if (chip->info->ops->port_egress_rate_limiting) {
		err = chip->info->ops->port_egress_rate_limiting(chip, port);
2199 2200
		if (err)
			return err;
2201 2202
	}

2203
	err = mv88e6xxx_setup_message_port(chip, port);
2204 2205
	if (err)
		return err;
2206

2207
	/* Port based VLAN map: give each port the same default address
2208 2209
	 * database, and allow bidirectional communication between the
	 * CPU and DSA port(s), and the other ports.
2210
	 */
2211
	err = mv88e6xxx_port_set_fid(chip, port, 0);
2212 2213
	if (err)
		return err;
2214

2215
	err = mv88e6xxx_port_vlan_map(chip, port);
2216 2217
	if (err)
		return err;
2218 2219 2220 2221

	/* Default VLAN ID and priority: don't set a default VLAN
	 * ID, and set the default packet priority to zero.
	 */
2222
	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
2223 2224
}

2225 2226 2227 2228
static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
				 struct phy_device *phydev)
{
	struct mv88e6xxx_chip *chip = ds->priv;
2229
	int err;
2230 2231

	mutex_lock(&chip->reg_lock);
2232
	err = mv88e6xxx_serdes_power(chip, port, true);
2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243
	mutex_unlock(&chip->reg_lock);

	return err;
}

static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port,
				   struct phy_device *phydev)
{
	struct mv88e6xxx_chip *chip = ds->priv;

	mutex_lock(&chip->reg_lock);
2244 2245
	if (mv88e6xxx_serdes_power(chip, port, false))
		dev_err(chip->dev, "failed to power off SERDES\n");
2246 2247 2248
	mutex_unlock(&chip->reg_lock);
}

2249 2250 2251
static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
				     unsigned int ageing_time)
{
V
Vivien Didelot 已提交
2252
	struct mv88e6xxx_chip *chip = ds->priv;
2253 2254 2255
	int err;

	mutex_lock(&chip->reg_lock);
2256
	err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2257 2258 2259 2260 2261
	mutex_unlock(&chip->reg_lock);

	return err;
}

2262
static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
2263
{
2264
	int err;
2265

2266
	/* Initialize the statistics unit */
2267 2268 2269 2270 2271
	if (chip->info->ops->stats_set_histogram) {
		err = chip->info->ops->stats_set_histogram(chip);
		if (err)
			return err;
	}
2272

2273
	return mv88e6xxx_g1_stats_clear(chip);
2274 2275
}

2276
static int mv88e6xxx_setup(struct dsa_switch *ds)
2277
{
V
Vivien Didelot 已提交
2278
	struct mv88e6xxx_chip *chip = ds->priv;
2279
	int err;
2280 2281
	int i;

2282
	chip->ds = ds;
2283
	ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
2284

2285
	mutex_lock(&chip->reg_lock);
2286

2287
	/* Setup Switch Port Registers */
2288
	for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2289 2290 2291
		if (dsa_is_unused_port(ds, i))
			continue;

2292 2293 2294 2295 2296
		err = mv88e6xxx_setup_port(chip, i);
		if (err)
			goto unlock;
	}

2297 2298 2299 2300
	err = mv88e6xxx_irl_setup(chip);
	if (err)
		goto unlock;

2301 2302 2303 2304
	err = mv88e6xxx_mac_setup(chip);
	if (err)
		goto unlock;

2305 2306 2307 2308
	err = mv88e6xxx_phy_setup(chip);
	if (err)
		goto unlock;

2309 2310 2311 2312
	err = mv88e6xxx_vtu_setup(chip);
	if (err)
		goto unlock;

2313 2314 2315 2316
	err = mv88e6xxx_pvt_setup(chip);
	if (err)
		goto unlock;

2317 2318 2319 2320
	err = mv88e6xxx_atu_setup(chip);
	if (err)
		goto unlock;

2321 2322 2323 2324
	err = mv88e6xxx_broadcast_setup(chip, 0);
	if (err)
		goto unlock;

2325 2326 2327 2328
	err = mv88e6xxx_pot_setup(chip);
	if (err)
		goto unlock;

2329 2330 2331 2332
	err = mv88e6xxx_rmu_setup(chip);
	if (err)
		goto unlock;

2333 2334 2335
	err = mv88e6xxx_rsvd2cpu_setup(chip);
	if (err)
		goto unlock;
2336

2337 2338 2339 2340
	err = mv88e6xxx_trunk_setup(chip);
	if (err)
		goto unlock;

2341 2342 2343 2344
	err = mv88e6xxx_devmap_setup(chip);
	if (err)
		goto unlock;

2345 2346 2347 2348
	err = mv88e6xxx_pri_setup(chip);
	if (err)
		goto unlock;

2349
	/* Setup PTP Hardware Clock and timestamping */
2350 2351 2352 2353
	if (chip->info->ptp_support) {
		err = mv88e6xxx_ptp_setup(chip);
		if (err)
			goto unlock;
2354 2355 2356 2357

		err = mv88e6xxx_hwtstamp_setup(chip);
		if (err)
			goto unlock;
2358 2359
	}

2360 2361 2362 2363
	err = mv88e6xxx_stats_setup(chip);
	if (err)
		goto unlock;

2364
unlock:
2365
	mutex_unlock(&chip->reg_lock);
2366

2367
	return err;
2368 2369
}

2370
static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
2371
{
2372 2373
	struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
	struct mv88e6xxx_chip *chip = mdio_bus->chip;
2374 2375
	u16 val;
	int err;
2376

2377 2378 2379
	if (!chip->info->ops->phy_read)
		return -EOPNOTSUPP;

2380
	mutex_lock(&chip->reg_lock);
2381
	err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
2382
	mutex_unlock(&chip->reg_lock);
2383

2384 2385 2386 2387 2388
	if (reg == MII_PHYSID2) {
		/* Some internal PHYS don't have a model number.  Use
		 * the mv88e6390 family model number instead.
		 */
		if (!(val & 0x3f0))
2389
			val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
2390 2391
	}

2392
	return err ? err : val;
2393 2394
}

2395
static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
2396
{
2397 2398
	struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
	struct mv88e6xxx_chip *chip = mdio_bus->chip;
2399
	int err;
2400

2401 2402 2403
	if (!chip->info->ops->phy_write)
		return -EOPNOTSUPP;

2404
	mutex_lock(&chip->reg_lock);
2405
	err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
2406
	mutex_unlock(&chip->reg_lock);
2407 2408

	return err;
2409 2410
}

2411
static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
2412 2413
				   struct device_node *np,
				   bool external)
2414 2415
{
	static int index;
2416
	struct mv88e6xxx_mdio_bus *mdio_bus;
2417 2418 2419
	struct mii_bus *bus;
	int err;

2420 2421 2422 2423 2424 2425 2426 2427 2428
	if (external) {
		mutex_lock(&chip->reg_lock);
		err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
		mutex_unlock(&chip->reg_lock);

		if (err)
			return err;
	}

2429
	bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
2430 2431 2432
	if (!bus)
		return -ENOMEM;

2433
	mdio_bus = bus->priv;
2434
	mdio_bus->bus = bus;
2435
	mdio_bus->chip = chip;
2436 2437
	INIT_LIST_HEAD(&mdio_bus->list);
	mdio_bus->external = external;
2438

2439 2440
	if (np) {
		bus->name = np->full_name;
2441
		snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
2442 2443 2444 2445 2446 2447 2448
	} else {
		bus->name = "mv88e6xxx SMI";
		snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
	}

	bus->read = mv88e6xxx_mdio_read;
	bus->write = mv88e6xxx_mdio_write;
2449
	bus->parent = chip->dev;
2450

2451 2452 2453 2454 2455 2456
	if (!external) {
		err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
		if (err)
			return err;
	}

2457 2458
	if (np)
		err = of_mdiobus_register(bus, np);
2459 2460 2461
	else
		err = mdiobus_register(bus);
	if (err) {
2462
		dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
2463
		mv88e6xxx_g2_irq_mdio_free(chip, bus);
2464
		return err;
2465
	}
2466 2467 2468 2469 2470

	if (external)
		list_add_tail(&mdio_bus->list, &chip->mdios);
	else
		list_add(&mdio_bus->list, &chip->mdios);
2471 2472

	return 0;
2473
}
2474

2475 2476 2477 2478 2479
static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
	{ .compatible = "marvell,mv88e6xxx-mdio-external",
	  .data = (void *)true },
	{ },
};
2480

2481 2482 2483 2484 2485 2486 2487 2488 2489
static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)

{
	struct mv88e6xxx_mdio_bus *mdio_bus;
	struct mii_bus *bus;

	list_for_each_entry(mdio_bus, &chip->mdios, list) {
		bus = mdio_bus->bus;

2490 2491 2492
		if (!mdio_bus->external)
			mv88e6xxx_g2_irq_mdio_free(chip, bus);

2493 2494 2495 2496
		mdiobus_unregister(bus);
	}
}

2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520
static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
				    struct device_node *np)
{
	const struct of_device_id *match;
	struct device_node *child;
	int err;

	/* Always register one mdio bus for the internal/default mdio
	 * bus. This maybe represented in the device tree, but is
	 * optional.
	 */
	child = of_get_child_by_name(np, "mdio");
	err = mv88e6xxx_mdio_register(chip, child, false);
	if (err)
		return err;

	/* Walk the device tree, and see if there are any other nodes
	 * which say they are compatible with the external mdio
	 * bus.
	 */
	for_each_available_child_of_node(np, child) {
		match = of_match_node(mv88e6xxx_mdio_external_match, child);
		if (match) {
			err = mv88e6xxx_mdio_register(chip, child, true);
2521 2522
			if (err) {
				mv88e6xxx_mdios_unregister(chip);
2523
				return err;
2524
			}
2525 2526 2527 2528
		}
	}

	return 0;
2529 2530
}

2531 2532
static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
{
V
Vivien Didelot 已提交
2533
	struct mv88e6xxx_chip *chip = ds->priv;
2534 2535 2536 2537 2538 2539 2540

	return chip->eeprom_len;
}

static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
				struct ethtool_eeprom *eeprom, u8 *data)
{
V
Vivien Didelot 已提交
2541
	struct mv88e6xxx_chip *chip = ds->priv;
2542 2543
	int err;

2544 2545
	if (!chip->info->ops->get_eeprom)
		return -EOPNOTSUPP;
2546

2547 2548
	mutex_lock(&chip->reg_lock);
	err = chip->info->ops->get_eeprom(chip, eeprom, data);
2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561
	mutex_unlock(&chip->reg_lock);

	if (err)
		return err;

	eeprom->magic = 0xc3ec4951;

	return 0;
}

static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
				struct ethtool_eeprom *eeprom, u8 *data)
{
V
Vivien Didelot 已提交
2562
	struct mv88e6xxx_chip *chip = ds->priv;
2563 2564
	int err;

2565 2566 2567
	if (!chip->info->ops->set_eeprom)
		return -EOPNOTSUPP;

2568 2569 2570 2571
	if (eeprom->magic != 0xc3ec4951)
		return -EINVAL;

	mutex_lock(&chip->reg_lock);
2572
	err = chip->info->ops->set_eeprom(chip, eeprom, data);
2573 2574 2575 2576 2577
	mutex_unlock(&chip->reg_lock);

	return err;
}

2578
static const struct mv88e6xxx_ops mv88e6085_ops = {
2579
	/* MV88E6XXX_FAMILY_6097 */
2580 2581
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2582
	.irl_init_all = mv88e6352_g2_irl_init_all,
2583
	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2584 2585
	.phy_read = mv88e6185_phy_ppu_read,
	.phy_write = mv88e6185_phy_ppu_write,
2586
	.port_set_link = mv88e6xxx_port_set_link,
2587
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2588
	.port_set_speed = mv88e6185_port_set_speed,
2589
	.port_tag_remap = mv88e6095_port_tag_remap,
2590
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2591
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2592
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2593
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2594
	.port_pause_limit = mv88e6097_port_pause_limit,
2595
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2596
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2597
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2598
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2599 2600
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2601
	.stats_get_stats = mv88e6095_stats_get_stats,
2602 2603
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2604
	.watchdog_ops = &mv88e6097_watchdog_ops,
2605
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2606
	.pot_clear = mv88e6xxx_g2_pot_clear,
2607 2608
	.ppu_enable = mv88e6185_g1_ppu_enable,
	.ppu_disable = mv88e6185_g1_ppu_disable,
2609
	.reset = mv88e6185_g1_reset,
2610
	.rmu_disable = mv88e6085_g1_rmu_disable,
2611
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2612
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2613
	.serdes_power = mv88e6341_serdes_power,
2614 2615 2616
};

static const struct mv88e6xxx_ops mv88e6095_ops = {
2617
	/* MV88E6XXX_FAMILY_6095 */
2618 2619
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2620
	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2621 2622
	.phy_read = mv88e6185_phy_ppu_read,
	.phy_write = mv88e6185_phy_ppu_write,
2623
	.port_set_link = mv88e6xxx_port_set_link,
2624
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2625
	.port_set_speed = mv88e6185_port_set_speed,
2626
	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
2627
	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
2628
	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
2629
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2630
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2631 2632
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2633
	.stats_get_stats = mv88e6095_stats_get_stats,
2634
	.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2635 2636
	.ppu_enable = mv88e6185_g1_ppu_enable,
	.ppu_disable = mv88e6185_g1_ppu_disable,
2637
	.reset = mv88e6185_g1_reset,
2638
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
2639
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2640 2641
};

2642
static const struct mv88e6xxx_ops mv88e6097_ops = {
2643
	/* MV88E6XXX_FAMILY_6097 */
2644 2645
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2646
	.irl_init_all = mv88e6352_g2_irl_init_all,
2647 2648 2649 2650 2651 2652
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_speed = mv88e6185_port_set_speed,
2653
	.port_tag_remap = mv88e6095_port_tag_remap,
2654
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2655
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2656
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2657
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2658
	.port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2659
	.port_pause_limit = mv88e6097_port_pause_limit,
2660
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2661
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2662
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2663
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2664 2665 2666
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
	.stats_get_stats = mv88e6095_stats_get_stats,
2667 2668
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2669
	.watchdog_ops = &mv88e6097_watchdog_ops,
2670
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2671
	.pot_clear = mv88e6xxx_g2_pot_clear,
2672
	.reset = mv88e6352_g1_reset,
2673
	.rmu_disable = mv88e6085_g1_rmu_disable,
2674
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2675
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2676 2677
};

2678
static const struct mv88e6xxx_ops mv88e6123_ops = {
2679
	/* MV88E6XXX_FAMILY_6165 */
2680 2681
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2682
	.irl_init_all = mv88e6352_g2_irl_init_all,
2683
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2684 2685
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2686
	.port_set_link = mv88e6xxx_port_set_link,
2687
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2688
	.port_set_speed = mv88e6185_port_set_speed,
2689
	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
2690
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2691
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2692
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2693
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2694
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2695 2696
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2697
	.stats_get_stats = mv88e6095_stats_get_stats,
2698 2699
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2700
	.watchdog_ops = &mv88e6097_watchdog_ops,
2701
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2702
	.pot_clear = mv88e6xxx_g2_pot_clear,
2703
	.reset = mv88e6352_g1_reset,
2704
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2705
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2706 2707 2708
};

static const struct mv88e6xxx_ops mv88e6131_ops = {
2709
	/* MV88E6XXX_FAMILY_6185 */
2710 2711
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2712
	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2713 2714
	.phy_read = mv88e6185_phy_ppu_read,
	.phy_write = mv88e6185_phy_ppu_write,
2715
	.port_set_link = mv88e6xxx_port_set_link,
2716
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2717
	.port_set_speed = mv88e6185_port_set_speed,
2718
	.port_tag_remap = mv88e6095_port_tag_remap,
2719
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2720
	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
2721
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2722
	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
2723
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2724
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2725
	.port_pause_limit = mv88e6097_port_pause_limit,
2726
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2727
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2728 2729
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2730
	.stats_get_stats = mv88e6095_stats_get_stats,
2731 2732
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2733
	.watchdog_ops = &mv88e6097_watchdog_ops,
2734
	.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2735
	.ppu_enable = mv88e6185_g1_ppu_enable,
2736
	.set_cascade_port = mv88e6185_g1_set_cascade_port,
2737
	.ppu_disable = mv88e6185_g1_ppu_disable,
2738
	.reset = mv88e6185_g1_reset,
2739
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
2740
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2741 2742
};

2743 2744
static const struct mv88e6xxx_ops mv88e6141_ops = {
	/* MV88E6XXX_FAMILY_6341 */
2745 2746
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2747
	.irl_init_all = mv88e6352_g2_irl_init_all,
2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758 2759 2760
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
	.port_tag_remap = mv88e6095_port_tag_remap,
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2761
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2762
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2763
	.port_pause_limit = mv88e6097_port_pause_limit,
2764 2765 2766
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
2767
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2768 2769 2770
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
	.stats_get_stats = mv88e6390_stats_get_stats,
2771 2772
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
2773 2774
	.watchdog_ops = &mv88e6390_watchdog_ops,
	.mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
2775
	.pot_clear = mv88e6xxx_g2_pot_clear,
2776
	.reset = mv88e6352_g1_reset,
2777
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2778
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2779
	.gpio_ops = &mv88e6352_gpio_ops,
2780 2781
};

2782
static const struct mv88e6xxx_ops mv88e6161_ops = {
2783
	/* MV88E6XXX_FAMILY_6165 */
2784 2785
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2786
	.irl_init_all = mv88e6352_g2_irl_init_all,
2787
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2788 2789
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2790
	.port_set_link = mv88e6xxx_port_set_link,
2791
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2792
	.port_set_speed = mv88e6185_port_set_speed,
2793
	.port_tag_remap = mv88e6095_port_tag_remap,
2794
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2795
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2796
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2797
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2798
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2799
	.port_pause_limit = mv88e6097_port_pause_limit,
2800
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2801
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2802
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2803
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2804 2805
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2806
	.stats_get_stats = mv88e6095_stats_get_stats,
2807 2808
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2809
	.watchdog_ops = &mv88e6097_watchdog_ops,
2810
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2811
	.pot_clear = mv88e6xxx_g2_pot_clear,
2812
	.reset = mv88e6352_g1_reset,
2813
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2814
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2815 2816 2817
};

static const struct mv88e6xxx_ops mv88e6165_ops = {
2818
	/* MV88E6XXX_FAMILY_6165 */
2819 2820
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2821
	.irl_init_all = mv88e6352_g2_irl_init_all,
2822
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2823 2824
	.phy_read = mv88e6165_phy_read,
	.phy_write = mv88e6165_phy_write,
2825
	.port_set_link = mv88e6xxx_port_set_link,
2826
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2827
	.port_set_speed = mv88e6185_port_set_speed,
2828
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2829
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2830
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2831
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2832 2833
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2834
	.stats_get_stats = mv88e6095_stats_get_stats,
2835 2836
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2837
	.watchdog_ops = &mv88e6097_watchdog_ops,
2838
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2839
	.pot_clear = mv88e6xxx_g2_pot_clear,
2840
	.reset = mv88e6352_g1_reset,
2841
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2842
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2843 2844 2845
};

static const struct mv88e6xxx_ops mv88e6171_ops = {
2846
	/* MV88E6XXX_FAMILY_6351 */
2847 2848
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2849
	.irl_init_all = mv88e6352_g2_irl_init_all,
2850
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2851 2852
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2853
	.port_set_link = mv88e6xxx_port_set_link,
2854
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2855
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2856
	.port_set_speed = mv88e6185_port_set_speed,
2857
	.port_tag_remap = mv88e6095_port_tag_remap,
2858
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2859
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2860
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2861
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2862
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2863
	.port_pause_limit = mv88e6097_port_pause_limit,
2864
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2865
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2866
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2867
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2868 2869
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2870
	.stats_get_stats = mv88e6095_stats_get_stats,
2871 2872
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2873
	.watchdog_ops = &mv88e6097_watchdog_ops,
2874
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2875
	.pot_clear = mv88e6xxx_g2_pot_clear,
2876
	.reset = mv88e6352_g1_reset,
2877
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2878
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2879 2880 2881
};

static const struct mv88e6xxx_ops mv88e6172_ops = {
2882
	/* MV88E6XXX_FAMILY_6352 */
2883 2884
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2885
	.irl_init_all = mv88e6352_g2_irl_init_all,
2886 2887
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
2888
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2889 2890
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2891
	.port_set_link = mv88e6xxx_port_set_link,
2892
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2893
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2894
	.port_set_speed = mv88e6352_port_set_speed,
2895
	.port_tag_remap = mv88e6095_port_tag_remap,
2896
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2897
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2898
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2899
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2900
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2901
	.port_pause_limit = mv88e6097_port_pause_limit,
2902
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2903
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2904
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2905
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2906 2907
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2908
	.stats_get_stats = mv88e6095_stats_get_stats,
2909 2910
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2911
	.watchdog_ops = &mv88e6097_watchdog_ops,
2912
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2913
	.pot_clear = mv88e6xxx_g2_pot_clear,
2914
	.reset = mv88e6352_g1_reset,
2915
	.rmu_disable = mv88e6352_g1_rmu_disable,
2916
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2917
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2918
	.serdes_power = mv88e6352_serdes_power,
2919
	.gpio_ops = &mv88e6352_gpio_ops,
2920 2921 2922
};

static const struct mv88e6xxx_ops mv88e6175_ops = {
2923
	/* MV88E6XXX_FAMILY_6351 */
2924 2925
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2926
	.irl_init_all = mv88e6352_g2_irl_init_all,
2927
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2928 2929
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2930
	.port_set_link = mv88e6xxx_port_set_link,
2931
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2932
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2933
	.port_set_speed = mv88e6185_port_set_speed,
2934
	.port_tag_remap = mv88e6095_port_tag_remap,
2935
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2936
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2937
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2938
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2939
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2940
	.port_pause_limit = mv88e6097_port_pause_limit,
2941
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2942
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2943
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2944
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2945 2946
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2947
	.stats_get_stats = mv88e6095_stats_get_stats,
2948 2949
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2950
	.watchdog_ops = &mv88e6097_watchdog_ops,
2951
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2952
	.pot_clear = mv88e6xxx_g2_pot_clear,
2953
	.reset = mv88e6352_g1_reset,
2954
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2955
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2956
	.serdes_power = mv88e6341_serdes_power,
2957 2958 2959
};

static const struct mv88e6xxx_ops mv88e6176_ops = {
2960
	/* MV88E6XXX_FAMILY_6352 */
2961 2962
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2963
	.irl_init_all = mv88e6352_g2_irl_init_all,
2964 2965
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
2966
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2967 2968
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2969
	.port_set_link = mv88e6xxx_port_set_link,
2970
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2971
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2972
	.port_set_speed = mv88e6352_port_set_speed,
2973
	.port_tag_remap = mv88e6095_port_tag_remap,
2974
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2975
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2976
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2977
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2978
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2979
	.port_pause_limit = mv88e6097_port_pause_limit,
2980
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2981
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2982
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2983
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2984 2985
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2986
	.stats_get_stats = mv88e6095_stats_get_stats,
2987 2988
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2989
	.watchdog_ops = &mv88e6097_watchdog_ops,
2990
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2991
	.pot_clear = mv88e6xxx_g2_pot_clear,
2992
	.reset = mv88e6352_g1_reset,
2993
	.rmu_disable = mv88e6352_g1_rmu_disable,
2994
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2995
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2996
	.serdes_power = mv88e6352_serdes_power,
2997
	.gpio_ops = &mv88e6352_gpio_ops,
2998 2999 3000
};

static const struct mv88e6xxx_ops mv88e6185_ops = {
3001
	/* MV88E6XXX_FAMILY_6185 */
3002 3003
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3004
	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3005 3006
	.phy_read = mv88e6185_phy_ppu_read,
	.phy_write = mv88e6185_phy_ppu_write,
3007
	.port_set_link = mv88e6xxx_port_set_link,
3008
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3009
	.port_set_speed = mv88e6185_port_set_speed,
3010
	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
3011
	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
3012
	.port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3013
	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
3014
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3015
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3016 3017
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
3018
	.stats_get_stats = mv88e6095_stats_get_stats,
3019 3020
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3021
	.watchdog_ops = &mv88e6097_watchdog_ops,
3022
	.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3023
	.set_cascade_port = mv88e6185_g1_set_cascade_port,
3024 3025
	.ppu_enable = mv88e6185_g1_ppu_enable,
	.ppu_disable = mv88e6185_g1_ppu_disable,
3026
	.reset = mv88e6185_g1_reset,
3027
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
3028
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3029 3030
};

3031
static const struct mv88e6xxx_ops mv88e6190_ops = {
3032
	/* MV88E6XXX_FAMILY_6390 */
3033
	.irl_init_all = mv88e6390_g2_irl_init_all,
3034 3035
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3036 3037 3038 3039 3040 3041 3042
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
3043
	.port_tag_remap = mv88e6390_port_tag_remap,
3044
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3045
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3046
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3047
	.port_pause_limit = mv88e6390_port_pause_limit,
3048
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3049
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3050
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3051
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3052 3053
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3054
	.stats_get_stats = mv88e6390_stats_get_stats,
3055 3056
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3057
	.watchdog_ops = &mv88e6390_watchdog_ops,
3058
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3059
	.pot_clear = mv88e6xxx_g2_pot_clear,
3060
	.reset = mv88e6352_g1_reset,
3061
	.rmu_disable = mv88e6390_g1_rmu_disable,
3062 3063
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3064
	.serdes_power = mv88e6390_serdes_power,
3065
	.gpio_ops = &mv88e6352_gpio_ops,
3066 3067 3068
};

static const struct mv88e6xxx_ops mv88e6190x_ops = {
3069
	/* MV88E6XXX_FAMILY_6390 */
3070
	.irl_init_all = mv88e6390_g2_irl_init_all,
3071 3072
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3073 3074 3075 3076 3077 3078 3079
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390x_port_set_speed,
3080
	.port_tag_remap = mv88e6390_port_tag_remap,
3081
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3082
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3083
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3084
	.port_pause_limit = mv88e6390_port_pause_limit,
3085
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3086
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3087
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3088
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3089 3090
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3091
	.stats_get_stats = mv88e6390_stats_get_stats,
3092 3093
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3094
	.watchdog_ops = &mv88e6390_watchdog_ops,
3095
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3096
	.pot_clear = mv88e6xxx_g2_pot_clear,
3097
	.reset = mv88e6352_g1_reset,
3098
	.rmu_disable = mv88e6390_g1_rmu_disable,
3099 3100
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3101
	.serdes_power = mv88e6390_serdes_power,
3102
	.gpio_ops = &mv88e6352_gpio_ops,
3103 3104 3105
};

static const struct mv88e6xxx_ops mv88e6191_ops = {
3106
	/* MV88E6XXX_FAMILY_6390 */
3107
	.irl_init_all = mv88e6390_g2_irl_init_all,
3108 3109
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3110 3111 3112 3113 3114 3115 3116
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
3117
	.port_tag_remap = mv88e6390_port_tag_remap,
3118
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3119
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3120
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3121
	.port_pause_limit = mv88e6390_port_pause_limit,
3122
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3123
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3124
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3125
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3126 3127
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3128
	.stats_get_stats = mv88e6390_stats_get_stats,
3129 3130
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3131
	.watchdog_ops = &mv88e6390_watchdog_ops,
3132
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3133
	.pot_clear = mv88e6xxx_g2_pot_clear,
3134
	.reset = mv88e6352_g1_reset,
3135
	.rmu_disable = mv88e6390_g1_rmu_disable,
3136 3137
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3138
	.serdes_power = mv88e6390_serdes_power,
3139 3140
};

3141
static const struct mv88e6xxx_ops mv88e6240_ops = {
3142
	/* MV88E6XXX_FAMILY_6352 */
3143 3144
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3145
	.irl_init_all = mv88e6352_g2_irl_init_all,
3146 3147
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
3148
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3149 3150
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3151
	.port_set_link = mv88e6xxx_port_set_link,
3152
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3153
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3154
	.port_set_speed = mv88e6352_port_set_speed,
3155
	.port_tag_remap = mv88e6095_port_tag_remap,
3156
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3157
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3158
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3159
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3160
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3161
	.port_pause_limit = mv88e6097_port_pause_limit,
3162
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3163
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3164
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3165
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3166 3167
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
3168
	.stats_get_stats = mv88e6095_stats_get_stats,
3169 3170
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3171
	.watchdog_ops = &mv88e6097_watchdog_ops,
3172
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3173
	.pot_clear = mv88e6xxx_g2_pot_clear,
3174
	.reset = mv88e6352_g1_reset,
3175
	.rmu_disable = mv88e6352_g1_rmu_disable,
3176
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3177
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3178
	.serdes_power = mv88e6352_serdes_power,
3179
	.gpio_ops = &mv88e6352_gpio_ops,
3180
	.avb_ops = &mv88e6352_avb_ops,
3181 3182
};

3183
static const struct mv88e6xxx_ops mv88e6290_ops = {
3184
	/* MV88E6XXX_FAMILY_6390 */
3185
	.irl_init_all = mv88e6390_g2_irl_init_all,
3186 3187
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3188 3189 3190 3191 3192 3193 3194
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
3195
	.port_tag_remap = mv88e6390_port_tag_remap,
3196
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3197
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3198
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3199
	.port_pause_limit = mv88e6390_port_pause_limit,
3200
	.port_set_cmode = mv88e6390x_port_set_cmode,
3201
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3202
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3203
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3204
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3205 3206
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3207
	.stats_get_stats = mv88e6390_stats_get_stats,
3208 3209
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3210
	.watchdog_ops = &mv88e6390_watchdog_ops,
3211
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3212
	.pot_clear = mv88e6xxx_g2_pot_clear,
3213
	.reset = mv88e6352_g1_reset,
3214
	.rmu_disable = mv88e6390_g1_rmu_disable,
3215 3216
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3217
	.serdes_power = mv88e6390_serdes_power,
3218
	.gpio_ops = &mv88e6352_gpio_ops,
3219
	.avb_ops = &mv88e6390_avb_ops,
3220 3221
};

3222
static const struct mv88e6xxx_ops mv88e6320_ops = {
3223
	/* MV88E6XXX_FAMILY_6320 */
3224 3225
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3226
	.irl_init_all = mv88e6352_g2_irl_init_all,
3227 3228
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
3229
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3230 3231
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3232
	.port_set_link = mv88e6xxx_port_set_link,
3233
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3234
	.port_set_speed = mv88e6185_port_set_speed,
3235
	.port_tag_remap = mv88e6095_port_tag_remap,
3236
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3237
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3238
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3239
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3240
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3241
	.port_pause_limit = mv88e6097_port_pause_limit,
3242
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3243
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3244
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3245
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3246 3247
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3248
	.stats_get_stats = mv88e6320_stats_get_stats,
3249 3250
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3251
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3252
	.pot_clear = mv88e6xxx_g2_pot_clear,
3253
	.reset = mv88e6352_g1_reset,
3254
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
3255
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3256
	.gpio_ops = &mv88e6352_gpio_ops,
3257
	.avb_ops = &mv88e6352_avb_ops,
3258 3259 3260
};

static const struct mv88e6xxx_ops mv88e6321_ops = {
3261
	/* MV88E6XXX_FAMILY_6320 */
3262 3263
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3264
	.irl_init_all = mv88e6352_g2_irl_init_all,
3265 3266
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
3267
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3268 3269
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3270
	.port_set_link = mv88e6xxx_port_set_link,
3271
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3272
	.port_set_speed = mv88e6185_port_set_speed,
3273
	.port_tag_remap = mv88e6095_port_tag_remap,
3274
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3275
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3276
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3277
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3278
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3279
	.port_pause_limit = mv88e6097_port_pause_limit,
3280
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3281
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3282
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3283
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3284 3285
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3286
	.stats_get_stats = mv88e6320_stats_get_stats,
3287 3288
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3289
	.reset = mv88e6352_g1_reset,
3290
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
3291
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3292
	.gpio_ops = &mv88e6352_gpio_ops,
3293
	.avb_ops = &mv88e6352_avb_ops,
3294 3295
};

3296 3297
static const struct mv88e6xxx_ops mv88e6341_ops = {
	/* MV88E6XXX_FAMILY_6341 */
3298 3299
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3300
	.irl_init_all = mv88e6352_g2_irl_init_all,
3301 3302 3303 3304 3305 3306 3307 3308 3309 3310 3311 3312 3313
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
	.port_tag_remap = mv88e6095_port_tag_remap,
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3314
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3315
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3316
	.port_pause_limit = mv88e6097_port_pause_limit,
3317 3318 3319
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3320
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3321 3322 3323
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
	.stats_get_stats = mv88e6390_stats_get_stats,
3324 3325
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3326 3327
	.watchdog_ops = &mv88e6390_watchdog_ops,
	.mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
3328
	.pot_clear = mv88e6xxx_g2_pot_clear,
3329
	.reset = mv88e6352_g1_reset,
3330
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3331
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3332
	.gpio_ops = &mv88e6352_gpio_ops,
3333
	.avb_ops = &mv88e6390_avb_ops,
3334 3335
};

3336
static const struct mv88e6xxx_ops mv88e6350_ops = {
3337
	/* MV88E6XXX_FAMILY_6351 */
3338 3339
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3340
	.irl_init_all = mv88e6352_g2_irl_init_all,
3341
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3342 3343
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3344
	.port_set_link = mv88e6xxx_port_set_link,
3345
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3346
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3347
	.port_set_speed = mv88e6185_port_set_speed,
3348
	.port_tag_remap = mv88e6095_port_tag_remap,
3349
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3350
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3351
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3352
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3353
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3354
	.port_pause_limit = mv88e6097_port_pause_limit,
3355
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3356
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3357
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3358
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3359 3360
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
3361
	.stats_get_stats = mv88e6095_stats_get_stats,
3362 3363
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3364
	.watchdog_ops = &mv88e6097_watchdog_ops,
3365
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3366
	.pot_clear = mv88e6xxx_g2_pot_clear,
3367
	.reset = mv88e6352_g1_reset,
3368
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3369
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3370 3371 3372
};

static const struct mv88e6xxx_ops mv88e6351_ops = {
3373
	/* MV88E6XXX_FAMILY_6351 */
3374 3375
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3376
	.irl_init_all = mv88e6352_g2_irl_init_all,
3377
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3378 3379
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3380
	.port_set_link = mv88e6xxx_port_set_link,
3381
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3382
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3383
	.port_set_speed = mv88e6185_port_set_speed,
3384
	.port_tag_remap = mv88e6095_port_tag_remap,
3385
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3386
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3387
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3388
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3389
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3390
	.port_pause_limit = mv88e6097_port_pause_limit,
3391
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3392
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3393
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3394
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3395 3396
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
3397
	.stats_get_stats = mv88e6095_stats_get_stats,
3398 3399
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3400
	.watchdog_ops = &mv88e6097_watchdog_ops,
3401
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3402
	.pot_clear = mv88e6xxx_g2_pot_clear,
3403
	.reset = mv88e6352_g1_reset,
3404
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3405
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3406
	.avb_ops = &mv88e6352_avb_ops,
3407 3408 3409
};

static const struct mv88e6xxx_ops mv88e6352_ops = {
3410
	/* MV88E6XXX_FAMILY_6352 */
3411 3412
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3413
	.irl_init_all = mv88e6352_g2_irl_init_all,
3414 3415
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
3416
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3417 3418
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3419
	.port_set_link = mv88e6xxx_port_set_link,
3420
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3421
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3422
	.port_set_speed = mv88e6352_port_set_speed,
3423
	.port_tag_remap = mv88e6095_port_tag_remap,
3424
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3425
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3426
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3427
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3428
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3429
	.port_pause_limit = mv88e6097_port_pause_limit,
3430
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3431
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3432
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3433
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3434 3435
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
3436
	.stats_get_stats = mv88e6095_stats_get_stats,
3437 3438
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3439
	.watchdog_ops = &mv88e6097_watchdog_ops,
3440
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3441
	.pot_clear = mv88e6xxx_g2_pot_clear,
3442
	.reset = mv88e6352_g1_reset,
3443
	.rmu_disable = mv88e6352_g1_rmu_disable,
3444
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3445
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3446
	.serdes_power = mv88e6352_serdes_power,
3447
	.gpio_ops = &mv88e6352_gpio_ops,
3448
	.avb_ops = &mv88e6352_avb_ops,
3449 3450 3451
	.serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
	.serdes_get_strings = mv88e6352_serdes_get_strings,
	.serdes_get_stats = mv88e6352_serdes_get_stats,
3452 3453
};

3454
static const struct mv88e6xxx_ops mv88e6390_ops = {
3455
	/* MV88E6XXX_FAMILY_6390 */
3456
	.irl_init_all = mv88e6390_g2_irl_init_all,
3457 3458
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3459 3460 3461 3462 3463 3464 3465
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
3466
	.port_tag_remap = mv88e6390_port_tag_remap,
3467
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3468
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3469
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3470
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3471
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3472
	.port_pause_limit = mv88e6390_port_pause_limit,
3473
	.port_set_cmode = mv88e6390x_port_set_cmode,
3474
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3475
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3476
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3477
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3478 3479
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3480
	.stats_get_stats = mv88e6390_stats_get_stats,
3481 3482
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3483
	.watchdog_ops = &mv88e6390_watchdog_ops,
3484
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3485
	.pot_clear = mv88e6xxx_g2_pot_clear,
3486
	.reset = mv88e6352_g1_reset,
3487
	.rmu_disable = mv88e6390_g1_rmu_disable,
3488 3489
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3490
	.serdes_power = mv88e6390_serdes_power,
3491
	.gpio_ops = &mv88e6352_gpio_ops,
3492
	.avb_ops = &mv88e6390_avb_ops,
3493 3494 3495
};

static const struct mv88e6xxx_ops mv88e6390x_ops = {
3496
	/* MV88E6XXX_FAMILY_6390 */
3497
	.irl_init_all = mv88e6390_g2_irl_init_all,
3498 3499
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3500 3501 3502 3503 3504 3505 3506
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390x_port_set_speed,
3507
	.port_tag_remap = mv88e6390_port_tag_remap,
3508
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3509
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3510
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3511
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3512
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3513
	.port_pause_limit = mv88e6390_port_pause_limit,
3514
	.port_set_cmode = mv88e6390x_port_set_cmode,
3515
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3516
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3517
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3518
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3519 3520
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3521
	.stats_get_stats = mv88e6390_stats_get_stats,
3522 3523
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3524
	.watchdog_ops = &mv88e6390_watchdog_ops,
3525
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3526
	.pot_clear = mv88e6xxx_g2_pot_clear,
3527
	.reset = mv88e6352_g1_reset,
3528
	.rmu_disable = mv88e6390_g1_rmu_disable,
3529 3530
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3531
	.serdes_power = mv88e6390_serdes_power,
3532
	.gpio_ops = &mv88e6352_gpio_ops,
3533
	.avb_ops = &mv88e6390_avb_ops,
3534 3535
};

3536 3537
static const struct mv88e6xxx_info mv88e6xxx_table[] = {
	[MV88E6085] = {
3538
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
3539 3540 3541 3542
		.family = MV88E6XXX_FAMILY_6097,
		.name = "Marvell 88E6085",
		.num_databases = 4096,
		.num_ports = 10,
3543
		.num_internal_phys = 5,
3544
		.max_vid = 4095,
3545
		.port_base_addr = 0x10,
3546
		.phy_base_addr = 0x0,
3547
		.global1_addr = 0x1b,
3548
		.global2_addr = 0x1c,
3549
		.age_time_coeff = 15000,
3550
		.g1_irqs = 8,
3551
		.g2_irqs = 10,
3552
		.atu_move_port_mask = 0xf,
3553
		.pvt = true,
3554
		.multi_chip = true,
3555
		.tag_protocol = DSA_TAG_PROTO_DSA,
3556
		.ops = &mv88e6085_ops,
3557 3558 3559
	},

	[MV88E6095] = {
3560
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
3561 3562 3563 3564
		.family = MV88E6XXX_FAMILY_6095,
		.name = "Marvell 88E6095/88E6095F",
		.num_databases = 256,
		.num_ports = 11,
3565
		.num_internal_phys = 0,
3566
		.max_vid = 4095,
3567
		.port_base_addr = 0x10,
3568
		.phy_base_addr = 0x0,
3569
		.global1_addr = 0x1b,
3570
		.global2_addr = 0x1c,
3571
		.age_time_coeff = 15000,
3572
		.g1_irqs = 8,
3573
		.atu_move_port_mask = 0xf,
3574
		.multi_chip = true,
3575
		.tag_protocol = DSA_TAG_PROTO_DSA,
3576
		.ops = &mv88e6095_ops,
3577 3578
	},

3579
	[MV88E6097] = {
3580
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
3581 3582 3583 3584
		.family = MV88E6XXX_FAMILY_6097,
		.name = "Marvell 88E6097/88E6097F",
		.num_databases = 4096,
		.num_ports = 11,
3585
		.num_internal_phys = 8,
3586
		.max_vid = 4095,
3587
		.port_base_addr = 0x10,
3588
		.phy_base_addr = 0x0,
3589
		.global1_addr = 0x1b,
3590
		.global2_addr = 0x1c,
3591
		.age_time_coeff = 15000,
3592
		.g1_irqs = 8,
3593
		.g2_irqs = 10,
3594
		.atu_move_port_mask = 0xf,
3595
		.pvt = true,
3596
		.multi_chip = true,
3597
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3598 3599 3600
		.ops = &mv88e6097_ops,
	},

3601
	[MV88E6123] = {
3602
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
3603 3604 3605 3606
		.family = MV88E6XXX_FAMILY_6165,
		.name = "Marvell 88E6123",
		.num_databases = 4096,
		.num_ports = 3,
3607
		.num_internal_phys = 5,
3608
		.max_vid = 4095,
3609
		.port_base_addr = 0x10,
3610
		.phy_base_addr = 0x0,
3611
		.global1_addr = 0x1b,
3612
		.global2_addr = 0x1c,
3613
		.age_time_coeff = 15000,
3614
		.g1_irqs = 9,
3615
		.g2_irqs = 10,
3616
		.atu_move_port_mask = 0xf,
3617
		.pvt = true,
3618
		.multi_chip = true,
3619
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3620
		.ops = &mv88e6123_ops,
3621 3622 3623
	},

	[MV88E6131] = {
3624
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
3625 3626 3627 3628
		.family = MV88E6XXX_FAMILY_6185,
		.name = "Marvell 88E6131",
		.num_databases = 256,
		.num_ports = 8,
3629
		.num_internal_phys = 0,
3630
		.max_vid = 4095,
3631
		.port_base_addr = 0x10,
3632
		.phy_base_addr = 0x0,
3633
		.global1_addr = 0x1b,
3634
		.global2_addr = 0x1c,
3635
		.age_time_coeff = 15000,
3636
		.g1_irqs = 9,
3637
		.atu_move_port_mask = 0xf,
3638
		.multi_chip = true,
3639
		.tag_protocol = DSA_TAG_PROTO_DSA,
3640
		.ops = &mv88e6131_ops,
3641 3642
	},

3643
	[MV88E6141] = {
3644
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
3645
		.family = MV88E6XXX_FAMILY_6341,
3646
		.name = "Marvell 88E6141",
3647 3648
		.num_databases = 4096,
		.num_ports = 6,
3649
		.num_internal_phys = 5,
3650
		.num_gpio = 11,
3651
		.max_vid = 4095,
3652
		.port_base_addr = 0x10,
3653
		.phy_base_addr = 0x10,
3654
		.global1_addr = 0x1b,
3655
		.global2_addr = 0x1c,
3656 3657
		.age_time_coeff = 3750,
		.atu_move_port_mask = 0x1f,
3658
		.g1_irqs = 9,
3659
		.g2_irqs = 10,
3660
		.pvt = true,
3661
		.multi_chip = true,
3662 3663 3664 3665
		.tag_protocol = DSA_TAG_PROTO_EDSA,
		.ops = &mv88e6141_ops,
	},

3666
	[MV88E6161] = {
3667
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
3668 3669 3670 3671
		.family = MV88E6XXX_FAMILY_6165,
		.name = "Marvell 88E6161",
		.num_databases = 4096,
		.num_ports = 6,
3672
		.num_internal_phys = 5,
3673
		.max_vid = 4095,
3674
		.port_base_addr = 0x10,
3675
		.phy_base_addr = 0x0,
3676
		.global1_addr = 0x1b,
3677
		.global2_addr = 0x1c,
3678
		.age_time_coeff = 15000,
3679
		.g1_irqs = 9,
3680
		.g2_irqs = 10,
3681
		.atu_move_port_mask = 0xf,
3682
		.pvt = true,
3683
		.multi_chip = true,
3684
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3685
		.ops = &mv88e6161_ops,
3686 3687 3688
	},

	[MV88E6165] = {
3689
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
3690 3691 3692 3693
		.family = MV88E6XXX_FAMILY_6165,
		.name = "Marvell 88E6165",
		.num_databases = 4096,
		.num_ports = 6,
3694
		.num_internal_phys = 0,
3695
		.max_vid = 4095,
3696
		.port_base_addr = 0x10,
3697
		.phy_base_addr = 0x0,
3698
		.global1_addr = 0x1b,
3699
		.global2_addr = 0x1c,
3700
		.age_time_coeff = 15000,
3701
		.g1_irqs = 9,
3702
		.g2_irqs = 10,
3703
		.atu_move_port_mask = 0xf,
3704
		.pvt = true,
3705
		.multi_chip = true,
3706
		.tag_protocol = DSA_TAG_PROTO_DSA,
3707
		.ops = &mv88e6165_ops,
3708 3709 3710
	},

	[MV88E6171] = {
3711
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
3712 3713 3714 3715
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6171",
		.num_databases = 4096,
		.num_ports = 7,
3716
		.num_internal_phys = 5,
3717
		.max_vid = 4095,
3718
		.port_base_addr = 0x10,
3719
		.phy_base_addr = 0x0,
3720
		.global1_addr = 0x1b,
3721
		.global2_addr = 0x1c,
3722
		.age_time_coeff = 15000,
3723
		.g1_irqs = 9,
3724
		.g2_irqs = 10,
3725
		.atu_move_port_mask = 0xf,
3726
		.pvt = true,
3727
		.multi_chip = true,
3728
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3729
		.ops = &mv88e6171_ops,
3730 3731 3732
	},

	[MV88E6172] = {
3733
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
3734 3735 3736 3737
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6172",
		.num_databases = 4096,
		.num_ports = 7,
3738
		.num_internal_phys = 5,
3739
		.num_gpio = 15,
3740
		.max_vid = 4095,
3741
		.port_base_addr = 0x10,
3742
		.phy_base_addr = 0x0,
3743
		.global1_addr = 0x1b,
3744
		.global2_addr = 0x1c,
3745
		.age_time_coeff = 15000,
3746
		.g1_irqs = 9,
3747
		.g2_irqs = 10,
3748
		.atu_move_port_mask = 0xf,
3749
		.pvt = true,
3750
		.multi_chip = true,
3751
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3752
		.ops = &mv88e6172_ops,
3753 3754 3755
	},

	[MV88E6175] = {
3756
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
3757 3758 3759 3760
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6175",
		.num_databases = 4096,
		.num_ports = 7,
3761
		.num_internal_phys = 5,
3762
		.max_vid = 4095,
3763
		.port_base_addr = 0x10,
3764
		.phy_base_addr = 0x0,
3765
		.global1_addr = 0x1b,
3766
		.global2_addr = 0x1c,
3767
		.age_time_coeff = 15000,
3768
		.g1_irqs = 9,
3769
		.g2_irqs = 10,
3770
		.atu_move_port_mask = 0xf,
3771
		.pvt = true,
3772
		.multi_chip = true,
3773
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3774
		.ops = &mv88e6175_ops,
3775 3776 3777
	},

	[MV88E6176] = {
3778
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
3779 3780 3781 3782
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6176",
		.num_databases = 4096,
		.num_ports = 7,
3783
		.num_internal_phys = 5,
3784
		.num_gpio = 15,
3785
		.max_vid = 4095,
3786
		.port_base_addr = 0x10,
3787
		.phy_base_addr = 0x0,
3788
		.global1_addr = 0x1b,
3789
		.global2_addr = 0x1c,
3790
		.age_time_coeff = 15000,
3791
		.g1_irqs = 9,
3792
		.g2_irqs = 10,
3793
		.atu_move_port_mask = 0xf,
3794
		.pvt = true,
3795
		.multi_chip = true,
3796
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3797
		.ops = &mv88e6176_ops,
3798 3799 3800
	},

	[MV88E6185] = {
3801
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
3802 3803 3804 3805
		.family = MV88E6XXX_FAMILY_6185,
		.name = "Marvell 88E6185",
		.num_databases = 256,
		.num_ports = 10,
3806
		.num_internal_phys = 0,
3807
		.max_vid = 4095,
3808
		.port_base_addr = 0x10,
3809
		.phy_base_addr = 0x0,
3810
		.global1_addr = 0x1b,
3811
		.global2_addr = 0x1c,
3812
		.age_time_coeff = 15000,
3813
		.g1_irqs = 8,
3814
		.atu_move_port_mask = 0xf,
3815
		.multi_chip = true,
3816
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3817
		.ops = &mv88e6185_ops,
3818 3819
	},

3820
	[MV88E6190] = {
3821
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
3822 3823 3824 3825
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6190",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3826
		.num_internal_phys = 11,
3827
		.num_gpio = 16,
3828
		.max_vid = 8191,
3829
		.port_base_addr = 0x0,
3830
		.phy_base_addr = 0x0,
3831
		.global1_addr = 0x1b,
3832
		.global2_addr = 0x1c,
3833
		.tag_protocol = DSA_TAG_PROTO_DSA,
3834
		.age_time_coeff = 3750,
3835
		.g1_irqs = 9,
3836
		.g2_irqs = 14,
3837
		.pvt = true,
3838
		.multi_chip = true,
3839
		.atu_move_port_mask = 0x1f,
3840 3841 3842 3843
		.ops = &mv88e6190_ops,
	},

	[MV88E6190X] = {
3844
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
3845 3846 3847 3848
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6190X",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3849
		.num_internal_phys = 11,
3850
		.num_gpio = 16,
3851
		.max_vid = 8191,
3852
		.port_base_addr = 0x0,
3853
		.phy_base_addr = 0x0,
3854
		.global1_addr = 0x1b,
3855
		.global2_addr = 0x1c,
3856
		.age_time_coeff = 3750,
3857
		.g1_irqs = 9,
3858
		.g2_irqs = 14,
3859
		.atu_move_port_mask = 0x1f,
3860
		.pvt = true,
3861
		.multi_chip = true,
3862
		.tag_protocol = DSA_TAG_PROTO_DSA,
3863 3864 3865 3866
		.ops = &mv88e6190x_ops,
	},

	[MV88E6191] = {
3867
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
3868 3869 3870 3871
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6191",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3872
		.num_internal_phys = 11,
3873
		.max_vid = 8191,
3874
		.port_base_addr = 0x0,
3875
		.phy_base_addr = 0x0,
3876
		.global1_addr = 0x1b,
3877
		.global2_addr = 0x1c,
3878
		.age_time_coeff = 3750,
3879
		.g1_irqs = 9,
3880
		.g2_irqs = 14,
3881
		.atu_move_port_mask = 0x1f,
3882
		.pvt = true,
3883
		.multi_chip = true,
3884
		.tag_protocol = DSA_TAG_PROTO_DSA,
3885
		.ptp_support = true,
3886
		.ops = &mv88e6191_ops,
3887 3888
	},

3889
	[MV88E6240] = {
3890
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
3891 3892 3893 3894
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6240",
		.num_databases = 4096,
		.num_ports = 7,
3895
		.num_internal_phys = 5,
3896
		.num_gpio = 15,
3897
		.max_vid = 4095,
3898
		.port_base_addr = 0x10,
3899
		.phy_base_addr = 0x0,
3900
		.global1_addr = 0x1b,
3901
		.global2_addr = 0x1c,
3902
		.age_time_coeff = 15000,
3903
		.g1_irqs = 9,
3904
		.g2_irqs = 10,
3905
		.atu_move_port_mask = 0xf,
3906
		.pvt = true,
3907
		.multi_chip = true,
3908
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3909
		.ptp_support = true,
3910
		.ops = &mv88e6240_ops,
3911 3912
	},

3913
	[MV88E6290] = {
3914
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
3915 3916 3917 3918
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6290",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3919
		.num_internal_phys = 11,
3920
		.num_gpio = 16,
3921
		.max_vid = 8191,
3922
		.port_base_addr = 0x0,
3923
		.phy_base_addr = 0x0,
3924
		.global1_addr = 0x1b,
3925
		.global2_addr = 0x1c,
3926
		.age_time_coeff = 3750,
3927
		.g1_irqs = 9,
3928
		.g2_irqs = 14,
3929
		.atu_move_port_mask = 0x1f,
3930
		.pvt = true,
3931
		.multi_chip = true,
3932
		.tag_protocol = DSA_TAG_PROTO_DSA,
3933
		.ptp_support = true,
3934 3935 3936
		.ops = &mv88e6290_ops,
	},

3937
	[MV88E6320] = {
3938
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
3939 3940 3941 3942
		.family = MV88E6XXX_FAMILY_6320,
		.name = "Marvell 88E6320",
		.num_databases = 4096,
		.num_ports = 7,
3943
		.num_internal_phys = 5,
3944
		.num_gpio = 15,
3945
		.max_vid = 4095,
3946
		.port_base_addr = 0x10,
3947
		.phy_base_addr = 0x0,
3948
		.global1_addr = 0x1b,
3949
		.global2_addr = 0x1c,
3950
		.age_time_coeff = 15000,
3951
		.g1_irqs = 8,
3952
		.g2_irqs = 10,
3953
		.atu_move_port_mask = 0xf,
3954
		.pvt = true,
3955
		.multi_chip = true,
3956
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3957
		.ptp_support = true,
3958
		.ops = &mv88e6320_ops,
3959 3960 3961
	},

	[MV88E6321] = {
3962
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
3963 3964 3965 3966
		.family = MV88E6XXX_FAMILY_6320,
		.name = "Marvell 88E6321",
		.num_databases = 4096,
		.num_ports = 7,
3967
		.num_internal_phys = 5,
3968
		.num_gpio = 15,
3969
		.max_vid = 4095,
3970
		.port_base_addr = 0x10,
3971
		.phy_base_addr = 0x0,
3972
		.global1_addr = 0x1b,
3973
		.global2_addr = 0x1c,
3974
		.age_time_coeff = 15000,
3975
		.g1_irqs = 8,
3976
		.g2_irqs = 10,
3977
		.atu_move_port_mask = 0xf,
3978
		.multi_chip = true,
3979
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3980
		.ptp_support = true,
3981
		.ops = &mv88e6321_ops,
3982 3983
	},

3984
	[MV88E6341] = {
3985
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3986 3987 3988
		.family = MV88E6XXX_FAMILY_6341,
		.name = "Marvell 88E6341",
		.num_databases = 4096,
3989
		.num_internal_phys = 5,
3990
		.num_ports = 6,
3991
		.num_gpio = 11,
3992
		.max_vid = 4095,
3993
		.port_base_addr = 0x10,
3994
		.phy_base_addr = 0x10,
3995
		.global1_addr = 0x1b,
3996
		.global2_addr = 0x1c,
3997
		.age_time_coeff = 3750,
3998
		.atu_move_port_mask = 0x1f,
3999
		.g1_irqs = 9,
4000
		.g2_irqs = 10,
4001
		.pvt = true,
4002
		.multi_chip = true,
4003
		.tag_protocol = DSA_TAG_PROTO_EDSA,
4004
		.ptp_support = true,
4005 4006 4007
		.ops = &mv88e6341_ops,
	},

4008
	[MV88E6350] = {
4009
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
4010 4011 4012 4013
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6350",
		.num_databases = 4096,
		.num_ports = 7,
4014
		.num_internal_phys = 5,
4015
		.max_vid = 4095,
4016
		.port_base_addr = 0x10,
4017
		.phy_base_addr = 0x0,
4018
		.global1_addr = 0x1b,
4019
		.global2_addr = 0x1c,
4020
		.age_time_coeff = 15000,
4021
		.g1_irqs = 9,
4022
		.g2_irqs = 10,
4023
		.atu_move_port_mask = 0xf,
4024
		.pvt = true,
4025
		.multi_chip = true,
4026
		.tag_protocol = DSA_TAG_PROTO_EDSA,
4027
		.ops = &mv88e6350_ops,
4028 4029 4030
	},

	[MV88E6351] = {
4031
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
4032 4033 4034 4035
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6351",
		.num_databases = 4096,
		.num_ports = 7,
4036
		.num_internal_phys = 5,
4037
		.max_vid = 4095,
4038
		.port_base_addr = 0x10,
4039
		.phy_base_addr = 0x0,
4040
		.global1_addr = 0x1b,
4041
		.global2_addr = 0x1c,
4042
		.age_time_coeff = 15000,
4043
		.g1_irqs = 9,
4044
		.g2_irqs = 10,
4045
		.atu_move_port_mask = 0xf,
4046
		.pvt = true,
4047
		.multi_chip = true,
4048
		.tag_protocol = DSA_TAG_PROTO_EDSA,
4049
		.ops = &mv88e6351_ops,
4050 4051 4052
	},

	[MV88E6352] = {
4053
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
4054 4055 4056 4057
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6352",
		.num_databases = 4096,
		.num_ports = 7,
4058
		.num_internal_phys = 5,
4059
		.num_gpio = 15,
4060
		.max_vid = 4095,
4061
		.port_base_addr = 0x10,
4062
		.phy_base_addr = 0x0,
4063
		.global1_addr = 0x1b,
4064
		.global2_addr = 0x1c,
4065
		.age_time_coeff = 15000,
4066
		.g1_irqs = 9,
4067
		.g2_irqs = 10,
4068
		.atu_move_port_mask = 0xf,
4069
		.pvt = true,
4070
		.multi_chip = true,
4071
		.tag_protocol = DSA_TAG_PROTO_EDSA,
4072
		.ptp_support = true,
4073
		.ops = &mv88e6352_ops,
4074
	},
4075
	[MV88E6390] = {
4076
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
4077 4078 4079 4080
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6390",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
4081
		.num_internal_phys = 11,
4082
		.num_gpio = 16,
4083
		.max_vid = 8191,
4084
		.port_base_addr = 0x0,
4085
		.phy_base_addr = 0x0,
4086
		.global1_addr = 0x1b,
4087
		.global2_addr = 0x1c,
4088
		.age_time_coeff = 3750,
4089
		.g1_irqs = 9,
4090
		.g2_irqs = 14,
4091
		.atu_move_port_mask = 0x1f,
4092
		.pvt = true,
4093
		.multi_chip = true,
4094
		.tag_protocol = DSA_TAG_PROTO_DSA,
4095
		.ptp_support = true,
4096 4097 4098
		.ops = &mv88e6390_ops,
	},
	[MV88E6390X] = {
4099
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
4100 4101 4102 4103
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6390X",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
4104
		.num_internal_phys = 11,
4105
		.num_gpio = 16,
4106
		.max_vid = 8191,
4107
		.port_base_addr = 0x0,
4108
		.phy_base_addr = 0x0,
4109
		.global1_addr = 0x1b,
4110
		.global2_addr = 0x1c,
4111
		.age_time_coeff = 3750,
4112
		.g1_irqs = 9,
4113
		.g2_irqs = 14,
4114
		.atu_move_port_mask = 0x1f,
4115
		.pvt = true,
4116
		.multi_chip = true,
4117
		.tag_protocol = DSA_TAG_PROTO_DSA,
4118
		.ptp_support = true,
4119 4120
		.ops = &mv88e6390x_ops,
	},
4121 4122
};

4123
static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
4124
{
4125
	int i;
4126

4127 4128 4129
	for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
		if (mv88e6xxx_table[i].prod_num == prod_num)
			return &mv88e6xxx_table[i];
4130 4131 4132 4133

	return NULL;
}

4134
static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
4135 4136
{
	const struct mv88e6xxx_info *info;
4137 4138 4139
	unsigned int prod_num, rev;
	u16 id;
	int err;
4140

4141
	mutex_lock(&chip->reg_lock);
4142
	err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
4143 4144 4145
	mutex_unlock(&chip->reg_lock);
	if (err)
		return err;
4146

4147 4148
	prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
	rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
4149 4150 4151 4152 4153

	info = mv88e6xxx_lookup_info(prod_num);
	if (!info)
		return -ENODEV;

4154
	/* Update the compatible info with the probed one */
4155
	chip->info = info;
4156

4157 4158 4159 4160
	err = mv88e6xxx_g2_require(chip);
	if (err)
		return err;

4161 4162
	dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
		 chip->info->prod_num, chip->info->name, rev);
4163 4164 4165 4166

	return 0;
}

4167
static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
4168
{
4169
	struct mv88e6xxx_chip *chip;
4170

4171 4172
	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
	if (!chip)
4173 4174
		return NULL;

4175
	chip->dev = dev;
4176

4177
	mutex_init(&chip->reg_lock);
4178
	INIT_LIST_HEAD(&chip->mdios);
4179

4180
	return chip;
4181 4182
}

4183
static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4184 4185
			      struct mii_bus *bus, int sw_addr)
{
4186
	if (sw_addr == 0)
4187
		chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
4188
	else if (chip->info->multi_chip)
4189
		chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
4190 4191 4192
	else
		return -EINVAL;

4193 4194
	chip->bus = bus;
	chip->sw_addr = sw_addr;
4195 4196 4197 4198

	return 0;
}

4199 4200
static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
							int port)
4201
{
V
Vivien Didelot 已提交
4202
	struct mv88e6xxx_chip *chip = ds->priv;
4203

4204
	return chip->info->tag_protocol;
4205 4206
}

4207
#if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
4208 4209 4210
static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
				       struct device *host_dev, int sw_addr,
				       void **priv)
4211
{
4212
	struct mv88e6xxx_chip *chip;
4213
	struct mii_bus *bus;
4214
	int err;
4215

4216
	bus = dsa_host_dev_to_mii_bus(host_dev);
4217 4218 4219
	if (!bus)
		return NULL;

4220 4221
	chip = mv88e6xxx_alloc_chip(dsa_dev);
	if (!chip)
4222 4223
		return NULL;

4224
	/* Legacy SMI probing will only support chips similar to 88E6085 */
4225
	chip->info = &mv88e6xxx_table[MV88E6085];
4226

4227
	err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4228 4229 4230
	if (err)
		goto free;

4231
	err = mv88e6xxx_detect(chip);
4232
	if (err)
4233
		goto free;
4234

4235 4236 4237 4238 4239 4240
	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_switch_reset(chip);
	mutex_unlock(&chip->reg_lock);
	if (err)
		goto free;

4241 4242
	mv88e6xxx_phy_init(chip);

4243
	err = mv88e6xxx_mdios_register(chip, NULL);
4244
	if (err)
4245
		goto free;
4246

4247
	*priv = chip;
4248

4249
	return chip->info->name;
4250
free:
4251
	devm_kfree(dsa_dev, chip);
4252 4253

	return NULL;
4254
}
4255
#endif
4256

4257
static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
4258
				      const struct switchdev_obj_port_mdb *mdb)
4259 4260 4261 4262 4263 4264 4265 4266 4267
{
	/* We don't need any dynamic resource from the kernel (yet),
	 * so skip the prepare phase.
	 */

	return 0;
}

static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
4268
				   const struct switchdev_obj_port_mdb *mdb)
4269
{
V
Vivien Didelot 已提交
4270
	struct mv88e6xxx_chip *chip = ds->priv;
4271 4272 4273

	mutex_lock(&chip->reg_lock);
	if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4274
					 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
4275 4276
		dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
			port);
4277 4278 4279 4280 4281 4282
	mutex_unlock(&chip->reg_lock);
}

static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
				  const struct switchdev_obj_port_mdb *mdb)
{
V
Vivien Didelot 已提交
4283
	struct mv88e6xxx_chip *chip = ds->priv;
4284 4285 4286 4287
	int err;

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4288
					   MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
4289 4290 4291 4292 4293
	mutex_unlock(&chip->reg_lock);

	return err;
}

4294
static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
4295
#if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
4296
	.probe			= mv88e6xxx_drv_probe,
4297
#endif
4298
	.get_tag_protocol	= mv88e6xxx_get_tag_protocol,
4299 4300
	.setup			= mv88e6xxx_setup,
	.adjust_link		= mv88e6xxx_adjust_link,
4301 4302 4303 4304 4305
	.phylink_validate	= mv88e6xxx_validate,
	.phylink_mac_link_state	= mv88e6xxx_link_state,
	.phylink_mac_config	= mv88e6xxx_mac_config,
	.phylink_mac_link_down	= mv88e6xxx_mac_link_down,
	.phylink_mac_link_up	= mv88e6xxx_mac_link_up,
4306 4307 4308
	.get_strings		= mv88e6xxx_get_strings,
	.get_ethtool_stats	= mv88e6xxx_get_ethtool_stats,
	.get_sset_count		= mv88e6xxx_get_sset_count,
4309 4310
	.port_enable		= mv88e6xxx_port_enable,
	.port_disable		= mv88e6xxx_port_disable,
V
Vivien Didelot 已提交
4311 4312
	.get_mac_eee		= mv88e6xxx_get_mac_eee,
	.set_mac_eee		= mv88e6xxx_set_mac_eee,
4313
	.get_eeprom_len		= mv88e6xxx_get_eeprom_len,
4314 4315 4316 4317
	.get_eeprom		= mv88e6xxx_get_eeprom,
	.set_eeprom		= mv88e6xxx_set_eeprom,
	.get_regs_len		= mv88e6xxx_get_regs_len,
	.get_regs		= mv88e6xxx_get_regs,
4318
	.set_ageing_time	= mv88e6xxx_set_ageing_time,
4319 4320 4321
	.port_bridge_join	= mv88e6xxx_port_bridge_join,
	.port_bridge_leave	= mv88e6xxx_port_bridge_leave,
	.port_stp_state_set	= mv88e6xxx_port_stp_state_set,
4322
	.port_fast_age		= mv88e6xxx_port_fast_age,
4323 4324 4325 4326 4327 4328 4329
	.port_vlan_filtering	= mv88e6xxx_port_vlan_filtering,
	.port_vlan_prepare	= mv88e6xxx_port_vlan_prepare,
	.port_vlan_add		= mv88e6xxx_port_vlan_add,
	.port_vlan_del		= mv88e6xxx_port_vlan_del,
	.port_fdb_add           = mv88e6xxx_port_fdb_add,
	.port_fdb_del           = mv88e6xxx_port_fdb_del,
	.port_fdb_dump          = mv88e6xxx_port_fdb_dump,
4330 4331 4332
	.port_mdb_prepare       = mv88e6xxx_port_mdb_prepare,
	.port_mdb_add           = mv88e6xxx_port_mdb_add,
	.port_mdb_del           = mv88e6xxx_port_mdb_del,
4333 4334
	.crosschip_bridge_join	= mv88e6xxx_crosschip_bridge_join,
	.crosschip_bridge_leave	= mv88e6xxx_crosschip_bridge_leave,
4335 4336 4337 4338 4339
	.port_hwtstamp_set	= mv88e6xxx_port_hwtstamp_set,
	.port_hwtstamp_get	= mv88e6xxx_port_hwtstamp_get,
	.port_txtstamp		= mv88e6xxx_port_txtstamp,
	.port_rxtstamp		= mv88e6xxx_port_rxtstamp,
	.get_ts_info		= mv88e6xxx_get_ts_info,
4340 4341
};

4342 4343 4344 4345
static struct dsa_switch_driver mv88e6xxx_switch_drv = {
	.ops			= &mv88e6xxx_switch_ops,
};

4346
static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
4347
{
4348
	struct device *dev = chip->dev;
4349 4350
	struct dsa_switch *ds;

4351
	ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip));
4352 4353 4354
	if (!ds)
		return -ENOMEM;

4355
	ds->priv = chip;
4356
	ds->ops = &mv88e6xxx_switch_ops;
4357 4358
	ds->ageing_time_min = chip->info->age_time_coeff;
	ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
4359 4360 4361

	dev_set_drvdata(dev, ds);

4362
	return dsa_register_switch(ds);
4363 4364
}

4365
static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
4366
{
4367
	dsa_unregister_switch(chip->ds);
4368 4369
}

4370
static int mv88e6xxx_probe(struct mdio_device *mdiodev)
4371
{
4372
	struct device *dev = &mdiodev->dev;
4373
	struct device_node *np = dev->of_node;
4374
	const struct mv88e6xxx_info *compat_info;
4375
	struct mv88e6xxx_chip *chip;
4376
	u32 eeprom_len;
4377
	int err;
4378

4379 4380 4381 4382
	compat_info = of_device_get_match_data(dev);
	if (!compat_info)
		return -EINVAL;

4383 4384
	chip = mv88e6xxx_alloc_chip(dev);
	if (!chip)
4385 4386
		return -ENOMEM;

4387
	chip->info = compat_info;
4388

4389
	err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4390 4391
	if (err)
		return err;
4392

4393 4394 4395 4396
	chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
	if (IS_ERR(chip->reset))
		return PTR_ERR(chip->reset);

4397
	err = mv88e6xxx_detect(chip);
4398 4399
	if (err)
		return err;
4400

4401 4402
	mv88e6xxx_phy_init(chip);

4403
	if (chip->info->ops->get_eeprom &&
4404
	    !of_property_read_u32(np, "eeprom-length", &eeprom_len))
4405
		chip->eeprom_len = eeprom_len;
4406

4407 4408 4409 4410 4411 4412 4413 4414 4415 4416 4417 4418
	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_switch_reset(chip);
	mutex_unlock(&chip->reg_lock);
	if (err)
		goto out;

	chip->irq = of_irq_get(np, 0);
	if (chip->irq == -EPROBE_DEFER) {
		err = chip->irq;
		goto out;
	}

4419
	/* Has to be performed before the MDIO bus is created, because
4420
	 * the PHYs will link their interrupts to these interrupt
4421 4422 4423 4424
	 * controllers
	 */
	mutex_lock(&chip->reg_lock);
	if (chip->irq > 0)
4425
		err = mv88e6xxx_g1_irq_setup(chip);
4426 4427 4428
	else
		err = mv88e6xxx_irq_poll_setup(chip);
	mutex_unlock(&chip->reg_lock);
4429

4430 4431
	if (err)
		goto out;
4432

4433 4434
	if (chip->info->g2_irqs > 0) {
		err = mv88e6xxx_g2_irq_setup(chip);
4435
		if (err)
4436
			goto out_g1_irq;
4437 4438
	}

4439 4440 4441 4442 4443 4444 4445 4446
	err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
	if (err)
		goto out_g2_irq;

	err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
	if (err)
		goto out_g1_atu_prob_irq;

4447
	err = mv88e6xxx_mdios_register(chip, np);
4448
	if (err)
4449
		goto out_g1_vtu_prob_irq;
4450

4451
	err = mv88e6xxx_register_switch(chip);
4452 4453
	if (err)
		goto out_mdio;
4454

4455
	return 0;
4456 4457

out_mdio:
4458
	mv88e6xxx_mdios_unregister(chip);
4459
out_g1_vtu_prob_irq:
4460
	mv88e6xxx_g1_vtu_prob_irq_free(chip);
4461
out_g1_atu_prob_irq:
4462
	mv88e6xxx_g1_atu_prob_irq_free(chip);
4463
out_g2_irq:
4464
	if (chip->info->g2_irqs > 0)
4465 4466
		mv88e6xxx_g2_irq_free(chip);
out_g1_irq:
4467 4468
	mutex_lock(&chip->reg_lock);
	if (chip->irq > 0)
4469
		mv88e6xxx_g1_irq_free(chip);
4470 4471 4472
	else
		mv88e6xxx_irq_poll_free(chip);
	mutex_unlock(&chip->reg_lock);
4473 4474
out:
	return err;
4475
}
4476 4477 4478 4479

static void mv88e6xxx_remove(struct mdio_device *mdiodev)
{
	struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
V
Vivien Didelot 已提交
4480
	struct mv88e6xxx_chip *chip = ds->priv;
4481

4482 4483
	if (chip->info->ptp_support) {
		mv88e6xxx_hwtstamp_free(chip);
4484
		mv88e6xxx_ptp_free(chip);
4485
	}
4486

4487
	mv88e6xxx_phy_destroy(chip);
4488
	mv88e6xxx_unregister_switch(chip);
4489
	mv88e6xxx_mdios_unregister(chip);
4490

4491 4492 4493 4494 4495 4496 4497 4498
	mv88e6xxx_g1_vtu_prob_irq_free(chip);
	mv88e6xxx_g1_atu_prob_irq_free(chip);

	if (chip->info->g2_irqs > 0)
		mv88e6xxx_g2_irq_free(chip);

	mutex_lock(&chip->reg_lock);
	if (chip->irq > 0)
4499
		mv88e6xxx_g1_irq_free(chip);
4500 4501 4502
	else
		mv88e6xxx_irq_poll_free(chip);
	mutex_unlock(&chip->reg_lock);
4503 4504 4505
}

static const struct of_device_id mv88e6xxx_of_match[] = {
4506 4507 4508 4509
	{
		.compatible = "marvell,mv88e6085",
		.data = &mv88e6xxx_table[MV88E6085],
	},
4510 4511 4512 4513
	{
		.compatible = "marvell,mv88e6190",
		.data = &mv88e6xxx_table[MV88E6190],
	},
4514 4515 4516 4517 4518 4519 4520 4521 4522 4523 4524 4525 4526 4527 4528 4529
	{ /* sentinel */ },
};

MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);

static struct mdio_driver mv88e6xxx_driver = {
	.probe	= mv88e6xxx_probe,
	.remove = mv88e6xxx_remove,
	.mdiodrv.driver = {
		.name = "mv88e6085",
		.of_match_table = mv88e6xxx_of_match,
	},
};

static int __init mv88e6xxx_init(void)
{
4530
	register_switch_driver(&mv88e6xxx_switch_drv);
4531 4532
	return mdio_driver_register(&mv88e6xxx_driver);
}
4533 4534 4535 4536
module_init(mv88e6xxx_init);

static void __exit mv88e6xxx_cleanup(void)
{
4537
	mdio_driver_unregister(&mv88e6xxx_driver);
4538
	unregister_switch_driver(&mv88e6xxx_switch_drv);
4539 4540
}
module_exit(mv88e6xxx_cleanup);
4541 4542 4543 4544

MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
MODULE_LICENSE("GPL");