chip.c 115.2 KB
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/*
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 * Marvell 88e6xxx Ethernet switch single-chip support
 *
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 * Copyright (c) 2008 Marvell Semiconductor
 *
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 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
 *
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 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
 *	Vivien Didelot <vivien.didelot@savoirfairelinux.com>
 *
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 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

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#include <linux/delay.h>
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#include <linux/etherdevice.h>
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#include <linux/ethtool.h>
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#include <linux/if_bridge.h>
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#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
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#include <linux/jiffies.h>
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#include <linux/list.h>
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#include <linux/mdio.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/of_mdio.h>
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#include <linux/netdevice.h>
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#include <linux/gpio/consumer.h>
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#include <linux/phy.h>
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#include <net/dsa.h>
35

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#include "chip.h"
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#include "global1.h"
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#include "global2.h"
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#include "phy.h"
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#include "port.h"
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#include "ptp.h"
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#include "serdes.h"
43

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static void assert_reg_lock(struct mv88e6xxx_chip *chip)
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{
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	if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
		dev_err(chip->dev, "Switch registers lock not held!\n");
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		dump_stack();
	}
}

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/* The switch ADDR[4:1] configuration pins define the chip SMI device address
 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
 *
 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
 * is the only device connected to the SMI master. In this mode it responds to
 * all 32 possible SMI addresses, and thus maps directly the internal devices.
 *
 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
 * multiple devices to share the SMI interface. In this mode it responds to only
 * 2 registers, used to indirectly access the internal SMI devices.
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 */
63

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static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
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			      int addr, int reg, u16 *val)
{
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	if (!chip->smi_ops)
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		return -EOPNOTSUPP;

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	return chip->smi_ops->read(chip, addr, reg, val);
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}

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static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
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			       int addr, int reg, u16 val)
{
76
	if (!chip->smi_ops)
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		return -EOPNOTSUPP;

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	return chip->smi_ops->write(chip, addr, reg, val);
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}

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static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
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					  int addr, int reg, u16 *val)
{
	int ret;

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	ret = mdiobus_read_nested(chip->bus, addr, reg);
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	if (ret < 0)
		return ret;

	*val = ret & 0xffff;

	return 0;
}

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static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
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					   int addr, int reg, u16 val)
{
	int ret;

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	ret = mdiobus_write_nested(chip->bus, addr, reg, val);
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	if (ret < 0)
		return ret;

	return 0;
}

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static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
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	.read = mv88e6xxx_smi_single_chip_read,
	.write = mv88e6xxx_smi_single_chip_write,
};

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static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
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{
	int ret;
	int i;

	for (i = 0; i < 16; i++) {
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		ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
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		if (ret < 0)
			return ret;

123
		if ((ret & SMI_CMD_BUSY) == 0)
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			return 0;
	}

	return -ETIMEDOUT;
}

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static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
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					 int addr, int reg, u16 *val)
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{
	int ret;

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	/* Wait for the bus to become free. */
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	ret = mv88e6xxx_smi_multi_chip_wait(chip);
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	if (ret < 0)
		return ret;

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	/* Transmit the read command. */
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	ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
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				   SMI_CMD_OP_22_READ | (addr << 5) | reg);
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	if (ret < 0)
		return ret;

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	/* Wait for the read command to complete. */
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	ret = mv88e6xxx_smi_multi_chip_wait(chip);
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	if (ret < 0)
		return ret;

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	/* Read the data. */
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	ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
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	if (ret < 0)
		return ret;

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	*val = ret & 0xffff;
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158
	return 0;
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}

161
static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
162
					  int addr, int reg, u16 val)
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{
	int ret;

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	/* Wait for the bus to become free. */
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	ret = mv88e6xxx_smi_multi_chip_wait(chip);
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	if (ret < 0)
		return ret;

171
	/* Transmit the data to write. */
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	ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
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	if (ret < 0)
		return ret;

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	/* Transmit the write command. */
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	ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
178
				   SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
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	if (ret < 0)
		return ret;

182
	/* Wait for the write command to complete. */
183
	ret = mv88e6xxx_smi_multi_chip_wait(chip);
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	if (ret < 0)
		return ret;

	return 0;
}

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static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
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	.read = mv88e6xxx_smi_multi_chip_read,
	.write = mv88e6xxx_smi_multi_chip_write,
};

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int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
196 197 198
{
	int err;

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	assert_reg_lock(chip);
200

201
	err = mv88e6xxx_smi_read(chip, addr, reg, val);
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	if (err)
		return err;

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	dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
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		addr, reg, *val);

	return 0;
}

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int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
212
{
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	int err;

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	assert_reg_lock(chip);
216

217
	err = mv88e6xxx_smi_write(chip, addr, reg, val);
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	if (err)
		return err;

221
	dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
222 223
		addr, reg, val);

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	return 0;
}

227
struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
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{
	struct mv88e6xxx_mdio_bus *mdio_bus;

	mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
				    list);
	if (!mdio_bus)
		return NULL;

	return mdio_bus->bus;
}

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static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
{
	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int n = d->hwirq;

	chip->g1_irq.masked |= (1 << n);
}

static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
{
	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int n = d->hwirq;

	chip->g1_irq.masked &= ~(1 << n);
}

static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
{
	struct mv88e6xxx_chip *chip = dev_id;
	unsigned int nhandled = 0;
	unsigned int sub_irq;
	unsigned int n;
	u16 reg;
	int err;

	mutex_lock(&chip->reg_lock);
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	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
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	mutex_unlock(&chip->reg_lock);

	if (err)
		goto out;

	for (n = 0; n < chip->g1_irq.nirqs; ++n) {
		if (reg & (1 << n)) {
			sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
			handle_nested_irq(sub_irq);
			++nhandled;
		}
	}
out:
	return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
}

static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
{
	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);

	mutex_lock(&chip->reg_lock);
}

static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
{
	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
	u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
	u16 reg;
	int err;

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	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
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	if (err)
		goto out;

	reg &= ~mask;
	reg |= (~chip->g1_irq.masked & mask);

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	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
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	if (err)
		goto out;

out:
	mutex_unlock(&chip->reg_lock);
}

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static const struct irq_chip mv88e6xxx_g1_irq_chip = {
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	.name			= "mv88e6xxx-g1",
	.irq_mask		= mv88e6xxx_g1_irq_mask,
	.irq_unmask		= mv88e6xxx_g1_irq_unmask,
	.irq_bus_lock		= mv88e6xxx_g1_irq_bus_lock,
	.irq_bus_sync_unlock	= mv88e6xxx_g1_irq_bus_sync_unlock,
};

static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
				       unsigned int irq,
				       irq_hw_number_t hwirq)
{
	struct mv88e6xxx_chip *chip = d->host_data;

	irq_set_chip_data(irq, d->host_data);
	irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
	irq_set_noprobe(irq);

	return 0;
}

static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
	.map	= mv88e6xxx_g1_irq_domain_map,
	.xlate	= irq_domain_xlate_twocell,
};

static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
{
	int irq, virq;
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	u16 mask;

342
	mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
343
	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
344
	mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
345 346

	free_irq(chip->irq, chip);
347

348
	for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
349
		virq = irq_find_mapping(chip->g1_irq.domain, irq);
350 351 352
		irq_dispose_mapping(virq);
	}

353
	irq_domain_remove(chip->g1_irq.domain);
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}

static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
{
358 359
	int err, irq, virq;
	u16 reg, mask;
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	chip->g1_irq.nirqs = chip->info->g1_irqs;
	chip->g1_irq.domain = irq_domain_add_simple(
		NULL, chip->g1_irq.nirqs, 0,
		&mv88e6xxx_g1_irq_domain_ops, chip);
	if (!chip->g1_irq.domain)
		return -ENOMEM;

	for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
		irq_create_mapping(chip->g1_irq.domain, irq);

	chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
	chip->g1_irq.masked = ~0;

374
	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
375
	if (err)
376
		goto out_mapping;
377

378
	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
379

380
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
381
	if (err)
382
		goto out_disable;
383 384

	/* Reading the interrupt status clears (most of) them */
385
	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
386
	if (err)
387
		goto out_disable;
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	err = request_threaded_irq(chip->irq, NULL,
				   mv88e6xxx_g1_irq_thread_fn,
				   IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
				   dev_name(chip->dev), chip);
	if (err)
394
		goto out_disable;
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	return 0;

398
out_disable:
399
	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
400
	mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
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out_mapping:
	for (irq = 0; irq < 16; irq++) {
		virq = irq_find_mapping(chip->g1_irq.domain, irq);
		irq_dispose_mapping(virq);
	}

	irq_domain_remove(chip->g1_irq.domain);
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	return err;
}

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int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
414
{
415
	int i;
416

417
	for (i = 0; i < 16; i++) {
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		u16 val;
		int err;

		err = mv88e6xxx_read(chip, addr, reg, &val);
		if (err)
			return err;

		if (!(val & mask))
			return 0;

		usleep_range(1000, 2000);
	}

431
	dev_err(chip->dev, "Timeout while waiting for switch\n");
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	return -ETIMEDOUT;
}

435
/* Indirect write to single pointer-data register with an Update bit */
436
int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
437 438
{
	u16 val;
439
	int err;
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	/* Wait until the previous operation is completed */
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	err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
	if (err)
		return err;
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	/* Set the Update bit to trigger a write operation */
	val = BIT(15) | update;

	return mv88e6xxx_write(chip, addr, reg, val);
}

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static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
				    int link, int speed, int duplex,
				    phy_interface_t mode)
{
	int err;

	if (!chip->info->ops->port_set_link)
		return 0;

	/* Port's MAC control must not be changed unless the link is down */
	err = chip->info->ops->port_set_link(chip, port, 0);
	if (err)
		return err;

	if (chip->info->ops->port_set_speed) {
		err = chip->info->ops->port_set_speed(chip, port, speed);
		if (err && err != -EOPNOTSUPP)
			goto restore_link;
	}

	if (chip->info->ops->port_set_duplex) {
		err = chip->info->ops->port_set_duplex(chip, port, duplex);
		if (err && err != -EOPNOTSUPP)
			goto restore_link;
	}

	if (chip->info->ops->port_set_rgmii_delay) {
		err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
		if (err && err != -EOPNOTSUPP)
			goto restore_link;
	}

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	if (chip->info->ops->port_set_cmode) {
		err = chip->info->ops->port_set_cmode(chip, port, mode);
		if (err && err != -EOPNOTSUPP)
			goto restore_link;
	}

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	err = 0;
restore_link:
	if (chip->info->ops->port_set_link(chip, port, link))
493
		dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
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	return err;
}

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/* We expect the switch to perform auto negotiation if there is a real
 * phy. However, in the case of a fixed link phy, we force the port
 * settings from the fixed link settings.
 */
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static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
				  struct phy_device *phydev)
504
{
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Vivien Didelot 已提交
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	struct mv88e6xxx_chip *chip = ds->priv;
506
	int err;
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	if (!phy_is_pseudo_fixed_link(phydev))
		return;

511
	mutex_lock(&chip->reg_lock);
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	err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
				       phydev->duplex, phydev->interface);
514
	mutex_unlock(&chip->reg_lock);
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	if (err && err != -EOPNOTSUPP)
517
		dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
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}

520
static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
521
{
522 523
	if (!chip->info->ops->stats_snapshot)
		return -EOPNOTSUPP;
524

525
	return chip->info->ops->stats_snapshot(chip, port);
526 527
}

528
static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
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	{ "in_good_octets",		8, 0x00, STATS_TYPE_BANK0, },
	{ "in_bad_octets",		4, 0x02, STATS_TYPE_BANK0, },
	{ "in_unicast",			4, 0x04, STATS_TYPE_BANK0, },
	{ "in_broadcasts",		4, 0x06, STATS_TYPE_BANK0, },
	{ "in_multicasts",		4, 0x07, STATS_TYPE_BANK0, },
	{ "in_pause",			4, 0x16, STATS_TYPE_BANK0, },
	{ "in_undersize",		4, 0x18, STATS_TYPE_BANK0, },
	{ "in_fragments",		4, 0x19, STATS_TYPE_BANK0, },
	{ "in_oversize",		4, 0x1a, STATS_TYPE_BANK0, },
	{ "in_jabber",			4, 0x1b, STATS_TYPE_BANK0, },
	{ "in_rx_error",		4, 0x1c, STATS_TYPE_BANK0, },
	{ "in_fcs_error",		4, 0x1d, STATS_TYPE_BANK0, },
	{ "out_octets",			8, 0x0e, STATS_TYPE_BANK0, },
	{ "out_unicast",		4, 0x10, STATS_TYPE_BANK0, },
	{ "out_broadcasts",		4, 0x13, STATS_TYPE_BANK0, },
	{ "out_multicasts",		4, 0x12, STATS_TYPE_BANK0, },
	{ "out_pause",			4, 0x15, STATS_TYPE_BANK0, },
	{ "excessive",			4, 0x11, STATS_TYPE_BANK0, },
	{ "collisions",			4, 0x1e, STATS_TYPE_BANK0, },
	{ "deferred",			4, 0x05, STATS_TYPE_BANK0, },
	{ "single",			4, 0x14, STATS_TYPE_BANK0, },
	{ "multiple",			4, 0x17, STATS_TYPE_BANK0, },
	{ "out_fcs_error",		4, 0x03, STATS_TYPE_BANK0, },
	{ "late",			4, 0x1f, STATS_TYPE_BANK0, },
	{ "hist_64bytes",		4, 0x08, STATS_TYPE_BANK0, },
	{ "hist_65_127bytes",		4, 0x09, STATS_TYPE_BANK0, },
	{ "hist_128_255bytes",		4, 0x0a, STATS_TYPE_BANK0, },
	{ "hist_256_511bytes",		4, 0x0b, STATS_TYPE_BANK0, },
	{ "hist_512_1023bytes",		4, 0x0c, STATS_TYPE_BANK0, },
	{ "hist_1024_max_bytes",	4, 0x0d, STATS_TYPE_BANK0, },
	{ "sw_in_discards",		4, 0x10, STATS_TYPE_PORT, },
	{ "sw_in_filtered",		2, 0x12, STATS_TYPE_PORT, },
	{ "sw_out_filtered",		2, 0x13, STATS_TYPE_PORT, },
	{ "in_discards",		4, 0x00, STATS_TYPE_BANK1, },
	{ "in_filtered",		4, 0x01, STATS_TYPE_BANK1, },
	{ "in_accepted",		4, 0x02, STATS_TYPE_BANK1, },
	{ "in_bad_accepted",		4, 0x03, STATS_TYPE_BANK1, },
	{ "in_good_avb_class_a",	4, 0x04, STATS_TYPE_BANK1, },
	{ "in_good_avb_class_b",	4, 0x05, STATS_TYPE_BANK1, },
	{ "in_bad_avb_class_a",		4, 0x06, STATS_TYPE_BANK1, },
	{ "in_bad_avb_class_b",		4, 0x07, STATS_TYPE_BANK1, },
	{ "tcam_counter_0",		4, 0x08, STATS_TYPE_BANK1, },
	{ "tcam_counter_1",		4, 0x09, STATS_TYPE_BANK1, },
	{ "tcam_counter_2",		4, 0x0a, STATS_TYPE_BANK1, },
	{ "tcam_counter_3",		4, 0x0b, STATS_TYPE_BANK1, },
	{ "in_da_unknown",		4, 0x0e, STATS_TYPE_BANK1, },
	{ "in_management",		4, 0x0f, STATS_TYPE_BANK1, },
	{ "out_queue_0",		4, 0x10, STATS_TYPE_BANK1, },
	{ "out_queue_1",		4, 0x11, STATS_TYPE_BANK1, },
	{ "out_queue_2",		4, 0x12, STATS_TYPE_BANK1, },
	{ "out_queue_3",		4, 0x13, STATS_TYPE_BANK1, },
	{ "out_queue_4",		4, 0x14, STATS_TYPE_BANK1, },
	{ "out_queue_5",		4, 0x15, STATS_TYPE_BANK1, },
	{ "out_queue_6",		4, 0x16, STATS_TYPE_BANK1, },
	{ "out_queue_7",		4, 0x17, STATS_TYPE_BANK1, },
	{ "out_cut_through",		4, 0x18, STATS_TYPE_BANK1, },
	{ "out_octets_a",		4, 0x1a, STATS_TYPE_BANK1, },
	{ "out_octets_b",		4, 0x1b, STATS_TYPE_BANK1, },
	{ "out_management",		4, 0x1f, STATS_TYPE_BANK1, },
588 589
};

590
static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
591
					    struct mv88e6xxx_hw_stat *s,
592 593
					    int port, u16 bank1_select,
					    u16 histogram)
594 595 596
{
	u32 low;
	u32 high = 0;
597
	u16 reg = 0;
598
	int err;
599 600
	u64 value;

601
	switch (s->type) {
602
	case STATS_TYPE_PORT:
603 604
		err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
		if (err)
605 606
			return UINT64_MAX;

607
		low = reg;
608
		if (s->sizeof_stat == 4) {
609 610
			err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
			if (err)
611
				return UINT64_MAX;
612
			high = reg;
613
		}
614
		break;
615
	case STATS_TYPE_BANK1:
616
		reg = bank1_select;
617 618
		/* fall through */
	case STATS_TYPE_BANK0:
619
		reg |= s->reg | histogram;
620
		mv88e6xxx_g1_stats_read(chip, reg, &low);
621
		if (s->sizeof_stat == 8)
622
			mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
623 624 625
		break;
	default:
		return UINT64_MAX;
626 627 628 629 630
	}
	value = (((u64)high) << 16) | low;
	return value;
}

631 632
static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
					uint8_t *data, int types)
633
{
634 635
	struct mv88e6xxx_hw_stat *stat;
	int i, j;
636

637 638
	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
		stat = &mv88e6xxx_hw_stats[i];
639
		if (stat->type & types) {
640 641 642 643
			memcpy(data + j * ETH_GSTRING_LEN, stat->string,
			       ETH_GSTRING_LEN);
			j++;
		}
644
	}
645 646
}

647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662
static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
					uint8_t *data)
{
	mv88e6xxx_stats_get_strings(chip, data,
				    STATS_TYPE_BANK0 | STATS_TYPE_PORT);
}

static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
					uint8_t *data)
{
	mv88e6xxx_stats_get_strings(chip, data,
				    STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
}

static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
				  uint8_t *data)
663
{
V
Vivien Didelot 已提交
664
	struct mv88e6xxx_chip *chip = ds->priv;
665 666 667 668 669 670 671 672

	if (chip->info->ops->stats_get_strings)
		chip->info->ops->stats_get_strings(chip, data);
}

static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
					  int types)
{
673 674 675 676 677
	struct mv88e6xxx_hw_stat *stat;
	int i, j;

	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
		stat = &mv88e6xxx_hw_stats[i];
678
		if (stat->type & types)
679 680 681
			j++;
	}
	return j;
682 683
}

684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705
static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
{
	return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
					      STATS_TYPE_PORT);
}

static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
{
	return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
					      STATS_TYPE_BANK1);
}

static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
{
	struct mv88e6xxx_chip *chip = ds->priv;

	if (chip->info->ops->stats_get_sset_count)
		return chip->info->ops->stats_get_sset_count(chip);

	return 0;
}

706
static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
707 708
				      uint64_t *data, int types,
				      u16 bank1_select, u16 histogram)
709 710 711 712 713 714 715
{
	struct mv88e6xxx_hw_stat *stat;
	int i, j;

	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
		stat = &mv88e6xxx_hw_stats[i];
		if (stat->type & types) {
716 717 718
			data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
							      bank1_select,
							      histogram);
719 720 721 722 723 724 725 726 727
			j++;
		}
	}
}

static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
				      uint64_t *data)
{
	return mv88e6xxx_stats_get_stats(chip, port, data,
728
					 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
729
					 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
730 731 732 733 734 735
}

static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
				      uint64_t *data)
{
	return mv88e6xxx_stats_get_stats(chip, port, data,
736
					 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
737 738
					 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
					 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
739 740 741 742 743 744 745
}

static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
				      uint64_t *data)
{
	return mv88e6xxx_stats_get_stats(chip, port, data,
					 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
746 747
					 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
					 0);
748 749 750 751 752 753 754 755 756
}

static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
				uint64_t *data)
{
	if (chip->info->ops->stats_get_stats)
		chip->info->ops->stats_get_stats(chip, port, data);
}

757 758
static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
					uint64_t *data)
759
{
V
Vivien Didelot 已提交
760
	struct mv88e6xxx_chip *chip = ds->priv;
761 762
	int ret;

763
	mutex_lock(&chip->reg_lock);
764

765
	ret = mv88e6xxx_stats_snapshot(chip, port);
766
	if (ret < 0) {
767
		mutex_unlock(&chip->reg_lock);
768 769
		return;
	}
770 771

	mv88e6xxx_get_stats(chip, port, data);
772

773
	mutex_unlock(&chip->reg_lock);
774 775
}

776 777 778 779 780 781 782 783
static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->stats_set_histogram)
		return chip->info->ops->stats_set_histogram(chip);

	return 0;
}

784
static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
785 786 787 788
{
	return 32 * sizeof(u16);
}

789 790
static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
			       struct ethtool_regs *regs, void *_p)
791
{
V
Vivien Didelot 已提交
792
	struct mv88e6xxx_chip *chip = ds->priv;
793 794
	int err;
	u16 reg;
795 796 797 798 799 800 801
	u16 *p = _p;
	int i;

	regs->version = 0;

	memset(p, 0xff, 32 * sizeof(u16));

802
	mutex_lock(&chip->reg_lock);
803

804 805
	for (i = 0; i < 32; i++) {

806 807 808
		err = mv88e6xxx_port_read(chip, port, i, &reg);
		if (!err)
			p[i] = reg;
809
	}
810

811
	mutex_unlock(&chip->reg_lock);
812 813
}

V
Vivien Didelot 已提交
814 815
static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
				 struct ethtool_eee *e)
816
{
817 818
	/* Nothing to do on the port's MAC */
	return 0;
819 820
}

V
Vivien Didelot 已提交
821 822
static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
				 struct ethtool_eee *e)
823
{
824 825
	/* Nothing to do on the port's MAC */
	return 0;
826 827
}

828
static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
829
{
830 831 832
	struct dsa_switch *ds = NULL;
	struct net_device *br;
	u16 pvlan;
833 834
	int i;

835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854
	if (dev < DSA_MAX_SWITCHES)
		ds = chip->ds->dst->ds[dev];

	/* Prevent frames from unknown switch or port */
	if (!ds || port >= ds->num_ports)
		return 0;

	/* Frames from DSA links and CPU ports can egress any local port */
	if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
		return mv88e6xxx_port_mask(chip);

	br = ds->ports[port].bridge_dev;
	pvlan = 0;

	/* Frames from user ports can egress any local DSA links and CPU ports,
	 * as well as any local member of their bridge group.
	 */
	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
		if (dsa_is_cpu_port(chip->ds, i) ||
		    dsa_is_dsa_port(chip->ds, i) ||
V
Vivien Didelot 已提交
855
		    (br && dsa_to_port(chip->ds, i)->bridge_dev == br))
856 857 858 859 860
			pvlan |= BIT(i);

	return pvlan;
}

861
static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
862 863
{
	u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
864 865 866

	/* prevent frames from going back out of the port they came in on */
	output_ports &= ~BIT(port);
867

868
	return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
869 870
}

871 872
static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
					 u8 state)
873
{
V
Vivien Didelot 已提交
874
	struct mv88e6xxx_chip *chip = ds->priv;
875
	int err;
876

877
	mutex_lock(&chip->reg_lock);
878
	err = mv88e6xxx_port_set_state(chip, port, state);
879
	mutex_unlock(&chip->reg_lock);
880 881

	if (err)
882
		dev_err(ds->dev, "p%d: failed to update state\n", port);
883 884
}

885 886 887 888 889 890 891 892
static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->pot_clear)
		return chip->info->ops->pot_clear(chip);

	return 0;
}

893 894 895 896 897 898 899 900
static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->mgmt_rsvd2cpu)
		return chip->info->ops->mgmt_rsvd2cpu(chip);

	return 0;
}

901 902
static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
{
903 904
	int err;

905 906 907 908
	err = mv88e6xxx_g1_atu_flush(chip, 0, true);
	if (err)
		return err;

909 910 911 912
	err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
	if (err)
		return err;

913 914 915
	return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
}

916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935
static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
{
	int port;
	int err;

	if (!chip->info->ops->irl_init_all)
		return 0;

	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
		/* Disable ingress rate limiting by resetting all per port
		 * ingress rate limit resources to their initial state.
		 */
		err = chip->info->ops->irl_init_all(chip, port);
		if (err)
			return err;
	}

	return 0;
}

936 937 938 939 940 941 942 943 944 945 946 947 948
static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->set_switch_mac) {
		u8 addr[ETH_ALEN];

		eth_random_addr(addr);

		return chip->info->ops->set_switch_mac(chip, addr);
	}

	return 0;
}

949 950 951 952 953 954 955 956 957
static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
{
	u16 pvlan = 0;

	if (!mv88e6xxx_has_pvt(chip))
		return -EOPNOTSUPP;

	/* Skip the local source device, which uses in-chip port VLAN */
	if (dev != chip->ds->index)
958
		pvlan = mv88e6xxx_port_vlan(chip, dev, port);
959 960 961 962

	return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
}

963 964
static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
{
965 966 967
	int dev, port;
	int err;

968 969 970 971 972 973
	if (!mv88e6xxx_has_pvt(chip))
		return 0;

	/* Clear 5 Bit Port for usage with Marvell Link Street devices:
	 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
	 */
974 975 976 977 978 979 980 981 982 983 984 985 986
	err = mv88e6xxx_g2_misc_4_bit_port(chip);
	if (err)
		return err;

	for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
		for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
			err = mv88e6xxx_pvt_map(chip, dev, port);
			if (err)
				return err;
		}
	}

	return 0;
987 988
}

989 990 991 992 993 994
static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int err;

	mutex_lock(&chip->reg_lock);
995
	err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
996 997 998
	mutex_unlock(&chip->reg_lock);

	if (err)
999
		dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
1000 1001
}

1002 1003 1004 1005 1006 1007 1008 1009
static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
{
	if (!chip->info->max_vid)
		return 0;

	return mv88e6xxx_g1_vtu_flush(chip);
}

1010 1011 1012 1013 1014 1015 1016 1017 1018
static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
				 struct mv88e6xxx_vtu_entry *entry)
{
	if (!chip->info->ops->vtu_getnext)
		return -EOPNOTSUPP;

	return chip->info->ops->vtu_getnext(chip, entry);
}

1019 1020 1021 1022 1023 1024 1025 1026 1027
static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
				   struct mv88e6xxx_vtu_entry *entry)
{
	if (!chip->info->ops->vtu_loadpurge)
		return -EOPNOTSUPP;

	return chip->info->ops->vtu_loadpurge(chip, entry);
}

1028
static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1029 1030
{
	DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1031 1032 1033
	struct mv88e6xxx_vtu_entry vlan = {
		.vid = chip->info->max_vid,
	};
1034
	int i, err;
1035 1036 1037

	bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);

1038
	/* Set every FID bit used by the (un)bridged ports */
1039
	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1040
		err = mv88e6xxx_port_get_fid(chip, i, fid);
1041 1042 1043 1044 1045 1046
		if (err)
			return err;

		set_bit(*fid, fid_bitmap);
	}

1047 1048
	/* Set every FID bit used by the VLAN entries */
	do {
1049
		err = mv88e6xxx_vtu_getnext(chip, &vlan);
1050 1051 1052 1053 1054 1055 1056
		if (err)
			return err;

		if (!vlan.valid)
			break;

		set_bit(vlan.fid, fid_bitmap);
1057
	} while (vlan.vid < chip->info->max_vid);
1058 1059 1060 1061 1062

	/* The reset value 0x000 is used to indicate that multiple address
	 * databases are not needed. Return the next positive available.
	 */
	*fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1063
	if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1064 1065 1066
		return -ENOSPC;

	/* Clear the database */
1067
	return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1068 1069
}

1070 1071
static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
			     struct mv88e6xxx_vtu_entry *entry, bool new)
1072 1073 1074 1075 1076 1077
{
	int err;

	if (!vid)
		return -EINVAL;

1078 1079
	entry->vid = vid - 1;
	entry->valid = false;
1080

1081
	err = mv88e6xxx_vtu_getnext(chip, entry);
1082 1083 1084
	if (err)
		return err;

1085 1086
	if (entry->vid == vid && entry->valid)
		return 0;
1087

1088 1089 1090 1091 1092 1093 1094 1095
	if (new) {
		int i;

		/* Initialize a fresh VLAN entry */
		memset(entry, 0, sizeof(*entry));
		entry->valid = true;
		entry->vid = vid;

1096
		/* Exclude all ports */
1097
		for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1098
			entry->member[i] =
1099
				MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1100 1101

		return mv88e6xxx_atu_new(chip, &entry->fid);
1102 1103
	}

1104 1105
	/* switchdev expects -EOPNOTSUPP to honor software VLANs */
	return -EOPNOTSUPP;
1106 1107
}

1108 1109 1110
static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
					u16 vid_begin, u16 vid_end)
{
V
Vivien Didelot 已提交
1111
	struct mv88e6xxx_chip *chip = ds->priv;
1112 1113 1114
	struct mv88e6xxx_vtu_entry vlan = {
		.vid = vid_begin - 1,
	};
1115 1116
	int i, err;

1117 1118 1119 1120
	/* DSA and CPU ports have to be members of multiple vlans */
	if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
		return 0;

1121 1122 1123
	if (!vid_begin)
		return -EOPNOTSUPP;

1124
	mutex_lock(&chip->reg_lock);
1125 1126

	do {
1127
		err = mv88e6xxx_vtu_getnext(chip, &vlan);
1128 1129 1130 1131 1132 1133 1134 1135 1136
		if (err)
			goto unlock;

		if (!vlan.valid)
			break;

		if (vlan.vid > vid_end)
			break;

1137
		for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1138 1139 1140
			if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
				continue;

1141
			if (!ds->ports[i].slave)
1142 1143
				continue;

1144
			if (vlan.member[i] ==
1145
			    MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1146 1147
				continue;

V
Vivien Didelot 已提交
1148
			if (dsa_to_port(ds, i)->bridge_dev ==
1149
			    ds->ports[port].bridge_dev)
1150 1151
				break; /* same bridge, check next VLAN */

V
Vivien Didelot 已提交
1152
			if (!dsa_to_port(ds, i)->bridge_dev)
1153 1154
				continue;

1155 1156
			dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
				port, vlan.vid, i,
V
Vivien Didelot 已提交
1157
				netdev_name(dsa_to_port(ds, i)->bridge_dev));
1158 1159 1160 1161 1162 1163
			err = -EOPNOTSUPP;
			goto unlock;
		}
	} while (vlan.vid < vid_end);

unlock:
1164
	mutex_unlock(&chip->reg_lock);
1165 1166 1167 1168

	return err;
}

1169 1170
static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
					 bool vlan_filtering)
1171
{
V
Vivien Didelot 已提交
1172
	struct mv88e6xxx_chip *chip = ds->priv;
1173 1174
	u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
		MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1175
	int err;
1176

1177
	if (!chip->info->max_vid)
1178 1179
		return -EOPNOTSUPP;

1180
	mutex_lock(&chip->reg_lock);
1181
	err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1182
	mutex_unlock(&chip->reg_lock);
1183

1184
	return err;
1185 1186
}

1187 1188
static int
mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1189
			    const struct switchdev_obj_port_vlan *vlan)
1190
{
V
Vivien Didelot 已提交
1191
	struct mv88e6xxx_chip *chip = ds->priv;
1192 1193
	int err;

1194
	if (!chip->info->max_vid)
1195 1196
		return -EOPNOTSUPP;

1197 1198 1199 1200 1201 1202 1203 1204
	/* If the requested port doesn't belong to the same bridge as the VLAN
	 * members, do not support it (yet) and fallback to software VLAN.
	 */
	err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
					   vlan->vid_end);
	if (err)
		return err;

1205 1206 1207 1208 1209 1210
	/* We don't need any dynamic resource from the kernel (yet),
	 * so skip the prepare phase.
	 */
	return 0;
}

1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254
static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
					const unsigned char *addr, u16 vid,
					u8 state)
{
	struct mv88e6xxx_vtu_entry vlan;
	struct mv88e6xxx_atu_entry entry;
	int err;

	/* Null VLAN ID corresponds to the port private database */
	if (vid == 0)
		err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
	else
		err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
	if (err)
		return err;

	entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
	ether_addr_copy(entry.mac, addr);
	eth_addr_dec(entry.mac);

	err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
	if (err)
		return err;

	/* Initialize a fresh ATU entry if it isn't found */
	if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED ||
	    !ether_addr_equal(entry.mac, addr)) {
		memset(&entry, 0, sizeof(entry));
		ether_addr_copy(entry.mac, addr);
	}

	/* Purge the ATU entry only if no port is using it anymore */
	if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
		entry.portvec &= ~BIT(port);
		if (!entry.portvec)
			entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
	} else {
		entry.portvec |= BIT(port);
		entry.state = state;
	}

	return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
}

1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277
static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
					u16 vid)
{
	const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
	u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;

	return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
}

static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
{
	int port;
	int err;

	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
		err = mv88e6xxx_port_add_broadcast(chip, port, vid);
		if (err)
			return err;
	}

	return 0;
}

1278
static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1279
				    u16 vid, u8 member)
1280
{
1281
	struct mv88e6xxx_vtu_entry vlan;
1282 1283
	int err;

1284
	err = mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1285
	if (err)
1286
		return err;
1287

1288
	vlan.member[port] = member;
1289

1290 1291 1292 1293 1294
	err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
	if (err)
		return err;

	return mv88e6xxx_broadcast_setup(chip, vid);
1295 1296
}

1297
static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1298
				    const struct switchdev_obj_port_vlan *vlan)
1299
{
V
Vivien Didelot 已提交
1300
	struct mv88e6xxx_chip *chip = ds->priv;
1301 1302
	bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
	bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1303
	u8 member;
1304 1305
	u16 vid;

1306
	if (!chip->info->max_vid)
1307 1308
		return;

1309
	if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1310
		member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
1311
	else if (untagged)
1312
		member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
1313
	else
1314
		member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
1315

1316
	mutex_lock(&chip->reg_lock);
1317

1318
	for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1319
		if (_mv88e6xxx_port_vlan_add(chip, port, vid, member))
1320 1321
			dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
				vid, untagged ? 'u' : 't');
1322

1323
	if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
1324 1325
		dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
			vlan->vid_end);
1326

1327
	mutex_unlock(&chip->reg_lock);
1328 1329
}

1330
static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1331
				    int port, u16 vid)
1332
{
1333
	struct mv88e6xxx_vtu_entry vlan;
1334 1335
	int i, err;

1336
	err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1337
	if (err)
1338
		return err;
1339

1340
	/* Tell switchdev if this VLAN is handled in software */
1341
	if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1342
		return -EOPNOTSUPP;
1343

1344
	vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1345 1346

	/* keep the VLAN unless all ports are excluded */
1347
	vlan.valid = false;
1348
	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1349 1350
		if (vlan.member[i] !=
		    MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1351
			vlan.valid = true;
1352 1353 1354 1355
			break;
		}
	}

1356
	err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1357 1358 1359
	if (err)
		return err;

1360
	return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
1361 1362
}

1363 1364
static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
				   const struct switchdev_obj_port_vlan *vlan)
1365
{
V
Vivien Didelot 已提交
1366
	struct mv88e6xxx_chip *chip = ds->priv;
1367 1368 1369
	u16 pvid, vid;
	int err = 0;

1370
	if (!chip->info->max_vid)
1371 1372
		return -EOPNOTSUPP;

1373
	mutex_lock(&chip->reg_lock);
1374

1375
	err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1376 1377 1378
	if (err)
		goto unlock;

1379
	for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1380
		err = _mv88e6xxx_port_vlan_del(chip, port, vid);
1381 1382 1383 1384
		if (err)
			goto unlock;

		if (vid == pvid) {
1385
			err = mv88e6xxx_port_set_pvid(chip, port, 0);
1386 1387 1388 1389 1390
			if (err)
				goto unlock;
		}
	}

1391
unlock:
1392
	mutex_unlock(&chip->reg_lock);
1393 1394 1395 1396

	return err;
}

1397 1398
static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
				  const unsigned char *addr, u16 vid)
1399
{
V
Vivien Didelot 已提交
1400
	struct mv88e6xxx_chip *chip = ds->priv;
1401
	int err;
1402

1403
	mutex_lock(&chip->reg_lock);
1404 1405
	err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
					   MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1406
	mutex_unlock(&chip->reg_lock);
1407 1408

	return err;
1409 1410
}

1411
static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1412
				  const unsigned char *addr, u16 vid)
1413
{
V
Vivien Didelot 已提交
1414
	struct mv88e6xxx_chip *chip = ds->priv;
1415
	int err;
1416

1417
	mutex_lock(&chip->reg_lock);
1418
	err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1419
					   MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
1420
	mutex_unlock(&chip->reg_lock);
1421

1422
	return err;
1423 1424
}

1425 1426
static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
				      u16 fid, u16 vid, int port,
1427
				      dsa_fdb_dump_cb_t *cb, void *data)
1428
{
1429
	struct mv88e6xxx_atu_entry addr;
1430
	bool is_static;
1431 1432
	int err;

1433
	addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1434
	eth_broadcast_addr(addr.mac);
1435 1436

	do {
1437
		err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
1438
		if (err)
1439
			return err;
1440

1441
		if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED)
1442 1443
			break;

1444
		if (addr.trunk || (addr.portvec & BIT(port)) == 0)
1445 1446
			continue;

1447 1448
		if (!is_unicast_ether_addr(addr.mac))
			continue;
1449

1450 1451 1452
		is_static = (addr.state ==
			     MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
		err = cb(addr.mac, vid, is_static, data);
1453 1454
		if (err)
			return err;
1455 1456 1457 1458 1459
	} while (!is_broadcast_ether_addr(addr.mac));

	return err;
}

1460
static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
1461
				  dsa_fdb_dump_cb_t *cb, void *data)
1462
{
1463
	struct mv88e6xxx_vtu_entry vlan = {
1464
		.vid = chip->info->max_vid,
1465
	};
1466
	u16 fid;
1467 1468
	int err;

1469
	/* Dump port's default Filtering Information Database (VLAN ID 0) */
1470
	err = mv88e6xxx_port_get_fid(chip, port, &fid);
1471
	if (err)
1472
		return err;
1473

1474
	err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
1475
	if (err)
1476
		return err;
1477

1478
	/* Dump VLANs' Filtering Information Databases */
1479
	do {
1480
		err = mv88e6xxx_vtu_getnext(chip, &vlan);
1481
		if (err)
1482
			return err;
1483 1484 1485 1486

		if (!vlan.valid)
			break;

1487
		err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
1488
						 cb, data);
1489
		if (err)
1490
			return err;
1491
	} while (vlan.vid < chip->info->max_vid);
1492

1493 1494 1495 1496
	return err;
}

static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
1497
				   dsa_fdb_dump_cb_t *cb, void *data)
1498
{
V
Vivien Didelot 已提交
1499
	struct mv88e6xxx_chip *chip = ds->priv;
1500 1501 1502
	int err;

	mutex_lock(&chip->reg_lock);
1503
	err = mv88e6xxx_port_db_dump(chip, port, cb, data);
1504
	mutex_unlock(&chip->reg_lock);
1505 1506 1507 1508

	return err;
}

1509 1510
static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
				struct net_device *br)
1511
{
1512
	struct dsa_switch *ds;
1513
	int port;
1514
	int dev;
1515
	int err;
1516

1517 1518 1519 1520
	/* Remap the Port VLAN of each local bridge group member */
	for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
		if (chip->ds->ports[port].bridge_dev == br) {
			err = mv88e6xxx_port_vlan_map(chip, port);
1521
			if (err)
1522
				return err;
1523 1524 1525
		}
	}

1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543
	if (!mv88e6xxx_has_pvt(chip))
		return 0;

	/* Remap the Port VLAN of each cross-chip bridge group member */
	for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) {
		ds = chip->ds->dst->ds[dev];
		if (!ds)
			break;

		for (port = 0; port < ds->num_ports; ++port) {
			if (ds->ports[port].bridge_dev == br) {
				err = mv88e6xxx_pvt_map(chip, dev, port);
				if (err)
					return err;
			}
		}
	}

1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554
	return 0;
}

static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
				      struct net_device *br)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int err;

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_bridge_map(chip, br);
1555
	mutex_unlock(&chip->reg_lock);
1556

1557
	return err;
1558 1559
}

1560 1561
static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
					struct net_device *br)
1562
{
V
Vivien Didelot 已提交
1563
	struct mv88e6xxx_chip *chip = ds->priv;
1564

1565
	mutex_lock(&chip->reg_lock);
1566 1567 1568
	if (mv88e6xxx_bridge_map(chip, br) ||
	    mv88e6xxx_port_vlan_map(chip, port))
		dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
1569
	mutex_unlock(&chip->reg_lock);
1570 1571
}

1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601
static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
					   int port, struct net_device *br)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int err;

	if (!mv88e6xxx_has_pvt(chip))
		return 0;

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_pvt_map(chip, dev, port);
	mutex_unlock(&chip->reg_lock);

	return err;
}

static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
					     int port, struct net_device *br)
{
	struct mv88e6xxx_chip *chip = ds->priv;

	if (!mv88e6xxx_has_pvt(chip))
		return;

	mutex_lock(&chip->reg_lock);
	if (mv88e6xxx_pvt_map(chip, dev, port))
		dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
	mutex_unlock(&chip->reg_lock);
}

1602 1603 1604 1605 1606 1607 1608 1609
static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->reset)
		return chip->info->ops->reset(chip);

	return 0;
}

1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622
static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
{
	struct gpio_desc *gpiod = chip->reset;

	/* If there is a GPIO connected to the reset pin, toggle it */
	if (gpiod) {
		gpiod_set_value_cansleep(gpiod, 1);
		usleep_range(10000, 20000);
		gpiod_set_value_cansleep(gpiod, 0);
		usleep_range(10000, 20000);
	}
}

1623
static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
1624
{
1625
	int i, err;
1626

1627
	/* Set all ports to the Disabled state */
1628
	for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
1629
		err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
1630 1631
		if (err)
			return err;
1632 1633
	}

1634 1635 1636
	/* Wait for transmit queues to drain,
	 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
	 */
1637 1638
	usleep_range(2000, 4000);

1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649
	return 0;
}

static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
{
	int err;

	err = mv88e6xxx_disable_ports(chip);
	if (err)
		return err;

1650
	mv88e6xxx_hardware_reset(chip);
1651

1652
	return mv88e6xxx_software_reset(chip);
1653 1654
}

1655
static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
1656 1657
				   enum mv88e6xxx_frame_mode frame,
				   enum mv88e6xxx_egress_mode egress, u16 etype)
1658 1659 1660
{
	int err;

1661 1662 1663 1664
	if (!chip->info->ops->port_set_frame_mode)
		return -EOPNOTSUPP;

	err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
1665 1666 1667
	if (err)
		return err;

1668 1669 1670 1671 1672 1673 1674 1675
	err = chip->info->ops->port_set_frame_mode(chip, port, frame);
	if (err)
		return err;

	if (chip->info->ops->port_set_ether_type)
		return chip->info->ops->port_set_ether_type(chip, port, etype);

	return 0;
1676 1677
}

1678
static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
1679
{
1680
	return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
1681
				       MV88E6XXX_EGRESS_MODE_UNMODIFIED,
1682
				       MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
1683
}
1684

1685 1686 1687
static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
{
	return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
1688
				       MV88E6XXX_EGRESS_MODE_UNMODIFIED,
1689
				       MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
1690
}
1691

1692 1693 1694 1695
static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
{
	return mv88e6xxx_set_port_mode(chip, port,
				       MV88E6XXX_FRAME_MODE_ETHERTYPE,
1696 1697
				       MV88E6XXX_EGRESS_MODE_ETHERTYPE,
				       ETH_P_EDSA);
1698
}
1699

1700 1701 1702 1703
static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
{
	if (dsa_is_dsa_port(chip->ds, port))
		return mv88e6xxx_set_port_mode_dsa(chip, port);
1704

1705
	if (dsa_is_user_port(chip->ds, port))
1706
		return mv88e6xxx_set_port_mode_normal(chip, port);
1707

1708 1709 1710
	/* Setup CPU port mode depending on its supported tag format */
	if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
		return mv88e6xxx_set_port_mode_dsa(chip, port);
1711

1712 1713
	if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
		return mv88e6xxx_set_port_mode_edsa(chip, port);
1714

1715
	return -EINVAL;
1716 1717
}

1718
static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
1719
{
1720
	bool message = dsa_is_dsa_port(chip->ds, port);
1721

1722
	return mv88e6xxx_port_set_message_port(chip, port, message);
1723
}
1724

1725
static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
1726
{
1727 1728
	struct dsa_switch *ds = chip->ds;
	bool flood;
1729

1730
	/* Upstream ports flood frames with unknown unicast or multicast DA */
1731
	flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port);
1732 1733 1734
	if (chip->info->ops->port_set_egress_floods)
		return chip->info->ops->port_set_egress_floods(chip, port,
							       flood, flood);
1735

1736
	return 0;
1737 1738
}

1739 1740 1741
static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
				  bool on)
{
1742 1743
	if (chip->info->ops->serdes_power)
		return chip->info->ops->serdes_power(chip, port, on);
1744

1745
	return 0;
1746 1747
}

1748 1749 1750 1751 1752 1753
static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
{
	struct dsa_switch *ds = chip->ds;
	int upstream_port;
	int err;

1754
	upstream_port = dsa_upstream_port(ds, port);
1755 1756 1757 1758 1759 1760 1761
	if (chip->info->ops->port_set_upstream_port) {
		err = chip->info->ops->port_set_upstream_port(chip, port,
							      upstream_port);
		if (err)
			return err;
	}

1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777
	if (port == upstream_port) {
		if (chip->info->ops->set_cpu_port) {
			err = chip->info->ops->set_cpu_port(chip,
							    upstream_port);
			if (err)
				return err;
		}

		if (chip->info->ops->set_egress_port) {
			err = chip->info->ops->set_egress_port(chip,
							       upstream_port);
			if (err)
				return err;
		}
	}

1778 1779 1780
	return 0;
}

1781
static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
1782
{
1783
	struct dsa_switch *ds = chip->ds;
1784
	int err;
1785
	u16 reg;
1786

1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800
	/* MAC Forcing register: don't force link, speed, duplex or flow control
	 * state to any particular values on physical ports, but force the CPU
	 * port and all DSA ports to their maximum bandwidth and full duplex.
	 */
	if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
		err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
					       SPEED_MAX, DUPLEX_FULL,
					       PHY_INTERFACE_MODE_NA);
	else
		err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
					       SPEED_UNFORCED, DUPLEX_UNFORCED,
					       PHY_INTERFACE_MODE_NA);
	if (err)
		return err;
1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815

	/* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
	 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
	 * tunneling, determine priority by looking at 802.1p and IP
	 * priority fields (IP prio has precedence), and set STP state
	 * to Forwarding.
	 *
	 * If this is the CPU link, use DSA or EDSA tagging depending
	 * on which tagging mode was configured.
	 *
	 * If this is a link to another switch, use DSA tagging mode.
	 *
	 * If this is the upstream port for this switch, enable
	 * forwarding of unknown unicasts and multicasts.
	 */
1816 1817 1818 1819
	reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
		MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
		MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
1820 1821
	if (err)
		return err;
1822

1823
	err = mv88e6xxx_setup_port_mode(chip, port);
1824 1825
	if (err)
		return err;
1826

1827
	err = mv88e6xxx_setup_egress_floods(chip, port);
1828 1829 1830
	if (err)
		return err;

1831 1832 1833
	/* Enable the SERDES interface for DSA and CPU ports. Normal
	 * ports SERDES are enabled when the port is enabled, thus
	 * saving a bit of power.
1834
	 */
1835 1836 1837 1838 1839
	if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) {
		err = mv88e6xxx_serdes_power(chip, port, true);
		if (err)
			return err;
	}
1840

1841
	/* Port Control 2: don't force a good FCS, set the maximum frame size to
1842
	 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
1843 1844 1845
	 * untagged frames on this port, do a destination address lookup on all
	 * received packets as usual, disable ARP mirroring and don't send a
	 * copy of all transmitted/received frames on this port to the CPU.
1846
	 */
1847 1848 1849
	err = mv88e6xxx_port_set_map_da(chip, port);
	if (err)
		return err;
1850

1851 1852 1853
	err = mv88e6xxx_setup_upstream_port(chip, port);
	if (err)
		return err;
1854

1855
	err = mv88e6xxx_port_set_8021q_mode(chip, port,
1856
				MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
1857 1858 1859
	if (err)
		return err;

1860 1861
	if (chip->info->ops->port_set_jumbo_size) {
		err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
1862 1863 1864 1865
		if (err)
			return err;
	}

1866 1867 1868 1869 1870
	/* Port Association Vector: when learning source addresses
	 * of packets, add the address to the address database using
	 * a port bitmap that has only the bit for this port set and
	 * the other bits clear.
	 */
1871
	reg = 1 << port;
1872 1873
	/* Disable learning for CPU port */
	if (dsa_is_cpu_port(ds, port))
1874
		reg = 0;
1875

1876 1877
	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
				   reg);
1878 1879
	if (err)
		return err;
1880 1881

	/* Egress rate control 2: disable egress rate control. */
1882 1883
	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
				   0x0000);
1884 1885
	if (err)
		return err;
1886

1887 1888
	if (chip->info->ops->port_pause_limit) {
		err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
1889 1890
		if (err)
			return err;
1891
	}
1892

1893 1894 1895 1896 1897 1898
	if (chip->info->ops->port_disable_learn_limit) {
		err = chip->info->ops->port_disable_learn_limit(chip, port);
		if (err)
			return err;
	}

1899 1900
	if (chip->info->ops->port_disable_pri_override) {
		err = chip->info->ops->port_disable_pri_override(chip, port);
1901 1902
		if (err)
			return err;
1903
	}
1904

1905 1906
	if (chip->info->ops->port_tag_remap) {
		err = chip->info->ops->port_tag_remap(chip, port);
1907 1908
		if (err)
			return err;
1909 1910
	}

1911 1912
	if (chip->info->ops->port_egress_rate_limiting) {
		err = chip->info->ops->port_egress_rate_limiting(chip, port);
1913 1914
		if (err)
			return err;
1915 1916
	}

1917
	err = mv88e6xxx_setup_message_port(chip, port);
1918 1919
	if (err)
		return err;
1920

1921
	/* Port based VLAN map: give each port the same default address
1922 1923
	 * database, and allow bidirectional communication between the
	 * CPU and DSA port(s), and the other ports.
1924
	 */
1925
	err = mv88e6xxx_port_set_fid(chip, port, 0);
1926 1927
	if (err)
		return err;
1928

1929
	err = mv88e6xxx_port_vlan_map(chip, port);
1930 1931
	if (err)
		return err;
1932 1933 1934 1935

	/* Default VLAN ID and priority: don't set a default VLAN
	 * ID, and set the default packet priority to zero.
	 */
1936
	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
1937 1938
}

1939 1940 1941 1942
static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
				 struct phy_device *phydev)
{
	struct mv88e6xxx_chip *chip = ds->priv;
1943
	int err;
1944 1945

	mutex_lock(&chip->reg_lock);
1946
	err = mv88e6xxx_serdes_power(chip, port, true);
1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957
	mutex_unlock(&chip->reg_lock);

	return err;
}

static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port,
				   struct phy_device *phydev)
{
	struct mv88e6xxx_chip *chip = ds->priv;

	mutex_lock(&chip->reg_lock);
1958 1959
	if (mv88e6xxx_serdes_power(chip, port, false))
		dev_err(chip->dev, "failed to power off SERDES\n");
1960 1961 1962
	mutex_unlock(&chip->reg_lock);
}

1963 1964 1965
static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
				     unsigned int ageing_time)
{
V
Vivien Didelot 已提交
1966
	struct mv88e6xxx_chip *chip = ds->priv;
1967 1968 1969
	int err;

	mutex_lock(&chip->reg_lock);
1970
	err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
1971 1972 1973 1974 1975
	mutex_unlock(&chip->reg_lock);

	return err;
}

1976
static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
1977
{
1978
	struct dsa_switch *ds = chip->ds;
1979
	int err;
1980

1981
	/* Disable remote management, and set the switch's DSA device number. */
1982 1983
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2,
				 MV88E6XXX_G1_CTL2_MULTIPLE_CASCADE |
1984
				 (ds->index & 0x1f));
1985 1986 1987
	if (err)
		return err;

1988
	/* Configure the IP ToS mapping registers. */
1989
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000);
1990
	if (err)
1991
		return err;
1992
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000);
1993
	if (err)
1994
		return err;
1995
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555);
1996
	if (err)
1997
		return err;
1998
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555);
1999
	if (err)
2000
		return err;
2001
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa);
2002
	if (err)
2003
		return err;
2004
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa);
2005
	if (err)
2006
		return err;
2007
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff);
2008
	if (err)
2009
		return err;
2010
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff);
2011
	if (err)
2012
		return err;
2013 2014

	/* Configure the IEEE 802.1p priority mapping register. */
2015
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41);
2016
	if (err)
2017
		return err;
2018

2019 2020 2021 2022 2023
	/* Initialize the statistics unit */
	err = mv88e6xxx_stats_set_histogram(chip);
	if (err)
		return err;

2024
	return mv88e6xxx_g1_stats_clear(chip);
2025 2026
}

2027
static int mv88e6xxx_setup(struct dsa_switch *ds)
2028
{
V
Vivien Didelot 已提交
2029
	struct mv88e6xxx_chip *chip = ds->priv;
2030
	int err;
2031 2032
	int i;

2033
	chip->ds = ds;
2034
	ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
2035

2036
	mutex_lock(&chip->reg_lock);
2037

2038
	/* Setup Switch Port Registers */
2039
	for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2040 2041 2042
		if (dsa_is_unused_port(ds, i))
			continue;

2043 2044 2045 2046 2047 2048 2049
		err = mv88e6xxx_setup_port(chip, i);
		if (err)
			goto unlock;
	}

	/* Setup Switch Global 1 Registers */
	err = mv88e6xxx_g1_setup(chip);
2050 2051 2052
	if (err)
		goto unlock;

2053
	/* Setup Switch Global 2 Registers */
2054
	if (chip->info->global2_addr) {
2055
		err = mv88e6xxx_g2_setup(chip);
2056 2057 2058
		if (err)
			goto unlock;
	}
2059

2060 2061 2062 2063
	err = mv88e6xxx_irl_setup(chip);
	if (err)
		goto unlock;

2064 2065 2066 2067
	err = mv88e6xxx_mac_setup(chip);
	if (err)
		goto unlock;

2068 2069 2070 2071
	err = mv88e6xxx_phy_setup(chip);
	if (err)
		goto unlock;

2072 2073 2074 2075
	err = mv88e6xxx_vtu_setup(chip);
	if (err)
		goto unlock;

2076 2077 2078 2079
	err = mv88e6xxx_pvt_setup(chip);
	if (err)
		goto unlock;

2080 2081 2082 2083
	err = mv88e6xxx_atu_setup(chip);
	if (err)
		goto unlock;

2084 2085 2086 2087
	err = mv88e6xxx_broadcast_setup(chip, 0);
	if (err)
		goto unlock;

2088 2089 2090 2091
	err = mv88e6xxx_pot_setup(chip);
	if (err)
		goto unlock;

2092 2093 2094
	err = mv88e6xxx_rsvd2cpu_setup(chip);
	if (err)
		goto unlock;
2095

2096 2097 2098 2099 2100 2101 2102
	/* Setup PTP Hardware Clock */
	if (chip->info->ptp_support) {
		err = mv88e6xxx_ptp_setup(chip);
		if (err)
			goto unlock;
	}

2103
unlock:
2104
	mutex_unlock(&chip->reg_lock);
2105

2106
	return err;
2107 2108
}

2109
static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
2110
{
2111 2112
	struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
	struct mv88e6xxx_chip *chip = mdio_bus->chip;
2113 2114
	u16 val;
	int err;
2115

2116 2117 2118
	if (!chip->info->ops->phy_read)
		return -EOPNOTSUPP;

2119
	mutex_lock(&chip->reg_lock);
2120
	err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
2121
	mutex_unlock(&chip->reg_lock);
2122

2123 2124 2125 2126 2127
	if (reg == MII_PHYSID2) {
		/* Some internal PHYS don't have a model number.  Use
		 * the mv88e6390 family model number instead.
		 */
		if (!(val & 0x3f0))
2128
			val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
2129 2130
	}

2131
	return err ? err : val;
2132 2133
}

2134
static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
2135
{
2136 2137
	struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
	struct mv88e6xxx_chip *chip = mdio_bus->chip;
2138
	int err;
2139

2140 2141 2142
	if (!chip->info->ops->phy_write)
		return -EOPNOTSUPP;

2143
	mutex_lock(&chip->reg_lock);
2144
	err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
2145
	mutex_unlock(&chip->reg_lock);
2146 2147

	return err;
2148 2149
}

2150
static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
2151 2152
				   struct device_node *np,
				   bool external)
2153 2154
{
	static int index;
2155
	struct mv88e6xxx_mdio_bus *mdio_bus;
2156 2157 2158
	struct mii_bus *bus;
	int err;

2159
	bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
2160 2161 2162
	if (!bus)
		return -ENOMEM;

2163
	mdio_bus = bus->priv;
2164
	mdio_bus->bus = bus;
2165
	mdio_bus->chip = chip;
2166 2167
	INIT_LIST_HEAD(&mdio_bus->list);
	mdio_bus->external = external;
2168

2169 2170
	if (np) {
		bus->name = np->full_name;
2171
		snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
2172 2173 2174 2175 2176 2177 2178
	} else {
		bus->name = "mv88e6xxx SMI";
		snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
	}

	bus->read = mv88e6xxx_mdio_read;
	bus->write = mv88e6xxx_mdio_write;
2179
	bus->parent = chip->dev;
2180

2181 2182
	if (np)
		err = of_mdiobus_register(bus, np);
2183 2184 2185
	else
		err = mdiobus_register(bus);
	if (err) {
2186
		dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
2187
		return err;
2188
	}
2189 2190 2191 2192 2193

	if (external)
		list_add_tail(&mdio_bus->list, &chip->mdios);
	else
		list_add(&mdio_bus->list, &chip->mdios);
2194 2195

	return 0;
2196
}
2197

2198 2199 2200 2201 2202
static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
	{ .compatible = "marvell,mv88e6xxx-mdio-external",
	  .data = (void *)true },
	{ },
};
2203

2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216
static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)

{
	struct mv88e6xxx_mdio_bus *mdio_bus;
	struct mii_bus *bus;

	list_for_each_entry(mdio_bus, &chip->mdios, list) {
		bus = mdio_bus->bus;

		mdiobus_unregister(bus);
	}
}

2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240
static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
				    struct device_node *np)
{
	const struct of_device_id *match;
	struct device_node *child;
	int err;

	/* Always register one mdio bus for the internal/default mdio
	 * bus. This maybe represented in the device tree, but is
	 * optional.
	 */
	child = of_get_child_by_name(np, "mdio");
	err = mv88e6xxx_mdio_register(chip, child, false);
	if (err)
		return err;

	/* Walk the device tree, and see if there are any other nodes
	 * which say they are compatible with the external mdio
	 * bus.
	 */
	for_each_available_child_of_node(np, child) {
		match = of_match_node(mv88e6xxx_mdio_external_match, child);
		if (match) {
			err = mv88e6xxx_mdio_register(chip, child, true);
2241 2242
			if (err) {
				mv88e6xxx_mdios_unregister(chip);
2243
				return err;
2244
			}
2245 2246 2247 2248
		}
	}

	return 0;
2249 2250
}

2251 2252
static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
{
V
Vivien Didelot 已提交
2253
	struct mv88e6xxx_chip *chip = ds->priv;
2254 2255 2256 2257 2258 2259 2260

	return chip->eeprom_len;
}

static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
				struct ethtool_eeprom *eeprom, u8 *data)
{
V
Vivien Didelot 已提交
2261
	struct mv88e6xxx_chip *chip = ds->priv;
2262 2263
	int err;

2264 2265
	if (!chip->info->ops->get_eeprom)
		return -EOPNOTSUPP;
2266

2267 2268
	mutex_lock(&chip->reg_lock);
	err = chip->info->ops->get_eeprom(chip, eeprom, data);
2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281
	mutex_unlock(&chip->reg_lock);

	if (err)
		return err;

	eeprom->magic = 0xc3ec4951;

	return 0;
}

static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
				struct ethtool_eeprom *eeprom, u8 *data)
{
V
Vivien Didelot 已提交
2282
	struct mv88e6xxx_chip *chip = ds->priv;
2283 2284
	int err;

2285 2286 2287
	if (!chip->info->ops->set_eeprom)
		return -EOPNOTSUPP;

2288 2289 2290 2291
	if (eeprom->magic != 0xc3ec4951)
		return -EINVAL;

	mutex_lock(&chip->reg_lock);
2292
	err = chip->info->ops->set_eeprom(chip, eeprom, data);
2293 2294 2295 2296 2297
	mutex_unlock(&chip->reg_lock);

	return err;
}

2298
static const struct mv88e6xxx_ops mv88e6085_ops = {
2299
	/* MV88E6XXX_FAMILY_6097 */
2300
	.irl_init_all = mv88e6352_g2_irl_init_all,
2301
	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2302 2303
	.phy_read = mv88e6185_phy_ppu_read,
	.phy_write = mv88e6185_phy_ppu_write,
2304
	.port_set_link = mv88e6xxx_port_set_link,
2305
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2306
	.port_set_speed = mv88e6185_port_set_speed,
2307
	.port_tag_remap = mv88e6095_port_tag_remap,
2308
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2309
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2310
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2311
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2312
	.port_pause_limit = mv88e6097_port_pause_limit,
2313
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2314
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2315
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2316
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2317 2318
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2319
	.stats_get_stats = mv88e6095_stats_get_stats,
2320 2321
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2322
	.watchdog_ops = &mv88e6097_watchdog_ops,
2323
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2324
	.pot_clear = mv88e6xxx_g2_pot_clear,
2325 2326
	.ppu_enable = mv88e6185_g1_ppu_enable,
	.ppu_disable = mv88e6185_g1_ppu_disable,
2327
	.reset = mv88e6185_g1_reset,
2328
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2329
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2330 2331 2332
};

static const struct mv88e6xxx_ops mv88e6095_ops = {
2333
	/* MV88E6XXX_FAMILY_6095 */
2334
	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2335 2336
	.phy_read = mv88e6185_phy_ppu_read,
	.phy_write = mv88e6185_phy_ppu_write,
2337
	.port_set_link = mv88e6xxx_port_set_link,
2338
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2339
	.port_set_speed = mv88e6185_port_set_speed,
2340
	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
2341
	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
2342
	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
2343
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2344
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2345 2346
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2347
	.stats_get_stats = mv88e6095_stats_get_stats,
2348
	.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2349 2350
	.ppu_enable = mv88e6185_g1_ppu_enable,
	.ppu_disable = mv88e6185_g1_ppu_disable,
2351
	.reset = mv88e6185_g1_reset,
2352
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
2353
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2354 2355
};

2356
static const struct mv88e6xxx_ops mv88e6097_ops = {
2357
	/* MV88E6XXX_FAMILY_6097 */
2358
	.irl_init_all = mv88e6352_g2_irl_init_all,
2359 2360 2361 2362 2363 2364
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_speed = mv88e6185_port_set_speed,
2365
	.port_tag_remap = mv88e6095_port_tag_remap,
2366
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2367
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2368
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2369
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2370
	.port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2371
	.port_pause_limit = mv88e6097_port_pause_limit,
2372
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2373
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2374
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2375
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2376 2377 2378
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
	.stats_get_stats = mv88e6095_stats_get_stats,
2379 2380
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2381
	.watchdog_ops = &mv88e6097_watchdog_ops,
2382
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2383
	.pot_clear = mv88e6xxx_g2_pot_clear,
2384
	.reset = mv88e6352_g1_reset,
2385
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2386
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2387 2388
};

2389
static const struct mv88e6xxx_ops mv88e6123_ops = {
2390
	/* MV88E6XXX_FAMILY_6165 */
2391
	.irl_init_all = mv88e6352_g2_irl_init_all,
2392
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2393 2394
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2395
	.port_set_link = mv88e6xxx_port_set_link,
2396
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2397
	.port_set_speed = mv88e6185_port_set_speed,
2398
	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
2399
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2400
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2401
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2402
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2403
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2404 2405
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2406
	.stats_get_stats = mv88e6095_stats_get_stats,
2407 2408
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2409
	.watchdog_ops = &mv88e6097_watchdog_ops,
2410
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2411
	.pot_clear = mv88e6xxx_g2_pot_clear,
2412
	.reset = mv88e6352_g1_reset,
2413
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2414
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2415 2416 2417
};

static const struct mv88e6xxx_ops mv88e6131_ops = {
2418
	/* MV88E6XXX_FAMILY_6185 */
2419
	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2420 2421
	.phy_read = mv88e6185_phy_ppu_read,
	.phy_write = mv88e6185_phy_ppu_write,
2422
	.port_set_link = mv88e6xxx_port_set_link,
2423
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2424
	.port_set_speed = mv88e6185_port_set_speed,
2425
	.port_tag_remap = mv88e6095_port_tag_remap,
2426
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2427
	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
2428
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2429
	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
2430
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2431
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2432
	.port_pause_limit = mv88e6097_port_pause_limit,
2433
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2434
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2435 2436
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2437
	.stats_get_stats = mv88e6095_stats_get_stats,
2438 2439
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2440
	.watchdog_ops = &mv88e6097_watchdog_ops,
2441
	.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2442 2443
	.ppu_enable = mv88e6185_g1_ppu_enable,
	.ppu_disable = mv88e6185_g1_ppu_disable,
2444
	.reset = mv88e6185_g1_reset,
2445
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
2446
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2447 2448
};

2449 2450
static const struct mv88e6xxx_ops mv88e6141_ops = {
	/* MV88E6XXX_FAMILY_6341 */
2451
	.irl_init_all = mv88e6352_g2_irl_init_all,
2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
	.port_tag_remap = mv88e6095_port_tag_remap,
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2465
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2466
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2467
	.port_pause_limit = mv88e6097_port_pause_limit,
2468 2469 2470
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
2471
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2472 2473 2474
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
	.stats_get_stats = mv88e6390_stats_get_stats,
2475 2476
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
2477 2478
	.watchdog_ops = &mv88e6390_watchdog_ops,
	.mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
2479
	.pot_clear = mv88e6xxx_g2_pot_clear,
2480
	.reset = mv88e6352_g1_reset,
2481
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2482
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2483 2484
};

2485
static const struct mv88e6xxx_ops mv88e6161_ops = {
2486
	/* MV88E6XXX_FAMILY_6165 */
2487
	.irl_init_all = mv88e6352_g2_irl_init_all,
2488
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2489 2490
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2491
	.port_set_link = mv88e6xxx_port_set_link,
2492
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2493
	.port_set_speed = mv88e6185_port_set_speed,
2494
	.port_tag_remap = mv88e6095_port_tag_remap,
2495
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2496
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2497
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2498
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2499
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2500
	.port_pause_limit = mv88e6097_port_pause_limit,
2501
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2502
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2503
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2504
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2505 2506
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2507
	.stats_get_stats = mv88e6095_stats_get_stats,
2508 2509
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2510
	.watchdog_ops = &mv88e6097_watchdog_ops,
2511
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2512
	.pot_clear = mv88e6xxx_g2_pot_clear,
2513
	.reset = mv88e6352_g1_reset,
2514
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2515
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2516 2517 2518
};

static const struct mv88e6xxx_ops mv88e6165_ops = {
2519
	/* MV88E6XXX_FAMILY_6165 */
2520
	.irl_init_all = mv88e6352_g2_irl_init_all,
2521
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2522 2523
	.phy_read = mv88e6165_phy_read,
	.phy_write = mv88e6165_phy_write,
2524
	.port_set_link = mv88e6xxx_port_set_link,
2525
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2526
	.port_set_speed = mv88e6185_port_set_speed,
2527
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2528
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2529
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2530
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2531 2532
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2533
	.stats_get_stats = mv88e6095_stats_get_stats,
2534 2535
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2536
	.watchdog_ops = &mv88e6097_watchdog_ops,
2537
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2538
	.pot_clear = mv88e6xxx_g2_pot_clear,
2539
	.reset = mv88e6352_g1_reset,
2540
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2541
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2542 2543 2544
};

static const struct mv88e6xxx_ops mv88e6171_ops = {
2545
	/* MV88E6XXX_FAMILY_6351 */
2546
	.irl_init_all = mv88e6352_g2_irl_init_all,
2547
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2548 2549
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2550
	.port_set_link = mv88e6xxx_port_set_link,
2551
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2552
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2553
	.port_set_speed = mv88e6185_port_set_speed,
2554
	.port_tag_remap = mv88e6095_port_tag_remap,
2555
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2556
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2557
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2558
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2559
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2560
	.port_pause_limit = mv88e6097_port_pause_limit,
2561
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2562
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2563
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2564
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2565 2566
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2567
	.stats_get_stats = mv88e6095_stats_get_stats,
2568 2569
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2570
	.watchdog_ops = &mv88e6097_watchdog_ops,
2571
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2572
	.pot_clear = mv88e6xxx_g2_pot_clear,
2573
	.reset = mv88e6352_g1_reset,
2574
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2575
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2576 2577 2578
};

static const struct mv88e6xxx_ops mv88e6172_ops = {
2579
	/* MV88E6XXX_FAMILY_6352 */
2580
	.irl_init_all = mv88e6352_g2_irl_init_all,
2581 2582
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
2583
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2584 2585
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2586
	.port_set_link = mv88e6xxx_port_set_link,
2587
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2588
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2589
	.port_set_speed = mv88e6352_port_set_speed,
2590
	.port_tag_remap = mv88e6095_port_tag_remap,
2591
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2592
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2593
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2594
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2595
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2596
	.port_pause_limit = mv88e6097_port_pause_limit,
2597
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2598
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2599
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2600
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2601 2602
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2603
	.stats_get_stats = mv88e6095_stats_get_stats,
2604 2605
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2606
	.watchdog_ops = &mv88e6097_watchdog_ops,
2607
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2608
	.pot_clear = mv88e6xxx_g2_pot_clear,
2609
	.reset = mv88e6352_g1_reset,
2610
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2611
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2612
	.serdes_power = mv88e6352_serdes_power,
2613 2614 2615
};

static const struct mv88e6xxx_ops mv88e6175_ops = {
2616
	/* MV88E6XXX_FAMILY_6351 */
2617
	.irl_init_all = mv88e6352_g2_irl_init_all,
2618
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2619 2620
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2621
	.port_set_link = mv88e6xxx_port_set_link,
2622
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2623
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2624
	.port_set_speed = mv88e6185_port_set_speed,
2625
	.port_tag_remap = mv88e6095_port_tag_remap,
2626
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2627
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2628
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2629
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2630
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2631
	.port_pause_limit = mv88e6097_port_pause_limit,
2632
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2633
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2634
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2635
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2636 2637
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2638
	.stats_get_stats = mv88e6095_stats_get_stats,
2639 2640
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2641
	.watchdog_ops = &mv88e6097_watchdog_ops,
2642
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2643
	.pot_clear = mv88e6xxx_g2_pot_clear,
2644
	.reset = mv88e6352_g1_reset,
2645
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2646
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2647 2648 2649
};

static const struct mv88e6xxx_ops mv88e6176_ops = {
2650
	/* MV88E6XXX_FAMILY_6352 */
2651
	.irl_init_all = mv88e6352_g2_irl_init_all,
2652 2653
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
2654
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2655 2656
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2657
	.port_set_link = mv88e6xxx_port_set_link,
2658
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2659
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2660
	.port_set_speed = mv88e6352_port_set_speed,
2661
	.port_tag_remap = mv88e6095_port_tag_remap,
2662
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2663
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2664
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2665
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2666
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2667
	.port_pause_limit = mv88e6097_port_pause_limit,
2668
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2669
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2670
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2671
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2672 2673
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2674
	.stats_get_stats = mv88e6095_stats_get_stats,
2675 2676
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2677
	.watchdog_ops = &mv88e6097_watchdog_ops,
2678
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2679
	.pot_clear = mv88e6xxx_g2_pot_clear,
2680
	.reset = mv88e6352_g1_reset,
2681
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2682
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2683
	.serdes_power = mv88e6352_serdes_power,
2684 2685 2686
};

static const struct mv88e6xxx_ops mv88e6185_ops = {
2687
	/* MV88E6XXX_FAMILY_6185 */
2688
	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2689 2690
	.phy_read = mv88e6185_phy_ppu_read,
	.phy_write = mv88e6185_phy_ppu_write,
2691
	.port_set_link = mv88e6xxx_port_set_link,
2692
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2693
	.port_set_speed = mv88e6185_port_set_speed,
2694
	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
2695
	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
2696
	.port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2697
	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
2698
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2699
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2700 2701
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2702
	.stats_get_stats = mv88e6095_stats_get_stats,
2703 2704
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2705
	.watchdog_ops = &mv88e6097_watchdog_ops,
2706
	.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2707 2708
	.ppu_enable = mv88e6185_g1_ppu_enable,
	.ppu_disable = mv88e6185_g1_ppu_disable,
2709
	.reset = mv88e6185_g1_reset,
2710
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
2711
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2712 2713
};

2714
static const struct mv88e6xxx_ops mv88e6190_ops = {
2715
	/* MV88E6XXX_FAMILY_6390 */
2716
	.irl_init_all = mv88e6390_g2_irl_init_all,
2717 2718
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
2719 2720 2721 2722 2723 2724 2725
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
2726
	.port_tag_remap = mv88e6390_port_tag_remap,
2727
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2728
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2729
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2730
	.port_pause_limit = mv88e6390_port_pause_limit,
2731
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2732
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2733
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
2734
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2735 2736
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
2737
	.stats_get_stats = mv88e6390_stats_get_stats,
2738 2739
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
2740
	.watchdog_ops = &mv88e6390_watchdog_ops,
2741
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2742
	.pot_clear = mv88e6xxx_g2_pot_clear,
2743
	.reset = mv88e6352_g1_reset,
2744 2745
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2746
	.serdes_power = mv88e6390_serdes_power,
2747 2748 2749
};

static const struct mv88e6xxx_ops mv88e6190x_ops = {
2750
	/* MV88E6XXX_FAMILY_6390 */
2751
	.irl_init_all = mv88e6390_g2_irl_init_all,
2752 2753
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
2754 2755 2756 2757 2758 2759 2760
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390x_port_set_speed,
2761
	.port_tag_remap = mv88e6390_port_tag_remap,
2762
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2763
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2764
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2765
	.port_pause_limit = mv88e6390_port_pause_limit,
2766
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2767
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2768
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
2769
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2770 2771
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
2772
	.stats_get_stats = mv88e6390_stats_get_stats,
2773 2774
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
2775
	.watchdog_ops = &mv88e6390_watchdog_ops,
2776
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2777
	.pot_clear = mv88e6xxx_g2_pot_clear,
2778
	.reset = mv88e6352_g1_reset,
2779 2780
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2781
	.serdes_power = mv88e6390_serdes_power,
2782 2783 2784
};

static const struct mv88e6xxx_ops mv88e6191_ops = {
2785
	/* MV88E6XXX_FAMILY_6390 */
2786
	.irl_init_all = mv88e6390_g2_irl_init_all,
2787 2788
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
2789 2790 2791 2792 2793 2794 2795
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
2796
	.port_tag_remap = mv88e6390_port_tag_remap,
2797
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2798
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2799
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2800
	.port_pause_limit = mv88e6390_port_pause_limit,
2801
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2802
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2803
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
2804
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2805 2806
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
2807
	.stats_get_stats = mv88e6390_stats_get_stats,
2808 2809
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
2810
	.watchdog_ops = &mv88e6390_watchdog_ops,
2811
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2812
	.pot_clear = mv88e6xxx_g2_pot_clear,
2813
	.reset = mv88e6352_g1_reset,
2814 2815
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2816
	.serdes_power = mv88e6390_serdes_power,
2817 2818
};

2819
static const struct mv88e6xxx_ops mv88e6240_ops = {
2820
	/* MV88E6XXX_FAMILY_6352 */
2821
	.irl_init_all = mv88e6352_g2_irl_init_all,
2822 2823
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
2824
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2825 2826
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2827
	.port_set_link = mv88e6xxx_port_set_link,
2828
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2829
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2830
	.port_set_speed = mv88e6352_port_set_speed,
2831
	.port_tag_remap = mv88e6095_port_tag_remap,
2832
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2833
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2834
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2835
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2836
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2837
	.port_pause_limit = mv88e6097_port_pause_limit,
2838
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2839
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2840
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2841
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2842 2843
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2844
	.stats_get_stats = mv88e6095_stats_get_stats,
2845 2846
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2847
	.watchdog_ops = &mv88e6097_watchdog_ops,
2848
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2849
	.pot_clear = mv88e6xxx_g2_pot_clear,
2850
	.reset = mv88e6352_g1_reset,
2851
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2852
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2853
	.serdes_power = mv88e6352_serdes_power,
2854
	.avb_ops = &mv88e6352_avb_ops,
2855 2856
};

2857
static const struct mv88e6xxx_ops mv88e6290_ops = {
2858
	/* MV88E6XXX_FAMILY_6390 */
2859
	.irl_init_all = mv88e6390_g2_irl_init_all,
2860 2861
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
2862 2863 2864 2865 2866 2867 2868
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
2869
	.port_tag_remap = mv88e6390_port_tag_remap,
2870
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2871
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2872
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2873
	.port_pause_limit = mv88e6390_port_pause_limit,
2874
	.port_set_cmode = mv88e6390x_port_set_cmode,
2875
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2876
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2877
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
2878
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2879 2880
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
2881
	.stats_get_stats = mv88e6390_stats_get_stats,
2882 2883
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
2884
	.watchdog_ops = &mv88e6390_watchdog_ops,
2885
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2886
	.pot_clear = mv88e6xxx_g2_pot_clear,
2887
	.reset = mv88e6352_g1_reset,
2888 2889
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2890
	.serdes_power = mv88e6390_serdes_power,
2891
	.avb_ops = &mv88e6390_avb_ops,
2892 2893
};

2894
static const struct mv88e6xxx_ops mv88e6320_ops = {
2895
	/* MV88E6XXX_FAMILY_6320 */
2896
	.irl_init_all = mv88e6352_g2_irl_init_all,
2897 2898
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
2899
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2900 2901
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2902
	.port_set_link = mv88e6xxx_port_set_link,
2903
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2904
	.port_set_speed = mv88e6185_port_set_speed,
2905
	.port_tag_remap = mv88e6095_port_tag_remap,
2906
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2907
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2908
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2909
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2910
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2911
	.port_pause_limit = mv88e6097_port_pause_limit,
2912
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2913
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2914
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2915
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2916 2917
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
2918
	.stats_get_stats = mv88e6320_stats_get_stats,
2919 2920
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2921
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2922
	.pot_clear = mv88e6xxx_g2_pot_clear,
2923
	.reset = mv88e6352_g1_reset,
2924
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
2925
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2926
	.avb_ops = &mv88e6352_avb_ops,
2927 2928 2929
};

static const struct mv88e6xxx_ops mv88e6321_ops = {
2930
	/* MV88E6XXX_FAMILY_6320 */
2931
	.irl_init_all = mv88e6352_g2_irl_init_all,
2932 2933
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
2934
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2935 2936
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2937
	.port_set_link = mv88e6xxx_port_set_link,
2938
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2939
	.port_set_speed = mv88e6185_port_set_speed,
2940
	.port_tag_remap = mv88e6095_port_tag_remap,
2941
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2942
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2943
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2944
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2945
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2946
	.port_pause_limit = mv88e6097_port_pause_limit,
2947
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2948
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2949
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2950
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2951 2952
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
2953
	.stats_get_stats = mv88e6320_stats_get_stats,
2954 2955
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2956
	.reset = mv88e6352_g1_reset,
2957
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
2958
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2959
	.avb_ops = &mv88e6352_avb_ops,
2960 2961
};

2962 2963
static const struct mv88e6xxx_ops mv88e6341_ops = {
	/* MV88E6XXX_FAMILY_6341 */
2964
	.irl_init_all = mv88e6352_g2_irl_init_all,
2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 2976 2977
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
	.port_tag_remap = mv88e6095_port_tag_remap,
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2978
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2979
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2980
	.port_pause_limit = mv88e6097_port_pause_limit,
2981 2982 2983
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
2984
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2985 2986 2987
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
	.stats_get_stats = mv88e6390_stats_get_stats,
2988 2989
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
2990 2991
	.watchdog_ops = &mv88e6390_watchdog_ops,
	.mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
2992
	.pot_clear = mv88e6xxx_g2_pot_clear,
2993
	.reset = mv88e6352_g1_reset,
2994
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2995
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2996
	.avb_ops = &mv88e6390_avb_ops,
2997 2998
};

2999
static const struct mv88e6xxx_ops mv88e6350_ops = {
3000
	/* MV88E6XXX_FAMILY_6351 */
3001
	.irl_init_all = mv88e6352_g2_irl_init_all,
3002
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3003 3004
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3005
	.port_set_link = mv88e6xxx_port_set_link,
3006
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3007
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3008
	.port_set_speed = mv88e6185_port_set_speed,
3009
	.port_tag_remap = mv88e6095_port_tag_remap,
3010
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3011
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3012
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3013
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3014
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3015
	.port_pause_limit = mv88e6097_port_pause_limit,
3016
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3017
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3018
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3019
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3020 3021
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
3022
	.stats_get_stats = mv88e6095_stats_get_stats,
3023 3024
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3025
	.watchdog_ops = &mv88e6097_watchdog_ops,
3026
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3027
	.pot_clear = mv88e6xxx_g2_pot_clear,
3028
	.reset = mv88e6352_g1_reset,
3029
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3030
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3031 3032 3033
};

static const struct mv88e6xxx_ops mv88e6351_ops = {
3034
	/* MV88E6XXX_FAMILY_6351 */
3035
	.irl_init_all = mv88e6352_g2_irl_init_all,
3036
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3037 3038
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3039
	.port_set_link = mv88e6xxx_port_set_link,
3040
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3041
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3042
	.port_set_speed = mv88e6185_port_set_speed,
3043
	.port_tag_remap = mv88e6095_port_tag_remap,
3044
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3045
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3046
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3047
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3048
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3049
	.port_pause_limit = mv88e6097_port_pause_limit,
3050
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3051
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3052
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3053
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3054 3055
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
3056
	.stats_get_stats = mv88e6095_stats_get_stats,
3057 3058
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3059
	.watchdog_ops = &mv88e6097_watchdog_ops,
3060
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3061
	.pot_clear = mv88e6xxx_g2_pot_clear,
3062
	.reset = mv88e6352_g1_reset,
3063
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3064
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3065
	.avb_ops = &mv88e6352_avb_ops,
3066 3067 3068
};

static const struct mv88e6xxx_ops mv88e6352_ops = {
3069
	/* MV88E6XXX_FAMILY_6352 */
3070
	.irl_init_all = mv88e6352_g2_irl_init_all,
3071 3072
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
3073
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3074 3075
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3076
	.port_set_link = mv88e6xxx_port_set_link,
3077
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3078
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3079
	.port_set_speed = mv88e6352_port_set_speed,
3080
	.port_tag_remap = mv88e6095_port_tag_remap,
3081
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3082
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3083
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3084
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3085
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3086
	.port_pause_limit = mv88e6097_port_pause_limit,
3087
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3088
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3089
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3090
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3091 3092
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
3093
	.stats_get_stats = mv88e6095_stats_get_stats,
3094 3095
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3096
	.watchdog_ops = &mv88e6097_watchdog_ops,
3097
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3098
	.pot_clear = mv88e6xxx_g2_pot_clear,
3099
	.reset = mv88e6352_g1_reset,
3100
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3101
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3102
	.serdes_power = mv88e6352_serdes_power,
3103
	.avb_ops = &mv88e6352_avb_ops,
3104 3105
};

3106
static const struct mv88e6xxx_ops mv88e6390_ops = {
3107
	/* MV88E6XXX_FAMILY_6390 */
3108
	.irl_init_all = mv88e6390_g2_irl_init_all,
3109 3110
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3111 3112 3113 3114 3115 3116 3117
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
3118
	.port_tag_remap = mv88e6390_port_tag_remap,
3119
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3120
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3121
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3122
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3123
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3124
	.port_pause_limit = mv88e6390_port_pause_limit,
3125
	.port_set_cmode = mv88e6390x_port_set_cmode,
3126
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3127
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3128
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3129
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3130 3131
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3132
	.stats_get_stats = mv88e6390_stats_get_stats,
3133 3134
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3135
	.watchdog_ops = &mv88e6390_watchdog_ops,
3136
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3137
	.pot_clear = mv88e6xxx_g2_pot_clear,
3138
	.reset = mv88e6352_g1_reset,
3139 3140
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3141
	.serdes_power = mv88e6390_serdes_power,
3142
	.avb_ops = &mv88e6390_avb_ops,
3143 3144 3145
};

static const struct mv88e6xxx_ops mv88e6390x_ops = {
3146
	/* MV88E6XXX_FAMILY_6390 */
3147
	.irl_init_all = mv88e6390_g2_irl_init_all,
3148 3149
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3150 3151 3152 3153 3154 3155 3156
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390x_port_set_speed,
3157
	.port_tag_remap = mv88e6390_port_tag_remap,
3158
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3159
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3160
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3161
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3162
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3163
	.port_pause_limit = mv88e6390_port_pause_limit,
3164
	.port_set_cmode = mv88e6390x_port_set_cmode,
3165
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3166
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3167
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3168
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3169 3170
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3171
	.stats_get_stats = mv88e6390_stats_get_stats,
3172 3173
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3174
	.watchdog_ops = &mv88e6390_watchdog_ops,
3175
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3176
	.pot_clear = mv88e6xxx_g2_pot_clear,
3177
	.reset = mv88e6352_g1_reset,
3178 3179
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3180
	.serdes_power = mv88e6390_serdes_power,
3181
	.avb_ops = &mv88e6390_avb_ops,
3182 3183
};

3184 3185
static const struct mv88e6xxx_info mv88e6xxx_table[] = {
	[MV88E6085] = {
3186
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
3187 3188 3189 3190
		.family = MV88E6XXX_FAMILY_6097,
		.name = "Marvell 88E6085",
		.num_databases = 4096,
		.num_ports = 10,
3191
		.max_vid = 4095,
3192
		.port_base_addr = 0x10,
3193
		.global1_addr = 0x1b,
3194
		.global2_addr = 0x1c,
3195
		.age_time_coeff = 15000,
3196
		.g1_irqs = 8,
3197
		.g2_irqs = 10,
3198
		.atu_move_port_mask = 0xf,
3199
		.pvt = true,
3200
		.multi_chip = true,
3201
		.tag_protocol = DSA_TAG_PROTO_DSA,
3202
		.ops = &mv88e6085_ops,
3203 3204 3205
	},

	[MV88E6095] = {
3206
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
3207 3208 3209 3210
		.family = MV88E6XXX_FAMILY_6095,
		.name = "Marvell 88E6095/88E6095F",
		.num_databases = 256,
		.num_ports = 11,
3211
		.max_vid = 4095,
3212
		.port_base_addr = 0x10,
3213
		.global1_addr = 0x1b,
3214
		.global2_addr = 0x1c,
3215
		.age_time_coeff = 15000,
3216
		.g1_irqs = 8,
3217
		.atu_move_port_mask = 0xf,
3218
		.multi_chip = true,
3219
		.tag_protocol = DSA_TAG_PROTO_DSA,
3220
		.ops = &mv88e6095_ops,
3221 3222
	},

3223
	[MV88E6097] = {
3224
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
3225 3226 3227 3228
		.family = MV88E6XXX_FAMILY_6097,
		.name = "Marvell 88E6097/88E6097F",
		.num_databases = 4096,
		.num_ports = 11,
3229
		.max_vid = 4095,
3230 3231
		.port_base_addr = 0x10,
		.global1_addr = 0x1b,
3232
		.global2_addr = 0x1c,
3233
		.age_time_coeff = 15000,
3234
		.g1_irqs = 8,
3235
		.g2_irqs = 10,
3236
		.atu_move_port_mask = 0xf,
3237
		.pvt = true,
3238
		.multi_chip = true,
3239
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3240 3241 3242
		.ops = &mv88e6097_ops,
	},

3243
	[MV88E6123] = {
3244
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
3245 3246 3247 3248
		.family = MV88E6XXX_FAMILY_6165,
		.name = "Marvell 88E6123",
		.num_databases = 4096,
		.num_ports = 3,
3249
		.max_vid = 4095,
3250
		.port_base_addr = 0x10,
3251
		.global1_addr = 0x1b,
3252
		.global2_addr = 0x1c,
3253
		.age_time_coeff = 15000,
3254
		.g1_irqs = 9,
3255
		.g2_irqs = 10,
3256
		.atu_move_port_mask = 0xf,
3257
		.pvt = true,
3258
		.multi_chip = true,
3259
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3260
		.ops = &mv88e6123_ops,
3261 3262 3263
	},

	[MV88E6131] = {
3264
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
3265 3266 3267 3268
		.family = MV88E6XXX_FAMILY_6185,
		.name = "Marvell 88E6131",
		.num_databases = 256,
		.num_ports = 8,
3269
		.max_vid = 4095,
3270
		.port_base_addr = 0x10,
3271
		.global1_addr = 0x1b,
3272
		.global2_addr = 0x1c,
3273
		.age_time_coeff = 15000,
3274
		.g1_irqs = 9,
3275
		.atu_move_port_mask = 0xf,
3276
		.multi_chip = true,
3277
		.tag_protocol = DSA_TAG_PROTO_DSA,
3278
		.ops = &mv88e6131_ops,
3279 3280
	},

3281
	[MV88E6141] = {
3282
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
3283 3284 3285 3286
		.family = MV88E6XXX_FAMILY_6341,
		.name = "Marvell 88E6341",
		.num_databases = 4096,
		.num_ports = 6,
3287
		.max_vid = 4095,
3288 3289
		.port_base_addr = 0x10,
		.global1_addr = 0x1b,
3290
		.global2_addr = 0x1c,
3291 3292
		.age_time_coeff = 3750,
		.atu_move_port_mask = 0x1f,
3293
		.g2_irqs = 10,
3294
		.pvt = true,
3295
		.multi_chip = true,
3296 3297 3298 3299
		.tag_protocol = DSA_TAG_PROTO_EDSA,
		.ops = &mv88e6141_ops,
	},

3300
	[MV88E6161] = {
3301
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
3302 3303 3304 3305
		.family = MV88E6XXX_FAMILY_6165,
		.name = "Marvell 88E6161",
		.num_databases = 4096,
		.num_ports = 6,
3306
		.max_vid = 4095,
3307
		.port_base_addr = 0x10,
3308
		.global1_addr = 0x1b,
3309
		.global2_addr = 0x1c,
3310
		.age_time_coeff = 15000,
3311
		.g1_irqs = 9,
3312
		.g2_irqs = 10,
3313
		.atu_move_port_mask = 0xf,
3314
		.pvt = true,
3315
		.multi_chip = true,
3316
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3317
		.ops = &mv88e6161_ops,
3318 3319 3320
	},

	[MV88E6165] = {
3321
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
3322 3323 3324 3325
		.family = MV88E6XXX_FAMILY_6165,
		.name = "Marvell 88E6165",
		.num_databases = 4096,
		.num_ports = 6,
3326
		.max_vid = 4095,
3327
		.port_base_addr = 0x10,
3328
		.global1_addr = 0x1b,
3329
		.global2_addr = 0x1c,
3330
		.age_time_coeff = 15000,
3331
		.g1_irqs = 9,
3332
		.g2_irqs = 10,
3333
		.atu_move_port_mask = 0xf,
3334
		.pvt = true,
3335
		.multi_chip = true,
3336
		.tag_protocol = DSA_TAG_PROTO_DSA,
3337
		.ops = &mv88e6165_ops,
3338 3339 3340
	},

	[MV88E6171] = {
3341
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
3342 3343 3344 3345
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6171",
		.num_databases = 4096,
		.num_ports = 7,
3346
		.max_vid = 4095,
3347
		.port_base_addr = 0x10,
3348
		.global1_addr = 0x1b,
3349
		.global2_addr = 0x1c,
3350
		.age_time_coeff = 15000,
3351
		.g1_irqs = 9,
3352
		.g2_irqs = 10,
3353
		.atu_move_port_mask = 0xf,
3354
		.pvt = true,
3355
		.multi_chip = true,
3356
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3357
		.ops = &mv88e6171_ops,
3358 3359 3360
	},

	[MV88E6172] = {
3361
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
3362 3363 3364 3365
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6172",
		.num_databases = 4096,
		.num_ports = 7,
3366
		.max_vid = 4095,
3367
		.port_base_addr = 0x10,
3368
		.global1_addr = 0x1b,
3369
		.global2_addr = 0x1c,
3370
		.age_time_coeff = 15000,
3371
		.g1_irqs = 9,
3372
		.g2_irqs = 10,
3373
		.atu_move_port_mask = 0xf,
3374
		.pvt = true,
3375
		.multi_chip = true,
3376
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3377
		.ops = &mv88e6172_ops,
3378 3379 3380
	},

	[MV88E6175] = {
3381
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
3382 3383 3384 3385
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6175",
		.num_databases = 4096,
		.num_ports = 7,
3386
		.max_vid = 4095,
3387
		.port_base_addr = 0x10,
3388
		.global1_addr = 0x1b,
3389
		.global2_addr = 0x1c,
3390
		.age_time_coeff = 15000,
3391
		.g1_irqs = 9,
3392
		.g2_irqs = 10,
3393
		.atu_move_port_mask = 0xf,
3394
		.pvt = true,
3395
		.multi_chip = true,
3396
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3397
		.ops = &mv88e6175_ops,
3398 3399 3400
	},

	[MV88E6176] = {
3401
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
3402 3403 3404 3405
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6176",
		.num_databases = 4096,
		.num_ports = 7,
3406
		.max_vid = 4095,
3407
		.port_base_addr = 0x10,
3408
		.global1_addr = 0x1b,
3409
		.global2_addr = 0x1c,
3410
		.age_time_coeff = 15000,
3411
		.g1_irqs = 9,
3412
		.g2_irqs = 10,
3413
		.atu_move_port_mask = 0xf,
3414
		.pvt = true,
3415
		.multi_chip = true,
3416
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3417
		.ops = &mv88e6176_ops,
3418 3419 3420
	},

	[MV88E6185] = {
3421
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
3422 3423 3424 3425
		.family = MV88E6XXX_FAMILY_6185,
		.name = "Marvell 88E6185",
		.num_databases = 256,
		.num_ports = 10,
3426
		.max_vid = 4095,
3427
		.port_base_addr = 0x10,
3428
		.global1_addr = 0x1b,
3429
		.global2_addr = 0x1c,
3430
		.age_time_coeff = 15000,
3431
		.g1_irqs = 8,
3432
		.atu_move_port_mask = 0xf,
3433
		.multi_chip = true,
3434
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3435
		.ops = &mv88e6185_ops,
3436 3437
	},

3438
	[MV88E6190] = {
3439
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
3440 3441 3442 3443
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6190",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3444
		.max_vid = 8191,
3445 3446
		.port_base_addr = 0x0,
		.global1_addr = 0x1b,
3447
		.global2_addr = 0x1c,
3448
		.tag_protocol = DSA_TAG_PROTO_DSA,
3449
		.age_time_coeff = 3750,
3450
		.g1_irqs = 9,
3451
		.g2_irqs = 14,
3452
		.pvt = true,
3453
		.multi_chip = true,
3454
		.atu_move_port_mask = 0x1f,
3455 3456 3457 3458
		.ops = &mv88e6190_ops,
	},

	[MV88E6190X] = {
3459
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
3460 3461 3462 3463
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6190X",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3464
		.max_vid = 8191,
3465 3466
		.port_base_addr = 0x0,
		.global1_addr = 0x1b,
3467
		.global2_addr = 0x1c,
3468
		.age_time_coeff = 3750,
3469
		.g1_irqs = 9,
3470
		.g2_irqs = 14,
3471
		.atu_move_port_mask = 0x1f,
3472
		.pvt = true,
3473
		.multi_chip = true,
3474
		.tag_protocol = DSA_TAG_PROTO_DSA,
3475 3476 3477 3478
		.ops = &mv88e6190x_ops,
	},

	[MV88E6191] = {
3479
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
3480 3481 3482 3483
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6191",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3484
		.max_vid = 8191,
3485 3486
		.port_base_addr = 0x0,
		.global1_addr = 0x1b,
3487
		.global2_addr = 0x1c,
3488
		.age_time_coeff = 3750,
3489
		.g1_irqs = 9,
3490
		.g2_irqs = 14,
3491
		.atu_move_port_mask = 0x1f,
3492
		.pvt = true,
3493
		.multi_chip = true,
3494
		.tag_protocol = DSA_TAG_PROTO_DSA,
3495
		.ptp_support = true,
3496
		.ops = &mv88e6191_ops,
3497 3498
	},

3499
	[MV88E6240] = {
3500
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
3501 3502 3503 3504
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6240",
		.num_databases = 4096,
		.num_ports = 7,
3505
		.max_vid = 4095,
3506
		.port_base_addr = 0x10,
3507
		.global1_addr = 0x1b,
3508
		.global2_addr = 0x1c,
3509
		.age_time_coeff = 15000,
3510
		.g1_irqs = 9,
3511
		.g2_irqs = 10,
3512
		.atu_move_port_mask = 0xf,
3513
		.pvt = true,
3514
		.multi_chip = true,
3515
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3516
		.ptp_support = true,
3517
		.ops = &mv88e6240_ops,
3518 3519
	},

3520
	[MV88E6290] = {
3521
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
3522 3523 3524 3525
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6290",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3526
		.max_vid = 8191,
3527 3528
		.port_base_addr = 0x0,
		.global1_addr = 0x1b,
3529
		.global2_addr = 0x1c,
3530
		.age_time_coeff = 3750,
3531
		.g1_irqs = 9,
3532
		.g2_irqs = 14,
3533
		.atu_move_port_mask = 0x1f,
3534
		.pvt = true,
3535
		.multi_chip = true,
3536
		.tag_protocol = DSA_TAG_PROTO_DSA,
3537
		.ptp_support = true,
3538 3539 3540
		.ops = &mv88e6290_ops,
	},

3541
	[MV88E6320] = {
3542
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
3543 3544 3545 3546
		.family = MV88E6XXX_FAMILY_6320,
		.name = "Marvell 88E6320",
		.num_databases = 4096,
		.num_ports = 7,
3547
		.max_vid = 4095,
3548
		.port_base_addr = 0x10,
3549
		.global1_addr = 0x1b,
3550
		.global2_addr = 0x1c,
3551
		.age_time_coeff = 15000,
3552
		.g1_irqs = 8,
3553
		.atu_move_port_mask = 0xf,
3554
		.pvt = true,
3555
		.multi_chip = true,
3556
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3557
		.ptp_support = true,
3558
		.ops = &mv88e6320_ops,
3559 3560 3561
	},

	[MV88E6321] = {
3562
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
3563 3564 3565 3566
		.family = MV88E6XXX_FAMILY_6320,
		.name = "Marvell 88E6321",
		.num_databases = 4096,
		.num_ports = 7,
3567
		.max_vid = 4095,
3568
		.port_base_addr = 0x10,
3569
		.global1_addr = 0x1b,
3570
		.global2_addr = 0x1c,
3571
		.age_time_coeff = 15000,
3572
		.g1_irqs = 8,
3573
		.atu_move_port_mask = 0xf,
3574
		.multi_chip = true,
3575
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3576
		.ptp_support = true,
3577
		.ops = &mv88e6321_ops,
3578 3579
	},

3580
	[MV88E6341] = {
3581
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3582 3583 3584 3585
		.family = MV88E6XXX_FAMILY_6341,
		.name = "Marvell 88E6341",
		.num_databases = 4096,
		.num_ports = 6,
3586
		.max_vid = 4095,
3587 3588
		.port_base_addr = 0x10,
		.global1_addr = 0x1b,
3589
		.global2_addr = 0x1c,
3590
		.age_time_coeff = 3750,
3591
		.atu_move_port_mask = 0x1f,
3592
		.g2_irqs = 10,
3593
		.pvt = true,
3594
		.multi_chip = true,
3595
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3596
		.ptp_support = true,
3597 3598 3599
		.ops = &mv88e6341_ops,
	},

3600
	[MV88E6350] = {
3601
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
3602 3603 3604 3605
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6350",
		.num_databases = 4096,
		.num_ports = 7,
3606
		.max_vid = 4095,
3607
		.port_base_addr = 0x10,
3608
		.global1_addr = 0x1b,
3609
		.global2_addr = 0x1c,
3610
		.age_time_coeff = 15000,
3611
		.g1_irqs = 9,
3612
		.g2_irqs = 10,
3613
		.atu_move_port_mask = 0xf,
3614
		.pvt = true,
3615
		.multi_chip = true,
3616
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3617
		.ops = &mv88e6350_ops,
3618 3619 3620
	},

	[MV88E6351] = {
3621
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
3622 3623 3624 3625
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6351",
		.num_databases = 4096,
		.num_ports = 7,
3626
		.max_vid = 4095,
3627
		.port_base_addr = 0x10,
3628
		.global1_addr = 0x1b,
3629
		.global2_addr = 0x1c,
3630
		.age_time_coeff = 15000,
3631
		.g1_irqs = 9,
3632
		.g2_irqs = 10,
3633
		.atu_move_port_mask = 0xf,
3634
		.pvt = true,
3635
		.multi_chip = true,
3636
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3637
		.ops = &mv88e6351_ops,
3638 3639 3640
	},

	[MV88E6352] = {
3641
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
3642 3643 3644 3645
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6352",
		.num_databases = 4096,
		.num_ports = 7,
3646
		.max_vid = 4095,
3647
		.port_base_addr = 0x10,
3648
		.global1_addr = 0x1b,
3649
		.global2_addr = 0x1c,
3650
		.age_time_coeff = 15000,
3651
		.g1_irqs = 9,
3652
		.g2_irqs = 10,
3653
		.atu_move_port_mask = 0xf,
3654
		.pvt = true,
3655
		.multi_chip = true,
3656
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3657
		.ptp_support = true,
3658
		.ops = &mv88e6352_ops,
3659
	},
3660
	[MV88E6390] = {
3661
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
3662 3663 3664 3665
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6390",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3666
		.max_vid = 8191,
3667 3668
		.port_base_addr = 0x0,
		.global1_addr = 0x1b,
3669
		.global2_addr = 0x1c,
3670
		.age_time_coeff = 3750,
3671
		.g1_irqs = 9,
3672
		.g2_irqs = 14,
3673
		.atu_move_port_mask = 0x1f,
3674
		.pvt = true,
3675
		.multi_chip = true,
3676
		.tag_protocol = DSA_TAG_PROTO_DSA,
3677
		.ptp_support = true,
3678 3679 3680
		.ops = &mv88e6390_ops,
	},
	[MV88E6390X] = {
3681
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
3682 3683 3684 3685
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6390X",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3686
		.max_vid = 8191,
3687 3688
		.port_base_addr = 0x0,
		.global1_addr = 0x1b,
3689
		.global2_addr = 0x1c,
3690
		.age_time_coeff = 3750,
3691
		.g1_irqs = 9,
3692
		.g2_irqs = 14,
3693
		.atu_move_port_mask = 0x1f,
3694
		.pvt = true,
3695
		.multi_chip = true,
3696
		.tag_protocol = DSA_TAG_PROTO_DSA,
3697
		.ptp_support = true,
3698 3699
		.ops = &mv88e6390x_ops,
	},
3700 3701
};

3702
static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
3703
{
3704
	int i;
3705

3706 3707 3708
	for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
		if (mv88e6xxx_table[i].prod_num == prod_num)
			return &mv88e6xxx_table[i];
3709 3710 3711 3712

	return NULL;
}

3713
static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
3714 3715
{
	const struct mv88e6xxx_info *info;
3716 3717 3718
	unsigned int prod_num, rev;
	u16 id;
	int err;
3719

3720
	mutex_lock(&chip->reg_lock);
3721
	err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
3722 3723 3724
	mutex_unlock(&chip->reg_lock);
	if (err)
		return err;
3725

3726 3727
	prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
	rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
3728 3729 3730 3731 3732

	info = mv88e6xxx_lookup_info(prod_num);
	if (!info)
		return -ENODEV;

3733
	/* Update the compatible info with the probed one */
3734
	chip->info = info;
3735

3736 3737 3738 3739
	err = mv88e6xxx_g2_require(chip);
	if (err)
		return err;

3740 3741
	dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
		 chip->info->prod_num, chip->info->name, rev);
3742 3743 3744 3745

	return 0;
}

3746
static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
3747
{
3748
	struct mv88e6xxx_chip *chip;
3749

3750 3751
	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
	if (!chip)
3752 3753
		return NULL;

3754
	chip->dev = dev;
3755

3756
	mutex_init(&chip->reg_lock);
3757
	INIT_LIST_HEAD(&chip->mdios);
3758

3759
	return chip;
3760 3761
}

3762
static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
3763 3764
			      struct mii_bus *bus, int sw_addr)
{
3765
	if (sw_addr == 0)
3766
		chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
3767
	else if (chip->info->multi_chip)
3768
		chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
3769 3770 3771
	else
		return -EINVAL;

3772 3773
	chip->bus = bus;
	chip->sw_addr = sw_addr;
3774 3775 3776 3777

	return 0;
}

3778 3779
static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
							int port)
3780
{
V
Vivien Didelot 已提交
3781
	struct mv88e6xxx_chip *chip = ds->priv;
3782

3783
	return chip->info->tag_protocol;
3784 3785
}

3786
#if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
3787 3788 3789
static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
				       struct device *host_dev, int sw_addr,
				       void **priv)
3790
{
3791
	struct mv88e6xxx_chip *chip;
3792
	struct mii_bus *bus;
3793
	int err;
3794

3795
	bus = dsa_host_dev_to_mii_bus(host_dev);
3796 3797 3798
	if (!bus)
		return NULL;

3799 3800
	chip = mv88e6xxx_alloc_chip(dsa_dev);
	if (!chip)
3801 3802
		return NULL;

3803
	/* Legacy SMI probing will only support chips similar to 88E6085 */
3804
	chip->info = &mv88e6xxx_table[MV88E6085];
3805

3806
	err = mv88e6xxx_smi_init(chip, bus, sw_addr);
3807 3808 3809
	if (err)
		goto free;

3810
	err = mv88e6xxx_detect(chip);
3811
	if (err)
3812
		goto free;
3813

3814 3815 3816 3817 3818 3819
	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_switch_reset(chip);
	mutex_unlock(&chip->reg_lock);
	if (err)
		goto free;

3820 3821
	mv88e6xxx_phy_init(chip);

3822
	err = mv88e6xxx_mdios_register(chip, NULL);
3823
	if (err)
3824
		goto free;
3825

3826
	*priv = chip;
3827

3828
	return chip->info->name;
3829
free:
3830
	devm_kfree(dsa_dev, chip);
3831 3832

	return NULL;
3833
}
3834
#endif
3835

3836
static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
3837
				      const struct switchdev_obj_port_mdb *mdb)
3838 3839 3840 3841 3842 3843 3844 3845 3846
{
	/* We don't need any dynamic resource from the kernel (yet),
	 * so skip the prepare phase.
	 */

	return 0;
}

static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
3847
				   const struct switchdev_obj_port_mdb *mdb)
3848
{
V
Vivien Didelot 已提交
3849
	struct mv88e6xxx_chip *chip = ds->priv;
3850 3851 3852

	mutex_lock(&chip->reg_lock);
	if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3853
					 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
3854 3855
		dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
			port);
3856 3857 3858 3859 3860 3861
	mutex_unlock(&chip->reg_lock);
}

static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
				  const struct switchdev_obj_port_mdb *mdb)
{
V
Vivien Didelot 已提交
3862
	struct mv88e6xxx_chip *chip = ds->priv;
3863 3864 3865 3866
	int err;

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3867
					   MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
3868 3869 3870 3871 3872
	mutex_unlock(&chip->reg_lock);

	return err;
}

3873
static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
3874
#if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
3875
	.probe			= mv88e6xxx_drv_probe,
3876
#endif
3877
	.get_tag_protocol	= mv88e6xxx_get_tag_protocol,
3878 3879 3880 3881 3882
	.setup			= mv88e6xxx_setup,
	.adjust_link		= mv88e6xxx_adjust_link,
	.get_strings		= mv88e6xxx_get_strings,
	.get_ethtool_stats	= mv88e6xxx_get_ethtool_stats,
	.get_sset_count		= mv88e6xxx_get_sset_count,
3883 3884
	.port_enable		= mv88e6xxx_port_enable,
	.port_disable		= mv88e6xxx_port_disable,
V
Vivien Didelot 已提交
3885 3886
	.get_mac_eee		= mv88e6xxx_get_mac_eee,
	.set_mac_eee		= mv88e6xxx_set_mac_eee,
3887
	.get_eeprom_len		= mv88e6xxx_get_eeprom_len,
3888 3889 3890 3891
	.get_eeprom		= mv88e6xxx_get_eeprom,
	.set_eeprom		= mv88e6xxx_set_eeprom,
	.get_regs_len		= mv88e6xxx_get_regs_len,
	.get_regs		= mv88e6xxx_get_regs,
3892
	.set_ageing_time	= mv88e6xxx_set_ageing_time,
3893 3894 3895
	.port_bridge_join	= mv88e6xxx_port_bridge_join,
	.port_bridge_leave	= mv88e6xxx_port_bridge_leave,
	.port_stp_state_set	= mv88e6xxx_port_stp_state_set,
3896
	.port_fast_age		= mv88e6xxx_port_fast_age,
3897 3898 3899 3900 3901 3902 3903
	.port_vlan_filtering	= mv88e6xxx_port_vlan_filtering,
	.port_vlan_prepare	= mv88e6xxx_port_vlan_prepare,
	.port_vlan_add		= mv88e6xxx_port_vlan_add,
	.port_vlan_del		= mv88e6xxx_port_vlan_del,
	.port_fdb_add           = mv88e6xxx_port_fdb_add,
	.port_fdb_del           = mv88e6xxx_port_fdb_del,
	.port_fdb_dump          = mv88e6xxx_port_fdb_dump,
3904 3905 3906
	.port_mdb_prepare       = mv88e6xxx_port_mdb_prepare,
	.port_mdb_add           = mv88e6xxx_port_mdb_add,
	.port_mdb_del           = mv88e6xxx_port_mdb_del,
3907 3908
	.crosschip_bridge_join	= mv88e6xxx_crosschip_bridge_join,
	.crosschip_bridge_leave	= mv88e6xxx_crosschip_bridge_leave,
3909 3910
};

3911 3912 3913 3914
static struct dsa_switch_driver mv88e6xxx_switch_drv = {
	.ops			= &mv88e6xxx_switch_ops,
};

3915
static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
3916
{
3917
	struct device *dev = chip->dev;
3918 3919
	struct dsa_switch *ds;

3920
	ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip));
3921 3922 3923
	if (!ds)
		return -ENOMEM;

3924
	ds->priv = chip;
3925
	ds->ops = &mv88e6xxx_switch_ops;
3926 3927
	ds->ageing_time_min = chip->info->age_time_coeff;
	ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
3928 3929 3930

	dev_set_drvdata(dev, ds);

3931
	return dsa_register_switch(ds);
3932 3933
}

3934
static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
3935
{
3936
	dsa_unregister_switch(chip->ds);
3937 3938
}

3939
static int mv88e6xxx_probe(struct mdio_device *mdiodev)
3940
{
3941
	struct device *dev = &mdiodev->dev;
3942
	struct device_node *np = dev->of_node;
3943
	const struct mv88e6xxx_info *compat_info;
3944
	struct mv88e6xxx_chip *chip;
3945
	u32 eeprom_len;
3946
	int err;
3947

3948 3949 3950 3951
	compat_info = of_device_get_match_data(dev);
	if (!compat_info)
		return -EINVAL;

3952 3953
	chip = mv88e6xxx_alloc_chip(dev);
	if (!chip)
3954 3955
		return -ENOMEM;

3956
	chip->info = compat_info;
3957

3958
	err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
3959 3960
	if (err)
		return err;
3961

3962 3963 3964 3965
	chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
	if (IS_ERR(chip->reset))
		return PTR_ERR(chip->reset);

3966
	err = mv88e6xxx_detect(chip);
3967 3968
	if (err)
		return err;
3969

3970 3971
	mv88e6xxx_phy_init(chip);

3972
	if (chip->info->ops->get_eeprom &&
3973
	    !of_property_read_u32(np, "eeprom-length", &eeprom_len))
3974
		chip->eeprom_len = eeprom_len;
3975

3976 3977 3978 3979 3980 3981 3982 3983 3984 3985 3986 3987 3988 3989 3990 3991 3992 3993 3994 3995 3996 3997 3998 3999
	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_switch_reset(chip);
	mutex_unlock(&chip->reg_lock);
	if (err)
		goto out;

	chip->irq = of_irq_get(np, 0);
	if (chip->irq == -EPROBE_DEFER) {
		err = chip->irq;
		goto out;
	}

	if (chip->irq > 0) {
		/* Has to be performed before the MDIO bus is created,
		 * because the PHYs will link there interrupts to these
		 * interrupt controllers
		 */
		mutex_lock(&chip->reg_lock);
		err = mv88e6xxx_g1_irq_setup(chip);
		mutex_unlock(&chip->reg_lock);

		if (err)
			goto out;

4000
		if (chip->info->g2_irqs > 0) {
4001 4002 4003 4004
			err = mv88e6xxx_g2_irq_setup(chip);
			if (err)
				goto out_g1_irq;
		}
4005 4006 4007 4008

		err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
		if (err)
			goto out_g2_irq;
4009 4010 4011 4012

		err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
		if (err)
			goto out_g1_atu_prob_irq;
4013 4014
	}

4015
	err = mv88e6xxx_mdios_register(chip, np);
4016
	if (err)
4017
		goto out_g1_vtu_prob_irq;
4018

4019
	err = mv88e6xxx_register_switch(chip);
4020 4021
	if (err)
		goto out_mdio;
4022

4023
	return 0;
4024 4025

out_mdio:
4026
	mv88e6xxx_mdios_unregister(chip);
4027
out_g1_vtu_prob_irq:
4028 4029
	if (chip->irq > 0)
		mv88e6xxx_g1_vtu_prob_irq_free(chip);
4030
out_g1_atu_prob_irq:
4031 4032
	if (chip->irq > 0)
		mv88e6xxx_g1_atu_prob_irq_free(chip);
4033
out_g2_irq:
4034
	if (chip->info->g2_irqs > 0 && chip->irq > 0)
4035 4036
		mv88e6xxx_g2_irq_free(chip);
out_g1_irq:
4037 4038
	if (chip->irq > 0) {
		mutex_lock(&chip->reg_lock);
4039
		mv88e6xxx_g1_irq_free(chip);
4040 4041
		mutex_unlock(&chip->reg_lock);
	}
4042 4043
out:
	return err;
4044
}
4045 4046 4047 4048

static void mv88e6xxx_remove(struct mdio_device *mdiodev)
{
	struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
V
Vivien Didelot 已提交
4049
	struct mv88e6xxx_chip *chip = ds->priv;
4050

4051 4052 4053
	if (chip->info->ptp_support)
		mv88e6xxx_ptp_free(chip);

4054
	mv88e6xxx_phy_destroy(chip);
4055
	mv88e6xxx_unregister_switch(chip);
4056
	mv88e6xxx_mdios_unregister(chip);
4057

4058
	if (chip->irq > 0) {
4059
		mv88e6xxx_g1_vtu_prob_irq_free(chip);
4060
		mv88e6xxx_g1_atu_prob_irq_free(chip);
4061
		if (chip->info->g2_irqs > 0)
4062
			mv88e6xxx_g2_irq_free(chip);
4063
		mutex_lock(&chip->reg_lock);
4064
		mv88e6xxx_g1_irq_free(chip);
4065
		mutex_unlock(&chip->reg_lock);
4066
	}
4067 4068 4069
}

static const struct of_device_id mv88e6xxx_of_match[] = {
4070 4071 4072 4073
	{
		.compatible = "marvell,mv88e6085",
		.data = &mv88e6xxx_table[MV88E6085],
	},
4074 4075 4076 4077
	{
		.compatible = "marvell,mv88e6190",
		.data = &mv88e6xxx_table[MV88E6190],
	},
4078 4079 4080 4081 4082 4083 4084 4085 4086 4087 4088 4089 4090 4091 4092 4093
	{ /* sentinel */ },
};

MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);

static struct mdio_driver mv88e6xxx_driver = {
	.probe	= mv88e6xxx_probe,
	.remove = mv88e6xxx_remove,
	.mdiodrv.driver = {
		.name = "mv88e6085",
		.of_match_table = mv88e6xxx_of_match,
	},
};

static int __init mv88e6xxx_init(void)
{
4094
	register_switch_driver(&mv88e6xxx_switch_drv);
4095 4096
	return mdio_driver_register(&mv88e6xxx_driver);
}
4097 4098 4099 4100
module_init(mv88e6xxx_init);

static void __exit mv88e6xxx_cleanup(void)
{
4101
	mdio_driver_unregister(&mv88e6xxx_driver);
4102
	unregister_switch_driver(&mv88e6xxx_switch_drv);
4103 4104
}
module_exit(mv88e6xxx_cleanup);
4105 4106 4107 4108

MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
MODULE_LICENSE("GPL");