chip.c 127.1 KB
Newer Older
1
/*
2 3
 * Marvell 88e6xxx Ethernet switch single-chip support
 *
4 5
 * Copyright (c) 2008 Marvell Semiconductor
 *
6 7
 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
 *
V
Vivien Didelot 已提交
8 9 10
 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
 *	Vivien Didelot <vivien.didelot@savoirfairelinux.com>
 *
11 12 13 14 15 16
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

17
#include <linux/delay.h>
18
#include <linux/etherdevice.h>
19
#include <linux/ethtool.h>
20
#include <linux/if_bridge.h>
21 22 23
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
24
#include <linux/jiffies.h>
25
#include <linux/list.h>
26
#include <linux/mdio.h>
27
#include <linux/module.h>
28
#include <linux/of_device.h>
29
#include <linux/of_irq.h>
30
#include <linux/of_mdio.h>
31
#include <linux/platform_data/mv88e6xxx.h>
32
#include <linux/netdevice.h>
33
#include <linux/gpio/consumer.h>
34
#include <linux/phy.h>
35
#include <linux/phylink.h>
36
#include <net/dsa.h>
37

38
#include "chip.h"
39
#include "global1.h"
40
#include "global2.h"
41
#include "hwtstamp.h"
42
#include "phy.h"
43
#include "port.h"
44
#include "ptp.h"
45
#include "serdes.h"
46

47
static void assert_reg_lock(struct mv88e6xxx_chip *chip)
48
{
49 50
	if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
		dev_err(chip->dev, "Switch registers lock not held!\n");
51 52 53 54
		dump_stack();
	}
}

55 56 57 58 59 60 61 62 63 64
/* The switch ADDR[4:1] configuration pins define the chip SMI device address
 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
 *
 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
 * is the only device connected to the SMI master. In this mode it responds to
 * all 32 possible SMI addresses, and thus maps directly the internal devices.
 *
 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
 * multiple devices to share the SMI interface. In this mode it responds to only
 * 2 registers, used to indirectly access the internal SMI devices.
65
 */
66

67
static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
68 69
			      int addr, int reg, u16 *val)
{
70
	if (!chip->smi_ops)
71 72
		return -EOPNOTSUPP;

73
	return chip->smi_ops->read(chip, addr, reg, val);
74 75
}

76
static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
77 78
			       int addr, int reg, u16 val)
{
79
	if (!chip->smi_ops)
80 81
		return -EOPNOTSUPP;

82
	return chip->smi_ops->write(chip, addr, reg, val);
83 84
}

85
static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
86 87 88 89
					  int addr, int reg, u16 *val)
{
	int ret;

90
	ret = mdiobus_read_nested(chip->bus, addr, reg);
91 92 93 94 95 96 97 98
	if (ret < 0)
		return ret;

	*val = ret & 0xffff;

	return 0;
}

99
static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
100 101 102 103
					   int addr, int reg, u16 val)
{
	int ret;

104
	ret = mdiobus_write_nested(chip->bus, addr, reg, val);
105 106 107 108 109 110
	if (ret < 0)
		return ret;

	return 0;
}

111
static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
112 113 114 115
	.read = mv88e6xxx_smi_single_chip_read,
	.write = mv88e6xxx_smi_single_chip_write,
};

116
static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
117 118 119 120 121
{
	int ret;
	int i;

	for (i = 0; i < 16; i++) {
122
		ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
123 124 125
		if (ret < 0)
			return ret;

126
		if ((ret & SMI_CMD_BUSY) == 0)
127 128 129 130 131 132
			return 0;
	}

	return -ETIMEDOUT;
}

133
static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
134
					 int addr, int reg, u16 *val)
135 136 137
{
	int ret;

138
	/* Wait for the bus to become free. */
139
	ret = mv88e6xxx_smi_multi_chip_wait(chip);
140 141 142
	if (ret < 0)
		return ret;

143
	/* Transmit the read command. */
144
	ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
145
				   SMI_CMD_OP_22_READ | (addr << 5) | reg);
146 147 148
	if (ret < 0)
		return ret;

149
	/* Wait for the read command to complete. */
150
	ret = mv88e6xxx_smi_multi_chip_wait(chip);
151 152 153
	if (ret < 0)
		return ret;

154
	/* Read the data. */
155
	ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
156 157 158
	if (ret < 0)
		return ret;

159
	*val = ret & 0xffff;
160

161
	return 0;
162 163
}

164
static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
165
					  int addr, int reg, u16 val)
166 167 168
{
	int ret;

169
	/* Wait for the bus to become free. */
170
	ret = mv88e6xxx_smi_multi_chip_wait(chip);
171 172 173
	if (ret < 0)
		return ret;

174
	/* Transmit the data to write. */
175
	ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
176 177 178
	if (ret < 0)
		return ret;

179
	/* Transmit the write command. */
180
	ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
181
				   SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
182 183 184
	if (ret < 0)
		return ret;

185
	/* Wait for the write command to complete. */
186
	ret = mv88e6xxx_smi_multi_chip_wait(chip);
187 188 189 190 191 192
	if (ret < 0)
		return ret;

	return 0;
}

193
static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
194 195 196 197
	.read = mv88e6xxx_smi_multi_chip_read,
	.write = mv88e6xxx_smi_multi_chip_write,
};

198
int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
199 200 201
{
	int err;

202
	assert_reg_lock(chip);
203

204
	err = mv88e6xxx_smi_read(chip, addr, reg, val);
205 206 207
	if (err)
		return err;

208
	dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
209 210 211 212 213
		addr, reg, *val);

	return 0;
}

214
int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
215
{
216 217
	int err;

218
	assert_reg_lock(chip);
219

220
	err = mv88e6xxx_smi_write(chip, addr, reg, val);
221 222 223
	if (err)
		return err;

224
	dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
225 226
		addr, reg, val);

227 228 229
	return 0;
}

230
struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
231 232 233 234 235 236 237 238 239 240 241
{
	struct mv88e6xxx_mdio_bus *mdio_bus;

	mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
				    list);
	if (!mdio_bus)
		return NULL;

	return mdio_bus->bus;
}

242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257
static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
{
	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int n = d->hwirq;

	chip->g1_irq.masked |= (1 << n);
}

static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
{
	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int n = d->hwirq;

	chip->g1_irq.masked &= ~(1 << n);
}

258
static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
259 260 261 262 263 264 265 266
{
	unsigned int nhandled = 0;
	unsigned int sub_irq;
	unsigned int n;
	u16 reg;
	int err;

	mutex_lock(&chip->reg_lock);
267
	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283
	mutex_unlock(&chip->reg_lock);

	if (err)
		goto out;

	for (n = 0; n < chip->g1_irq.nirqs; ++n) {
		if (reg & (1 << n)) {
			sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
			handle_nested_irq(sub_irq);
			++nhandled;
		}
	}
out:
	return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
}

284 285 286 287 288 289 290
static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
{
	struct mv88e6xxx_chip *chip = dev_id;

	return mv88e6xxx_g1_irq_thread_work(chip);
}

291 292 293 294 295 296 297 298 299 300 301 302 303 304
static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
{
	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);

	mutex_lock(&chip->reg_lock);
}

static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
{
	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
	u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
	u16 reg;
	int err;

305
	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
306 307 308 309 310 311
	if (err)
		goto out;

	reg &= ~mask;
	reg |= (~chip->g1_irq.masked & mask);

312
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
313 314 315 316 317 318 319
	if (err)
		goto out;

out:
	mutex_unlock(&chip->reg_lock);
}

320
static const struct irq_chip mv88e6xxx_g1_irq_chip = {
321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345
	.name			= "mv88e6xxx-g1",
	.irq_mask		= mv88e6xxx_g1_irq_mask,
	.irq_unmask		= mv88e6xxx_g1_irq_unmask,
	.irq_bus_lock		= mv88e6xxx_g1_irq_bus_lock,
	.irq_bus_sync_unlock	= mv88e6xxx_g1_irq_bus_sync_unlock,
};

static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
				       unsigned int irq,
				       irq_hw_number_t hwirq)
{
	struct mv88e6xxx_chip *chip = d->host_data;

	irq_set_chip_data(irq, d->host_data);
	irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
	irq_set_noprobe(irq);

	return 0;
}

static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
	.map	= mv88e6xxx_g1_irq_domain_map,
	.xlate	= irq_domain_xlate_twocell,
};

346
static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
347 348
{
	int irq, virq;
349 350
	u16 mask;

351
	mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
352
	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
353
	mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
354

355
	for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
356
		virq = irq_find_mapping(chip->g1_irq.domain, irq);
357 358 359
		irq_dispose_mapping(virq);
	}

360
	irq_domain_remove(chip->g1_irq.domain);
361 362
}

363 364
static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
{
365
	mv88e6xxx_g1_irq_free_common(chip);
366 367 368 369 370

	free_irq(chip->irq, chip);
}

static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
371
{
372 373
	int err, irq, virq;
	u16 reg, mask;
374 375 376 377 378 379 380 381 382 383 384 385 386 387

	chip->g1_irq.nirqs = chip->info->g1_irqs;
	chip->g1_irq.domain = irq_domain_add_simple(
		NULL, chip->g1_irq.nirqs, 0,
		&mv88e6xxx_g1_irq_domain_ops, chip);
	if (!chip->g1_irq.domain)
		return -ENOMEM;

	for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
		irq_create_mapping(chip->g1_irq.domain, irq);

	chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
	chip->g1_irq.masked = ~0;

388
	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
389
	if (err)
390
		goto out_mapping;
391

392
	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
393

394
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
395
	if (err)
396
		goto out_disable;
397 398

	/* Reading the interrupt status clears (most of) them */
399
	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
400
	if (err)
401
		goto out_disable;
402 403 404

	return 0;

405
out_disable:
406
	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
407
	mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
408 409 410 411 412 413 414 415

out_mapping:
	for (irq = 0; irq < 16; irq++) {
		virq = irq_find_mapping(chip->g1_irq.domain, irq);
		irq_dispose_mapping(virq);
	}

	irq_domain_remove(chip->g1_irq.domain);
416 417 418 419

	return err;
}

420 421 422 423 424 425 426 427 428 429
static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
{
	int err;

	err = mv88e6xxx_g1_irq_setup_common(chip);
	if (err)
		return err;

	err = request_threaded_irq(chip->irq, NULL,
				   mv88e6xxx_g1_irq_thread_fn,
430
				   IRQF_ONESHOT,
431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471
				   dev_name(chip->dev), chip);
	if (err)
		mv88e6xxx_g1_irq_free_common(chip);

	return err;
}

static void mv88e6xxx_irq_poll(struct kthread_work *work)
{
	struct mv88e6xxx_chip *chip = container_of(work,
						   struct mv88e6xxx_chip,
						   irq_poll_work.work);
	mv88e6xxx_g1_irq_thread_work(chip);

	kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
				   msecs_to_jiffies(100));
}

static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
{
	int err;

	err = mv88e6xxx_g1_irq_setup_common(chip);
	if (err)
		return err;

	kthread_init_delayed_work(&chip->irq_poll_work,
				  mv88e6xxx_irq_poll);

	chip->kworker = kthread_create_worker(0, dev_name(chip->dev));
	if (IS_ERR(chip->kworker))
		return PTR_ERR(chip->kworker);

	kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
				   msecs_to_jiffies(100));

	return 0;
}

static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
{
472 473
	mv88e6xxx_g1_irq_free_common(chip);

474 475 476 477
	kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
	kthread_destroy_worker(chip->kworker);
}

478
int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
479
{
480
	int i;
481

482
	for (i = 0; i < 16; i++) {
483 484 485 486 487 488 489 490 491 492 493 494 495
		u16 val;
		int err;

		err = mv88e6xxx_read(chip, addr, reg, &val);
		if (err)
			return err;

		if (!(val & mask))
			return 0;

		usleep_range(1000, 2000);
	}

496
	dev_err(chip->dev, "Timeout while waiting for switch\n");
497 498 499
	return -ETIMEDOUT;
}

500
/* Indirect write to single pointer-data register with an Update bit */
501
int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
502 503
{
	u16 val;
504
	int err;
505 506

	/* Wait until the previous operation is completed */
507 508 509
	err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
	if (err)
		return err;
510 511 512 513 514 515 516

	/* Set the Update bit to trigger a write operation */
	val = BIT(15) | update;

	return mv88e6xxx_write(chip, addr, reg, val);
}

517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548
static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
				    int link, int speed, int duplex,
				    phy_interface_t mode)
{
	int err;

	if (!chip->info->ops->port_set_link)
		return 0;

	/* Port's MAC control must not be changed unless the link is down */
	err = chip->info->ops->port_set_link(chip, port, 0);
	if (err)
		return err;

	if (chip->info->ops->port_set_speed) {
		err = chip->info->ops->port_set_speed(chip, port, speed);
		if (err && err != -EOPNOTSUPP)
			goto restore_link;
	}

	if (chip->info->ops->port_set_duplex) {
		err = chip->info->ops->port_set_duplex(chip, port, duplex);
		if (err && err != -EOPNOTSUPP)
			goto restore_link;
	}

	if (chip->info->ops->port_set_rgmii_delay) {
		err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
		if (err && err != -EOPNOTSUPP)
			goto restore_link;
	}

549 550 551 552 553 554
	if (chip->info->ops->port_set_cmode) {
		err = chip->info->ops->port_set_cmode(chip, port, mode);
		if (err && err != -EOPNOTSUPP)
			goto restore_link;
	}

555 556 557
	err = 0;
restore_link:
	if (chip->info->ops->port_set_link(chip, port, link))
558
		dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
559 560 561 562

	return err;
}

563 564 565 566
/* We expect the switch to perform auto negotiation if there is a real
 * phy. However, in the case of a fixed link phy, we force the port
 * settings from the fixed link settings.
 */
567 568
static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
				  struct phy_device *phydev)
569
{
V
Vivien Didelot 已提交
570
	struct mv88e6xxx_chip *chip = ds->priv;
571
	int err;
572 573 574 575

	if (!phy_is_pseudo_fixed_link(phydev))
		return;

576
	mutex_lock(&chip->reg_lock);
577 578
	err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
				       phydev->duplex, phydev->interface);
579
	mutex_unlock(&chip->reg_lock);
580 581

	if (err && err != -EOPNOTSUPP)
582
		dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
583 584
}

585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661
static void mv88e6xxx_validate(struct dsa_switch *ds, int port,
			       unsigned long *supported,
			       struct phylink_link_state *state)
{
}

static int mv88e6xxx_link_state(struct dsa_switch *ds, int port,
				struct phylink_link_state *state)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int err;

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_port_link_state(chip, port, state);
	mutex_unlock(&chip->reg_lock);

	return err;
}

static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
				 unsigned int mode,
				 const struct phylink_link_state *state)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int speed, duplex, link, err;

	if (mode == MLO_AN_PHY)
		return;

	if (mode == MLO_AN_FIXED) {
		link = LINK_FORCED_UP;
		speed = state->speed;
		duplex = state->duplex;
	} else {
		speed = SPEED_UNFORCED;
		duplex = DUPLEX_UNFORCED;
		link = LINK_UNFORCED;
	}

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_port_setup_mac(chip, port, link, speed, duplex,
				       state->interface);
	mutex_unlock(&chip->reg_lock);

	if (err && err != -EOPNOTSUPP)
		dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
}

static void mv88e6xxx_mac_link_force(struct dsa_switch *ds, int port, int link)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int err;

	mutex_lock(&chip->reg_lock);
	err = chip->info->ops->port_set_link(chip, port, link);
	mutex_unlock(&chip->reg_lock);

	if (err)
		dev_err(chip->dev, "p%d: failed to force MAC link\n", port);
}

static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
				    unsigned int mode,
				    phy_interface_t interface)
{
	if (mode == MLO_AN_FIXED)
		mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_DOWN);
}

static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
				  unsigned int mode, phy_interface_t interface,
				  struct phy_device *phydev)
{
	if (mode == MLO_AN_FIXED)
		mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_UP);
}

662
static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
663
{
664 665
	if (!chip->info->ops->stats_snapshot)
		return -EOPNOTSUPP;
666

667
	return chip->info->ops->stats_snapshot(chip, port);
668 669
}

670
static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729
	{ "in_good_octets",		8, 0x00, STATS_TYPE_BANK0, },
	{ "in_bad_octets",		4, 0x02, STATS_TYPE_BANK0, },
	{ "in_unicast",			4, 0x04, STATS_TYPE_BANK0, },
	{ "in_broadcasts",		4, 0x06, STATS_TYPE_BANK0, },
	{ "in_multicasts",		4, 0x07, STATS_TYPE_BANK0, },
	{ "in_pause",			4, 0x16, STATS_TYPE_BANK0, },
	{ "in_undersize",		4, 0x18, STATS_TYPE_BANK0, },
	{ "in_fragments",		4, 0x19, STATS_TYPE_BANK0, },
	{ "in_oversize",		4, 0x1a, STATS_TYPE_BANK0, },
	{ "in_jabber",			4, 0x1b, STATS_TYPE_BANK0, },
	{ "in_rx_error",		4, 0x1c, STATS_TYPE_BANK0, },
	{ "in_fcs_error",		4, 0x1d, STATS_TYPE_BANK0, },
	{ "out_octets",			8, 0x0e, STATS_TYPE_BANK0, },
	{ "out_unicast",		4, 0x10, STATS_TYPE_BANK0, },
	{ "out_broadcasts",		4, 0x13, STATS_TYPE_BANK0, },
	{ "out_multicasts",		4, 0x12, STATS_TYPE_BANK0, },
	{ "out_pause",			4, 0x15, STATS_TYPE_BANK0, },
	{ "excessive",			4, 0x11, STATS_TYPE_BANK0, },
	{ "collisions",			4, 0x1e, STATS_TYPE_BANK0, },
	{ "deferred",			4, 0x05, STATS_TYPE_BANK0, },
	{ "single",			4, 0x14, STATS_TYPE_BANK0, },
	{ "multiple",			4, 0x17, STATS_TYPE_BANK0, },
	{ "out_fcs_error",		4, 0x03, STATS_TYPE_BANK0, },
	{ "late",			4, 0x1f, STATS_TYPE_BANK0, },
	{ "hist_64bytes",		4, 0x08, STATS_TYPE_BANK0, },
	{ "hist_65_127bytes",		4, 0x09, STATS_TYPE_BANK0, },
	{ "hist_128_255bytes",		4, 0x0a, STATS_TYPE_BANK0, },
	{ "hist_256_511bytes",		4, 0x0b, STATS_TYPE_BANK0, },
	{ "hist_512_1023bytes",		4, 0x0c, STATS_TYPE_BANK0, },
	{ "hist_1024_max_bytes",	4, 0x0d, STATS_TYPE_BANK0, },
	{ "sw_in_discards",		4, 0x10, STATS_TYPE_PORT, },
	{ "sw_in_filtered",		2, 0x12, STATS_TYPE_PORT, },
	{ "sw_out_filtered",		2, 0x13, STATS_TYPE_PORT, },
	{ "in_discards",		4, 0x00, STATS_TYPE_BANK1, },
	{ "in_filtered",		4, 0x01, STATS_TYPE_BANK1, },
	{ "in_accepted",		4, 0x02, STATS_TYPE_BANK1, },
	{ "in_bad_accepted",		4, 0x03, STATS_TYPE_BANK1, },
	{ "in_good_avb_class_a",	4, 0x04, STATS_TYPE_BANK1, },
	{ "in_good_avb_class_b",	4, 0x05, STATS_TYPE_BANK1, },
	{ "in_bad_avb_class_a",		4, 0x06, STATS_TYPE_BANK1, },
	{ "in_bad_avb_class_b",		4, 0x07, STATS_TYPE_BANK1, },
	{ "tcam_counter_0",		4, 0x08, STATS_TYPE_BANK1, },
	{ "tcam_counter_1",		4, 0x09, STATS_TYPE_BANK1, },
	{ "tcam_counter_2",		4, 0x0a, STATS_TYPE_BANK1, },
	{ "tcam_counter_3",		4, 0x0b, STATS_TYPE_BANK1, },
	{ "in_da_unknown",		4, 0x0e, STATS_TYPE_BANK1, },
	{ "in_management",		4, 0x0f, STATS_TYPE_BANK1, },
	{ "out_queue_0",		4, 0x10, STATS_TYPE_BANK1, },
	{ "out_queue_1",		4, 0x11, STATS_TYPE_BANK1, },
	{ "out_queue_2",		4, 0x12, STATS_TYPE_BANK1, },
	{ "out_queue_3",		4, 0x13, STATS_TYPE_BANK1, },
	{ "out_queue_4",		4, 0x14, STATS_TYPE_BANK1, },
	{ "out_queue_5",		4, 0x15, STATS_TYPE_BANK1, },
	{ "out_queue_6",		4, 0x16, STATS_TYPE_BANK1, },
	{ "out_queue_7",		4, 0x17, STATS_TYPE_BANK1, },
	{ "out_cut_through",		4, 0x18, STATS_TYPE_BANK1, },
	{ "out_octets_a",		4, 0x1a, STATS_TYPE_BANK1, },
	{ "out_octets_b",		4, 0x1b, STATS_TYPE_BANK1, },
	{ "out_management",		4, 0x1f, STATS_TYPE_BANK1, },
730 731
};

732
static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
733
					    struct mv88e6xxx_hw_stat *s,
734 735
					    int port, u16 bank1_select,
					    u16 histogram)
736 737 738
{
	u32 low;
	u32 high = 0;
739
	u16 reg = 0;
740
	int err;
741 742
	u64 value;

743
	switch (s->type) {
744
	case STATS_TYPE_PORT:
745 746
		err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
		if (err)
747
			return U64_MAX;
748

749
		low = reg;
750
		if (s->size == 4) {
751 752
			err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
			if (err)
753
				return U64_MAX;
754
			high = reg;
755
		}
756
		break;
757
	case STATS_TYPE_BANK1:
758
		reg = bank1_select;
759 760
		/* fall through */
	case STATS_TYPE_BANK0:
761
		reg |= s->reg | histogram;
762
		mv88e6xxx_g1_stats_read(chip, reg, &low);
763
		if (s->size == 8)
764
			mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
765 766
		break;
	default:
767
		return U64_MAX;
768 769 770 771 772
	}
	value = (((u64)high) << 16) | low;
	return value;
}

773 774
static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
				       uint8_t *data, int types)
775
{
776 777
	struct mv88e6xxx_hw_stat *stat;
	int i, j;
778

779 780
	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
		stat = &mv88e6xxx_hw_stats[i];
781
		if (stat->type & types) {
782 783 784 785
			memcpy(data + j * ETH_GSTRING_LEN, stat->string,
			       ETH_GSTRING_LEN);
			j++;
		}
786
	}
787 788

	return j;
789 790
}

791 792
static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
				       uint8_t *data)
793
{
794 795
	return mv88e6xxx_stats_get_strings(chip, data,
					   STATS_TYPE_BANK0 | STATS_TYPE_PORT);
796 797
}

798 799
static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
				       uint8_t *data)
800
{
801 802
	return mv88e6xxx_stats_get_strings(chip, data,
					   STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
803 804
}

805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822
static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
	"atu_member_violation",
	"atu_miss_violation",
	"atu_full_violation",
	"vtu_member_violation",
	"vtu_miss_violation",
};

static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
{
	unsigned int i;

	for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
		strlcpy(data + i * ETH_GSTRING_LEN,
			mv88e6xxx_atu_vtu_stats_strings[i],
			ETH_GSTRING_LEN);
}

823
static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
824
				  u32 stringset, uint8_t *data)
825
{
V
Vivien Didelot 已提交
826
	struct mv88e6xxx_chip *chip = ds->priv;
827
	int count = 0;
828

829 830 831
	if (stringset != ETH_SS_STATS)
		return;

832 833
	mutex_lock(&chip->reg_lock);

834
	if (chip->info->ops->stats_get_strings)
835 836 837 838
		count = chip->info->ops->stats_get_strings(chip, data);

	if (chip->info->ops->serdes_get_strings) {
		data += count * ETH_GSTRING_LEN;
839
		count = chip->info->ops->serdes_get_strings(chip, port, data);
840
	}
841

842 843 844
	data += count * ETH_GSTRING_LEN;
	mv88e6xxx_atu_vtu_get_strings(data);

845
	mutex_unlock(&chip->reg_lock);
846 847 848 849 850
}

static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
					  int types)
{
851 852 853 854 855
	struct mv88e6xxx_hw_stat *stat;
	int i, j;

	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
		stat = &mv88e6xxx_hw_stats[i];
856
		if (stat->type & types)
857 858 859
			j++;
	}
	return j;
860 861
}

862 863 864 865 866 867 868 869 870 871 872 873
static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
{
	return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
					      STATS_TYPE_PORT);
}

static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
{
	return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
					      STATS_TYPE_BANK1);
}

874
static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
875 876
{
	struct mv88e6xxx_chip *chip = ds->priv;
877 878
	int serdes_count = 0;
	int count = 0;
879

880 881 882
	if (sset != ETH_SS_STATS)
		return 0;

883
	mutex_lock(&chip->reg_lock);
884
	if (chip->info->ops->stats_get_sset_count)
885 886 887 888 889 890 891
		count = chip->info->ops->stats_get_sset_count(chip);
	if (count < 0)
		goto out;

	if (chip->info->ops->serdes_get_sset_count)
		serdes_count = chip->info->ops->serdes_get_sset_count(chip,
								      port);
892
	if (serdes_count < 0) {
893
		count = serdes_count;
894 895 896 897 898
		goto out;
	}
	count += serdes_count;
	count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);

899
out:
900
	mutex_unlock(&chip->reg_lock);
901

902
	return count;
903 904
}

905 906 907
static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
				     uint64_t *data, int types,
				     u16 bank1_select, u16 histogram)
908 909 910 911 912 913 914
{
	struct mv88e6xxx_hw_stat *stat;
	int i, j;

	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
		stat = &mv88e6xxx_hw_stats[i];
		if (stat->type & types) {
915
			mutex_lock(&chip->reg_lock);
916 917 918
			data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
							      bank1_select,
							      histogram);
919 920
			mutex_unlock(&chip->reg_lock);

921 922 923
			j++;
		}
	}
924
	return j;
925 926
}

927 928
static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
				     uint64_t *data)
929 930
{
	return mv88e6xxx_stats_get_stats(chip, port, data,
931
					 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
932
					 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
933 934
}

935 936
static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
				     uint64_t *data)
937 938
{
	return mv88e6xxx_stats_get_stats(chip, port, data,
939
					 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
940 941
					 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
					 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
942 943
}

944 945
static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
				     uint64_t *data)
946 947 948
{
	return mv88e6xxx_stats_get_stats(chip, port, data,
					 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
949 950
					 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
					 0);
951 952
}

953 954 955 956 957 958 959 960 961 962
static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
					uint64_t *data)
{
	*data++ = chip->ports[port].atu_member_violation;
	*data++ = chip->ports[port].atu_miss_violation;
	*data++ = chip->ports[port].atu_full_violation;
	*data++ = chip->ports[port].vtu_member_violation;
	*data++ = chip->ports[port].vtu_miss_violation;
}

963 964 965
static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
				uint64_t *data)
{
966 967
	int count = 0;

968
	if (chip->info->ops->stats_get_stats)
969 970
		count = chip->info->ops->stats_get_stats(chip, port, data);

971
	mutex_lock(&chip->reg_lock);
972 973
	if (chip->info->ops->serdes_get_stats) {
		data += count;
974
		count = chip->info->ops->serdes_get_stats(chip, port, data);
975
	}
976 977 978
	data += count;
	mv88e6xxx_atu_vtu_get_stats(chip, port, data);
	mutex_unlock(&chip->reg_lock);
979 980
}

981 982
static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
					uint64_t *data)
983
{
V
Vivien Didelot 已提交
984
	struct mv88e6xxx_chip *chip = ds->priv;
985 986
	int ret;

987
	mutex_lock(&chip->reg_lock);
988

989
	ret = mv88e6xxx_stats_snapshot(chip, port);
990 991 992
	mutex_unlock(&chip->reg_lock);

	if (ret < 0)
993
		return;
994 995

	mv88e6xxx_get_stats(chip, port, data);
996

997 998
}

999
static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1000 1001 1002 1003
{
	return 32 * sizeof(u16);
}

1004 1005
static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
			       struct ethtool_regs *regs, void *_p)
1006
{
V
Vivien Didelot 已提交
1007
	struct mv88e6xxx_chip *chip = ds->priv;
1008 1009
	int err;
	u16 reg;
1010 1011 1012 1013 1014 1015 1016
	u16 *p = _p;
	int i;

	regs->version = 0;

	memset(p, 0xff, 32 * sizeof(u16));

1017
	mutex_lock(&chip->reg_lock);
1018

1019 1020
	for (i = 0; i < 32; i++) {

1021 1022 1023
		err = mv88e6xxx_port_read(chip, port, i, &reg);
		if (!err)
			p[i] = reg;
1024
	}
1025

1026
	mutex_unlock(&chip->reg_lock);
1027 1028
}

V
Vivien Didelot 已提交
1029 1030
static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
				 struct ethtool_eee *e)
1031
{
1032 1033
	/* Nothing to do on the port's MAC */
	return 0;
1034 1035
}

V
Vivien Didelot 已提交
1036 1037
static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
				 struct ethtool_eee *e)
1038
{
1039 1040
	/* Nothing to do on the port's MAC */
	return 0;
1041 1042
}

1043
static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1044
{
1045 1046 1047
	struct dsa_switch *ds = NULL;
	struct net_device *br;
	u16 pvlan;
1048 1049
	int i;

1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069
	if (dev < DSA_MAX_SWITCHES)
		ds = chip->ds->dst->ds[dev];

	/* Prevent frames from unknown switch or port */
	if (!ds || port >= ds->num_ports)
		return 0;

	/* Frames from DSA links and CPU ports can egress any local port */
	if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
		return mv88e6xxx_port_mask(chip);

	br = ds->ports[port].bridge_dev;
	pvlan = 0;

	/* Frames from user ports can egress any local DSA links and CPU ports,
	 * as well as any local member of their bridge group.
	 */
	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
		if (dsa_is_cpu_port(chip->ds, i) ||
		    dsa_is_dsa_port(chip->ds, i) ||
V
Vivien Didelot 已提交
1070
		    (br && dsa_to_port(chip->ds, i)->bridge_dev == br))
1071 1072 1073 1074 1075
			pvlan |= BIT(i);

	return pvlan;
}

1076
static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1077 1078
{
	u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1079 1080 1081

	/* prevent frames from going back out of the port they came in on */
	output_ports &= ~BIT(port);
1082

1083
	return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1084 1085
}

1086 1087
static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
					 u8 state)
1088
{
V
Vivien Didelot 已提交
1089
	struct mv88e6xxx_chip *chip = ds->priv;
1090
	int err;
1091

1092
	mutex_lock(&chip->reg_lock);
1093
	err = mv88e6xxx_port_set_state(chip, port, state);
1094
	mutex_unlock(&chip->reg_lock);
1095 1096

	if (err)
1097
		dev_err(ds->dev, "p%d: failed to update state\n", port);
1098 1099
}

1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118
static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
{
	int err;

	if (chip->info->ops->ieee_pri_map) {
		err = chip->info->ops->ieee_pri_map(chip);
		if (err)
			return err;
	}

	if (chip->info->ops->ip_pri_map) {
		err = chip->info->ops->ip_pri_map(chip);
		if (err)
			return err;
	}

	return 0;
}

1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138
static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
{
	int target, port;
	int err;

	if (!chip->info->global2_addr)
		return 0;

	/* Initialize the routing port to the 32 possible target devices */
	for (target = 0; target < 32; target++) {
		port = 0x1f;
		if (target < DSA_MAX_SWITCHES)
			if (chip->ds->rtable[target] != DSA_RTABLE_NONE)
				port = chip->ds->rtable[target];

		err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
		if (err)
			return err;
	}

1139 1140 1141 1142 1143 1144 1145
	if (chip->info->ops->set_cascade_port) {
		port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
		err = chip->info->ops->set_cascade_port(chip, port);
		if (err)
			return err;
	}

1146 1147 1148 1149
	err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
	if (err)
		return err;

1150 1151 1152
	return 0;
}

1153 1154 1155 1156 1157 1158 1159 1160 1161
static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
{
	/* Clear all trunk masks and mapping */
	if (chip->info->global2_addr)
		return mv88e6xxx_g2_trunk_clear(chip);

	return 0;
}

1162 1163 1164 1165 1166 1167 1168 1169
static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->rmu_disable)
		return chip->info->ops->rmu_disable(chip);

	return 0;
}

1170 1171 1172 1173 1174 1175 1176 1177
static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->pot_clear)
		return chip->info->ops->pot_clear(chip);

	return 0;
}

1178 1179 1180 1181 1182 1183 1184 1185
static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->mgmt_rsvd2cpu)
		return chip->info->ops->mgmt_rsvd2cpu(chip);

	return 0;
}

1186 1187
static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
{
1188 1189
	int err;

1190 1191 1192 1193
	err = mv88e6xxx_g1_atu_flush(chip, 0, true);
	if (err)
		return err;

1194 1195 1196 1197
	err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
	if (err)
		return err;

1198 1199 1200
	return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
}

1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220
static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
{
	int port;
	int err;

	if (!chip->info->ops->irl_init_all)
		return 0;

	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
		/* Disable ingress rate limiting by resetting all per port
		 * ingress rate limit resources to their initial state.
		 */
		err = chip->info->ops->irl_init_all(chip, port);
		if (err)
			return err;
	}

	return 0;
}

1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233
static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->set_switch_mac) {
		u8 addr[ETH_ALEN];

		eth_random_addr(addr);

		return chip->info->ops->set_switch_mac(chip, addr);
	}

	return 0;
}

1234 1235 1236 1237 1238 1239 1240 1241 1242
static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
{
	u16 pvlan = 0;

	if (!mv88e6xxx_has_pvt(chip))
		return -EOPNOTSUPP;

	/* Skip the local source device, which uses in-chip port VLAN */
	if (dev != chip->ds->index)
1243
		pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1244 1245 1246 1247

	return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
}

1248 1249
static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
{
1250 1251 1252
	int dev, port;
	int err;

1253 1254 1255 1256 1257 1258
	if (!mv88e6xxx_has_pvt(chip))
		return 0;

	/* Clear 5 Bit Port for usage with Marvell Link Street devices:
	 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
	 */
1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271
	err = mv88e6xxx_g2_misc_4_bit_port(chip);
	if (err)
		return err;

	for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
		for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
			err = mv88e6xxx_pvt_map(chip, dev, port);
			if (err)
				return err;
		}
	}

	return 0;
1272 1273
}

1274 1275 1276 1277 1278 1279
static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int err;

	mutex_lock(&chip->reg_lock);
1280
	err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
1281 1282 1283
	mutex_unlock(&chip->reg_lock);

	if (err)
1284
		dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
1285 1286
}

1287 1288 1289 1290 1291 1292 1293 1294
static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
{
	if (!chip->info->max_vid)
		return 0;

	return mv88e6xxx_g1_vtu_flush(chip);
}

1295 1296 1297 1298 1299 1300 1301 1302 1303
static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
				 struct mv88e6xxx_vtu_entry *entry)
{
	if (!chip->info->ops->vtu_getnext)
		return -EOPNOTSUPP;

	return chip->info->ops->vtu_getnext(chip, entry);
}

1304 1305 1306 1307 1308 1309 1310 1311 1312
static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
				   struct mv88e6xxx_vtu_entry *entry)
{
	if (!chip->info->ops->vtu_loadpurge)
		return -EOPNOTSUPP;

	return chip->info->ops->vtu_loadpurge(chip, entry);
}

1313
static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1314 1315
{
	DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1316 1317 1318
	struct mv88e6xxx_vtu_entry vlan = {
		.vid = chip->info->max_vid,
	};
1319
	int i, err;
1320 1321 1322

	bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);

1323
	/* Set every FID bit used by the (un)bridged ports */
1324
	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1325
		err = mv88e6xxx_port_get_fid(chip, i, fid);
1326 1327 1328 1329 1330 1331
		if (err)
			return err;

		set_bit(*fid, fid_bitmap);
	}

1332 1333
	/* Set every FID bit used by the VLAN entries */
	do {
1334
		err = mv88e6xxx_vtu_getnext(chip, &vlan);
1335 1336 1337 1338 1339 1340 1341
		if (err)
			return err;

		if (!vlan.valid)
			break;

		set_bit(vlan.fid, fid_bitmap);
1342
	} while (vlan.vid < chip->info->max_vid);
1343 1344 1345 1346 1347

	/* The reset value 0x000 is used to indicate that multiple address
	 * databases are not needed. Return the next positive available.
	 */
	*fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1348
	if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1349 1350 1351
		return -ENOSPC;

	/* Clear the database */
1352
	return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1353 1354
}

1355 1356
static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
			     struct mv88e6xxx_vtu_entry *entry, bool new)
1357 1358 1359 1360 1361 1362
{
	int err;

	if (!vid)
		return -EINVAL;

1363 1364
	entry->vid = vid - 1;
	entry->valid = false;
1365

1366
	err = mv88e6xxx_vtu_getnext(chip, entry);
1367 1368 1369
	if (err)
		return err;

1370 1371
	if (entry->vid == vid && entry->valid)
		return 0;
1372

1373 1374 1375 1376 1377 1378 1379 1380
	if (new) {
		int i;

		/* Initialize a fresh VLAN entry */
		memset(entry, 0, sizeof(*entry));
		entry->valid = true;
		entry->vid = vid;

1381
		/* Exclude all ports */
1382
		for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1383
			entry->member[i] =
1384
				MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1385 1386

		return mv88e6xxx_atu_new(chip, &entry->fid);
1387 1388
	}

1389 1390
	/* switchdev expects -EOPNOTSUPP to honor software VLANs */
	return -EOPNOTSUPP;
1391 1392
}

1393 1394 1395
static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
					u16 vid_begin, u16 vid_end)
{
V
Vivien Didelot 已提交
1396
	struct mv88e6xxx_chip *chip = ds->priv;
1397 1398 1399
	struct mv88e6xxx_vtu_entry vlan = {
		.vid = vid_begin - 1,
	};
1400 1401
	int i, err;

1402 1403 1404 1405
	/* DSA and CPU ports have to be members of multiple vlans */
	if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
		return 0;

1406 1407 1408
	if (!vid_begin)
		return -EOPNOTSUPP;

1409
	mutex_lock(&chip->reg_lock);
1410 1411

	do {
1412
		err = mv88e6xxx_vtu_getnext(chip, &vlan);
1413 1414 1415 1416 1417 1418 1419 1420 1421
		if (err)
			goto unlock;

		if (!vlan.valid)
			break;

		if (vlan.vid > vid_end)
			break;

1422
		for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1423 1424 1425
			if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
				continue;

1426
			if (!ds->ports[i].slave)
1427 1428
				continue;

1429
			if (vlan.member[i] ==
1430
			    MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1431 1432
				continue;

V
Vivien Didelot 已提交
1433
			if (dsa_to_port(ds, i)->bridge_dev ==
1434
			    ds->ports[port].bridge_dev)
1435 1436
				break; /* same bridge, check next VLAN */

V
Vivien Didelot 已提交
1437
			if (!dsa_to_port(ds, i)->bridge_dev)
1438 1439
				continue;

1440 1441
			dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
				port, vlan.vid, i,
V
Vivien Didelot 已提交
1442
				netdev_name(dsa_to_port(ds, i)->bridge_dev));
1443 1444 1445 1446 1447 1448
			err = -EOPNOTSUPP;
			goto unlock;
		}
	} while (vlan.vid < vid_end);

unlock:
1449
	mutex_unlock(&chip->reg_lock);
1450 1451 1452 1453

	return err;
}

1454 1455
static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
					 bool vlan_filtering)
1456
{
V
Vivien Didelot 已提交
1457
	struct mv88e6xxx_chip *chip = ds->priv;
1458 1459
	u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
		MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1460
	int err;
1461

1462
	if (!chip->info->max_vid)
1463 1464
		return -EOPNOTSUPP;

1465
	mutex_lock(&chip->reg_lock);
1466
	err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1467
	mutex_unlock(&chip->reg_lock);
1468

1469
	return err;
1470 1471
}

1472 1473
static int
mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1474
			    const struct switchdev_obj_port_vlan *vlan)
1475
{
V
Vivien Didelot 已提交
1476
	struct mv88e6xxx_chip *chip = ds->priv;
1477 1478
	int err;

1479
	if (!chip->info->max_vid)
1480 1481
		return -EOPNOTSUPP;

1482 1483 1484 1485 1486 1487 1488 1489
	/* If the requested port doesn't belong to the same bridge as the VLAN
	 * members, do not support it (yet) and fallback to software VLAN.
	 */
	err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
					   vlan->vid_end);
	if (err)
		return err;

1490 1491 1492 1493 1494 1495
	/* We don't need any dynamic resource from the kernel (yet),
	 * so skip the prepare phase.
	 */
	return 0;
}

1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539
static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
					const unsigned char *addr, u16 vid,
					u8 state)
{
	struct mv88e6xxx_vtu_entry vlan;
	struct mv88e6xxx_atu_entry entry;
	int err;

	/* Null VLAN ID corresponds to the port private database */
	if (vid == 0)
		err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
	else
		err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
	if (err)
		return err;

	entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
	ether_addr_copy(entry.mac, addr);
	eth_addr_dec(entry.mac);

	err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
	if (err)
		return err;

	/* Initialize a fresh ATU entry if it isn't found */
	if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED ||
	    !ether_addr_equal(entry.mac, addr)) {
		memset(&entry, 0, sizeof(entry));
		ether_addr_copy(entry.mac, addr);
	}

	/* Purge the ATU entry only if no port is using it anymore */
	if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
		entry.portvec &= ~BIT(port);
		if (!entry.portvec)
			entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
	} else {
		entry.portvec |= BIT(port);
		entry.state = state;
	}

	return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
}

1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562
static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
					u16 vid)
{
	const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
	u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;

	return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
}

static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
{
	int port;
	int err;

	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
		err = mv88e6xxx_port_add_broadcast(chip, port, vid);
		if (err)
			return err;
	}

	return 0;
}

1563
static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1564
				    u16 vid, u8 member)
1565
{
1566
	struct mv88e6xxx_vtu_entry vlan;
1567 1568
	int err;

1569
	err = mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1570
	if (err)
1571
		return err;
1572

1573
	vlan.member[port] = member;
1574

1575 1576 1577 1578 1579
	err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
	if (err)
		return err;

	return mv88e6xxx_broadcast_setup(chip, vid);
1580 1581
}

1582
static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1583
				    const struct switchdev_obj_port_vlan *vlan)
1584
{
V
Vivien Didelot 已提交
1585
	struct mv88e6xxx_chip *chip = ds->priv;
1586 1587
	bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
	bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1588
	u8 member;
1589 1590
	u16 vid;

1591
	if (!chip->info->max_vid)
1592 1593
		return;

1594
	if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1595
		member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
1596
	else if (untagged)
1597
		member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
1598
	else
1599
		member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
1600

1601
	mutex_lock(&chip->reg_lock);
1602

1603
	for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1604
		if (_mv88e6xxx_port_vlan_add(chip, port, vid, member))
1605 1606
			dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
				vid, untagged ? 'u' : 't');
1607

1608
	if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
1609 1610
		dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
			vlan->vid_end);
1611

1612
	mutex_unlock(&chip->reg_lock);
1613 1614
}

1615
static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1616
				    int port, u16 vid)
1617
{
1618
	struct mv88e6xxx_vtu_entry vlan;
1619 1620
	int i, err;

1621
	err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1622
	if (err)
1623
		return err;
1624

1625
	/* Tell switchdev if this VLAN is handled in software */
1626
	if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1627
		return -EOPNOTSUPP;
1628

1629
	vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1630 1631

	/* keep the VLAN unless all ports are excluded */
1632
	vlan.valid = false;
1633
	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1634 1635
		if (vlan.member[i] !=
		    MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1636
			vlan.valid = true;
1637 1638 1639 1640
			break;
		}
	}

1641
	err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1642 1643 1644
	if (err)
		return err;

1645
	return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
1646 1647
}

1648 1649
static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
				   const struct switchdev_obj_port_vlan *vlan)
1650
{
V
Vivien Didelot 已提交
1651
	struct mv88e6xxx_chip *chip = ds->priv;
1652 1653 1654
	u16 pvid, vid;
	int err = 0;

1655
	if (!chip->info->max_vid)
1656 1657
		return -EOPNOTSUPP;

1658
	mutex_lock(&chip->reg_lock);
1659

1660
	err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1661 1662 1663
	if (err)
		goto unlock;

1664
	for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1665
		err = _mv88e6xxx_port_vlan_del(chip, port, vid);
1666 1667 1668 1669
		if (err)
			goto unlock;

		if (vid == pvid) {
1670
			err = mv88e6xxx_port_set_pvid(chip, port, 0);
1671 1672 1673 1674 1675
			if (err)
				goto unlock;
		}
	}

1676
unlock:
1677
	mutex_unlock(&chip->reg_lock);
1678 1679 1680 1681

	return err;
}

1682 1683
static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
				  const unsigned char *addr, u16 vid)
1684
{
V
Vivien Didelot 已提交
1685
	struct mv88e6xxx_chip *chip = ds->priv;
1686
	int err;
1687

1688
	mutex_lock(&chip->reg_lock);
1689 1690
	err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
					   MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1691
	mutex_unlock(&chip->reg_lock);
1692 1693

	return err;
1694 1695
}

1696
static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1697
				  const unsigned char *addr, u16 vid)
1698
{
V
Vivien Didelot 已提交
1699
	struct mv88e6xxx_chip *chip = ds->priv;
1700
	int err;
1701

1702
	mutex_lock(&chip->reg_lock);
1703
	err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1704
					   MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
1705
	mutex_unlock(&chip->reg_lock);
1706

1707
	return err;
1708 1709
}

1710 1711
static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
				      u16 fid, u16 vid, int port,
1712
				      dsa_fdb_dump_cb_t *cb, void *data)
1713
{
1714
	struct mv88e6xxx_atu_entry addr;
1715
	bool is_static;
1716 1717
	int err;

1718
	addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1719
	eth_broadcast_addr(addr.mac);
1720 1721

	do {
1722
		mutex_lock(&chip->reg_lock);
1723
		err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
1724
		mutex_unlock(&chip->reg_lock);
1725
		if (err)
1726
			return err;
1727

1728
		if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED)
1729 1730
			break;

1731
		if (addr.trunk || (addr.portvec & BIT(port)) == 0)
1732 1733
			continue;

1734 1735
		if (!is_unicast_ether_addr(addr.mac))
			continue;
1736

1737 1738 1739
		is_static = (addr.state ==
			     MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
		err = cb(addr.mac, vid, is_static, data);
1740 1741
		if (err)
			return err;
1742 1743 1744 1745 1746
	} while (!is_broadcast_ether_addr(addr.mac));

	return err;
}

1747
static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
1748
				  dsa_fdb_dump_cb_t *cb, void *data)
1749
{
1750
	struct mv88e6xxx_vtu_entry vlan = {
1751
		.vid = chip->info->max_vid,
1752
	};
1753
	u16 fid;
1754 1755
	int err;

1756
	/* Dump port's default Filtering Information Database (VLAN ID 0) */
1757
	mutex_lock(&chip->reg_lock);
1758
	err = mv88e6xxx_port_get_fid(chip, port, &fid);
1759 1760
	mutex_unlock(&chip->reg_lock);

1761
	if (err)
1762
		return err;
1763

1764
	err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
1765
	if (err)
1766
		return err;
1767

1768
	/* Dump VLANs' Filtering Information Databases */
1769
	do {
1770
		mutex_lock(&chip->reg_lock);
1771
		err = mv88e6xxx_vtu_getnext(chip, &vlan);
1772
		mutex_unlock(&chip->reg_lock);
1773
		if (err)
1774
			return err;
1775 1776 1777 1778

		if (!vlan.valid)
			break;

1779
		err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
1780
						 cb, data);
1781
		if (err)
1782
			return err;
1783
	} while (vlan.vid < chip->info->max_vid);
1784

1785 1786 1787 1788
	return err;
}

static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
1789
				   dsa_fdb_dump_cb_t *cb, void *data)
1790
{
V
Vivien Didelot 已提交
1791
	struct mv88e6xxx_chip *chip = ds->priv;
1792

1793
	return mv88e6xxx_port_db_dump(chip, port, cb, data);
1794 1795
}

1796 1797
static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
				struct net_device *br)
1798
{
1799
	struct dsa_switch *ds;
1800
	int port;
1801
	int dev;
1802
	int err;
1803

1804 1805 1806 1807
	/* Remap the Port VLAN of each local bridge group member */
	for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
		if (chip->ds->ports[port].bridge_dev == br) {
			err = mv88e6xxx_port_vlan_map(chip, port);
1808
			if (err)
1809
				return err;
1810 1811 1812
		}
	}

1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830
	if (!mv88e6xxx_has_pvt(chip))
		return 0;

	/* Remap the Port VLAN of each cross-chip bridge group member */
	for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) {
		ds = chip->ds->dst->ds[dev];
		if (!ds)
			break;

		for (port = 0; port < ds->num_ports; ++port) {
			if (ds->ports[port].bridge_dev == br) {
				err = mv88e6xxx_pvt_map(chip, dev, port);
				if (err)
					return err;
			}
		}
	}

1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841
	return 0;
}

static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
				      struct net_device *br)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int err;

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_bridge_map(chip, br);
1842
	mutex_unlock(&chip->reg_lock);
1843

1844
	return err;
1845 1846
}

1847 1848
static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
					struct net_device *br)
1849
{
V
Vivien Didelot 已提交
1850
	struct mv88e6xxx_chip *chip = ds->priv;
1851

1852
	mutex_lock(&chip->reg_lock);
1853 1854 1855
	if (mv88e6xxx_bridge_map(chip, br) ||
	    mv88e6xxx_port_vlan_map(chip, port))
		dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
1856
	mutex_unlock(&chip->reg_lock);
1857 1858
}

1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888
static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
					   int port, struct net_device *br)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int err;

	if (!mv88e6xxx_has_pvt(chip))
		return 0;

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_pvt_map(chip, dev, port);
	mutex_unlock(&chip->reg_lock);

	return err;
}

static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
					     int port, struct net_device *br)
{
	struct mv88e6xxx_chip *chip = ds->priv;

	if (!mv88e6xxx_has_pvt(chip))
		return;

	mutex_lock(&chip->reg_lock);
	if (mv88e6xxx_pvt_map(chip, dev, port))
		dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
	mutex_unlock(&chip->reg_lock);
}

1889 1890 1891 1892 1893 1894 1895 1896
static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->reset)
		return chip->info->ops->reset(chip);

	return 0;
}

1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909
static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
{
	struct gpio_desc *gpiod = chip->reset;

	/* If there is a GPIO connected to the reset pin, toggle it */
	if (gpiod) {
		gpiod_set_value_cansleep(gpiod, 1);
		usleep_range(10000, 20000);
		gpiod_set_value_cansleep(gpiod, 0);
		usleep_range(10000, 20000);
	}
}

1910
static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
1911
{
1912
	int i, err;
1913

1914
	/* Set all ports to the Disabled state */
1915
	for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
1916
		err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
1917 1918
		if (err)
			return err;
1919 1920
	}

1921 1922 1923
	/* Wait for transmit queues to drain,
	 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
	 */
1924 1925
	usleep_range(2000, 4000);

1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936
	return 0;
}

static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
{
	int err;

	err = mv88e6xxx_disable_ports(chip);
	if (err)
		return err;

1937
	mv88e6xxx_hardware_reset(chip);
1938

1939
	return mv88e6xxx_software_reset(chip);
1940 1941
}

1942
static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
1943 1944
				   enum mv88e6xxx_frame_mode frame,
				   enum mv88e6xxx_egress_mode egress, u16 etype)
1945 1946 1947
{
	int err;

1948 1949 1950 1951
	if (!chip->info->ops->port_set_frame_mode)
		return -EOPNOTSUPP;

	err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
1952 1953 1954
	if (err)
		return err;

1955 1956 1957 1958 1959 1960 1961 1962
	err = chip->info->ops->port_set_frame_mode(chip, port, frame);
	if (err)
		return err;

	if (chip->info->ops->port_set_ether_type)
		return chip->info->ops->port_set_ether_type(chip, port, etype);

	return 0;
1963 1964
}

1965
static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
1966
{
1967
	return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
1968
				       MV88E6XXX_EGRESS_MODE_UNMODIFIED,
1969
				       MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
1970
}
1971

1972 1973 1974
static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
{
	return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
1975
				       MV88E6XXX_EGRESS_MODE_UNMODIFIED,
1976
				       MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
1977
}
1978

1979 1980 1981 1982
static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
{
	return mv88e6xxx_set_port_mode(chip, port,
				       MV88E6XXX_FRAME_MODE_ETHERTYPE,
1983 1984
				       MV88E6XXX_EGRESS_MODE_ETHERTYPE,
				       ETH_P_EDSA);
1985
}
1986

1987 1988 1989 1990
static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
{
	if (dsa_is_dsa_port(chip->ds, port))
		return mv88e6xxx_set_port_mode_dsa(chip, port);
1991

1992
	if (dsa_is_user_port(chip->ds, port))
1993
		return mv88e6xxx_set_port_mode_normal(chip, port);
1994

1995 1996 1997
	/* Setup CPU port mode depending on its supported tag format */
	if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
		return mv88e6xxx_set_port_mode_dsa(chip, port);
1998

1999 2000
	if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
		return mv88e6xxx_set_port_mode_edsa(chip, port);
2001

2002
	return -EINVAL;
2003 2004
}

2005
static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
2006
{
2007
	bool message = dsa_is_dsa_port(chip->ds, port);
2008

2009
	return mv88e6xxx_port_set_message_port(chip, port, message);
2010
}
2011

2012
static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
2013
{
2014 2015
	struct dsa_switch *ds = chip->ds;
	bool flood;
2016

2017
	/* Upstream ports flood frames with unknown unicast or multicast DA */
2018
	flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port);
2019 2020 2021
	if (chip->info->ops->port_set_egress_floods)
		return chip->info->ops->port_set_egress_floods(chip, port,
							       flood, flood);
2022

2023
	return 0;
2024 2025
}

2026 2027 2028
static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
				  bool on)
{
2029 2030
	if (chip->info->ops->serdes_power)
		return chip->info->ops->serdes_power(chip, port, on);
2031

2032
	return 0;
2033 2034
}

2035 2036 2037 2038 2039 2040
static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
{
	struct dsa_switch *ds = chip->ds;
	int upstream_port;
	int err;

2041
	upstream_port = dsa_upstream_port(ds, port);
2042 2043 2044 2045 2046 2047 2048
	if (chip->info->ops->port_set_upstream_port) {
		err = chip->info->ops->port_set_upstream_port(chip, port,
							      upstream_port);
		if (err)
			return err;
	}

2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064
	if (port == upstream_port) {
		if (chip->info->ops->set_cpu_port) {
			err = chip->info->ops->set_cpu_port(chip,
							    upstream_port);
			if (err)
				return err;
		}

		if (chip->info->ops->set_egress_port) {
			err = chip->info->ops->set_egress_port(chip,
							       upstream_port);
			if (err)
				return err;
		}
	}

2065 2066 2067
	return 0;
}

2068
static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2069
{
2070
	struct dsa_switch *ds = chip->ds;
2071
	int err;
2072
	u16 reg;
2073

2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087
	/* MAC Forcing register: don't force link, speed, duplex or flow control
	 * state to any particular values on physical ports, but force the CPU
	 * port and all DSA ports to their maximum bandwidth and full duplex.
	 */
	if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
		err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
					       SPEED_MAX, DUPLEX_FULL,
					       PHY_INTERFACE_MODE_NA);
	else
		err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
					       SPEED_UNFORCED, DUPLEX_UNFORCED,
					       PHY_INTERFACE_MODE_NA);
	if (err)
		return err;
2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102

	/* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
	 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
	 * tunneling, determine priority by looking at 802.1p and IP
	 * priority fields (IP prio has precedence), and set STP state
	 * to Forwarding.
	 *
	 * If this is the CPU link, use DSA or EDSA tagging depending
	 * on which tagging mode was configured.
	 *
	 * If this is a link to another switch, use DSA tagging mode.
	 *
	 * If this is the upstream port for this switch, enable
	 * forwarding of unknown unicasts and multicasts.
	 */
2103 2104 2105 2106
	reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
		MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
		MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
2107 2108
	if (err)
		return err;
2109

2110
	err = mv88e6xxx_setup_port_mode(chip, port);
2111 2112
	if (err)
		return err;
2113

2114
	err = mv88e6xxx_setup_egress_floods(chip, port);
2115 2116 2117
	if (err)
		return err;

2118 2119 2120
	/* Enable the SERDES interface for DSA and CPU ports. Normal
	 * ports SERDES are enabled when the port is enabled, thus
	 * saving a bit of power.
2121
	 */
2122 2123 2124 2125 2126
	if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) {
		err = mv88e6xxx_serdes_power(chip, port, true);
		if (err)
			return err;
	}
2127

2128
	/* Port Control 2: don't force a good FCS, set the maximum frame size to
2129
	 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2130 2131 2132
	 * untagged frames on this port, do a destination address lookup on all
	 * received packets as usual, disable ARP mirroring and don't send a
	 * copy of all transmitted/received frames on this port to the CPU.
2133
	 */
2134 2135 2136
	err = mv88e6xxx_port_set_map_da(chip, port);
	if (err)
		return err;
2137

2138 2139 2140
	err = mv88e6xxx_setup_upstream_port(chip, port);
	if (err)
		return err;
2141

2142
	err = mv88e6xxx_port_set_8021q_mode(chip, port,
2143
				MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
2144 2145 2146
	if (err)
		return err;

2147 2148
	if (chip->info->ops->port_set_jumbo_size) {
		err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
2149 2150 2151 2152
		if (err)
			return err;
	}

2153 2154 2155 2156 2157
	/* Port Association Vector: when learning source addresses
	 * of packets, add the address to the address database using
	 * a port bitmap that has only the bit for this port set and
	 * the other bits clear.
	 */
2158
	reg = 1 << port;
2159 2160
	/* Disable learning for CPU port */
	if (dsa_is_cpu_port(ds, port))
2161
		reg = 0;
2162

2163 2164
	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
				   reg);
2165 2166
	if (err)
		return err;
2167 2168

	/* Egress rate control 2: disable egress rate control. */
2169 2170
	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
				   0x0000);
2171 2172
	if (err)
		return err;
2173

2174 2175
	if (chip->info->ops->port_pause_limit) {
		err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
2176 2177
		if (err)
			return err;
2178
	}
2179

2180 2181 2182 2183 2184 2185
	if (chip->info->ops->port_disable_learn_limit) {
		err = chip->info->ops->port_disable_learn_limit(chip, port);
		if (err)
			return err;
	}

2186 2187
	if (chip->info->ops->port_disable_pri_override) {
		err = chip->info->ops->port_disable_pri_override(chip, port);
2188 2189
		if (err)
			return err;
2190
	}
2191

2192 2193
	if (chip->info->ops->port_tag_remap) {
		err = chip->info->ops->port_tag_remap(chip, port);
2194 2195
		if (err)
			return err;
2196 2197
	}

2198 2199
	if (chip->info->ops->port_egress_rate_limiting) {
		err = chip->info->ops->port_egress_rate_limiting(chip, port);
2200 2201
		if (err)
			return err;
2202 2203
	}

2204
	err = mv88e6xxx_setup_message_port(chip, port);
2205 2206
	if (err)
		return err;
2207

2208
	/* Port based VLAN map: give each port the same default address
2209 2210
	 * database, and allow bidirectional communication between the
	 * CPU and DSA port(s), and the other ports.
2211
	 */
2212
	err = mv88e6xxx_port_set_fid(chip, port, 0);
2213 2214
	if (err)
		return err;
2215

2216
	err = mv88e6xxx_port_vlan_map(chip, port);
2217 2218
	if (err)
		return err;
2219 2220 2221 2222

	/* Default VLAN ID and priority: don't set a default VLAN
	 * ID, and set the default packet priority to zero.
	 */
2223
	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
2224 2225
}

2226 2227 2228 2229
static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
				 struct phy_device *phydev)
{
	struct mv88e6xxx_chip *chip = ds->priv;
2230
	int err;
2231 2232

	mutex_lock(&chip->reg_lock);
2233
	err = mv88e6xxx_serdes_power(chip, port, true);
2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244
	mutex_unlock(&chip->reg_lock);

	return err;
}

static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port,
				   struct phy_device *phydev)
{
	struct mv88e6xxx_chip *chip = ds->priv;

	mutex_lock(&chip->reg_lock);
2245 2246
	if (mv88e6xxx_serdes_power(chip, port, false))
		dev_err(chip->dev, "failed to power off SERDES\n");
2247 2248 2249
	mutex_unlock(&chip->reg_lock);
}

2250 2251 2252
static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
				     unsigned int ageing_time)
{
V
Vivien Didelot 已提交
2253
	struct mv88e6xxx_chip *chip = ds->priv;
2254 2255 2256
	int err;

	mutex_lock(&chip->reg_lock);
2257
	err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2258 2259 2260 2261 2262
	mutex_unlock(&chip->reg_lock);

	return err;
}

2263
static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
2264
{
2265
	int err;
2266

2267
	/* Initialize the statistics unit */
2268 2269 2270 2271 2272
	if (chip->info->ops->stats_set_histogram) {
		err = chip->info->ops->stats_set_histogram(chip);
		if (err)
			return err;
	}
2273

2274
	return mv88e6xxx_g1_stats_clear(chip);
2275 2276
}

2277
static int mv88e6xxx_setup(struct dsa_switch *ds)
2278
{
V
Vivien Didelot 已提交
2279
	struct mv88e6xxx_chip *chip = ds->priv;
2280
	int err;
2281 2282
	int i;

2283
	chip->ds = ds;
2284
	ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
2285

2286
	mutex_lock(&chip->reg_lock);
2287

2288
	/* Setup Switch Port Registers */
2289
	for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2290 2291 2292
		if (dsa_is_unused_port(ds, i))
			continue;

2293 2294 2295 2296 2297
		err = mv88e6xxx_setup_port(chip, i);
		if (err)
			goto unlock;
	}

2298 2299 2300 2301
	err = mv88e6xxx_irl_setup(chip);
	if (err)
		goto unlock;

2302 2303 2304 2305
	err = mv88e6xxx_mac_setup(chip);
	if (err)
		goto unlock;

2306 2307 2308 2309
	err = mv88e6xxx_phy_setup(chip);
	if (err)
		goto unlock;

2310 2311 2312 2313
	err = mv88e6xxx_vtu_setup(chip);
	if (err)
		goto unlock;

2314 2315 2316 2317
	err = mv88e6xxx_pvt_setup(chip);
	if (err)
		goto unlock;

2318 2319 2320 2321
	err = mv88e6xxx_atu_setup(chip);
	if (err)
		goto unlock;

2322 2323 2324 2325
	err = mv88e6xxx_broadcast_setup(chip, 0);
	if (err)
		goto unlock;

2326 2327 2328 2329
	err = mv88e6xxx_pot_setup(chip);
	if (err)
		goto unlock;

2330 2331 2332 2333
	err = mv88e6xxx_rmu_setup(chip);
	if (err)
		goto unlock;

2334 2335 2336
	err = mv88e6xxx_rsvd2cpu_setup(chip);
	if (err)
		goto unlock;
2337

2338 2339 2340 2341
	err = mv88e6xxx_trunk_setup(chip);
	if (err)
		goto unlock;

2342 2343 2344 2345
	err = mv88e6xxx_devmap_setup(chip);
	if (err)
		goto unlock;

2346 2347 2348 2349
	err = mv88e6xxx_pri_setup(chip);
	if (err)
		goto unlock;

2350
	/* Setup PTP Hardware Clock and timestamping */
2351 2352 2353 2354
	if (chip->info->ptp_support) {
		err = mv88e6xxx_ptp_setup(chip);
		if (err)
			goto unlock;
2355 2356 2357 2358

		err = mv88e6xxx_hwtstamp_setup(chip);
		if (err)
			goto unlock;
2359 2360
	}

2361 2362 2363 2364
	err = mv88e6xxx_stats_setup(chip);
	if (err)
		goto unlock;

2365
unlock:
2366
	mutex_unlock(&chip->reg_lock);
2367

2368
	return err;
2369 2370
}

2371
static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
2372
{
2373 2374
	struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
	struct mv88e6xxx_chip *chip = mdio_bus->chip;
2375 2376
	u16 val;
	int err;
2377

2378 2379 2380
	if (!chip->info->ops->phy_read)
		return -EOPNOTSUPP;

2381
	mutex_lock(&chip->reg_lock);
2382
	err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
2383
	mutex_unlock(&chip->reg_lock);
2384

2385 2386 2387 2388 2389
	if (reg == MII_PHYSID2) {
		/* Some internal PHYS don't have a model number.  Use
		 * the mv88e6390 family model number instead.
		 */
		if (!(val & 0x3f0))
2390
			val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
2391 2392
	}

2393
	return err ? err : val;
2394 2395
}

2396
static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
2397
{
2398 2399
	struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
	struct mv88e6xxx_chip *chip = mdio_bus->chip;
2400
	int err;
2401

2402 2403 2404
	if (!chip->info->ops->phy_write)
		return -EOPNOTSUPP;

2405
	mutex_lock(&chip->reg_lock);
2406
	err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
2407
	mutex_unlock(&chip->reg_lock);
2408 2409

	return err;
2410 2411
}

2412
static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
2413 2414
				   struct device_node *np,
				   bool external)
2415 2416
{
	static int index;
2417
	struct mv88e6xxx_mdio_bus *mdio_bus;
2418 2419 2420
	struct mii_bus *bus;
	int err;

2421 2422 2423 2424 2425 2426 2427 2428 2429
	if (external) {
		mutex_lock(&chip->reg_lock);
		err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
		mutex_unlock(&chip->reg_lock);

		if (err)
			return err;
	}

2430
	bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
2431 2432 2433
	if (!bus)
		return -ENOMEM;

2434
	mdio_bus = bus->priv;
2435
	mdio_bus->bus = bus;
2436
	mdio_bus->chip = chip;
2437 2438
	INIT_LIST_HEAD(&mdio_bus->list);
	mdio_bus->external = external;
2439

2440 2441
	if (np) {
		bus->name = np->full_name;
2442
		snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
2443 2444 2445 2446 2447 2448 2449
	} else {
		bus->name = "mv88e6xxx SMI";
		snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
	}

	bus->read = mv88e6xxx_mdio_read;
	bus->write = mv88e6xxx_mdio_write;
2450
	bus->parent = chip->dev;
2451

2452 2453 2454 2455 2456 2457
	if (!external) {
		err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
		if (err)
			return err;
	}

2458
	err = of_mdiobus_register(bus, np);
2459
	if (err) {
2460
		dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
2461
		mv88e6xxx_g2_irq_mdio_free(chip, bus);
2462
		return err;
2463
	}
2464 2465 2466 2467 2468

	if (external)
		list_add_tail(&mdio_bus->list, &chip->mdios);
	else
		list_add(&mdio_bus->list, &chip->mdios);
2469 2470

	return 0;
2471
}
2472

2473 2474 2475 2476 2477
static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
	{ .compatible = "marvell,mv88e6xxx-mdio-external",
	  .data = (void *)true },
	{ },
};
2478

2479 2480 2481 2482 2483 2484 2485 2486 2487
static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)

{
	struct mv88e6xxx_mdio_bus *mdio_bus;
	struct mii_bus *bus;

	list_for_each_entry(mdio_bus, &chip->mdios, list) {
		bus = mdio_bus->bus;

2488 2489 2490
		if (!mdio_bus->external)
			mv88e6xxx_g2_irq_mdio_free(chip, bus);

2491 2492 2493 2494
		mdiobus_unregister(bus);
	}
}

2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518
static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
				    struct device_node *np)
{
	const struct of_device_id *match;
	struct device_node *child;
	int err;

	/* Always register one mdio bus for the internal/default mdio
	 * bus. This maybe represented in the device tree, but is
	 * optional.
	 */
	child = of_get_child_by_name(np, "mdio");
	err = mv88e6xxx_mdio_register(chip, child, false);
	if (err)
		return err;

	/* Walk the device tree, and see if there are any other nodes
	 * which say they are compatible with the external mdio
	 * bus.
	 */
	for_each_available_child_of_node(np, child) {
		match = of_match_node(mv88e6xxx_mdio_external_match, child);
		if (match) {
			err = mv88e6xxx_mdio_register(chip, child, true);
2519 2520
			if (err) {
				mv88e6xxx_mdios_unregister(chip);
2521
				return err;
2522
			}
2523 2524 2525 2526
		}
	}

	return 0;
2527 2528
}

2529 2530
static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
{
V
Vivien Didelot 已提交
2531
	struct mv88e6xxx_chip *chip = ds->priv;
2532 2533 2534 2535 2536 2537 2538

	return chip->eeprom_len;
}

static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
				struct ethtool_eeprom *eeprom, u8 *data)
{
V
Vivien Didelot 已提交
2539
	struct mv88e6xxx_chip *chip = ds->priv;
2540 2541
	int err;

2542 2543
	if (!chip->info->ops->get_eeprom)
		return -EOPNOTSUPP;
2544

2545 2546
	mutex_lock(&chip->reg_lock);
	err = chip->info->ops->get_eeprom(chip, eeprom, data);
2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559
	mutex_unlock(&chip->reg_lock);

	if (err)
		return err;

	eeprom->magic = 0xc3ec4951;

	return 0;
}

static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
				struct ethtool_eeprom *eeprom, u8 *data)
{
V
Vivien Didelot 已提交
2560
	struct mv88e6xxx_chip *chip = ds->priv;
2561 2562
	int err;

2563 2564 2565
	if (!chip->info->ops->set_eeprom)
		return -EOPNOTSUPP;

2566 2567 2568 2569
	if (eeprom->magic != 0xc3ec4951)
		return -EINVAL;

	mutex_lock(&chip->reg_lock);
2570
	err = chip->info->ops->set_eeprom(chip, eeprom, data);
2571 2572 2573 2574 2575
	mutex_unlock(&chip->reg_lock);

	return err;
}

2576
static const struct mv88e6xxx_ops mv88e6085_ops = {
2577
	/* MV88E6XXX_FAMILY_6097 */
2578 2579
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2580
	.irl_init_all = mv88e6352_g2_irl_init_all,
2581
	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2582 2583
	.phy_read = mv88e6185_phy_ppu_read,
	.phy_write = mv88e6185_phy_ppu_write,
2584
	.port_set_link = mv88e6xxx_port_set_link,
2585
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2586
	.port_set_speed = mv88e6185_port_set_speed,
2587
	.port_tag_remap = mv88e6095_port_tag_remap,
2588
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2589
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2590
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2591
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2592
	.port_pause_limit = mv88e6097_port_pause_limit,
2593
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2594
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2595
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2596
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2597 2598
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2599
	.stats_get_stats = mv88e6095_stats_get_stats,
2600 2601
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2602
	.watchdog_ops = &mv88e6097_watchdog_ops,
2603
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2604
	.pot_clear = mv88e6xxx_g2_pot_clear,
2605 2606
	.ppu_enable = mv88e6185_g1_ppu_enable,
	.ppu_disable = mv88e6185_g1_ppu_disable,
2607
	.reset = mv88e6185_g1_reset,
2608
	.rmu_disable = mv88e6085_g1_rmu_disable,
2609
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2610
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2611
	.serdes_power = mv88e6341_serdes_power,
2612 2613 2614
};

static const struct mv88e6xxx_ops mv88e6095_ops = {
2615
	/* MV88E6XXX_FAMILY_6095 */
2616 2617
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2618
	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2619 2620
	.phy_read = mv88e6185_phy_ppu_read,
	.phy_write = mv88e6185_phy_ppu_write,
2621
	.port_set_link = mv88e6xxx_port_set_link,
2622
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2623
	.port_set_speed = mv88e6185_port_set_speed,
2624
	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
2625
	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
2626
	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
2627
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2628
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2629 2630
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2631
	.stats_get_stats = mv88e6095_stats_get_stats,
2632
	.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2633 2634
	.ppu_enable = mv88e6185_g1_ppu_enable,
	.ppu_disable = mv88e6185_g1_ppu_disable,
2635
	.reset = mv88e6185_g1_reset,
2636
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
2637
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2638 2639
};

2640
static const struct mv88e6xxx_ops mv88e6097_ops = {
2641
	/* MV88E6XXX_FAMILY_6097 */
2642 2643
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2644
	.irl_init_all = mv88e6352_g2_irl_init_all,
2645 2646 2647 2648 2649 2650
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_speed = mv88e6185_port_set_speed,
2651
	.port_tag_remap = mv88e6095_port_tag_remap,
2652
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2653
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2654
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2655
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2656
	.port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2657
	.port_pause_limit = mv88e6097_port_pause_limit,
2658
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2659
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2660
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2661
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2662 2663 2664
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
	.stats_get_stats = mv88e6095_stats_get_stats,
2665 2666
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2667
	.watchdog_ops = &mv88e6097_watchdog_ops,
2668
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2669
	.pot_clear = mv88e6xxx_g2_pot_clear,
2670
	.reset = mv88e6352_g1_reset,
2671
	.rmu_disable = mv88e6085_g1_rmu_disable,
2672
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2673
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2674 2675
};

2676
static const struct mv88e6xxx_ops mv88e6123_ops = {
2677
	/* MV88E6XXX_FAMILY_6165 */
2678 2679
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2680
	.irl_init_all = mv88e6352_g2_irl_init_all,
2681
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2682 2683
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2684
	.port_set_link = mv88e6xxx_port_set_link,
2685
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2686
	.port_set_speed = mv88e6185_port_set_speed,
2687
	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
2688
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2689
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2690
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2691
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2692
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2693 2694
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2695
	.stats_get_stats = mv88e6095_stats_get_stats,
2696 2697
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2698
	.watchdog_ops = &mv88e6097_watchdog_ops,
2699
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2700
	.pot_clear = mv88e6xxx_g2_pot_clear,
2701
	.reset = mv88e6352_g1_reset,
2702
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2703
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2704 2705 2706
};

static const struct mv88e6xxx_ops mv88e6131_ops = {
2707
	/* MV88E6XXX_FAMILY_6185 */
2708 2709
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2710
	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2711 2712
	.phy_read = mv88e6185_phy_ppu_read,
	.phy_write = mv88e6185_phy_ppu_write,
2713
	.port_set_link = mv88e6xxx_port_set_link,
2714
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2715
	.port_set_speed = mv88e6185_port_set_speed,
2716
	.port_tag_remap = mv88e6095_port_tag_remap,
2717
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2718
	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
2719
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2720
	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
2721
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2722
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2723
	.port_pause_limit = mv88e6097_port_pause_limit,
2724
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2725
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2726 2727
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2728
	.stats_get_stats = mv88e6095_stats_get_stats,
2729 2730
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2731
	.watchdog_ops = &mv88e6097_watchdog_ops,
2732
	.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2733
	.ppu_enable = mv88e6185_g1_ppu_enable,
2734
	.set_cascade_port = mv88e6185_g1_set_cascade_port,
2735
	.ppu_disable = mv88e6185_g1_ppu_disable,
2736
	.reset = mv88e6185_g1_reset,
2737
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
2738
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2739 2740
};

2741 2742
static const struct mv88e6xxx_ops mv88e6141_ops = {
	/* MV88E6XXX_FAMILY_6341 */
2743 2744
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2745
	.irl_init_all = mv88e6352_g2_irl_init_all,
2746 2747 2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
	.port_tag_remap = mv88e6095_port_tag_remap,
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2759
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2760
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2761
	.port_pause_limit = mv88e6097_port_pause_limit,
2762 2763 2764
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
2765
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2766 2767 2768
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
	.stats_get_stats = mv88e6390_stats_get_stats,
2769 2770
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
2771 2772
	.watchdog_ops = &mv88e6390_watchdog_ops,
	.mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
2773
	.pot_clear = mv88e6xxx_g2_pot_clear,
2774
	.reset = mv88e6352_g1_reset,
2775
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2776
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2777
	.gpio_ops = &mv88e6352_gpio_ops,
2778 2779
};

2780
static const struct mv88e6xxx_ops mv88e6161_ops = {
2781
	/* MV88E6XXX_FAMILY_6165 */
2782 2783
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2784
	.irl_init_all = mv88e6352_g2_irl_init_all,
2785
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2786 2787
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2788
	.port_set_link = mv88e6xxx_port_set_link,
2789
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2790
	.port_set_speed = mv88e6185_port_set_speed,
2791
	.port_tag_remap = mv88e6095_port_tag_remap,
2792
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2793
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2794
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2795
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2796
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2797
	.port_pause_limit = mv88e6097_port_pause_limit,
2798
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2799
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2800
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2801
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2802 2803
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2804
	.stats_get_stats = mv88e6095_stats_get_stats,
2805 2806
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2807
	.watchdog_ops = &mv88e6097_watchdog_ops,
2808
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2809
	.pot_clear = mv88e6xxx_g2_pot_clear,
2810
	.reset = mv88e6352_g1_reset,
2811
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2812
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2813 2814 2815
};

static const struct mv88e6xxx_ops mv88e6165_ops = {
2816
	/* MV88E6XXX_FAMILY_6165 */
2817 2818
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2819
	.irl_init_all = mv88e6352_g2_irl_init_all,
2820
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2821 2822
	.phy_read = mv88e6165_phy_read,
	.phy_write = mv88e6165_phy_write,
2823
	.port_set_link = mv88e6xxx_port_set_link,
2824
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2825
	.port_set_speed = mv88e6185_port_set_speed,
2826
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2827
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2828
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2829
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2830 2831
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2832
	.stats_get_stats = mv88e6095_stats_get_stats,
2833 2834
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2835
	.watchdog_ops = &mv88e6097_watchdog_ops,
2836
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2837
	.pot_clear = mv88e6xxx_g2_pot_clear,
2838
	.reset = mv88e6352_g1_reset,
2839
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2840
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2841 2842 2843
};

static const struct mv88e6xxx_ops mv88e6171_ops = {
2844
	/* MV88E6XXX_FAMILY_6351 */
2845 2846
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2847
	.irl_init_all = mv88e6352_g2_irl_init_all,
2848
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2849 2850
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2851
	.port_set_link = mv88e6xxx_port_set_link,
2852
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2853
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2854
	.port_set_speed = mv88e6185_port_set_speed,
2855
	.port_tag_remap = mv88e6095_port_tag_remap,
2856
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2857
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2858
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2859
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2860
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2861
	.port_pause_limit = mv88e6097_port_pause_limit,
2862
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2863
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2864
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2865
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2866 2867
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2868
	.stats_get_stats = mv88e6095_stats_get_stats,
2869 2870
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2871
	.watchdog_ops = &mv88e6097_watchdog_ops,
2872
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2873
	.pot_clear = mv88e6xxx_g2_pot_clear,
2874
	.reset = mv88e6352_g1_reset,
2875
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2876
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2877 2878 2879
};

static const struct mv88e6xxx_ops mv88e6172_ops = {
2880
	/* MV88E6XXX_FAMILY_6352 */
2881 2882
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2883
	.irl_init_all = mv88e6352_g2_irl_init_all,
2884 2885
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
2886
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2887 2888
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2889
	.port_set_link = mv88e6xxx_port_set_link,
2890
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2891
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2892
	.port_set_speed = mv88e6352_port_set_speed,
2893
	.port_tag_remap = mv88e6095_port_tag_remap,
2894
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2895
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2896
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2897
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2898
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2899
	.port_pause_limit = mv88e6097_port_pause_limit,
2900
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2901
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2902
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2903
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2904 2905
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2906
	.stats_get_stats = mv88e6095_stats_get_stats,
2907 2908
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2909
	.watchdog_ops = &mv88e6097_watchdog_ops,
2910
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2911
	.pot_clear = mv88e6xxx_g2_pot_clear,
2912
	.reset = mv88e6352_g1_reset,
2913
	.rmu_disable = mv88e6352_g1_rmu_disable,
2914
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2915
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2916
	.serdes_power = mv88e6352_serdes_power,
2917
	.gpio_ops = &mv88e6352_gpio_ops,
2918 2919 2920
};

static const struct mv88e6xxx_ops mv88e6175_ops = {
2921
	/* MV88E6XXX_FAMILY_6351 */
2922 2923
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2924
	.irl_init_all = mv88e6352_g2_irl_init_all,
2925
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2926 2927
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2928
	.port_set_link = mv88e6xxx_port_set_link,
2929
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2930
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2931
	.port_set_speed = mv88e6185_port_set_speed,
2932
	.port_tag_remap = mv88e6095_port_tag_remap,
2933
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2934
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2935
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2936
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2937
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2938
	.port_pause_limit = mv88e6097_port_pause_limit,
2939
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2940
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2941
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2942
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2943 2944
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2945
	.stats_get_stats = mv88e6095_stats_get_stats,
2946 2947
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2948
	.watchdog_ops = &mv88e6097_watchdog_ops,
2949
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2950
	.pot_clear = mv88e6xxx_g2_pot_clear,
2951
	.reset = mv88e6352_g1_reset,
2952
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2953
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2954
	.serdes_power = mv88e6341_serdes_power,
2955 2956 2957
};

static const struct mv88e6xxx_ops mv88e6176_ops = {
2958
	/* MV88E6XXX_FAMILY_6352 */
2959 2960
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2961
	.irl_init_all = mv88e6352_g2_irl_init_all,
2962 2963
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
2964
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2965 2966
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2967
	.port_set_link = mv88e6xxx_port_set_link,
2968
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2969
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2970
	.port_set_speed = mv88e6352_port_set_speed,
2971
	.port_tag_remap = mv88e6095_port_tag_remap,
2972
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2973
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2974
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2975
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2976
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2977
	.port_pause_limit = mv88e6097_port_pause_limit,
2978
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2979
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2980
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2981
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2982 2983
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2984
	.stats_get_stats = mv88e6095_stats_get_stats,
2985 2986
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2987
	.watchdog_ops = &mv88e6097_watchdog_ops,
2988
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2989
	.pot_clear = mv88e6xxx_g2_pot_clear,
2990
	.reset = mv88e6352_g1_reset,
2991
	.rmu_disable = mv88e6352_g1_rmu_disable,
2992
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2993
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2994
	.serdes_power = mv88e6352_serdes_power,
2995
	.gpio_ops = &mv88e6352_gpio_ops,
2996 2997 2998
};

static const struct mv88e6xxx_ops mv88e6185_ops = {
2999
	/* MV88E6XXX_FAMILY_6185 */
3000 3001
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3002
	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3003 3004
	.phy_read = mv88e6185_phy_ppu_read,
	.phy_write = mv88e6185_phy_ppu_write,
3005
	.port_set_link = mv88e6xxx_port_set_link,
3006
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3007
	.port_set_speed = mv88e6185_port_set_speed,
3008
	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
3009
	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
3010
	.port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3011
	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
3012
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3013
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3014 3015
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
3016
	.stats_get_stats = mv88e6095_stats_get_stats,
3017 3018
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3019
	.watchdog_ops = &mv88e6097_watchdog_ops,
3020
	.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3021
	.set_cascade_port = mv88e6185_g1_set_cascade_port,
3022 3023
	.ppu_enable = mv88e6185_g1_ppu_enable,
	.ppu_disable = mv88e6185_g1_ppu_disable,
3024
	.reset = mv88e6185_g1_reset,
3025
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
3026
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3027 3028
};

3029
static const struct mv88e6xxx_ops mv88e6190_ops = {
3030
	/* MV88E6XXX_FAMILY_6390 */
3031
	.irl_init_all = mv88e6390_g2_irl_init_all,
3032 3033
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3034 3035 3036 3037 3038 3039 3040
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
3041
	.port_tag_remap = mv88e6390_port_tag_remap,
3042
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3043
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3044
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3045
	.port_pause_limit = mv88e6390_port_pause_limit,
3046
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3047
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3048
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3049
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3050 3051
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3052
	.stats_get_stats = mv88e6390_stats_get_stats,
3053 3054
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3055
	.watchdog_ops = &mv88e6390_watchdog_ops,
3056
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3057
	.pot_clear = mv88e6xxx_g2_pot_clear,
3058
	.reset = mv88e6352_g1_reset,
3059
	.rmu_disable = mv88e6390_g1_rmu_disable,
3060 3061
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3062
	.serdes_power = mv88e6390_serdes_power,
3063
	.gpio_ops = &mv88e6352_gpio_ops,
3064 3065 3066
};

static const struct mv88e6xxx_ops mv88e6190x_ops = {
3067
	/* MV88E6XXX_FAMILY_6390 */
3068
	.irl_init_all = mv88e6390_g2_irl_init_all,
3069 3070
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3071 3072 3073 3074 3075 3076 3077
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390x_port_set_speed,
3078
	.port_tag_remap = mv88e6390_port_tag_remap,
3079
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3080
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3081
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3082
	.port_pause_limit = mv88e6390_port_pause_limit,
3083
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3084
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3085
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3086
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3087 3088
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3089
	.stats_get_stats = mv88e6390_stats_get_stats,
3090 3091
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3092
	.watchdog_ops = &mv88e6390_watchdog_ops,
3093
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3094
	.pot_clear = mv88e6xxx_g2_pot_clear,
3095
	.reset = mv88e6352_g1_reset,
3096
	.rmu_disable = mv88e6390_g1_rmu_disable,
3097 3098
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3099
	.serdes_power = mv88e6390_serdes_power,
3100
	.gpio_ops = &mv88e6352_gpio_ops,
3101 3102 3103
};

static const struct mv88e6xxx_ops mv88e6191_ops = {
3104
	/* MV88E6XXX_FAMILY_6390 */
3105
	.irl_init_all = mv88e6390_g2_irl_init_all,
3106 3107
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3108 3109 3110 3111 3112 3113 3114
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
3115
	.port_tag_remap = mv88e6390_port_tag_remap,
3116
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3117
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3118
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3119
	.port_pause_limit = mv88e6390_port_pause_limit,
3120
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3121
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3122
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3123
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3124 3125
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3126
	.stats_get_stats = mv88e6390_stats_get_stats,
3127 3128
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3129
	.watchdog_ops = &mv88e6390_watchdog_ops,
3130
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3131
	.pot_clear = mv88e6xxx_g2_pot_clear,
3132
	.reset = mv88e6352_g1_reset,
3133
	.rmu_disable = mv88e6390_g1_rmu_disable,
3134 3135
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3136
	.serdes_power = mv88e6390_serdes_power,
3137 3138
};

3139
static const struct mv88e6xxx_ops mv88e6240_ops = {
3140
	/* MV88E6XXX_FAMILY_6352 */
3141 3142
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3143
	.irl_init_all = mv88e6352_g2_irl_init_all,
3144 3145
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
3146
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3147 3148
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3149
	.port_set_link = mv88e6xxx_port_set_link,
3150
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3151
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3152
	.port_set_speed = mv88e6352_port_set_speed,
3153
	.port_tag_remap = mv88e6095_port_tag_remap,
3154
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3155
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3156
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3157
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3158
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3159
	.port_pause_limit = mv88e6097_port_pause_limit,
3160
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3161
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3162
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3163
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3164 3165
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
3166
	.stats_get_stats = mv88e6095_stats_get_stats,
3167 3168
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3169
	.watchdog_ops = &mv88e6097_watchdog_ops,
3170
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3171
	.pot_clear = mv88e6xxx_g2_pot_clear,
3172
	.reset = mv88e6352_g1_reset,
3173
	.rmu_disable = mv88e6352_g1_rmu_disable,
3174
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3175
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3176
	.serdes_power = mv88e6352_serdes_power,
3177
	.gpio_ops = &mv88e6352_gpio_ops,
3178
	.avb_ops = &mv88e6352_avb_ops,
3179 3180
};

3181
static const struct mv88e6xxx_ops mv88e6290_ops = {
3182
	/* MV88E6XXX_FAMILY_6390 */
3183
	.irl_init_all = mv88e6390_g2_irl_init_all,
3184 3185
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3186 3187 3188 3189 3190 3191 3192
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
3193
	.port_tag_remap = mv88e6390_port_tag_remap,
3194
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3195
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3196
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3197
	.port_pause_limit = mv88e6390_port_pause_limit,
3198
	.port_set_cmode = mv88e6390x_port_set_cmode,
3199
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3200
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3201
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3202
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3203 3204
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3205
	.stats_get_stats = mv88e6390_stats_get_stats,
3206 3207
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3208
	.watchdog_ops = &mv88e6390_watchdog_ops,
3209
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3210
	.pot_clear = mv88e6xxx_g2_pot_clear,
3211
	.reset = mv88e6352_g1_reset,
3212
	.rmu_disable = mv88e6390_g1_rmu_disable,
3213 3214
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3215
	.serdes_power = mv88e6390_serdes_power,
3216
	.gpio_ops = &mv88e6352_gpio_ops,
3217
	.avb_ops = &mv88e6390_avb_ops,
3218 3219
};

3220
static const struct mv88e6xxx_ops mv88e6320_ops = {
3221
	/* MV88E6XXX_FAMILY_6320 */
3222 3223
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3224
	.irl_init_all = mv88e6352_g2_irl_init_all,
3225 3226
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
3227
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3228 3229
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3230
	.port_set_link = mv88e6xxx_port_set_link,
3231
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3232
	.port_set_speed = mv88e6185_port_set_speed,
3233
	.port_tag_remap = mv88e6095_port_tag_remap,
3234
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3235
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3236
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3237
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3238
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3239
	.port_pause_limit = mv88e6097_port_pause_limit,
3240
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3241
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3242
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3243
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3244 3245
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3246
	.stats_get_stats = mv88e6320_stats_get_stats,
3247 3248
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3249
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3250
	.pot_clear = mv88e6xxx_g2_pot_clear,
3251
	.reset = mv88e6352_g1_reset,
3252
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
3253
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3254
	.gpio_ops = &mv88e6352_gpio_ops,
3255
	.avb_ops = &mv88e6352_avb_ops,
3256 3257 3258
};

static const struct mv88e6xxx_ops mv88e6321_ops = {
3259
	/* MV88E6XXX_FAMILY_6320 */
3260 3261
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3262
	.irl_init_all = mv88e6352_g2_irl_init_all,
3263 3264
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
3265
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3266 3267
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3268
	.port_set_link = mv88e6xxx_port_set_link,
3269
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3270
	.port_set_speed = mv88e6185_port_set_speed,
3271
	.port_tag_remap = mv88e6095_port_tag_remap,
3272
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3273
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3274
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3275
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3276
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3277
	.port_pause_limit = mv88e6097_port_pause_limit,
3278
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3279
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3280
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3281
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3282 3283
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3284
	.stats_get_stats = mv88e6320_stats_get_stats,
3285 3286
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3287
	.reset = mv88e6352_g1_reset,
3288
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
3289
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3290
	.gpio_ops = &mv88e6352_gpio_ops,
3291
	.avb_ops = &mv88e6352_avb_ops,
3292 3293
};

3294 3295
static const struct mv88e6xxx_ops mv88e6341_ops = {
	/* MV88E6XXX_FAMILY_6341 */
3296 3297
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3298
	.irl_init_all = mv88e6352_g2_irl_init_all,
3299 3300 3301 3302 3303 3304 3305 3306 3307 3308 3309 3310 3311
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
	.port_tag_remap = mv88e6095_port_tag_remap,
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3312
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3313
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3314
	.port_pause_limit = mv88e6097_port_pause_limit,
3315 3316 3317
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3318
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3319 3320 3321
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
	.stats_get_stats = mv88e6390_stats_get_stats,
3322 3323
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3324 3325
	.watchdog_ops = &mv88e6390_watchdog_ops,
	.mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
3326
	.pot_clear = mv88e6xxx_g2_pot_clear,
3327
	.reset = mv88e6352_g1_reset,
3328
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3329
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3330
	.gpio_ops = &mv88e6352_gpio_ops,
3331
	.avb_ops = &mv88e6390_avb_ops,
3332 3333
};

3334
static const struct mv88e6xxx_ops mv88e6350_ops = {
3335
	/* MV88E6XXX_FAMILY_6351 */
3336 3337
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3338
	.irl_init_all = mv88e6352_g2_irl_init_all,
3339
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3340 3341
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3342
	.port_set_link = mv88e6xxx_port_set_link,
3343
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3344
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3345
	.port_set_speed = mv88e6185_port_set_speed,
3346
	.port_tag_remap = mv88e6095_port_tag_remap,
3347
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3348
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3349
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3350
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3351
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3352
	.port_pause_limit = mv88e6097_port_pause_limit,
3353
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3354
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3355
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3356
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3357 3358
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
3359
	.stats_get_stats = mv88e6095_stats_get_stats,
3360 3361
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3362
	.watchdog_ops = &mv88e6097_watchdog_ops,
3363
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3364
	.pot_clear = mv88e6xxx_g2_pot_clear,
3365
	.reset = mv88e6352_g1_reset,
3366
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3367
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3368 3369 3370
};

static const struct mv88e6xxx_ops mv88e6351_ops = {
3371
	/* MV88E6XXX_FAMILY_6351 */
3372 3373
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3374
	.irl_init_all = mv88e6352_g2_irl_init_all,
3375
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3376 3377
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3378
	.port_set_link = mv88e6xxx_port_set_link,
3379
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3380
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3381
	.port_set_speed = mv88e6185_port_set_speed,
3382
	.port_tag_remap = mv88e6095_port_tag_remap,
3383
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3384
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3385
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3386
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3387
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3388
	.port_pause_limit = mv88e6097_port_pause_limit,
3389
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3390
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3391
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3392
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3393 3394
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
3395
	.stats_get_stats = mv88e6095_stats_get_stats,
3396 3397
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3398
	.watchdog_ops = &mv88e6097_watchdog_ops,
3399
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3400
	.pot_clear = mv88e6xxx_g2_pot_clear,
3401
	.reset = mv88e6352_g1_reset,
3402
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3403
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3404
	.avb_ops = &mv88e6352_avb_ops,
3405 3406 3407
};

static const struct mv88e6xxx_ops mv88e6352_ops = {
3408
	/* MV88E6XXX_FAMILY_6352 */
3409 3410
	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3411
	.irl_init_all = mv88e6352_g2_irl_init_all,
3412 3413
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
3414
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3415 3416
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3417
	.port_set_link = mv88e6xxx_port_set_link,
3418
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3419
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3420
	.port_set_speed = mv88e6352_port_set_speed,
3421
	.port_tag_remap = mv88e6095_port_tag_remap,
3422
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3423
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3424
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3425
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3426
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3427
	.port_pause_limit = mv88e6097_port_pause_limit,
3428
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3429
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3430
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3431
	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3432 3433
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
3434
	.stats_get_stats = mv88e6095_stats_get_stats,
3435 3436
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3437
	.watchdog_ops = &mv88e6097_watchdog_ops,
3438
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3439
	.pot_clear = mv88e6xxx_g2_pot_clear,
3440
	.reset = mv88e6352_g1_reset,
3441
	.rmu_disable = mv88e6352_g1_rmu_disable,
3442
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3443
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3444
	.serdes_power = mv88e6352_serdes_power,
3445
	.gpio_ops = &mv88e6352_gpio_ops,
3446
	.avb_ops = &mv88e6352_avb_ops,
3447 3448 3449
	.serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
	.serdes_get_strings = mv88e6352_serdes_get_strings,
	.serdes_get_stats = mv88e6352_serdes_get_stats,
3450 3451
};

3452
static const struct mv88e6xxx_ops mv88e6390_ops = {
3453
	/* MV88E6XXX_FAMILY_6390 */
3454
	.irl_init_all = mv88e6390_g2_irl_init_all,
3455 3456
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3457 3458 3459 3460 3461 3462 3463
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
3464
	.port_tag_remap = mv88e6390_port_tag_remap,
3465
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3466
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3467
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3468
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3469
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3470
	.port_pause_limit = mv88e6390_port_pause_limit,
3471
	.port_set_cmode = mv88e6390x_port_set_cmode,
3472
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3473
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3474
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3475
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3476 3477
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3478
	.stats_get_stats = mv88e6390_stats_get_stats,
3479 3480
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3481
	.watchdog_ops = &mv88e6390_watchdog_ops,
3482
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3483
	.pot_clear = mv88e6xxx_g2_pot_clear,
3484
	.reset = mv88e6352_g1_reset,
3485
	.rmu_disable = mv88e6390_g1_rmu_disable,
3486 3487
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3488
	.serdes_power = mv88e6390_serdes_power,
3489
	.gpio_ops = &mv88e6352_gpio_ops,
3490
	.avb_ops = &mv88e6390_avb_ops,
3491 3492 3493
};

static const struct mv88e6xxx_ops mv88e6390x_ops = {
3494
	/* MV88E6XXX_FAMILY_6390 */
3495
	.irl_init_all = mv88e6390_g2_irl_init_all,
3496 3497
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3498 3499 3500 3501 3502 3503 3504
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390x_port_set_speed,
3505
	.port_tag_remap = mv88e6390_port_tag_remap,
3506
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3507
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3508
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3509
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3510
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3511
	.port_pause_limit = mv88e6390_port_pause_limit,
3512
	.port_set_cmode = mv88e6390x_port_set_cmode,
3513
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3514
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3515
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3516
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3517 3518
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3519
	.stats_get_stats = mv88e6390_stats_get_stats,
3520 3521
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3522
	.watchdog_ops = &mv88e6390_watchdog_ops,
3523
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3524
	.pot_clear = mv88e6xxx_g2_pot_clear,
3525
	.reset = mv88e6352_g1_reset,
3526
	.rmu_disable = mv88e6390_g1_rmu_disable,
3527 3528
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3529
	.serdes_power = mv88e6390_serdes_power,
3530
	.gpio_ops = &mv88e6352_gpio_ops,
3531
	.avb_ops = &mv88e6390_avb_ops,
3532 3533
};

3534 3535
static const struct mv88e6xxx_info mv88e6xxx_table[] = {
	[MV88E6085] = {
3536
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
3537 3538 3539 3540
		.family = MV88E6XXX_FAMILY_6097,
		.name = "Marvell 88E6085",
		.num_databases = 4096,
		.num_ports = 10,
3541
		.num_internal_phys = 5,
3542
		.max_vid = 4095,
3543
		.port_base_addr = 0x10,
3544
		.phy_base_addr = 0x0,
3545
		.global1_addr = 0x1b,
3546
		.global2_addr = 0x1c,
3547
		.age_time_coeff = 15000,
3548
		.g1_irqs = 8,
3549
		.g2_irqs = 10,
3550
		.atu_move_port_mask = 0xf,
3551
		.pvt = true,
3552
		.multi_chip = true,
3553
		.tag_protocol = DSA_TAG_PROTO_DSA,
3554
		.ops = &mv88e6085_ops,
3555 3556 3557
	},

	[MV88E6095] = {
3558
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
3559 3560 3561 3562
		.family = MV88E6XXX_FAMILY_6095,
		.name = "Marvell 88E6095/88E6095F",
		.num_databases = 256,
		.num_ports = 11,
3563
		.num_internal_phys = 0,
3564
		.max_vid = 4095,
3565
		.port_base_addr = 0x10,
3566
		.phy_base_addr = 0x0,
3567
		.global1_addr = 0x1b,
3568
		.global2_addr = 0x1c,
3569
		.age_time_coeff = 15000,
3570
		.g1_irqs = 8,
3571
		.atu_move_port_mask = 0xf,
3572
		.multi_chip = true,
3573
		.tag_protocol = DSA_TAG_PROTO_DSA,
3574
		.ops = &mv88e6095_ops,
3575 3576
	},

3577
	[MV88E6097] = {
3578
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
3579 3580 3581 3582
		.family = MV88E6XXX_FAMILY_6097,
		.name = "Marvell 88E6097/88E6097F",
		.num_databases = 4096,
		.num_ports = 11,
3583
		.num_internal_phys = 8,
3584
		.max_vid = 4095,
3585
		.port_base_addr = 0x10,
3586
		.phy_base_addr = 0x0,
3587
		.global1_addr = 0x1b,
3588
		.global2_addr = 0x1c,
3589
		.age_time_coeff = 15000,
3590
		.g1_irqs = 8,
3591
		.g2_irqs = 10,
3592
		.atu_move_port_mask = 0xf,
3593
		.pvt = true,
3594
		.multi_chip = true,
3595
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3596 3597 3598
		.ops = &mv88e6097_ops,
	},

3599
	[MV88E6123] = {
3600
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
3601 3602 3603 3604
		.family = MV88E6XXX_FAMILY_6165,
		.name = "Marvell 88E6123",
		.num_databases = 4096,
		.num_ports = 3,
3605
		.num_internal_phys = 5,
3606
		.max_vid = 4095,
3607
		.port_base_addr = 0x10,
3608
		.phy_base_addr = 0x0,
3609
		.global1_addr = 0x1b,
3610
		.global2_addr = 0x1c,
3611
		.age_time_coeff = 15000,
3612
		.g1_irqs = 9,
3613
		.g2_irqs = 10,
3614
		.atu_move_port_mask = 0xf,
3615
		.pvt = true,
3616
		.multi_chip = true,
3617
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3618
		.ops = &mv88e6123_ops,
3619 3620 3621
	},

	[MV88E6131] = {
3622
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
3623 3624 3625 3626
		.family = MV88E6XXX_FAMILY_6185,
		.name = "Marvell 88E6131",
		.num_databases = 256,
		.num_ports = 8,
3627
		.num_internal_phys = 0,
3628
		.max_vid = 4095,
3629
		.port_base_addr = 0x10,
3630
		.phy_base_addr = 0x0,
3631
		.global1_addr = 0x1b,
3632
		.global2_addr = 0x1c,
3633
		.age_time_coeff = 15000,
3634
		.g1_irqs = 9,
3635
		.atu_move_port_mask = 0xf,
3636
		.multi_chip = true,
3637
		.tag_protocol = DSA_TAG_PROTO_DSA,
3638
		.ops = &mv88e6131_ops,
3639 3640
	},

3641
	[MV88E6141] = {
3642
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
3643
		.family = MV88E6XXX_FAMILY_6341,
3644
		.name = "Marvell 88E6141",
3645 3646
		.num_databases = 4096,
		.num_ports = 6,
3647
		.num_internal_phys = 5,
3648
		.num_gpio = 11,
3649
		.max_vid = 4095,
3650
		.port_base_addr = 0x10,
3651
		.phy_base_addr = 0x10,
3652
		.global1_addr = 0x1b,
3653
		.global2_addr = 0x1c,
3654 3655
		.age_time_coeff = 3750,
		.atu_move_port_mask = 0x1f,
3656
		.g1_irqs = 9,
3657
		.g2_irqs = 10,
3658
		.pvt = true,
3659
		.multi_chip = true,
3660 3661 3662 3663
		.tag_protocol = DSA_TAG_PROTO_EDSA,
		.ops = &mv88e6141_ops,
	},

3664
	[MV88E6161] = {
3665
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
3666 3667 3668 3669
		.family = MV88E6XXX_FAMILY_6165,
		.name = "Marvell 88E6161",
		.num_databases = 4096,
		.num_ports = 6,
3670
		.num_internal_phys = 5,
3671
		.max_vid = 4095,
3672
		.port_base_addr = 0x10,
3673
		.phy_base_addr = 0x0,
3674
		.global1_addr = 0x1b,
3675
		.global2_addr = 0x1c,
3676
		.age_time_coeff = 15000,
3677
		.g1_irqs = 9,
3678
		.g2_irqs = 10,
3679
		.atu_move_port_mask = 0xf,
3680
		.pvt = true,
3681
		.multi_chip = true,
3682
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3683
		.ops = &mv88e6161_ops,
3684 3685 3686
	},

	[MV88E6165] = {
3687
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
3688 3689 3690 3691
		.family = MV88E6XXX_FAMILY_6165,
		.name = "Marvell 88E6165",
		.num_databases = 4096,
		.num_ports = 6,
3692
		.num_internal_phys = 0,
3693
		.max_vid = 4095,
3694
		.port_base_addr = 0x10,
3695
		.phy_base_addr = 0x0,
3696
		.global1_addr = 0x1b,
3697
		.global2_addr = 0x1c,
3698
		.age_time_coeff = 15000,
3699
		.g1_irqs = 9,
3700
		.g2_irqs = 10,
3701
		.atu_move_port_mask = 0xf,
3702
		.pvt = true,
3703
		.multi_chip = true,
3704
		.tag_protocol = DSA_TAG_PROTO_DSA,
3705
		.ops = &mv88e6165_ops,
3706 3707 3708
	},

	[MV88E6171] = {
3709
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
3710 3711 3712 3713
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6171",
		.num_databases = 4096,
		.num_ports = 7,
3714
		.num_internal_phys = 5,
3715
		.max_vid = 4095,
3716
		.port_base_addr = 0x10,
3717
		.phy_base_addr = 0x0,
3718
		.global1_addr = 0x1b,
3719
		.global2_addr = 0x1c,
3720
		.age_time_coeff = 15000,
3721
		.g1_irqs = 9,
3722
		.g2_irqs = 10,
3723
		.atu_move_port_mask = 0xf,
3724
		.pvt = true,
3725
		.multi_chip = true,
3726
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3727
		.ops = &mv88e6171_ops,
3728 3729 3730
	},

	[MV88E6172] = {
3731
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
3732 3733 3734 3735
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6172",
		.num_databases = 4096,
		.num_ports = 7,
3736
		.num_internal_phys = 5,
3737
		.num_gpio = 15,
3738
		.max_vid = 4095,
3739
		.port_base_addr = 0x10,
3740
		.phy_base_addr = 0x0,
3741
		.global1_addr = 0x1b,
3742
		.global2_addr = 0x1c,
3743
		.age_time_coeff = 15000,
3744
		.g1_irqs = 9,
3745
		.g2_irqs = 10,
3746
		.atu_move_port_mask = 0xf,
3747
		.pvt = true,
3748
		.multi_chip = true,
3749
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3750
		.ops = &mv88e6172_ops,
3751 3752 3753
	},

	[MV88E6175] = {
3754
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
3755 3756 3757 3758
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6175",
		.num_databases = 4096,
		.num_ports = 7,
3759
		.num_internal_phys = 5,
3760
		.max_vid = 4095,
3761
		.port_base_addr = 0x10,
3762
		.phy_base_addr = 0x0,
3763
		.global1_addr = 0x1b,
3764
		.global2_addr = 0x1c,
3765
		.age_time_coeff = 15000,
3766
		.g1_irqs = 9,
3767
		.g2_irqs = 10,
3768
		.atu_move_port_mask = 0xf,
3769
		.pvt = true,
3770
		.multi_chip = true,
3771
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3772
		.ops = &mv88e6175_ops,
3773 3774 3775
	},

	[MV88E6176] = {
3776
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
3777 3778 3779 3780
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6176",
		.num_databases = 4096,
		.num_ports = 7,
3781
		.num_internal_phys = 5,
3782
		.num_gpio = 15,
3783
		.max_vid = 4095,
3784
		.port_base_addr = 0x10,
3785
		.phy_base_addr = 0x0,
3786
		.global1_addr = 0x1b,
3787
		.global2_addr = 0x1c,
3788
		.age_time_coeff = 15000,
3789
		.g1_irqs = 9,
3790
		.g2_irqs = 10,
3791
		.atu_move_port_mask = 0xf,
3792
		.pvt = true,
3793
		.multi_chip = true,
3794
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3795
		.ops = &mv88e6176_ops,
3796 3797 3798
	},

	[MV88E6185] = {
3799
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
3800 3801 3802 3803
		.family = MV88E6XXX_FAMILY_6185,
		.name = "Marvell 88E6185",
		.num_databases = 256,
		.num_ports = 10,
3804
		.num_internal_phys = 0,
3805
		.max_vid = 4095,
3806
		.port_base_addr = 0x10,
3807
		.phy_base_addr = 0x0,
3808
		.global1_addr = 0x1b,
3809
		.global2_addr = 0x1c,
3810
		.age_time_coeff = 15000,
3811
		.g1_irqs = 8,
3812
		.atu_move_port_mask = 0xf,
3813
		.multi_chip = true,
3814
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3815
		.ops = &mv88e6185_ops,
3816 3817
	},

3818
	[MV88E6190] = {
3819
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
3820 3821 3822 3823
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6190",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3824
		.num_internal_phys = 11,
3825
		.num_gpio = 16,
3826
		.max_vid = 8191,
3827
		.port_base_addr = 0x0,
3828
		.phy_base_addr = 0x0,
3829
		.global1_addr = 0x1b,
3830
		.global2_addr = 0x1c,
3831
		.tag_protocol = DSA_TAG_PROTO_DSA,
3832
		.age_time_coeff = 3750,
3833
		.g1_irqs = 9,
3834
		.g2_irqs = 14,
3835
		.pvt = true,
3836
		.multi_chip = true,
3837
		.atu_move_port_mask = 0x1f,
3838 3839 3840 3841
		.ops = &mv88e6190_ops,
	},

	[MV88E6190X] = {
3842
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
3843 3844 3845 3846
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6190X",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3847
		.num_internal_phys = 11,
3848
		.num_gpio = 16,
3849
		.max_vid = 8191,
3850
		.port_base_addr = 0x0,
3851
		.phy_base_addr = 0x0,
3852
		.global1_addr = 0x1b,
3853
		.global2_addr = 0x1c,
3854
		.age_time_coeff = 3750,
3855
		.g1_irqs = 9,
3856
		.g2_irqs = 14,
3857
		.atu_move_port_mask = 0x1f,
3858
		.pvt = true,
3859
		.multi_chip = true,
3860
		.tag_protocol = DSA_TAG_PROTO_DSA,
3861 3862 3863 3864
		.ops = &mv88e6190x_ops,
	},

	[MV88E6191] = {
3865
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
3866 3867 3868 3869
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6191",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3870
		.num_internal_phys = 11,
3871
		.max_vid = 8191,
3872
		.port_base_addr = 0x0,
3873
		.phy_base_addr = 0x0,
3874
		.global1_addr = 0x1b,
3875
		.global2_addr = 0x1c,
3876
		.age_time_coeff = 3750,
3877
		.g1_irqs = 9,
3878
		.g2_irqs = 14,
3879
		.atu_move_port_mask = 0x1f,
3880
		.pvt = true,
3881
		.multi_chip = true,
3882
		.tag_protocol = DSA_TAG_PROTO_DSA,
3883
		.ptp_support = true,
3884
		.ops = &mv88e6191_ops,
3885 3886
	},

3887
	[MV88E6240] = {
3888
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
3889 3890 3891 3892
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6240",
		.num_databases = 4096,
		.num_ports = 7,
3893
		.num_internal_phys = 5,
3894
		.num_gpio = 15,
3895
		.max_vid = 4095,
3896
		.port_base_addr = 0x10,
3897
		.phy_base_addr = 0x0,
3898
		.global1_addr = 0x1b,
3899
		.global2_addr = 0x1c,
3900
		.age_time_coeff = 15000,
3901
		.g1_irqs = 9,
3902
		.g2_irqs = 10,
3903
		.atu_move_port_mask = 0xf,
3904
		.pvt = true,
3905
		.multi_chip = true,
3906
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3907
		.ptp_support = true,
3908
		.ops = &mv88e6240_ops,
3909 3910
	},

3911
	[MV88E6290] = {
3912
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
3913 3914 3915 3916
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6290",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3917
		.num_internal_phys = 11,
3918
		.num_gpio = 16,
3919
		.max_vid = 8191,
3920
		.port_base_addr = 0x0,
3921
		.phy_base_addr = 0x0,
3922
		.global1_addr = 0x1b,
3923
		.global2_addr = 0x1c,
3924
		.age_time_coeff = 3750,
3925
		.g1_irqs = 9,
3926
		.g2_irqs = 14,
3927
		.atu_move_port_mask = 0x1f,
3928
		.pvt = true,
3929
		.multi_chip = true,
3930
		.tag_protocol = DSA_TAG_PROTO_DSA,
3931
		.ptp_support = true,
3932 3933 3934
		.ops = &mv88e6290_ops,
	},

3935
	[MV88E6320] = {
3936
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
3937 3938 3939 3940
		.family = MV88E6XXX_FAMILY_6320,
		.name = "Marvell 88E6320",
		.num_databases = 4096,
		.num_ports = 7,
3941
		.num_internal_phys = 5,
3942
		.num_gpio = 15,
3943
		.max_vid = 4095,
3944
		.port_base_addr = 0x10,
3945
		.phy_base_addr = 0x0,
3946
		.global1_addr = 0x1b,
3947
		.global2_addr = 0x1c,
3948
		.age_time_coeff = 15000,
3949
		.g1_irqs = 8,
3950
		.g2_irqs = 10,
3951
		.atu_move_port_mask = 0xf,
3952
		.pvt = true,
3953
		.multi_chip = true,
3954
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3955
		.ptp_support = true,
3956
		.ops = &mv88e6320_ops,
3957 3958 3959
	},

	[MV88E6321] = {
3960
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
3961 3962 3963 3964
		.family = MV88E6XXX_FAMILY_6320,
		.name = "Marvell 88E6321",
		.num_databases = 4096,
		.num_ports = 7,
3965
		.num_internal_phys = 5,
3966
		.num_gpio = 15,
3967
		.max_vid = 4095,
3968
		.port_base_addr = 0x10,
3969
		.phy_base_addr = 0x0,
3970
		.global1_addr = 0x1b,
3971
		.global2_addr = 0x1c,
3972
		.age_time_coeff = 15000,
3973
		.g1_irqs = 8,
3974
		.g2_irqs = 10,
3975
		.atu_move_port_mask = 0xf,
3976
		.multi_chip = true,
3977
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3978
		.ptp_support = true,
3979
		.ops = &mv88e6321_ops,
3980 3981
	},

3982
	[MV88E6341] = {
3983
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3984 3985 3986
		.family = MV88E6XXX_FAMILY_6341,
		.name = "Marvell 88E6341",
		.num_databases = 4096,
3987
		.num_internal_phys = 5,
3988
		.num_ports = 6,
3989
		.num_gpio = 11,
3990
		.max_vid = 4095,
3991
		.port_base_addr = 0x10,
3992
		.phy_base_addr = 0x10,
3993
		.global1_addr = 0x1b,
3994
		.global2_addr = 0x1c,
3995
		.age_time_coeff = 3750,
3996
		.atu_move_port_mask = 0x1f,
3997
		.g1_irqs = 9,
3998
		.g2_irqs = 10,
3999
		.pvt = true,
4000
		.multi_chip = true,
4001
		.tag_protocol = DSA_TAG_PROTO_EDSA,
4002
		.ptp_support = true,
4003 4004 4005
		.ops = &mv88e6341_ops,
	},

4006
	[MV88E6350] = {
4007
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
4008 4009 4010 4011
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6350",
		.num_databases = 4096,
		.num_ports = 7,
4012
		.num_internal_phys = 5,
4013
		.max_vid = 4095,
4014
		.port_base_addr = 0x10,
4015
		.phy_base_addr = 0x0,
4016
		.global1_addr = 0x1b,
4017
		.global2_addr = 0x1c,
4018
		.age_time_coeff = 15000,
4019
		.g1_irqs = 9,
4020
		.g2_irqs = 10,
4021
		.atu_move_port_mask = 0xf,
4022
		.pvt = true,
4023
		.multi_chip = true,
4024
		.tag_protocol = DSA_TAG_PROTO_EDSA,
4025
		.ops = &mv88e6350_ops,
4026 4027 4028
	},

	[MV88E6351] = {
4029
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
4030 4031 4032 4033
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6351",
		.num_databases = 4096,
		.num_ports = 7,
4034
		.num_internal_phys = 5,
4035
		.max_vid = 4095,
4036
		.port_base_addr = 0x10,
4037
		.phy_base_addr = 0x0,
4038
		.global1_addr = 0x1b,
4039
		.global2_addr = 0x1c,
4040
		.age_time_coeff = 15000,
4041
		.g1_irqs = 9,
4042
		.g2_irqs = 10,
4043
		.atu_move_port_mask = 0xf,
4044
		.pvt = true,
4045
		.multi_chip = true,
4046
		.tag_protocol = DSA_TAG_PROTO_EDSA,
4047
		.ops = &mv88e6351_ops,
4048 4049 4050
	},

	[MV88E6352] = {
4051
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
4052 4053 4054 4055
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6352",
		.num_databases = 4096,
		.num_ports = 7,
4056
		.num_internal_phys = 5,
4057
		.num_gpio = 15,
4058
		.max_vid = 4095,
4059
		.port_base_addr = 0x10,
4060
		.phy_base_addr = 0x0,
4061
		.global1_addr = 0x1b,
4062
		.global2_addr = 0x1c,
4063
		.age_time_coeff = 15000,
4064
		.g1_irqs = 9,
4065
		.g2_irqs = 10,
4066
		.atu_move_port_mask = 0xf,
4067
		.pvt = true,
4068
		.multi_chip = true,
4069
		.tag_protocol = DSA_TAG_PROTO_EDSA,
4070
		.ptp_support = true,
4071
		.ops = &mv88e6352_ops,
4072
	},
4073
	[MV88E6390] = {
4074
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
4075 4076 4077 4078
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6390",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
4079
		.num_internal_phys = 11,
4080
		.num_gpio = 16,
4081
		.max_vid = 8191,
4082
		.port_base_addr = 0x0,
4083
		.phy_base_addr = 0x0,
4084
		.global1_addr = 0x1b,
4085
		.global2_addr = 0x1c,
4086
		.age_time_coeff = 3750,
4087
		.g1_irqs = 9,
4088
		.g2_irqs = 14,
4089
		.atu_move_port_mask = 0x1f,
4090
		.pvt = true,
4091
		.multi_chip = true,
4092
		.tag_protocol = DSA_TAG_PROTO_DSA,
4093
		.ptp_support = true,
4094 4095 4096
		.ops = &mv88e6390_ops,
	},
	[MV88E6390X] = {
4097
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
4098 4099 4100 4101
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6390X",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
4102
		.num_internal_phys = 11,
4103
		.num_gpio = 16,
4104
		.max_vid = 8191,
4105
		.port_base_addr = 0x0,
4106
		.phy_base_addr = 0x0,
4107
		.global1_addr = 0x1b,
4108
		.global2_addr = 0x1c,
4109
		.age_time_coeff = 3750,
4110
		.g1_irqs = 9,
4111
		.g2_irqs = 14,
4112
		.atu_move_port_mask = 0x1f,
4113
		.pvt = true,
4114
		.multi_chip = true,
4115
		.tag_protocol = DSA_TAG_PROTO_DSA,
4116
		.ptp_support = true,
4117 4118
		.ops = &mv88e6390x_ops,
	},
4119 4120
};

4121
static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
4122
{
4123
	int i;
4124

4125 4126 4127
	for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
		if (mv88e6xxx_table[i].prod_num == prod_num)
			return &mv88e6xxx_table[i];
4128 4129 4130 4131

	return NULL;
}

4132
static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
4133 4134
{
	const struct mv88e6xxx_info *info;
4135 4136 4137
	unsigned int prod_num, rev;
	u16 id;
	int err;
4138

4139
	mutex_lock(&chip->reg_lock);
4140
	err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
4141 4142 4143
	mutex_unlock(&chip->reg_lock);
	if (err)
		return err;
4144

4145 4146
	prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
	rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
4147 4148 4149 4150 4151

	info = mv88e6xxx_lookup_info(prod_num);
	if (!info)
		return -ENODEV;

4152
	/* Update the compatible info with the probed one */
4153
	chip->info = info;
4154

4155 4156 4157 4158
	err = mv88e6xxx_g2_require(chip);
	if (err)
		return err;

4159 4160
	dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
		 chip->info->prod_num, chip->info->name, rev);
4161 4162 4163 4164

	return 0;
}

4165
static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
4166
{
4167
	struct mv88e6xxx_chip *chip;
4168

4169 4170
	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
	if (!chip)
4171 4172
		return NULL;

4173
	chip->dev = dev;
4174

4175
	mutex_init(&chip->reg_lock);
4176
	INIT_LIST_HEAD(&chip->mdios);
4177

4178
	return chip;
4179 4180
}

4181
static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4182 4183
			      struct mii_bus *bus, int sw_addr)
{
4184
	if (sw_addr == 0)
4185
		chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
4186
	else if (chip->info->multi_chip)
4187
		chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
4188 4189 4190
	else
		return -EINVAL;

4191 4192
	chip->bus = bus;
	chip->sw_addr = sw_addr;
4193 4194 4195 4196

	return 0;
}

4197 4198
static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
							int port)
4199
{
V
Vivien Didelot 已提交
4200
	struct mv88e6xxx_chip *chip = ds->priv;
4201

4202
	return chip->info->tag_protocol;
4203 4204
}

4205
#if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
4206 4207 4208
static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
				       struct device *host_dev, int sw_addr,
				       void **priv)
4209
{
4210
	struct mv88e6xxx_chip *chip;
4211
	struct mii_bus *bus;
4212
	int err;
4213

4214
	bus = dsa_host_dev_to_mii_bus(host_dev);
4215 4216 4217
	if (!bus)
		return NULL;

4218 4219
	chip = mv88e6xxx_alloc_chip(dsa_dev);
	if (!chip)
4220 4221
		return NULL;

4222
	/* Legacy SMI probing will only support chips similar to 88E6085 */
4223
	chip->info = &mv88e6xxx_table[MV88E6085];
4224

4225
	err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4226 4227 4228
	if (err)
		goto free;

4229
	err = mv88e6xxx_detect(chip);
4230
	if (err)
4231
		goto free;
4232

4233 4234 4235 4236 4237 4238
	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_switch_reset(chip);
	mutex_unlock(&chip->reg_lock);
	if (err)
		goto free;

4239 4240
	mv88e6xxx_phy_init(chip);

4241
	err = mv88e6xxx_mdios_register(chip, NULL);
4242
	if (err)
4243
		goto free;
4244

4245
	*priv = chip;
4246

4247
	return chip->info->name;
4248
free:
4249
	devm_kfree(dsa_dev, chip);
4250 4251

	return NULL;
4252
}
4253
#endif
4254

4255
static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
4256
				      const struct switchdev_obj_port_mdb *mdb)
4257 4258 4259 4260 4261 4262 4263 4264 4265
{
	/* We don't need any dynamic resource from the kernel (yet),
	 * so skip the prepare phase.
	 */

	return 0;
}

static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
4266
				   const struct switchdev_obj_port_mdb *mdb)
4267
{
V
Vivien Didelot 已提交
4268
	struct mv88e6xxx_chip *chip = ds->priv;
4269 4270 4271

	mutex_lock(&chip->reg_lock);
	if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4272
					 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
4273 4274
		dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
			port);
4275 4276 4277 4278 4279 4280
	mutex_unlock(&chip->reg_lock);
}

static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
				  const struct switchdev_obj_port_mdb *mdb)
{
V
Vivien Didelot 已提交
4281
	struct mv88e6xxx_chip *chip = ds->priv;
4282 4283 4284 4285
	int err;

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4286
					   MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
4287 4288 4289 4290 4291
	mutex_unlock(&chip->reg_lock);

	return err;
}

4292
static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
4293
#if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
4294
	.probe			= mv88e6xxx_drv_probe,
4295
#endif
4296
	.get_tag_protocol	= mv88e6xxx_get_tag_protocol,
4297 4298
	.setup			= mv88e6xxx_setup,
	.adjust_link		= mv88e6xxx_adjust_link,
4299 4300 4301 4302 4303
	.phylink_validate	= mv88e6xxx_validate,
	.phylink_mac_link_state	= mv88e6xxx_link_state,
	.phylink_mac_config	= mv88e6xxx_mac_config,
	.phylink_mac_link_down	= mv88e6xxx_mac_link_down,
	.phylink_mac_link_up	= mv88e6xxx_mac_link_up,
4304 4305 4306
	.get_strings		= mv88e6xxx_get_strings,
	.get_ethtool_stats	= mv88e6xxx_get_ethtool_stats,
	.get_sset_count		= mv88e6xxx_get_sset_count,
4307 4308
	.port_enable		= mv88e6xxx_port_enable,
	.port_disable		= mv88e6xxx_port_disable,
V
Vivien Didelot 已提交
4309 4310
	.get_mac_eee		= mv88e6xxx_get_mac_eee,
	.set_mac_eee		= mv88e6xxx_set_mac_eee,
4311
	.get_eeprom_len		= mv88e6xxx_get_eeprom_len,
4312 4313 4314 4315
	.get_eeprom		= mv88e6xxx_get_eeprom,
	.set_eeprom		= mv88e6xxx_set_eeprom,
	.get_regs_len		= mv88e6xxx_get_regs_len,
	.get_regs		= mv88e6xxx_get_regs,
4316
	.set_ageing_time	= mv88e6xxx_set_ageing_time,
4317 4318 4319
	.port_bridge_join	= mv88e6xxx_port_bridge_join,
	.port_bridge_leave	= mv88e6xxx_port_bridge_leave,
	.port_stp_state_set	= mv88e6xxx_port_stp_state_set,
4320
	.port_fast_age		= mv88e6xxx_port_fast_age,
4321 4322 4323 4324 4325 4326 4327
	.port_vlan_filtering	= mv88e6xxx_port_vlan_filtering,
	.port_vlan_prepare	= mv88e6xxx_port_vlan_prepare,
	.port_vlan_add		= mv88e6xxx_port_vlan_add,
	.port_vlan_del		= mv88e6xxx_port_vlan_del,
	.port_fdb_add           = mv88e6xxx_port_fdb_add,
	.port_fdb_del           = mv88e6xxx_port_fdb_del,
	.port_fdb_dump          = mv88e6xxx_port_fdb_dump,
4328 4329 4330
	.port_mdb_prepare       = mv88e6xxx_port_mdb_prepare,
	.port_mdb_add           = mv88e6xxx_port_mdb_add,
	.port_mdb_del           = mv88e6xxx_port_mdb_del,
4331 4332
	.crosschip_bridge_join	= mv88e6xxx_crosschip_bridge_join,
	.crosschip_bridge_leave	= mv88e6xxx_crosschip_bridge_leave,
4333 4334 4335 4336 4337
	.port_hwtstamp_set	= mv88e6xxx_port_hwtstamp_set,
	.port_hwtstamp_get	= mv88e6xxx_port_hwtstamp_get,
	.port_txtstamp		= mv88e6xxx_port_txtstamp,
	.port_rxtstamp		= mv88e6xxx_port_rxtstamp,
	.get_ts_info		= mv88e6xxx_get_ts_info,
4338 4339
};

4340 4341 4342 4343
static struct dsa_switch_driver mv88e6xxx_switch_drv = {
	.ops			= &mv88e6xxx_switch_ops,
};

4344
static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
4345
{
4346
	struct device *dev = chip->dev;
4347 4348
	struct dsa_switch *ds;

4349
	ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip));
4350 4351 4352
	if (!ds)
		return -ENOMEM;

4353
	ds->priv = chip;
4354
	ds->dev = dev;
4355
	ds->ops = &mv88e6xxx_switch_ops;
4356 4357
	ds->ageing_time_min = chip->info->age_time_coeff;
	ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
4358 4359 4360

	dev_set_drvdata(dev, ds);

4361
	return dsa_register_switch(ds);
4362 4363
}

4364
static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
4365
{
4366
	dsa_unregister_switch(chip->ds);
4367 4368
}

4369 4370 4371 4372 4373 4374 4375 4376 4377 4378 4379 4380 4381
static const void *pdata_device_get_match_data(struct device *dev)
{
	const struct of_device_id *matches = dev->driver->of_match_table;
	const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;

	for (; matches->name[0] || matches->type[0] || matches->compatible[0];
	     matches++) {
		if (!strcmp(pdata->compatible, matches->compatible))
			return matches->data;
	}
	return NULL;
}

4382
static int mv88e6xxx_probe(struct mdio_device *mdiodev)
4383
{
4384
	struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
4385
	const struct mv88e6xxx_info *compat_info = NULL;
4386
	struct device *dev = &mdiodev->dev;
4387
	struct device_node *np = dev->of_node;
4388
	struct mv88e6xxx_chip *chip;
4389
	int port;
4390
	int err;
4391

4392 4393 4394
	if (!np && !pdata)
		return -EINVAL;

4395 4396 4397 4398 4399 4400 4401 4402 4403 4404 4405 4406 4407 4408 4409 4410 4411 4412 4413
	if (np)
		compat_info = of_device_get_match_data(dev);

	if (pdata) {
		compat_info = pdata_device_get_match_data(dev);

		if (!pdata->netdev)
			return -EINVAL;

		for (port = 0; port < DSA_MAX_PORTS; port++) {
			if (!(pdata->enabled_ports & (1 << port)))
				continue;
			if (strcmp(pdata->cd.port_names[port], "cpu"))
				continue;
			pdata->cd.netdev[port] = &pdata->netdev->dev;
			break;
		}
	}

4414 4415 4416
	if (!compat_info)
		return -EINVAL;

4417
	chip = mv88e6xxx_alloc_chip(dev);
4418 4419 4420 4421
	if (!chip) {
		err = -ENOMEM;
		goto out;
	}
4422

4423
	chip->info = compat_info;
4424

4425
	err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4426
	if (err)
4427
		goto out;
4428

4429
	chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4430 4431 4432 4433
	if (IS_ERR(chip->reset)) {
		err = PTR_ERR(chip->reset);
		goto out;
	}
4434

4435
	err = mv88e6xxx_detect(chip);
4436
	if (err)
4437
		goto out;
4438

4439 4440
	mv88e6xxx_phy_init(chip);

4441 4442 4443 4444 4445 4446 4447
	if (chip->info->ops->get_eeprom) {
		if (np)
			of_property_read_u32(np, "eeprom-length",
					     &chip->eeprom_len);
		else
			chip->eeprom_len = pdata->eeprom_len;
	}
4448

4449 4450 4451 4452 4453 4454 4455 4456 4457 4458 4459 4460
	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_switch_reset(chip);
	mutex_unlock(&chip->reg_lock);
	if (err)
		goto out;

	chip->irq = of_irq_get(np, 0);
	if (chip->irq == -EPROBE_DEFER) {
		err = chip->irq;
		goto out;
	}

4461
	/* Has to be performed before the MDIO bus is created, because
4462
	 * the PHYs will link their interrupts to these interrupt
4463 4464 4465 4466
	 * controllers
	 */
	mutex_lock(&chip->reg_lock);
	if (chip->irq > 0)
4467
		err = mv88e6xxx_g1_irq_setup(chip);
4468 4469 4470
	else
		err = mv88e6xxx_irq_poll_setup(chip);
	mutex_unlock(&chip->reg_lock);
4471

4472 4473
	if (err)
		goto out;
4474

4475 4476
	if (chip->info->g2_irqs > 0) {
		err = mv88e6xxx_g2_irq_setup(chip);
4477
		if (err)
4478
			goto out_g1_irq;
4479 4480
	}

4481 4482 4483 4484 4485 4486 4487 4488
	err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
	if (err)
		goto out_g2_irq;

	err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
	if (err)
		goto out_g1_atu_prob_irq;

4489
	err = mv88e6xxx_mdios_register(chip, np);
4490
	if (err)
4491
		goto out_g1_vtu_prob_irq;
4492

4493
	err = mv88e6xxx_register_switch(chip);
4494 4495
	if (err)
		goto out_mdio;
4496

4497
	return 0;
4498 4499

out_mdio:
4500
	mv88e6xxx_mdios_unregister(chip);
4501
out_g1_vtu_prob_irq:
4502
	mv88e6xxx_g1_vtu_prob_irq_free(chip);
4503
out_g1_atu_prob_irq:
4504
	mv88e6xxx_g1_atu_prob_irq_free(chip);
4505
out_g2_irq:
4506
	if (chip->info->g2_irqs > 0)
4507 4508
		mv88e6xxx_g2_irq_free(chip);
out_g1_irq:
4509 4510
	mutex_lock(&chip->reg_lock);
	if (chip->irq > 0)
4511
		mv88e6xxx_g1_irq_free(chip);
4512 4513 4514
	else
		mv88e6xxx_irq_poll_free(chip);
	mutex_unlock(&chip->reg_lock);
4515
out:
4516 4517 4518
	if (pdata)
		dev_put(pdata->netdev);

4519
	return err;
4520
}
4521 4522 4523 4524

static void mv88e6xxx_remove(struct mdio_device *mdiodev)
{
	struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
V
Vivien Didelot 已提交
4525
	struct mv88e6xxx_chip *chip = ds->priv;
4526

4527 4528
	if (chip->info->ptp_support) {
		mv88e6xxx_hwtstamp_free(chip);
4529
		mv88e6xxx_ptp_free(chip);
4530
	}
4531

4532
	mv88e6xxx_phy_destroy(chip);
4533
	mv88e6xxx_unregister_switch(chip);
4534
	mv88e6xxx_mdios_unregister(chip);
4535

4536 4537 4538 4539 4540 4541 4542 4543
	mv88e6xxx_g1_vtu_prob_irq_free(chip);
	mv88e6xxx_g1_atu_prob_irq_free(chip);

	if (chip->info->g2_irqs > 0)
		mv88e6xxx_g2_irq_free(chip);

	mutex_lock(&chip->reg_lock);
	if (chip->irq > 0)
4544
		mv88e6xxx_g1_irq_free(chip);
4545 4546 4547
	else
		mv88e6xxx_irq_poll_free(chip);
	mutex_unlock(&chip->reg_lock);
4548 4549 4550
}

static const struct of_device_id mv88e6xxx_of_match[] = {
4551 4552 4553 4554
	{
		.compatible = "marvell,mv88e6085",
		.data = &mv88e6xxx_table[MV88E6085],
	},
4555 4556 4557 4558
	{
		.compatible = "marvell,mv88e6190",
		.data = &mv88e6xxx_table[MV88E6190],
	},
4559 4560 4561 4562 4563 4564 4565 4566 4567 4568 4569 4570 4571 4572 4573 4574
	{ /* sentinel */ },
};

MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);

static struct mdio_driver mv88e6xxx_driver = {
	.probe	= mv88e6xxx_probe,
	.remove = mv88e6xxx_remove,
	.mdiodrv.driver = {
		.name = "mv88e6085",
		.of_match_table = mv88e6xxx_of_match,
	},
};

static int __init mv88e6xxx_init(void)
{
4575
	register_switch_driver(&mv88e6xxx_switch_drv);
4576 4577
	return mdio_driver_register(&mv88e6xxx_driver);
}
4578 4579 4580 4581
module_init(mv88e6xxx_init);

static void __exit mv88e6xxx_cleanup(void)
{
4582
	mdio_driver_unregister(&mv88e6xxx_driver);
4583
	unregister_switch_driver(&mv88e6xxx_switch_drv);
4584 4585
}
module_exit(mv88e6xxx_cleanup);
4586 4587 4588 4589

MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
MODULE_LICENSE("GPL");