chip.c 89.0 KB
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/*
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 * Marvell 88e6xxx Ethernet switch single-chip support
 *
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 * Copyright (c) 2008 Marvell Semiconductor
 *
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 * Copyright (c) 2015 CMC Electronics, Inc.
 *	Added support for VLAN Table Unit operations
 *
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 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
 *
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 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

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#include <linux/delay.h>
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#include <linux/etherdevice.h>
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#include <linux/ethtool.h>
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#include <linux/if_bridge.h>
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#include <linux/jiffies.h>
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#include <linux/list.h>
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#include <linux/mdio.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_mdio.h>
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#include <linux/netdevice.h>
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#include <linux/gpio/consumer.h>
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#include <linux/phy.h>
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#include <net/dsa.h>
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#include <net/switchdev.h>
32

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#include "mv88e6xxx.h"
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#include "global1.h"
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#include "global2.h"
36

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static void assert_reg_lock(struct mv88e6xxx_chip *chip)
38
{
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	if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
		dev_err(chip->dev, "Switch registers lock not held!\n");
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		dump_stack();
	}
}

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/* The switch ADDR[4:1] configuration pins define the chip SMI device address
 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
 *
 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
 * is the only device connected to the SMI master. In this mode it responds to
 * all 32 possible SMI addresses, and thus maps directly the internal devices.
 *
 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
 * multiple devices to share the SMI interface. In this mode it responds to only
 * 2 registers, used to indirectly access the internal SMI devices.
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 */
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static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
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			      int addr, int reg, u16 *val)
{
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	if (!chip->smi_ops)
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		return -EOPNOTSUPP;

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	return chip->smi_ops->read(chip, addr, reg, val);
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}

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static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
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			       int addr, int reg, u16 val)
{
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	if (!chip->smi_ops)
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		return -EOPNOTSUPP;

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	return chip->smi_ops->write(chip, addr, reg, val);
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}

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static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
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					  int addr, int reg, u16 *val)
{
	int ret;

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	ret = mdiobus_read_nested(chip->bus, addr, reg);
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	if (ret < 0)
		return ret;

	*val = ret & 0xffff;

	return 0;
}

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static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
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					   int addr, int reg, u16 val)
{
	int ret;

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	ret = mdiobus_write_nested(chip->bus, addr, reg, val);
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	if (ret < 0)
		return ret;

	return 0;
}

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static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
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	.read = mv88e6xxx_smi_single_chip_read,
	.write = mv88e6xxx_smi_single_chip_write,
};

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static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
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{
	int ret;
	int i;

	for (i = 0; i < 16; i++) {
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		ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
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		if (ret < 0)
			return ret;

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		if ((ret & SMI_CMD_BUSY) == 0)
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			return 0;
	}

	return -ETIMEDOUT;
}

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static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
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					 int addr, int reg, u16 *val)
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{
	int ret;

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	/* Wait for the bus to become free. */
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	ret = mv88e6xxx_smi_multi_chip_wait(chip);
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	if (ret < 0)
		return ret;

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	/* Transmit the read command. */
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	ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
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				   SMI_CMD_OP_22_READ | (addr << 5) | reg);
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	if (ret < 0)
		return ret;

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	/* Wait for the read command to complete. */
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	ret = mv88e6xxx_smi_multi_chip_wait(chip);
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	if (ret < 0)
		return ret;

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	/* Read the data. */
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	ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
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	if (ret < 0)
		return ret;

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	*val = ret & 0xffff;
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	return 0;
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}

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static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
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					  int addr, int reg, u16 val)
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{
	int ret;

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	/* Wait for the bus to become free. */
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	ret = mv88e6xxx_smi_multi_chip_wait(chip);
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	if (ret < 0)
		return ret;

164
	/* Transmit the data to write. */
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	ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
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	if (ret < 0)
		return ret;

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	/* Transmit the write command. */
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	ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
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				   SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
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	if (ret < 0)
		return ret;

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	/* Wait for the write command to complete. */
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	ret = mv88e6xxx_smi_multi_chip_wait(chip);
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	if (ret < 0)
		return ret;

	return 0;
}

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static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
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	.read = mv88e6xxx_smi_multi_chip_read,
	.write = mv88e6xxx_smi_multi_chip_write,
};

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int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
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{
	int err;

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	assert_reg_lock(chip);
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194
	err = mv88e6xxx_smi_read(chip, addr, reg, val);
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	if (err)
		return err;

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	dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
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		addr, reg, *val);

	return 0;
}

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int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
205
{
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	int err;

208
	assert_reg_lock(chip);
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210
	err = mv88e6xxx_smi_write(chip, addr, reg, val);
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	if (err)
		return err;

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	dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
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		addr, reg, val);

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	return 0;
}

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static int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
			       u16 *val)
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{
	int addr = chip->info->port_base_addr + port;

	return mv88e6xxx_read(chip, addr, reg, val);
}

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static int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
				u16 val)
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{
	int addr = chip->info->port_base_addr + port;

	return mv88e6xxx_write(chip, addr, reg, val);
}

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static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
			      int reg, u16 *val)
{
	int addr = phy; /* PHY devices addresses start at 0x0 */

	if (!chip->phy_ops)
		return -EOPNOTSUPP;

	return chip->phy_ops->read(chip, addr, reg, val);
}

static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
			       int reg, u16 val)
{
	int addr = phy; /* PHY devices addresses start at 0x0 */

	if (!chip->phy_ops)
		return -EOPNOTSUPP;

	return chip->phy_ops->write(chip, addr, reg, val);
}

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static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
{
	if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
		return -EOPNOTSUPP;

	return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
}

static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
{
	int err;

	/* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
	err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
	if (unlikely(err)) {
		dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
			phy, err);
	}
}

static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
				   u8 page, int reg, u16 *val)
{
	int err;

	/* There is no paging for registers 22 */
	if (reg == PHY_PAGE)
		return -EINVAL;

	err = mv88e6xxx_phy_page_get(chip, phy, page);
	if (!err) {
		err = mv88e6xxx_phy_read(chip, phy, reg, val);
		mv88e6xxx_phy_page_put(chip, phy);
	}

	return err;
}

static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
				    u8 page, int reg, u16 val)
{
	int err;

	/* There is no paging for registers 22 */
	if (reg == PHY_PAGE)
		return -EINVAL;

	err = mv88e6xxx_phy_page_get(chip, phy, page);
	if (!err) {
		err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
		mv88e6xxx_phy_page_put(chip, phy);
	}

	return err;
}

static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
{
	return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
				       reg, val);
}

static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
{
	return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
					reg, val);
}

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int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
327
{
328
	int i;
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330
	for (i = 0; i < 16; i++) {
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		u16 val;
		int err;

		err = mv88e6xxx_read(chip, addr, reg, &val);
		if (err)
			return err;

		if (!(val & mask))
			return 0;

		usleep_range(1000, 2000);
	}

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	dev_err(chip->dev, "Timeout while waiting for switch\n");
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	return -ETIMEDOUT;
}

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/* Indirect write to single pointer-data register with an Update bit */
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int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
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{
	u16 val;
352
	int err;
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	/* Wait until the previous operation is completed */
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	err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
	if (err)
		return err;
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	/* Set the Update bit to trigger a write operation */
	val = BIT(15) | update;

	return mv88e6xxx_write(chip, addr, reg, val);
}

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static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
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{
	u16 val;
368
	int i, err;
369

370
	err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
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	if (err)
		return err;

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	err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL,
				 val & ~GLOBAL_CONTROL_PPU_ENABLE);
	if (err)
		return err;
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379
	for (i = 0; i < 16; i++) {
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		err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val);
		if (err)
			return err;
383

384
		usleep_range(1000, 2000);
385
		if ((val & GLOBAL_STATUS_PPU_MASK) != GLOBAL_STATUS_PPU_POLLING)
386
			return 0;
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	}

	return -ETIMEDOUT;
}

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static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
393
{
394 395
	u16 val;
	int i, err;
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397 398 399
	err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
	if (err)
		return err;
400

401 402
	err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL,
				 val | GLOBAL_CONTROL_PPU_ENABLE);
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	if (err)
		return err;
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406
	for (i = 0; i < 16; i++) {
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		err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val);
		if (err)
			return err;
410

411
		usleep_range(1000, 2000);
412
		if ((val & GLOBAL_STATUS_PPU_MASK) == GLOBAL_STATUS_PPU_POLLING)
413
			return 0;
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	}

	return -ETIMEDOUT;
}

static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
{
421
	struct mv88e6xxx_chip *chip;
422

423
	chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
424

425
	mutex_lock(&chip->reg_lock);
426

427 428 429 430
	if (mutex_trylock(&chip->ppu_mutex)) {
		if (mv88e6xxx_ppu_enable(chip) == 0)
			chip->ppu_disabled = 0;
		mutex_unlock(&chip->ppu_mutex);
431
	}
432

433
	mutex_unlock(&chip->reg_lock);
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}

static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
{
438
	struct mv88e6xxx_chip *chip = (void *)_ps;
439

440
	schedule_work(&chip->ppu_work);
441 442
}

443
static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
444 445 446
{
	int ret;

447
	mutex_lock(&chip->ppu_mutex);
448

449
	/* If the PHY polling unit is enabled, disable it so that
450 451 452 453
	 * we can access the PHY registers.  If it was already
	 * disabled, cancel the timer that is going to re-enable
	 * it.
	 */
454 455
	if (!chip->ppu_disabled) {
		ret = mv88e6xxx_ppu_disable(chip);
456
		if (ret < 0) {
457
			mutex_unlock(&chip->ppu_mutex);
458 459
			return ret;
		}
460
		chip->ppu_disabled = 1;
461
	} else {
462
		del_timer(&chip->ppu_timer);
463
		ret = 0;
464 465 466 467 468
	}

	return ret;
}

469
static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
470
{
471
	/* Schedule a timer to re-enable the PHY polling unit. */
472 473
	mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
	mutex_unlock(&chip->ppu_mutex);
474 475
}

476
static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
477
{
478 479 480 481 482
	mutex_init(&chip->ppu_mutex);
	INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
	init_timer(&chip->ppu_timer);
	chip->ppu_timer.data = (unsigned long)chip;
	chip->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
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}

485 486 487 488 489
static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip)
{
	del_timer_sync(&chip->ppu_timer);
}

490 491
static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip, int addr,
				  int reg, u16 *val)
492
{
493
	int err;
494

495 496 497
	err = mv88e6xxx_ppu_access_get(chip);
	if (!err) {
		err = mv88e6xxx_read(chip, addr, reg, val);
498
		mv88e6xxx_ppu_access_put(chip);
499 500
	}

501
	return err;
502 503
}

504 505
static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip, int addr,
				   int reg, u16 val)
506
{
507
	int err;
508

509 510 511
	err = mv88e6xxx_ppu_access_get(chip);
	if (!err) {
		err = mv88e6xxx_write(chip, addr, reg, val);
512
		mv88e6xxx_ppu_access_put(chip);
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	}

515
	return err;
516 517
}

518
static const struct mv88e6xxx_bus_ops mv88e6xxx_phy_ppu_ops = {
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	.read = mv88e6xxx_phy_ppu_read,
	.write = mv88e6xxx_phy_ppu_write,
};

523
static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip)
524
{
525
	return chip->info->family == MV88E6XXX_FAMILY_6065;
526 527
}

528
static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
529
{
530
	return chip->info->family == MV88E6XXX_FAMILY_6095;
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}

533
static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
534
{
535
	return chip->info->family == MV88E6XXX_FAMILY_6097;
536 537
}

538
static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
539
{
540
	return chip->info->family == MV88E6XXX_FAMILY_6165;
541 542
}

543
static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip)
544
{
545
	return chip->info->family == MV88E6XXX_FAMILY_6185;
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}

548
static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
549
{
550
	return chip->info->family == MV88E6XXX_FAMILY_6320;
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}

553
static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
554
{
555
	return chip->info->family == MV88E6XXX_FAMILY_6351;
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}

558
static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
559
{
560
	return chip->info->family == MV88E6XXX_FAMILY_6352;
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}

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/* We expect the switch to perform auto negotiation if there is a real
 * phy. However, in the case of a fixed link phy, we force the port
 * settings from the fixed link settings.
 */
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static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
				  struct phy_device *phydev)
569
{
V
Vivien Didelot 已提交
570
	struct mv88e6xxx_chip *chip = ds->priv;
571 572
	u16 reg;
	int err;
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	if (!phy_is_pseudo_fixed_link(phydev))
		return;

577
	mutex_lock(&chip->reg_lock);
578

579 580
	err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, &reg);
	if (err)
581 582
		goto out;

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	reg &= ~(PORT_PCS_CTRL_LINK_UP |
		 PORT_PCS_CTRL_FORCE_LINK |
		 PORT_PCS_CTRL_DUPLEX_FULL |
		 PORT_PCS_CTRL_FORCE_DUPLEX |
		 PORT_PCS_CTRL_UNFORCED);
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	reg |= PORT_PCS_CTRL_FORCE_LINK;
	if (phydev->link)
591
		reg |= PORT_PCS_CTRL_LINK_UP;
592

593
	if (mv88e6xxx_6065_family(chip) && phydev->speed > SPEED_100)
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		goto out;

	switch (phydev->speed) {
	case SPEED_1000:
		reg |= PORT_PCS_CTRL_1000;
		break;
	case SPEED_100:
		reg |= PORT_PCS_CTRL_100;
		break;
	case SPEED_10:
		reg |= PORT_PCS_CTRL_10;
		break;
	default:
		pr_info("Unknown speed");
		goto out;
	}

	reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
	if (phydev->duplex == DUPLEX_FULL)
		reg |= PORT_PCS_CTRL_DUPLEX_FULL;

615
	if ((mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip)) &&
616
	    (port >= mv88e6xxx_num_ports(chip) - 2)) {
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		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
			reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
			reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
			reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
				PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
	}
625
	mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
626 627

out:
628
	mutex_unlock(&chip->reg_lock);
629 630
}

631
static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip *chip)
632
{
633 634
	u16 val;
	int i, err;
635 636

	for (i = 0; i < 10; i++) {
637 638
		err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_OP, &val);
		if ((val & GLOBAL_STATS_OP_BUSY) == 0)
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			return 0;
	}

	return -ETIMEDOUT;
}

645
static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
646
{
647
	int err;
648

649
	if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
650 651
		port = (port + 1) << 5;

652
	/* Snapshot the hardware statistics counters for this port. */
653 654 655 656 657
	err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
				 GLOBAL_STATS_OP_CAPTURE_PORT |
				 GLOBAL_STATS_OP_HIST_RX_TX | port);
	if (err)
		return err;
658

659
	/* Wait for the snapshotting to complete. */
660
	return _mv88e6xxx_stats_wait(chip);
661 662
}

663
static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip *chip,
664
				  int stat, u32 *val)
665
{
666 667 668
	u32 value;
	u16 reg;
	int err;
669 670 671

	*val = 0;

672 673 674 675
	err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
				 GLOBAL_STATS_OP_READ_CAPTURED |
				 GLOBAL_STATS_OP_HIST_RX_TX | stat);
	if (err)
676 677
		return;

678 679
	err = _mv88e6xxx_stats_wait(chip);
	if (err)
680 681
		return;

682 683
	err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_COUNTER_32, &reg);
	if (err)
684 685
		return;

686
	value = reg << 16;
687

688 689
	err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_COUNTER_01, &reg);
	if (err)
690 691
		return;

692
	*val = value | reg;
693 694
}

695
static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754
	{ "in_good_octets",	8, 0x00, BANK0, },
	{ "in_bad_octets",	4, 0x02, BANK0, },
	{ "in_unicast",		4, 0x04, BANK0, },
	{ "in_broadcasts",	4, 0x06, BANK0, },
	{ "in_multicasts",	4, 0x07, BANK0, },
	{ "in_pause",		4, 0x16, BANK0, },
	{ "in_undersize",	4, 0x18, BANK0, },
	{ "in_fragments",	4, 0x19, BANK0, },
	{ "in_oversize",	4, 0x1a, BANK0, },
	{ "in_jabber",		4, 0x1b, BANK0, },
	{ "in_rx_error",	4, 0x1c, BANK0, },
	{ "in_fcs_error",	4, 0x1d, BANK0, },
	{ "out_octets",		8, 0x0e, BANK0, },
	{ "out_unicast",	4, 0x10, BANK0, },
	{ "out_broadcasts",	4, 0x13, BANK0, },
	{ "out_multicasts",	4, 0x12, BANK0, },
	{ "out_pause",		4, 0x15, BANK0, },
	{ "excessive",		4, 0x11, BANK0, },
	{ "collisions",		4, 0x1e, BANK0, },
	{ "deferred",		4, 0x05, BANK0, },
	{ "single",		4, 0x14, BANK0, },
	{ "multiple",		4, 0x17, BANK0, },
	{ "out_fcs_error",	4, 0x03, BANK0, },
	{ "late",		4, 0x1f, BANK0, },
	{ "hist_64bytes",	4, 0x08, BANK0, },
	{ "hist_65_127bytes",	4, 0x09, BANK0, },
	{ "hist_128_255bytes",	4, 0x0a, BANK0, },
	{ "hist_256_511bytes",	4, 0x0b, BANK0, },
	{ "hist_512_1023bytes", 4, 0x0c, BANK0, },
	{ "hist_1024_max_bytes", 4, 0x0d, BANK0, },
	{ "sw_in_discards",	4, 0x10, PORT, },
	{ "sw_in_filtered",	2, 0x12, PORT, },
	{ "sw_out_filtered",	2, 0x13, PORT, },
	{ "in_discards",	4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
	{ "in_filtered",	4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
	{ "in_accepted",	4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
	{ "in_bad_accepted",	4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
	{ "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
	{ "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
	{ "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
	{ "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
	{ "tcam_counter_0",	4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
	{ "tcam_counter_1",	4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
	{ "tcam_counter_2",	4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
	{ "tcam_counter_3",	4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
	{ "in_da_unknown",	4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
	{ "in_management",	4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
	{ "out_queue_0",	4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
	{ "out_queue_1",	4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
	{ "out_queue_2",	4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
	{ "out_queue_3",	4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
	{ "out_queue_4",	4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
	{ "out_queue_5",	4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
	{ "out_queue_6",	4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
	{ "out_queue_7",	4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
	{ "out_cut_through",	4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
	{ "out_octets_a",	4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
	{ "out_octets_b",	4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
	{ "out_management",	4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
755 756
};

757
static bool mv88e6xxx_has_stat(struct mv88e6xxx_chip *chip,
758
			       struct mv88e6xxx_hw_stat *stat)
759
{
760 761
	switch (stat->type) {
	case BANK0:
762
		return true;
763
	case BANK1:
764
		return mv88e6xxx_6320_family(chip);
765
	case PORT:
766 767 768 769 770 771
		return mv88e6xxx_6095_family(chip) ||
			mv88e6xxx_6185_family(chip) ||
			mv88e6xxx_6097_family(chip) ||
			mv88e6xxx_6165_family(chip) ||
			mv88e6xxx_6351_family(chip) ||
			mv88e6xxx_6352_family(chip);
772
	}
773
	return false;
774 775
}

776
static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
777
					    struct mv88e6xxx_hw_stat *s,
778 779 780 781
					    int port)
{
	u32 low;
	u32 high = 0;
782 783
	int err;
	u16 reg;
784 785
	u64 value;

786 787
	switch (s->type) {
	case PORT:
788 789
		err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
		if (err)
790 791
			return UINT64_MAX;

792
		low = reg;
793
		if (s->sizeof_stat == 4) {
794 795
			err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
			if (err)
796
				return UINT64_MAX;
797
			high = reg;
798
		}
799 800 801
		break;
	case BANK0:
	case BANK1:
802
		_mv88e6xxx_stats_read(chip, s->reg, &low);
803
		if (s->sizeof_stat == 8)
804
			_mv88e6xxx_stats_read(chip, s->reg + 1, &high);
805 806 807 808 809
	}
	value = (((u64)high) << 16) | low;
	return value;
}

810 811
static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
				  uint8_t *data)
812
{
V
Vivien Didelot 已提交
813
	struct mv88e6xxx_chip *chip = ds->priv;
814 815
	struct mv88e6xxx_hw_stat *stat;
	int i, j;
816

817 818
	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
		stat = &mv88e6xxx_hw_stats[i];
819
		if (mv88e6xxx_has_stat(chip, stat)) {
820 821 822 823
			memcpy(data + j * ETH_GSTRING_LEN, stat->string,
			       ETH_GSTRING_LEN);
			j++;
		}
824
	}
825 826
}

827
static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
828
{
V
Vivien Didelot 已提交
829
	struct mv88e6xxx_chip *chip = ds->priv;
830 831 832 833 834
	struct mv88e6xxx_hw_stat *stat;
	int i, j;

	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
		stat = &mv88e6xxx_hw_stats[i];
835
		if (mv88e6xxx_has_stat(chip, stat))
836 837 838
			j++;
	}
	return j;
839 840
}

841 842
static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
					uint64_t *data)
843
{
V
Vivien Didelot 已提交
844
	struct mv88e6xxx_chip *chip = ds->priv;
845 846 847 848
	struct mv88e6xxx_hw_stat *stat;
	int ret;
	int i, j;

849
	mutex_lock(&chip->reg_lock);
850

851
	ret = _mv88e6xxx_stats_snapshot(chip, port);
852
	if (ret < 0) {
853
		mutex_unlock(&chip->reg_lock);
854 855 856 857
		return;
	}
	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
		stat = &mv88e6xxx_hw_stats[i];
858 859
		if (mv88e6xxx_has_stat(chip, stat)) {
			data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port);
860 861 862 863
			j++;
		}
	}

864
	mutex_unlock(&chip->reg_lock);
865 866
}

867
static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
868 869 870 871
{
	return 32 * sizeof(u16);
}

872 873
static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
			       struct ethtool_regs *regs, void *_p)
874
{
V
Vivien Didelot 已提交
875
	struct mv88e6xxx_chip *chip = ds->priv;
876 877
	int err;
	u16 reg;
878 879 880 881 882 883 884
	u16 *p = _p;
	int i;

	regs->version = 0;

	memset(p, 0xff, 32 * sizeof(u16));

885
	mutex_lock(&chip->reg_lock);
886

887 888
	for (i = 0; i < 32; i++) {

889 890 891
		err = mv88e6xxx_port_read(chip, port, i, &reg);
		if (!err)
			p[i] = reg;
892
	}
893

894
	mutex_unlock(&chip->reg_lock);
895 896
}

897
static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
898
{
899
	return mv88e6xxx_g1_wait(chip, GLOBAL_ATU_OP, GLOBAL_ATU_OP_BUSY);
900 901
}

902 903
static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
			     struct ethtool_eee *e)
904
{
V
Vivien Didelot 已提交
905
	struct mv88e6xxx_chip *chip = ds->priv;
906 907
	u16 reg;
	int err;
908

909
	if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
910 911
		return -EOPNOTSUPP;

912
	mutex_lock(&chip->reg_lock);
913

914 915
	err = mv88e6xxx_phy_read(chip, port, 16, &reg);
	if (err)
916
		goto out;
917 918 919 920

	e->eee_enabled = !!(reg & 0x0200);
	e->tx_lpi_enabled = !!(reg & 0x0100);

921
	err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
922
	if (err)
923
		goto out;
924

925
	e->eee_active = !!(reg & PORT_STATUS_EEE);
926
out:
927
	mutex_unlock(&chip->reg_lock);
928 929

	return err;
930 931
}

932 933
static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
			     struct phy_device *phydev, struct ethtool_eee *e)
934
{
V
Vivien Didelot 已提交
935
	struct mv88e6xxx_chip *chip = ds->priv;
936 937
	u16 reg;
	int err;
938

939
	if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
940 941
		return -EOPNOTSUPP;

942
	mutex_lock(&chip->reg_lock);
943

944 945
	err = mv88e6xxx_phy_read(chip, port, 16, &reg);
	if (err)
946 947
		goto out;

948
	reg &= ~0x0300;
949 950 951 952 953
	if (e->eee_enabled)
		reg |= 0x0200;
	if (e->tx_lpi_enabled)
		reg |= 0x0100;

954
	err = mv88e6xxx_phy_write(chip, port, 16, reg);
955
out:
956
	mutex_unlock(&chip->reg_lock);
957

958
	return err;
959 960
}

961
static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
962
{
963 964
	u16 val;
	int err;
965

966
	if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_ATU_FID)) {
967 968 969
		err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_FID, fid);
		if (err)
			return err;
970
	} else if (mv88e6xxx_num_databases(chip) == 256) {
971
		/* ATU DBNum[7:4] are located in ATU Control 15:12 */
972 973 974
		err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
		if (err)
			return err;
975

976 977 978 979
		err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
					 (val & 0xfff) | ((fid << 8) & 0xf000));
		if (err)
			return err;
980 981 982

		/* ATU DBNum[3:0] are located in ATU Operation 3:0 */
		cmd |= fid & 0xf;
983 984
	}

985 986 987
	err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_OP, cmd);
	if (err)
		return err;
988

989
	return _mv88e6xxx_atu_wait(chip);
990 991
}

992
static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011
				     struct mv88e6xxx_atu_entry *entry)
{
	u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;

	if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
		unsigned int mask, shift;

		if (entry->trunk) {
			data |= GLOBAL_ATU_DATA_TRUNK;
			mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
			shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
		} else {
			mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
			shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
		}

		data |= (entry->portv_trunkid << shift) & mask;
	}

1012
	return mv88e6xxx_g1_write(chip, GLOBAL_ATU_DATA, data);
1013 1014
}

1015
static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
1016 1017
				     struct mv88e6xxx_atu_entry *entry,
				     bool static_too)
1018
{
1019 1020
	int op;
	int err;
1021

1022
	err = _mv88e6xxx_atu_wait(chip);
1023 1024
	if (err)
		return err;
1025

1026
	err = _mv88e6xxx_atu_data_write(chip, entry);
1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037
	if (err)
		return err;

	if (entry->fid) {
		op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
			GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
	} else {
		op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
			GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
	}

1038
	return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
1039 1040
}

1041
static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
1042
				u16 fid, bool static_too)
1043 1044 1045 1046 1047
{
	struct mv88e6xxx_atu_entry entry = {
		.fid = fid,
		.state = 0, /* EntryState bits must be 0 */
	};
1048

1049
	return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1050 1051
}

1052
static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
1053
			       int from_port, int to_port, bool static_too)
1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066
{
	struct mv88e6xxx_atu_entry entry = {
		.trunk = false,
		.fid = fid,
	};

	/* EntryState bits must be 0xF */
	entry.state = GLOBAL_ATU_DATA_STATE_MASK;

	/* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
	entry.portv_trunkid = (to_port & 0x0f) << 4;
	entry.portv_trunkid |= from_port & 0x0f;

1067
	return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1068 1069
}

1070
static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
1071
				 int port, bool static_too)
1072 1073
{
	/* Destination port 0xF means remove the entries */
1074
	return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
1075 1076
}

1077 1078 1079 1080 1081 1082 1083
static const char * const mv88e6xxx_port_state_names[] = {
	[PORT_CONTROL_STATE_DISABLED] = "Disabled",
	[PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
	[PORT_CONTROL_STATE_LEARNING] = "Learning",
	[PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
};

1084
static int _mv88e6xxx_port_state(struct mv88e6xxx_chip *chip, int port,
1085
				 u8 state)
1086
{
1087
	struct dsa_switch *ds = chip->ds;
1088 1089
	u16 reg;
	int err;
1090 1091
	u8 oldstate;

1092 1093 1094
	err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, &reg);
	if (err)
		return err;
1095

1096
	oldstate = reg & PORT_CONTROL_STATE_MASK;
1097

1098 1099
	reg &= ~PORT_CONTROL_STATE_MASK;
	reg |= state;
1100

1101 1102 1103
	err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
	if (err)
		return err;
1104

1105 1106 1107
	netdev_dbg(ds->ports[port].netdev, "PortState %s (was %s)\n",
		   mv88e6xxx_port_state_names[state],
		   mv88e6xxx_port_state_names[oldstate]);
1108

1109
	return 0;
1110 1111
}

1112
static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
1113
{
1114
	struct net_device *bridge = chip->ports[port].bridge_dev;
1115
	const u16 mask = (1 << mv88e6xxx_num_ports(chip)) - 1;
1116
	struct dsa_switch *ds = chip->ds;
1117
	u16 output_ports = 0;
1118 1119
	u16 reg;
	int err;
1120 1121 1122 1123 1124 1125
	int i;

	/* allow CPU port or DSA link(s) to send frames to every port */
	if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
		output_ports = mask;
	} else {
1126
		for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1127
			/* allow sending frames to every group member */
1128
			if (bridge && chip->ports[i].bridge_dev == bridge)
1129 1130 1131 1132 1133 1134 1135 1136 1137 1138
				output_ports |= BIT(i);

			/* allow sending frames to CPU port and DSA link(s) */
			if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
				output_ports |= BIT(i);
		}
	}

	/* prevent frames from going back out of the port they came in on */
	output_ports &= ~BIT(port);
1139

1140 1141 1142
	err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, &reg);
	if (err)
		return err;
1143

1144 1145
	reg &= ~mask;
	reg |= output_ports & mask;
1146

1147
	return mv88e6xxx_port_write(chip, port, PORT_BASE_VLAN, reg);
1148 1149
}

1150 1151
static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
					 u8 state)
1152
{
V
Vivien Didelot 已提交
1153
	struct mv88e6xxx_chip *chip = ds->priv;
1154
	int stp_state;
1155
	int err;
1156 1157 1158

	switch (state) {
	case BR_STATE_DISABLED:
1159
		stp_state = PORT_CONTROL_STATE_DISABLED;
1160 1161 1162
		break;
	case BR_STATE_BLOCKING:
	case BR_STATE_LISTENING:
1163
		stp_state = PORT_CONTROL_STATE_BLOCKING;
1164 1165
		break;
	case BR_STATE_LEARNING:
1166
		stp_state = PORT_CONTROL_STATE_LEARNING;
1167 1168 1169
		break;
	case BR_STATE_FORWARDING:
	default:
1170
		stp_state = PORT_CONTROL_STATE_FORWARDING;
1171 1172 1173
		break;
	}

1174 1175 1176
	mutex_lock(&chip->reg_lock);
	err = _mv88e6xxx_port_state(chip, port, stp_state);
	mutex_unlock(&chip->reg_lock);
1177 1178

	if (err)
1179 1180
		netdev_err(ds->ports[port].netdev,
			   "failed to update state to %s\n",
1181
			   mv88e6xxx_port_state_names[stp_state]);
1182 1183
}

1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196
static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int err;

	mutex_lock(&chip->reg_lock);
	err = _mv88e6xxx_atu_remove(chip, 0, port, false);
	mutex_unlock(&chip->reg_lock);

	if (err)
		netdev_err(ds->ports[port].netdev, "failed to flush ATU\n");
}

1197
static int _mv88e6xxx_port_pvid(struct mv88e6xxx_chip *chip, int port,
1198
				u16 *new, u16 *old)
1199
{
1200
	struct dsa_switch *ds = chip->ds;
1201 1202
	u16 pvid, reg;
	int err;
1203

1204 1205 1206
	err = mv88e6xxx_port_read(chip, port, PORT_DEFAULT_VLAN, &reg);
	if (err)
		return err;
1207

1208
	pvid = reg & PORT_DEFAULT_VLAN_MASK;
1209 1210

	if (new) {
1211 1212
		reg &= ~PORT_DEFAULT_VLAN_MASK;
		reg |= *new & PORT_DEFAULT_VLAN_MASK;
1213

1214 1215 1216
		err = mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, reg);
		if (err)
			return err;
1217

1218 1219
		netdev_dbg(ds->ports[port].netdev,
			   "DefaultVID %d (was %d)\n", *new, pvid);
1220 1221 1222 1223
	}

	if (old)
		*old = pvid;
1224 1225 1226 1227

	return 0;
}

1228
static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_chip *chip,
1229
				    int port, u16 *pvid)
1230
{
1231
	return _mv88e6xxx_port_pvid(chip, port, NULL, pvid);
1232 1233
}

1234
static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_chip *chip,
1235
				    int port, u16 pvid)
1236
{
1237
	return _mv88e6xxx_port_pvid(chip, port, &pvid, NULL);
1238 1239
}

1240
static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
1241
{
1242
	return mv88e6xxx_g1_wait(chip, GLOBAL_VTU_OP, GLOBAL_VTU_OP_BUSY);
1243 1244
}

1245
static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
1246
{
1247
	int err;
1248

1249 1250 1251
	err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_OP, op);
	if (err)
		return err;
1252

1253
	return _mv88e6xxx_vtu_wait(chip);
1254 1255
}

1256
static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
1257 1258 1259
{
	int ret;

1260
	ret = _mv88e6xxx_vtu_wait(chip);
1261 1262 1263
	if (ret < 0)
		return ret;

1264
	return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
1265 1266
}

1267
static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
1268
					struct mv88e6xxx_vtu_entry *entry,
1269 1270 1271
					unsigned int nibble_offset)
{
	u16 regs[3];
1272
	int i, err;
1273 1274

	for (i = 0; i < 3; ++i) {
1275
		u16 *reg = &regs[i];
1276

1277 1278 1279
		err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
		if (err)
			return err;
1280 1281
	}

1282
	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1283 1284 1285 1286 1287 1288 1289 1290 1291
		unsigned int shift = (i % 4) * 4 + nibble_offset;
		u16 reg = regs[i / 4];

		entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
	}

	return 0;
}

1292
static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
1293
				   struct mv88e6xxx_vtu_entry *entry)
1294
{
1295
	return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
1296 1297
}

1298
static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
1299
				   struct mv88e6xxx_vtu_entry *entry)
1300
{
1301
	return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
1302 1303
}

1304
static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
1305
					 struct mv88e6xxx_vtu_entry *entry,
1306 1307 1308
					 unsigned int nibble_offset)
{
	u16 regs[3] = { 0 };
1309
	int i, err;
1310

1311
	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1312 1313 1314 1315 1316 1317 1318
		unsigned int shift = (i % 4) * 4 + nibble_offset;
		u8 data = entry->data[i];

		regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
	}

	for (i = 0; i < 3; ++i) {
1319 1320 1321 1322 1323
		u16 reg = regs[i];

		err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
		if (err)
			return err;
1324 1325 1326 1327 1328
	}

	return 0;
}

1329
static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
1330
				    struct mv88e6xxx_vtu_entry *entry)
1331
{
1332
	return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
1333 1334
}

1335
static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
1336
				    struct mv88e6xxx_vtu_entry *entry)
1337
{
1338
	return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
1339 1340
}

1341
static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
1342
{
1343 1344
	return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID,
				  vid & GLOBAL_VTU_VID_MASK);
1345 1346
}

1347
static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1348
				  struct mv88e6xxx_vtu_entry *entry)
1349
{
1350
	struct mv88e6xxx_vtu_entry next = { 0 };
1351 1352
	u16 val;
	int err;
1353

1354 1355 1356
	err = _mv88e6xxx_vtu_wait(chip);
	if (err)
		return err;
1357

1358 1359 1360
	err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
	if (err)
		return err;
1361

1362 1363 1364
	err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
	if (err)
		return err;
1365

1366 1367
	next.vid = val & GLOBAL_VTU_VID_MASK;
	next.valid = !!(val & GLOBAL_VTU_VID_VALID);
1368 1369

	if (next.valid) {
1370 1371 1372
		err = mv88e6xxx_vtu_data_read(chip, &next);
		if (err)
			return err;
1373

1374
		if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
1375 1376 1377
			err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val);
			if (err)
				return err;
1378

1379
			next.fid = val & GLOBAL_VTU_FID_MASK;
1380
		} else if (mv88e6xxx_num_databases(chip) == 256) {
1381 1382 1383
			/* VTU DBNum[7:4] are located in VTU Operation 11:8, and
			 * VTU DBNum[3:0] are located in VTU Operation 3:0
			 */
1384 1385 1386
			err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val);
			if (err)
				return err;
1387

1388 1389
			next.fid = (val & 0xf00) >> 4;
			next.fid |= val & 0xf;
1390
		}
1391

1392
		if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1393 1394 1395
			err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
			if (err)
				return err;
1396

1397
			next.sid = val & GLOBAL_VTU_SID_MASK;
1398 1399 1400 1401 1402 1403 1404
		}
	}

	*entry = next;
	return 0;
}

1405 1406 1407
static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
				    struct switchdev_obj_port_vlan *vlan,
				    int (*cb)(struct switchdev_obj *obj))
1408
{
V
Vivien Didelot 已提交
1409
	struct mv88e6xxx_chip *chip = ds->priv;
1410
	struct mv88e6xxx_vtu_entry next;
1411 1412 1413
	u16 pvid;
	int err;

1414
	if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1415 1416
		return -EOPNOTSUPP;

1417
	mutex_lock(&chip->reg_lock);
1418

1419
	err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
1420 1421 1422
	if (err)
		goto unlock;

1423
	err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1424 1425 1426 1427
	if (err)
		goto unlock;

	do {
1428
		err = _mv88e6xxx_vtu_getnext(chip, &next);
1429 1430 1431 1432 1433 1434 1435 1436 1437 1438
		if (err)
			break;

		if (!next.valid)
			break;

		if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
			continue;

		/* reinit and dump this VLAN obj */
1439 1440
		vlan->vid_begin = next.vid;
		vlan->vid_end = next.vid;
1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454
		vlan->flags = 0;

		if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
			vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;

		if (next.vid == pvid)
			vlan->flags |= BRIDGE_VLAN_INFO_PVID;

		err = cb(&vlan->obj);
		if (err)
			break;
	} while (next.vid < GLOBAL_VTU_VID_MASK);

unlock:
1455
	mutex_unlock(&chip->reg_lock);
1456 1457 1458 1459

	return err;
}

1460
static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1461
				    struct mv88e6xxx_vtu_entry *entry)
1462
{
1463
	u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
1464
	u16 reg = 0;
1465
	int err;
1466

1467 1468 1469
	err = _mv88e6xxx_vtu_wait(chip);
	if (err)
		return err;
1470 1471 1472 1473 1474

	if (!entry->valid)
		goto loadpurge;

	/* Write port member tags */
1475 1476 1477
	err = mv88e6xxx_vtu_data_write(chip, entry);
	if (err)
		return err;
1478

1479
	if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1480
		reg = entry->sid & GLOBAL_VTU_SID_MASK;
1481 1482 1483
		err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
		if (err)
			return err;
1484
	}
1485

1486
	if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
1487
		reg = entry->fid & GLOBAL_VTU_FID_MASK;
1488 1489 1490
		err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, reg);
		if (err)
			return err;
1491
	} else if (mv88e6xxx_num_databases(chip) == 256) {
1492 1493 1494 1495 1496
		/* VTU DBNum[7:4] are located in VTU Operation 11:8, and
		 * VTU DBNum[3:0] are located in VTU Operation 3:0
		 */
		op |= (entry->fid & 0xf0) << 8;
		op |= entry->fid & 0xf;
1497 1498 1499 1500 1501
	}

	reg = GLOBAL_VTU_VID_VALID;
loadpurge:
	reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1502 1503 1504
	err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
	if (err)
		return err;
1505

1506
	return _mv88e6xxx_vtu_cmd(chip, op);
1507 1508
}

1509
static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
1510
				  struct mv88e6xxx_vtu_entry *entry)
1511
{
1512
	struct mv88e6xxx_vtu_entry next = { 0 };
1513 1514
	u16 val;
	int err;
1515

1516 1517 1518
	err = _mv88e6xxx_vtu_wait(chip);
	if (err)
		return err;
1519

1520 1521 1522 1523
	err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID,
				 sid & GLOBAL_VTU_SID_MASK);
	if (err)
		return err;
1524

1525 1526 1527
	err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
	if (err)
		return err;
1528

1529 1530 1531
	err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
	if (err)
		return err;
1532

1533
	next.sid = val & GLOBAL_VTU_SID_MASK;
1534

1535 1536 1537
	err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
	if (err)
		return err;
1538

1539
	next.valid = !!(val & GLOBAL_VTU_VID_VALID);
1540 1541

	if (next.valid) {
1542 1543 1544
		err = mv88e6xxx_stu_data_read(chip, &next);
		if (err)
			return err;
1545 1546 1547 1548 1549 1550
	}

	*entry = next;
	return 0;
}

1551
static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1552
				    struct mv88e6xxx_vtu_entry *entry)
1553 1554
{
	u16 reg = 0;
1555
	int err;
1556

1557 1558 1559
	err = _mv88e6xxx_vtu_wait(chip);
	if (err)
		return err;
1560 1561 1562 1563 1564

	if (!entry->valid)
		goto loadpurge;

	/* Write port states */
1565 1566 1567
	err = mv88e6xxx_stu_data_write(chip, entry);
	if (err)
		return err;
1568 1569 1570

	reg = GLOBAL_VTU_VID_VALID;
loadpurge:
1571 1572 1573
	err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
	if (err)
		return err;
1574 1575

	reg = entry->sid & GLOBAL_VTU_SID_MASK;
1576 1577 1578
	err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
	if (err)
		return err;
1579

1580
	return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1581 1582
}

1583
static int _mv88e6xxx_port_fid(struct mv88e6xxx_chip *chip, int port,
1584
			       u16 *new, u16 *old)
1585
{
1586
	struct dsa_switch *ds = chip->ds;
1587
	u16 upper_mask;
1588
	u16 fid;
1589 1590
	u16 reg;
	int err;
1591

1592
	if (mv88e6xxx_num_databases(chip) == 4096)
1593
		upper_mask = 0xff;
1594
	else if (mv88e6xxx_num_databases(chip) == 256)
1595
		upper_mask = 0xf;
1596 1597 1598
	else
		return -EOPNOTSUPP;

1599
	/* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
1600 1601 1602
	err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, &reg);
	if (err)
		return err;
1603

1604
	fid = (reg & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1605 1606

	if (new) {
1607 1608
		reg &= ~PORT_BASE_VLAN_FID_3_0_MASK;
		reg |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1609

1610 1611 1612
		err = mv88e6xxx_port_write(chip, port, PORT_BASE_VLAN, reg);
		if (err)
			return err;
1613 1614 1615
	}

	/* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
1616 1617 1618
	err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_1, &reg);
	if (err)
		return err;
1619

1620
	fid |= (reg & upper_mask) << 4;
1621 1622

	if (new) {
1623 1624
		reg &= ~upper_mask;
		reg |= (*new >> 4) & upper_mask;
1625

1626 1627 1628
		err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, reg);
		if (err)
			return err;
1629

1630 1631
		netdev_dbg(ds->ports[port].netdev,
			   "FID %d (was %d)\n", *new, fid);
1632 1633 1634 1635 1636 1637 1638 1639
	}

	if (old)
		*old = fid;

	return 0;
}

1640
static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_chip *chip,
1641
				   int port, u16 *fid)
1642
{
1643
	return _mv88e6xxx_port_fid(chip, port, NULL, fid);
1644 1645
}

1646
static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_chip *chip,
1647
				   int port, u16 fid)
1648
{
1649
	return _mv88e6xxx_port_fid(chip, port, &fid, NULL);
1650 1651
}

1652
static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
1653 1654
{
	DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1655
	struct mv88e6xxx_vtu_entry vlan;
1656
	int i, err;
1657 1658 1659

	bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);

1660
	/* Set every FID bit used by the (un)bridged ports */
1661
	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1662
		err = _mv88e6xxx_port_fid_get(chip, i, fid);
1663 1664 1665 1666 1667 1668
		if (err)
			return err;

		set_bit(*fid, fid_bitmap);
	}

1669
	/* Set every FID bit used by the VLAN entries */
1670
	err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1671 1672 1673 1674
	if (err)
		return err;

	do {
1675
		err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688
		if (err)
			return err;

		if (!vlan.valid)
			break;

		set_bit(vlan.fid, fid_bitmap);
	} while (vlan.vid < GLOBAL_VTU_VID_MASK);

	/* The reset value 0x000 is used to indicate that multiple address
	 * databases are not needed. Return the next positive available.
	 */
	*fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1689
	if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1690 1691 1692
		return -ENOSPC;

	/* Clear the database */
1693
	return _mv88e6xxx_atu_flush(chip, *fid, true);
1694 1695
}

1696
static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
1697
			      struct mv88e6xxx_vtu_entry *entry)
1698
{
1699
	struct dsa_switch *ds = chip->ds;
1700
	struct mv88e6xxx_vtu_entry vlan = {
1701 1702 1703
		.valid = true,
		.vid = vid,
	};
1704 1705
	int i, err;

1706
	err = _mv88e6xxx_fid_new(chip, &vlan.fid);
1707 1708
	if (err)
		return err;
1709

1710
	/* exclude all ports except the CPU and DSA ports */
1711
	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1712 1713 1714
		vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
			? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
			: GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1715

1716 1717
	if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
	    mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
1718
		struct mv88e6xxx_vtu_entry vstp;
1719 1720 1721 1722 1723 1724

		/* Adding a VTU entry requires a valid STU entry. As VSTP is not
		 * implemented, only one STU entry is needed to cover all VTU
		 * entries. Thus, validate the SID 0.
		 */
		vlan.sid = 0;
1725
		err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
1726 1727 1728 1729 1730 1731 1732 1733
		if (err)
			return err;

		if (vstp.sid != vlan.sid || !vstp.valid) {
			memset(&vstp, 0, sizeof(vstp));
			vstp.valid = true;
			vstp.sid = vlan.sid;

1734
			err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
1735 1736 1737 1738 1739 1740 1741 1742 1743
			if (err)
				return err;
		}
	}

	*entry = vlan;
	return 0;
}

1744
static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1745
			      struct mv88e6xxx_vtu_entry *entry, bool creat)
1746 1747 1748 1749 1750 1751
{
	int err;

	if (!vid)
		return -EINVAL;

1752
	err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
1753 1754 1755
	if (err)
		return err;

1756
	err = _mv88e6xxx_vtu_getnext(chip, entry);
1757 1758 1759 1760 1761 1762 1763 1764 1765 1766
	if (err)
		return err;

	if (entry->vid != vid || !entry->valid) {
		if (!creat)
			return -EOPNOTSUPP;
		/* -ENOENT would've been more appropriate, but switchdev expects
		 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
		 */

1767
		err = _mv88e6xxx_vtu_new(chip, vid, entry);
1768 1769 1770 1771 1772
	}

	return err;
}

1773 1774 1775
static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
					u16 vid_begin, u16 vid_end)
{
V
Vivien Didelot 已提交
1776
	struct mv88e6xxx_chip *chip = ds->priv;
1777
	struct mv88e6xxx_vtu_entry vlan;
1778 1779 1780 1781 1782
	int i, err;

	if (!vid_begin)
		return -EOPNOTSUPP;

1783
	mutex_lock(&chip->reg_lock);
1784

1785
	err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
1786 1787 1788 1789
	if (err)
		goto unlock;

	do {
1790
		err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1791 1792 1793 1794 1795 1796 1797 1798 1799
		if (err)
			goto unlock;

		if (!vlan.valid)
			break;

		if (vlan.vid > vid_end)
			break;

1800
		for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1801 1802 1803 1804 1805 1806 1807
			if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
				continue;

			if (vlan.data[i] ==
			    GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
				continue;

1808 1809
			if (chip->ports[i].bridge_dev ==
			    chip->ports[port].bridge_dev)
1810 1811
				break; /* same bridge, check next VLAN */

1812
			netdev_warn(ds->ports[port].netdev,
1813 1814
				    "hardware VLAN %d already used by %s\n",
				    vlan.vid,
1815
				    netdev_name(chip->ports[i].bridge_dev));
1816 1817 1818 1819 1820 1821
			err = -EOPNOTSUPP;
			goto unlock;
		}
	} while (vlan.vid < vid_end);

unlock:
1822
	mutex_unlock(&chip->reg_lock);
1823 1824 1825 1826

	return err;
}

1827 1828 1829 1830 1831 1832 1833
static const char * const mv88e6xxx_port_8021q_mode_names[] = {
	[PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
	[PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
	[PORT_CONTROL_2_8021Q_CHECK] = "Check",
	[PORT_CONTROL_2_8021Q_SECURE] = "Secure",
};

1834 1835
static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
					 bool vlan_filtering)
1836
{
V
Vivien Didelot 已提交
1837
	struct mv88e6xxx_chip *chip = ds->priv;
1838 1839
	u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
		PORT_CONTROL_2_8021Q_DISABLED;
1840 1841
	u16 reg;
	int err;
1842

1843
	if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1844 1845
		return -EOPNOTSUPP;

1846
	mutex_lock(&chip->reg_lock);
1847

1848 1849
	err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_2, &reg);
	if (err)
1850 1851
		goto unlock;

1852
	old = reg & PORT_CONTROL_2_8021Q_MASK;
1853

1854
	if (new != old) {
1855 1856
		reg &= ~PORT_CONTROL_2_8021Q_MASK;
		reg |= new & PORT_CONTROL_2_8021Q_MASK;
1857

1858 1859
		err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
		if (err)
1860 1861
			goto unlock;

1862
		netdev_dbg(ds->ports[port].netdev, "802.1Q Mode %s (was %s)\n",
1863 1864 1865
			   mv88e6xxx_port_8021q_mode_names[new],
			   mv88e6xxx_port_8021q_mode_names[old]);
	}
1866

1867
	err = 0;
1868
unlock:
1869
	mutex_unlock(&chip->reg_lock);
1870

1871
	return err;
1872 1873
}

1874 1875 1876 1877
static int
mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
			    const struct switchdev_obj_port_vlan *vlan,
			    struct switchdev_trans *trans)
1878
{
V
Vivien Didelot 已提交
1879
	struct mv88e6xxx_chip *chip = ds->priv;
1880 1881
	int err;

1882
	if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1883 1884
		return -EOPNOTSUPP;

1885 1886 1887 1888 1889 1890 1891 1892
	/* If the requested port doesn't belong to the same bridge as the VLAN
	 * members, do not support it (yet) and fallback to software VLAN.
	 */
	err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
					   vlan->vid_end);
	if (err)
		return err;

1893 1894 1895 1896 1897 1898
	/* We don't need any dynamic resource from the kernel (yet),
	 * so skip the prepare phase.
	 */
	return 0;
}

1899
static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1900
				    u16 vid, bool untagged)
1901
{
1902
	struct mv88e6xxx_vtu_entry vlan;
1903 1904
	int err;

1905
	err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1906
	if (err)
1907
		return err;
1908 1909 1910 1911 1912

	vlan.data[port] = untagged ?
		GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
		GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;

1913
	return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
1914 1915
}

1916 1917 1918
static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
				    const struct switchdev_obj_port_vlan *vlan,
				    struct switchdev_trans *trans)
1919
{
V
Vivien Didelot 已提交
1920
	struct mv88e6xxx_chip *chip = ds->priv;
1921 1922 1923 1924
	bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
	bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
	u16 vid;

1925
	if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1926 1927
		return;

1928
	mutex_lock(&chip->reg_lock);
1929

1930
	for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1931
		if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
1932 1933
			netdev_err(ds->ports[port].netdev,
				   "failed to add VLAN %d%c\n",
1934
				   vid, untagged ? 'u' : 't');
1935

1936
	if (pvid && _mv88e6xxx_port_pvid_set(chip, port, vlan->vid_end))
1937
		netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
1938
			   vlan->vid_end);
1939

1940
	mutex_unlock(&chip->reg_lock);
1941 1942
}

1943
static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1944
				    int port, u16 vid)
1945
{
1946
	struct dsa_switch *ds = chip->ds;
1947
	struct mv88e6xxx_vtu_entry vlan;
1948 1949
	int i, err;

1950
	err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1951
	if (err)
1952
		return err;
1953

1954 1955
	/* Tell switchdev if this VLAN is handled in software */
	if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1956
		return -EOPNOTSUPP;
1957 1958 1959 1960

	vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;

	/* keep the VLAN unless all ports are excluded */
1961
	vlan.valid = false;
1962
	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1963
		if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1964 1965 1966
			continue;

		if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1967
			vlan.valid = true;
1968 1969 1970 1971
			break;
		}
	}

1972
	err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
1973 1974 1975
	if (err)
		return err;

1976
	return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
1977 1978
}

1979 1980
static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
				   const struct switchdev_obj_port_vlan *vlan)
1981
{
V
Vivien Didelot 已提交
1982
	struct mv88e6xxx_chip *chip = ds->priv;
1983 1984 1985
	u16 pvid, vid;
	int err = 0;

1986
	if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1987 1988
		return -EOPNOTSUPP;

1989
	mutex_lock(&chip->reg_lock);
1990

1991
	err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
1992 1993 1994
	if (err)
		goto unlock;

1995
	for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1996
		err = _mv88e6xxx_port_vlan_del(chip, port, vid);
1997 1998 1999 2000
		if (err)
			goto unlock;

		if (vid == pvid) {
2001
			err = _mv88e6xxx_port_pvid_set(chip, port, 0);
2002 2003 2004 2005 2006
			if (err)
				goto unlock;
		}
	}

2007
unlock:
2008
	mutex_unlock(&chip->reg_lock);
2009 2010 2011 2012

	return err;
}

2013
static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
2014
				    const unsigned char *addr)
2015
{
2016
	int i, err;
2017 2018

	for (i = 0; i < 3; i++) {
2019 2020 2021 2022
		err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_MAC_01 + i,
					 (addr[i * 2] << 8) | addr[i * 2 + 1]);
		if (err)
			return err;
2023 2024 2025 2026 2027
	}

	return 0;
}

2028
static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
2029
				   unsigned char *addr)
2030
{
2031 2032
	u16 val;
	int i, err;
2033 2034

	for (i = 0; i < 3; i++) {
2035 2036 2037 2038 2039 2040
		err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_MAC_01 + i, &val);
		if (err)
			return err;

		addr[i * 2] = val >> 8;
		addr[i * 2 + 1] = val & 0xff;
2041 2042 2043 2044 2045
	}

	return 0;
}

2046
static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
2047
			       struct mv88e6xxx_atu_entry *entry)
2048
{
2049 2050
	int ret;

2051
	ret = _mv88e6xxx_atu_wait(chip);
2052 2053 2054
	if (ret < 0)
		return ret;

2055
	ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
2056 2057 2058
	if (ret < 0)
		return ret;

2059
	ret = _mv88e6xxx_atu_data_write(chip, entry);
2060
	if (ret < 0)
2061 2062
		return ret;

2063
	return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
2064
}
2065

2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101
static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
				  struct mv88e6xxx_atu_entry *entry);

static int mv88e6xxx_atu_get(struct mv88e6xxx_chip *chip, int fid,
			     const u8 *addr, struct mv88e6xxx_atu_entry *entry)
{
	struct mv88e6xxx_atu_entry next;
	int err;

	eth_broadcast_addr(next.mac);

	err = _mv88e6xxx_atu_mac_write(chip, next.mac);
	if (err)
		return err;

	do {
		err = _mv88e6xxx_atu_getnext(chip, fid, &next);
		if (err)
			return err;

		if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED)
			break;

		if (ether_addr_equal(next.mac, addr)) {
			*entry = next;
			return 0;
		}
	} while (!is_broadcast_ether_addr(next.mac));

	memset(entry, 0, sizeof(*entry));
	entry->fid = fid;
	ether_addr_copy(entry->mac, addr);

	return 0;
}

2102 2103 2104
static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
					const unsigned char *addr, u16 vid,
					u8 state)
2105
{
2106
	struct mv88e6xxx_vtu_entry vlan;
2107
	struct mv88e6xxx_atu_entry entry;
2108 2109
	int err;

2110 2111
	/* Null VLAN ID corresponds to the port private database */
	if (vid == 0)
2112
		err = _mv88e6xxx_port_fid_get(chip, port, &vlan.fid);
2113
	else
2114
		err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
2115 2116
	if (err)
		return err;
2117

2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129
	err = mv88e6xxx_atu_get(chip, vlan.fid, addr, &entry);
	if (err)
		return err;

	/* Purge the ATU entry only if no port is using it anymore */
	if (state == GLOBAL_ATU_DATA_STATE_UNUSED) {
		entry.portv_trunkid &= ~BIT(port);
		if (!entry.portv_trunkid)
			entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
	} else {
		entry.portv_trunkid |= BIT(port);
		entry.state = state;
2130 2131
	}

2132
	return _mv88e6xxx_atu_load(chip, &entry);
2133 2134
}

2135 2136 2137
static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
				      const struct switchdev_obj_port_fdb *fdb,
				      struct switchdev_trans *trans)
V
Vivien Didelot 已提交
2138 2139 2140 2141 2142 2143 2144
{
	/* We don't need any dynamic resource from the kernel (yet),
	 * so skip the prepare phase.
	 */
	return 0;
}

2145 2146 2147
static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
				   const struct switchdev_obj_port_fdb *fdb,
				   struct switchdev_trans *trans)
2148
{
V
Vivien Didelot 已提交
2149
	struct mv88e6xxx_chip *chip = ds->priv;
2150

2151
	mutex_lock(&chip->reg_lock);
2152 2153 2154
	if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
					 GLOBAL_ATU_DATA_STATE_UC_STATIC))
		netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n");
2155
	mutex_unlock(&chip->reg_lock);
2156 2157
}

2158 2159
static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
				  const struct switchdev_obj_port_fdb *fdb)
2160
{
V
Vivien Didelot 已提交
2161
	struct mv88e6xxx_chip *chip = ds->priv;
2162
	int err;
2163

2164
	mutex_lock(&chip->reg_lock);
2165 2166
	err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
					   GLOBAL_ATU_DATA_STATE_UNUSED);
2167
	mutex_unlock(&chip->reg_lock);
2168

2169
	return err;
2170 2171
}

2172
static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2173
				  struct mv88e6xxx_atu_entry *entry)
2174
{
2175
	struct mv88e6xxx_atu_entry next = { 0 };
2176 2177
	u16 val;
	int err;
2178 2179

	next.fid = fid;
2180

2181 2182 2183
	err = _mv88e6xxx_atu_wait(chip);
	if (err)
		return err;
2184

2185 2186 2187
	err = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
	if (err)
		return err;
2188

2189 2190 2191
	err = _mv88e6xxx_atu_mac_read(chip, next.mac);
	if (err)
		return err;
2192

2193 2194 2195
	err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_DATA, &val);
	if (err)
		return err;
2196

2197
	next.state = val & GLOBAL_ATU_DATA_STATE_MASK;
2198 2199 2200
	if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
		unsigned int mask, shift;

2201
		if (val & GLOBAL_ATU_DATA_TRUNK) {
2202 2203 2204 2205 2206 2207 2208 2209 2210
			next.trunk = true;
			mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
			shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
		} else {
			next.trunk = false;
			mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
			shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
		}

2211
		next.portv_trunkid = (val & mask) >> shift;
2212
	}
2213

2214
	*entry = next;
2215 2216 2217
	return 0;
}

2218 2219 2220 2221
static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
				      u16 fid, u16 vid, int port,
				      struct switchdev_obj *obj,
				      int (*cb)(struct switchdev_obj *obj))
2222 2223 2224 2225 2226 2227
{
	struct mv88e6xxx_atu_entry addr = {
		.mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
	};
	int err;

2228
	err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
2229 2230 2231 2232
	if (err)
		return err;

	do {
2233
		err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
2234
		if (err)
2235
			return err;
2236 2237 2238 2239

		if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
			break;

2240 2241 2242 2243 2244
		if (addr.trunk || (addr.portv_trunkid & BIT(port)) == 0)
			continue;

		if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
			struct switchdev_obj_port_fdb *fdb;
2245

2246 2247 2248 2249
			if (!is_unicast_ether_addr(addr.mac))
				continue;

			fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
2250 2251
			fdb->vid = vid;
			ether_addr_copy(fdb->addr, addr.mac);
2252 2253 2254 2255
			if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC)
				fdb->ndm_state = NUD_NOARP;
			else
				fdb->ndm_state = NUD_REACHABLE;
2256 2257 2258 2259 2260 2261 2262 2263 2264
		} else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
			struct switchdev_obj_port_mdb *mdb;

			if (!is_multicast_ether_addr(addr.mac))
				continue;

			mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
			mdb->vid = vid;
			ether_addr_copy(mdb->addr, addr.mac);
2265 2266
		} else {
			return -EOPNOTSUPP;
2267
		}
2268 2269 2270 2271

		err = cb(obj);
		if (err)
			return err;
2272 2273 2274 2275 2276
	} while (!is_broadcast_ether_addr(addr.mac));

	return err;
}

2277 2278 2279
static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
				  struct switchdev_obj *obj,
				  int (*cb)(struct switchdev_obj *obj))
2280
{
2281
	struct mv88e6xxx_vtu_entry vlan = {
2282 2283
		.vid = GLOBAL_VTU_VID_MASK, /* all ones */
	};
2284
	u16 fid;
2285 2286
	int err;

2287
	/* Dump port's default Filtering Information Database (VLAN ID 0) */
2288
	err = _mv88e6xxx_port_fid_get(chip, port, &fid);
2289
	if (err)
2290
		return err;
2291

2292
	err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
2293
	if (err)
2294
		return err;
2295

2296
	/* Dump VLANs' Filtering Information Databases */
2297
	err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
2298
	if (err)
2299
		return err;
2300 2301

	do {
2302
		err = _mv88e6xxx_vtu_getnext(chip, &vlan);
2303
		if (err)
2304
			return err;
2305 2306 2307 2308

		if (!vlan.valid)
			break;

2309 2310
		err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
						 obj, cb);
2311
		if (err)
2312
			return err;
2313 2314
	} while (vlan.vid < GLOBAL_VTU_VID_MASK);

2315 2316 2317 2318 2319 2320 2321
	return err;
}

static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
				   struct switchdev_obj_port_fdb *fdb,
				   int (*cb)(struct switchdev_obj *obj))
{
V
Vivien Didelot 已提交
2322
	struct mv88e6xxx_chip *chip = ds->priv;
2323 2324 2325 2326
	int err;

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
2327
	mutex_unlock(&chip->reg_lock);
2328 2329 2330 2331

	return err;
}

2332 2333
static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
				      struct net_device *bridge)
2334
{
V
Vivien Didelot 已提交
2335
	struct mv88e6xxx_chip *chip = ds->priv;
2336
	int i, err = 0;
2337

2338
	mutex_lock(&chip->reg_lock);
2339

2340
	/* Assign the bridge and remap each port's VLANTable */
2341
	chip->ports[port].bridge_dev = bridge;
2342

2343
	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
2344 2345
		if (chip->ports[i].bridge_dev == bridge) {
			err = _mv88e6xxx_port_based_vlan_map(chip, i);
2346 2347 2348 2349 2350
			if (err)
				break;
		}
	}

2351
	mutex_unlock(&chip->reg_lock);
2352

2353
	return err;
2354 2355
}

2356
static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
2357
{
V
Vivien Didelot 已提交
2358
	struct mv88e6xxx_chip *chip = ds->priv;
2359
	struct net_device *bridge = chip->ports[port].bridge_dev;
2360
	int i;
2361

2362
	mutex_lock(&chip->reg_lock);
2363

2364
	/* Unassign the bridge and remap each port's VLANTable */
2365
	chip->ports[port].bridge_dev = NULL;
2366

2367
	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
2368 2369
		if (i == port || chip->ports[i].bridge_dev == bridge)
			if (_mv88e6xxx_port_based_vlan_map(chip, i))
2370 2371
				netdev_warn(ds->ports[i].netdev,
					    "failed to remap\n");
2372

2373
	mutex_unlock(&chip->reg_lock);
2374 2375
}

2376
static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2377
{
2378
	bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE);
2379
	u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2380
	struct gpio_desc *gpiod = chip->reset;
2381
	unsigned long timeout;
2382
	u16 reg;
2383
	int err;
2384 2385 2386
	int i;

	/* Set all ports to the disabled state. */
2387
	for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2388 2389 2390
		err = mv88e6xxx_port_read(chip, i, PORT_CONTROL, &reg);
		if (err)
			return err;
2391

2392 2393 2394 2395
		err = mv88e6xxx_port_write(chip, i, PORT_CONTROL,
					   reg & 0xfffc);
		if (err)
			return err;
2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413
	}

	/* Wait for transmit queues to drain. */
	usleep_range(2000, 4000);

	/* If there is a gpio connected to the reset pin, toggle it */
	if (gpiod) {
		gpiod_set_value_cansleep(gpiod, 1);
		usleep_range(10000, 20000);
		gpiod_set_value_cansleep(gpiod, 0);
		usleep_range(10000, 20000);
	}

	/* Reset the switch. Keep the PPU active if requested. The PPU
	 * needs to be active to support indirect phy register access
	 * through global registers 0x18 and 0x19.
	 */
	if (ppu_active)
2414
		err = mv88e6xxx_g1_write(chip, 0x04, 0xc000);
2415
	else
2416
		err = mv88e6xxx_g1_write(chip, 0x04, 0xc400);
2417 2418
	if (err)
		return err;
2419 2420 2421 2422

	/* Wait up to one second for reset to complete. */
	timeout = jiffies + 1 * HZ;
	while (time_before(jiffies, timeout)) {
2423 2424 2425
		err = mv88e6xxx_g1_read(chip, 0x00, &reg);
		if (err)
			return err;
2426

2427
		if ((reg & is_reset) == is_reset)
2428 2429 2430 2431
			break;
		usleep_range(1000, 2000);
	}
	if (time_after(jiffies, timeout))
2432
		err = -ETIMEDOUT;
2433
	else
2434
		err = 0;
2435

2436
	return err;
2437 2438
}

2439
static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
2440
{
2441 2442
	u16 val;
	int err;
2443

2444 2445 2446 2447
	/* Clear Power Down bit */
	err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
	if (err)
		return err;
2448

2449 2450 2451
	if (val & BMCR_PDOWN) {
		val &= ~BMCR_PDOWN;
		err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
2452 2453
	}

2454
	return err;
2455 2456
}

2457
static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2458
{
2459
	struct dsa_switch *ds = chip->ds;
2460
	int err;
2461
	u16 reg;
2462

2463 2464 2465 2466
	if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
	    mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
	    mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
	    mv88e6xxx_6065_family(chip) || mv88e6xxx_6320_family(chip)) {
2467 2468 2469 2470 2471 2472
		/* MAC Forcing register: don't force link, speed,
		 * duplex or flow control state to any particular
		 * values on physical ports, but force the CPU port
		 * and all DSA ports to their maximum bandwidth and
		 * full duplex.
		 */
2473
		err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, &reg);
2474
		if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
2475
			reg &= ~PORT_PCS_CTRL_UNFORCED;
2476 2477 2478 2479
			reg |= PORT_PCS_CTRL_FORCE_LINK |
				PORT_PCS_CTRL_LINK_UP |
				PORT_PCS_CTRL_DUPLEX_FULL |
				PORT_PCS_CTRL_FORCE_DUPLEX;
2480
			if (mv88e6xxx_6065_family(chip))
2481 2482 2483 2484 2485 2486 2487
				reg |= PORT_PCS_CTRL_100;
			else
				reg |= PORT_PCS_CTRL_1000;
		} else {
			reg |= PORT_PCS_CTRL_UNFORCED;
		}

2488 2489 2490
		err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
		if (err)
			return err;
2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507
	}

	/* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
	 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
	 * tunneling, determine priority by looking at 802.1p and IP
	 * priority fields (IP prio has precedence), and set STP state
	 * to Forwarding.
	 *
	 * If this is the CPU link, use DSA or EDSA tagging depending
	 * on which tagging mode was configured.
	 *
	 * If this is a link to another switch, use DSA tagging mode.
	 *
	 * If this is the upstream port for this switch, enable
	 * forwarding of unknown unicasts and multicasts.
	 */
	reg = 0;
2508 2509 2510 2511
	if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
	    mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
	    mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) ||
	    mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip))
2512 2513 2514 2515
		reg = PORT_CONTROL_IGMP_MLD_SNOOP |
		PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
		PORT_CONTROL_STATE_FORWARDING;
	if (dsa_is_cpu_port(ds, port)) {
2516
		if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA))
2517
			reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA |
2518
				PORT_CONTROL_FORWARD_UNKNOWN_MC;
2519 2520
		else
			reg |= PORT_CONTROL_DSA_TAG;
2521 2522
		reg |= PORT_CONTROL_EGRESS_ADD_TAG |
			PORT_CONTROL_FORWARD_UNKNOWN;
2523
	}
2524
	if (dsa_is_dsa_port(ds, port)) {
2525 2526
		if (mv88e6xxx_6095_family(chip) ||
		    mv88e6xxx_6185_family(chip))
2527
			reg |= PORT_CONTROL_DSA_TAG;
2528 2529 2530 2531 2532
		if (mv88e6xxx_6352_family(chip) ||
		    mv88e6xxx_6351_family(chip) ||
		    mv88e6xxx_6165_family(chip) ||
		    mv88e6xxx_6097_family(chip) ||
		    mv88e6xxx_6320_family(chip)) {
2533
			reg |= PORT_CONTROL_FRAME_MODE_DSA;
2534 2535
		}

2536 2537 2538 2539 2540
		if (port == dsa_upstream_port(ds))
			reg |= PORT_CONTROL_FORWARD_UNKNOWN |
				PORT_CONTROL_FORWARD_UNKNOWN_MC;
	}
	if (reg) {
2541 2542 2543
		err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
		if (err)
			return err;
2544 2545
	}

2546 2547 2548
	/* If this port is connected to a SerDes, make sure the SerDes is not
	 * powered down.
	 */
2549
	if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
2550 2551 2552 2553 2554 2555 2556 2557 2558 2559
		err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
		if (err)
			return err;
		reg &= PORT_STATUS_CMODE_MASK;
		if ((reg == PORT_STATUS_CMODE_100BASE_X) ||
		    (reg == PORT_STATUS_CMODE_1000BASE_X) ||
		    (reg == PORT_STATUS_CMODE_SGMII)) {
			err = mv88e6xxx_serdes_power_on(chip);
			if (err < 0)
				return err;
2560 2561 2562
		}
	}

2563
	/* Port Control 2: don't force a good FCS, set the maximum frame size to
2564
	 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2565 2566 2567
	 * untagged frames on this port, do a destination address lookup on all
	 * received packets as usual, disable ARP mirroring and don't send a
	 * copy of all transmitted/received frames on this port to the CPU.
2568 2569
	 */
	reg = 0;
2570 2571 2572 2573
	if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
	    mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
	    mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
	    mv88e6xxx_6185_family(chip))
2574 2575
		reg = PORT_CONTROL_2_MAP_DA;

2576 2577
	if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
	    mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip))
2578 2579
		reg |= PORT_CONTROL_2_JUMBO_10240;

2580
	if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
2581 2582 2583 2584 2585 2586 2587 2588 2589
		/* Set the upstream port this port should use */
		reg |= dsa_upstream_port(ds);
		/* enable forwarding of unknown multicast addresses to
		 * the upstream port
		 */
		if (port == dsa_upstream_port(ds))
			reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
	}

2590
	reg |= PORT_CONTROL_2_8021Q_DISABLED;
2591

2592
	if (reg) {
2593 2594 2595
		err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
		if (err)
			return err;
2596 2597 2598 2599 2600 2601 2602
	}

	/* Port Association Vector: when learning source addresses
	 * of packets, add the address to the address database using
	 * a port bitmap that has only the bit for this port set and
	 * the other bits clear.
	 */
2603
	reg = 1 << port;
2604 2605
	/* Disable learning for CPU port */
	if (dsa_is_cpu_port(ds, port))
2606
		reg = 0;
2607

2608 2609 2610
	err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg);
	if (err)
		return err;
2611 2612

	/* Egress rate control 2: disable egress rate control. */
2613 2614 2615
	err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000);
	if (err)
		return err;
2616

2617 2618 2619
	if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
	    mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
	    mv88e6xxx_6320_family(chip)) {
2620 2621 2622 2623
		/* Do not limit the period of time that this port can
		 * be paused for by the remote end or the period of
		 * time that this port can pause the remote end.
		 */
2624 2625 2626
		err = mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL, 0x0000);
		if (err)
			return err;
2627 2628 2629 2630 2631

		/* Port ATU control: disable limiting the number of
		 * address database entries that this port is allowed
		 * to use.
		 */
2632 2633
		err = mv88e6xxx_port_write(chip, port, PORT_ATU_CONTROL,
					   0x0000);
2634 2635 2636
		/* Priority Override: disable DA, SA and VTU priority
		 * override.
		 */
2637 2638 2639 2640
		err = mv88e6xxx_port_write(chip, port, PORT_PRI_OVERRIDE,
					   0x0000);
		if (err)
			return err;
2641 2642 2643 2644

		/* Port Ethertype: use the Ethertype DSA Ethertype
		 * value.
		 */
2645
		if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA)) {
2646 2647 2648 2649
			err = mv88e6xxx_port_write(chip, port, PORT_ETH_TYPE,
						   ETH_P_EDSA);
			if (err)
				return err;
2650 2651
		}

2652 2653 2654
		/* Tag Remap: use an identity 802.1p prio -> switch
		 * prio mapping.
		 */
2655 2656 2657 2658
		err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_0123,
					   0x3210);
		if (err)
			return err;
2659 2660 2661 2662

		/* Tag Remap 2: use an identity 802.1p prio -> switch
		 * prio mapping.
		 */
2663 2664 2665 2666
		err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_4567,
					   0x7654);
		if (err)
			return err;
2667 2668
	}

2669
	/* Rate Control: disable ingress rate limiting. */
2670 2671 2672
	if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
	    mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
	    mv88e6xxx_6320_family(chip)) {
2673 2674 2675 2676
		err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL,
					   0x0001);
		if (err)
			return err;
2677
	} else if (mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip)) {
2678 2679 2680 2681
		err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL,
					   0x0000);
		if (err)
			return err;
2682 2683
	}

2684 2685
	/* Port Control 1: disable trunking, disable sending
	 * learning messages to this port.
2686
	 */
2687 2688 2689
	err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, 0x0000);
	if (err)
		return err;
2690

2691
	/* Port based VLAN map: give each port the same default address
2692 2693
	 * database, and allow bidirectional communication between the
	 * CPU and DSA port(s), and the other ports.
2694
	 */
2695 2696 2697
	err = _mv88e6xxx_port_fid_set(chip, port, 0);
	if (err)
		return err;
2698

2699 2700 2701
	err = _mv88e6xxx_port_based_vlan_map(chip, port);
	if (err)
		return err;
2702 2703 2704 2705

	/* Default VLAN ID and priority: don't set a default VLAN
	 * ID, and set the default packet priority to zero.
	 */
2706
	return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000);
2707 2708
}

2709
int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2710 2711 2712
{
	int err;

2713
	err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
2714 2715 2716
	if (err)
		return err;

2717
	err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
2718 2719 2720
	if (err)
		return err;

2721 2722 2723 2724 2725
	err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
	if (err)
		return err;

	return 0;
2726 2727
}

2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743
static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip,
				     unsigned int msecs)
{
	const unsigned int coeff = chip->info->age_time_coeff;
	const unsigned int min = 0x01 * coeff;
	const unsigned int max = 0xff * coeff;
	u8 age_time;
	u16 val;
	int err;

	if (msecs < min || msecs > max)
		return -ERANGE;

	/* Round to nearest multiple of coeff */
	age_time = (msecs + coeff / 2) / coeff;

2744
	err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
2745 2746 2747 2748 2749 2750 2751
	if (err)
		return err;

	/* AgeTime is 11:4 bits */
	val &= ~0xff0;
	val |= age_time << 4;

2752
	return mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, val);
2753 2754
}

2755 2756 2757
static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
				     unsigned int ageing_time)
{
V
Vivien Didelot 已提交
2758
	struct mv88e6xxx_chip *chip = ds->priv;
2759 2760 2761 2762 2763 2764 2765 2766 2767
	int err;

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_g1_set_age_time(chip, ageing_time);
	mutex_unlock(&chip->reg_lock);

	return err;
}

2768
static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
2769
{
2770
	struct dsa_switch *ds = chip->ds;
2771
	u32 upstream_port = dsa_upstream_port(ds);
2772
	u16 reg;
2773
	int err;
2774

2775 2776 2777 2778
	/* Enable the PHY Polling Unit if present, don't discard any packets,
	 * and mask all interrupt sources.
	 */
	reg = 0;
2779 2780
	if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) ||
	    mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE))
2781 2782
		reg |= GLOBAL_CONTROL_PPU_ENABLE;

2783
	err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
2784 2785 2786
	if (err)
		return err;

2787 2788 2789 2790 2791 2792
	/* Configure the upstream port, and configure it as the port to which
	 * ingress and egress and ARP monitor frames are to be sent.
	 */
	reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
		upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
		upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
2793
	err = mv88e6xxx_g1_write(chip, GLOBAL_MONITOR_CONTROL, reg);
2794 2795 2796
	if (err)
		return err;

2797
	/* Disable remote management, and set the switch's DSA device number. */
2798 2799 2800
	err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2,
				 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
				 (ds->index & 0x1f));
2801 2802 2803
	if (err)
		return err;

2804 2805 2806 2807 2808
	/* Clear all the VTU and STU entries */
	err = _mv88e6xxx_vtu_stu_flush(chip);
	if (err < 0)
		return err;

2809 2810 2811 2812
	/* Set the default address aging time to 5 minutes, and
	 * enable address learn messages to be sent to all message
	 * ports.
	 */
2813 2814
	err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
				 GLOBAL_ATU_CONTROL_LEARN2ALL);
2815
	if (err)
2816
		return err;
2817

2818 2819
	err = mv88e6xxx_g1_set_age_time(chip, 300000);
	if (err)
2820 2821 2822 2823 2824 2825 2826
		return err;

	/* Clear all ATU entries */
	err = _mv88e6xxx_atu_flush(chip, 0, true);
	if (err)
		return err;

2827
	/* Configure the IP ToS mapping registers. */
2828
	err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000);
2829
	if (err)
2830
		return err;
2831
	err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000);
2832
	if (err)
2833
		return err;
2834
	err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555);
2835
	if (err)
2836
		return err;
2837
	err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555);
2838
	if (err)
2839
		return err;
2840
	err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa);
2841
	if (err)
2842
		return err;
2843
	err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa);
2844
	if (err)
2845
		return err;
2846
	err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff);
2847
	if (err)
2848
		return err;
2849
	err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff);
2850
	if (err)
2851
		return err;
2852 2853

	/* Configure the IEEE 802.1p priority mapping register. */
2854
	err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41);
2855
	if (err)
2856
		return err;
2857

2858
	/* Clear the statistics counters for all ports */
2859 2860
	err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
				 GLOBAL_STATS_OP_FLUSH_ALL);
2861 2862 2863 2864 2865 2866 2867 2868 2869 2870 2871
	if (err)
		return err;

	/* Wait for the flush to complete. */
	err = _mv88e6xxx_stats_wait(chip);
	if (err)
		return err;

	return 0;
}

2872
static int mv88e6xxx_setup(struct dsa_switch *ds)
2873
{
V
Vivien Didelot 已提交
2874
	struct mv88e6xxx_chip *chip = ds->priv;
2875
	int err;
2876 2877
	int i;

2878 2879
	chip->ds = ds;
	ds->slave_mii_bus = chip->mdio_bus;
2880

2881
	mutex_lock(&chip->reg_lock);
2882

2883
	err = mv88e6xxx_switch_reset(chip);
2884 2885 2886
	if (err)
		goto unlock;

2887
	/* Setup Switch Port Registers */
2888
	for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2889 2890 2891 2892 2893 2894 2895
		err = mv88e6xxx_setup_port(chip, i);
		if (err)
			goto unlock;
	}

	/* Setup Switch Global 1 Registers */
	err = mv88e6xxx_g1_setup(chip);
2896 2897 2898
	if (err)
		goto unlock;

2899 2900 2901
	/* Setup Switch Global 2 Registers */
	if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
		err = mv88e6xxx_g2_setup(chip);
2902 2903 2904
		if (err)
			goto unlock;
	}
2905

2906
unlock:
2907
	mutex_unlock(&chip->reg_lock);
2908

2909
	return err;
2910 2911
}

2912 2913
static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
{
V
Vivien Didelot 已提交
2914
	struct mv88e6xxx_chip *chip = ds->priv;
2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929
	int err;

	mutex_lock(&chip->reg_lock);

	/* Has an indirect Switch MAC/WoL/WoF register in Global 2? */
	if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_SWITCH_MAC))
		err = mv88e6xxx_g2_set_switch_mac(chip, addr);
	else
		err = mv88e6xxx_g1_set_switch_mac(chip, addr);

	mutex_unlock(&chip->reg_lock);

	return err;
}

2930
static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
2931
{
2932
	struct mv88e6xxx_chip *chip = bus->priv;
2933 2934
	u16 val;
	int err;
2935

2936
	if (phy >= mv88e6xxx_num_ports(chip))
2937
		return 0xffff;
2938

2939
	mutex_lock(&chip->reg_lock);
2940
	err = mv88e6xxx_phy_read(chip, phy, reg, &val);
2941
	mutex_unlock(&chip->reg_lock);
2942 2943

	return err ? err : val;
2944 2945
}

2946
static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
2947
{
2948
	struct mv88e6xxx_chip *chip = bus->priv;
2949
	int err;
2950

2951
	if (phy >= mv88e6xxx_num_ports(chip))
2952
		return 0xffff;
2953

2954
	mutex_lock(&chip->reg_lock);
2955
	err = mv88e6xxx_phy_write(chip, phy, reg, val);
2956
	mutex_unlock(&chip->reg_lock);
2957 2958

	return err;
2959 2960
}

2961
static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
2962 2963 2964 2965 2966 2967 2968
				   struct device_node *np)
{
	static int index;
	struct mii_bus *bus;
	int err;

	if (np)
2969
		chip->mdio_np = of_get_child_by_name(np, "mdio");
2970

2971
	bus = devm_mdiobus_alloc(chip->dev);
2972 2973 2974
	if (!bus)
		return -ENOMEM;

2975
	bus->priv = (void *)chip;
2976 2977 2978 2979 2980 2981 2982 2983 2984 2985
	if (np) {
		bus->name = np->full_name;
		snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
	} else {
		bus->name = "mv88e6xxx SMI";
		snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
	}

	bus->read = mv88e6xxx_mdio_read;
	bus->write = mv88e6xxx_mdio_write;
2986
	bus->parent = chip->dev;
2987

2988 2989
	if (chip->mdio_np)
		err = of_mdiobus_register(bus, chip->mdio_np);
2990 2991 2992
	else
		err = mdiobus_register(bus);
	if (err) {
2993
		dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
2994 2995
		goto out;
	}
2996
	chip->mdio_bus = bus;
2997 2998 2999 3000

	return 0;

out:
3001 3002
	if (chip->mdio_np)
		of_node_put(chip->mdio_np);
3003 3004 3005 3006

	return err;
}

3007
static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip)
3008 3009

{
3010
	struct mii_bus *bus = chip->mdio_bus;
3011 3012 3013

	mdiobus_unregister(bus);

3014 3015
	if (chip->mdio_np)
		of_node_put(chip->mdio_np);
3016 3017
}

3018 3019 3020 3021
#ifdef CONFIG_NET_DSA_HWMON

static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
{
V
Vivien Didelot 已提交
3022
	struct mv88e6xxx_chip *chip = ds->priv;
3023
	u16 val;
3024 3025 3026 3027
	int ret;

	*temp = 0;

3028
	mutex_lock(&chip->reg_lock);
3029

3030
	ret = mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x6);
3031 3032 3033 3034
	if (ret < 0)
		goto error;

	/* Enable temperature sensor */
3035
	ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
3036 3037 3038
	if (ret < 0)
		goto error;

3039
	ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val | (1 << 5));
3040 3041 3042 3043 3044 3045
	if (ret < 0)
		goto error;

	/* Wait for temperature to stabilize */
	usleep_range(10000, 12000);

3046 3047
	ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
	if (ret < 0)
3048 3049 3050
		goto error;

	/* Disable temperature sensor */
3051
	ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val & ~(1 << 5));
3052 3053 3054 3055 3056 3057
	if (ret < 0)
		goto error;

	*temp = ((val & 0x1f) - 5) * 5;

error:
3058
	mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x0);
3059
	mutex_unlock(&chip->reg_lock);
3060 3061 3062 3063 3064
	return ret;
}

static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
{
V
Vivien Didelot 已提交
3065
	struct mv88e6xxx_chip *chip = ds->priv;
3066
	int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3067
	u16 val;
3068 3069 3070 3071
	int ret;

	*temp = 0;

3072 3073 3074
	mutex_lock(&chip->reg_lock);
	ret = mv88e6xxx_phy_page_read(chip, phy, 6, 27, &val);
	mutex_unlock(&chip->reg_lock);
3075 3076 3077
	if (ret < 0)
		return ret;

3078
	*temp = (val & 0xff) - 25;
3079 3080 3081 3082

	return 0;
}

3083
static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
3084
{
V
Vivien Didelot 已提交
3085
	struct mv88e6xxx_chip *chip = ds->priv;
3086

3087
	if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP))
3088 3089
		return -EOPNOTSUPP;

3090
	if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
3091 3092 3093 3094 3095
		return mv88e63xx_get_temp(ds, temp);

	return mv88e61xx_get_temp(ds, temp);
}

3096
static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
3097
{
V
Vivien Didelot 已提交
3098
	struct mv88e6xxx_chip *chip = ds->priv;
3099
	int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3100
	u16 val;
3101 3102
	int ret;

3103
	if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3104 3105 3106 3107
		return -EOPNOTSUPP;

	*temp = 0;

3108 3109 3110
	mutex_lock(&chip->reg_lock);
	ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
	mutex_unlock(&chip->reg_lock);
3111 3112 3113
	if (ret < 0)
		return ret;

3114
	*temp = (((val >> 8) & 0x1f) * 5) - 25;
3115 3116 3117 3118

	return 0;
}

3119
static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
3120
{
V
Vivien Didelot 已提交
3121
	struct mv88e6xxx_chip *chip = ds->priv;
3122
	int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3123 3124
	u16 val;
	int err;
3125

3126
	if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3127 3128
		return -EOPNOTSUPP;

3129 3130 3131 3132
	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
	if (err)
		goto unlock;
3133
	temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
3134 3135 3136 3137 3138 3139
	err = mv88e6xxx_phy_page_write(chip, phy, 6, 26,
				       (val & 0xe0ff) | (temp << 8));
unlock:
	mutex_unlock(&chip->reg_lock);

	return err;
3140 3141
}

3142
static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
3143
{
V
Vivien Didelot 已提交
3144
	struct mv88e6xxx_chip *chip = ds->priv;
3145
	int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3146
	u16 val;
3147 3148
	int ret;

3149
	if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3150 3151 3152 3153
		return -EOPNOTSUPP;

	*alarm = false;

3154 3155 3156
	mutex_lock(&chip->reg_lock);
	ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
	mutex_unlock(&chip->reg_lock);
3157 3158 3159
	if (ret < 0)
		return ret;

3160
	*alarm = !!(val & 0x40);
3161 3162 3163 3164 3165

	return 0;
}
#endif /* CONFIG_NET_DSA_HWMON */

3166 3167
static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
{
V
Vivien Didelot 已提交
3168
	struct mv88e6xxx_chip *chip = ds->priv;
3169 3170 3171 3172 3173 3174 3175

	return chip->eeprom_len;
}

static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
				struct ethtool_eeprom *eeprom, u8 *data)
{
V
Vivien Didelot 已提交
3176
	struct mv88e6xxx_chip *chip = ds->priv;
3177 3178 3179 3180 3181
	int err;

	mutex_lock(&chip->reg_lock);

	if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
3182
		err = mv88e6xxx_g2_get_eeprom16(chip, eeprom, data);
3183 3184 3185 3186 3187 3188 3189 3190 3191 3192 3193 3194 3195 3196 3197 3198
	else
		err = -EOPNOTSUPP;

	mutex_unlock(&chip->reg_lock);

	if (err)
		return err;

	eeprom->magic = 0xc3ec4951;

	return 0;
}

static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
				struct ethtool_eeprom *eeprom, u8 *data)
{
V
Vivien Didelot 已提交
3199
	struct mv88e6xxx_chip *chip = ds->priv;
3200 3201 3202 3203 3204 3205 3206 3207
	int err;

	if (eeprom->magic != 0xc3ec4951)
		return -EINVAL;

	mutex_lock(&chip->reg_lock);

	if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
3208
		err = mv88e6xxx_g2_set_eeprom16(chip, eeprom, data);
3209 3210 3211 3212 3213 3214 3215 3216
	else
		err = -EOPNOTSUPP;

	mutex_unlock(&chip->reg_lock);

	return err;
}

3217 3218 3219 3220 3221 3222 3223
static const struct mv88e6xxx_info mv88e6xxx_table[] = {
	[MV88E6085] = {
		.prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
		.family = MV88E6XXX_FAMILY_6097,
		.name = "Marvell 88E6085",
		.num_databases = 4096,
		.num_ports = 10,
3224
		.port_base_addr = 0x10,
3225
		.global1_addr = 0x1b,
3226
		.age_time_coeff = 15000,
3227 3228 3229 3230 3231 3232 3233 3234 3235
		.flags = MV88E6XXX_FLAGS_FAMILY_6097,
	},

	[MV88E6095] = {
		.prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
		.family = MV88E6XXX_FAMILY_6095,
		.name = "Marvell 88E6095/88E6095F",
		.num_databases = 256,
		.num_ports = 11,
3236
		.port_base_addr = 0x10,
3237
		.global1_addr = 0x1b,
3238
		.age_time_coeff = 15000,
3239 3240 3241 3242 3243 3244 3245 3246 3247
		.flags = MV88E6XXX_FLAGS_FAMILY_6095,
	},

	[MV88E6123] = {
		.prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
		.family = MV88E6XXX_FAMILY_6165,
		.name = "Marvell 88E6123",
		.num_databases = 4096,
		.num_ports = 3,
3248
		.port_base_addr = 0x10,
3249
		.global1_addr = 0x1b,
3250
		.age_time_coeff = 15000,
3251 3252 3253 3254 3255 3256 3257 3258 3259
		.flags = MV88E6XXX_FLAGS_FAMILY_6165,
	},

	[MV88E6131] = {
		.prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
		.family = MV88E6XXX_FAMILY_6185,
		.name = "Marvell 88E6131",
		.num_databases = 256,
		.num_ports = 8,
3260
		.port_base_addr = 0x10,
3261
		.global1_addr = 0x1b,
3262
		.age_time_coeff = 15000,
3263 3264 3265 3266 3267 3268 3269 3270 3271
		.flags = MV88E6XXX_FLAGS_FAMILY_6185,
	},

	[MV88E6161] = {
		.prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
		.family = MV88E6XXX_FAMILY_6165,
		.name = "Marvell 88E6161",
		.num_databases = 4096,
		.num_ports = 6,
3272
		.port_base_addr = 0x10,
3273
		.global1_addr = 0x1b,
3274
		.age_time_coeff = 15000,
3275 3276 3277 3278 3279 3280 3281 3282 3283
		.flags = MV88E6XXX_FLAGS_FAMILY_6165,
	},

	[MV88E6165] = {
		.prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
		.family = MV88E6XXX_FAMILY_6165,
		.name = "Marvell 88E6165",
		.num_databases = 4096,
		.num_ports = 6,
3284
		.port_base_addr = 0x10,
3285
		.global1_addr = 0x1b,
3286
		.age_time_coeff = 15000,
3287 3288 3289 3290 3291 3292 3293 3294 3295
		.flags = MV88E6XXX_FLAGS_FAMILY_6165,
	},

	[MV88E6171] = {
		.prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6171",
		.num_databases = 4096,
		.num_ports = 7,
3296
		.port_base_addr = 0x10,
3297
		.global1_addr = 0x1b,
3298
		.age_time_coeff = 15000,
3299 3300 3301 3302 3303 3304 3305 3306 3307
		.flags = MV88E6XXX_FLAGS_FAMILY_6351,
	},

	[MV88E6172] = {
		.prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6172",
		.num_databases = 4096,
		.num_ports = 7,
3308
		.port_base_addr = 0x10,
3309
		.global1_addr = 0x1b,
3310
		.age_time_coeff = 15000,
3311 3312 3313 3314 3315 3316 3317 3318 3319
		.flags = MV88E6XXX_FLAGS_FAMILY_6352,
	},

	[MV88E6175] = {
		.prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6175",
		.num_databases = 4096,
		.num_ports = 7,
3320
		.port_base_addr = 0x10,
3321
		.global1_addr = 0x1b,
3322
		.age_time_coeff = 15000,
3323 3324 3325 3326 3327 3328 3329 3330 3331
		.flags = MV88E6XXX_FLAGS_FAMILY_6351,
	},

	[MV88E6176] = {
		.prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6176",
		.num_databases = 4096,
		.num_ports = 7,
3332
		.port_base_addr = 0x10,
3333
		.global1_addr = 0x1b,
3334
		.age_time_coeff = 15000,
3335 3336 3337 3338 3339 3340 3341 3342 3343
		.flags = MV88E6XXX_FLAGS_FAMILY_6352,
	},

	[MV88E6185] = {
		.prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
		.family = MV88E6XXX_FAMILY_6185,
		.name = "Marvell 88E6185",
		.num_databases = 256,
		.num_ports = 10,
3344
		.port_base_addr = 0x10,
3345
		.global1_addr = 0x1b,
3346
		.age_time_coeff = 15000,
3347 3348 3349 3350 3351 3352 3353 3354 3355
		.flags = MV88E6XXX_FLAGS_FAMILY_6185,
	},

	[MV88E6240] = {
		.prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6240",
		.num_databases = 4096,
		.num_ports = 7,
3356
		.port_base_addr = 0x10,
3357
		.global1_addr = 0x1b,
3358
		.age_time_coeff = 15000,
3359 3360 3361 3362 3363 3364 3365 3366 3367
		.flags = MV88E6XXX_FLAGS_FAMILY_6352,
	},

	[MV88E6320] = {
		.prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
		.family = MV88E6XXX_FAMILY_6320,
		.name = "Marvell 88E6320",
		.num_databases = 4096,
		.num_ports = 7,
3368
		.port_base_addr = 0x10,
3369
		.global1_addr = 0x1b,
3370
		.age_time_coeff = 15000,
3371 3372 3373 3374 3375 3376 3377 3378 3379
		.flags = MV88E6XXX_FLAGS_FAMILY_6320,
	},

	[MV88E6321] = {
		.prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
		.family = MV88E6XXX_FAMILY_6320,
		.name = "Marvell 88E6321",
		.num_databases = 4096,
		.num_ports = 7,
3380
		.port_base_addr = 0x10,
3381
		.global1_addr = 0x1b,
3382
		.age_time_coeff = 15000,
3383 3384 3385 3386 3387 3388 3389 3390 3391
		.flags = MV88E6XXX_FLAGS_FAMILY_6320,
	},

	[MV88E6350] = {
		.prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6350",
		.num_databases = 4096,
		.num_ports = 7,
3392
		.port_base_addr = 0x10,
3393
		.global1_addr = 0x1b,
3394
		.age_time_coeff = 15000,
3395 3396 3397 3398 3399 3400 3401 3402 3403
		.flags = MV88E6XXX_FLAGS_FAMILY_6351,
	},

	[MV88E6351] = {
		.prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6351",
		.num_databases = 4096,
		.num_ports = 7,
3404
		.port_base_addr = 0x10,
3405
		.global1_addr = 0x1b,
3406
		.age_time_coeff = 15000,
3407 3408 3409 3410 3411 3412 3413 3414 3415
		.flags = MV88E6XXX_FLAGS_FAMILY_6351,
	},

	[MV88E6352] = {
		.prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6352",
		.num_databases = 4096,
		.num_ports = 7,
3416
		.port_base_addr = 0x10,
3417
		.global1_addr = 0x1b,
3418
		.age_time_coeff = 15000,
3419 3420 3421 3422
		.flags = MV88E6XXX_FLAGS_FAMILY_6352,
	},
};

3423
static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
3424
{
3425
	int i;
3426

3427 3428 3429
	for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
		if (mv88e6xxx_table[i].prod_num == prod_num)
			return &mv88e6xxx_table[i];
3430 3431 3432 3433

	return NULL;
}

3434
static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
3435 3436
{
	const struct mv88e6xxx_info *info;
3437 3438 3439
	unsigned int prod_num, rev;
	u16 id;
	int err;
3440

3441 3442 3443 3444 3445
	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
	mutex_unlock(&chip->reg_lock);
	if (err)
		return err;
3446 3447 3448 3449 3450 3451 3452 3453

	prod_num = (id & 0xfff0) >> 4;
	rev = id & 0x000f;

	info = mv88e6xxx_lookup_info(prod_num);
	if (!info)
		return -ENODEV;

3454
	/* Update the compatible info with the probed one */
3455
	chip->info = info;
3456

3457 3458 3459 3460
	err = mv88e6xxx_g2_require(chip);
	if (err)
		return err;

3461 3462
	dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
		 chip->info->prod_num, chip->info->name, rev);
3463 3464 3465 3466

	return 0;
}

3467
static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
3468
{
3469
	struct mv88e6xxx_chip *chip;
3470

3471 3472
	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
	if (!chip)
3473 3474
		return NULL;

3475
	chip->dev = dev;
3476

3477
	mutex_init(&chip->reg_lock);
3478

3479
	return chip;
3480 3481
}

3482
static const struct mv88e6xxx_bus_ops mv88e6xxx_g2_smi_phy_ops = {
3483 3484 3485 3486
	.read = mv88e6xxx_g2_smi_phy_read,
	.write = mv88e6xxx_g2_smi_phy_write,
};

3487
static const struct mv88e6xxx_bus_ops mv88e6xxx_phy_ops = {
3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498 3499 3500 3501 3502 3503
	.read = mv88e6xxx_read,
	.write = mv88e6xxx_write,
};

static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
{
	if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SMI_PHY)) {
		chip->phy_ops = &mv88e6xxx_g2_smi_phy_ops;
	} else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) {
		chip->phy_ops = &mv88e6xxx_phy_ppu_ops;
		mv88e6xxx_ppu_state_init(chip);
	} else {
		chip->phy_ops = &mv88e6xxx_phy_ops;
	}
}

3504 3505 3506 3507 3508 3509 3510
static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
{
	if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) {
		mv88e6xxx_ppu_state_destroy(chip);
	}
}

3511
static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
3512 3513 3514 3515 3516 3517
			      struct mii_bus *bus, int sw_addr)
{
	/* ADDR[0] pin is unavailable externally and considered zero */
	if (sw_addr & 0x1)
		return -EINVAL;

3518
	if (sw_addr == 0)
3519
		chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
3520
	else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
3521
		chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
3522 3523 3524
	else
		return -EINVAL;

3525 3526
	chip->bus = bus;
	chip->sw_addr = sw_addr;
3527 3528 3529 3530

	return 0;
}

3531 3532
static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
{
V
Vivien Didelot 已提交
3533
	struct mv88e6xxx_chip *chip = ds->priv;
3534 3535 3536 3537 3538

	if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA))
		return DSA_TAG_PROTO_EDSA;

	return DSA_TAG_PROTO_DSA;
3539 3540
}

3541 3542 3543
static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
				       struct device *host_dev, int sw_addr,
				       void **priv)
3544
{
3545
	struct mv88e6xxx_chip *chip;
3546
	struct mii_bus *bus;
3547
	int err;
3548

3549
	bus = dsa_host_dev_to_mii_bus(host_dev);
3550 3551 3552
	if (!bus)
		return NULL;

3553 3554
	chip = mv88e6xxx_alloc_chip(dsa_dev);
	if (!chip)
3555 3556
		return NULL;

3557
	/* Legacy SMI probing will only support chips similar to 88E6085 */
3558
	chip->info = &mv88e6xxx_table[MV88E6085];
3559

3560
	err = mv88e6xxx_smi_init(chip, bus, sw_addr);
3561 3562 3563
	if (err)
		goto free;

3564
	err = mv88e6xxx_detect(chip);
3565
	if (err)
3566
		goto free;
3567

3568 3569
	mv88e6xxx_phy_init(chip);

3570
	err = mv88e6xxx_mdio_register(chip, NULL);
3571
	if (err)
3572
		goto free;
3573

3574
	*priv = chip;
3575

3576
	return chip->info->name;
3577
free:
3578
	devm_kfree(dsa_dev, chip);
3579 3580

	return NULL;
3581 3582
}

3583 3584 3585 3586 3587 3588 3589 3590 3591 3592 3593 3594 3595 3596 3597
static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
				      const struct switchdev_obj_port_mdb *mdb,
				      struct switchdev_trans *trans)
{
	/* We don't need any dynamic resource from the kernel (yet),
	 * so skip the prepare phase.
	 */

	return 0;
}

static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
				   const struct switchdev_obj_port_mdb *mdb,
				   struct switchdev_trans *trans)
{
V
Vivien Didelot 已提交
3598
	struct mv88e6xxx_chip *chip = ds->priv;
3599 3600 3601 3602 3603 3604 3605 3606 3607 3608 3609

	mutex_lock(&chip->reg_lock);
	if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
					 GLOBAL_ATU_DATA_STATE_MC_STATIC))
		netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n");
	mutex_unlock(&chip->reg_lock);
}

static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
				  const struct switchdev_obj_port_mdb *mdb)
{
V
Vivien Didelot 已提交
3610
	struct mv88e6xxx_chip *chip = ds->priv;
3611 3612 3613 3614 3615 3616 3617 3618 3619 3620 3621 3622 3623 3624
	int err;

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
					   GLOBAL_ATU_DATA_STATE_UNUSED);
	mutex_unlock(&chip->reg_lock);

	return err;
}

static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
				   struct switchdev_obj_port_mdb *mdb,
				   int (*cb)(struct switchdev_obj *obj))
{
V
Vivien Didelot 已提交
3625
	struct mv88e6xxx_chip *chip = ds->priv;
3626 3627 3628 3629 3630 3631 3632 3633 3634
	int err;

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
	mutex_unlock(&chip->reg_lock);

	return err;
}

3635
static struct dsa_switch_ops mv88e6xxx_switch_ops = {
3636
	.probe			= mv88e6xxx_drv_probe,
3637
	.get_tag_protocol	= mv88e6xxx_get_tag_protocol,
3638 3639 3640 3641 3642 3643 3644 3645 3646 3647 3648 3649 3650 3651
	.setup			= mv88e6xxx_setup,
	.set_addr		= mv88e6xxx_set_addr,
	.adjust_link		= mv88e6xxx_adjust_link,
	.get_strings		= mv88e6xxx_get_strings,
	.get_ethtool_stats	= mv88e6xxx_get_ethtool_stats,
	.get_sset_count		= mv88e6xxx_get_sset_count,
	.set_eee		= mv88e6xxx_set_eee,
	.get_eee		= mv88e6xxx_get_eee,
#ifdef CONFIG_NET_DSA_HWMON
	.get_temp		= mv88e6xxx_get_temp,
	.get_temp_limit		= mv88e6xxx_get_temp_limit,
	.set_temp_limit		= mv88e6xxx_set_temp_limit,
	.get_temp_alarm		= mv88e6xxx_get_temp_alarm,
#endif
3652
	.get_eeprom_len		= mv88e6xxx_get_eeprom_len,
3653 3654 3655 3656
	.get_eeprom		= mv88e6xxx_get_eeprom,
	.set_eeprom		= mv88e6xxx_set_eeprom,
	.get_regs_len		= mv88e6xxx_get_regs_len,
	.get_regs		= mv88e6xxx_get_regs,
3657
	.set_ageing_time	= mv88e6xxx_set_ageing_time,
3658 3659 3660
	.port_bridge_join	= mv88e6xxx_port_bridge_join,
	.port_bridge_leave	= mv88e6xxx_port_bridge_leave,
	.port_stp_state_set	= mv88e6xxx_port_stp_state_set,
3661
	.port_fast_age		= mv88e6xxx_port_fast_age,
3662 3663 3664 3665 3666 3667 3668 3669 3670
	.port_vlan_filtering	= mv88e6xxx_port_vlan_filtering,
	.port_vlan_prepare	= mv88e6xxx_port_vlan_prepare,
	.port_vlan_add		= mv88e6xxx_port_vlan_add,
	.port_vlan_del		= mv88e6xxx_port_vlan_del,
	.port_vlan_dump		= mv88e6xxx_port_vlan_dump,
	.port_fdb_prepare       = mv88e6xxx_port_fdb_prepare,
	.port_fdb_add           = mv88e6xxx_port_fdb_add,
	.port_fdb_del           = mv88e6xxx_port_fdb_del,
	.port_fdb_dump          = mv88e6xxx_port_fdb_dump,
3671 3672 3673 3674
	.port_mdb_prepare       = mv88e6xxx_port_mdb_prepare,
	.port_mdb_add           = mv88e6xxx_port_mdb_add,
	.port_mdb_del           = mv88e6xxx_port_mdb_del,
	.port_mdb_dump          = mv88e6xxx_port_mdb_dump,
3675 3676
};

3677
static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
3678 3679
				     struct device_node *np)
{
3680
	struct device *dev = chip->dev;
3681 3682 3683 3684 3685 3686 3687
	struct dsa_switch *ds;

	ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
	if (!ds)
		return -ENOMEM;

	ds->dev = dev;
3688
	ds->priv = chip;
3689
	ds->ops = &mv88e6xxx_switch_ops;
3690 3691 3692 3693 3694 3695

	dev_set_drvdata(dev, ds);

	return dsa_register_switch(ds, np);
}

3696
static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
3697
{
3698
	dsa_unregister_switch(chip->ds);
3699 3700
}

3701
static int mv88e6xxx_probe(struct mdio_device *mdiodev)
3702
{
3703
	struct device *dev = &mdiodev->dev;
3704
	struct device_node *np = dev->of_node;
3705
	const struct mv88e6xxx_info *compat_info;
3706
	struct mv88e6xxx_chip *chip;
3707
	u32 eeprom_len;
3708
	int err;
3709

3710 3711 3712 3713
	compat_info = of_device_get_match_data(dev);
	if (!compat_info)
		return -EINVAL;

3714 3715
	chip = mv88e6xxx_alloc_chip(dev);
	if (!chip)
3716 3717
		return -ENOMEM;

3718
	chip->info = compat_info;
3719

3720
	err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
3721 3722
	if (err)
		return err;
3723

3724
	err = mv88e6xxx_detect(chip);
3725 3726
	if (err)
		return err;
3727

3728 3729
	mv88e6xxx_phy_init(chip);

3730 3731 3732
	chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
	if (IS_ERR(chip->reset))
		return PTR_ERR(chip->reset);
3733

3734
	if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16) &&
3735
	    !of_property_read_u32(np, "eeprom-length", &eeprom_len))
3736
		chip->eeprom_len = eeprom_len;
3737

3738
	err = mv88e6xxx_mdio_register(chip, np);
3739 3740 3741
	if (err)
		return err;

3742
	err = mv88e6xxx_register_switch(chip, np);
3743
	if (err) {
3744
		mv88e6xxx_mdio_unregister(chip);
3745 3746 3747
		return err;
	}

3748 3749
	return 0;
}
3750 3751 3752 3753

static void mv88e6xxx_remove(struct mdio_device *mdiodev)
{
	struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
V
Vivien Didelot 已提交
3754
	struct mv88e6xxx_chip *chip = ds->priv;
3755

3756
	mv88e6xxx_phy_destroy(chip);
3757 3758
	mv88e6xxx_unregister_switch(chip);
	mv88e6xxx_mdio_unregister(chip);
3759 3760 3761
}

static const struct of_device_id mv88e6xxx_of_match[] = {
3762 3763 3764 3765
	{
		.compatible = "marvell,mv88e6085",
		.data = &mv88e6xxx_table[MV88E6085],
	},
3766 3767 3768 3769 3770 3771 3772 3773 3774 3775 3776 3777 3778 3779 3780 3781
	{ /* sentinel */ },
};

MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);

static struct mdio_driver mv88e6xxx_driver = {
	.probe	= mv88e6xxx_probe,
	.remove = mv88e6xxx_remove,
	.mdiodrv.driver = {
		.name = "mv88e6085",
		.of_match_table = mv88e6xxx_of_match,
	},
};

static int __init mv88e6xxx_init(void)
{
3782
	register_switch_driver(&mv88e6xxx_switch_ops);
3783 3784
	return mdio_driver_register(&mv88e6xxx_driver);
}
3785 3786 3787 3788
module_init(mv88e6xxx_init);

static void __exit mv88e6xxx_cleanup(void)
{
3789
	mdio_driver_unregister(&mv88e6xxx_driver);
3790
	unregister_switch_driver(&mv88e6xxx_switch_ops);
3791 3792
}
module_exit(mv88e6xxx_cleanup);
3793 3794 3795 3796

MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
MODULE_LICENSE("GPL");