chip.c 112.4 KB
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/*
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 * Marvell 88e6xxx Ethernet switch single-chip support
 *
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 * Copyright (c) 2008 Marvell Semiconductor
 *
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 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
 *
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 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
 *	Vivien Didelot <vivien.didelot@savoirfairelinux.com>
 *
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 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

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#include <linux/delay.h>
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#include <linux/etherdevice.h>
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#include <linux/ethtool.h>
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#include <linux/if_bridge.h>
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#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
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#include <linux/jiffies.h>
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#include <linux/list.h>
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#include <linux/mdio.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/of_mdio.h>
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#include <linux/netdevice.h>
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#include <linux/gpio/consumer.h>
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#include <linux/phy.h>
34
#include <net/dsa.h>
35

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#include "chip.h"
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#include "global1.h"
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#include "global2.h"
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#include "phy.h"
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#include "port.h"
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#include "serdes.h"
42

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static void assert_reg_lock(struct mv88e6xxx_chip *chip)
44
{
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	if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
		dev_err(chip->dev, "Switch registers lock not held!\n");
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		dump_stack();
	}
}

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/* The switch ADDR[4:1] configuration pins define the chip SMI device address
 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
 *
 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
 * is the only device connected to the SMI master. In this mode it responds to
 * all 32 possible SMI addresses, and thus maps directly the internal devices.
 *
 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
 * multiple devices to share the SMI interface. In this mode it responds to only
 * 2 registers, used to indirectly access the internal SMI devices.
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 */
62

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static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
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			      int addr, int reg, u16 *val)
{
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	if (!chip->smi_ops)
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		return -EOPNOTSUPP;

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	return chip->smi_ops->read(chip, addr, reg, val);
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}

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static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
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			       int addr, int reg, u16 val)
{
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	if (!chip->smi_ops)
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		return -EOPNOTSUPP;

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	return chip->smi_ops->write(chip, addr, reg, val);
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}

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static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
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					  int addr, int reg, u16 *val)
{
	int ret;

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	ret = mdiobus_read_nested(chip->bus, addr, reg);
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	if (ret < 0)
		return ret;

	*val = ret & 0xffff;

	return 0;
}

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static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
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					   int addr, int reg, u16 val)
{
	int ret;

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	ret = mdiobus_write_nested(chip->bus, addr, reg, val);
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	if (ret < 0)
		return ret;

	return 0;
}

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static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
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	.read = mv88e6xxx_smi_single_chip_read,
	.write = mv88e6xxx_smi_single_chip_write,
};

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static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
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{
	int ret;
	int i;

	for (i = 0; i < 16; i++) {
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		ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
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		if (ret < 0)
			return ret;

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		if ((ret & SMI_CMD_BUSY) == 0)
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			return 0;
	}

	return -ETIMEDOUT;
}

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static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
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					 int addr, int reg, u16 *val)
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{
	int ret;

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	/* Wait for the bus to become free. */
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	ret = mv88e6xxx_smi_multi_chip_wait(chip);
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	if (ret < 0)
		return ret;

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	/* Transmit the read command. */
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	ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
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				   SMI_CMD_OP_22_READ | (addr << 5) | reg);
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	if (ret < 0)
		return ret;

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	/* Wait for the read command to complete. */
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	ret = mv88e6xxx_smi_multi_chip_wait(chip);
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	if (ret < 0)
		return ret;

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	/* Read the data. */
151
	ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
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	if (ret < 0)
		return ret;

155
	*val = ret & 0xffff;
156

157
	return 0;
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}

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static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
161
					  int addr, int reg, u16 val)
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{
	int ret;

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	/* Wait for the bus to become free. */
166
	ret = mv88e6xxx_smi_multi_chip_wait(chip);
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	if (ret < 0)
		return ret;

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	/* Transmit the data to write. */
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	ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
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	if (ret < 0)
		return ret;

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	/* Transmit the write command. */
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	ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
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				   SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
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	if (ret < 0)
		return ret;

181
	/* Wait for the write command to complete. */
182
	ret = mv88e6xxx_smi_multi_chip_wait(chip);
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	if (ret < 0)
		return ret;

	return 0;
}

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static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
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	.read = mv88e6xxx_smi_multi_chip_read,
	.write = mv88e6xxx_smi_multi_chip_write,
};

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int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
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{
	int err;

198
	assert_reg_lock(chip);
199

200
	err = mv88e6xxx_smi_read(chip, addr, reg, val);
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	if (err)
		return err;

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	dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
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		addr, reg, *val);

	return 0;
}

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int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
211
{
212 213
	int err;

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	assert_reg_lock(chip);
215

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	err = mv88e6xxx_smi_write(chip, addr, reg, val);
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	if (err)
		return err;

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	dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
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		addr, reg, val);

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	return 0;
}

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struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
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{
	struct mv88e6xxx_mdio_bus *mdio_bus;

	mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
				    list);
	if (!mdio_bus)
		return NULL;

	return mdio_bus->bus;
}

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static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
{
	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int n = d->hwirq;

	chip->g1_irq.masked |= (1 << n);
}

static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
{
	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int n = d->hwirq;

	chip->g1_irq.masked &= ~(1 << n);
}

static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
{
	struct mv88e6xxx_chip *chip = dev_id;
	unsigned int nhandled = 0;
	unsigned int sub_irq;
	unsigned int n;
	u16 reg;
	int err;

	mutex_lock(&chip->reg_lock);
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	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
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	mutex_unlock(&chip->reg_lock);

	if (err)
		goto out;

	for (n = 0; n < chip->g1_irq.nirqs; ++n) {
		if (reg & (1 << n)) {
			sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
			handle_nested_irq(sub_irq);
			++nhandled;
		}
	}
out:
	return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
}

static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
{
	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);

	mutex_lock(&chip->reg_lock);
}

static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
{
	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
	u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
	u16 reg;
	int err;

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	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
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	if (err)
		goto out;

	reg &= ~mask;
	reg |= (~chip->g1_irq.masked & mask);

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	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
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	if (err)
		goto out;

out:
	mutex_unlock(&chip->reg_lock);
}

static struct irq_chip mv88e6xxx_g1_irq_chip = {
	.name			= "mv88e6xxx-g1",
	.irq_mask		= mv88e6xxx_g1_irq_mask,
	.irq_unmask		= mv88e6xxx_g1_irq_unmask,
	.irq_bus_lock		= mv88e6xxx_g1_irq_bus_lock,
	.irq_bus_sync_unlock	= mv88e6xxx_g1_irq_bus_sync_unlock,
};

static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
				       unsigned int irq,
				       irq_hw_number_t hwirq)
{
	struct mv88e6xxx_chip *chip = d->host_data;

	irq_set_chip_data(irq, d->host_data);
	irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
	irq_set_noprobe(irq);

	return 0;
}

static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
	.map	= mv88e6xxx_g1_irq_domain_map,
	.xlate	= irq_domain_xlate_twocell,
};

static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
{
	int irq, virq;
339 340
	u16 mask;

341
	mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
342
	mask |= GENMASK(chip->g1_irq.nirqs, 0);
343
	mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
344 345

	free_irq(chip->irq, chip);
346

347
	for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
348
		virq = irq_find_mapping(chip->g1_irq.domain, irq);
349 350 351
		irq_dispose_mapping(virq);
	}

352
	irq_domain_remove(chip->g1_irq.domain);
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}

static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
{
357 358
	int err, irq, virq;
	u16 reg, mask;
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	chip->g1_irq.nirqs = chip->info->g1_irqs;
	chip->g1_irq.domain = irq_domain_add_simple(
		NULL, chip->g1_irq.nirqs, 0,
		&mv88e6xxx_g1_irq_domain_ops, chip);
	if (!chip->g1_irq.domain)
		return -ENOMEM;

	for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
		irq_create_mapping(chip->g1_irq.domain, irq);

	chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
	chip->g1_irq.masked = ~0;

373
	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
374
	if (err)
375
		goto out_mapping;
376

377
	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
378

379
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
380
	if (err)
381
		goto out_disable;
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	/* Reading the interrupt status clears (most of) them */
384
	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
385
	if (err)
386
		goto out_disable;
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	err = request_threaded_irq(chip->irq, NULL,
				   mv88e6xxx_g1_irq_thread_fn,
				   IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
				   dev_name(chip->dev), chip);
	if (err)
393
		goto out_disable;
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	return 0;

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out_disable:
	mask |= GENMASK(chip->g1_irq.nirqs, 0);
399
	mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
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out_mapping:
	for (irq = 0; irq < 16; irq++) {
		virq = irq_find_mapping(chip->g1_irq.domain, irq);
		irq_dispose_mapping(virq);
	}

	irq_domain_remove(chip->g1_irq.domain);
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	return err;
}

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int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
413
{
414
	int i;
415

416
	for (i = 0; i < 16; i++) {
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		u16 val;
		int err;

		err = mv88e6xxx_read(chip, addr, reg, &val);
		if (err)
			return err;

		if (!(val & mask))
			return 0;

		usleep_range(1000, 2000);
	}

430
	dev_err(chip->dev, "Timeout while waiting for switch\n");
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	return -ETIMEDOUT;
}

434
/* Indirect write to single pointer-data register with an Update bit */
435
int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
436 437
{
	u16 val;
438
	int err;
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	/* Wait until the previous operation is completed */
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	err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
	if (err)
		return err;
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	/* Set the Update bit to trigger a write operation */
	val = BIT(15) | update;

	return mv88e6xxx_write(chip, addr, reg, val);
}

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static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
				    int link, int speed, int duplex,
				    phy_interface_t mode)
{
	int err;

	if (!chip->info->ops->port_set_link)
		return 0;

	/* Port's MAC control must not be changed unless the link is down */
	err = chip->info->ops->port_set_link(chip, port, 0);
	if (err)
		return err;

	if (chip->info->ops->port_set_speed) {
		err = chip->info->ops->port_set_speed(chip, port, speed);
		if (err && err != -EOPNOTSUPP)
			goto restore_link;
	}

	if (chip->info->ops->port_set_duplex) {
		err = chip->info->ops->port_set_duplex(chip, port, duplex);
		if (err && err != -EOPNOTSUPP)
			goto restore_link;
	}

	if (chip->info->ops->port_set_rgmii_delay) {
		err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
		if (err && err != -EOPNOTSUPP)
			goto restore_link;
	}

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	if (chip->info->ops->port_set_cmode) {
		err = chip->info->ops->port_set_cmode(chip, port, mode);
		if (err && err != -EOPNOTSUPP)
			goto restore_link;
	}

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	err = 0;
restore_link:
	if (chip->info->ops->port_set_link(chip, port, link))
492
		dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
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	return err;
}

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/* We expect the switch to perform auto negotiation if there is a real
 * phy. However, in the case of a fixed link phy, we force the port
 * settings from the fixed link settings.
 */
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static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
				  struct phy_device *phydev)
503
{
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	struct mv88e6xxx_chip *chip = ds->priv;
505
	int err;
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	if (!phy_is_pseudo_fixed_link(phydev))
		return;

510
	mutex_lock(&chip->reg_lock);
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	err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
				       phydev->duplex, phydev->interface);
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	mutex_unlock(&chip->reg_lock);
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	if (err && err != -EOPNOTSUPP)
516
		dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
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}

519
static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
520
{
521 522
	if (!chip->info->ops->stats_snapshot)
		return -EOPNOTSUPP;
523

524
	return chip->info->ops->stats_snapshot(chip, port);
525 526
}

527
static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
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	{ "in_good_octets",		8, 0x00, STATS_TYPE_BANK0, },
	{ "in_bad_octets",		4, 0x02, STATS_TYPE_BANK0, },
	{ "in_unicast",			4, 0x04, STATS_TYPE_BANK0, },
	{ "in_broadcasts",		4, 0x06, STATS_TYPE_BANK0, },
	{ "in_multicasts",		4, 0x07, STATS_TYPE_BANK0, },
	{ "in_pause",			4, 0x16, STATS_TYPE_BANK0, },
	{ "in_undersize",		4, 0x18, STATS_TYPE_BANK0, },
	{ "in_fragments",		4, 0x19, STATS_TYPE_BANK0, },
	{ "in_oversize",		4, 0x1a, STATS_TYPE_BANK0, },
	{ "in_jabber",			4, 0x1b, STATS_TYPE_BANK0, },
	{ "in_rx_error",		4, 0x1c, STATS_TYPE_BANK0, },
	{ "in_fcs_error",		4, 0x1d, STATS_TYPE_BANK0, },
	{ "out_octets",			8, 0x0e, STATS_TYPE_BANK0, },
	{ "out_unicast",		4, 0x10, STATS_TYPE_BANK0, },
	{ "out_broadcasts",		4, 0x13, STATS_TYPE_BANK0, },
	{ "out_multicasts",		4, 0x12, STATS_TYPE_BANK0, },
	{ "out_pause",			4, 0x15, STATS_TYPE_BANK0, },
	{ "excessive",			4, 0x11, STATS_TYPE_BANK0, },
	{ "collisions",			4, 0x1e, STATS_TYPE_BANK0, },
	{ "deferred",			4, 0x05, STATS_TYPE_BANK0, },
	{ "single",			4, 0x14, STATS_TYPE_BANK0, },
	{ "multiple",			4, 0x17, STATS_TYPE_BANK0, },
	{ "out_fcs_error",		4, 0x03, STATS_TYPE_BANK0, },
	{ "late",			4, 0x1f, STATS_TYPE_BANK0, },
	{ "hist_64bytes",		4, 0x08, STATS_TYPE_BANK0, },
	{ "hist_65_127bytes",		4, 0x09, STATS_TYPE_BANK0, },
	{ "hist_128_255bytes",		4, 0x0a, STATS_TYPE_BANK0, },
	{ "hist_256_511bytes",		4, 0x0b, STATS_TYPE_BANK0, },
	{ "hist_512_1023bytes",		4, 0x0c, STATS_TYPE_BANK0, },
	{ "hist_1024_max_bytes",	4, 0x0d, STATS_TYPE_BANK0, },
	{ "sw_in_discards",		4, 0x10, STATS_TYPE_PORT, },
	{ "sw_in_filtered",		2, 0x12, STATS_TYPE_PORT, },
	{ "sw_out_filtered",		2, 0x13, STATS_TYPE_PORT, },
	{ "in_discards",		4, 0x00, STATS_TYPE_BANK1, },
	{ "in_filtered",		4, 0x01, STATS_TYPE_BANK1, },
	{ "in_accepted",		4, 0x02, STATS_TYPE_BANK1, },
	{ "in_bad_accepted",		4, 0x03, STATS_TYPE_BANK1, },
	{ "in_good_avb_class_a",	4, 0x04, STATS_TYPE_BANK1, },
	{ "in_good_avb_class_b",	4, 0x05, STATS_TYPE_BANK1, },
	{ "in_bad_avb_class_a",		4, 0x06, STATS_TYPE_BANK1, },
	{ "in_bad_avb_class_b",		4, 0x07, STATS_TYPE_BANK1, },
	{ "tcam_counter_0",		4, 0x08, STATS_TYPE_BANK1, },
	{ "tcam_counter_1",		4, 0x09, STATS_TYPE_BANK1, },
	{ "tcam_counter_2",		4, 0x0a, STATS_TYPE_BANK1, },
	{ "tcam_counter_3",		4, 0x0b, STATS_TYPE_BANK1, },
	{ "in_da_unknown",		4, 0x0e, STATS_TYPE_BANK1, },
	{ "in_management",		4, 0x0f, STATS_TYPE_BANK1, },
	{ "out_queue_0",		4, 0x10, STATS_TYPE_BANK1, },
	{ "out_queue_1",		4, 0x11, STATS_TYPE_BANK1, },
	{ "out_queue_2",		4, 0x12, STATS_TYPE_BANK1, },
	{ "out_queue_3",		4, 0x13, STATS_TYPE_BANK1, },
	{ "out_queue_4",		4, 0x14, STATS_TYPE_BANK1, },
	{ "out_queue_5",		4, 0x15, STATS_TYPE_BANK1, },
	{ "out_queue_6",		4, 0x16, STATS_TYPE_BANK1, },
	{ "out_queue_7",		4, 0x17, STATS_TYPE_BANK1, },
	{ "out_cut_through",		4, 0x18, STATS_TYPE_BANK1, },
	{ "out_octets_a",		4, 0x1a, STATS_TYPE_BANK1, },
	{ "out_octets_b",		4, 0x1b, STATS_TYPE_BANK1, },
	{ "out_management",		4, 0x1f, STATS_TYPE_BANK1, },
587 588
};

589
static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
590
					    struct mv88e6xxx_hw_stat *s,
591 592
					    int port, u16 bank1_select,
					    u16 histogram)
593 594 595
{
	u32 low;
	u32 high = 0;
596
	u16 reg = 0;
597
	int err;
598 599
	u64 value;

600
	switch (s->type) {
601
	case STATS_TYPE_PORT:
602 603
		err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
		if (err)
604 605
			return UINT64_MAX;

606
		low = reg;
607
		if (s->sizeof_stat == 4) {
608 609
			err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
			if (err)
610
				return UINT64_MAX;
611
			high = reg;
612
		}
613
		break;
614
	case STATS_TYPE_BANK1:
615
		reg = bank1_select;
616 617
		/* fall through */
	case STATS_TYPE_BANK0:
618
		reg |= s->reg | histogram;
619
		mv88e6xxx_g1_stats_read(chip, reg, &low);
620
		if (s->sizeof_stat == 8)
621
			mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
622 623 624
		break;
	default:
		return UINT64_MAX;
625 626 627 628 629
	}
	value = (((u64)high) << 16) | low;
	return value;
}

630 631
static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
					uint8_t *data, int types)
632
{
633 634
	struct mv88e6xxx_hw_stat *stat;
	int i, j;
635

636 637
	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
		stat = &mv88e6xxx_hw_stats[i];
638
		if (stat->type & types) {
639 640 641 642
			memcpy(data + j * ETH_GSTRING_LEN, stat->string,
			       ETH_GSTRING_LEN);
			j++;
		}
643
	}
644 645
}

646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661
static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
					uint8_t *data)
{
	mv88e6xxx_stats_get_strings(chip, data,
				    STATS_TYPE_BANK0 | STATS_TYPE_PORT);
}

static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
					uint8_t *data)
{
	mv88e6xxx_stats_get_strings(chip, data,
				    STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
}

static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
				  uint8_t *data)
662
{
V
Vivien Didelot 已提交
663
	struct mv88e6xxx_chip *chip = ds->priv;
664 665 666 667 668 669 670 671

	if (chip->info->ops->stats_get_strings)
		chip->info->ops->stats_get_strings(chip, data);
}

static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
					  int types)
{
672 673 674 675 676
	struct mv88e6xxx_hw_stat *stat;
	int i, j;

	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
		stat = &mv88e6xxx_hw_stats[i];
677
		if (stat->type & types)
678 679 680
			j++;
	}
	return j;
681 682
}

683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704
static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
{
	return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
					      STATS_TYPE_PORT);
}

static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
{
	return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
					      STATS_TYPE_BANK1);
}

static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
{
	struct mv88e6xxx_chip *chip = ds->priv;

	if (chip->info->ops->stats_get_sset_count)
		return chip->info->ops->stats_get_sset_count(chip);

	return 0;
}

705
static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
706 707
				      uint64_t *data, int types,
				      u16 bank1_select, u16 histogram)
708 709 710 711 712 713 714
{
	struct mv88e6xxx_hw_stat *stat;
	int i, j;

	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
		stat = &mv88e6xxx_hw_stats[i];
		if (stat->type & types) {
715 716 717
			data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
							      bank1_select,
							      histogram);
718 719 720 721 722 723 724 725 726
			j++;
		}
	}
}

static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
				      uint64_t *data)
{
	return mv88e6xxx_stats_get_stats(chip, port, data,
727
					 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
728
					 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
729 730 731 732 733 734
}

static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
				      uint64_t *data)
{
	return mv88e6xxx_stats_get_stats(chip, port, data,
735
					 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
736 737
					 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
					 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
738 739 740 741 742 743 744
}

static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
				      uint64_t *data)
{
	return mv88e6xxx_stats_get_stats(chip, port, data,
					 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
745 746
					 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
					 0);
747 748 749 750 751 752 753 754 755
}

static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
				uint64_t *data)
{
	if (chip->info->ops->stats_get_stats)
		chip->info->ops->stats_get_stats(chip, port, data);
}

756 757
static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
					uint64_t *data)
758
{
V
Vivien Didelot 已提交
759
	struct mv88e6xxx_chip *chip = ds->priv;
760 761
	int ret;

762
	mutex_lock(&chip->reg_lock);
763

764
	ret = mv88e6xxx_stats_snapshot(chip, port);
765
	if (ret < 0) {
766
		mutex_unlock(&chip->reg_lock);
767 768
		return;
	}
769 770

	mv88e6xxx_get_stats(chip, port, data);
771

772
	mutex_unlock(&chip->reg_lock);
773 774
}

775 776 777 778 779 780 781 782
static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->stats_set_histogram)
		return chip->info->ops->stats_set_histogram(chip);

	return 0;
}

783
static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
784 785 786 787
{
	return 32 * sizeof(u16);
}

788 789
static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
			       struct ethtool_regs *regs, void *_p)
790
{
V
Vivien Didelot 已提交
791
	struct mv88e6xxx_chip *chip = ds->priv;
792 793
	int err;
	u16 reg;
794 795 796 797 798 799 800
	u16 *p = _p;
	int i;

	regs->version = 0;

	memset(p, 0xff, 32 * sizeof(u16));

801
	mutex_lock(&chip->reg_lock);
802

803 804
	for (i = 0; i < 32; i++) {

805 806 807
		err = mv88e6xxx_port_read(chip, port, i, &reg);
		if (!err)
			p[i] = reg;
808
	}
809

810
	mutex_unlock(&chip->reg_lock);
811 812
}

V
Vivien Didelot 已提交
813 814
static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
				 struct ethtool_eee *e)
815
{
816 817
	/* Nothing to do on the port's MAC */
	return 0;
818 819
}

V
Vivien Didelot 已提交
820 821
static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
				 struct ethtool_eee *e)
822
{
823 824
	/* Nothing to do on the port's MAC */
	return 0;
825 826
}

827
static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
828
{
829 830 831
	struct dsa_switch *ds = NULL;
	struct net_device *br;
	u16 pvlan;
832 833
	int i;

834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859
	if (dev < DSA_MAX_SWITCHES)
		ds = chip->ds->dst->ds[dev];

	/* Prevent frames from unknown switch or port */
	if (!ds || port >= ds->num_ports)
		return 0;

	/* Frames from DSA links and CPU ports can egress any local port */
	if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
		return mv88e6xxx_port_mask(chip);

	br = ds->ports[port].bridge_dev;
	pvlan = 0;

	/* Frames from user ports can egress any local DSA links and CPU ports,
	 * as well as any local member of their bridge group.
	 */
	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
		if (dsa_is_cpu_port(chip->ds, i) ||
		    dsa_is_dsa_port(chip->ds, i) ||
		    (br && chip->ds->ports[i].bridge_dev == br))
			pvlan |= BIT(i);

	return pvlan;
}

860
static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
861 862
{
	u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
863 864 865

	/* prevent frames from going back out of the port they came in on */
	output_ports &= ~BIT(port);
866

867
	return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
868 869
}

870 871
static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
					 u8 state)
872
{
V
Vivien Didelot 已提交
873
	struct mv88e6xxx_chip *chip = ds->priv;
874
	int err;
875

876
	mutex_lock(&chip->reg_lock);
877
	err = mv88e6xxx_port_set_state(chip, port, state);
878
	mutex_unlock(&chip->reg_lock);
879 880

	if (err)
881
		dev_err(ds->dev, "p%d: failed to update state\n", port);
882 883
}

884 885 886 887 888 889 890 891
static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->pot_clear)
		return chip->info->ops->pot_clear(chip);

	return 0;
}

892 893 894 895 896 897 898 899
static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->mgmt_rsvd2cpu)
		return chip->info->ops->mgmt_rsvd2cpu(chip);

	return 0;
}

900 901
static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
{
902 903
	int err;

904 905 906 907
	err = mv88e6xxx_g1_atu_flush(chip, 0, true);
	if (err)
		return err;

908 909 910 911
	err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
	if (err)
		return err;

912 913 914
	return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
}

915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934
static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
{
	int port;
	int err;

	if (!chip->info->ops->irl_init_all)
		return 0;

	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
		/* Disable ingress rate limiting by resetting all per port
		 * ingress rate limit resources to their initial state.
		 */
		err = chip->info->ops->irl_init_all(chip, port);
		if (err)
			return err;
	}

	return 0;
}

935 936 937 938 939 940 941 942 943
static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
{
	u16 pvlan = 0;

	if (!mv88e6xxx_has_pvt(chip))
		return -EOPNOTSUPP;

	/* Skip the local source device, which uses in-chip port VLAN */
	if (dev != chip->ds->index)
944
		pvlan = mv88e6xxx_port_vlan(chip, dev, port);
945 946 947 948

	return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
}

949 950
static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
{
951 952 953
	int dev, port;
	int err;

954 955 956 957 958 959
	if (!mv88e6xxx_has_pvt(chip))
		return 0;

	/* Clear 5 Bit Port for usage with Marvell Link Street devices:
	 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
	 */
960 961 962 963 964 965 966 967 968 969 970 971 972
	err = mv88e6xxx_g2_misc_4_bit_port(chip);
	if (err)
		return err;

	for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
		for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
			err = mv88e6xxx_pvt_map(chip, dev, port);
			if (err)
				return err;
		}
	}

	return 0;
973 974
}

975 976 977 978 979 980
static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int err;

	mutex_lock(&chip->reg_lock);
981
	err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
982 983 984
	mutex_unlock(&chip->reg_lock);

	if (err)
985
		dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
986 987
}

988 989 990 991 992 993 994 995
static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
{
	if (!chip->info->max_vid)
		return 0;

	return mv88e6xxx_g1_vtu_flush(chip);
}

996 997 998 999 1000 1001 1002 1003 1004
static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
				 struct mv88e6xxx_vtu_entry *entry)
{
	if (!chip->info->ops->vtu_getnext)
		return -EOPNOTSUPP;

	return chip->info->ops->vtu_getnext(chip, entry);
}

1005 1006 1007 1008 1009 1010 1011 1012 1013
static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
				   struct mv88e6xxx_vtu_entry *entry)
{
	if (!chip->info->ops->vtu_loadpurge)
		return -EOPNOTSUPP;

	return chip->info->ops->vtu_loadpurge(chip, entry);
}

1014
static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1015 1016
{
	DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1017 1018 1019
	struct mv88e6xxx_vtu_entry vlan = {
		.vid = chip->info->max_vid,
	};
1020
	int i, err;
1021 1022 1023

	bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);

1024
	/* Set every FID bit used by the (un)bridged ports */
1025
	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1026
		err = mv88e6xxx_port_get_fid(chip, i, fid);
1027 1028 1029 1030 1031 1032
		if (err)
			return err;

		set_bit(*fid, fid_bitmap);
	}

1033 1034
	/* Set every FID bit used by the VLAN entries */
	do {
1035
		err = mv88e6xxx_vtu_getnext(chip, &vlan);
1036 1037 1038 1039 1040 1041 1042
		if (err)
			return err;

		if (!vlan.valid)
			break;

		set_bit(vlan.fid, fid_bitmap);
1043
	} while (vlan.vid < chip->info->max_vid);
1044 1045 1046 1047 1048

	/* The reset value 0x000 is used to indicate that multiple address
	 * databases are not needed. Return the next positive available.
	 */
	*fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1049
	if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1050 1051 1052
		return -ENOSPC;

	/* Clear the database */
1053
	return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1054 1055
}

1056 1057
static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
			     struct mv88e6xxx_vtu_entry *entry, bool new)
1058 1059 1060 1061 1062 1063
{
	int err;

	if (!vid)
		return -EINVAL;

1064 1065
	entry->vid = vid - 1;
	entry->valid = false;
1066

1067
	err = mv88e6xxx_vtu_getnext(chip, entry);
1068 1069 1070
	if (err)
		return err;

1071 1072
	if (entry->vid == vid && entry->valid)
		return 0;
1073

1074 1075 1076 1077 1078 1079 1080 1081
	if (new) {
		int i;

		/* Initialize a fresh VLAN entry */
		memset(entry, 0, sizeof(*entry));
		entry->valid = true;
		entry->vid = vid;

1082
		/* Exclude all ports */
1083
		for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1084
			entry->member[i] =
1085
				MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1086 1087

		return mv88e6xxx_atu_new(chip, &entry->fid);
1088 1089
	}

1090 1091
	/* switchdev expects -EOPNOTSUPP to honor software VLANs */
	return -EOPNOTSUPP;
1092 1093
}

1094 1095 1096
static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
					u16 vid_begin, u16 vid_end)
{
V
Vivien Didelot 已提交
1097
	struct mv88e6xxx_chip *chip = ds->priv;
1098 1099 1100
	struct mv88e6xxx_vtu_entry vlan = {
		.vid = vid_begin - 1,
	};
1101 1102 1103 1104 1105
	int i, err;

	if (!vid_begin)
		return -EOPNOTSUPP;

1106
	mutex_lock(&chip->reg_lock);
1107 1108

	do {
1109
		err = mv88e6xxx_vtu_getnext(chip, &vlan);
1110 1111 1112 1113 1114 1115 1116 1117 1118
		if (err)
			goto unlock;

		if (!vlan.valid)
			break;

		if (vlan.vid > vid_end)
			break;

1119
		for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1120 1121 1122
			if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
				continue;

1123 1124 1125
			if (!ds->ports[port].netdev)
				continue;

1126
			if (vlan.member[i] ==
1127
			    MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1128 1129
				continue;

1130 1131
			if (ds->ports[i].bridge_dev ==
			    ds->ports[port].bridge_dev)
1132 1133
				break; /* same bridge, check next VLAN */

1134
			if (!ds->ports[i].bridge_dev)
1135 1136
				continue;

1137 1138 1139
			dev_err(ds->dev, "p%d: hw VLAN %d already used by %s\n",
				port, vlan.vid,
				netdev_name(ds->ports[i].bridge_dev));
1140 1141 1142 1143 1144 1145
			err = -EOPNOTSUPP;
			goto unlock;
		}
	} while (vlan.vid < vid_end);

unlock:
1146
	mutex_unlock(&chip->reg_lock);
1147 1148 1149 1150

	return err;
}

1151 1152
static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
					 bool vlan_filtering)
1153
{
V
Vivien Didelot 已提交
1154
	struct mv88e6xxx_chip *chip = ds->priv;
1155 1156
	u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
		MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1157
	int err;
1158

1159
	if (!chip->info->max_vid)
1160 1161
		return -EOPNOTSUPP;

1162
	mutex_lock(&chip->reg_lock);
1163
	err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1164
	mutex_unlock(&chip->reg_lock);
1165

1166
	return err;
1167 1168
}

1169 1170 1171 1172
static int
mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
			    const struct switchdev_obj_port_vlan *vlan,
			    struct switchdev_trans *trans)
1173
{
V
Vivien Didelot 已提交
1174
	struct mv88e6xxx_chip *chip = ds->priv;
1175 1176
	int err;

1177
	if (!chip->info->max_vid)
1178 1179
		return -EOPNOTSUPP;

1180 1181 1182 1183 1184 1185 1186 1187
	/* If the requested port doesn't belong to the same bridge as the VLAN
	 * members, do not support it (yet) and fallback to software VLAN.
	 */
	err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
					   vlan->vid_end);
	if (err)
		return err;

1188 1189 1190 1191 1192 1193
	/* We don't need any dynamic resource from the kernel (yet),
	 * so skip the prepare phase.
	 */
	return 0;
}

1194
static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1195
				    u16 vid, u8 member)
1196
{
1197
	struct mv88e6xxx_vtu_entry vlan;
1198 1199
	int err;

1200
	err = mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1201
	if (err)
1202
		return err;
1203

1204
	vlan.member[port] = member;
1205

1206
	return mv88e6xxx_vtu_loadpurge(chip, &vlan);
1207 1208
}

1209 1210 1211
static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
				    const struct switchdev_obj_port_vlan *vlan,
				    struct switchdev_trans *trans)
1212
{
V
Vivien Didelot 已提交
1213
	struct mv88e6xxx_chip *chip = ds->priv;
1214 1215
	bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
	bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1216
	u8 member;
1217 1218
	u16 vid;

1219
	if (!chip->info->max_vid)
1220 1221
		return;

1222
	if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1223
		member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
1224
	else if (untagged)
1225
		member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
1226
	else
1227
		member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
1228

1229
	mutex_lock(&chip->reg_lock);
1230

1231
	for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1232
		if (_mv88e6xxx_port_vlan_add(chip, port, vid, member))
1233 1234
			dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
				vid, untagged ? 'u' : 't');
1235

1236
	if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
1237 1238
		dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
			vlan->vid_end);
1239

1240
	mutex_unlock(&chip->reg_lock);
1241 1242
}

1243
static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1244
				    int port, u16 vid)
1245
{
1246
	struct mv88e6xxx_vtu_entry vlan;
1247 1248
	int i, err;

1249
	err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1250
	if (err)
1251
		return err;
1252

1253
	/* Tell switchdev if this VLAN is handled in software */
1254
	if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1255
		return -EOPNOTSUPP;
1256

1257
	vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1258 1259

	/* keep the VLAN unless all ports are excluded */
1260
	vlan.valid = false;
1261
	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1262 1263
		if (vlan.member[i] !=
		    MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1264
			vlan.valid = true;
1265 1266 1267 1268
			break;
		}
	}

1269
	err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1270 1271 1272
	if (err)
		return err;

1273
	return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
1274 1275
}

1276 1277
static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
				   const struct switchdev_obj_port_vlan *vlan)
1278
{
V
Vivien Didelot 已提交
1279
	struct mv88e6xxx_chip *chip = ds->priv;
1280 1281 1282
	u16 pvid, vid;
	int err = 0;

1283
	if (!chip->info->max_vid)
1284 1285
		return -EOPNOTSUPP;

1286
	mutex_lock(&chip->reg_lock);
1287

1288
	err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1289 1290 1291
	if (err)
		goto unlock;

1292
	for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1293
		err = _mv88e6xxx_port_vlan_del(chip, port, vid);
1294 1295 1296 1297
		if (err)
			goto unlock;

		if (vid == pvid) {
1298
			err = mv88e6xxx_port_set_pvid(chip, port, 0);
1299 1300 1301 1302 1303
			if (err)
				goto unlock;
		}
	}

1304
unlock:
1305
	mutex_unlock(&chip->reg_lock);
1306 1307 1308 1309

	return err;
}

1310 1311 1312
static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
					const unsigned char *addr, u16 vid,
					u8 state)
1313
{
1314
	struct mv88e6xxx_vtu_entry vlan;
1315
	struct mv88e6xxx_atu_entry entry;
1316 1317
	int err;

1318 1319
	/* Null VLAN ID corresponds to the port private database */
	if (vid == 0)
1320
		err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
1321
	else
1322
		err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1323 1324
	if (err)
		return err;
1325

1326
	entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1327 1328 1329 1330
	ether_addr_copy(entry.mac, addr);
	eth_addr_dec(entry.mac);

	err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
1331 1332 1333
	if (err)
		return err;

1334
	/* Initialize a fresh ATU entry if it isn't found */
1335
	if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED ||
1336 1337 1338 1339 1340
	    !ether_addr_equal(entry.mac, addr)) {
		memset(&entry, 0, sizeof(entry));
		ether_addr_copy(entry.mac, addr);
	}

1341
	/* Purge the ATU entry only if no port is using it anymore */
1342
	if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
1343 1344
		entry.portvec &= ~BIT(port);
		if (!entry.portvec)
1345
			entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1346
	} else {
1347
		entry.portvec |= BIT(port);
1348
		entry.state = state;
1349 1350
	}

1351
	return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
1352 1353
}

1354 1355
static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
				  const unsigned char *addr, u16 vid)
1356
{
V
Vivien Didelot 已提交
1357
	struct mv88e6xxx_chip *chip = ds->priv;
1358
	int err;
1359

1360
	mutex_lock(&chip->reg_lock);
1361 1362
	err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
					   MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1363
	mutex_unlock(&chip->reg_lock);
1364 1365

	return err;
1366 1367
}

1368
static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1369
				  const unsigned char *addr, u16 vid)
1370
{
V
Vivien Didelot 已提交
1371
	struct mv88e6xxx_chip *chip = ds->priv;
1372
	int err;
1373

1374
	mutex_lock(&chip->reg_lock);
1375
	err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1376
					   MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
1377
	mutex_unlock(&chip->reg_lock);
1378

1379
	return err;
1380 1381
}

1382 1383 1384
static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
				      u16 fid, u16 vid, int port,
				      struct switchdev_obj *obj,
1385
				      switchdev_obj_dump_cb_t *cb)
1386
{
1387
	struct mv88e6xxx_atu_entry addr;
1388 1389
	int err;

1390
	addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1391
	eth_broadcast_addr(addr.mac);
1392 1393

	do {
1394
		err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
1395
		if (err)
1396
			return err;
1397

1398
		if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED)
1399 1400
			break;

1401
		if (addr.trunk || (addr.portvec & BIT(port)) == 0)
1402 1403 1404 1405
			continue;

		if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
			struct switchdev_obj_port_fdb *fdb;
1406

1407 1408 1409 1410
			if (!is_unicast_ether_addr(addr.mac))
				continue;

			fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
1411 1412
			fdb->vid = vid;
			ether_addr_copy(fdb->addr, addr.mac);
1413
			if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
1414 1415 1416 1417 1418
				fdb->ndm_state = NUD_NOARP;
			else
				fdb->ndm_state = NUD_REACHABLE;
		} else {
			return -EOPNOTSUPP;
1419
		}
1420 1421 1422 1423

		err = cb(obj);
		if (err)
			return err;
1424 1425 1426 1427 1428
	} while (!is_broadcast_ether_addr(addr.mac));

	return err;
}

1429 1430
static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
				  struct switchdev_obj *obj,
1431
				  switchdev_obj_dump_cb_t *cb)
1432
{
1433
	struct mv88e6xxx_vtu_entry vlan = {
1434
		.vid = chip->info->max_vid,
1435
	};
1436
	u16 fid;
1437 1438
	int err;

1439
	/* Dump port's default Filtering Information Database (VLAN ID 0) */
1440
	err = mv88e6xxx_port_get_fid(chip, port, &fid);
1441
	if (err)
1442
		return err;
1443

1444
	err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
1445
	if (err)
1446
		return err;
1447

1448
	/* Dump VLANs' Filtering Information Databases */
1449
	do {
1450
		err = mv88e6xxx_vtu_getnext(chip, &vlan);
1451
		if (err)
1452
			return err;
1453 1454 1455 1456

		if (!vlan.valid)
			break;

1457 1458
		err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
						 obj, cb);
1459
		if (err)
1460
			return err;
1461
	} while (vlan.vid < chip->info->max_vid);
1462

1463 1464 1465 1466 1467
	return err;
}

static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
				   struct switchdev_obj_port_fdb *fdb,
1468
				   switchdev_obj_dump_cb_t *cb)
1469
{
V
Vivien Didelot 已提交
1470
	struct mv88e6xxx_chip *chip = ds->priv;
1471 1472 1473 1474
	int err;

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
1475
	mutex_unlock(&chip->reg_lock);
1476 1477 1478 1479

	return err;
}

1480 1481
static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
				struct net_device *br)
1482
{
1483
	struct dsa_switch *ds;
1484
	int port;
1485
	int dev;
1486
	int err;
1487

1488 1489 1490 1491
	/* Remap the Port VLAN of each local bridge group member */
	for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
		if (chip->ds->ports[port].bridge_dev == br) {
			err = mv88e6xxx_port_vlan_map(chip, port);
1492
			if (err)
1493
				return err;
1494 1495 1496
		}
	}

1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514
	if (!mv88e6xxx_has_pvt(chip))
		return 0;

	/* Remap the Port VLAN of each cross-chip bridge group member */
	for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) {
		ds = chip->ds->dst->ds[dev];
		if (!ds)
			break;

		for (port = 0; port < ds->num_ports; ++port) {
			if (ds->ports[port].bridge_dev == br) {
				err = mv88e6xxx_pvt_map(chip, dev, port);
				if (err)
					return err;
			}
		}
	}

1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525
	return 0;
}

static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
				      struct net_device *br)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int err;

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_bridge_map(chip, br);
1526
	mutex_unlock(&chip->reg_lock);
1527

1528
	return err;
1529 1530
}

1531 1532
static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
					struct net_device *br)
1533
{
V
Vivien Didelot 已提交
1534
	struct mv88e6xxx_chip *chip = ds->priv;
1535

1536
	mutex_lock(&chip->reg_lock);
1537 1538 1539
	if (mv88e6xxx_bridge_map(chip, br) ||
	    mv88e6xxx_port_vlan_map(chip, port))
		dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
1540
	mutex_unlock(&chip->reg_lock);
1541 1542
}

1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572
static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
					   int port, struct net_device *br)
{
	struct mv88e6xxx_chip *chip = ds->priv;
	int err;

	if (!mv88e6xxx_has_pvt(chip))
		return 0;

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_pvt_map(chip, dev, port);
	mutex_unlock(&chip->reg_lock);

	return err;
}

static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
					     int port, struct net_device *br)
{
	struct mv88e6xxx_chip *chip = ds->priv;

	if (!mv88e6xxx_has_pvt(chip))
		return;

	mutex_lock(&chip->reg_lock);
	if (mv88e6xxx_pvt_map(chip, dev, port))
		dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
	mutex_unlock(&chip->reg_lock);
}

1573 1574 1575 1576 1577 1578 1579 1580
static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
{
	if (chip->info->ops->reset)
		return chip->info->ops->reset(chip);

	return 0;
}

1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593
static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
{
	struct gpio_desc *gpiod = chip->reset;

	/* If there is a GPIO connected to the reset pin, toggle it */
	if (gpiod) {
		gpiod_set_value_cansleep(gpiod, 1);
		usleep_range(10000, 20000);
		gpiod_set_value_cansleep(gpiod, 0);
		usleep_range(10000, 20000);
	}
}

1594
static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
1595
{
1596
	int i, err;
1597

1598
	/* Set all ports to the Disabled state */
1599
	for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
1600
		err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
1601 1602
		if (err)
			return err;
1603 1604
	}

1605 1606 1607
	/* Wait for transmit queues to drain,
	 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
	 */
1608 1609
	usleep_range(2000, 4000);

1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620
	return 0;
}

static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
{
	int err;

	err = mv88e6xxx_disable_ports(chip);
	if (err)
		return err;

1621
	mv88e6xxx_hardware_reset(chip);
1622

1623
	return mv88e6xxx_software_reset(chip);
1624 1625
}

1626
static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
1627 1628
				   enum mv88e6xxx_frame_mode frame,
				   enum mv88e6xxx_egress_mode egress, u16 etype)
1629 1630 1631
{
	int err;

1632 1633 1634 1635
	if (!chip->info->ops->port_set_frame_mode)
		return -EOPNOTSUPP;

	err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
1636 1637 1638
	if (err)
		return err;

1639 1640 1641 1642 1643 1644 1645 1646
	err = chip->info->ops->port_set_frame_mode(chip, port, frame);
	if (err)
		return err;

	if (chip->info->ops->port_set_ether_type)
		return chip->info->ops->port_set_ether_type(chip, port, etype);

	return 0;
1647 1648
}

1649
static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
1650
{
1651
	return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
1652
				       MV88E6XXX_EGRESS_MODE_UNMODIFIED,
1653
				       MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
1654
}
1655

1656 1657 1658
static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
{
	return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
1659
				       MV88E6XXX_EGRESS_MODE_UNMODIFIED,
1660
				       MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
1661
}
1662

1663 1664 1665 1666
static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
{
	return mv88e6xxx_set_port_mode(chip, port,
				       MV88E6XXX_FRAME_MODE_ETHERTYPE,
1667 1668
				       MV88E6XXX_EGRESS_MODE_ETHERTYPE,
				       ETH_P_EDSA);
1669
}
1670

1671 1672 1673 1674
static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
{
	if (dsa_is_dsa_port(chip->ds, port))
		return mv88e6xxx_set_port_mode_dsa(chip, port);
1675

1676 1677
	if (dsa_is_normal_port(chip->ds, port))
		return mv88e6xxx_set_port_mode_normal(chip, port);
1678

1679 1680 1681
	/* Setup CPU port mode depending on its supported tag format */
	if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
		return mv88e6xxx_set_port_mode_dsa(chip, port);
1682

1683 1684
	if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
		return mv88e6xxx_set_port_mode_edsa(chip, port);
1685

1686
	return -EINVAL;
1687 1688
}

1689
static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
1690
{
1691
	bool message = dsa_is_dsa_port(chip->ds, port);
1692

1693
	return mv88e6xxx_port_set_message_port(chip, port, message);
1694
}
1695

1696
static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
1697
{
1698
	bool flood = port == dsa_upstream_port(chip->ds);
1699

1700 1701 1702 1703
	/* Upstream ports flood frames with unknown unicast or multicast DA */
	if (chip->info->ops->port_set_egress_floods)
		return chip->info->ops->port_set_egress_floods(chip, port,
							       flood, flood);
1704

1705
	return 0;
1706 1707
}

1708 1709 1710
static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
				  bool on)
{
1711 1712
	if (chip->info->ops->serdes_power)
		return chip->info->ops->serdes_power(chip, port, on);
1713

1714
	return 0;
1715 1716
}

1717
static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
1718
{
1719
	struct dsa_switch *ds = chip->ds;
1720
	int err;
1721
	u16 reg;
1722

1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736
	/* MAC Forcing register: don't force link, speed, duplex or flow control
	 * state to any particular values on physical ports, but force the CPU
	 * port and all DSA ports to their maximum bandwidth and full duplex.
	 */
	if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
		err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
					       SPEED_MAX, DUPLEX_FULL,
					       PHY_INTERFACE_MODE_NA);
	else
		err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
					       SPEED_UNFORCED, DUPLEX_UNFORCED,
					       PHY_INTERFACE_MODE_NA);
	if (err)
		return err;
1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751

	/* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
	 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
	 * tunneling, determine priority by looking at 802.1p and IP
	 * priority fields (IP prio has precedence), and set STP state
	 * to Forwarding.
	 *
	 * If this is the CPU link, use DSA or EDSA tagging depending
	 * on which tagging mode was configured.
	 *
	 * If this is a link to another switch, use DSA tagging mode.
	 *
	 * If this is the upstream port for this switch, enable
	 * forwarding of unknown unicasts and multicasts.
	 */
1752 1753 1754 1755
	reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
		MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
		MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
1756 1757
	if (err)
		return err;
1758

1759
	err = mv88e6xxx_setup_port_mode(chip, port);
1760 1761
	if (err)
		return err;
1762

1763
	err = mv88e6xxx_setup_egress_floods(chip, port);
1764 1765 1766
	if (err)
		return err;

1767 1768 1769
	/* Enable the SERDES interface for DSA and CPU ports. Normal
	 * ports SERDES are enabled when the port is enabled, thus
	 * saving a bit of power.
1770
	 */
1771 1772 1773 1774 1775
	if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) {
		err = mv88e6xxx_serdes_power(chip, port, true);
		if (err)
			return err;
	}
1776

1777
	/* Port Control 2: don't force a good FCS, set the maximum frame size to
1778
	 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
1779 1780 1781
	 * untagged frames on this port, do a destination address lookup on all
	 * received packets as usual, disable ARP mirroring and don't send a
	 * copy of all transmitted/received frames on this port to the CPU.
1782
	 */
1783 1784 1785
	err = mv88e6xxx_port_set_map_da(chip, port);
	if (err)
		return err;
1786

1787 1788 1789 1790
	reg = 0;
	if (chip->info->ops->port_set_upstream_port) {
		err = chip->info->ops->port_set_upstream_port(
			chip, port, dsa_upstream_port(ds));
1791 1792
		if (err)
			return err;
1793 1794
	}

1795
	err = mv88e6xxx_port_set_8021q_mode(chip, port,
1796
				MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
1797 1798 1799
	if (err)
		return err;

1800 1801
	if (chip->info->ops->port_set_jumbo_size) {
		err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
1802 1803 1804 1805
		if (err)
			return err;
	}

1806 1807 1808 1809 1810
	/* Port Association Vector: when learning source addresses
	 * of packets, add the address to the address database using
	 * a port bitmap that has only the bit for this port set and
	 * the other bits clear.
	 */
1811
	reg = 1 << port;
1812 1813
	/* Disable learning for CPU port */
	if (dsa_is_cpu_port(ds, port))
1814
		reg = 0;
1815

1816 1817
	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
				   reg);
1818 1819
	if (err)
		return err;
1820 1821

	/* Egress rate control 2: disable egress rate control. */
1822 1823
	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
				   0x0000);
1824 1825
	if (err)
		return err;
1826

1827 1828
	if (chip->info->ops->port_pause_limit) {
		err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
1829 1830
		if (err)
			return err;
1831
	}
1832

1833 1834 1835 1836 1837 1838
	if (chip->info->ops->port_disable_learn_limit) {
		err = chip->info->ops->port_disable_learn_limit(chip, port);
		if (err)
			return err;
	}

1839 1840
	if (chip->info->ops->port_disable_pri_override) {
		err = chip->info->ops->port_disable_pri_override(chip, port);
1841 1842
		if (err)
			return err;
1843
	}
1844

1845 1846
	if (chip->info->ops->port_tag_remap) {
		err = chip->info->ops->port_tag_remap(chip, port);
1847 1848
		if (err)
			return err;
1849 1850
	}

1851 1852
	if (chip->info->ops->port_egress_rate_limiting) {
		err = chip->info->ops->port_egress_rate_limiting(chip, port);
1853 1854
		if (err)
			return err;
1855 1856
	}

1857
	err = mv88e6xxx_setup_message_port(chip, port);
1858 1859
	if (err)
		return err;
1860

1861
	/* Port based VLAN map: give each port the same default address
1862 1863
	 * database, and allow bidirectional communication between the
	 * CPU and DSA port(s), and the other ports.
1864
	 */
1865
	err = mv88e6xxx_port_set_fid(chip, port, 0);
1866 1867
	if (err)
		return err;
1868

1869
	err = mv88e6xxx_port_vlan_map(chip, port);
1870 1871
	if (err)
		return err;
1872 1873 1874 1875

	/* Default VLAN ID and priority: don't set a default VLAN
	 * ID, and set the default packet priority to zero.
	 */
1876
	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
1877 1878
}

1879 1880 1881 1882
static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
				 struct phy_device *phydev)
{
	struct mv88e6xxx_chip *chip = ds->priv;
1883
	int err;
1884 1885

	mutex_lock(&chip->reg_lock);
1886
	err = mv88e6xxx_serdes_power(chip, port, true);
1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897
	mutex_unlock(&chip->reg_lock);

	return err;
}

static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port,
				   struct phy_device *phydev)
{
	struct mv88e6xxx_chip *chip = ds->priv;

	mutex_lock(&chip->reg_lock);
1898 1899
	if (mv88e6xxx_serdes_power(chip, port, false))
		dev_err(chip->dev, "failed to power off SERDES\n");
1900 1901 1902
	mutex_unlock(&chip->reg_lock);
}

1903 1904 1905
static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
				     unsigned int ageing_time)
{
V
Vivien Didelot 已提交
1906
	struct mv88e6xxx_chip *chip = ds->priv;
1907 1908 1909
	int err;

	mutex_lock(&chip->reg_lock);
1910
	err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
1911 1912 1913 1914 1915
	mutex_unlock(&chip->reg_lock);

	return err;
}

1916
static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
1917
{
1918
	struct dsa_switch *ds = chip->ds;
1919
	u32 upstream_port = dsa_upstream_port(ds);
1920
	int err;
1921

1922 1923
	if (chip->info->ops->set_cpu_port) {
		err = chip->info->ops->set_cpu_port(chip, upstream_port);
1924 1925 1926 1927
		if (err)
			return err;
	}

1928 1929
	if (chip->info->ops->set_egress_port) {
		err = chip->info->ops->set_egress_port(chip, upstream_port);
1930 1931 1932
		if (err)
			return err;
	}
1933

1934
	/* Disable remote management, and set the switch's DSA device number. */
1935 1936
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2,
				 MV88E6XXX_G1_CTL2_MULTIPLE_CASCADE |
1937
				 (ds->index & 0x1f));
1938 1939 1940
	if (err)
		return err;

1941
	/* Configure the IP ToS mapping registers. */
1942
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000);
1943
	if (err)
1944
		return err;
1945
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000);
1946
	if (err)
1947
		return err;
1948
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555);
1949
	if (err)
1950
		return err;
1951
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555);
1952
	if (err)
1953
		return err;
1954
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa);
1955
	if (err)
1956
		return err;
1957
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa);
1958
	if (err)
1959
		return err;
1960
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff);
1961
	if (err)
1962
		return err;
1963
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff);
1964
	if (err)
1965
		return err;
1966 1967

	/* Configure the IEEE 802.1p priority mapping register. */
1968
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41);
1969
	if (err)
1970
		return err;
1971

1972 1973 1974 1975 1976
	/* Initialize the statistics unit */
	err = mv88e6xxx_stats_set_histogram(chip);
	if (err)
		return err;

1977
	/* Clear the statistics counters for all ports */
1978 1979 1980
	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
				 MV88E6XXX_G1_STATS_OP_BUSY |
				 MV88E6XXX_G1_STATS_OP_FLUSH_ALL);
1981 1982 1983 1984
	if (err)
		return err;

	/* Wait for the flush to complete. */
1985
	err = mv88e6xxx_g1_stats_wait(chip);
1986 1987 1988 1989 1990 1991
	if (err)
		return err;

	return 0;
}

1992
static int mv88e6xxx_setup(struct dsa_switch *ds)
1993
{
V
Vivien Didelot 已提交
1994
	struct mv88e6xxx_chip *chip = ds->priv;
1995
	int err;
1996 1997
	int i;

1998
	chip->ds = ds;
1999
	ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
2000

2001
	mutex_lock(&chip->reg_lock);
2002

2003
	/* Setup Switch Port Registers */
2004
	for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2005 2006 2007 2008 2009 2010 2011
		err = mv88e6xxx_setup_port(chip, i);
		if (err)
			goto unlock;
	}

	/* Setup Switch Global 1 Registers */
	err = mv88e6xxx_g1_setup(chip);
2012 2013 2014
	if (err)
		goto unlock;

2015
	/* Setup Switch Global 2 Registers */
2016
	if (chip->info->global2_addr) {
2017
		err = mv88e6xxx_g2_setup(chip);
2018 2019 2020
		if (err)
			goto unlock;
	}
2021

2022 2023 2024 2025
	err = mv88e6xxx_irl_setup(chip);
	if (err)
		goto unlock;

2026 2027 2028 2029
	err = mv88e6xxx_phy_setup(chip);
	if (err)
		goto unlock;

2030 2031 2032 2033
	err = mv88e6xxx_vtu_setup(chip);
	if (err)
		goto unlock;

2034 2035 2036 2037
	err = mv88e6xxx_pvt_setup(chip);
	if (err)
		goto unlock;

2038 2039 2040 2041
	err = mv88e6xxx_atu_setup(chip);
	if (err)
		goto unlock;

2042 2043 2044 2045
	err = mv88e6xxx_pot_setup(chip);
	if (err)
		goto unlock;

2046 2047 2048
	err = mv88e6xxx_rsvd2cpu_setup(chip);
	if (err)
		goto unlock;
2049

2050
unlock:
2051
	mutex_unlock(&chip->reg_lock);
2052

2053
	return err;
2054 2055
}

2056 2057
static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
{
V
Vivien Didelot 已提交
2058
	struct mv88e6xxx_chip *chip = ds->priv;
2059 2060
	int err;

2061 2062
	if (!chip->info->ops->set_switch_mac)
		return -EOPNOTSUPP;
2063

2064 2065
	mutex_lock(&chip->reg_lock);
	err = chip->info->ops->set_switch_mac(chip, addr);
2066 2067 2068 2069 2070
	mutex_unlock(&chip->reg_lock);

	return err;
}

2071
static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
2072
{
2073 2074
	struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
	struct mv88e6xxx_chip *chip = mdio_bus->chip;
2075 2076
	u16 val;
	int err;
2077

2078 2079 2080
	if (!chip->info->ops->phy_read)
		return -EOPNOTSUPP;

2081
	mutex_lock(&chip->reg_lock);
2082
	err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
2083
	mutex_unlock(&chip->reg_lock);
2084

2085 2086 2087 2088 2089
	if (reg == MII_PHYSID2) {
		/* Some internal PHYS don't have a model number.  Use
		 * the mv88e6390 family model number instead.
		 */
		if (!(val & 0x3f0))
2090
			val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
2091 2092
	}

2093
	return err ? err : val;
2094 2095
}

2096
static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
2097
{
2098 2099
	struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
	struct mv88e6xxx_chip *chip = mdio_bus->chip;
2100
	int err;
2101

2102 2103 2104
	if (!chip->info->ops->phy_write)
		return -EOPNOTSUPP;

2105
	mutex_lock(&chip->reg_lock);
2106
	err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
2107
	mutex_unlock(&chip->reg_lock);
2108 2109

	return err;
2110 2111
}

2112
static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
2113 2114
				   struct device_node *np,
				   bool external)
2115 2116
{
	static int index;
2117
	struct mv88e6xxx_mdio_bus *mdio_bus;
2118 2119 2120
	struct mii_bus *bus;
	int err;

2121
	bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
2122 2123 2124
	if (!bus)
		return -ENOMEM;

2125
	mdio_bus = bus->priv;
2126
	mdio_bus->bus = bus;
2127
	mdio_bus->chip = chip;
2128 2129
	INIT_LIST_HEAD(&mdio_bus->list);
	mdio_bus->external = external;
2130

2131 2132
	if (np) {
		bus->name = np->full_name;
2133
		snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
2134 2135 2136 2137 2138 2139 2140
	} else {
		bus->name = "mv88e6xxx SMI";
		snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
	}

	bus->read = mv88e6xxx_mdio_read;
	bus->write = mv88e6xxx_mdio_write;
2141
	bus->parent = chip->dev;
2142

2143 2144
	if (np)
		err = of_mdiobus_register(bus, np);
2145 2146 2147
	else
		err = mdiobus_register(bus);
	if (err) {
2148
		dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
2149
		return err;
2150
	}
2151 2152 2153 2154 2155

	if (external)
		list_add_tail(&mdio_bus->list, &chip->mdios);
	else
		list_add(&mdio_bus->list, &chip->mdios);
2156 2157

	return 0;
2158
}
2159

2160 2161 2162 2163 2164
static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
	{ .compatible = "marvell,mv88e6xxx-mdio-external",
	  .data = (void *)true },
	{ },
};
2165

2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195
static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
				    struct device_node *np)
{
	const struct of_device_id *match;
	struct device_node *child;
	int err;

	/* Always register one mdio bus for the internal/default mdio
	 * bus. This maybe represented in the device tree, but is
	 * optional.
	 */
	child = of_get_child_by_name(np, "mdio");
	err = mv88e6xxx_mdio_register(chip, child, false);
	if (err)
		return err;

	/* Walk the device tree, and see if there are any other nodes
	 * which say they are compatible with the external mdio
	 * bus.
	 */
	for_each_available_child_of_node(np, child) {
		match = of_match_node(mv88e6xxx_mdio_external_match, child);
		if (match) {
			err = mv88e6xxx_mdio_register(chip, child, true);
			if (err)
				return err;
		}
	}

	return 0;
2196 2197
}

2198
static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
2199 2200

{
2201 2202
	struct mv88e6xxx_mdio_bus *mdio_bus;
	struct mii_bus *bus;
2203

2204 2205
	list_for_each_entry(mdio_bus, &chip->mdios, list) {
		bus = mdio_bus->bus;
2206

2207 2208
		mdiobus_unregister(bus);
	}
2209 2210
}

2211 2212
static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
{
V
Vivien Didelot 已提交
2213
	struct mv88e6xxx_chip *chip = ds->priv;
2214 2215 2216 2217 2218 2219 2220

	return chip->eeprom_len;
}

static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
				struct ethtool_eeprom *eeprom, u8 *data)
{
V
Vivien Didelot 已提交
2221
	struct mv88e6xxx_chip *chip = ds->priv;
2222 2223
	int err;

2224 2225
	if (!chip->info->ops->get_eeprom)
		return -EOPNOTSUPP;
2226

2227 2228
	mutex_lock(&chip->reg_lock);
	err = chip->info->ops->get_eeprom(chip, eeprom, data);
2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241
	mutex_unlock(&chip->reg_lock);

	if (err)
		return err;

	eeprom->magic = 0xc3ec4951;

	return 0;
}

static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
				struct ethtool_eeprom *eeprom, u8 *data)
{
V
Vivien Didelot 已提交
2242
	struct mv88e6xxx_chip *chip = ds->priv;
2243 2244
	int err;

2245 2246 2247
	if (!chip->info->ops->set_eeprom)
		return -EOPNOTSUPP;

2248 2249 2250 2251
	if (eeprom->magic != 0xc3ec4951)
		return -EINVAL;

	mutex_lock(&chip->reg_lock);
2252
	err = chip->info->ops->set_eeprom(chip, eeprom, data);
2253 2254 2255 2256 2257
	mutex_unlock(&chip->reg_lock);

	return err;
}

2258
static const struct mv88e6xxx_ops mv88e6085_ops = {
2259
	/* MV88E6XXX_FAMILY_6097 */
2260
	.irl_init_all = mv88e6352_g2_irl_init_all,
2261
	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2262 2263
	.phy_read = mv88e6185_phy_ppu_read,
	.phy_write = mv88e6185_phy_ppu_write,
2264
	.port_set_link = mv88e6xxx_port_set_link,
2265
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2266
	.port_set_speed = mv88e6185_port_set_speed,
2267
	.port_tag_remap = mv88e6095_port_tag_remap,
2268
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2269
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2270
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2271
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2272
	.port_pause_limit = mv88e6097_port_pause_limit,
2273
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2274
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2275
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2276 2277
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2278
	.stats_get_stats = mv88e6095_stats_get_stats,
2279 2280
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2281
	.watchdog_ops = &mv88e6097_watchdog_ops,
2282
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2283
	.pot_clear = mv88e6xxx_g2_pot_clear,
2284 2285
	.ppu_enable = mv88e6185_g1_ppu_enable,
	.ppu_disable = mv88e6185_g1_ppu_disable,
2286
	.reset = mv88e6185_g1_reset,
2287
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2288
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2289 2290 2291
};

static const struct mv88e6xxx_ops mv88e6095_ops = {
2292
	/* MV88E6XXX_FAMILY_6095 */
2293
	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2294 2295
	.phy_read = mv88e6185_phy_ppu_read,
	.phy_write = mv88e6185_phy_ppu_write,
2296
	.port_set_link = mv88e6xxx_port_set_link,
2297
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2298
	.port_set_speed = mv88e6185_port_set_speed,
2299
	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
2300
	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
2301
	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
2302
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2303 2304
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2305
	.stats_get_stats = mv88e6095_stats_get_stats,
2306
	.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2307 2308
	.ppu_enable = mv88e6185_g1_ppu_enable,
	.ppu_disable = mv88e6185_g1_ppu_disable,
2309
	.reset = mv88e6185_g1_reset,
2310
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
2311
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2312 2313
};

2314
static const struct mv88e6xxx_ops mv88e6097_ops = {
2315
	/* MV88E6XXX_FAMILY_6097 */
2316
	.irl_init_all = mv88e6352_g2_irl_init_all,
2317 2318 2319 2320 2321 2322
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_speed = mv88e6185_port_set_speed,
2323
	.port_tag_remap = mv88e6095_port_tag_remap,
2324
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2325
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2326
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2327
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2328
	.port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2329
	.port_pause_limit = mv88e6097_port_pause_limit,
2330
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2331
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2332 2333 2334 2335
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
	.stats_get_stats = mv88e6095_stats_get_stats,
2336 2337
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2338
	.watchdog_ops = &mv88e6097_watchdog_ops,
2339
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2340
	.pot_clear = mv88e6xxx_g2_pot_clear,
2341
	.reset = mv88e6352_g1_reset,
2342
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2343
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2344 2345
};

2346
static const struct mv88e6xxx_ops mv88e6123_ops = {
2347
	/* MV88E6XXX_FAMILY_6165 */
2348
	.irl_init_all = mv88e6352_g2_irl_init_all,
2349
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2350 2351
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2352
	.port_set_link = mv88e6xxx_port_set_link,
2353
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2354
	.port_set_speed = mv88e6185_port_set_speed,
2355
	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
2356
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2357
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2358
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2359
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2360 2361
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2362
	.stats_get_stats = mv88e6095_stats_get_stats,
2363 2364
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2365
	.watchdog_ops = &mv88e6097_watchdog_ops,
2366
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2367
	.pot_clear = mv88e6xxx_g2_pot_clear,
2368
	.reset = mv88e6352_g1_reset,
2369
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2370
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2371 2372 2373
};

static const struct mv88e6xxx_ops mv88e6131_ops = {
2374
	/* MV88E6XXX_FAMILY_6185 */
2375
	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2376 2377
	.phy_read = mv88e6185_phy_ppu_read,
	.phy_write = mv88e6185_phy_ppu_write,
2378
	.port_set_link = mv88e6xxx_port_set_link,
2379
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2380
	.port_set_speed = mv88e6185_port_set_speed,
2381
	.port_tag_remap = mv88e6095_port_tag_remap,
2382
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2383
	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
2384
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2385
	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
2386
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2387
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2388
	.port_pause_limit = mv88e6097_port_pause_limit,
2389
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2390 2391
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2392
	.stats_get_stats = mv88e6095_stats_get_stats,
2393 2394
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2395
	.watchdog_ops = &mv88e6097_watchdog_ops,
2396
	.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2397 2398
	.ppu_enable = mv88e6185_g1_ppu_enable,
	.ppu_disable = mv88e6185_g1_ppu_disable,
2399
	.reset = mv88e6185_g1_reset,
2400
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
2401
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2402 2403
};

2404 2405
static const struct mv88e6xxx_ops mv88e6141_ops = {
	/* MV88E6XXX_FAMILY_6341 */
2406
	.irl_init_all = mv88e6352_g2_irl_init_all,
2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
	.port_tag_remap = mv88e6095_port_tag_remap,
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2420
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2421
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2422
	.port_pause_limit = mv88e6097_port_pause_limit,
2423 2424 2425 2426 2427 2428
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
	.stats_get_stats = mv88e6390_stats_get_stats,
2429 2430
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
2431 2432
	.watchdog_ops = &mv88e6390_watchdog_ops,
	.mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
2433
	.pot_clear = mv88e6xxx_g2_pot_clear,
2434
	.reset = mv88e6352_g1_reset,
2435
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2436
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2437 2438
};

2439
static const struct mv88e6xxx_ops mv88e6161_ops = {
2440
	/* MV88E6XXX_FAMILY_6165 */
2441
	.irl_init_all = mv88e6352_g2_irl_init_all,
2442
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2443 2444
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2445
	.port_set_link = mv88e6xxx_port_set_link,
2446
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2447
	.port_set_speed = mv88e6185_port_set_speed,
2448
	.port_tag_remap = mv88e6095_port_tag_remap,
2449
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2450
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2451
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2452
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2453
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2454
	.port_pause_limit = mv88e6097_port_pause_limit,
2455
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2456
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2457
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2458 2459
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2460
	.stats_get_stats = mv88e6095_stats_get_stats,
2461 2462
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2463
	.watchdog_ops = &mv88e6097_watchdog_ops,
2464
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2465
	.pot_clear = mv88e6xxx_g2_pot_clear,
2466
	.reset = mv88e6352_g1_reset,
2467
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2468
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2469 2470 2471
};

static const struct mv88e6xxx_ops mv88e6165_ops = {
2472
	/* MV88E6XXX_FAMILY_6165 */
2473
	.irl_init_all = mv88e6352_g2_irl_init_all,
2474
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2475 2476
	.phy_read = mv88e6165_phy_read,
	.phy_write = mv88e6165_phy_write,
2477
	.port_set_link = mv88e6xxx_port_set_link,
2478
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2479
	.port_set_speed = mv88e6185_port_set_speed,
2480
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2481
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2482
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2483 2484
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2485
	.stats_get_stats = mv88e6095_stats_get_stats,
2486 2487
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2488
	.watchdog_ops = &mv88e6097_watchdog_ops,
2489
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2490
	.pot_clear = mv88e6xxx_g2_pot_clear,
2491
	.reset = mv88e6352_g1_reset,
2492
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2493
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2494 2495 2496
};

static const struct mv88e6xxx_ops mv88e6171_ops = {
2497
	/* MV88E6XXX_FAMILY_6351 */
2498
	.irl_init_all = mv88e6352_g2_irl_init_all,
2499
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2500 2501
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2502
	.port_set_link = mv88e6xxx_port_set_link,
2503
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2504
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2505
	.port_set_speed = mv88e6185_port_set_speed,
2506
	.port_tag_remap = mv88e6095_port_tag_remap,
2507
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2508
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2509
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2510
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2511
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2512
	.port_pause_limit = mv88e6097_port_pause_limit,
2513
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2514
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2515
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2516 2517
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2518
	.stats_get_stats = mv88e6095_stats_get_stats,
2519 2520
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2521
	.watchdog_ops = &mv88e6097_watchdog_ops,
2522
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2523
	.pot_clear = mv88e6xxx_g2_pot_clear,
2524
	.reset = mv88e6352_g1_reset,
2525
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2526
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2527 2528 2529
};

static const struct mv88e6xxx_ops mv88e6172_ops = {
2530
	/* MV88E6XXX_FAMILY_6352 */
2531
	.irl_init_all = mv88e6352_g2_irl_init_all,
2532 2533
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
2534
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2535 2536
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2537
	.port_set_link = mv88e6xxx_port_set_link,
2538
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2539
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2540
	.port_set_speed = mv88e6352_port_set_speed,
2541
	.port_tag_remap = mv88e6095_port_tag_remap,
2542
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2543
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2544
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2545
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2546
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2547
	.port_pause_limit = mv88e6097_port_pause_limit,
2548
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2549
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2550
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2551 2552
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2553
	.stats_get_stats = mv88e6095_stats_get_stats,
2554 2555
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2556
	.watchdog_ops = &mv88e6097_watchdog_ops,
2557
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2558
	.pot_clear = mv88e6xxx_g2_pot_clear,
2559
	.reset = mv88e6352_g1_reset,
2560
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2561
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2562
	.serdes_power = mv88e6352_serdes_power,
2563 2564 2565
};

static const struct mv88e6xxx_ops mv88e6175_ops = {
2566
	/* MV88E6XXX_FAMILY_6351 */
2567
	.irl_init_all = mv88e6352_g2_irl_init_all,
2568
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2569 2570
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2571
	.port_set_link = mv88e6xxx_port_set_link,
2572
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2573
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2574
	.port_set_speed = mv88e6185_port_set_speed,
2575
	.port_tag_remap = mv88e6095_port_tag_remap,
2576
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2577
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2578
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2579
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2580
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2581
	.port_pause_limit = mv88e6097_port_pause_limit,
2582
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2583
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2584
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2585 2586
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2587
	.stats_get_stats = mv88e6095_stats_get_stats,
2588 2589
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2590
	.watchdog_ops = &mv88e6097_watchdog_ops,
2591
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2592
	.pot_clear = mv88e6xxx_g2_pot_clear,
2593
	.reset = mv88e6352_g1_reset,
2594
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2595
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2596 2597 2598
};

static const struct mv88e6xxx_ops mv88e6176_ops = {
2599
	/* MV88E6XXX_FAMILY_6352 */
2600
	.irl_init_all = mv88e6352_g2_irl_init_all,
2601 2602
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
2603
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2604 2605
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2606
	.port_set_link = mv88e6xxx_port_set_link,
2607
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2608
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2609
	.port_set_speed = mv88e6352_port_set_speed,
2610
	.port_tag_remap = mv88e6095_port_tag_remap,
2611
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2612
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2613
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2614
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2615
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2616
	.port_pause_limit = mv88e6097_port_pause_limit,
2617
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2618
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2619
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2620 2621
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2622
	.stats_get_stats = mv88e6095_stats_get_stats,
2623 2624
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2625
	.watchdog_ops = &mv88e6097_watchdog_ops,
2626
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2627
	.pot_clear = mv88e6xxx_g2_pot_clear,
2628
	.reset = mv88e6352_g1_reset,
2629
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2630
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2631
	.serdes_power = mv88e6352_serdes_power,
2632 2633 2634
};

static const struct mv88e6xxx_ops mv88e6185_ops = {
2635
	/* MV88E6XXX_FAMILY_6185 */
2636
	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2637 2638
	.phy_read = mv88e6185_phy_ppu_read,
	.phy_write = mv88e6185_phy_ppu_write,
2639
	.port_set_link = mv88e6xxx_port_set_link,
2640
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2641
	.port_set_speed = mv88e6185_port_set_speed,
2642
	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
2643
	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
2644
	.port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2645
	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
2646
	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2647 2648
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2649
	.stats_get_stats = mv88e6095_stats_get_stats,
2650 2651
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2652
	.watchdog_ops = &mv88e6097_watchdog_ops,
2653
	.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2654 2655
	.ppu_enable = mv88e6185_g1_ppu_enable,
	.ppu_disable = mv88e6185_g1_ppu_disable,
2656
	.reset = mv88e6185_g1_reset,
2657
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
2658
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2659 2660
};

2661
static const struct mv88e6xxx_ops mv88e6190_ops = {
2662
	/* MV88E6XXX_FAMILY_6390 */
2663
	.irl_init_all = mv88e6390_g2_irl_init_all,
2664 2665
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
2666 2667 2668 2669 2670 2671 2672
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
2673
	.port_tag_remap = mv88e6390_port_tag_remap,
2674
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2675
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2676
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2677
	.port_pause_limit = mv88e6390_port_pause_limit,
2678
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2679
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2680
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
2681
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2682 2683
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
2684
	.stats_get_stats = mv88e6390_stats_get_stats,
2685 2686
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
2687
	.watchdog_ops = &mv88e6390_watchdog_ops,
2688
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2689
	.pot_clear = mv88e6xxx_g2_pot_clear,
2690
	.reset = mv88e6352_g1_reset,
2691 2692
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2693
	.serdes_power = mv88e6390_serdes_power,
2694 2695 2696
};

static const struct mv88e6xxx_ops mv88e6190x_ops = {
2697
	/* MV88E6XXX_FAMILY_6390 */
2698
	.irl_init_all = mv88e6390_g2_irl_init_all,
2699 2700
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
2701 2702 2703 2704 2705 2706 2707
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390x_port_set_speed,
2708
	.port_tag_remap = mv88e6390_port_tag_remap,
2709
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2710
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2711
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2712
	.port_pause_limit = mv88e6390_port_pause_limit,
2713
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2714
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2715
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
2716
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2717 2718
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
2719
	.stats_get_stats = mv88e6390_stats_get_stats,
2720 2721
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
2722
	.watchdog_ops = &mv88e6390_watchdog_ops,
2723
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2724
	.pot_clear = mv88e6xxx_g2_pot_clear,
2725
	.reset = mv88e6352_g1_reset,
2726 2727
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2728
	.serdes_power = mv88e6390_serdes_power,
2729 2730 2731
};

static const struct mv88e6xxx_ops mv88e6191_ops = {
2732
	/* MV88E6XXX_FAMILY_6390 */
2733
	.irl_init_all = mv88e6390_g2_irl_init_all,
2734 2735
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
2736 2737 2738 2739 2740 2741 2742
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
2743
	.port_tag_remap = mv88e6390_port_tag_remap,
2744
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2745
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2746
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2747
	.port_pause_limit = mv88e6390_port_pause_limit,
2748
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2749
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2750
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
2751
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2752 2753
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
2754
	.stats_get_stats = mv88e6390_stats_get_stats,
2755 2756
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
2757
	.watchdog_ops = &mv88e6390_watchdog_ops,
2758
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2759
	.pot_clear = mv88e6xxx_g2_pot_clear,
2760
	.reset = mv88e6352_g1_reset,
2761 2762
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2763
	.serdes_power = mv88e6390_serdes_power,
2764 2765
};

2766
static const struct mv88e6xxx_ops mv88e6240_ops = {
2767
	/* MV88E6XXX_FAMILY_6352 */
2768
	.irl_init_all = mv88e6352_g2_irl_init_all,
2769 2770
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
2771
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2772 2773
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2774
	.port_set_link = mv88e6xxx_port_set_link,
2775
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2776
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2777
	.port_set_speed = mv88e6352_port_set_speed,
2778
	.port_tag_remap = mv88e6095_port_tag_remap,
2779
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2780
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2781
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2782
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2783
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2784
	.port_pause_limit = mv88e6097_port_pause_limit,
2785
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2786
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2787
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2788 2789
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2790
	.stats_get_stats = mv88e6095_stats_get_stats,
2791 2792
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2793
	.watchdog_ops = &mv88e6097_watchdog_ops,
2794
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2795
	.pot_clear = mv88e6xxx_g2_pot_clear,
2796
	.reset = mv88e6352_g1_reset,
2797
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2798
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2799
	.serdes_power = mv88e6352_serdes_power,
2800 2801
};

2802
static const struct mv88e6xxx_ops mv88e6290_ops = {
2803
	/* MV88E6XXX_FAMILY_6390 */
2804
	.irl_init_all = mv88e6390_g2_irl_init_all,
2805 2806
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
2807 2808 2809 2810 2811 2812 2813
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
2814
	.port_tag_remap = mv88e6390_port_tag_remap,
2815
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2816
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2817
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2818
	.port_pause_limit = mv88e6390_port_pause_limit,
2819
	.port_set_cmode = mv88e6390x_port_set_cmode,
2820
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2821
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2822
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
2823
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2824 2825
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
2826
	.stats_get_stats = mv88e6390_stats_get_stats,
2827 2828
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
2829
	.watchdog_ops = &mv88e6390_watchdog_ops,
2830
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2831
	.pot_clear = mv88e6xxx_g2_pot_clear,
2832
	.reset = mv88e6352_g1_reset,
2833 2834
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2835
	.serdes_power = mv88e6390_serdes_power,
2836 2837
};

2838
static const struct mv88e6xxx_ops mv88e6320_ops = {
2839
	/* MV88E6XXX_FAMILY_6320 */
2840
	.irl_init_all = mv88e6352_g2_irl_init_all,
2841 2842
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
2843
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2844 2845
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2846
	.port_set_link = mv88e6xxx_port_set_link,
2847
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2848
	.port_set_speed = mv88e6185_port_set_speed,
2849
	.port_tag_remap = mv88e6095_port_tag_remap,
2850
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2851
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2852
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2853
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2854
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2855
	.port_pause_limit = mv88e6097_port_pause_limit,
2856
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2857
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2858
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2859 2860
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
2861
	.stats_get_stats = mv88e6320_stats_get_stats,
2862 2863
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2864
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2865
	.pot_clear = mv88e6xxx_g2_pot_clear,
2866
	.reset = mv88e6352_g1_reset,
2867
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
2868
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2869 2870 2871
};

static const struct mv88e6xxx_ops mv88e6321_ops = {
2872
	/* MV88E6XXX_FAMILY_6320 */
2873
	.irl_init_all = mv88e6352_g2_irl_init_all,
2874 2875
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
2876
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2877 2878
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2879
	.port_set_link = mv88e6xxx_port_set_link,
2880
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2881
	.port_set_speed = mv88e6185_port_set_speed,
2882
	.port_tag_remap = mv88e6095_port_tag_remap,
2883
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2884
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2885
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2886
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2887
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2888
	.port_pause_limit = mv88e6097_port_pause_limit,
2889
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2890
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2891
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2892 2893
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
2894
	.stats_get_stats = mv88e6320_stats_get_stats,
2895 2896
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2897
	.reset = mv88e6352_g1_reset,
2898
	.vtu_getnext = mv88e6185_g1_vtu_getnext,
2899
	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2900 2901
};

2902 2903
static const struct mv88e6xxx_ops mv88e6341_ops = {
	/* MV88E6XXX_FAMILY_6341 */
2904
	.irl_init_all = mv88e6352_g2_irl_init_all,
2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
	.port_tag_remap = mv88e6095_port_tag_remap,
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2918
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2919
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2920
	.port_pause_limit = mv88e6097_port_pause_limit,
2921 2922 2923 2924 2925 2926
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
	.stats_get_stats = mv88e6390_stats_get_stats,
2927 2928
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
2929 2930
	.watchdog_ops = &mv88e6390_watchdog_ops,
	.mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
2931
	.pot_clear = mv88e6xxx_g2_pot_clear,
2932
	.reset = mv88e6352_g1_reset,
2933
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2934
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2935 2936
};

2937
static const struct mv88e6xxx_ops mv88e6350_ops = {
2938
	/* MV88E6XXX_FAMILY_6351 */
2939
	.irl_init_all = mv88e6352_g2_irl_init_all,
2940
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2941 2942
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2943
	.port_set_link = mv88e6xxx_port_set_link,
2944
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2945
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2946
	.port_set_speed = mv88e6185_port_set_speed,
2947
	.port_tag_remap = mv88e6095_port_tag_remap,
2948
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2949
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2950
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2951
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2952
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2953
	.port_pause_limit = mv88e6097_port_pause_limit,
2954
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2955
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2956
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2957 2958
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2959
	.stats_get_stats = mv88e6095_stats_get_stats,
2960 2961
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2962
	.watchdog_ops = &mv88e6097_watchdog_ops,
2963
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2964
	.pot_clear = mv88e6xxx_g2_pot_clear,
2965
	.reset = mv88e6352_g1_reset,
2966
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2967
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2968 2969 2970
};

static const struct mv88e6xxx_ops mv88e6351_ops = {
2971
	/* MV88E6XXX_FAMILY_6351 */
2972
	.irl_init_all = mv88e6352_g2_irl_init_all,
2973
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2974 2975
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
2976
	.port_set_link = mv88e6xxx_port_set_link,
2977
	.port_set_duplex = mv88e6xxx_port_set_duplex,
2978
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2979
	.port_set_speed = mv88e6185_port_set_speed,
2980
	.port_tag_remap = mv88e6095_port_tag_remap,
2981
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2982
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2983
	.port_set_ether_type = mv88e6351_port_set_ether_type,
2984
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2985
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2986
	.port_pause_limit = mv88e6097_port_pause_limit,
2987
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2988
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2989
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2990 2991
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
2992
	.stats_get_stats = mv88e6095_stats_get_stats,
2993 2994
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
2995
	.watchdog_ops = &mv88e6097_watchdog_ops,
2996
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2997
	.pot_clear = mv88e6xxx_g2_pot_clear,
2998
	.reset = mv88e6352_g1_reset,
2999
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3000
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3001 3002 3003
};

static const struct mv88e6xxx_ops mv88e6352_ops = {
3004
	/* MV88E6XXX_FAMILY_6352 */
3005
	.irl_init_all = mv88e6352_g2_irl_init_all,
3006 3007
	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
3008
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3009 3010
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
3011
	.port_set_link = mv88e6xxx_port_set_link,
3012
	.port_set_duplex = mv88e6xxx_port_set_duplex,
3013
	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3014
	.port_set_speed = mv88e6352_port_set_speed,
3015
	.port_tag_remap = mv88e6095_port_tag_remap,
3016
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3017
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3018
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3019
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3020
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3021
	.port_pause_limit = mv88e6097_port_pause_limit,
3022
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3023
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3024
	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3025 3026
	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
	.stats_get_strings = mv88e6095_stats_get_strings,
3027
	.stats_get_stats = mv88e6095_stats_get_stats,
3028 3029
	.set_cpu_port = mv88e6095_g1_set_cpu_port,
	.set_egress_port = mv88e6095_g1_set_egress_port,
3030
	.watchdog_ops = &mv88e6097_watchdog_ops,
3031
	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3032
	.pot_clear = mv88e6xxx_g2_pot_clear,
3033
	.reset = mv88e6352_g1_reset,
3034
	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3035
	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3036
	.serdes_power = mv88e6352_serdes_power,
3037 3038
};

3039
static const struct mv88e6xxx_ops mv88e6390_ops = {
3040
	/* MV88E6XXX_FAMILY_6390 */
3041
	.irl_init_all = mv88e6390_g2_irl_init_all,
3042 3043
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3044 3045 3046 3047 3048 3049 3050
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
3051
	.port_tag_remap = mv88e6390_port_tag_remap,
3052
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3053
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3054
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3055
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3056
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3057
	.port_pause_limit = mv88e6390_port_pause_limit,
3058
	.port_set_cmode = mv88e6390x_port_set_cmode,
3059
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3060
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3061
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3062
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3063 3064
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3065
	.stats_get_stats = mv88e6390_stats_get_stats,
3066 3067
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3068
	.watchdog_ops = &mv88e6390_watchdog_ops,
3069
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3070
	.pot_clear = mv88e6xxx_g2_pot_clear,
3071
	.reset = mv88e6352_g1_reset,
3072 3073
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3074
	.serdes_power = mv88e6390_serdes_power,
3075 3076 3077
};

static const struct mv88e6xxx_ops mv88e6390x_ops = {
3078
	/* MV88E6XXX_FAMILY_6390 */
3079
	.irl_init_all = mv88e6390_g2_irl_init_all,
3080 3081
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3082 3083 3084 3085 3086 3087 3088
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390x_port_set_speed,
3089
	.port_tag_remap = mv88e6390_port_tag_remap,
3090
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3091
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3092
	.port_set_ether_type = mv88e6351_port_set_ether_type,
3093
	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3094
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3095
	.port_pause_limit = mv88e6390_port_pause_limit,
3096
	.port_set_cmode = mv88e6390x_port_set_cmode,
3097
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3098
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3099
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3100
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3101 3102
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
3103
	.stats_get_stats = mv88e6390_stats_get_stats,
3104 3105
	.set_cpu_port = mv88e6390_g1_set_cpu_port,
	.set_egress_port = mv88e6390_g1_set_egress_port,
3106
	.watchdog_ops = &mv88e6390_watchdog_ops,
3107
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3108
	.pot_clear = mv88e6xxx_g2_pot_clear,
3109
	.reset = mv88e6352_g1_reset,
3110 3111
	.vtu_getnext = mv88e6390_g1_vtu_getnext,
	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3112
	.serdes_power = mv88e6390_serdes_power,
3113 3114
};

3115 3116
static const struct mv88e6xxx_info mv88e6xxx_table[] = {
	[MV88E6085] = {
3117
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
3118 3119 3120 3121
		.family = MV88E6XXX_FAMILY_6097,
		.name = "Marvell 88E6085",
		.num_databases = 4096,
		.num_ports = 10,
3122
		.max_vid = 4095,
3123
		.port_base_addr = 0x10,
3124
		.global1_addr = 0x1b,
3125
		.global2_addr = 0x1c,
3126
		.age_time_coeff = 15000,
3127
		.g1_irqs = 8,
3128
		.g2_irqs = 10,
3129
		.atu_move_port_mask = 0xf,
3130
		.pvt = true,
3131
		.multi_chip = true,
3132
		.tag_protocol = DSA_TAG_PROTO_DSA,
3133
		.ops = &mv88e6085_ops,
3134 3135 3136
	},

	[MV88E6095] = {
3137
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
3138 3139 3140 3141
		.family = MV88E6XXX_FAMILY_6095,
		.name = "Marvell 88E6095/88E6095F",
		.num_databases = 256,
		.num_ports = 11,
3142
		.max_vid = 4095,
3143
		.port_base_addr = 0x10,
3144
		.global1_addr = 0x1b,
3145
		.global2_addr = 0x1c,
3146
		.age_time_coeff = 15000,
3147
		.g1_irqs = 8,
3148
		.atu_move_port_mask = 0xf,
3149
		.multi_chip = true,
3150
		.tag_protocol = DSA_TAG_PROTO_DSA,
3151
		.ops = &mv88e6095_ops,
3152 3153
	},

3154
	[MV88E6097] = {
3155
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
3156 3157 3158 3159
		.family = MV88E6XXX_FAMILY_6097,
		.name = "Marvell 88E6097/88E6097F",
		.num_databases = 4096,
		.num_ports = 11,
3160
		.max_vid = 4095,
3161 3162
		.port_base_addr = 0x10,
		.global1_addr = 0x1b,
3163
		.global2_addr = 0x1c,
3164
		.age_time_coeff = 15000,
3165
		.g1_irqs = 8,
3166
		.g2_irqs = 10,
3167
		.atu_move_port_mask = 0xf,
3168
		.pvt = true,
3169
		.multi_chip = true,
3170
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3171 3172 3173
		.ops = &mv88e6097_ops,
	},

3174
	[MV88E6123] = {
3175
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
3176 3177 3178 3179
		.family = MV88E6XXX_FAMILY_6165,
		.name = "Marvell 88E6123",
		.num_databases = 4096,
		.num_ports = 3,
3180
		.max_vid = 4095,
3181
		.port_base_addr = 0x10,
3182
		.global1_addr = 0x1b,
3183
		.global2_addr = 0x1c,
3184
		.age_time_coeff = 15000,
3185
		.g1_irqs = 9,
3186
		.g2_irqs = 10,
3187
		.atu_move_port_mask = 0xf,
3188
		.pvt = true,
3189
		.multi_chip = true,
3190
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3191
		.ops = &mv88e6123_ops,
3192 3193 3194
	},

	[MV88E6131] = {
3195
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
3196 3197 3198 3199
		.family = MV88E6XXX_FAMILY_6185,
		.name = "Marvell 88E6131",
		.num_databases = 256,
		.num_ports = 8,
3200
		.max_vid = 4095,
3201
		.port_base_addr = 0x10,
3202
		.global1_addr = 0x1b,
3203
		.global2_addr = 0x1c,
3204
		.age_time_coeff = 15000,
3205
		.g1_irqs = 9,
3206
		.atu_move_port_mask = 0xf,
3207
		.multi_chip = true,
3208
		.tag_protocol = DSA_TAG_PROTO_DSA,
3209
		.ops = &mv88e6131_ops,
3210 3211
	},

3212
	[MV88E6141] = {
3213
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
3214 3215 3216 3217
		.family = MV88E6XXX_FAMILY_6341,
		.name = "Marvell 88E6341",
		.num_databases = 4096,
		.num_ports = 6,
3218
		.max_vid = 4095,
3219 3220
		.port_base_addr = 0x10,
		.global1_addr = 0x1b,
3221
		.global2_addr = 0x1c,
3222 3223
		.age_time_coeff = 3750,
		.atu_move_port_mask = 0x1f,
3224
		.g2_irqs = 10,
3225
		.pvt = true,
3226
		.multi_chip = true,
3227 3228 3229 3230
		.tag_protocol = DSA_TAG_PROTO_EDSA,
		.ops = &mv88e6141_ops,
	},

3231
	[MV88E6161] = {
3232
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
3233 3234 3235 3236
		.family = MV88E6XXX_FAMILY_6165,
		.name = "Marvell 88E6161",
		.num_databases = 4096,
		.num_ports = 6,
3237
		.max_vid = 4095,
3238
		.port_base_addr = 0x10,
3239
		.global1_addr = 0x1b,
3240
		.global2_addr = 0x1c,
3241
		.age_time_coeff = 15000,
3242
		.g1_irqs = 9,
3243
		.g2_irqs = 10,
3244
		.atu_move_port_mask = 0xf,
3245
		.pvt = true,
3246
		.multi_chip = true,
3247
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3248
		.ops = &mv88e6161_ops,
3249 3250 3251
	},

	[MV88E6165] = {
3252
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
3253 3254 3255 3256
		.family = MV88E6XXX_FAMILY_6165,
		.name = "Marvell 88E6165",
		.num_databases = 4096,
		.num_ports = 6,
3257
		.max_vid = 4095,
3258
		.port_base_addr = 0x10,
3259
		.global1_addr = 0x1b,
3260
		.global2_addr = 0x1c,
3261
		.age_time_coeff = 15000,
3262
		.g1_irqs = 9,
3263
		.g2_irqs = 10,
3264
		.atu_move_port_mask = 0xf,
3265
		.pvt = true,
3266
		.multi_chip = true,
3267
		.tag_protocol = DSA_TAG_PROTO_DSA,
3268
		.ops = &mv88e6165_ops,
3269 3270 3271
	},

	[MV88E6171] = {
3272
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
3273 3274 3275 3276
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6171",
		.num_databases = 4096,
		.num_ports = 7,
3277
		.max_vid = 4095,
3278
		.port_base_addr = 0x10,
3279
		.global1_addr = 0x1b,
3280
		.global2_addr = 0x1c,
3281
		.age_time_coeff = 15000,
3282
		.g1_irqs = 9,
3283
		.g2_irqs = 10,
3284
		.atu_move_port_mask = 0xf,
3285
		.pvt = true,
3286
		.multi_chip = true,
3287
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3288
		.ops = &mv88e6171_ops,
3289 3290 3291
	},

	[MV88E6172] = {
3292
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
3293 3294 3295 3296
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6172",
		.num_databases = 4096,
		.num_ports = 7,
3297
		.max_vid = 4095,
3298
		.port_base_addr = 0x10,
3299
		.global1_addr = 0x1b,
3300
		.global2_addr = 0x1c,
3301
		.age_time_coeff = 15000,
3302
		.g1_irqs = 9,
3303
		.g2_irqs = 10,
3304
		.atu_move_port_mask = 0xf,
3305
		.pvt = true,
3306
		.multi_chip = true,
3307
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3308
		.ops = &mv88e6172_ops,
3309 3310 3311
	},

	[MV88E6175] = {
3312
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
3313 3314 3315 3316
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6175",
		.num_databases = 4096,
		.num_ports = 7,
3317
		.max_vid = 4095,
3318
		.port_base_addr = 0x10,
3319
		.global1_addr = 0x1b,
3320
		.global2_addr = 0x1c,
3321
		.age_time_coeff = 15000,
3322
		.g1_irqs = 9,
3323
		.g2_irqs = 10,
3324
		.atu_move_port_mask = 0xf,
3325
		.pvt = true,
3326
		.multi_chip = true,
3327
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3328
		.ops = &mv88e6175_ops,
3329 3330 3331
	},

	[MV88E6176] = {
3332
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
3333 3334 3335 3336
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6176",
		.num_databases = 4096,
		.num_ports = 7,
3337
		.max_vid = 4095,
3338
		.port_base_addr = 0x10,
3339
		.global1_addr = 0x1b,
3340
		.global2_addr = 0x1c,
3341
		.age_time_coeff = 15000,
3342
		.g1_irqs = 9,
3343
		.g2_irqs = 10,
3344
		.atu_move_port_mask = 0xf,
3345
		.pvt = true,
3346
		.multi_chip = true,
3347
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3348
		.ops = &mv88e6176_ops,
3349 3350 3351
	},

	[MV88E6185] = {
3352
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
3353 3354 3355 3356
		.family = MV88E6XXX_FAMILY_6185,
		.name = "Marvell 88E6185",
		.num_databases = 256,
		.num_ports = 10,
3357
		.max_vid = 4095,
3358
		.port_base_addr = 0x10,
3359
		.global1_addr = 0x1b,
3360
		.global2_addr = 0x1c,
3361
		.age_time_coeff = 15000,
3362
		.g1_irqs = 8,
3363
		.atu_move_port_mask = 0xf,
3364
		.multi_chip = true,
3365
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3366
		.ops = &mv88e6185_ops,
3367 3368
	},

3369
	[MV88E6190] = {
3370
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
3371 3372 3373 3374
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6190",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3375
		.max_vid = 8191,
3376 3377
		.port_base_addr = 0x0,
		.global1_addr = 0x1b,
3378
		.global2_addr = 0x1c,
3379
		.tag_protocol = DSA_TAG_PROTO_DSA,
3380
		.age_time_coeff = 3750,
3381
		.g1_irqs = 9,
3382
		.g2_irqs = 14,
3383
		.pvt = true,
3384
		.multi_chip = true,
3385
		.atu_move_port_mask = 0x1f,
3386 3387 3388 3389
		.ops = &mv88e6190_ops,
	},

	[MV88E6190X] = {
3390
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
3391 3392 3393 3394
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6190X",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3395
		.max_vid = 8191,
3396 3397
		.port_base_addr = 0x0,
		.global1_addr = 0x1b,
3398
		.global2_addr = 0x1c,
3399
		.age_time_coeff = 3750,
3400
		.g1_irqs = 9,
3401
		.g2_irqs = 14,
3402
		.atu_move_port_mask = 0x1f,
3403
		.pvt = true,
3404
		.multi_chip = true,
3405
		.tag_protocol = DSA_TAG_PROTO_DSA,
3406 3407 3408 3409
		.ops = &mv88e6190x_ops,
	},

	[MV88E6191] = {
3410
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
3411 3412 3413 3414
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6191",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3415
		.max_vid = 8191,
3416 3417
		.port_base_addr = 0x0,
		.global1_addr = 0x1b,
3418
		.global2_addr = 0x1c,
3419
		.age_time_coeff = 3750,
3420
		.g1_irqs = 9,
3421
		.g2_irqs = 14,
3422
		.atu_move_port_mask = 0x1f,
3423
		.pvt = true,
3424
		.multi_chip = true,
3425
		.tag_protocol = DSA_TAG_PROTO_DSA,
3426
		.ops = &mv88e6191_ops,
3427 3428
	},

3429
	[MV88E6240] = {
3430
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
3431 3432 3433 3434
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6240",
		.num_databases = 4096,
		.num_ports = 7,
3435
		.max_vid = 4095,
3436
		.port_base_addr = 0x10,
3437
		.global1_addr = 0x1b,
3438
		.global2_addr = 0x1c,
3439
		.age_time_coeff = 15000,
3440
		.g1_irqs = 9,
3441
		.g2_irqs = 10,
3442
		.atu_move_port_mask = 0xf,
3443
		.pvt = true,
3444
		.multi_chip = true,
3445
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3446
		.ops = &mv88e6240_ops,
3447 3448
	},

3449
	[MV88E6290] = {
3450
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
3451 3452 3453 3454
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6290",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3455
		.max_vid = 8191,
3456 3457
		.port_base_addr = 0x0,
		.global1_addr = 0x1b,
3458
		.global2_addr = 0x1c,
3459
		.age_time_coeff = 3750,
3460
		.g1_irqs = 9,
3461
		.g2_irqs = 14,
3462
		.atu_move_port_mask = 0x1f,
3463
		.pvt = true,
3464
		.multi_chip = true,
3465
		.tag_protocol = DSA_TAG_PROTO_DSA,
3466 3467 3468
		.ops = &mv88e6290_ops,
	},

3469
	[MV88E6320] = {
3470
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
3471 3472 3473 3474
		.family = MV88E6XXX_FAMILY_6320,
		.name = "Marvell 88E6320",
		.num_databases = 4096,
		.num_ports = 7,
3475
		.max_vid = 4095,
3476
		.port_base_addr = 0x10,
3477
		.global1_addr = 0x1b,
3478
		.global2_addr = 0x1c,
3479
		.age_time_coeff = 15000,
3480
		.g1_irqs = 8,
3481
		.atu_move_port_mask = 0xf,
3482
		.pvt = true,
3483
		.multi_chip = true,
3484
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3485
		.ops = &mv88e6320_ops,
3486 3487 3488
	},

	[MV88E6321] = {
3489
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
3490 3491 3492 3493
		.family = MV88E6XXX_FAMILY_6320,
		.name = "Marvell 88E6321",
		.num_databases = 4096,
		.num_ports = 7,
3494
		.max_vid = 4095,
3495
		.port_base_addr = 0x10,
3496
		.global1_addr = 0x1b,
3497
		.global2_addr = 0x1c,
3498
		.age_time_coeff = 15000,
3499
		.g1_irqs = 8,
3500
		.atu_move_port_mask = 0xf,
3501
		.multi_chip = true,
3502
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3503
		.ops = &mv88e6321_ops,
3504 3505
	},

3506
	[MV88E6341] = {
3507
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3508 3509 3510 3511
		.family = MV88E6XXX_FAMILY_6341,
		.name = "Marvell 88E6341",
		.num_databases = 4096,
		.num_ports = 6,
3512
		.max_vid = 4095,
3513 3514
		.port_base_addr = 0x10,
		.global1_addr = 0x1b,
3515
		.global2_addr = 0x1c,
3516
		.age_time_coeff = 3750,
3517
		.atu_move_port_mask = 0x1f,
3518
		.g2_irqs = 10,
3519
		.pvt = true,
3520
		.multi_chip = true,
3521 3522 3523 3524
		.tag_protocol = DSA_TAG_PROTO_EDSA,
		.ops = &mv88e6341_ops,
	},

3525
	[MV88E6350] = {
3526
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
3527 3528 3529 3530
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6350",
		.num_databases = 4096,
		.num_ports = 7,
3531
		.max_vid = 4095,
3532
		.port_base_addr = 0x10,
3533
		.global1_addr = 0x1b,
3534
		.global2_addr = 0x1c,
3535
		.age_time_coeff = 15000,
3536
		.g1_irqs = 9,
3537
		.g2_irqs = 10,
3538
		.atu_move_port_mask = 0xf,
3539
		.pvt = true,
3540
		.multi_chip = true,
3541
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3542
		.ops = &mv88e6350_ops,
3543 3544 3545
	},

	[MV88E6351] = {
3546
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
3547 3548 3549 3550
		.family = MV88E6XXX_FAMILY_6351,
		.name = "Marvell 88E6351",
		.num_databases = 4096,
		.num_ports = 7,
3551
		.max_vid = 4095,
3552
		.port_base_addr = 0x10,
3553
		.global1_addr = 0x1b,
3554
		.global2_addr = 0x1c,
3555
		.age_time_coeff = 15000,
3556
		.g1_irqs = 9,
3557
		.g2_irqs = 10,
3558
		.atu_move_port_mask = 0xf,
3559
		.pvt = true,
3560
		.multi_chip = true,
3561
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3562
		.ops = &mv88e6351_ops,
3563 3564 3565
	},

	[MV88E6352] = {
3566
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
3567 3568 3569 3570
		.family = MV88E6XXX_FAMILY_6352,
		.name = "Marvell 88E6352",
		.num_databases = 4096,
		.num_ports = 7,
3571
		.max_vid = 4095,
3572
		.port_base_addr = 0x10,
3573
		.global1_addr = 0x1b,
3574
		.global2_addr = 0x1c,
3575
		.age_time_coeff = 15000,
3576
		.g1_irqs = 9,
3577
		.g2_irqs = 10,
3578
		.atu_move_port_mask = 0xf,
3579
		.pvt = true,
3580
		.multi_chip = true,
3581
		.tag_protocol = DSA_TAG_PROTO_EDSA,
3582
		.ops = &mv88e6352_ops,
3583
	},
3584
	[MV88E6390] = {
3585
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
3586 3587 3588 3589
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6390",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3590
		.max_vid = 8191,
3591 3592
		.port_base_addr = 0x0,
		.global1_addr = 0x1b,
3593
		.global2_addr = 0x1c,
3594
		.age_time_coeff = 3750,
3595
		.g1_irqs = 9,
3596
		.g2_irqs = 14,
3597
		.atu_move_port_mask = 0x1f,
3598
		.pvt = true,
3599
		.multi_chip = true,
3600
		.tag_protocol = DSA_TAG_PROTO_DSA,
3601 3602 3603
		.ops = &mv88e6390_ops,
	},
	[MV88E6390X] = {
3604
		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
3605 3606 3607 3608
		.family = MV88E6XXX_FAMILY_6390,
		.name = "Marvell 88E6390X",
		.num_databases = 4096,
		.num_ports = 11,	/* 10 + Z80 */
3609
		.max_vid = 8191,
3610 3611
		.port_base_addr = 0x0,
		.global1_addr = 0x1b,
3612
		.global2_addr = 0x1c,
3613
		.age_time_coeff = 3750,
3614
		.g1_irqs = 9,
3615
		.g2_irqs = 14,
3616
		.atu_move_port_mask = 0x1f,
3617
		.pvt = true,
3618
		.multi_chip = true,
3619
		.tag_protocol = DSA_TAG_PROTO_DSA,
3620 3621
		.ops = &mv88e6390x_ops,
	},
3622 3623
};

3624
static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
3625
{
3626
	int i;
3627

3628 3629 3630
	for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
		if (mv88e6xxx_table[i].prod_num == prod_num)
			return &mv88e6xxx_table[i];
3631 3632 3633 3634

	return NULL;
}

3635
static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
3636 3637
{
	const struct mv88e6xxx_info *info;
3638 3639 3640
	unsigned int prod_num, rev;
	u16 id;
	int err;
3641

3642
	mutex_lock(&chip->reg_lock);
3643
	err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
3644 3645 3646
	mutex_unlock(&chip->reg_lock);
	if (err)
		return err;
3647

3648 3649
	prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
	rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
3650 3651 3652 3653 3654

	info = mv88e6xxx_lookup_info(prod_num);
	if (!info)
		return -ENODEV;

3655
	/* Update the compatible info with the probed one */
3656
	chip->info = info;
3657

3658 3659 3660 3661
	err = mv88e6xxx_g2_require(chip);
	if (err)
		return err;

3662 3663
	dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
		 chip->info->prod_num, chip->info->name, rev);
3664 3665 3666 3667

	return 0;
}

3668
static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
3669
{
3670
	struct mv88e6xxx_chip *chip;
3671

3672 3673
	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
	if (!chip)
3674 3675
		return NULL;

3676
	chip->dev = dev;
3677

3678
	mutex_init(&chip->reg_lock);
3679
	INIT_LIST_HEAD(&chip->mdios);
3680

3681
	return chip;
3682 3683
}

3684
static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
3685 3686
			      struct mii_bus *bus, int sw_addr)
{
3687
	if (sw_addr == 0)
3688
		chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
3689
	else if (chip->info->multi_chip)
3690
		chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
3691 3692 3693
	else
		return -EINVAL;

3694 3695
	chip->bus = bus;
	chip->sw_addr = sw_addr;
3696 3697 3698 3699

	return 0;
}

3700 3701
static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
{
V
Vivien Didelot 已提交
3702
	struct mv88e6xxx_chip *chip = ds->priv;
3703

3704
	return chip->info->tag_protocol;
3705 3706
}

3707 3708 3709
static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
				       struct device *host_dev, int sw_addr,
				       void **priv)
3710
{
3711
	struct mv88e6xxx_chip *chip;
3712
	struct mii_bus *bus;
3713
	int err;
3714

3715
	bus = dsa_host_dev_to_mii_bus(host_dev);
3716 3717 3718
	if (!bus)
		return NULL;

3719 3720
	chip = mv88e6xxx_alloc_chip(dsa_dev);
	if (!chip)
3721 3722
		return NULL;

3723
	/* Legacy SMI probing will only support chips similar to 88E6085 */
3724
	chip->info = &mv88e6xxx_table[MV88E6085];
3725

3726
	err = mv88e6xxx_smi_init(chip, bus, sw_addr);
3727 3728 3729
	if (err)
		goto free;

3730
	err = mv88e6xxx_detect(chip);
3731
	if (err)
3732
		goto free;
3733

3734 3735 3736 3737 3738 3739
	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_switch_reset(chip);
	mutex_unlock(&chip->reg_lock);
	if (err)
		goto free;

3740 3741
	mv88e6xxx_phy_init(chip);

3742
	err = mv88e6xxx_mdios_register(chip, NULL);
3743
	if (err)
3744
		goto free;
3745

3746
	*priv = chip;
3747

3748
	return chip->info->name;
3749
free:
3750
	devm_kfree(dsa_dev, chip);
3751 3752

	return NULL;
3753 3754
}

3755 3756 3757 3758 3759 3760 3761 3762 3763 3764 3765 3766 3767 3768 3769
static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
				      const struct switchdev_obj_port_mdb *mdb,
				      struct switchdev_trans *trans)
{
	/* We don't need any dynamic resource from the kernel (yet),
	 * so skip the prepare phase.
	 */

	return 0;
}

static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
				   const struct switchdev_obj_port_mdb *mdb,
				   struct switchdev_trans *trans)
{
V
Vivien Didelot 已提交
3770
	struct mv88e6xxx_chip *chip = ds->priv;
3771 3772 3773

	mutex_lock(&chip->reg_lock);
	if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3774
					 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
3775 3776
		dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
			port);
3777 3778 3779 3780 3781 3782
	mutex_unlock(&chip->reg_lock);
}

static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
				  const struct switchdev_obj_port_mdb *mdb)
{
V
Vivien Didelot 已提交
3783
	struct mv88e6xxx_chip *chip = ds->priv;
3784 3785 3786 3787
	int err;

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3788
					   MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
3789 3790 3791 3792 3793
	mutex_unlock(&chip->reg_lock);

	return err;
}

3794
static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
3795
	.probe			= mv88e6xxx_drv_probe,
3796
	.get_tag_protocol	= mv88e6xxx_get_tag_protocol,
3797 3798 3799 3800 3801 3802
	.setup			= mv88e6xxx_setup,
	.set_addr		= mv88e6xxx_set_addr,
	.adjust_link		= mv88e6xxx_adjust_link,
	.get_strings		= mv88e6xxx_get_strings,
	.get_ethtool_stats	= mv88e6xxx_get_ethtool_stats,
	.get_sset_count		= mv88e6xxx_get_sset_count,
3803 3804
	.port_enable		= mv88e6xxx_port_enable,
	.port_disable		= mv88e6xxx_port_disable,
V
Vivien Didelot 已提交
3805 3806
	.get_mac_eee		= mv88e6xxx_get_mac_eee,
	.set_mac_eee		= mv88e6xxx_set_mac_eee,
3807
	.get_eeprom_len		= mv88e6xxx_get_eeprom_len,
3808 3809 3810 3811
	.get_eeprom		= mv88e6xxx_get_eeprom,
	.set_eeprom		= mv88e6xxx_set_eeprom,
	.get_regs_len		= mv88e6xxx_get_regs_len,
	.get_regs		= mv88e6xxx_get_regs,
3812
	.set_ageing_time	= mv88e6xxx_set_ageing_time,
3813 3814 3815
	.port_bridge_join	= mv88e6xxx_port_bridge_join,
	.port_bridge_leave	= mv88e6xxx_port_bridge_leave,
	.port_stp_state_set	= mv88e6xxx_port_stp_state_set,
3816
	.port_fast_age		= mv88e6xxx_port_fast_age,
3817 3818 3819 3820 3821 3822 3823
	.port_vlan_filtering	= mv88e6xxx_port_vlan_filtering,
	.port_vlan_prepare	= mv88e6xxx_port_vlan_prepare,
	.port_vlan_add		= mv88e6xxx_port_vlan_add,
	.port_vlan_del		= mv88e6xxx_port_vlan_del,
	.port_fdb_add           = mv88e6xxx_port_fdb_add,
	.port_fdb_del           = mv88e6xxx_port_fdb_del,
	.port_fdb_dump          = mv88e6xxx_port_fdb_dump,
3824 3825 3826
	.port_mdb_prepare       = mv88e6xxx_port_mdb_prepare,
	.port_mdb_add           = mv88e6xxx_port_mdb_add,
	.port_mdb_del           = mv88e6xxx_port_mdb_del,
3827 3828
	.crosschip_bridge_join	= mv88e6xxx_crosschip_bridge_join,
	.crosschip_bridge_leave	= mv88e6xxx_crosschip_bridge_leave,
3829 3830
};

3831 3832 3833 3834
static struct dsa_switch_driver mv88e6xxx_switch_drv = {
	.ops			= &mv88e6xxx_switch_ops,
};

3835
static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
3836
{
3837
	struct device *dev = chip->dev;
3838 3839
	struct dsa_switch *ds;

3840
	ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip));
3841 3842 3843
	if (!ds)
		return -ENOMEM;

3844
	ds->priv = chip;
3845
	ds->ops = &mv88e6xxx_switch_ops;
3846 3847
	ds->ageing_time_min = chip->info->age_time_coeff;
	ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
3848 3849 3850

	dev_set_drvdata(dev, ds);

3851
	return dsa_register_switch(ds);
3852 3853
}

3854
static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
3855
{
3856
	dsa_unregister_switch(chip->ds);
3857 3858
}

3859
static int mv88e6xxx_probe(struct mdio_device *mdiodev)
3860
{
3861
	struct device *dev = &mdiodev->dev;
3862
	struct device_node *np = dev->of_node;
3863
	const struct mv88e6xxx_info *compat_info;
3864
	struct mv88e6xxx_chip *chip;
3865
	u32 eeprom_len;
3866
	int err;
3867

3868 3869 3870 3871
	compat_info = of_device_get_match_data(dev);
	if (!compat_info)
		return -EINVAL;

3872 3873
	chip = mv88e6xxx_alloc_chip(dev);
	if (!chip)
3874 3875
		return -ENOMEM;

3876
	chip->info = compat_info;
3877

3878
	err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
3879 3880
	if (err)
		return err;
3881

3882 3883 3884 3885
	chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
	if (IS_ERR(chip->reset))
		return PTR_ERR(chip->reset);

3886
	err = mv88e6xxx_detect(chip);
3887 3888
	if (err)
		return err;
3889

3890 3891
	mv88e6xxx_phy_init(chip);

3892
	if (chip->info->ops->get_eeprom &&
3893
	    !of_property_read_u32(np, "eeprom-length", &eeprom_len))
3894
		chip->eeprom_len = eeprom_len;
3895

3896 3897 3898 3899 3900 3901 3902 3903 3904 3905 3906 3907 3908 3909 3910 3911 3912 3913 3914 3915 3916 3917 3918 3919
	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_switch_reset(chip);
	mutex_unlock(&chip->reg_lock);
	if (err)
		goto out;

	chip->irq = of_irq_get(np, 0);
	if (chip->irq == -EPROBE_DEFER) {
		err = chip->irq;
		goto out;
	}

	if (chip->irq > 0) {
		/* Has to be performed before the MDIO bus is created,
		 * because the PHYs will link there interrupts to these
		 * interrupt controllers
		 */
		mutex_lock(&chip->reg_lock);
		err = mv88e6xxx_g1_irq_setup(chip);
		mutex_unlock(&chip->reg_lock);

		if (err)
			goto out;

3920
		if (chip->info->g2_irqs > 0) {
3921 3922 3923 3924 3925 3926
			err = mv88e6xxx_g2_irq_setup(chip);
			if (err)
				goto out_g1_irq;
		}
	}

3927
	err = mv88e6xxx_mdios_register(chip, np);
3928
	if (err)
3929
		goto out_g2_irq;
3930

3931
	err = mv88e6xxx_register_switch(chip);
3932 3933
	if (err)
		goto out_mdio;
3934

3935
	return 0;
3936 3937

out_mdio:
3938
	mv88e6xxx_mdios_unregister(chip);
3939
out_g2_irq:
3940
	if (chip->info->g2_irqs > 0 && chip->irq > 0)
3941 3942
		mv88e6xxx_g2_irq_free(chip);
out_g1_irq:
3943 3944
	if (chip->irq > 0) {
		mutex_lock(&chip->reg_lock);
3945
		mv88e6xxx_g1_irq_free(chip);
3946 3947
		mutex_unlock(&chip->reg_lock);
	}
3948 3949
out:
	return err;
3950
}
3951 3952 3953 3954

static void mv88e6xxx_remove(struct mdio_device *mdiodev)
{
	struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
V
Vivien Didelot 已提交
3955
	struct mv88e6xxx_chip *chip = ds->priv;
3956

3957
	mv88e6xxx_phy_destroy(chip);
3958
	mv88e6xxx_unregister_switch(chip);
3959
	mv88e6xxx_mdios_unregister(chip);
3960

3961
	if (chip->irq > 0) {
3962
		if (chip->info->g2_irqs > 0)
3963 3964 3965
			mv88e6xxx_g2_irq_free(chip);
		mv88e6xxx_g1_irq_free(chip);
	}
3966 3967 3968
}

static const struct of_device_id mv88e6xxx_of_match[] = {
3969 3970 3971 3972
	{
		.compatible = "marvell,mv88e6085",
		.data = &mv88e6xxx_table[MV88E6085],
	},
3973 3974 3975 3976
	{
		.compatible = "marvell,mv88e6190",
		.data = &mv88e6xxx_table[MV88E6190],
	},
3977 3978 3979 3980 3981 3982 3983 3984 3985 3986 3987 3988 3989 3990 3991 3992
	{ /* sentinel */ },
};

MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);

static struct mdio_driver mv88e6xxx_driver = {
	.probe	= mv88e6xxx_probe,
	.remove = mv88e6xxx_remove,
	.mdiodrv.driver = {
		.name = "mv88e6085",
		.of_match_table = mv88e6xxx_of_match,
	},
};

static int __init mv88e6xxx_init(void)
{
3993
	register_switch_driver(&mv88e6xxx_switch_drv);
3994 3995
	return mdio_driver_register(&mv88e6xxx_driver);
}
3996 3997 3998 3999
module_init(mv88e6xxx_init);

static void __exit mv88e6xxx_cleanup(void)
{
4000
	mdio_driver_unregister(&mv88e6xxx_driver);
4001
	unregister_switch_driver(&mv88e6xxx_switch_drv);
4002 4003
}
module_exit(mv88e6xxx_cleanup);
4004 4005 4006 4007

MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
MODULE_LICENSE("GPL");