i915_drv.h 56.8 KB
Newer Older
L
Linus Torvalds 已提交
1 2
/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
 */
D
Dave Airlie 已提交
3
/*
4
 *
L
Linus Torvalds 已提交
5 6
 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
D
Dave Airlie 已提交
28
 */
L
Linus Torvalds 已提交
29 30 31 32

#ifndef _I915_DRV_H_
#define _I915_DRV_H_

33
#include <uapi/drm/i915_drm.h>
34
#include <uapi/drm/drm_fourcc.h>
35

36 37
#include <asm/hypervisor.h>

38
#include <linux/io-mapping.h>
39
#include <linux/i2c.h>
40
#include <linux/i2c-algo-bit.h>
41
#include <linux/backlight.h>
42
#include <linux/hash.h>
43
#include <linux/intel-iommu.h>
44
#include <linux/kref.h>
45
#include <linux/mm_types.h>
46
#include <linux/perf_event.h>
47
#include <linux/pm_qos.h>
48
#include <linux/dma-resv.h>
49
#include <linux/shmem_fs.h>
50
#include <linux/stackdepot.h>
51
#include <linux/xarray.h>
52 53 54 55

#include <drm/intel-gtt.h>
#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
#include <drm/drm_gem.h>
D
Daniel Vetter 已提交
56
#include <drm/drm_auth.h>
57
#include <drm/drm_cache.h>
58
#include <drm/drm_util.h>
59
#include <drm/drm_dsc.h>
60
#include <drm/drm_atomic.h>
J
Jani Nikula 已提交
61
#include <drm/drm_connector.h>
62
#include <drm/i915_mei_hdcp_interface.h>
63 64 65

#include "i915_params.h"
#include "i915_reg.h"
66
#include "i915_utils.h"
67

68 69 70 71
#include "display/intel_bios.h"
#include "display/intel_display.h"
#include "display/intel_display_power.h"
#include "display/intel_dpll_mgr.h"
72
#include "display/intel_dsb.h"
73
#include "display/intel_frontbuffer.h"
74
#include "display/intel_global_state.h"
75
#include "display/intel_gmbus.h"
76 77
#include "display/intel_opregion.h"

78
#include "gem/i915_gem_context_types.h"
79
#include "gem/i915_gem_shrinker.h"
80 81
#include "gem/i915_gem_stolen.h"

82
#include "gt/intel_engine.h"
83
#include "gt/intel_gt_types.h"
84
#include "gt/intel_region_lmem.h"
85
#include "gt/intel_workarounds.h"
86
#include "gt/uc/intel_uc.h"
87

88
#include "intel_device_info.h"
89
#include "intel_pch.h"
90
#include "intel_runtime_pm.h"
91
#include "intel_memory_region.h"
92
#include "intel_uncore.h"
93
#include "intel_wakeref.h"
94
#include "intel_wopcm.h"
95

96
#include "i915_gem.h"
97
#include "i915_gem_gtt.h"
98
#include "i915_gpu_error.h"
99
#include "i915_perf_types.h"
100
#include "i915_request.h"
101
#include "i915_scheduler.h"
102
#include "gt/intel_timeline.h"
J
Joonas Lahtinen 已提交
103
#include "i915_vma.h"
104
#include "i915_irq.h"
J
Joonas Lahtinen 已提交
105

106

L
Linus Torvalds 已提交
107 108 109 110 111
/* General customization:
 */

#define DRIVER_NAME		"i915"
#define DRIVER_DESC		"Intel Graphics"
112 113
#define DRIVER_DATE		"20201103"
#define DRIVER_TIMESTAMP	1604406085
L
Linus Torvalds 已提交
114

115 116
struct drm_i915_gem_object;

117 118 119 120 121 122
enum hpd_pin {
	HPD_NONE = 0,
	HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
	HPD_CRT,
	HPD_SDVO_B,
	HPD_SDVO_C,
123
	HPD_PORT_A,
124 125 126
	HPD_PORT_B,
	HPD_PORT_C,
	HPD_PORT_D,
X
Xiong Zhang 已提交
127
	HPD_PORT_E,
128 129 130 131 132 133
	HPD_PORT_TC1,
	HPD_PORT_TC2,
	HPD_PORT_TC3,
	HPD_PORT_TC4,
	HPD_PORT_TC5,
	HPD_PORT_TC6,
134

135 136 137
	HPD_NUM_PINS
};

138 139 140
#define for_each_hpd_pin(__pin) \
	for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)

141 142
/* Threshold == 5 for long IRQs, 50 for short */
#define HPD_STORM_DEFAULT_THRESHOLD 50
L
Lyude 已提交
143

144
struct i915_hotplug {
145
	struct delayed_work hotplug_work;
146

147 148
	const u32 *hpd, *pch_hpd;

149 150 151 152 153 154 155 156 157 158
	struct {
		unsigned long last_jiffies;
		int count;
		enum {
			HPD_ENABLED = 0,
			HPD_DISABLED = 1,
			HPD_MARK_DISABLED = 2
		} state;
	} stats[HPD_NUM_PINS];
	u32 event_bits;
159
	u32 retry_bits;
160 161 162 163 164 165
	struct delayed_work reenable_work;

	u32 long_port_mask;
	u32 short_port_mask;
	struct work_struct dig_port_work;

166 167 168
	struct work_struct poll_init_work;
	bool poll_enabled;

L
Lyude 已提交
169
	unsigned int hpd_storm_threshold;
170 171
	/* Whether or not to count short HPD IRQs in HPD storms */
	u8 hpd_short_storm_enabled;
L
Lyude 已提交
172

173 174 175 176 177 178 179 180 181 182
	/*
	 * if we get a HPD irq from DP and a HPD irq from non-DP
	 * the non-DP HPD could block the workqueue on a mode config
	 * mutex getting, that userspace may have taken. However
	 * userspace is waiting on the DP workqueue to run which is
	 * blocked behind the non-DP one.
	 */
	struct workqueue_struct *dp_wq;
};

183 184 185 186 187 188
#define I915_GEM_GPU_DOMAINS \
	(I915_GEM_DOMAIN_RENDER | \
	 I915_GEM_DOMAIN_SAMPLER | \
	 I915_GEM_DOMAIN_COMMAND | \
	 I915_GEM_DOMAIN_INSTRUCTION | \
	 I915_GEM_DOMAIN_VERTEX)
189

190
struct drm_i915_private;
191
struct i915_mm_struct;
192
struct i915_mmu_object;
193

194 195
struct drm_i915_file_private {
	struct drm_i915_private *dev_priv;
196 197 198 199 200

	union {
		struct drm_file *file;
		struct rcu_head rcu;
	};
201

202
	struct xarray context_xa;
203
	struct xarray vm_xa;
204

205
	unsigned int bsd_engine;
206

207 208 209 210 211 212 213
/*
 * Every context ban increments per client ban score. Also
 * hangs in short succession increments ban score. If ban threshold
 * is reached, client is considered banned and submitting more work
 * will fail. This is a stop gap measure to limit the badly behaving
 * clients access to gpu. Note that unbannable contexts never increment
 * the client ban score.
214
 */
215 216 217 218 219 220 221
#define I915_CLIENT_SCORE_HANG_FAST	1
#define   I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
#define I915_CLIENT_SCORE_CONTEXT_BAN   3
#define I915_CLIENT_SCORE_BANNED	9
	/** ban_score: Accumulated score of all ctx bans and fast hangs. */
	atomic_t ban_score;
	unsigned long hang_timestamp;
222 223
};

L
Linus Torvalds 已提交
224 225 226
/* Interface history:
 *
 * 1.1: Original.
D
Dave Airlie 已提交
227 228
 * 1.2: Add Power Management
 * 1.3: Add vblank support
229
 * 1.4: Fix cmdbuffer path, add heap destroy
230
 * 1.5: Add vblank pipe configuration
=
=?utf-8?q?Michel_D=C3=A4nzer?= 已提交
231 232
 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 *      - Support vertical blank on secondary display pipe
L
Linus Torvalds 已提交
233 234
 */
#define DRIVER_MAJOR		1
=
=?utf-8?q?Michel_D=C3=A4nzer?= 已提交
235
#define DRIVER_MINOR		6
L
Linus Torvalds 已提交
236 237
#define DRIVER_PATCHLEVEL	0

238 239 240
struct intel_overlay;
struct intel_overlay_error_state;

241
struct sdvo_device_mapping {
C
Chris Wilson 已提交
242
	u8 initialized;
243 244 245
	u8 dvo_port;
	u8 slave_addr;
	u8 dvo_wiring;
C
Chris Wilson 已提交
246
	u8 i2c_pin;
247
	u8 ddc_pin;
248 249
};

250
struct intel_connector;
251
struct intel_encoder;
252
struct intel_atomic_state;
253
struct intel_cdclk_config;
254 255
struct intel_cdclk_state;
struct intel_cdclk_vals;
256
struct intel_initial_plane_config;
257
struct intel_crtc;
258 259
struct intel_limit;
struct dpll;
260

261
struct drm_i915_display_funcs {
262
	void (*get_cdclk)(struct drm_i915_private *dev_priv,
263
			  struct intel_cdclk_config *cdclk_config);
264
	void (*set_cdclk)(struct drm_i915_private *dev_priv,
265
			  const struct intel_cdclk_config *cdclk_config,
266
			  enum pipe pipe);
267
	int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
268 269
	int (*get_fifo_size)(struct drm_i915_private *dev_priv,
			     enum i9xx_plane_id i9xx_plane);
270 271
	int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
	int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
272
	void (*initial_watermarks)(struct intel_atomic_state *state,
273
				   struct intel_crtc *crtc);
274
	void (*atomic_update_watermarks)(struct intel_atomic_state *state,
275
					 struct intel_crtc *crtc);
276
	void (*optimize_watermarks)(struct intel_atomic_state *state,
277
				    struct intel_crtc *crtc);
278
	int (*compute_global_watermarks)(struct intel_atomic_state *state);
279
	void (*update_wm)(struct intel_crtc *crtc);
280
	int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
281
	u8 (*calc_voltage_level)(int cdclk);
282 283 284
	/* Returns the active state of the crtc, and if the crtc is active,
	 * fills out the pipe-config with the hw state. */
	bool (*get_pipe_config)(struct intel_crtc *,
285
				struct intel_crtc_state *);
286 287
	void (*get_initial_plane_config)(struct intel_crtc *,
					 struct intel_initial_plane_config *);
288 289
	int (*crtc_compute_clock)(struct intel_crtc *crtc,
				  struct intel_crtc_state *crtc_state);
290 291 292 293
	void (*crtc_enable)(struct intel_atomic_state *state,
			    struct intel_crtc *crtc);
	void (*crtc_disable)(struct intel_atomic_state *state,
			     struct intel_crtc *crtc);
294
	void (*commit_modeset_enables)(struct intel_atomic_state *state);
295
	void (*commit_modeset_disables)(struct intel_atomic_state *state);
296 297 298 299 300 301
	void (*audio_codec_enable)(struct intel_encoder *encoder,
				   const struct intel_crtc_state *crtc_state,
				   const struct drm_connector_state *conn_state);
	void (*audio_codec_disable)(struct intel_encoder *encoder,
				    const struct intel_crtc_state *old_crtc_state,
				    const struct drm_connector_state *old_conn_state);
302 303
	void (*fdi_link_train)(struct intel_crtc *crtc,
			       const struct intel_crtc_state *crtc_state);
304
	void (*init_clock_gating)(struct drm_i915_private *dev_priv);
305
	void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
306 307 308 309 310
	/* clock updates for mode set */
	/* cursor updates */
	/* render clock increase/decrease */
	/* display clock increase/decrease */
	/* pll clock increase/decrease */
311

312
	int (*color_check)(struct intel_crtc_state *crtc_state);
313 314 315 316 317 318 319 320 321 322 323 324 325
	/*
	 * Program double buffered color management registers during
	 * vblank evasion. The registers should then latch during the
	 * next vblank start, alongside any other double buffered registers
	 * involved with the same commit.
	 */
	void (*color_commit)(const struct intel_crtc_state *crtc_state);
	/*
	 * Load LUTs (and other single buffered color management
	 * registers). Will (hopefully) be called during the vblank
	 * following the latching of any double buffered registers
	 * involved with the same commit.
	 */
326
	void (*load_luts)(const struct intel_crtc_state *crtc_state);
327
	void (*read_luts)(struct intel_crtc_state *crtc_state);
328 329
};

330
struct intel_csr {
331
	struct work_struct work;
332
	const char *fw_path;
333 334 335 336 337 338
	u32 required_version;
	u32 max_fw_size; /* bytes */
	u32 *dmc_payload;
	u32 dmc_fw_size; /* dwords */
	u32 version;
	u32 mmio_count;
339 340
	i915_reg_t mmioaddr[20];
	u32 mmiodata[20];
341
	u32 dc_state;
342
	u32 target_dc_state;
343
	u32 allowed_dc_mask;
344
	intel_wakeref_t wakeref;
345 346
};

347 348
enum i915_cache_level {
	I915_CACHE_NONE = 0,
349 350 351 352 353
	I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
	I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
			      caches, eg sampler/render caches, and the
			      large Last-Level-Cache. LLC is coherent with
			      the CPU, but L3 is only visible to the GPU. */
354
	I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
355 356
};

357 358
#define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */

359
struct intel_fbc {
P
Paulo Zanoni 已提交
360 361 362
	/* This is always the inner lock when overlapping with struct_mutex and
	 * it's the outer lock when overlapping with stolen_lock. */
	struct mutex lock;
B
Ben Widawsky 已提交
363
	unsigned threshold;
364 365
	unsigned int possible_framebuffer_bits;
	unsigned int busy_bits;
366
	struct intel_crtc *crtc;
367

368
	struct drm_mm_node compressed_fb;
369 370
	struct drm_mm_node *compressed_llb;

371 372
	bool false_color;

373
	bool active;
374
	bool activated;
375
	bool flip_pending;
376

377 378 379
	bool underrun_detected;
	struct work_struct underrun_work;

380 381 382 383 384
	/*
	 * Due to the atomic rules we can't access some structures without the
	 * appropriate locking, so we cache information here in order to avoid
	 * these problems.
	 */
385 386 387
	struct intel_fbc_state_cache {
		struct {
			unsigned int mode_flags;
388
			u32 hsw_bdw_pixel_rate;
389 390 391 392 393 394 395
		} crtc;

		struct {
			unsigned int rotation;
			int src_w;
			int src_h;
			bool visible;
396 397 398 399 400 401 402 403
			/*
			 * Display surface base address adjustement for
			 * pageflips. Note that on gen4+ this only adjusts up
			 * to a tile, offsets within a tile are handled in
			 * the hw itself (with the TILEOFF register).
			 */
			int adjusted_x;
			int adjusted_y;
404

405
			u16 pixel_blend_mode;
406 407 408
		} plane;

		struct {
409
			const struct drm_format_info *format;
410
			unsigned int stride;
411
			u64 modifier;
412
		} fb;
413 414

		unsigned int fence_y_offset;
415
		u16 gen9_wa_cfb_stride;
416
		u16 interval;
417
		s8 fence_id;
418
		bool psr2_active;
419 420
	} state_cache;

421 422 423 424 425 426 427
	/*
	 * This structure contains everything that's relevant to program the
	 * hardware registers. When we want to figure out if we need to disable
	 * and re-enable FBC for a new configuration we just check if there's
	 * something different in the struct. The genx_fbc_activate functions
	 * are supposed to read from it in order to program the registers.
	 */
428 429 430
	struct intel_fbc_reg_params {
		struct {
			enum pipe pipe;
431
			enum i9xx_plane_id i9xx_plane;
432 433 434
		} crtc;

		struct {
435
			const struct drm_format_info *format;
436
			unsigned int stride;
437
			u64 modifier;
438 439 440
		} fb;

		int cfb_size;
441
		unsigned int fence_y_offset;
442
		u16 gen9_wa_cfb_stride;
443
		u16 interval;
444
		s8 fence_id;
445
		bool plane_visible;
446 447
	} params;

448
	const char *no_fbc_reason;
449 450
};

451
/*
452 453 454 455 456 457 458 459 460 461 462 463 464 465
 * HIGH_RR is the highest eDP panel refresh rate read from EDID
 * LOW_RR is the lowest eDP panel refresh rate found from EDID
 * parsing for same resolution.
 */
enum drrs_refresh_rate_type {
	DRRS_HIGH_RR,
	DRRS_LOW_RR,
	DRRS_MAX_RR, /* RR count */
};

enum drrs_support_type {
	DRRS_NOT_SUPPORTED = 0,
	STATIC_DRRS_SUPPORT = 1,
	SEAMLESS_DRRS_SUPPORT = 2
466 467
};

468
struct intel_dp;
469 470 471 472 473 474 475 476 477
struct i915_drrs {
	struct mutex mutex;
	struct delayed_work work;
	struct intel_dp *dp;
	unsigned busy_frontbuffer_bits;
	enum drrs_refresh_rate_type refresh_rate_type;
	enum drrs_support_type type;
};

R
Rodrigo Vivi 已提交
478
struct i915_psr {
479
	struct mutex lock;
480 481 482 483 484

#define I915_PSR_DEBUG_MODE_MASK	0x0f
#define I915_PSR_DEBUG_DEFAULT		0x00
#define I915_PSR_DEBUG_DISABLE		0x01
#define I915_PSR_DEBUG_ENABLE		0x02
485
#define I915_PSR_DEBUG_FORCE_PSR1	0x03
486 487 488
#define I915_PSR_DEBUG_IRQ		0x10

	u32 debug;
R
Rodrigo Vivi 已提交
489
	bool sink_support;
490
	bool enabled;
491
	struct intel_dp *dp;
492
	enum pipe pipe;
493
	enum transcoder transcoder;
494
	bool active;
495
	struct work_struct work;
496
	unsigned busy_frontbuffer_bits;
497
	bool sink_psr2_support;
498
	bool link_standby;
499
	bool colorimetry_support;
500
	bool psr2_enabled;
501
	bool psr2_sel_fetch_enabled;
502
	u8 sink_sync_latency;
503 504
	ktime_t last_entry_attempt;
	ktime_t last_exit;
505
	bool sink_not_reliable;
506
	bool irq_aux_error;
507
	u16 su_x_granularity;
508 509
	bool dc3co_enabled;
	u32 dc3co_exit_delay;
510
	struct delayed_work dc3co_work;
511
	struct drm_dp_vsc_sdp vsc;
512
};
513

514
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
515
#define QUIRK_INVERT_BRIGHTNESS (1<<2)
516
#define QUIRK_BACKLIGHT_PRESENT (1<<3)
517
#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
518
#define QUIRK_INCREASE_T12_DELAY (1<<6)
519
#define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
520

521
struct intel_fbdev;
522
struct intel_fbc_work;
523

524 525
struct intel_gmbus {
	struct i2c_adapter adapter;
526
#define GMBUS_FORCE_BIT_RETRY (1U << 31)
527
	u32 force_bit;
528
	u32 reg0;
529
	i915_reg_t gpio_reg;
530
	struct i2c_algo_bit_data bit_algo;
531 532 533
	struct drm_i915_private *dev_priv;
};

534
struct i915_suspend_saved_registers {
535
	u32 saveDSPARB;
J
Jesse Barnes 已提交
536 537
	u32 saveSWF0[16];
	u32 saveSWF1[16];
538
	u32 saveSWF3[3];
539
	u16 saveGCDGMBUS;
540
};
541

542
struct vlv_s0ix_state;
543

544
#define MAX_L3_SLICES 2
545
struct intel_l3_parity {
546
	u32 *remap_info[MAX_L3_SLICES];
547
	struct work_struct error_work;
548
	int which_slice;
549 550
};

551 552 553
struct i915_gem_mm {
	/** Memory allocator for GTT stolen memory */
	struct drm_mm stolen;
554 555 556 557
	/** Protects the usage of the GTT stolen memory allocator. This is
	 * always the inner lock when overlapping with struct_mutex. */
	struct mutex stolen_lock;

558 559 560
	/* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
	spinlock_t obj_lock;

561
	/**
562
	 * List of objects which are purgeable.
563
	 */
564 565
	struct list_head purge_list;

566
	/**
567
	 * List of objects which have allocated pages and are shrinkable.
568
	 */
569
	struct list_head shrink_list;
570

571 572 573 574 575
	/**
	 * List of objects which are pending destruction.
	 */
	struct llist_head free_list;
	struct work_struct free_work;
576 577 578 579 580
	/**
	 * Count of objects pending destructions. Used to skip needlessly
	 * waiting on an RCU barrier if no objects are waiting to be freed.
	 */
	atomic_t free_count;
581

M
Matthew Auld 已提交
582 583 584 585 586
	/**
	 * tmpfs instance used for shmem backed objects
	 */
	struct vfsmount *gemfs;

587 588
	struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];

589
	struct notifier_block oom_notifier;
590
	struct notifier_block vmap_notifier;
591
	struct shrinker shrinker;
592

593 594 595 596 597 598 599
	/**
	 * Workqueue to fault in userptr pages, flushed by the execbuf
	 * when required but otherwise left to userspace to try again
	 * on EAGAIN.
	 */
	struct workqueue_struct *userptr_wq;

600 601 602
	/* shrinker accounting, also useful for userland debugging */
	u64 shrink_memory;
	u32 shrink_count;
603 604
};

605 606
#define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */

607 608 609 610 611 612 613 614 615
unsigned long i915_fence_context_timeout(const struct drm_i915_private *i915,
					 u64 context);

static inline unsigned long
i915_fence_timeout(const struct drm_i915_private *i915)
{
	return i915_fence_context_timeout(i915, U64_MAX);
}

616 617 618
/* Amount of SAGV/QGV points, BSpec precisely defines this */
#define I915_NUM_QGV_POINTS 8

619
struct ddi_vbt_port_info {
620 621 622
	/* Non-NULL if port present. */
	const struct child_device_config *child;

623 624
	int max_tmds_clock;

625
	/* This is an index in the HDMI/DVI DDI buffer translation table. */
626
	u8 hdmi_level_shift;
627
	u8 hdmi_level_shift_set:1;
628

629 630 631 632 633 634
	u8 supports_dvi:1;
	u8 supports_hdmi:1;
	u8 supports_dp:1;
	u8 supports_edp:1;
	u8 supports_typec_usb:1;
	u8 supports_tbt:1;
635

636 637
	u8 alternate_aux_channel;
	u8 alternate_ddc_pin;
638

639 640
	u8 dp_boost_level;
	u8 hdmi_boost_level;
641
	int dp_max_link_rate;		/* 0 for not limited by VBT */
642 643
};

R
Rodrigo Vivi 已提交
644 645 646 647 648
enum psr_lines_to_wait {
	PSR_0_LINES_TO_WAIT = 0,
	PSR_1_LINE_TO_WAIT,
	PSR_4_LINES_TO_WAIT,
	PSR_8_LINES_TO_WAIT
649 650
};

651 652 653 654 655 656 657 658 659
struct intel_vbt_data {
	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */

	/* Feature bits */
	unsigned int int_tv_support:1;
	unsigned int lvds_dither:1;
	unsigned int int_crt_support:1;
	unsigned int lvds_use_ssc:1;
660
	unsigned int int_lvds_support:1;
661 662
	unsigned int display_clock_mode:1;
	unsigned int fdi_rx_polarity_inverted:1;
663
	unsigned int panel_type:4;
664 665
	int lvds_ssc_freq;
	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
666
	enum drm_panel_orientation orientation;
667

668 669
	enum drrs_support_type drrs_type;

670 671 672 673 674
	struct {
		int rate;
		int lanes;
		int preemphasis;
		int vswing;
675
		bool low_vswing;
676 677 678
		bool initialized;
		int bpp;
		struct edp_power_seq pps;
679
		bool hobl;
680
	} edp;
681

R
Rodrigo Vivi 已提交
682
	struct {
683
		bool enable;
R
Rodrigo Vivi 已提交
684 685 686 687
		bool full_link;
		bool require_aux_wakeup;
		int idle_frames;
		enum psr_lines_to_wait lines_to_wait;
688 689
		int tp1_wakeup_time_us;
		int tp2_tp3_wakeup_time_us;
690
		int psr2_tp2_tp3_wakeup_time_us;
R
Rodrigo Vivi 已提交
691 692
	} psr;

693 694
	struct {
		u16 pwm_freq_hz;
695
		bool present;
696
		bool active_low_pwm;
697
		u8 min_brightness;	/* min_brightness/255 of max */
698
		u8 controller;		/* brightness controller number */
699
		enum intel_backlight_type type;
700 701
	} backlight;

702 703 704
	/* MIPI DSI */
	struct {
		u16 panel_id;
705 706
		struct mipi_config *config;
		struct mipi_pps_data *pps;
707 708
		u16 bl_ports;
		u16 cabc_ports;
709 710 711
		u8 seq_version;
		u32 size;
		u8 *data;
712
		const u8 *sequence[MIPI_SEQ_MAX];
713
		u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
714
		enum drm_panel_orientation orientation;
715 716
	} dsi;

717 718
	int crt_ddc_pin;

719
	struct list_head display_devices;
720 721

	struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
722
	struct sdvo_device_mapping sdvo_mappings[2];
723 724
};

725 726 727 728 729
enum intel_ddb_partitioning {
	INTEL_DDB_PART_1_2,
	INTEL_DDB_PART_5_6, /* IVB+ */
};

730
struct ilk_wm_values {
731 732 733
	u32 wm_pipe[3];
	u32 wm_lp[3];
	u32 wm_lp_spr[3];
734 735 736 737
	bool enable_fbc_wm;
	enum intel_ddb_partitioning partitioning;
};

738
struct g4x_pipe_wm {
739 740
	u16 plane[I915_MAX_PLANES];
	u16 fbc;
741
};
742

743
struct g4x_sr_wm {
744 745 746
	u16 plane;
	u16 cursor;
	u16 fbc;
747 748 749
};

struct vlv_wm_ddl_values {
750
	u8 plane[I915_MAX_PLANES];
751
};
752

753
struct vlv_wm_values {
754 755
	struct g4x_pipe_wm pipe[3];
	struct g4x_sr_wm sr;
756
	struct vlv_wm_ddl_values ddl[3];
757
	u8 level;
758
	bool cxsr;
759 760
};

761 762 763 764 765 766 767 768 769
struct g4x_wm_values {
	struct g4x_pipe_wm pipe[2];
	struct g4x_sr_wm sr;
	struct g4x_sr_wm hpll;
	bool cxsr;
	bool hpll_en;
	bool fbc_en;
};

770
struct skl_ddb_entry {
771
	u16 start, end;	/* in number of blocks, 'end' is exclusive */
772 773
};

774
static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
775
{
776
	return entry->end - entry->start;
777 778
}

779 780 781 782 783 784 785 786 787
static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
				       const struct skl_ddb_entry *e2)
{
	if (e1->start == e2->start && e1->end == e2->end)
		return true;

	return false;
}

788
struct i915_frontbuffer_tracking {
789
	spinlock_t lock;
790 791 792 793 794 795 796 797 798

	/*
	 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
	 * scheduled flips.
	 */
	unsigned busy_bits;
	unsigned flip_bits;
};

799
struct i915_virtual_gpu {
800
	struct mutex lock; /* serialises sending of g2v_notify command pkts */
801
	bool active;
802
	u32 caps;
803 804
};

805
struct intel_cdclk_config {
806
	unsigned int cdclk, vco, ref, bypass;
807
	u8 voltage_level;
808 809
};

810 811 812 813
struct i915_selftest_stash {
	atomic_t counter;
};

814
struct drm_i915_private {
815 816
	struct drm_device drm;

817 818 819
	/* FIXME: Device release actions should all be moved to drmm_ */
	bool do_release;

820 821 822
	/* i915 device parameters */
	struct i915_params params;

823
	const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
824
	struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
825
	struct intel_driver_caps caps;
826

827 828 829
	/**
	 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
	 * end of stolen which we can optionally use to create GEM objects
830
	 * backed by stolen memory. Note that stolen_usable_size tells us
831 832 833 834
	 * exactly how much of this we are actually allowed to use, given that
	 * some portion of it is in fact reserved for use by hardware functions.
	 */
	struct resource dsm;
835 836 837 838
	/**
	 * Reseved portion of Data Stolen Memory
	 */
	struct resource dsm_reserved;
839

840 841 842 843 844 845 846 847 848
	/*
	 * Stolen memory is segmented in hardware with different portions
	 * offlimits to certain functions.
	 *
	 * The drm_mm is initialised to the total accessible range, as found
	 * from the PCI config. On Broadwell+, this is further restricted to
	 * avoid the first page! The upper end of stolen memory is reserved for
	 * hardware functions and similarly removed from the accessible range.
	 */
849
	resource_size_t stolen_usable_size;	/* Total size minus reserved ranges */
850

851
	struct intel_uncore uncore;
852
	struct intel_uncore_mmio_debug mmio_debug;
853

854 855
	struct i915_virtual_gpu vgpu;

856
	struct intel_gvt *gvt;
857

858 859
	struct intel_wopcm wopcm;

860 861
	struct intel_csr csr;

862
	struct intel_gmbus gmbus[GMBUS_NUM_PINS];
863

864 865 866 867 868
	/** gmbus_mutex protects against concurrent usage of the single hw gmbus
	 * controller on different i2c buses. */
	struct mutex gmbus_mutex;

	/**
869 870
	 * Base address of where the gmbus and gpio blocks are located (either
	 * on PCH or on SoC for platforms without PCH).
871
	 */
872
	u32 gpio_mmio_base;
873

874 875
	u32 hsw_psr_mmio_adjust;

876
	/* MMIO base address for MIPI regs */
877
	u32 mipi_mmio_base;
878

879
	u32 pps_mmio_base;
880

881 882
	wait_queue_head_t gmbus_wait_queue;

883
	struct pci_dev *bridge_dev;
884 885

	struct rb_root uabi_engines;
886 887 888 889 890 891

	struct resource mch_res;

	/* protects the irq masks */
	spinlock_t irq_lock;

892 893
	bool display_irqs_enabled;

V
Ville Syrjälä 已提交
894 895
	/* Sideband mailbox protection */
	struct mutex sb_lock;
896
	struct pm_qos_request sb_qos;
897 898

	/** Cached value of IMR to avoid reads in updating the bitfield */
899 900 901 902
	union {
		u32 irq_mask;
		u32 de_irq_mask[I915_MAX_PIPES];
	};
903
	u32 pipestat_irq_mask[I915_MAX_PIPES];
904

905
	struct i915_hotplug hotplug;
906
	struct intel_fbc fbc;
907
	struct i915_drrs drrs;
908
	struct intel_opregion opregion;
909
	struct intel_vbt_data vbt;
910

911 912
	bool preserve_bios_swizzle;

913 914 915
	/* overlay */
	struct intel_overlay *overlay;

916
	/* backlight registers and fields in struct intel_panel */
917
	struct mutex backlight_lock;
918

V
Ville Syrjälä 已提交
919 920 921
	/* protects panel power sequencer state */
	struct mutex pps_mutex;

922
	unsigned int fsb_freq, mem_freq, is_ddr3;
923
	unsigned int skl_preferred_vco_freq;
924
	unsigned int max_cdclk_freq;
925

M
Mika Kahola 已提交
926
	unsigned int max_dotclk_freq;
927
	unsigned int hpll_freq;
928
	unsigned int fdi_pll_freq;
929
	unsigned int czclk_freq;
930

931
	struct {
932 933
		/* The current hardware cdclk configuration */
		struct intel_cdclk_config hw;
934

935 936
		/* cdclk, divider, and ratio table from bspec */
		const struct intel_cdclk_vals *table;
937 938

		struct intel_global_obj obj;
939
	} cdclk;
940

941 942 943 944 945 946 947
	struct {
		/* The current hardware dbuf configuration */
		u8 enabled_slices;

		struct intel_global_obj obj;
	} dbuf;

948 949 950 951 952 953 954
	/**
	 * wq - Driver workqueue for GEM.
	 *
	 * NOTE: Work items scheduled here are not allowed to grab any modeset
	 * locks, for otherwise the flushing done in the pageflip code will
	 * result in deadlocks.
	 */
955 956
	struct workqueue_struct *wq;

957 958
	/* ordered wq for modesets */
	struct workqueue_struct *modeset_wq;
959 960
	/* unbound hipri wq for page flips/plane updates */
	struct workqueue_struct *flip_wq;
961

962 963 964 965 966
	/* Display functions */
	struct drm_i915_display_funcs display;

	/* PCH chipset type */
	enum intel_pch pch_type;
967
	unsigned short pch_id;
968 969 970

	unsigned long quirks;

971
	struct drm_atomic_state *modeset_restore_state;
972
	struct drm_modeset_acquire_ctx reset_ctx;
973

974
	struct i915_ggtt ggtt; /* VM representing the global address space */
B
Ben Widawsky 已提交
975

976
	struct i915_gem_mm mm;
977
	DECLARE_HASHTABLE(mm_structs, 7);
978
	spinlock_t mm_lock;
979 980 981

	/* Kernel Modesetting */

982 983
	struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
	struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
984

985 986 987 988 989
	/**
	 * dpll and cdclk state is protected by connection_mutex
	 * dpll.lock serializes intel_{prepare,enable,disable}_shared_dpll.
	 * Must be global rather than per dpll, because on some platforms plls
	 * share registers.
990
	 */
991 992 993 994 995 996
	struct {
		struct mutex lock;

		int num_shared_dpll;
		struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
		const struct intel_dpll_mgr *mgr;
997 998 999 1000 1001

		struct {
			int nssc;
			int ssc;
		} ref_clks;
1002
	} dpll;
1003

1004 1005
	struct list_head global_obj_list;

1006
	/*
1007 1008
	 * For reading active_pipes holding any crtc lock is
	 * sufficient, for writing must hold all of them.
1009
	 */
1010
	u8 active_pipes;
1011

1012
	struct i915_wa_list gt_wa_list;
1013

1014 1015
	struct i915_frontbuffer_tracking fb_tracking;

1016 1017 1018 1019 1020
	struct intel_atomic_helper {
		struct llist_head free_list;
		struct work_struct free_work;
	} atomic_helper;

1021
	bool mchbar_need_disable;
1022

1023 1024
	struct intel_l3_parity l3_parity;

M
Matt Roper 已提交
1025 1026 1027 1028 1029 1030 1031 1032
	/*
	 * HTI (aka HDPORT) state read during initial hw readout.  Most
	 * platforms don't have HTI, so this will just stay 0.  Those that do
	 * will use this later to figure out which PLLs and PHYs are unavailable
	 * for driver usage.
	 */
	u32 hti_state;

1033 1034 1035 1036 1037
	/*
	 * edram size in MB.
	 * Cannot be determined by PCIID. You must always read a register.
	 */
	u32 edram_size_mb;
B
Ben Widawsky 已提交
1038

1039
	struct i915_power_domains power_domains;
1040

R
Rodrigo Vivi 已提交
1041
	struct i915_psr psr;
1042

1043
	struct i915_gpu_error gpu_error;
1044

1045 1046
	struct drm_i915_gem_object *vlv_pctx;

1047 1048
	/* list of fbdev register on this device */
	struct intel_fbdev *fbdev;
1049
	struct work_struct fbdev_suspend_work;
1050 1051

	struct drm_property *broadcast_rgb_property;
1052
	struct drm_property *force_audio_property;
1053

I
Imre Deak 已提交
1054
	/* hda/i915 audio component */
1055
	struct i915_audio_component *audio_component;
I
Imre Deak 已提交
1056
	bool audio_component_registered;
1057 1058 1059 1060 1061
	/**
	 * av_mutex - mutex for audio/video sync
	 *
	 */
	struct mutex av_mutex;
1062
	int audio_power_refcount;
1063
	u32 audio_freq_cntrl;
I
Imre Deak 已提交
1064

1065
	u32 fdi_rx_config;
1066

1067
	/* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1068
	u32 chv_phy_control;
1069 1070 1071 1072 1073 1074
	/*
	 * Shadows for CHV DPLL_MD regs to keep the state
	 * checker somewhat working in the presence hardware
	 * crappiness (can't read out DPLL_MD for pipes B & C).
	 */
	u32 chv_dpll_md[I915_MAX_PIPES];
1075
	u32 bxt_phy_grc;
1076

1077
	u32 suspend_count;
1078
	bool power_domains_suspended;
1079
	struct i915_suspend_saved_registers regfile;
1080
	struct vlv_s0ix_state *vlv_s0ix_state;
1081

1082
	enum {
1083 1084 1085 1086 1087
		I915_SAGV_UNKNOWN = 0,
		I915_SAGV_DISABLED,
		I915_SAGV_ENABLED,
		I915_SAGV_NOT_CONTROLLED
	} sagv_status;
1088

1089 1090
	u32 sagv_block_time_us;

1091 1092 1093 1094 1095 1096 1097
	struct {
		/*
		 * Raw watermark latency values:
		 * in 0.1us units for WM0,
		 * in 0.5us units for WM1+.
		 */
		/* primary */
1098
		u16 pri_latency[5];
1099
		/* sprite */
1100
		u16 spr_latency[5];
1101
		/* cursor */
1102
		u16 cur_latency[5];
1103 1104 1105 1106 1107
		/*
		 * Raw watermark memory latency values
		 * for SKL for all 8 levels
		 * in 1us units.
		 */
1108
		u16 skl_latency[8];
1109 1110

		/* current hardware state */
1111 1112
		union {
			struct ilk_wm_values hw;
1113
			struct vlv_wm_values vlv;
1114
			struct g4x_wm_values g4x;
1115
		};
1116

1117
		u8 max_level;
1118 1119 1120 1121

		/*
		 * Should be held around atomic WM register writing; also
		 * protects * intel_crtc->wm.active and
1122
		 * crtc_state->wm.need_postvbl_update.
1123 1124
		 */
		struct mutex wm_mutex;
1125 1126
	} wm;

1127
	struct dram_info {
1128
		bool is_16gb_dimm;
1129
		u8 num_channels;
1130
		bool symmetric_memory;
V
Ville Syrjälä 已提交
1131 1132 1133 1134 1135 1136 1137
		enum intel_dram_type {
			INTEL_DRAM_UNKNOWN,
			INTEL_DRAM_DDR3,
			INTEL_DRAM_DDR4,
			INTEL_DRAM_LPDDR3,
			INTEL_DRAM_LPDDR4
		} type;
1138 1139
	} dram_info;

1140
	struct intel_bw_info {
1141 1142
		/* for each QGV point */
		unsigned int deratedbw[I915_NUM_QGV_POINTS];
1143 1144
		u8 num_qgv_points;
		u8 num_planes;
1145 1146
	} max_bw[6];

1147
	struct intel_global_obj bw_obj;
1148

1149
	struct intel_runtime_pm runtime_pm;
1150

1151
	struct i915_perf perf;
1152

1153
	/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1154
	struct intel_gt gt;
1155 1156

	struct {
1157 1158 1159 1160
		struct i915_gem_contexts {
			spinlock_t lock; /* locks list */
			struct list_head list;
		} contexts;
1161 1162 1163 1164 1165 1166 1167 1168 1169 1170

		/*
		 * We replace the local file with a global mappings as the
		 * backing storage for the mmap is on the device and not
		 * on the struct file, and we do not want to prolong the
		 * lifetime of the local fd. To minimise the number of
		 * anonymous inodes we create, we use a global singleton to
		 * share the global mapping.
		 */
		struct file *mmap_singleton;
1171
	} gem;
1172

1173 1174
	u8 framestart_delay;

1175 1176
	u8 pch_ssc_use;

1177 1178
	/* For i915gm/i945gm vblank irq workaround */
	u8 vblank_enabled;
1179

1180 1181 1182
	/* perform PHY state sanity checks? */
	bool chv_phy_assert[2];

M
Mahesh Kumar 已提交
1183 1184
	bool ipc_enabled;

1185 1186
	/* Used to save the pipe-to-encoder mapping for audio */
	struct intel_encoder *av_enc_map[I915_MAX_PIPES];
1187

1188 1189 1190 1191 1192 1193
	/* necessary resource sharing with HDMI LPE audio driver. */
	struct {
		struct platform_device *platdev;
		int	irq;
	} lpe_audio;

1194 1195
	struct i915_pmu pmu;

1196 1197 1198 1199 1200 1201
	struct i915_hdcp_comp_master *hdcp_master;
	bool hdcp_comp_added;

	/* Mutex to protect the above hdcp component related values. */
	struct mutex hdcp_comp_mutex;

1202 1203
	I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)

1204 1205 1206 1207
	/*
	 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
	 * will be rejected. Instead look for a better place.
	 */
1208
};
L
Linus Torvalds 已提交
1209

1210 1211
static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
{
1212
	return container_of(dev, struct drm_i915_private, drm);
1213 1214
}

1215
static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
I
Imre Deak 已提交
1216
{
1217 1218 1219 1220 1221 1222
	return dev_get_drvdata(kdev);
}

static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
{
	return pci_get_drvdata(pdev);
I
Imre Deak 已提交
1223 1224
}

1225
/* Simple iterator over all initialised engines */
1226 1227 1228 1229 1230
#define for_each_engine(engine__, dev_priv__, id__) \
	for ((id__) = 0; \
	     (id__) < I915_NUM_ENGINES; \
	     (id__)++) \
		for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
1231 1232

/* Iterator over subset of engines selected by mask */
1233
#define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
1234
	for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
1235
	     (tmp__) ? \
1236
	     ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
1237
	     0;)
1238

1239 1240 1241 1242 1243 1244 1245 1246
#define rb_to_uabi_engine(rb) \
	rb_entry_safe(rb, struct intel_engine_cs, uabi_node)

#define for_each_uabi_engine(engine__, i915__) \
	for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
	     (engine__); \
	     (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))

1247 1248 1249 1250 1251
#define for_each_uabi_class_engine(engine__, class__, i915__) \
	for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \
	     (engine__) && (engine__)->uabi_class == (class__); \
	     (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))

1252
#define I915_GTT_OFFSET_NONE ((u32)-1)
1253

1254 1255
/*
 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1256
 * considered to be the frontbuffer for the given plane interface-wise. This
1257 1258 1259 1260 1261
 * doesn't mean that the hw necessarily already scans it out, but that any
 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
 *
 * We have one bit per pipe and per scanout plane type.
 */
1262
#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
1263 1264 1265 1266 1267
#define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
	BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
	BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
	BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
})
1268
#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1269
	BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1270
#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1271 1272
	GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
		INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1273

1274
#define INTEL_INFO(dev_priv)	(&(dev_priv)->__info)
1275
#define RUNTIME_INFO(dev_priv)	(&(dev_priv)->__runtime)
1276
#define DRIVER_CAPS(dev_priv)	(&(dev_priv)->caps)
1277

1278
#define INTEL_GEN(dev_priv)	(INTEL_INFO(dev_priv)->gen)
1279
#define INTEL_DEVID(dev_priv)	(RUNTIME_INFO(dev_priv)->device_id)
1280

1281
#define REVID_FOREVER		0xff
1282
#define INTEL_REVID(dev_priv)	((dev_priv)->drm.pdev->revision)
1283

1284 1285 1286
#define INTEL_GEN_MASK(s, e) ( \
	BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
	BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
R
Rodrigo Vivi 已提交
1287
	GENMASK((e) - 1, (s) - 1))
1288

R
Rodrigo Vivi 已提交
1289
/* Returns true if Gen is in inclusive range [Start, End] */
1290
#define IS_GEN_RANGE(dev_priv, s, e) \
1291
	(!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
1292

1293 1294
#define IS_GEN(dev_priv, n) \
	(BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
1295
	 INTEL_INFO(dev_priv)->gen == (n))
1296

1297 1298
#define HAS_DSB(dev_priv)	(INTEL_INFO(dev_priv)->display.has_dsb)

1299 1300 1301 1302 1303 1304 1305 1306
/*
 * Return true if revision is in range [since,until] inclusive.
 *
 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
 */
#define IS_REVID(p, since, until) \
	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))

1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367
static __always_inline unsigned int
__platform_mask_index(const struct intel_runtime_info *info,
		      enum intel_platform p)
{
	const unsigned int pbits =
		BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;

	/* Expand the platform_mask array if this fails. */
	BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
		     pbits * ARRAY_SIZE(info->platform_mask));

	return p / pbits;
}

static __always_inline unsigned int
__platform_mask_bit(const struct intel_runtime_info *info,
		    enum intel_platform p)
{
	const unsigned int pbits =
		BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;

	return p % pbits + INTEL_SUBPLATFORM_BITS;
}

static inline u32
intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
{
	const unsigned int pi = __platform_mask_index(info, p);

	return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS;
}

static __always_inline bool
IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
{
	const struct intel_runtime_info *info = RUNTIME_INFO(i915);
	const unsigned int pi = __platform_mask_index(info, p);
	const unsigned int pb = __platform_mask_bit(info, p);

	BUILD_BUG_ON(!__builtin_constant_p(p));

	return info->platform_mask[pi] & BIT(pb);
}

static __always_inline bool
IS_SUBPLATFORM(const struct drm_i915_private *i915,
	       enum intel_platform p, unsigned int s)
{
	const struct intel_runtime_info *info = RUNTIME_INFO(i915);
	const unsigned int pi = __platform_mask_index(info, p);
	const unsigned int pb = __platform_mask_bit(info, p);
	const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
	const u32 mask = info->platform_mask[pi];

	BUILD_BUG_ON(!__builtin_constant_p(p));
	BUILD_BUG_ON(!__builtin_constant_p(s));
	BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);

	/* Shift and test on the MSB position so sign flag can be used. */
	return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
}
T
Tvrtko Ursulin 已提交
1368

1369
#define IS_MOBILE(dev_priv)	(INTEL_INFO(dev_priv)->is_mobile)
1370
#define IS_DGFX(dev_priv)   (INTEL_INFO(dev_priv)->is_dgfx)
1371

T
Tvrtko Ursulin 已提交
1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383
#define IS_I830(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I830)
#define IS_I845G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I845G)
#define IS_I85X(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I85X)
#define IS_I865G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I865G)
#define IS_I915G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915G)
#define IS_I915GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915GM)
#define IS_I945G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I945G)
#define IS_I945GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I945GM)
#define IS_I965G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I965G)
#define IS_I965GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I965GM)
#define IS_G45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G45)
#define IS_GM45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GM45)
1384
#define IS_G4X(dev_priv)	(IS_G45(dev_priv) || IS_GM45(dev_priv))
T
Tvrtko Ursulin 已提交
1385 1386
#define IS_PINEVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
#define IS_G33(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G33)
1387 1388 1389
#define IS_IRONLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
#define IS_IRONLAKE_M(dev_priv) \
	(IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
T
Tvrtko Ursulin 已提交
1390
#define IS_IVYBRIDGE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
1391
#define IS_IVB_GT1(dev_priv)	(IS_IVYBRIDGE(dev_priv) && \
1392
				 INTEL_INFO(dev_priv)->gt == 1)
T
Tvrtko Ursulin 已提交
1393 1394 1395 1396 1397 1398 1399 1400 1401
#define IS_VALLEYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
#define IS_CHERRYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
#define IS_HASWELL(dev_priv)	IS_PLATFORM(dev_priv, INTEL_HASWELL)
#define IS_BROADWELL(dev_priv)	IS_PLATFORM(dev_priv, INTEL_BROADWELL)
#define IS_SKYLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
#define IS_BROXTON(dev_priv)	IS_PLATFORM(dev_priv, INTEL_BROXTON)
#define IS_KABYLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
#define IS_GEMINILAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
#define IS_COFFEELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
1402
#define IS_COMETLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
T
Tvrtko Ursulin 已提交
1403
#define IS_CANNONLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
1404
#define IS_ICELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ICELAKE)
1405 1406
#define IS_JSL_EHL(dev_priv)	(IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \
				IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
1407
#define IS_TIGERLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
1408
#define IS_ROCKETLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
1409
#define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
1410 1411
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
1412 1413 1414 1415
#define IS_BDW_ULT(dev_priv) \
	IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
#define IS_BDW_ULX(dev_priv) \
	IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
1416
#define IS_BDW_GT3(dev_priv)	(IS_BROADWELL(dev_priv) && \
1417
				 INTEL_INFO(dev_priv)->gt == 3)
1418 1419
#define IS_HSW_ULT(dev_priv) \
	IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
1420
#define IS_HSW_GT3(dev_priv)	(IS_HASWELL(dev_priv) && \
1421
				 INTEL_INFO(dev_priv)->gt == 3)
1422
#define IS_HSW_GT1(dev_priv)	(IS_HASWELL(dev_priv) && \
1423
				 INTEL_INFO(dev_priv)->gt == 1)
1424
/* ULX machines are also considered ULT. */
1425 1426 1427 1428 1429 1430 1431 1432 1433 1434
#define IS_HSW_ULX(dev_priv) \
	IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
#define IS_SKL_ULT(dev_priv) \
	IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
#define IS_SKL_ULX(dev_priv) \
	IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
#define IS_KBL_ULT(dev_priv) \
	IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
#define IS_KBL_ULX(dev_priv) \
	IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
1435
#define IS_SKL_GT2(dev_priv)	(IS_SKYLAKE(dev_priv) && \
1436
				 INTEL_INFO(dev_priv)->gt == 2)
1437
#define IS_SKL_GT3(dev_priv)	(IS_SKYLAKE(dev_priv) && \
1438
				 INTEL_INFO(dev_priv)->gt == 3)
1439
#define IS_SKL_GT4(dev_priv)	(IS_SKYLAKE(dev_priv) && \
1440
				 INTEL_INFO(dev_priv)->gt == 4)
1441
#define IS_KBL_GT2(dev_priv)	(IS_KABYLAKE(dev_priv) && \
1442
				 INTEL_INFO(dev_priv)->gt == 2)
1443
#define IS_KBL_GT3(dev_priv)	(IS_KABYLAKE(dev_priv) && \
1444
				 INTEL_INFO(dev_priv)->gt == 3)
1445 1446
#define IS_CFL_ULT(dev_priv) \
	IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
1447 1448
#define IS_CFL_ULX(dev_priv) \
	IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
1449
#define IS_CFL_GT2(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
1450
				 INTEL_INFO(dev_priv)->gt == 2)
1451
#define IS_CFL_GT3(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
1452
				 INTEL_INFO(dev_priv)->gt == 3)
1453 1454 1455 1456 1457 1458 1459 1460

#define IS_CML_ULT(dev_priv) \
	IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
#define IS_CML_ULX(dev_priv) \
	IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
#define IS_CML_GT2(dev_priv)	(IS_COMETLAKE(dev_priv) && \
				 INTEL_INFO(dev_priv)->gt == 2)

1461 1462 1463 1464
#define IS_CNL_WITH_PORT_F(dev_priv) \
	IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
#define IS_ICL_WITH_PORT_F(dev_priv) \
	IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
1465

1466 1467 1468 1469 1470 1471
#define IS_TGL_U(dev_priv) \
	IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULT)

#define IS_TGL_Y(dev_priv) \
	IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULX)

1472 1473 1474 1475 1476 1477
#define SKL_REVID_A0		0x0
#define SKL_REVID_B0		0x1
#define SKL_REVID_C0		0x2
#define SKL_REVID_D0		0x3
#define SKL_REVID_E0		0x4
#define SKL_REVID_F0		0x5
1478 1479
#define SKL_REVID_G0		0x6
#define SKL_REVID_H0		0x7
1480

1481 1482
#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))

1483
#define BXT_REVID_A0		0x0
1484
#define BXT_REVID_A1		0x1
1485
#define BXT_REVID_B0		0x3
1486
#define BXT_REVID_B_LAST	0x8
1487
#define BXT_REVID_C0		0x9
N
Nick Hoath 已提交
1488

1489 1490
#define IS_BXT_REVID(dev_priv, since, until) \
	(IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
1491

1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519
enum {
	KBL_REVID_A0,
	KBL_REVID_B0,
	KBL_REVID_B1,
	KBL_REVID_C0,
	KBL_REVID_D0,
	KBL_REVID_D1,
	KBL_REVID_E0,
	KBL_REVID_F0,
	KBL_REVID_G0,
};

struct i915_rev_steppings {
	u8 gt_stepping;
	u8 disp_stepping;
};

/* Defined in intel_workarounds.c */
extern const struct i915_rev_steppings kbl_revids[];

#define IS_KBL_GT_REVID(dev_priv, since, until) \
	(IS_KABYLAKE(dev_priv) && \
	 kbl_revids[INTEL_REVID(dev_priv)].gt_stepping >= since && \
	 kbl_revids[INTEL_REVID(dev_priv)].gt_stepping <= until)
#define IS_KBL_DISP_REVID(dev_priv, since, until) \
	(IS_KABYLAKE(dev_priv) && \
	 kbl_revids[INTEL_REVID(dev_priv)].disp_stepping >= since && \
	 kbl_revids[INTEL_REVID(dev_priv)].disp_stepping <= until)
M
Mika Kuoppala 已提交
1520

1521 1522
#define GLK_REVID_A0		0x0
#define GLK_REVID_A1		0x1
1523 1524
#define GLK_REVID_A2		0x2
#define GLK_REVID_B0		0x3
1525 1526 1527 1528

#define IS_GLK_REVID(dev_priv, since, until) \
	(IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))

1529 1530
#define CNL_REVID_A0		0x0
#define CNL_REVID_B0		0x1
R
Rodrigo Vivi 已提交
1531
#define CNL_REVID_C0		0x2
1532 1533 1534 1535

#define IS_CNL_REVID(p, since, until) \
	(IS_CANNONLAKE(p) && IS_REVID(p, since, until))

1536 1537 1538 1539 1540 1541 1542 1543 1544
#define ICL_REVID_A0		0x0
#define ICL_REVID_A2		0x1
#define ICL_REVID_B0		0x3
#define ICL_REVID_B2		0x4
#define ICL_REVID_C0		0x5

#define IS_ICL_REVID(p, since, until) \
	(IS_ICELAKE(p) && IS_REVID(p, since, until))

1545
#define EHL_REVID_A0            0x0
1546
#define EHL_REVID_B0            0x1
1547

1548 1549
#define IS_JSL_EHL_REVID(p, since, until) \
	(IS_JSL_EHL(p) && IS_REVID(p, since, until))
1550

1551 1552 1553 1554 1555 1556 1557 1558
enum {
	TGL_REVID_A0,
	TGL_REVID_B0,
	TGL_REVID_B1,
	TGL_REVID_C0,
	TGL_REVID_D0,
};

1559 1560 1561 1562 1563
#define TGL_UY_REVIDS_SIZE	4
#define TGL_REVIDS_SIZE		2

extern const struct i915_rev_steppings tgl_uy_revids[TGL_UY_REVIDS_SIZE];
extern const struct i915_rev_steppings tgl_revids[TGL_REVIDS_SIZE];
1564 1565 1566 1567

static inline const struct i915_rev_steppings *
tgl_revids_get(struct drm_i915_private *dev_priv)
{
1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582
	u8 revid = INTEL_REVID(dev_priv);
	u8 size;
	const struct i915_rev_steppings *tgl_revid_tbl;

	if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
		tgl_revid_tbl = tgl_uy_revids;
		size = ARRAY_SIZE(tgl_uy_revids);
	} else {
		tgl_revid_tbl = tgl_revids;
		size = ARRAY_SIZE(tgl_revids);
	}

	revid = min_t(u8, revid, size - 1);

	return &tgl_revid_tbl[revid];
1583
}
M
Mika Kuoppala 已提交
1584

1585 1586 1587 1588 1589 1590 1591
#define IS_TGL_DISP_REVID(p, since, until) \
	(IS_TIGERLAKE(p) && \
	 tgl_revids_get(p)->disp_stepping >= (since) && \
	 tgl_revids_get(p)->disp_stepping <= (until))

#define IS_TGL_UY_GT_REVID(p, since, until) \
	((IS_TGL_U(p) || IS_TGL_Y(p)) && \
1592 1593
	 tgl_revids_get(p)->gt_stepping >= (since) && \
	 tgl_revids_get(p)->gt_stepping <= (until))
1594 1595 1596 1597

#define IS_TGL_GT_REVID(p, since, until) \
	(IS_TIGERLAKE(p) && \
	 !(IS_TGL_U(p) || IS_TGL_Y(p)) && \
1598 1599
	 tgl_revids_get(p)->gt_stepping >= (since) && \
	 tgl_revids_get(p)->gt_stepping <= (until))
M
Mika Kuoppala 已提交
1600

1601 1602 1603 1604 1605 1606 1607
#define RKL_REVID_A0		0x0
#define RKL_REVID_B0		0x1
#define RKL_REVID_C0		0x4

#define IS_RKL_REVID(p, since, until) \
	(IS_ROCKETLAKE(p) && IS_REVID(p, since, until))

1608 1609 1610 1611 1612 1613
#define DG1_REVID_A0		0x0
#define DG1_REVID_B0		0x1

#define IS_DG1_REVID(p, since, until) \
	(IS_DG1(p) && IS_REVID(p, since, until))

1614
#define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
1615 1616
#define IS_GEN9_LP(dev_priv)	(IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
#define IS_GEN9_BC(dev_priv)	(IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
1617

1618
#define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
1619
#define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
1620

1621
#define ENGINE_INSTANCES_MASK(gt, first, count) ({		\
1622 1623
	unsigned int first__ = (first);					\
	unsigned int count__ = (count);					\
1624
	((gt)->info.engine_mask &						\
1625
	 GENMASK(first__ + count__ - 1, first__)) >> first__;		\
1626
})
1627 1628 1629 1630
#define VDBOX_MASK(gt) \
	ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
#define VEBOX_MASK(gt) \
	ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
1631

1632 1633 1634 1635 1636 1637
/*
 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
 * All later gens can run the final buffer from the ppgtt
 */
#define CMDPARSER_USES_GGTT(dev_priv) IS_GEN(dev_priv, 7)

1638 1639
#define HAS_LLC(dev_priv)	(INTEL_INFO(dev_priv)->has_llc)
#define HAS_SNOOP(dev_priv)	(INTEL_INFO(dev_priv)->has_snoop)
1640
#define HAS_EDRAM(dev_priv)	((dev_priv)->edram_size_mb)
1641
#define HAS_SECURE_BATCHES(dev_priv) (INTEL_GEN(dev_priv) < 6)
1642
#define HAS_WT(dev_priv)	HAS_EDRAM(dev_priv)
1643

1644
#define HWS_NEEDS_PHYSICAL(dev_priv)	(INTEL_INFO(dev_priv)->hws_needs_physical)
1645

1646
#define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
1647
		(INTEL_INFO(dev_priv)->has_logical_ring_contexts)
1648
#define HAS_LOGICAL_RING_ELSQ(dev_priv) \
1649
		(INTEL_INFO(dev_priv)->has_logical_ring_elsq)
1650

1651 1652
#define HAS_MASTER_UNIT_IRQ(dev_priv) (INTEL_INFO(dev_priv)->has_master_unit_irq)

1653 1654
#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)

1655
#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
1656 1657 1658 1659 1660
#define HAS_PPGTT(dev_priv) \
	(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
#define HAS_FULL_PPGTT(dev_priv) \
	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)

1661 1662
#define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
	GEM_BUG_ON((sizes) == 0); \
1663
	((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
1664
})
1665

1666
#define HAS_OVERLAY(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_overlay)
1667
#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
1668
		(INTEL_INFO(dev_priv)->display.overlay_needs_physical)
1669

1670
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
1671
#define HAS_BROKEN_CS_TLB(dev_priv)	(IS_I830(dev_priv) || IS_I845G(dev_priv))
1672

1673 1674 1675
#define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv)	\
	(IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9))

1676
/* WaRsDisableCoarsePowerGating:skl,cnl */
1677 1678 1679 1680
#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv)			\
	(IS_CANNONLAKE(dev_priv) ||					\
	 IS_SKL_GT3(dev_priv) ||					\
	 IS_SKL_GT4(dev_priv))
1681

1682
#define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
R
Ramalingam C 已提交
1683 1684 1685
#define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
					IS_GEMINILAKE(dev_priv) || \
					IS_KABYLAKE(dev_priv))
1686

1687 1688 1689
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 * rows, which changed the alignment requirements and fence programming.
 */
1690
#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
1691 1692
					 !(IS_I915G(dev_priv) || \
					 IS_I915GM(dev_priv)))
1693 1694
#define SUPPORTS_TV(dev_priv)		(INTEL_INFO(dev_priv)->display.supports_tv)
#define I915_HAS_HOTPLUG(dev_priv)	(INTEL_INFO(dev_priv)->display.has_hotplug)
1695

1696
#define HAS_FW_BLC(dev_priv) 	(INTEL_GEN(dev_priv) > 2)
1697
#define HAS_FBC(dev_priv)	(INTEL_INFO(dev_priv)->display.has_fbc)
R
Rodrigo Vivi 已提交
1698
#define HAS_CUR_FBC(dev_priv)	(!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7)
1699

1700
#define HAS_IPS(dev_priv)	(IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
1701

1702
#define HAS_DP_MST(dev_priv)	(INTEL_INFO(dev_priv)->display.has_dp_mst)
1703

1704 1705 1706
#define HAS_DDI(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_ddi)
#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
#define HAS_PSR(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_psr)
1707 1708
#define HAS_PSR_HW_TRACKING(dev_priv) \
	(INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
1709
#define HAS_PSR2_SEL_FETCH(dev_priv)	 (INTEL_GEN(dev_priv) >= 12)
1710
#define HAS_TRANSCODER(dev_priv, trans)	 ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
1711

1712 1713
#define HAS_RC6(dev_priv)		 (INTEL_INFO(dev_priv)->has_rc6)
#define HAS_RC6p(dev_priv)		 (INTEL_INFO(dev_priv)->has_rc6p)
1714
#define HAS_RC6pp(dev_priv)		 (false) /* HW was never validated */
P
Paulo Zanoni 已提交
1715

1716 1717
#define HAS_RPS(dev_priv)	(INTEL_INFO(dev_priv)->has_rps)

1718
#define HAS_CSR(dev_priv)	(INTEL_INFO(dev_priv)->display.has_csr)
1719

1720 1721
#define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
#define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
1722

1723
#define HAS_IPC(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_ipc)
1724

1725
#define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
1726
#define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
1727

1728
#define HAS_GT_UC(dev_priv)	(INTEL_INFO(dev_priv)->has_gt_uc)
1729

1730
#define HAS_POOLED_EU(dev_priv)	(INTEL_INFO(dev_priv)->has_pooled_eu)
1731

1732 1733
#define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)	(INTEL_INFO(dev_priv)->has_global_mocs)

1734

R
Rodrigo Vivi 已提交
1735
#define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
1736

1737
#define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
1738

1739
/* DPF == dynamic parity feature */
1740
#define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
1741 1742
#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
				 2 : HAS_L3_DPF(dev_priv))
1743

1744
#define GT_FREQUENCY_MULTIPLIER 50
A
Akash Goel 已提交
1745
#define GEN9_FREQ_SCALER 3
1746

1747
#define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask))
1748

1749
#define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
1750

1751 1752
#define HAS_VRR(i915)	(INTEL_GEN(i915) >= 12)

1753
/* Only valid when HAS_DISPLAY() is true */
1754
#define INTEL_DISPLAY_ENABLED(dev_priv) \
1755
	(drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display)
1756

1757 1758 1759 1760 1761
static inline bool run_as_guest(void)
{
	return !hypervisor_is_type(X86_HYPER_NATIVE);
}

1762
static inline bool intel_vtd_active(void)
1763 1764
{
#ifdef CONFIG_INTEL_IOMMU
1765
	if (intel_iommu_gfx_mapped)
1766 1767
		return true;
#endif
1768 1769

	/* Running as a guest, we assume the host is enforcing VT'd */
1770
	return run_as_guest();
1771 1772
}

1773 1774 1775 1776 1777
static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
{
	return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
}

1778 1779 1780
static inline bool
intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
{
1781
	return IS_BROXTON(dev_priv) && intel_vtd_active();
1782 1783
}

1784
/* i915_drv.c */
1785 1786
extern const struct dev_pm_ops i915_pm_ops;

1787
int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
1788
void i915_driver_remove(struct drm_i915_private *i915);
1789
void i915_driver_shutdown(struct drm_i915_private *i915);
1790 1791 1792

int i915_resume_switcheroo(struct drm_i915_private *i915);
int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state);
1793

1794 1795 1796
int i915_getparam_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);

1797
/* i915_gem.c */
1798 1799
int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
1800
void i915_gem_init_early(struct drm_i915_private *dev_priv);
1801
void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
1802
int i915_gem_freeze(struct drm_i915_private *dev_priv);
1803 1804
int i915_gem_freeze_late(struct drm_i915_private *dev_priv);

M
Matthew Auld 已提交
1805 1806
struct intel_memory_region *i915_gem_shmem_setup(struct drm_i915_private *i915);

1807 1808
static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
{
1809 1810
	/*
	 * A single pass should suffice to release all the freed objects (along
1811 1812 1813 1814 1815
	 * most call paths) , but be a little more paranoid in that freeing
	 * the objects does take a little amount of time, during which the rcu
	 * callbacks could have added new objects into the freed list, and
	 * armed the work again.
	 */
1816 1817
	while (atomic_read(&i915->mm.free_count)) {
		flush_work(&i915->mm.free_work);
1818
		rcu_barrier();
1819
	}
1820 1821
}

1822 1823 1824 1825 1826 1827 1828 1829 1830 1831
static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
{
	/*
	 * Similar to objects above (see i915_gem_drain_freed-objects), in
	 * general we have workers that are armed by RCU and then rearm
	 * themselves in their callbacks. To be paranoid, we need to
	 * drain the workqueue a second time after waiting for the RCU
	 * grace period so that we catch work queued via RCU from the first
	 * pass. As neither drain_workqueue() nor flush_workqueue() report
	 * a result, we make an assumption that we only don't require more
1832
	 * than 3 passes to catch all _recursive_ RCU delayed work.
1833 1834
	 *
	 */
1835
	int pass = 3;
1836
	do {
1837
		flush_workqueue(i915->wq);
1838
		rcu_barrier();
1839
		i915_gem_drain_freed_objects(i915);
1840
	} while (--pass);
1841
	drain_workqueue(i915->wq);
1842 1843
}

C
Chris Wilson 已提交
1844
struct i915_vma * __must_check
1845 1846 1847 1848 1849 1850
i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj,
			    struct i915_gem_ww_ctx *ww,
			    const struct i915_ggtt_view *view,
			    u64 size, u64 alignment, u64 flags);

static inline struct i915_vma * __must_check
1851 1852
i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
			 const struct i915_ggtt_view *view,
1853 1854 1855 1856
			 u64 size, u64 alignment, u64 flags)
{
	return i915_gem_object_ggtt_pin_ww(obj, NULL, view, size, alignment, flags);
}
1857

1858 1859 1860
int i915_gem_object_unbind(struct drm_i915_gem_object *obj,
			   unsigned long flags);
#define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0)
1861
#define I915_GEM_OBJECT_UNBIND_BARRIER BIT(1)
1862
#define I915_GEM_OBJECT_UNBIND_TEST BIT(2)
1863

1864 1865
void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);

1866 1867 1868
int i915_gem_dumb_create(struct drm_file *file_priv,
			 struct drm_device *dev,
			 struct drm_mode_create_dumb *args);
1869

1870
int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
1871

M
Mika Kuoppala 已提交
1872 1873
static inline u32 i915_reset_count(struct i915_gpu_error *error)
{
1874
	return atomic_read(&error->reset_count);
1875
}
1876

1877
static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
1878
					  const struct intel_engine_cs *engine)
1879
{
1880
	return atomic_read(&error->reset_engine_count[engine->uabi_class]);
1881 1882
}

1883
int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
1884 1885
void i915_gem_driver_register(struct drm_i915_private *i915);
void i915_gem_driver_unregister(struct drm_i915_private *i915);
1886
void i915_gem_driver_remove(struct drm_i915_private *dev_priv);
1887
void i915_gem_driver_release(struct drm_i915_private *dev_priv);
1888
void i915_gem_suspend(struct drm_i915_private *dev_priv);
1889
void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
1890
void i915_gem_resume(struct drm_i915_private *dev_priv);
1891

1892
int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
1893

1894 1895 1896
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
				    enum i915_cache_level cache_level);

1897 1898 1899
struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
				struct dma_buf *dma_buf);

1900
struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags);
1901

1902 1903 1904
static inline struct i915_gem_context *
__i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
{
1905
	return xa_load(&file_priv->context_xa, id);
1906 1907
}

1908 1909 1910 1911 1912
static inline struct i915_gem_context *
i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
{
	struct i915_gem_context *ctx;

1913 1914 1915 1916 1917
	rcu_read_lock();
	ctx = __i915_gem_context_lookup_rcu(file_priv, id);
	if (ctx && !kref_get_unless_zero(&ctx->ref))
		ctx = NULL;
	rcu_read_unlock();
1918 1919 1920 1921

	return ctx;
}

1922
/* i915_gem_evict.c */
1923
int __must_check i915_gem_evict_something(struct i915_address_space *vm,
1924
					  u64 min_size, u64 alignment,
M
Matthew Auld 已提交
1925
					  unsigned long color,
1926
					  u64 start, u64 end,
1927
					  unsigned flags);
1928 1929 1930
int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
					 struct drm_mm_node *node,
					 unsigned int flags);
1931
int i915_gem_evict_vm(struct i915_address_space *vm);
1932

1933 1934 1935
/* i915_gem_internal.c */
struct drm_i915_gem_object *
i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
1936
				phys_addr_t size);
1937

1938
/* i915_gem_tiling.c */
1939
static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
1940
{
1941
	struct drm_i915_private *i915 = to_i915(obj->base.dev);
1942

1943
	return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
1944
		i915_gem_object_is_tiled(obj);
1945 1946
}

1947 1948 1949 1950 1951
u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
			unsigned int tiling, unsigned int stride);
u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
			     unsigned int tiling, unsigned int stride);

1952
const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
1953

1954
/* i915_cmd_parser.c */
1955
int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
1956
void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
1957
void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
1958
int intel_engine_cmd_parser(struct intel_engine_cs *engine,
1959
			    struct i915_vma *batch,
1960 1961
			    unsigned long batch_offset,
			    unsigned long batch_length,
1962 1963 1964
			    struct i915_vma *shadow,
			    bool trampoline);
#define I915_CMD_PARSER_TRAMPOLINE_SIZE 8
1965

1966 1967 1968 1969
/* intel_device_info.c */
static inline struct intel_device_info *
mkwrite_device_info(struct drm_i915_private *dev_priv)
{
1970
	return (struct intel_device_info *)INTEL_INFO(dev_priv);
1971 1972
}

B
Ben Widawsky 已提交
1973 1974
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file);
1975

1976 1977 1978 1979
/* i915_mm.c */
int remap_io_mapping(struct vm_area_struct *vma,
		     unsigned long addr, unsigned long pfn, unsigned long size,
		     struct io_mapping *iomap);
1980 1981 1982
int remap_io_sg(struct vm_area_struct *vma,
		unsigned long addr, unsigned long size,
		struct scatterlist *sgl, resource_size_t iobase);
1983

1984 1985 1986 1987 1988 1989 1990 1991
static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
{
	if (INTEL_GEN(i915) >= 10)
		return CNL_HWS_CSB_WRITE_INDEX;
	else
		return I915_HWS_CSB_WRITE_INDEX;
}

1992 1993 1994 1995 1996 1997
static inline enum i915_map_type
i915_coherent_map_type(struct drm_i915_private *i915)
{
	return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
}

L
Linus Torvalds 已提交
1998
#endif