intel_dp.c 170.6 KB
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/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Keith Packard <keithp@keithp.com>
 *
 */

#include <linux/i2c.h>
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#include <linux/slab.h>
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#include <linux/export.h>
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#include <linux/notifier.h>
#include <linux/reboot.h>
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#include <drm/drmP.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_edid.h>
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#include "intel_drv.h"
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#include <drm/i915_drm.h>
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#include "i915_drv.h"

#define DP_LINK_CHECK_TIMEOUT	(10 * 1000)

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/* Compliance test status bits  */
#define INTEL_DP_RESOLUTION_SHIFT_MASK	0
#define INTEL_DP_RESOLUTION_PREFERRED	(1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
#define INTEL_DP_RESOLUTION_STANDARD	(2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
#define INTEL_DP_RESOLUTION_FAILSAFE	(3 << INTEL_DP_RESOLUTION_SHIFT_MASK)

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struct dp_link_dpll {
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	int clock;
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	struct dpll dpll;
};

static const struct dp_link_dpll gen4_dpll[] = {
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	{ 162000,
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		{ .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
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	{ 270000,
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		{ .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
};

static const struct dp_link_dpll pch_dpll[] = {
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	{ 162000,
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		{ .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
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	{ 270000,
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		{ .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
};

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static const struct dp_link_dpll vlv_dpll[] = {
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	{ 162000,
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		{ .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
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	{ 270000,
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		{ .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
};

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/*
 * CHV supports eDP 1.4 that have  more link rates.
 * Below only provides the fixed rate but exclude variable rate.
 */
static const struct dp_link_dpll chv_dpll[] = {
	/*
	 * CHV requires to program fractional division for m2.
	 * m2 is stored in fixed point format using formula below
	 * (m2_int << 22) | m2_fraction
	 */
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	{ 162000,	/* m2_int = 32, m2_fraction = 1677722 */
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		{ .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
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	{ 270000,	/* m2_int = 27, m2_fraction = 0 */
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		{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
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	{ 540000,	/* m2_int = 27, m2_fraction = 0 */
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		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
};
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static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
				  324000, 432000, 540000 };
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static const int skl_rates[] = { 162000, 216000, 270000,
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				  324000, 432000, 540000 };
static const int default_rates[] = { 162000, 270000, 540000 };
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/**
 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 * @intel_dp: DP struct
 *
 * If a CPU or PCH DP output is attached to an eDP panel, this function
 * will return true, and false otherwise.
 */
static bool is_edp(struct intel_dp *intel_dp)
{
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	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
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}

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static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
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{
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	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	return intel_dig_port->base.base.dev;
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}

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static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
{
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	return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
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}

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static void intel_dp_link_down(struct intel_dp *intel_dp);
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static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
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static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
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static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
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static void vlv_steal_power_sequencer(struct drm_device *dev,
				      enum pipe pipe);
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static unsigned int intel_dp_unused_lane_mask(int lane_count)
{
	return ~((1 << lane_count) - 1) & 0xf;
}

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static int
intel_dp_max_link_bw(struct intel_dp  *intel_dp)
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{
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	int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
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	switch (max_link_bw) {
	case DP_LINK_BW_1_62:
	case DP_LINK_BW_2_7:
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	case DP_LINK_BW_5_4:
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		break;
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	default:
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		WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
		     max_link_bw);
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		max_link_bw = DP_LINK_BW_1_62;
		break;
	}
	return max_link_bw;
}

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static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	u8 source_max, sink_max;

	source_max = 4;
	if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
	    (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
		source_max = 2;

	sink_max = drm_dp_max_lane_count(intel_dp->dpcd);

	return min(source_max, sink_max);
}

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/*
 * The units on the numbers in the next two are... bizarre.  Examples will
 * make it clearer; this one parallels an example in the eDP spec.
 *
 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 *
 *     270000 * 1 * 8 / 10 == 216000
 *
 * The actual data capacity of that configuration is 2.16Gbit/s, so the
 * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 * 119000.  At 18bpp that's 2142000 kilobits per second.
 *
 * Thus the strange-looking division by 10 in intel_dp_link_required, to
 * get the result in decakilobits instead of kilobits.
 */

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static int
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intel_dp_link_required(int pixel_clock, int bpp)
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{
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	return (pixel_clock * bpp + 9) / 10;
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}

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static int
intel_dp_max_data_rate(int max_link_clock, int max_lanes)
{
	return (max_link_clock * max_lanes * 8) / 10;
}

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static enum drm_mode_status
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intel_dp_mode_valid(struct drm_connector *connector,
		    struct drm_display_mode *mode)
{
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	struct intel_dp *intel_dp = intel_attached_dp(connector);
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	struct intel_connector *intel_connector = to_intel_connector(connector);
	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
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	int target_clock = mode->clock;
	int max_rate, mode_rate, max_lanes, max_link_clock;
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	if (is_edp(intel_dp) && fixed_mode) {
		if (mode->hdisplay > fixed_mode->hdisplay)
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			return MODE_PANEL;

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		if (mode->vdisplay > fixed_mode->vdisplay)
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			return MODE_PANEL;
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		target_clock = fixed_mode->clock;
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	}

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	max_link_clock = intel_dp_max_link_rate(intel_dp);
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	max_lanes = intel_dp_max_lane_count(intel_dp);
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	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
	mode_rate = intel_dp_link_required(target_clock, 18);

	if (mode_rate > max_rate)
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		return MODE_CLOCK_HIGH;
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	if (mode->clock < 10000)
		return MODE_CLOCK_LOW;

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	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
		return MODE_H_ILLEGAL;

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	return MODE_OK;
}

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uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
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{
	int	i;
	uint32_t v = 0;

	if (src_bytes > 4)
		src_bytes = 4;
	for (i = 0; i < src_bytes; i++)
		v |= ((uint32_t) src[i]) << ((3-i) * 8);
	return v;
}

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static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
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{
	int i;
	if (dst_bytes > 4)
		dst_bytes = 4;
	for (i = 0; i < dst_bytes; i++)
		dst[i] = src >> ((3-i) * 8);
}

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static void
intel_dp_init_panel_power_sequencer(struct drm_device *dev,
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				    struct intel_dp *intel_dp);
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static void
intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
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					      struct intel_dp *intel_dp);
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static void pps_lock(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *encoder = &intel_dig_port->base;
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum intel_display_power_domain power_domain;

	/*
	 * See vlv_power_sequencer_reset() why we need
	 * a power domain reference here.
	 */
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	power_domain = intel_display_port_aux_power_domain(encoder);
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	intel_display_power_get(dev_priv, power_domain);

	mutex_lock(&dev_priv->pps_mutex);
}

static void pps_unlock(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *encoder = &intel_dig_port->base;
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum intel_display_power_domain power_domain;

	mutex_unlock(&dev_priv->pps_mutex);

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	power_domain = intel_display_port_aux_power_domain(encoder);
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	intel_display_power_put(dev_priv, power_domain);
}

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static void
vlv_power_sequencer_kick(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum pipe pipe = intel_dp->pps_pipe;
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	bool pll_enabled, release_cl_override = false;
	enum dpio_phy phy = DPIO_PHY(pipe);
	enum dpio_channel ch = vlv_pipe_to_channel(pipe);
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	uint32_t DP;

	if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
		 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
		 pipe_name(pipe), port_name(intel_dig_port->port)))
		return;

	DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
		      pipe_name(pipe), port_name(intel_dig_port->port));

	/* Preserve the BIOS-computed detected bit. This is
	 * supposed to be read-only.
	 */
	DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
	DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
	DP |= DP_PORT_WIDTH(1);
	DP |= DP_LINK_TRAIN_PAT_1;

	if (IS_CHERRYVIEW(dev))
		DP |= DP_PIPE_SELECT_CHV(pipe);
	else if (pipe == PIPE_B)
		DP |= DP_PIPEB_SELECT;

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	pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;

	/*
	 * The DPLL for the pipe must be enabled for this to work.
	 * So enable temporarily it if it's not already enabled.
	 */
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	if (!pll_enabled) {
		release_cl_override = IS_CHERRYVIEW(dev) &&
			!chv_phy_powergate_ch(dev_priv, phy, ch, true);

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		vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
				 &chv_dpll[0].dpll : &vlv_dpll[0].dpll);
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	}
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	/*
	 * Similar magic as in intel_dp_enable_port().
	 * We _must_ do this port enable + disable trick
	 * to make this power seqeuencer lock onto the port.
	 * Otherwise even VDD force bit won't work.
	 */
	I915_WRITE(intel_dp->output_reg, DP);
	POSTING_READ(intel_dp->output_reg);

	I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
	POSTING_READ(intel_dp->output_reg);

	I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
	POSTING_READ(intel_dp->output_reg);
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	if (!pll_enabled) {
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		vlv_force_pll_off(dev, pipe);
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		if (release_cl_override)
			chv_phy_powergate_ch(dev_priv, phy, ch, false);
	}
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}

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static enum pipe
vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct intel_encoder *encoder;
	unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
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	enum pipe pipe;
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	lockdep_assert_held(&dev_priv->pps_mutex);
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	/* We should never land here with regular DP ports */
	WARN_ON(!is_edp(intel_dp));

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	if (intel_dp->pps_pipe != INVALID_PIPE)
		return intel_dp->pps_pipe;

	/*
	 * We don't have power sequencer currently.
	 * Pick one that's not used by other ports.
	 */
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		struct intel_dp *tmp;

		if (encoder->type != INTEL_OUTPUT_EDP)
			continue;

		tmp = enc_to_intel_dp(&encoder->base);

		if (tmp->pps_pipe != INVALID_PIPE)
			pipes &= ~(1 << tmp->pps_pipe);
	}

	/*
	 * Didn't find one. This should not happen since there
	 * are two power sequencers and up to two eDP ports.
	 */
	if (WARN_ON(pipes == 0))
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		pipe = PIPE_A;
	else
		pipe = ffs(pipes) - 1;
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	vlv_steal_power_sequencer(dev, pipe);
	intel_dp->pps_pipe = pipe;
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	DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
		      pipe_name(intel_dp->pps_pipe),
		      port_name(intel_dig_port->port));

	/* init power sequencer on this pipe and port */
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	intel_dp_init_panel_power_sequencer(dev, intel_dp);
	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
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	/*
	 * Even vdd force doesn't work until we've made
	 * the power sequencer lock in on the port.
	 */
	vlv_power_sequencer_kick(intel_dp);
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	return intel_dp->pps_pipe;
}

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typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
			       enum pipe pipe);

static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
			       enum pipe pipe)
{
	return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
}

static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
				enum pipe pipe)
{
	return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
}

static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
			 enum pipe pipe)
{
	return true;
}
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static enum pipe
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vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
		     enum port port,
		     vlv_pipe_check pipe_check)
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{
	enum pipe pipe;
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	for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
		u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
			PANEL_PORT_SELECT_MASK;
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		if (port_sel != PANEL_PORT_SELECT_VLV(port))
			continue;

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		if (!pipe_check(dev_priv, pipe))
			continue;

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		return pipe;
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	}

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	return INVALID_PIPE;
}

static void
vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = intel_dig_port->port;

	lockdep_assert_held(&dev_priv->pps_mutex);

	/* try to find a pipe with this port selected */
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	/* first pick one where the panel is on */
	intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
						  vlv_pipe_has_pp_on);
	/* didn't find one? pick one where vdd is on */
	if (intel_dp->pps_pipe == INVALID_PIPE)
		intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
							  vlv_pipe_has_vdd_on);
	/* didn't find one? pick one with just the correct port */
	if (intel_dp->pps_pipe == INVALID_PIPE)
		intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
							  vlv_pipe_any);
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	/* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
	if (intel_dp->pps_pipe == INVALID_PIPE) {
		DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
			      port_name(port));
		return;
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	}

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	DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
		      port_name(port), pipe_name(intel_dp->pps_pipe));

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	intel_dp_init_panel_power_sequencer(dev, intel_dp);
	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
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}

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void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
{
	struct drm_device *dev = dev_priv->dev;
	struct intel_encoder *encoder;

	if (WARN_ON(!IS_VALLEYVIEW(dev)))
		return;

	/*
	 * We can't grab pps_mutex here due to deadlock with power_domain
	 * mutex when power_domain functions are called while holding pps_mutex.
	 * That also means that in order to use pps_pipe the code needs to
	 * hold both a power domain reference and pps_mutex, and the power domain
	 * reference get/put must be done while _not_ holding pps_mutex.
	 * pps_{lock,unlock}() do these steps in the correct order, so one
	 * should use them always.
	 */

	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		struct intel_dp *intel_dp;

		if (encoder->type != INTEL_OUTPUT_EDP)
			continue;

		intel_dp = enc_to_intel_dp(&encoder->base);
		intel_dp->pps_pipe = INVALID_PIPE;
	}
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}

static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);

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	if (IS_BROXTON(dev))
		return BXT_PP_CONTROL(0);
	else if (HAS_PCH_SPLIT(dev))
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		return PCH_PP_CONTROL;
	else
		return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
}

static u32 _pp_stat_reg(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);

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	if (IS_BROXTON(dev))
		return BXT_PP_STATUS(0);
	else if (HAS_PCH_SPLIT(dev))
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		return PCH_PP_STATUS;
	else
		return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
}

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/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
   This function only applicable when panel PM state is not to be tracked */
static int edp_notify_handler(struct notifier_block *this, unsigned long code,
			      void *unused)
{
	struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
						 edp_notifier);
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (!is_edp(intel_dp) || code != SYS_RESTART)
		return 0;

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	pps_lock(intel_dp);
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	if (IS_VALLEYVIEW(dev)) {
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		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
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		u32 pp_ctrl_reg, pp_div_reg;
		u32 pp_div;
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		pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
		pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
		pp_div = I915_READ(pp_div_reg);
		pp_div &= PP_REFERENCE_DIVIDER_MASK;

		/* 0x1F write to PP_DIV_REG sets max cycle delay */
		I915_WRITE(pp_div_reg, pp_div | 0x1F);
		I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
		msleep(intel_dp->panel_power_cycle_delay);
	}

599
	pps_unlock(intel_dp);
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600

601 602 603
	return 0;
}

604
static bool edp_have_panel_power(struct intel_dp *intel_dp)
605
{
606
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
607 608
	struct drm_i915_private *dev_priv = dev->dev_private;

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609 610
	lockdep_assert_held(&dev_priv->pps_mutex);

611 612 613 614
	if (IS_VALLEYVIEW(dev) &&
	    intel_dp->pps_pipe == INVALID_PIPE)
		return false;

615
	return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
616 617
}

618
static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
619
{
620
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
621 622
	struct drm_i915_private *dev_priv = dev->dev_private;

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623 624
	lockdep_assert_held(&dev_priv->pps_mutex);

625 626 627 628
	if (IS_VALLEYVIEW(dev) &&
	    intel_dp->pps_pipe == INVALID_PIPE)
		return false;

629
	return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
630 631
}

632 633 634
static void
intel_dp_check_edp(struct intel_dp *intel_dp)
{
635
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
636
	struct drm_i915_private *dev_priv = dev->dev_private;
637

638 639
	if (!is_edp(intel_dp))
		return;
640

641
	if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
642 643
		WARN(1, "eDP powered off while attempting aux channel communication.\n");
		DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
644 645
			      I915_READ(_pp_stat_reg(intel_dp)),
			      I915_READ(_pp_ctrl_reg(intel_dp)));
646 647 648
	}
}

649 650 651 652 653 654
static uint32_t
intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
655
	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
656 657 658
	uint32_t status;
	bool done;

659
#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
660
	if (has_aux_irq)
661
		done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
662
					  msecs_to_jiffies_timeout(10));
663 664 665 666 667 668 669 670 671 672
	else
		done = wait_for_atomic(C, 10) == 0;
	if (!done)
		DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
			  has_aux_irq);
#undef C

	return status;
}

673
static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
674
{
675 676
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
677

678 679 680
	/*
	 * The clock divider is based off the hrawclk, and would like to run at
	 * 2MHz.  So, take the hrawclk value and divide by 2 and use that
681
	 */
682 683 684 685 686 687 688
	return index ? 0 : intel_hrawclk(dev) / 2;
}

static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
689
	struct drm_i915_private *dev_priv = dev->dev_private;
690 691 692 693 694

	if (index)
		return 0;

	if (intel_dig_port->port == PORT_A) {
695 696
		return DIV_ROUND_UP(dev_priv->cdclk_freq, 2000);

697 698 699 700 701 702 703 704 705 706 707 708 709 710
	} else {
		return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
	}
}

static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (intel_dig_port->port == PORT_A) {
		if (index)
			return 0;
711
		return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
712 713
	} else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
		/* Workaround for non-ULT HSW */
714 715 716 717 718
		switch (index) {
		case 0: return 63;
		case 1: return 72;
		default: return 0;
		}
719
	} else  {
720
		return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
721
	}
722 723
}

724 725 726 727 728
static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
	return index ? 0 : 100;
}

729 730 731 732 733 734 735 736 737 738
static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
	/*
	 * SKL doesn't need us to program the AUX clock divider (Hardware will
	 * derive the clock from CDCLK automatically). We still implement the
	 * get_aux_clock_divider vfunc to plug-in into the existing code.
	 */
	return index ? 0 : 1;
}

739 740 741 742 743 744 745 746 747 748 749 750 751 752
static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
				      bool has_aux_irq,
				      int send_bytes,
				      uint32_t aux_clock_divider)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	uint32_t precharge, timeout;

	if (IS_GEN6(dev))
		precharge = 3;
	else
		precharge = 5;

753
	if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A)
754 755 756 757 758
		timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
	else
		timeout = DP_AUX_CH_CTL_TIME_OUT_400us;

	return DP_AUX_CH_CTL_SEND_BUSY |
759
	       DP_AUX_CH_CTL_DONE |
760
	       (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
761
	       DP_AUX_CH_CTL_TIME_OUT_ERROR |
762
	       timeout |
763
	       DP_AUX_CH_CTL_RECEIVE_ERROR |
764 765
	       (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
	       (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
766
	       (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
767 768
}

769 770 771 772 773 774 775 776 777 778 779 780 781 782 783
static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
				      bool has_aux_irq,
				      int send_bytes,
				      uint32_t unused)
{
	return DP_AUX_CH_CTL_SEND_BUSY |
	       DP_AUX_CH_CTL_DONE |
	       (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
	       DP_AUX_CH_CTL_TIME_OUT_ERROR |
	       DP_AUX_CH_CTL_TIME_OUT_1600us |
	       DP_AUX_CH_CTL_RECEIVE_ERROR |
	       (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
	       DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
}

784 785
static int
intel_dp_aux_ch(struct intel_dp *intel_dp,
786
		const uint8_t *send, int send_bytes,
787 788 789 790 791 792
		uint8_t *recv, int recv_size)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
793
	uint32_t aux_clock_divider;
794 795
	int i, ret, recv_bytes;
	uint32_t status;
796
	int try, clock = 0;
797
	bool has_aux_irq = HAS_AUX_IRQ(dev);
798 799
	bool vdd;

800
	pps_lock(intel_dp);
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801

802 803 804 805 806 807
	/*
	 * We will be called with VDD already enabled for dpcd/edid/oui reads.
	 * In such cases we want to leave VDD enabled and it's up to upper layers
	 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
	 * ourselves.
	 */
808
	vdd = edp_panel_vdd_on(intel_dp);
809 810 811 812 813 814 815 816

	/* dp aux is extremely sensitive to irq latency, hence request the
	 * lowest possible wakeup latency and so prevent the cpu from going into
	 * deep sleep states.
	 */
	pm_qos_update_request(&dev_priv->pm_qos, 0);

	intel_dp_check_edp(intel_dp);
817

818 819
	/* Try to wait for any previous AUX channel activity */
	for (try = 0; try < 3; try++) {
820
		status = I915_READ_NOTRACE(ch_ctl);
821 822 823 824 825 826
		if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
			break;
		msleep(1);
	}

	if (try == 3) {
827 828 829 830 831 832 833 834 835
		static u32 last_status = -1;
		const u32 status = I915_READ(ch_ctl);

		if (status != last_status) {
			WARN(1, "dp_aux_ch not started status 0x%08x\n",
			     status);
			last_status = status;
		}

836 837
		ret = -EBUSY;
		goto out;
838 839
	}

840 841 842 843 844 845
	/* Only 5 data registers! */
	if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
		ret = -E2BIG;
		goto out;
	}

846
	while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
847 848 849 850
		u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
							  has_aux_irq,
							  send_bytes,
							  aux_clock_divider);
851

852 853 854 855
		/* Must try at least 3 times according to DP spec */
		for (try = 0; try < 5; try++) {
			/* Load the send data into the aux channel data registers */
			for (i = 0; i < send_bytes; i += 4)
856
				I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
857 858
					   intel_dp_pack_aux(send + i,
							     send_bytes - i));
859 860

			/* Send the command and wait for it to complete */
861
			I915_WRITE(ch_ctl, send_ctl);
862 863 864 865 866 867 868 869 870 871

			status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);

			/* Clear done status and any errors */
			I915_WRITE(ch_ctl,
				   status |
				   DP_AUX_CH_CTL_DONE |
				   DP_AUX_CH_CTL_TIME_OUT_ERROR |
				   DP_AUX_CH_CTL_RECEIVE_ERROR);

872
			if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
873
				continue;
874 875 876 877 878 879 880 881

			/* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
			 *   400us delay required for errors and timeouts
			 *   Timeout errors from the HW already meet this
			 *   requirement so skip to next iteration
			 */
			if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
				usleep_range(400, 500);
882
				continue;
883
			}
884
			if (status & DP_AUX_CH_CTL_DONE)
885
				goto done;
886
		}
887 888 889
	}

	if ((status & DP_AUX_CH_CTL_DONE) == 0) {
890
		DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
891 892
		ret = -EBUSY;
		goto out;
893 894
	}

895
done:
896 897 898
	/* Check for timeout or receive error.
	 * Timeouts occur when the sink is not connected
	 */
899
	if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
900
		DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
901 902
		ret = -EIO;
		goto out;
903
	}
904 905 906

	/* Timeouts occur when the device isn't connected, so they're
	 * "normal" -- don't fill the kernel log with these */
907
	if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
908
		DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
909 910
		ret = -ETIMEDOUT;
		goto out;
911 912 913 914 915 916 917
	}

	/* Unload any bytes sent back from the other side */
	recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
		      DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
	if (recv_bytes > recv_size)
		recv_bytes = recv_size;
918

919
	for (i = 0; i < recv_bytes; i += 4)
920
		intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
921
				    recv + i, recv_bytes - i);
922

923 924 925 926
	ret = recv_bytes;
out:
	pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);

927 928 929
	if (vdd)
		edp_panel_vdd_off(intel_dp, false);

930
	pps_unlock(intel_dp);
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931

932
	return ret;
933 934
}

935 936
#define BARE_ADDRESS_SIZE	3
#define HEADER_SIZE		(BARE_ADDRESS_SIZE + 1)
937 938
static ssize_t
intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
939
{
940 941 942
	struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
	uint8_t txbuf[20], rxbuf[20];
	size_t txsize, rxsize;
943 944
	int ret;

945 946 947
	txbuf[0] = (msg->request << 4) |
		((msg->address >> 16) & 0xf);
	txbuf[1] = (msg->address >> 8) & 0xff;
948 949
	txbuf[2] = msg->address & 0xff;
	txbuf[3] = msg->size - 1;
950

951 952 953
	switch (msg->request & ~DP_AUX_I2C_MOT) {
	case DP_AUX_NATIVE_WRITE:
	case DP_AUX_I2C_WRITE:
954
	case DP_AUX_I2C_WRITE_STATUS_UPDATE:
955
		txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
956
		rxsize = 2; /* 0 or 1 data bytes */
957

958 959
		if (WARN_ON(txsize > 20))
			return -E2BIG;
960

961
		memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
962

963 964 965
		ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
		if (ret > 0) {
			msg->reply = rxbuf[0] >> 4;
966

967 968 969 970 971 972 973
			if (ret > 1) {
				/* Number of bytes written in a short write. */
				ret = clamp_t(int, rxbuf[1], 0, msg->size);
			} else {
				/* Return payload size. */
				ret = msg->size;
			}
974 975
		}
		break;
976

977 978
	case DP_AUX_NATIVE_READ:
	case DP_AUX_I2C_READ:
979
		txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
980
		rxsize = msg->size + 1;
981

982 983
		if (WARN_ON(rxsize > 20))
			return -E2BIG;
984

985 986 987 988 989 990 991 992 993 994 995
		ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
		if (ret > 0) {
			msg->reply = rxbuf[0] >> 4;
			/*
			 * Assume happy day, and copy the data. The caller is
			 * expected to check msg->reply before touching it.
			 *
			 * Return payload size.
			 */
			ret--;
			memcpy(msg->buffer, rxbuf + 1, ret);
996
		}
997 998 999 1000 1001
		break;

	default:
		ret = -EINVAL;
		break;
1002
	}
1003

1004
	return ret;
1005 1006
}

1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020
static uint32_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
				enum port port)
{
	switch (port) {
	case PORT_B:
	case PORT_C:
	case PORT_D:
		return DP_AUX_CH_CTL(port);
	default:
		MISSING_CASE(port);
		return DP_AUX_CH_CTL(PORT_B);
	}
}

1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034
static uint32_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
				 enum port port, int index)
{
	switch (port) {
	case PORT_B:
	case PORT_C:
	case PORT_D:
		return DP_AUX_CH_DATA(port, index);
	default:
		MISSING_CASE(port);
		return DP_AUX_CH_DATA(PORT_B, index);
	}
}

1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050
static uint32_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
				enum port port)
{
	switch (port) {
	case PORT_A:
		return DP_AUX_CH_CTL(port);
	case PORT_B:
	case PORT_C:
	case PORT_D:
		return PCH_DP_AUX_CH_CTL(port);
	default:
		MISSING_CASE(port);
		return DP_AUX_CH_CTL(PORT_A);
	}
}

1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066
static uint32_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
				 enum port port, int index)
{
	switch (port) {
	case PORT_A:
		return DP_AUX_CH_DATA(port, index);
	case PORT_B:
	case PORT_C:
	case PORT_D:
		return PCH_DP_AUX_CH_DATA(port, index);
	default:
		MISSING_CASE(port);
		return DP_AUX_CH_DATA(PORT_A, index);
	}
}

1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108
/*
 * On SKL we don't have Aux for port E so we rely
 * on VBT to set a proper alternate aux channel.
 */
static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
{
	const struct ddi_vbt_port_info *info =
		&dev_priv->vbt.ddi_port_info[PORT_E];

	switch (info->alternate_aux_channel) {
	case DP_AUX_A:
		return PORT_A;
	case DP_AUX_B:
		return PORT_B;
	case DP_AUX_C:
		return PORT_C;
	case DP_AUX_D:
		return PORT_D;
	default:
		MISSING_CASE(info->alternate_aux_channel);
		return PORT_A;
	}
}

static uint32_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
				enum port port)
{
	if (port == PORT_E)
		port = skl_porte_aux_port(dev_priv);

	switch (port) {
	case PORT_A:
	case PORT_B:
	case PORT_C:
	case PORT_D:
		return DP_AUX_CH_CTL(port);
	default:
		MISSING_CASE(port);
		return DP_AUX_CH_CTL(PORT_A);
	}
}

1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159
static uint32_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
				 enum port port, int index)
{
	if (port == PORT_E)
		port = skl_porte_aux_port(dev_priv);

	switch (port) {
	case PORT_A:
	case PORT_B:
	case PORT_C:
	case PORT_D:
		return DP_AUX_CH_DATA(port, index);
	default:
		MISSING_CASE(port);
		return DP_AUX_CH_DATA(PORT_A, index);
	}
}

static uint32_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
				  enum port port)
{
	if (INTEL_INFO(dev_priv)->gen >= 9)
		return skl_aux_ctl_reg(dev_priv, port);
	else if (HAS_PCH_SPLIT(dev_priv))
		return ilk_aux_ctl_reg(dev_priv, port);
	else
		return g4x_aux_ctl_reg(dev_priv, port);
}

static uint32_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
				   enum port port, int index)
{
	if (INTEL_INFO(dev_priv)->gen >= 9)
		return skl_aux_data_reg(dev_priv, port, index);
	else if (HAS_PCH_SPLIT(dev_priv))
		return ilk_aux_data_reg(dev_priv, port, index);
	else
		return g4x_aux_data_reg(dev_priv, port, index);
}

static void intel_aux_reg_init(struct intel_dp *intel_dp)
{
	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
	enum port port = dp_to_dig_port(intel_dp)->port;
	int i;

	intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
	for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
		intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
}

1160
static void
1161 1162 1163 1164 1165 1166 1167
intel_dp_aux_fini(struct intel_dp *intel_dp)
{
	drm_dp_aux_unregister(&intel_dp->aux);
	kfree(intel_dp->aux.name);
}

static int
1168 1169 1170
intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1171 1172
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	enum port port = intel_dig_port->port;
1173 1174
	int ret;

1175
	intel_aux_reg_init(intel_dp);
1176

1177 1178 1179 1180
	intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
	if (!intel_dp->aux.name)
		return -ENOMEM;

1181 1182
	intel_dp->aux.dev = dev->dev;
	intel_dp->aux.transfer = intel_dp_aux_transfer;
1183

1184 1185
	DRM_DEBUG_KMS("registering %s bus for %s\n",
		      intel_dp->aux.name,
1186
		      connector->base.kdev->kobj.name);
1187

1188
	ret = drm_dp_aux_register(&intel_dp->aux);
1189
	if (ret < 0) {
1190
		DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1191 1192 1193
			  intel_dp->aux.name, ret);
		kfree(intel_dp->aux.name);
		return ret;
1194
	}
1195

1196 1197 1198 1199
	ret = sysfs_create_link(&connector->base.kdev->kobj,
				&intel_dp->aux.ddc.dev.kobj,
				intel_dp->aux.ddc.dev.kobj.name);
	if (ret < 0) {
1200 1201 1202 1203
		DRM_ERROR("sysfs_create_link() for %s failed (%d)\n",
			  intel_dp->aux.name, ret);
		intel_dp_aux_fini(intel_dp);
		return ret;
1204
	}
1205 1206

	return 0;
1207 1208
}

1209 1210 1211 1212 1213
static void
intel_dp_connector_unregister(struct intel_connector *intel_connector)
{
	struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);

1214 1215 1216
	if (!intel_connector->mst_port)
		sysfs_remove_link(&intel_connector->base.kdev->kobj,
				  intel_dp->aux.ddc.dev.kobj.name);
1217 1218 1219
	intel_connector_unregister(intel_connector);
}

1220
static void
1221
skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
1222 1223 1224
{
	u32 ctrl1;

1225 1226 1227
	memset(&pipe_config->dpll_hw_state, 0,
	       sizeof(pipe_config->dpll_hw_state));

1228 1229 1230 1231 1232
	pipe_config->ddi_pll_sel = SKL_DPLL0;
	pipe_config->dpll_hw_state.cfgcr1 = 0;
	pipe_config->dpll_hw_state.cfgcr2 = 0;

	ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
1233
	switch (pipe_config->port_clock / 2) {
1234
	case 81000:
1235
		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
1236 1237
					      SKL_DPLL0);
		break;
1238
	case 135000:
1239
		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350,
1240 1241
					      SKL_DPLL0);
		break;
1242
	case 270000:
1243
		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700,
1244 1245
					      SKL_DPLL0);
		break;
1246
	case 162000:
1247
		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620,
1248 1249 1250 1251 1252 1253
					      SKL_DPLL0);
		break;
	/* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
	results in CDCLK change. Need to handle the change of CDCLK by
	disabling pipes and re-enabling them */
	case 108000:
1254
		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
1255 1256 1257
					      SKL_DPLL0);
		break;
	case 216000:
1258
		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
1259 1260 1261
					      SKL_DPLL0);
		break;

1262 1263 1264 1265
	}
	pipe_config->dpll_hw_state.ctrl1 = ctrl1;
}

1266
void
1267
hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config)
1268
{
1269 1270 1271
	memset(&pipe_config->dpll_hw_state, 0,
	       sizeof(pipe_config->dpll_hw_state));

1272 1273
	switch (pipe_config->port_clock / 2) {
	case 81000:
1274 1275
		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
		break;
1276
	case 135000:
1277 1278
		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
		break;
1279
	case 270000:
1280 1281 1282 1283 1284
		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
		break;
	}
}

1285
static int
1286
intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
1287
{
1288 1289 1290
	if (intel_dp->num_sink_rates) {
		*sink_rates = intel_dp->sink_rates;
		return intel_dp->num_sink_rates;
1291
	}
1292 1293 1294 1295

	*sink_rates = default_rates;

	return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
1296 1297
}

1298
bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1299
{
1300 1301 1302
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;

1303
	/* WaDisableHBR2:skl */
1304
	if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
1305 1306 1307 1308 1309 1310 1311 1312 1313
		return false;

	if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
	    (INTEL_INFO(dev)->gen >= 9))
		return true;
	else
		return false;
}

1314
static int
1315
intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
1316
{
1317 1318
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
1319 1320
	int size;

1321 1322
	if (IS_BROXTON(dev)) {
		*source_rates = bxt_rates;
1323
		size = ARRAY_SIZE(bxt_rates);
1324
	} else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1325
		*source_rates = skl_rates;
1326 1327 1328 1329
		size = ARRAY_SIZE(skl_rates);
	} else {
		*source_rates = default_rates;
		size = ARRAY_SIZE(default_rates);
1330
	}
1331

1332
	/* This depends on the fact that 5.4 is last value in the array */
1333
	if (!intel_dp_source_supports_hbr2(intel_dp))
1334
		size--;
1335

1336
	return size;
1337 1338
}

1339 1340
static void
intel_dp_set_clock(struct intel_encoder *encoder,
1341
		   struct intel_crtc_state *pipe_config)
1342 1343
{
	struct drm_device *dev = encoder->base.dev;
1344 1345
	const struct dp_link_dpll *divisor = NULL;
	int i, count = 0;
1346 1347

	if (IS_G4X(dev)) {
1348 1349
		divisor = gen4_dpll;
		count = ARRAY_SIZE(gen4_dpll);
1350
	} else if (HAS_PCH_SPLIT(dev)) {
1351 1352
		divisor = pch_dpll;
		count = ARRAY_SIZE(pch_dpll);
1353 1354 1355
	} else if (IS_CHERRYVIEW(dev)) {
		divisor = chv_dpll;
		count = ARRAY_SIZE(chv_dpll);
1356
	} else if (IS_VALLEYVIEW(dev)) {
1357 1358
		divisor = vlv_dpll;
		count = ARRAY_SIZE(vlv_dpll);
1359
	}
1360 1361 1362

	if (divisor && count) {
		for (i = 0; i < count; i++) {
1363
			if (pipe_config->port_clock == divisor[i].clock) {
1364 1365 1366 1367 1368
				pipe_config->dpll = divisor[i].dpll;
				pipe_config->clock_set = true;
				break;
			}
		}
1369 1370 1371
	}
}

1372 1373
static int intersect_rates(const int *source_rates, int source_len,
			   const int *sink_rates, int sink_len,
1374
			   int *common_rates)
1375 1376 1377 1378 1379
{
	int i = 0, j = 0, k = 0;

	while (i < source_len && j < sink_len) {
		if (source_rates[i] == sink_rates[j]) {
1380 1381
			if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
				return k;
1382
			common_rates[k] = source_rates[i];
1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394
			++k;
			++i;
			++j;
		} else if (source_rates[i] < sink_rates[j]) {
			++i;
		} else {
			++j;
		}
	}
	return k;
}

1395 1396
static int intel_dp_common_rates(struct intel_dp *intel_dp,
				 int *common_rates)
1397 1398 1399 1400 1401
{
	const int *source_rates, *sink_rates;
	int source_len, sink_len;

	sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1402
	source_len = intel_dp_source_rates(intel_dp, &source_rates);
1403 1404 1405

	return intersect_rates(source_rates, source_len,
			       sink_rates, sink_len,
1406
			       common_rates);
1407 1408
}

1409 1410 1411 1412 1413 1414 1415 1416
static void snprintf_int_array(char *str, size_t len,
			       const int *array, int nelem)
{
	int i;

	str[0] = '\0';

	for (i = 0; i < nelem; i++) {
1417
		int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1418 1419 1420 1421 1422 1423 1424 1425 1426 1427
		if (r >= len)
			return;
		str += r;
		len -= r;
	}
}

static void intel_dp_print_rates(struct intel_dp *intel_dp)
{
	const int *source_rates, *sink_rates;
1428 1429
	int source_len, sink_len, common_len;
	int common_rates[DP_MAX_SUPPORTED_RATES];
1430 1431 1432 1433 1434
	char str[128]; /* FIXME: too big for stack? */

	if ((drm_debug & DRM_UT_KMS) == 0)
		return;

1435
	source_len = intel_dp_source_rates(intel_dp, &source_rates);
1436 1437 1438 1439 1440 1441 1442
	snprintf_int_array(str, sizeof(str), source_rates, source_len);
	DRM_DEBUG_KMS("source rates: %s\n", str);

	sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
	snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
	DRM_DEBUG_KMS("sink rates: %s\n", str);

1443 1444 1445
	common_len = intel_dp_common_rates(intel_dp, common_rates);
	snprintf_int_array(str, sizeof(str), common_rates, common_len);
	DRM_DEBUG_KMS("common rates: %s\n", str);
1446 1447
}

1448
static int rate_to_index(int find, const int *rates)
1449 1450 1451 1452 1453 1454 1455 1456 1457 1458
{
	int i = 0;

	for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
		if (find == rates[i])
			break;

	return i;
}

1459 1460 1461 1462 1463 1464
int
intel_dp_max_link_rate(struct intel_dp *intel_dp)
{
	int rates[DP_MAX_SUPPORTED_RATES] = {};
	int len;

1465
	len = intel_dp_common_rates(intel_dp, rates);
1466 1467 1468 1469 1470 1471
	if (WARN_ON(len <= 0))
		return 162000;

	return rates[rate_to_index(0, rates) - 1];
}

1472 1473
int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
{
1474
	return rate_to_index(rate, intel_dp->sink_rates);
1475 1476
}

1477 1478
void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
			   uint8_t *link_bw, uint8_t *rate_select)
1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489
{
	if (intel_dp->num_sink_rates) {
		*link_bw = 0;
		*rate_select =
			intel_dp_rate_select(intel_dp, port_clock);
	} else {
		*link_bw = drm_dp_link_rate_to_bw_code(port_clock);
		*rate_select = 0;
	}
}

P
Paulo Zanoni 已提交
1490
bool
1491
intel_dp_compute_config(struct intel_encoder *encoder,
1492
			struct intel_crtc_state *pipe_config)
1493
{
1494
	struct drm_device *dev = encoder->base.dev;
1495
	struct drm_i915_private *dev_priv = dev->dev_private;
1496
	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1497
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1498
	enum port port = dp_to_dig_port(intel_dp)->port;
1499
	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1500
	struct intel_connector *intel_connector = intel_dp->attached_connector;
1501
	int lane_count, clock;
1502
	int min_lane_count = 1;
1503
	int max_lane_count = intel_dp_max_lane_count(intel_dp);
1504
	/* Conveniently, the link BW constants become indices with a shift...*/
1505
	int min_clock = 0;
1506
	int max_clock;
1507
	int bpp, mode_rate;
1508
	int link_avail, link_clock;
1509 1510
	int common_rates[DP_MAX_SUPPORTED_RATES] = {};
	int common_len;
1511
	uint8_t link_bw, rate_select;
1512

1513
	common_len = intel_dp_common_rates(intel_dp, common_rates);
1514 1515

	/* No common link rates between source and sink */
1516
	WARN_ON(common_len <= 0);
1517

1518
	max_clock = common_len - 1;
1519

1520
	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
1521 1522
		pipe_config->has_pch_encoder = true;

1523
	pipe_config->has_dp_encoder = true;
1524
	pipe_config->has_drrs = false;
1525
	pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
1526

1527 1528 1529
	if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
		intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
				       adjusted_mode);
1530 1531 1532

		if (INTEL_INFO(dev)->gen >= 9) {
			int ret;
1533
			ret = skl_update_scaler_crtc(pipe_config);
1534 1535 1536 1537
			if (ret)
				return ret;
		}

1538
		if (HAS_GMCH_DISPLAY(dev))
1539 1540 1541
			intel_gmch_panel_fitting(intel_crtc, pipe_config,
						 intel_connector->panel.fitting_mode);
		else
1542 1543
			intel_pch_panel_fitting(intel_crtc, pipe_config,
						intel_connector->panel.fitting_mode);
1544 1545
	}

1546
	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1547 1548
		return false;

1549
	DRM_DEBUG_KMS("DP link computation with max lane count %i "
1550
		      "max bw %d pixel clock %iKHz\n",
1551
		      max_lane_count, common_rates[max_clock],
1552
		      adjusted_mode->crtc_clock);
1553

1554 1555
	/* Walk through all bpp values. Luckily they're all nicely spaced with 2
	 * bpc in between. */
1556
	bpp = pipe_config->pipe_bpp;
1557
	if (is_edp(intel_dp)) {
1558 1559 1560 1561

		/* Get bpp from vbt only for panels that dont have bpp in edid */
		if (intel_connector->base.display_info.bpc == 0 &&
			(dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp)) {
1562 1563 1564 1565 1566
			DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
				      dev_priv->vbt.edp_bpp);
			bpp = dev_priv->vbt.edp_bpp;
		}

1567 1568 1569 1570 1571 1572 1573 1574 1575
		/*
		 * Use the maximum clock and number of lanes the eDP panel
		 * advertizes being capable of. The panels are generally
		 * designed to support only a single clock and lane
		 * configuration, and typically these values correspond to the
		 * native resolution of the panel.
		 */
		min_lane_count = max_lane_count;
		min_clock = max_clock;
1576
	}
1577

1578
	for (; bpp >= 6*3; bpp -= 2*3) {
1579 1580
		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
						   bpp);
1581

1582
		for (clock = min_clock; clock <= max_clock; clock++) {
1583 1584 1585 1586
			for (lane_count = min_lane_count;
				lane_count <= max_lane_count;
				lane_count <<= 1) {

1587
				link_clock = common_rates[clock];
1588 1589 1590 1591 1592 1593 1594 1595 1596
				link_avail = intel_dp_max_data_rate(link_clock,
								    lane_count);

				if (mode_rate <= link_avail) {
					goto found;
				}
			}
		}
	}
1597

1598
	return false;
1599

1600
found:
1601 1602 1603 1604 1605 1606
	if (intel_dp->color_range_auto) {
		/*
		 * See:
		 * CEA-861-E - 5.1 Default Encoding Parameters
		 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
		 */
1607 1608 1609 1610 1611
		pipe_config->limited_color_range =
			bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
	} else {
		pipe_config->limited_color_range =
			intel_dp->limited_color_range;
1612 1613
	}

1614
	pipe_config->lane_count = lane_count;
1615

1616
	pipe_config->pipe_bpp = bpp;
1617
	pipe_config->port_clock = common_rates[clock];
1618

1619 1620 1621 1622 1623
	intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
			      &link_bw, &rate_select);

	DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
		      link_bw, rate_select, pipe_config->lane_count,
1624
		      pipe_config->port_clock, bpp);
1625 1626
	DRM_DEBUG_KMS("DP link bw required %i available %i\n",
		      mode_rate, link_avail);
1627

1628
	intel_link_compute_m_n(bpp, lane_count,
1629 1630
			       adjusted_mode->crtc_clock,
			       pipe_config->port_clock,
1631
			       &pipe_config->dp_m_n);
1632

1633
	if (intel_connector->panel.downclock_mode != NULL &&
1634
		dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1635
			pipe_config->has_drrs = true;
1636 1637 1638 1639 1640 1641
			intel_link_compute_m_n(bpp, lane_count,
				intel_connector->panel.downclock_mode->clock,
				pipe_config->port_clock,
				&pipe_config->dp_m2_n2);
	}

1642
	if ((IS_SKYLAKE(dev)  || IS_KABYLAKE(dev)) && is_edp(intel_dp))
1643
		skl_edp_set_pll_config(pipe_config);
1644 1645
	else if (IS_BROXTON(dev))
		/* handled in ddi */;
1646
	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1647
		hsw_dp_set_ddi_pll_sel(pipe_config);
1648
	else
1649
		intel_dp_set_clock(encoder, pipe_config);
1650

1651
	return true;
1652 1653
}

1654 1655 1656 1657 1658 1659 1660
void intel_dp_set_link_params(struct intel_dp *intel_dp,
			      const struct intel_crtc_state *pipe_config)
{
	intel_dp->link_rate = pipe_config->port_clock;
	intel_dp->lane_count = pipe_config->lane_count;
}

1661
static void intel_dp_prepare(struct intel_encoder *encoder)
1662
{
1663
	struct drm_device *dev = encoder->base.dev;
1664
	struct drm_i915_private *dev_priv = dev->dev_private;
1665
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1666
	enum port port = dp_to_dig_port(intel_dp)->port;
1667
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1668
	const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
1669

1670 1671
	intel_dp_set_link_params(intel_dp, crtc->config);

1672
	/*
K
Keith Packard 已提交
1673
	 * There are four kinds of DP registers:
1674 1675
	 *
	 * 	IBX PCH
K
Keith Packard 已提交
1676 1677
	 * 	SNB CPU
	 *	IVB CPU
1678 1679 1680 1681 1682 1683 1684 1685 1686 1687
	 * 	CPT PCH
	 *
	 * IBX PCH and CPU are the same for almost everything,
	 * except that the CPU DP PLL is configured in this
	 * register
	 *
	 * CPT PCH is quite different, having many bits moved
	 * to the TRANS_DP_CTL register instead. That
	 * configuration happens (oddly) in ironlake_pch_enable
	 */
1688

1689 1690 1691 1692
	/* Preserve the BIOS-computed detected bit. This is
	 * supposed to be read-only.
	 */
	intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1693

1694 1695
	/* Handle DP bits in common between all three register formats */
	intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1696
	intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count);
1697

1698
	/* Split out the IBX/CPU vs CPT settings */
1699

1700
	if (IS_GEN7(dev) && port == PORT_A) {
K
Keith Packard 已提交
1701 1702 1703 1704 1705 1706
		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
			intel_dp->DP |= DP_SYNC_HS_HIGH;
		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
			intel_dp->DP |= DP_SYNC_VS_HIGH;
		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;

1707
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
K
Keith Packard 已提交
1708 1709
			intel_dp->DP |= DP_ENHANCED_FRAMING;

1710
		intel_dp->DP |= crtc->pipe << 29;
1711
	} else if (HAS_PCH_CPT(dev) && port != PORT_A) {
1712 1713
		u32 trans_dp;

1714
		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1715 1716 1717 1718 1719 1720 1721

		trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
			trans_dp |= TRANS_DP_ENH_FRAMING;
		else
			trans_dp &= ~TRANS_DP_ENH_FRAMING;
		I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1722
	} else {
1723 1724 1725
		if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
		    crtc->config->limited_color_range)
			intel_dp->DP |= DP_COLOR_RANGE_16_235;
1726 1727 1728 1729 1730 1731 1732

		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
			intel_dp->DP |= DP_SYNC_HS_HIGH;
		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
			intel_dp->DP |= DP_SYNC_VS_HIGH;
		intel_dp->DP |= DP_LINK_TRAIN_OFF;

1733
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1734 1735
			intel_dp->DP |= DP_ENHANCED_FRAMING;

1736
		if (IS_CHERRYVIEW(dev))
1737
			intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1738 1739
		else if (crtc->pipe == PIPE_B)
			intel_dp->DP |= DP_PIPEB_SELECT;
1740
	}
1741 1742
}

1743 1744
#define IDLE_ON_MASK		(PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
#define IDLE_ON_VALUE   	(PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1745

1746 1747
#define IDLE_OFF_MASK		(PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
#define IDLE_OFF_VALUE		(0     | PP_SEQUENCE_NONE | 0                     | 0)
1748

1749 1750
#define IDLE_CYCLE_MASK		(PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
#define IDLE_CYCLE_VALUE	(0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1751

1752
static void wait_panel_status(struct intel_dp *intel_dp,
1753 1754
				       u32 mask,
				       u32 value)
1755
{
1756
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1757
	struct drm_i915_private *dev_priv = dev->dev_private;
1758 1759
	u32 pp_stat_reg, pp_ctrl_reg;

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1760 1761
	lockdep_assert_held(&dev_priv->pps_mutex);

1762 1763
	pp_stat_reg = _pp_stat_reg(intel_dp);
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1764

1765
	DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1766 1767 1768
			mask, value,
			I915_READ(pp_stat_reg),
			I915_READ(pp_ctrl_reg));
1769

1770
	if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1771
		DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1772 1773
				I915_READ(pp_stat_reg),
				I915_READ(pp_ctrl_reg));
1774
	}
1775 1776

	DRM_DEBUG_KMS("Wait complete\n");
1777
}
1778

1779
static void wait_panel_on(struct intel_dp *intel_dp)
1780 1781
{
	DRM_DEBUG_KMS("Wait for panel power on\n");
1782
	wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1783 1784
}

1785
static void wait_panel_off(struct intel_dp *intel_dp)
1786 1787
{
	DRM_DEBUG_KMS("Wait for panel power off time\n");
1788
	wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1789 1790
}

1791
static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1792 1793
{
	DRM_DEBUG_KMS("Wait for panel power cycle\n");
1794 1795 1796 1797 1798 1799

	/* When we disable the VDD override bit last we have to do the manual
	 * wait. */
	wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
				       intel_dp->panel_power_cycle_delay);

1800
	wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1801 1802
}

1803
static void wait_backlight_on(struct intel_dp *intel_dp)
1804 1805 1806 1807 1808
{
	wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
				       intel_dp->backlight_on_delay);
}

1809
static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1810 1811 1812 1813
{
	wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
				       intel_dp->backlight_off_delay);
}
1814

1815 1816 1817 1818
/* Read the current pp_control value, unlocking the register if it
 * is locked
 */

1819
static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1820
{
1821 1822 1823
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 control;
1824

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1825 1826
	lockdep_assert_held(&dev_priv->pps_mutex);

1827
	control = I915_READ(_pp_ctrl_reg(intel_dp));
1828 1829 1830 1831
	if (!IS_BROXTON(dev)) {
		control &= ~PANEL_UNLOCK_MASK;
		control |= PANEL_UNLOCK_REGS;
	}
1832
	return control;
1833 1834
}

1835 1836 1837 1838 1839
/*
 * Must be paired with edp_panel_vdd_off().
 * Must hold pps_mutex around the whole on/off sequence.
 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
 */
1840
static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1841
{
1842
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1843 1844
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
1845
	struct drm_i915_private *dev_priv = dev->dev_private;
1846
	enum intel_display_power_domain power_domain;
1847
	u32 pp;
1848
	u32 pp_stat_reg, pp_ctrl_reg;
1849
	bool need_to_disable = !intel_dp->want_panel_vdd;
1850

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1851 1852
	lockdep_assert_held(&dev_priv->pps_mutex);

1853
	if (!is_edp(intel_dp))
1854
		return false;
1855

1856
	cancel_delayed_work(&intel_dp->panel_vdd_work);
1857
	intel_dp->want_panel_vdd = true;
1858

1859
	if (edp_have_panel_vdd(intel_dp))
1860
		return need_to_disable;
1861

1862
	power_domain = intel_display_port_aux_power_domain(intel_encoder);
1863
	intel_display_power_get(dev_priv, power_domain);
1864

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1865 1866
	DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
		      port_name(intel_dig_port->port));
1867

1868 1869
	if (!edp_have_panel_power(intel_dp))
		wait_panel_power_cycle(intel_dp);
1870

1871
	pp = ironlake_get_pp_control(intel_dp);
1872
	pp |= EDP_FORCE_VDD;
1873

1874 1875
	pp_stat_reg = _pp_stat_reg(intel_dp);
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1876 1877 1878 1879 1880

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
	DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
			I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1881 1882 1883
	/*
	 * If the panel wasn't on, delay before accessing aux channel
	 */
1884
	if (!edp_have_panel_power(intel_dp)) {
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1885 1886
		DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
			      port_name(intel_dig_port->port));
1887 1888
		msleep(intel_dp->panel_power_up_delay);
	}
1889 1890 1891 1892

	return need_to_disable;
}

1893 1894 1895 1896 1897 1898 1899
/*
 * Must be paired with intel_edp_panel_vdd_off() or
 * intel_edp_panel_off().
 * Nested calls to these functions are not allowed since
 * we drop the lock. Caller must use some higher level
 * locking to prevent nested calls from other threads.
 */
1900
void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1901
{
1902
	bool vdd;
1903

1904 1905 1906
	if (!is_edp(intel_dp))
		return;

1907
	pps_lock(intel_dp);
1908
	vdd = edp_panel_vdd_on(intel_dp);
1909
	pps_unlock(intel_dp);
1910

R
Rob Clark 已提交
1911
	I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
V
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1912
	     port_name(dp_to_dig_port(intel_dp)->port));
1913 1914
}

1915
static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1916
{
1917
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1918
	struct drm_i915_private *dev_priv = dev->dev_private;
1919 1920 1921 1922
	struct intel_digital_port *intel_dig_port =
		dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	enum intel_display_power_domain power_domain;
1923
	u32 pp;
1924
	u32 pp_stat_reg, pp_ctrl_reg;
1925

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1926
	lockdep_assert_held(&dev_priv->pps_mutex);
1927

1928
	WARN_ON(intel_dp->want_panel_vdd);
1929

1930
	if (!edp_have_panel_vdd(intel_dp))
1931
		return;
1932

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1933 1934
	DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
		      port_name(intel_dig_port->port));
1935

1936 1937
	pp = ironlake_get_pp_control(intel_dp);
	pp &= ~EDP_FORCE_VDD;
1938

1939 1940
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
	pp_stat_reg = _pp_stat_reg(intel_dp);
1941

1942 1943
	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
P
Paulo Zanoni 已提交
1944

1945 1946 1947
	/* Make sure sequencer is idle before allowing subsequent activity */
	DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
	I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1948

1949 1950
	if ((pp & POWER_TARGET_ON) == 0)
		intel_dp->last_power_cycle = jiffies;
1951

1952
	power_domain = intel_display_port_aux_power_domain(intel_encoder);
1953
	intel_display_power_put(dev_priv, power_domain);
1954
}
1955

1956
static void edp_panel_vdd_work(struct work_struct *__work)
1957 1958 1959 1960
{
	struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
						 struct intel_dp, panel_vdd_work);

1961
	pps_lock(intel_dp);
1962 1963
	if (!intel_dp->want_panel_vdd)
		edp_panel_vdd_off_sync(intel_dp);
1964
	pps_unlock(intel_dp);
1965 1966
}

1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979
static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
{
	unsigned long delay;

	/*
	 * Queue the timer to fire a long time from now (relative to the power
	 * down delay) to keep the panel power up across a sequence of
	 * operations.
	 */
	delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
	schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
}

1980 1981 1982 1983 1984
/*
 * Must be paired with edp_panel_vdd_on().
 * Must hold pps_mutex around the whole on/off sequence.
 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
 */
1985
static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1986
{
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1987 1988 1989 1990 1991
	struct drm_i915_private *dev_priv =
		intel_dp_to_dev(intel_dp)->dev_private;

	lockdep_assert_held(&dev_priv->pps_mutex);

1992 1993
	if (!is_edp(intel_dp))
		return;
1994

R
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1995
	I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
V
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1996
	     port_name(dp_to_dig_port(intel_dp)->port));
1997

1998 1999
	intel_dp->want_panel_vdd = false;

2000
	if (sync)
2001
		edp_panel_vdd_off_sync(intel_dp);
2002 2003
	else
		edp_panel_vdd_schedule_off(intel_dp);
2004 2005
}

2006
static void edp_panel_on(struct intel_dp *intel_dp)
2007
{
2008
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2009
	struct drm_i915_private *dev_priv = dev->dev_private;
2010
	u32 pp;
2011
	u32 pp_ctrl_reg;
2012

2013 2014
	lockdep_assert_held(&dev_priv->pps_mutex);

2015
	if (!is_edp(intel_dp))
2016
		return;
2017

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2018 2019
	DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
		      port_name(dp_to_dig_port(intel_dp)->port));
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2020

2021 2022 2023
	if (WARN(edp_have_panel_power(intel_dp),
		 "eDP port %c panel power already on\n",
		 port_name(dp_to_dig_port(intel_dp)->port)))
2024
		return;
2025

2026
	wait_panel_power_cycle(intel_dp);
2027

2028
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2029
	pp = ironlake_get_pp_control(intel_dp);
2030 2031 2032
	if (IS_GEN5(dev)) {
		/* ILK workaround: disable reset around power sequence */
		pp &= ~PANEL_POWER_RESET;
2033 2034
		I915_WRITE(pp_ctrl_reg, pp);
		POSTING_READ(pp_ctrl_reg);
2035
	}
2036

2037
	pp |= POWER_TARGET_ON;
2038 2039 2040
	if (!IS_GEN5(dev))
		pp |= PANEL_POWER_RESET;

2041 2042
	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
2043

2044
	wait_panel_on(intel_dp);
2045
	intel_dp->last_power_on = jiffies;
2046

2047 2048
	if (IS_GEN5(dev)) {
		pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2049 2050
		I915_WRITE(pp_ctrl_reg, pp);
		POSTING_READ(pp_ctrl_reg);
2051
	}
2052
}
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2053

2054 2055 2056 2057 2058 2059 2060
void intel_edp_panel_on(struct intel_dp *intel_dp)
{
	if (!is_edp(intel_dp))
		return;

	pps_lock(intel_dp);
	edp_panel_on(intel_dp);
2061
	pps_unlock(intel_dp);
2062 2063
}

2064 2065

static void edp_panel_off(struct intel_dp *intel_dp)
2066
{
2067 2068
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
2069
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2070
	struct drm_i915_private *dev_priv = dev->dev_private;
2071
	enum intel_display_power_domain power_domain;
2072
	u32 pp;
2073
	u32 pp_ctrl_reg;
2074

2075 2076
	lockdep_assert_held(&dev_priv->pps_mutex);

2077 2078
	if (!is_edp(intel_dp))
		return;
2079

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2080 2081
	DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
		      port_name(dp_to_dig_port(intel_dp)->port));
2082

V
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2083 2084
	WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
	     port_name(dp_to_dig_port(intel_dp)->port));
2085

2086
	pp = ironlake_get_pp_control(intel_dp);
2087 2088
	/* We need to switch off panel power _and_ force vdd, for otherwise some
	 * panels get very unhappy and cease to work. */
2089 2090
	pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
		EDP_BLC_ENABLE);
2091

2092
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2093

2094 2095
	intel_dp->want_panel_vdd = false;

2096 2097
	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
2098

2099
	intel_dp->last_power_cycle = jiffies;
2100
	wait_panel_off(intel_dp);
2101 2102

	/* We got a reference when we enabled the VDD. */
2103
	power_domain = intel_display_port_aux_power_domain(intel_encoder);
2104
	intel_display_power_put(dev_priv, power_domain);
2105
}
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2106

2107 2108 2109 2110
void intel_edp_panel_off(struct intel_dp *intel_dp)
{
	if (!is_edp(intel_dp))
		return;
V
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2111

2112 2113
	pps_lock(intel_dp);
	edp_panel_off(intel_dp);
2114
	pps_unlock(intel_dp);
2115 2116
}

2117 2118
/* Enable backlight in the panel power control. */
static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2119
{
2120 2121
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
2122 2123
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
2124
	u32 pp_ctrl_reg;
2125

2126 2127 2128 2129 2130 2131
	/*
	 * If we enable the backlight right away following a panel power
	 * on, we may see slight flicker as the panel syncs with the eDP
	 * link.  So delay a bit to make sure the image is solid before
	 * allowing it to appear.
	 */
2132
	wait_backlight_on(intel_dp);
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2133

2134
	pps_lock(intel_dp);
V
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2135

2136
	pp = ironlake_get_pp_control(intel_dp);
2137
	pp |= EDP_BLC_ENABLE;
2138

2139
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2140 2141 2142

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
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2143

2144
	pps_unlock(intel_dp);
2145 2146
}

2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160
/* Enable backlight PWM and backlight PP control. */
void intel_edp_backlight_on(struct intel_dp *intel_dp)
{
	if (!is_edp(intel_dp))
		return;

	DRM_DEBUG_KMS("\n");

	intel_panel_enable_backlight(intel_dp->attached_connector);
	_intel_edp_backlight_on(intel_dp);
}

/* Disable backlight in the panel power control. */
static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2161
{
2162
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2163 2164
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
2165
	u32 pp_ctrl_reg;
2166

2167 2168 2169
	if (!is_edp(intel_dp))
		return;

2170
	pps_lock(intel_dp);
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2171

2172
	pp = ironlake_get_pp_control(intel_dp);
2173
	pp &= ~EDP_BLC_ENABLE;
2174

2175
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2176 2177 2178

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
2179

2180
	pps_unlock(intel_dp);
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2181 2182

	intel_dp->last_backlight_off = jiffies;
2183
	edp_wait_backlight_off(intel_dp);
2184
}
2185

2186 2187 2188 2189 2190 2191 2192
/* Disable backlight PP control and backlight PWM. */
void intel_edp_backlight_off(struct intel_dp *intel_dp)
{
	if (!is_edp(intel_dp))
		return;

	DRM_DEBUG_KMS("\n");
2193

2194
	_intel_edp_backlight_off(intel_dp);
2195
	intel_panel_disable_backlight(intel_dp->attached_connector);
2196
}
2197

2198 2199 2200 2201 2202 2203 2204 2205
/*
 * Hook for controlling the panel power control backlight through the bl_power
 * sysfs attribute. Take care to handle multiple calls.
 */
static void intel_edp_backlight_power(struct intel_connector *connector,
				      bool enable)
{
	struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
V
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2206 2207
	bool is_enabled;

2208
	pps_lock(intel_dp);
V
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2209
	is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2210
	pps_unlock(intel_dp);
2211 2212 2213 2214

	if (is_enabled == enable)
		return;

2215 2216
	DRM_DEBUG_KMS("panel power control backlight %s\n",
		      enable ? "enable" : "disable");
2217 2218 2219 2220 2221 2222 2223

	if (enable)
		_intel_edp_backlight_on(intel_dp);
	else
		_intel_edp_backlight_off(intel_dp);
}

2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252
static const char *state_string(bool enabled)
{
	return enabled ? "on" : "off";
}

static void assert_dp_port(struct intel_dp *intel_dp, bool state)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
	bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;

	I915_STATE_WARN(cur_state != state,
			"DP port %c state assertion failure (expected %s, current %s)\n",
			port_name(dig_port->port),
			state_string(state), state_string(cur_state));
}
#define assert_dp_port_disabled(d) assert_dp_port((d), false)

static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
{
	bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;

	I915_STATE_WARN(cur_state != state,
			"eDP PLL state assertion failure (expected %s, current %s)\n",
			state_string(state), state_string(cur_state));
}
#define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
#define assert_edp_pll_disabled(d) assert_edp_pll((d), false)

2253
static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
2254
{
2255
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2256 2257
	struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2258

2259 2260 2261
	assert_pipe_disabled(dev_priv, crtc->pipe);
	assert_dp_port_disabled(intel_dp);
	assert_edp_pll_disabled(dev_priv);
2262

2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276
	DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
		      crtc->config->port_clock);

	intel_dp->DP &= ~DP_PLL_FREQ_MASK;

	if (crtc->config->port_clock == 162000)
		intel_dp->DP |= DP_PLL_FREQ_162MHZ;
	else
		intel_dp->DP |= DP_PLL_FREQ_270MHZ;

	I915_WRITE(DP_A, intel_dp->DP);
	POSTING_READ(DP_A);
	udelay(500);

2277
	intel_dp->DP |= DP_PLL_ENABLE;
2278

2279
	I915_WRITE(DP_A, intel_dp->DP);
2280 2281
	POSTING_READ(DP_A);
	udelay(200);
2282 2283
}

2284
static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2285
{
2286
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2287 2288
	struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2289

2290 2291 2292
	assert_pipe_disabled(dev_priv, crtc->pipe);
	assert_dp_port_disabled(intel_dp);
	assert_edp_pll_enabled(dev_priv);
2293

2294 2295
	DRM_DEBUG_KMS("disabling eDP PLL\n");

2296
	intel_dp->DP &= ~DP_PLL_ENABLE;
2297

2298
	I915_WRITE(DP_A, intel_dp->DP);
2299
	POSTING_READ(DP_A);
2300 2301 2302
	udelay(200);
}

2303
/* If the sink supports it, try to set the power state appropriately */
2304
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2305 2306 2307 2308 2309 2310 2311 2312
{
	int ret, i;

	/* Should have a valid DPCD by this point */
	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
		return;

	if (mode != DRM_MODE_DPMS_ON) {
2313 2314
		ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
					 DP_SET_POWER_D3);
2315 2316 2317 2318 2319 2320
	} else {
		/*
		 * When turning on, we need to retry for 1ms to give the sink
		 * time to wake up.
		 */
		for (i = 0; i < 3; i++) {
2321 2322
			ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
						 DP_SET_POWER_D0);
2323 2324 2325 2326 2327
			if (ret == 1)
				break;
			msleep(1);
		}
	}
2328 2329 2330 2331

	if (ret != 1)
		DRM_DEBUG_KMS("failed to %s sink power state\n",
			      mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2332 2333
}

2334 2335
static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
				  enum pipe *pipe)
2336
{
2337
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2338
	enum port port = dp_to_dig_port(intel_dp)->port;
2339 2340
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2341 2342 2343 2344
	enum intel_display_power_domain power_domain;
	u32 tmp;

	power_domain = intel_display_port_power_domain(encoder);
2345
	if (!intel_display_power_is_enabled(dev_priv, power_domain))
2346 2347 2348
		return false;

	tmp = I915_READ(intel_dp->output_reg);
2349 2350 2351 2352

	if (!(tmp & DP_PORT_EN))
		return false;

2353
	if (IS_GEN7(dev) && port == PORT_A) {
2354
		*pipe = PORT_TO_PIPE_CPT(tmp);
2355
	} else if (HAS_PCH_CPT(dev) && port != PORT_A) {
2356
		enum pipe p;
2357

2358 2359 2360 2361
		for_each_pipe(dev_priv, p) {
			u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
			if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
				*pipe = p;
2362 2363 2364 2365
				return true;
			}
		}

2366 2367
		DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
			      intel_dp->output_reg);
2368 2369 2370 2371
	} else if (IS_CHERRYVIEW(dev)) {
		*pipe = DP_PORT_TO_PIPE_CHV(tmp);
	} else {
		*pipe = PORT_TO_PIPE(tmp);
2372
	}
2373

2374 2375
	return true;
}
2376

2377
static void intel_dp_get_config(struct intel_encoder *encoder,
2378
				struct intel_crtc_state *pipe_config)
2379 2380 2381
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	u32 tmp, flags = 0;
2382 2383 2384 2385
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = dp_to_dig_port(intel_dp)->port;
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2386
	int dotclock;
2387

2388
	tmp = I915_READ(intel_dp->output_reg);
2389 2390

	pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2391

2392
	if (HAS_PCH_CPT(dev) && port != PORT_A) {
2393 2394 2395
		u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));

		if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2396 2397 2398
			flags |= DRM_MODE_FLAG_PHSYNC;
		else
			flags |= DRM_MODE_FLAG_NHSYNC;
2399

2400
		if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2401 2402 2403 2404
			flags |= DRM_MODE_FLAG_PVSYNC;
		else
			flags |= DRM_MODE_FLAG_NVSYNC;
	} else {
2405
		if (tmp & DP_SYNC_HS_HIGH)
2406 2407 2408
			flags |= DRM_MODE_FLAG_PHSYNC;
		else
			flags |= DRM_MODE_FLAG_NHSYNC;
2409

2410
		if (tmp & DP_SYNC_VS_HIGH)
2411 2412 2413 2414
			flags |= DRM_MODE_FLAG_PVSYNC;
		else
			flags |= DRM_MODE_FLAG_NVSYNC;
	}
2415

2416
	pipe_config->base.adjusted_mode.flags |= flags;
2417

2418 2419 2420 2421
	if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
	    tmp & DP_COLOR_RANGE_16_235)
		pipe_config->limited_color_range = true;

2422 2423
	pipe_config->has_dp_encoder = true;

2424 2425 2426
	pipe_config->lane_count =
		((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;

2427 2428
	intel_dp_get_m_n(crtc, pipe_config);

2429
	if (port == PORT_A) {
2430
		if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2431 2432 2433 2434
			pipe_config->port_clock = 162000;
		else
			pipe_config->port_clock = 270000;
	}
2435 2436 2437 2438 2439 2440 2441

	dotclock = intel_dotclock_calculate(pipe_config->port_clock,
					    &pipe_config->dp_m_n);

	if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
		ironlake_check_encoder_dotclock(pipe_config, dotclock);

2442
	pipe_config->base.adjusted_mode.crtc_clock = dotclock;
2443

2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462
	if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
	    pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
		/*
		 * This is a big fat ugly hack.
		 *
		 * Some machines in UEFI boot mode provide us a VBT that has 18
		 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
		 * unknown we fail to light up. Yet the same BIOS boots up with
		 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
		 * max, not what it tells us to use.
		 *
		 * Note: This will still be broken if the eDP panel is not lit
		 * up by the BIOS, and thus we can't get the mode at module
		 * load.
		 */
		DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
			      pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
		dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
	}
2463 2464
}

2465
static void intel_disable_dp(struct intel_encoder *encoder)
2466
{
2467
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2468
	struct drm_device *dev = encoder->base.dev;
2469 2470
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);

2471
	if (crtc->config->has_audio)
2472
		intel_audio_codec_disable(encoder);
2473

2474 2475 2476
	if (HAS_PSR(dev) && !HAS_DDI(dev))
		intel_psr_disable(intel_dp);

2477 2478
	/* Make sure the panel is off before trying to change the mode. But also
	 * ensure that we have vdd while we switch off the panel. */
2479
	intel_edp_panel_vdd_on(intel_dp);
2480
	intel_edp_backlight_off(intel_dp);
2481
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2482
	intel_edp_panel_off(intel_dp);
2483

2484 2485
	/* disable the port before the pipe on g4x */
	if (INTEL_INFO(dev)->gen < 5)
2486
		intel_dp_link_down(intel_dp);
2487 2488
}

2489
static void ilk_post_disable_dp(struct intel_encoder *encoder)
2490
{
2491
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2492
	enum port port = dp_to_dig_port(intel_dp)->port;
2493

2494
	intel_dp_link_down(intel_dp);
2495 2496

	/* Only ilk+ has port A */
2497 2498
	if (port == PORT_A)
		ironlake_edp_pll_off(intel_dp);
2499 2500 2501 2502 2503 2504 2505
}

static void vlv_post_disable_dp(struct intel_encoder *encoder)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

	intel_dp_link_down(intel_dp);
2506 2507
}

2508 2509
static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
				     bool reset)
2510
{
2511 2512 2513 2514 2515
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
	enum pipe pipe = crtc->pipe;
	uint32_t val;
2516

2517 2518 2519 2520 2521 2522
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
	if (reset)
		val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
	else
		val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2523

2524 2525 2526 2527 2528 2529 2530 2531
	if (crtc->config->lane_count > 2) {
		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
		if (reset)
			val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
		else
			val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
	}
2532

2533
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2534
	val |= CHV_PCS_REQ_SOFTRESET_EN;
2535 2536 2537 2538
	if (reset)
		val &= ~DPIO_PCS_CLK_SOFT_RESET;
	else
		val |= DPIO_PCS_CLK_SOFT_RESET;
2539
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2540

2541
	if (crtc->config->lane_count > 2) {
2542 2543
		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
		val |= CHV_PCS_REQ_SOFTRESET_EN;
2544 2545 2546 2547
		if (reset)
			val &= ~DPIO_PCS_CLK_SOFT_RESET;
		else
			val |= DPIO_PCS_CLK_SOFT_RESET;
2548 2549
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
	}
2550
}
2551

2552 2553 2554 2555 2556
static void chv_post_disable_dp(struct intel_encoder *encoder)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2557

2558 2559 2560 2561 2562 2563
	intel_dp_link_down(intel_dp);

	mutex_lock(&dev_priv->sb_lock);

	/* Assert data lane reset */
	chv_data_lane_soft_reset(encoder, true);
2564

V
Ville Syrjälä 已提交
2565
	mutex_unlock(&dev_priv->sb_lock);
2566 2567
}

2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603
static void
_intel_dp_set_link_train(struct intel_dp *intel_dp,
			 uint32_t *DP,
			 uint8_t dp_train_pat)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = intel_dig_port->port;

	if (HAS_DDI(dev)) {
		uint32_t temp = I915_READ(DP_TP_CTL(port));

		if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
			temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
		else
			temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;

		temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
			temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;

			break;
		case DP_TRAINING_PATTERN_1:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
			break;
		case DP_TRAINING_PATTERN_2:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
			break;
		case DP_TRAINING_PATTERN_3:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
			break;
		}
		I915_WRITE(DP_TP_CTL(port), temp);

2604 2605
	} else if ((IS_GEN7(dev) && port == PORT_A) ||
		   (HAS_PCH_CPT(dev) && port != PORT_A)) {
2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655
		*DP &= ~DP_LINK_TRAIN_MASK_CPT;

		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
			*DP |= DP_LINK_TRAIN_OFF_CPT;
			break;
		case DP_TRAINING_PATTERN_1:
			*DP |= DP_LINK_TRAIN_PAT_1_CPT;
			break;
		case DP_TRAINING_PATTERN_2:
			*DP |= DP_LINK_TRAIN_PAT_2_CPT;
			break;
		case DP_TRAINING_PATTERN_3:
			DRM_ERROR("DP training pattern 3 not supported\n");
			*DP |= DP_LINK_TRAIN_PAT_2_CPT;
			break;
		}

	} else {
		if (IS_CHERRYVIEW(dev))
			*DP &= ~DP_LINK_TRAIN_MASK_CHV;
		else
			*DP &= ~DP_LINK_TRAIN_MASK;

		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
			*DP |= DP_LINK_TRAIN_OFF;
			break;
		case DP_TRAINING_PATTERN_1:
			*DP |= DP_LINK_TRAIN_PAT_1;
			break;
		case DP_TRAINING_PATTERN_2:
			*DP |= DP_LINK_TRAIN_PAT_2;
			break;
		case DP_TRAINING_PATTERN_3:
			if (IS_CHERRYVIEW(dev)) {
				*DP |= DP_LINK_TRAIN_PAT_3_CHV;
			} else {
				DRM_ERROR("DP training pattern 3 not supported\n");
				*DP |= DP_LINK_TRAIN_PAT_2;
			}
			break;
		}
	}
}

static void intel_dp_enable_port(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
2656 2657
	struct intel_crtc *crtc =
		to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
2658 2659 2660 2661 2662 2663 2664

	/* enable with pattern 1 (as per spec) */
	_intel_dp_set_link_train(intel_dp, &intel_dp->DP,
				 DP_TRAINING_PATTERN_1);

	I915_WRITE(intel_dp->output_reg, intel_dp->DP);
	POSTING_READ(intel_dp->output_reg);
2665 2666 2667 2668 2669 2670 2671 2672

	/*
	 * Magic for VLV/CHV. We _must_ first set up the register
	 * without actually enabling the port, and then do another
	 * write to enable the port. Otherwise link training will
	 * fail when the power sequencer is freshly used for this port.
	 */
	intel_dp->DP |= DP_PORT_EN;
2673 2674
	if (crtc->config->has_audio)
		intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2675 2676 2677

	I915_WRITE(intel_dp->output_reg, intel_dp->DP);
	POSTING_READ(intel_dp->output_reg);
2678 2679
}

2680
static void intel_enable_dp(struct intel_encoder *encoder)
2681
{
2682 2683 2684
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2685
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2686
	uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2687 2688
	enum port port = dp_to_dig_port(intel_dp)->port;
	enum pipe pipe = crtc->pipe;
2689

2690 2691
	if (WARN_ON(dp_reg & DP_PORT_EN))
		return;
2692

2693 2694 2695 2696 2697
	pps_lock(intel_dp);

	if (IS_VALLEYVIEW(dev))
		vlv_init_panel_power_sequencer(intel_dp);

2698
	intel_dp_enable_port(intel_dp);
2699

2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710
	if (port == PORT_A && IS_GEN5(dev_priv)) {
		/*
		 * Underrun reporting for the other pipe was disabled in
		 * g4x_pre_enable_dp(). The eDP PLL and port have now been
		 * enabled, so it's now safe to re-enable underrun reporting.
		 */
		intel_wait_for_vblank_if_active(dev_priv->dev, !pipe);
		intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, true);
		intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, true);
	}

2711 2712 2713 2714 2715 2716
	edp_panel_vdd_on(intel_dp);
	edp_panel_on(intel_dp);
	edp_panel_vdd_off(intel_dp, true);

	pps_unlock(intel_dp);

2717 2718 2719 2720 2721 2722
	if (IS_VALLEYVIEW(dev)) {
		unsigned int lane_mask = 0x0;

		if (IS_CHERRYVIEW(dev))
			lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count);

2723 2724
		vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
				    lane_mask);
2725
	}
2726

2727
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2728
	intel_dp_start_link_train(intel_dp);
2729
	intel_dp_stop_link_train(intel_dp);
2730

2731
	if (crtc->config->has_audio) {
2732
		DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2733
				 pipe_name(pipe));
2734 2735
		intel_audio_codec_enable(encoder);
	}
2736
}
2737

2738 2739
static void g4x_enable_dp(struct intel_encoder *encoder)
{
2740 2741
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

2742
	intel_enable_dp(encoder);
2743
	intel_edp_backlight_on(intel_dp);
2744
}
2745

2746 2747
static void vlv_enable_dp(struct intel_encoder *encoder)
{
2748 2749
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

2750
	intel_edp_backlight_on(intel_dp);
2751
	intel_psr_enable(intel_dp);
2752 2753
}

2754
static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2755
{
2756
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2757
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2758 2759
	enum port port = dp_to_dig_port(intel_dp)->port;
	enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
2760

2761 2762
	intel_dp_prepare(encoder);

2763 2764 2765 2766 2767 2768 2769 2770 2771 2772 2773 2774 2775
	if (port == PORT_A && IS_GEN5(dev_priv)) {
		/*
		 * We get FIFO underruns on the other pipe when
		 * enabling the CPU eDP PLL, and when enabling CPU
		 * eDP port. We could potentially avoid the PLL
		 * underrun with a vblank wait just prior to enabling
		 * the PLL, but that doesn't appear to help the port
		 * enable case. Just sweep it all under the rug.
		 */
		intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, false);
		intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, false);
	}

2776
	/* Only ilk+ has port A */
2777
	if (port == PORT_A)
2778 2779 2780
		ironlake_edp_pll_on(intel_dp);
}

2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806
static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
	enum pipe pipe = intel_dp->pps_pipe;
	int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);

	edp_panel_vdd_off_sync(intel_dp);

	/*
	 * VLV seems to get confused when multiple power seqeuencers
	 * have the same port selected (even if only one has power/vdd
	 * enabled). The failure manifests as vlv_wait_port_ready() failing
	 * CHV on the other hand doesn't seem to mind having the same port
	 * selected in multiple power seqeuencers, but let's clear the
	 * port select always when logically disconnecting a power sequencer
	 * from a port.
	 */
	DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
		      pipe_name(pipe), port_name(intel_dig_port->port));
	I915_WRITE(pp_on_reg, 0);
	POSTING_READ(pp_on_reg);

	intel_dp->pps_pipe = INVALID_PIPE;
}

2807 2808 2809 2810 2811 2812 2813 2814
static void vlv_steal_power_sequencer(struct drm_device *dev,
				      enum pipe pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_encoder *encoder;

	lockdep_assert_held(&dev_priv->pps_mutex);

2815 2816 2817
	if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
		return;

2818 2819 2820
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		struct intel_dp *intel_dp;
2821
		enum port port;
2822 2823 2824 2825 2826

		if (encoder->type != INTEL_OUTPUT_EDP)
			continue;

		intel_dp = enc_to_intel_dp(&encoder->base);
2827
		port = dp_to_dig_port(intel_dp)->port;
2828 2829 2830 2831 2832

		if (intel_dp->pps_pipe != pipe)
			continue;

		DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2833
			      pipe_name(pipe), port_name(port));
2834

2835
		WARN(encoder->base.crtc,
2836 2837
		     "stealing pipe %c power sequencer from active eDP port %c\n",
		     pipe_name(pipe), port_name(port));
2838 2839

		/* make sure vdd is off before we steal it */
2840
		vlv_detach_power_sequencer(intel_dp);
2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853
	}
}

static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *encoder = &intel_dig_port->base;
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);

	lockdep_assert_held(&dev_priv->pps_mutex);

2854 2855 2856
	if (!is_edp(intel_dp))
		return;

2857 2858 2859 2860 2861 2862 2863 2864 2865
	if (intel_dp->pps_pipe == crtc->pipe)
		return;

	/*
	 * If another power sequencer was being used on this
	 * port previously make sure to turn off vdd there while
	 * we still have control of it.
	 */
	if (intel_dp->pps_pipe != INVALID_PIPE)
2866
		vlv_detach_power_sequencer(intel_dp);
2867 2868 2869 2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880

	/*
	 * We may be stealing the power
	 * sequencer from another port.
	 */
	vlv_steal_power_sequencer(dev, crtc->pipe);

	/* now it's all ours */
	intel_dp->pps_pipe = crtc->pipe;

	DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
		      pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));

	/* init power sequencer on this pipe and port */
2881 2882
	intel_dp_init_panel_power_sequencer(dev, intel_dp);
	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
2883 2884
}

2885
static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2886
{
2887
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2888
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2889
	struct drm_device *dev = encoder->base.dev;
2890
	struct drm_i915_private *dev_priv = dev->dev_private;
2891
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2892
	enum dpio_channel port = vlv_dport_to_channel(dport);
2893 2894
	int pipe = intel_crtc->pipe;
	u32 val;
2895

V
Ville Syrjälä 已提交
2896
	mutex_lock(&dev_priv->sb_lock);
2897

2898
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2899 2900 2901 2902 2903 2904
	val = 0;
	if (pipe)
		val |= (1<<21);
	else
		val &= ~(1<<21);
	val |= 0x001000c4;
2905 2906 2907
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2908

V
Ville Syrjälä 已提交
2909
	mutex_unlock(&dev_priv->sb_lock);
2910 2911

	intel_enable_dp(encoder);
2912 2913
}

2914
static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2915 2916 2917 2918
{
	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2919 2920
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
2921
	enum dpio_channel port = vlv_dport_to_channel(dport);
2922
	int pipe = intel_crtc->pipe;
2923

2924 2925
	intel_dp_prepare(encoder);

2926
	/* Program Tx lane resets to default */
V
Ville Syrjälä 已提交
2927
	mutex_lock(&dev_priv->sb_lock);
2928
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2929 2930
			 DPIO_PCS_TX_LANE2_RESET |
			 DPIO_PCS_TX_LANE1_RESET);
2931
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2932 2933 2934 2935 2936 2937
			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
			 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
			 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
				 DPIO_PCS_CLK_SOFT_RESET);

	/* Fix up inter-pair skew failure */
2938 2939 2940
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
V
Ville Syrjälä 已提交
2941
	mutex_unlock(&dev_priv->sb_lock);
2942 2943
}

2944 2945 2946 2947 2948 2949 2950 2951 2952 2953
static void chv_pre_enable_dp(struct intel_encoder *encoder)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
	enum dpio_channel ch = vlv_dport_to_channel(dport);
	int pipe = intel_crtc->pipe;
2954
	int data, i, stagger;
2955
	u32 val;
2956

V
Ville Syrjälä 已提交
2957
	mutex_lock(&dev_priv->sb_lock);
2958

2959 2960 2961 2962 2963
	/* allow hardware to manage TX FIFO reset source */
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);

2964 2965 2966 2967 2968
	if (intel_crtc->config->lane_count > 2) {
		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
		val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
	}
2969

2970
	/* Program Tx lane latency optimal setting*/
2971
	for (i = 0; i < intel_crtc->config->lane_count; i++) {
2972
		/* Set the upar bit */
2973 2974 2975 2976
		if (intel_crtc->config->lane_count == 1)
			data = 0x0;
		else
			data = (i == 1) ? 0x0 : 0x1;
2977 2978 2979 2980 2981
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
				data << DPIO_UPAR_SHIFT);
	}

	/* Data lane stagger programming */
2982 2983 2984 2985 2986 2987 2988 2989 2990 2991 2992 2993 2994 2995 2996
	if (intel_crtc->config->port_clock > 270000)
		stagger = 0x18;
	else if (intel_crtc->config->port_clock > 135000)
		stagger = 0xd;
	else if (intel_crtc->config->port_clock > 67500)
		stagger = 0x7;
	else if (intel_crtc->config->port_clock > 33750)
		stagger = 0x4;
	else
		stagger = 0x2;

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
	val |= DPIO_TX2_STAGGER_MASK(0x1f);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);

2997 2998 2999 3000 3001
	if (intel_crtc->config->lane_count > 2) {
		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
		val |= DPIO_TX2_STAGGER_MASK(0x1f);
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
	}
3002 3003 3004 3005 3006 3007 3008 3009

	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
		       DPIO_LANESTAGGER_STRAP(stagger) |
		       DPIO_LANESTAGGER_STRAP_OVRD |
		       DPIO_TX1_STAGGER_MASK(0x1f) |
		       DPIO_TX1_STAGGER_MULT(6) |
		       DPIO_TX2_STAGGER_MULT(0));

3010 3011 3012 3013 3014 3015 3016 3017
	if (intel_crtc->config->lane_count > 2) {
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
			       DPIO_LANESTAGGER_STRAP(stagger) |
			       DPIO_LANESTAGGER_STRAP_OVRD |
			       DPIO_TX1_STAGGER_MASK(0x1f) |
			       DPIO_TX1_STAGGER_MULT(7) |
			       DPIO_TX2_STAGGER_MULT(5));
	}
3018

3019 3020 3021
	/* Deassert data lane reset */
	chv_data_lane_soft_reset(encoder, false);

V
Ville Syrjälä 已提交
3022
	mutex_unlock(&dev_priv->sb_lock);
3023 3024

	intel_enable_dp(encoder);
3025 3026 3027 3028 3029 3030

	/* Second common lane will stay alive on its own now */
	if (dport->release_cl2_override) {
		chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
		dport->release_cl2_override = false;
	}
3031 3032
}

3033 3034 3035 3036 3037 3038 3039 3040 3041
static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
{
	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
	enum dpio_channel ch = vlv_dport_to_channel(dport);
	enum pipe pipe = intel_crtc->pipe;
3042 3043
	unsigned int lane_mask =
		intel_dp_unused_lane_mask(intel_crtc->config->lane_count);
3044 3045
	u32 val;

3046 3047
	intel_dp_prepare(encoder);

3048 3049 3050 3051 3052 3053 3054 3055
	/*
	 * Must trick the second common lane into life.
	 * Otherwise we can't even access the PLL.
	 */
	if (ch == DPIO_CH0 && pipe == PIPE_B)
		dport->release_cl2_override =
			!chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);

3056 3057
	chv_phy_powergate_lanes(encoder, true, lane_mask);

V
Ville Syrjälä 已提交
3058
	mutex_lock(&dev_priv->sb_lock);
3059

3060 3061 3062
	/* Assert data lane reset */
	chv_data_lane_soft_reset(encoder, true);

3063 3064 3065 3066 3067 3068 3069 3070 3071 3072 3073 3074 3075 3076 3077 3078 3079 3080 3081
	/* program left/right clock distribution */
	if (pipe != PIPE_B) {
		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
		if (ch == DPIO_CH0)
			val |= CHV_BUFLEFTENA1_FORCE;
		if (ch == DPIO_CH1)
			val |= CHV_BUFRIGHTENA1_FORCE;
		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
	} else {
		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
		if (ch == DPIO_CH0)
			val |= CHV_BUFLEFTENA2_FORCE;
		if (ch == DPIO_CH1)
			val |= CHV_BUFRIGHTENA2_FORCE;
		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
	}

3082 3083 3084 3085 3086 3087 3088 3089 3090
	/* program clock channel usage */
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
	if (pipe != PIPE_B)
		val &= ~CHV_PCS_USEDCLKCHANNEL;
	else
		val |= CHV_PCS_USEDCLKCHANNEL;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);

3091 3092 3093 3094 3095 3096 3097 3098 3099
	if (intel_crtc->config->lane_count > 2) {
		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
		val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
		if (pipe != PIPE_B)
			val &= ~CHV_PCS_USEDCLKCHANNEL;
		else
			val |= CHV_PCS_USEDCLKCHANNEL;
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
	}
3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111 3112

	/*
	 * This a a bit weird since generally CL
	 * matches the pipe, but here we need to
	 * pick the CL based on the port.
	 */
	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
	if (pipe != PIPE_B)
		val &= ~CHV_CMN_USEDCLKCHANNEL;
	else
		val |= CHV_CMN_USEDCLKCHANNEL;
	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);

V
Ville Syrjälä 已提交
3113
	mutex_unlock(&dev_priv->sb_lock);
3114 3115
}

3116 3117 3118 3119 3120 3121 3122 3123 3124 3125 3126 3127 3128 3129 3130 3131 3132 3133 3134 3135
static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
	u32 val;

	mutex_lock(&dev_priv->sb_lock);

	/* disable left/right clock distribution */
	if (pipe != PIPE_B) {
		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
	} else {
		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
	}

	mutex_unlock(&dev_priv->sb_lock);
3136

3137 3138 3139 3140 3141 3142 3143 3144 3145
	/*
	 * Leave the power down bit cleared for at least one
	 * lane so that chv_powergate_phy_ch() will power
	 * on something when the channel is otherwise unused.
	 * When the port is off and the override is removed
	 * the lanes power down anyway, so otherwise it doesn't
	 * really matter what the state of power down bits is
	 * after this.
	 */
3146
	chv_phy_powergate_lanes(encoder, false, 0x0);
3147 3148
}

3149
/*
3150 3151
 * Native read with retry for link status and receiver capability reads for
 * cases where the sink may still be asleep.
3152 3153 3154
 *
 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
 * supposed to retry 3 times per the spec.
3155
 */
3156 3157 3158
static ssize_t
intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
			void *buffer, size_t size)
3159
{
3160 3161
	ssize_t ret;
	int i;
3162

3163 3164 3165 3166 3167 3168 3169
	/*
	 * Sometime we just get the same incorrect byte repeated
	 * over the entire buffer. Doing just one throw away read
	 * initially seems to "solve" it.
	 */
	drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);

3170
	for (i = 0; i < 3; i++) {
3171 3172 3173
		ret = drm_dp_dpcd_read(aux, offset, buffer, size);
		if (ret == size)
			return ret;
3174 3175
		msleep(1);
	}
3176

3177
	return ret;
3178 3179 3180 3181 3182 3183
}

/*
 * Fetch AUX CH registers 0x202 - 0x207 which contain
 * link status information
 */
3184
bool
3185
intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3186
{
3187 3188 3189 3190
	return intel_dp_dpcd_read_wake(&intel_dp->aux,
				       DP_LANE0_1_STATUS,
				       link_status,
				       DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3191 3192
}

3193
/* These are source-specific values. */
3194
uint8_t
K
Keith Packard 已提交
3195
intel_dp_voltage_max(struct intel_dp *intel_dp)
3196
{
3197
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
3198
	struct drm_i915_private *dev_priv = dev->dev_private;
3199
	enum port port = dp_to_dig_port(intel_dp)->port;
K
Keith Packard 已提交
3200

3201 3202 3203
	if (IS_BROXTON(dev))
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
	else if (INTEL_INFO(dev)->gen >= 9) {
3204
		if (dev_priv->edp_low_vswing && port == PORT_A)
3205
			return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3206
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3207
	} else if (IS_VALLEYVIEW(dev))
3208
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3209
	else if (IS_GEN7(dev) && port == PORT_A)
3210
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3211
	else if (HAS_PCH_CPT(dev) && port != PORT_A)
3212
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
K
Keith Packard 已提交
3213
	else
3214
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
K
Keith Packard 已提交
3215 3216
}

3217
uint8_t
K
Keith Packard 已提交
3218 3219
intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
{
3220
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
3221
	enum port port = dp_to_dig_port(intel_dp)->port;
K
Keith Packard 已提交
3222

3223 3224 3225 3226 3227 3228 3229 3230
	if (INTEL_INFO(dev)->gen >= 9) {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
			return DP_TRAIN_PRE_EMPH_LEVEL_3;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
			return DP_TRAIN_PRE_EMPH_LEVEL_1;
3231 3232
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
3233 3234 3235 3236
		default:
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
		}
	} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3237
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3238 3239 3240 3241 3242 3243 3244
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
			return DP_TRAIN_PRE_EMPH_LEVEL_3;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
			return DP_TRAIN_PRE_EMPH_LEVEL_1;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3245
		default:
3246
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
3247
		}
3248 3249
	} else if (IS_VALLEYVIEW(dev)) {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3250 3251 3252 3253 3254 3255 3256
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
			return DP_TRAIN_PRE_EMPH_LEVEL_3;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
			return DP_TRAIN_PRE_EMPH_LEVEL_1;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3257
		default:
3258
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
3259
		}
3260
	} else if (IS_GEN7(dev) && port == PORT_A) {
K
Keith Packard 已提交
3261
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3262 3263 3264 3265 3266
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
			return DP_TRAIN_PRE_EMPH_LEVEL_1;
K
Keith Packard 已提交
3267
		default:
3268
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
K
Keith Packard 已提交
3269 3270 3271
		}
	} else {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3272 3273 3274 3275 3276 3277 3278
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
			return DP_TRAIN_PRE_EMPH_LEVEL_1;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
K
Keith Packard 已提交
3279
		default:
3280
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
K
Keith Packard 已提交
3281
		}
3282 3283 3284
	}
}

3285
static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3286 3287 3288 3289
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3290 3291
	struct intel_crtc *intel_crtc =
		to_intel_crtc(dport->base.base.crtc);
3292 3293 3294
	unsigned long demph_reg_value, preemph_reg_value,
		uniqtranscale_reg_value;
	uint8_t train_set = intel_dp->train_set[0];
3295
	enum dpio_channel port = vlv_dport_to_channel(dport);
3296
	int pipe = intel_crtc->pipe;
3297 3298

	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3299
	case DP_TRAIN_PRE_EMPH_LEVEL_0:
3300 3301
		preemph_reg_value = 0x0004000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3302
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3303 3304 3305
			demph_reg_value = 0x2B405555;
			uniqtranscale_reg_value = 0x552AB83A;
			break;
3306
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3307 3308 3309
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x5548B83A;
			break;
3310
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3311 3312 3313
			demph_reg_value = 0x2B245555;
			uniqtranscale_reg_value = 0x5560B83A;
			break;
3314
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3315 3316 3317 3318 3319 3320 3321
			demph_reg_value = 0x2B405555;
			uniqtranscale_reg_value = 0x5598DA3A;
			break;
		default:
			return 0;
		}
		break;
3322
	case DP_TRAIN_PRE_EMPH_LEVEL_1:
3323 3324
		preemph_reg_value = 0x0002000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3325
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3326 3327 3328
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x5552B83A;
			break;
3329
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3330 3331 3332
			demph_reg_value = 0x2B404848;
			uniqtranscale_reg_value = 0x5580B83A;
			break;
3333
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3334 3335 3336 3337 3338 3339 3340
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
3341
	case DP_TRAIN_PRE_EMPH_LEVEL_2:
3342 3343
		preemph_reg_value = 0x0000000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3344
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3345 3346 3347
			demph_reg_value = 0x2B305555;
			uniqtranscale_reg_value = 0x5570B83A;
			break;
3348
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3349 3350 3351 3352 3353 3354 3355
			demph_reg_value = 0x2B2B4040;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
3356
	case DP_TRAIN_PRE_EMPH_LEVEL_3:
3357 3358
		preemph_reg_value = 0x0006000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3359
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3360 3361 3362 3363 3364 3365 3366 3367 3368 3369 3370
			demph_reg_value = 0x1B405555;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
	default:
		return 0;
	}

V
Ville Syrjälä 已提交
3371
	mutex_lock(&dev_priv->sb_lock);
3372 3373 3374
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
3375
			 uniqtranscale_reg_value);
3376 3377 3378 3379
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
V
Ville Syrjälä 已提交
3380
	mutex_unlock(&dev_priv->sb_lock);
3381 3382 3383 3384

	return 0;
}

3385 3386 3387 3388 3389 3390
static bool chv_need_uniq_trans_scale(uint8_t train_set)
{
	return (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) == DP_TRAIN_PRE_EMPH_LEVEL_0 &&
		(train_set & DP_TRAIN_VOLTAGE_SWING_MASK) == DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
}

3391
static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3392 3393 3394 3395 3396
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
	struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
3397
	u32 deemph_reg_value, margin_reg_value, val;
3398 3399
	uint8_t train_set = intel_dp->train_set[0];
	enum dpio_channel ch = vlv_dport_to_channel(dport);
3400 3401
	enum pipe pipe = intel_crtc->pipe;
	int i;
3402 3403

	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3404
	case DP_TRAIN_PRE_EMPH_LEVEL_0:
3405
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3406
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3407 3408 3409
			deemph_reg_value = 128;
			margin_reg_value = 52;
			break;
3410
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3411 3412 3413
			deemph_reg_value = 128;
			margin_reg_value = 77;
			break;
3414
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3415 3416 3417
			deemph_reg_value = 128;
			margin_reg_value = 102;
			break;
3418
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3419 3420 3421 3422 3423 3424 3425 3426
			deemph_reg_value = 128;
			margin_reg_value = 154;
			/* FIXME extra to set for 1200 */
			break;
		default:
			return 0;
		}
		break;
3427
	case DP_TRAIN_PRE_EMPH_LEVEL_1:
3428
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3429
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3430 3431 3432
			deemph_reg_value = 85;
			margin_reg_value = 78;
			break;
3433
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3434 3435 3436
			deemph_reg_value = 85;
			margin_reg_value = 116;
			break;
3437
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3438 3439 3440 3441 3442 3443 3444
			deemph_reg_value = 85;
			margin_reg_value = 154;
			break;
		default:
			return 0;
		}
		break;
3445
	case DP_TRAIN_PRE_EMPH_LEVEL_2:
3446
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3447
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3448 3449 3450
			deemph_reg_value = 64;
			margin_reg_value = 104;
			break;
3451
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3452 3453 3454 3455 3456 3457 3458
			deemph_reg_value = 64;
			margin_reg_value = 154;
			break;
		default:
			return 0;
		}
		break;
3459
	case DP_TRAIN_PRE_EMPH_LEVEL_3:
3460
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3461
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3462 3463 3464 3465 3466 3467 3468 3469 3470 3471 3472
			deemph_reg_value = 43;
			margin_reg_value = 154;
			break;
		default:
			return 0;
		}
		break;
	default:
		return 0;
	}

V
Ville Syrjälä 已提交
3473
	mutex_lock(&dev_priv->sb_lock);
3474 3475

	/* Clear calc init */
3476 3477
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3478 3479
	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3480 3481
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);

3482 3483 3484 3485 3486 3487 3488
	if (intel_crtc->config->lane_count > 2) {
		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
		val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
		val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
		val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
	}
3489

3490 3491 3492 3493 3494
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);

3495 3496 3497 3498 3499 3500
	if (intel_crtc->config->lane_count > 2) {
		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
		val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
		val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
	}
3501

3502
	/* Program swing deemph */
3503
	for (i = 0; i < intel_crtc->config->lane_count; i++) {
3504 3505 3506 3507 3508
		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
		val &= ~DPIO_SWING_DEEMPH9P5_MASK;
		val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
	}
3509 3510

	/* Program swing margin */
3511
	for (i = 0; i < intel_crtc->config->lane_count; i++) {
3512
		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3513

3514 3515
		val &= ~DPIO_SWING_MARGIN000_MASK;
		val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
3516 3517 3518 3519 3520 3521 3522 3523 3524

		/*
		 * Supposedly this value shouldn't matter when unique transition
		 * scale is disabled, but in fact it does matter. Let's just
		 * always program the same value and hope it's OK.
		 */
		val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
		val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;

3525 3526
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
	}
3527

3528 3529 3530 3531 3532 3533
	/*
	 * The document said it needs to set bit 27 for ch0 and bit 26
	 * for ch1. Might be a typo in the doc.
	 * For now, for this unique transition scale selection, set bit
	 * 27 for ch0 and ch1.
	 */
3534
	for (i = 0; i < intel_crtc->config->lane_count; i++) {
3535
		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3536
		if (chv_need_uniq_trans_scale(train_set))
3537
			val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3538 3539 3540
		else
			val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3541 3542 3543
	}

	/* Start swing calculation */
3544 3545 3546 3547
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);

3548 3549 3550 3551 3552
	if (intel_crtc->config->lane_count > 2) {
		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
		val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
	}
3553

V
Ville Syrjälä 已提交
3554
	mutex_unlock(&dev_priv->sb_lock);
3555 3556 3557 3558

	return 0;
}

3559
static uint32_t
3560
gen4_signal_levels(uint8_t train_set)
3561
{
3562
	uint32_t	signal_levels = 0;
3563

3564
	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3565
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3566 3567 3568
	default:
		signal_levels |= DP_VOLTAGE_0_4;
		break;
3569
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3570 3571
		signal_levels |= DP_VOLTAGE_0_6;
		break;
3572
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3573 3574
		signal_levels |= DP_VOLTAGE_0_8;
		break;
3575
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3576 3577 3578
		signal_levels |= DP_VOLTAGE_1_2;
		break;
	}
3579
	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3580
	case DP_TRAIN_PRE_EMPH_LEVEL_0:
3581 3582 3583
	default:
		signal_levels |= DP_PRE_EMPHASIS_0;
		break;
3584
	case DP_TRAIN_PRE_EMPH_LEVEL_1:
3585 3586
		signal_levels |= DP_PRE_EMPHASIS_3_5;
		break;
3587
	case DP_TRAIN_PRE_EMPH_LEVEL_2:
3588 3589
		signal_levels |= DP_PRE_EMPHASIS_6;
		break;
3590
	case DP_TRAIN_PRE_EMPH_LEVEL_3:
3591 3592 3593 3594 3595 3596
		signal_levels |= DP_PRE_EMPHASIS_9_5;
		break;
	}
	return signal_levels;
}

3597 3598
/* Gen6's DP voltage swing and pre-emphasis control */
static uint32_t
3599
gen6_edp_signal_levels(uint8_t train_set)
3600
{
3601 3602 3603
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
3604 3605
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3606
		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3607
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3608
		return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3609 3610
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3611
		return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3612 3613
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3614
		return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3615 3616
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3617
		return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3618
	default:
3619 3620 3621
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3622 3623 3624
	}
}

K
Keith Packard 已提交
3625 3626
/* Gen7's DP voltage swing and pre-emphasis control */
static uint32_t
3627
gen7_edp_signal_levels(uint8_t train_set)
K
Keith Packard 已提交
3628 3629 3630 3631
{
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
3632
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
K
Keith Packard 已提交
3633
		return EDP_LINK_TRAIN_400MV_0DB_IVB;
3634
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
K
Keith Packard 已提交
3635
		return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3636
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
K
Keith Packard 已提交
3637 3638
		return EDP_LINK_TRAIN_400MV_6DB_IVB;

3639
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
K
Keith Packard 已提交
3640
		return EDP_LINK_TRAIN_600MV_0DB_IVB;
3641
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
K
Keith Packard 已提交
3642 3643
		return EDP_LINK_TRAIN_600MV_3_5DB_IVB;

3644
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
K
Keith Packard 已提交
3645
		return EDP_LINK_TRAIN_800MV_0DB_IVB;
3646
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
K
Keith Packard 已提交
3647 3648 3649 3650 3651 3652 3653 3654 3655
		return EDP_LINK_TRAIN_800MV_3_5DB_IVB;

	default:
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return EDP_LINK_TRAIN_500MV_0DB_IVB;
	}
}

3656
void
3657
intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3658 3659
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3660
	enum port port = intel_dig_port->port;
3661
	struct drm_device *dev = intel_dig_port->base.base.dev;
3662
	struct drm_i915_private *dev_priv = to_i915(dev);
3663
	uint32_t signal_levels, mask = 0;
3664 3665
	uint8_t train_set = intel_dp->train_set[0];

3666 3667 3668 3669 3670 3671 3672
	if (HAS_DDI(dev)) {
		signal_levels = ddi_signal_levels(intel_dp);

		if (IS_BROXTON(dev))
			signal_levels = 0;
		else
			mask = DDI_BUF_EMP_MASK;
3673
	} else if (IS_CHERRYVIEW(dev)) {
3674
		signal_levels = chv_signal_levels(intel_dp);
3675
	} else if (IS_VALLEYVIEW(dev)) {
3676
		signal_levels = vlv_signal_levels(intel_dp);
3677
	} else if (IS_GEN7(dev) && port == PORT_A) {
3678
		signal_levels = gen7_edp_signal_levels(train_set);
3679
		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3680
	} else if (IS_GEN6(dev) && port == PORT_A) {
3681
		signal_levels = gen6_edp_signal_levels(train_set);
3682 3683
		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
	} else {
3684
		signal_levels = gen4_signal_levels(train_set);
3685 3686 3687
		mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
	}

3688 3689 3690 3691 3692 3693 3694 3695
	if (mask)
		DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);

	DRM_DEBUG_KMS("Using vswing level %d\n",
		train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
	DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
		(train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
			DP_TRAIN_PRE_EMPHASIS_SHIFT);
3696

3697
	intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3698 3699 3700

	I915_WRITE(intel_dp->output_reg, intel_dp->DP);
	POSTING_READ(intel_dp->output_reg);
3701 3702
}

3703
void
3704 3705
intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
				       uint8_t dp_train_pat)
3706
{
3707
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3708 3709
	struct drm_i915_private *dev_priv =
		to_i915(intel_dig_port->base.base.dev);
3710

3711
	_intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3712

3713
	I915_WRITE(intel_dp->output_reg, intel_dp->DP);
C
Chris Wilson 已提交
3714
	POSTING_READ(intel_dp->output_reg);
3715 3716
}

3717
void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3718 3719 3720 3721 3722 3723 3724 3725 3726 3727 3728 3729 3730 3731 3732 3733 3734 3735 3736 3737 3738 3739 3740 3741 3742 3743 3744 3745 3746 3747
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = intel_dig_port->port;
	uint32_t val;

	if (!HAS_DDI(dev))
		return;

	val = I915_READ(DP_TP_CTL(port));
	val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
	val |= DP_TP_CTL_LINK_TRAIN_IDLE;
	I915_WRITE(DP_TP_CTL(port), val);

	/*
	 * On PORT_A we can have only eDP in SST mode. There the only reason
	 * we need to set idle transmission mode is to work around a HW issue
	 * where we enable the pipe while not in idle link-training mode.
	 * In this case there is requirement to wait for a minimum number of
	 * idle patterns to be sent.
	 */
	if (port == PORT_A)
		return;

	if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
		     1))
		DRM_ERROR("Timed out waiting for DP idle patterns\n");
}

3748
static void
C
Chris Wilson 已提交
3749
intel_dp_link_down(struct intel_dp *intel_dp)
3750
{
3751
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3752
	struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3753
	enum port port = intel_dig_port->port;
3754
	struct drm_device *dev = intel_dig_port->base.base.dev;
3755
	struct drm_i915_private *dev_priv = dev->dev_private;
C
Chris Wilson 已提交
3756
	uint32_t DP = intel_dp->DP;
3757

3758
	if (WARN_ON(HAS_DDI(dev)))
3759 3760
		return;

3761
	if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3762 3763
		return;

3764
	DRM_DEBUG_KMS("\n");
3765

3766 3767
	if ((IS_GEN7(dev) && port == PORT_A) ||
	    (HAS_PCH_CPT(dev) && port != PORT_A)) {
3768
		DP &= ~DP_LINK_TRAIN_MASK_CPT;
3769
		DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3770
	} else {
3771 3772 3773 3774
		if (IS_CHERRYVIEW(dev))
			DP &= ~DP_LINK_TRAIN_MASK_CHV;
		else
			DP &= ~DP_LINK_TRAIN_MASK;
3775
		DP |= DP_LINK_TRAIN_PAT_IDLE;
3776
	}
3777
	I915_WRITE(intel_dp->output_reg, DP);
3778
	POSTING_READ(intel_dp->output_reg);
3779

3780 3781 3782 3783 3784 3785 3786 3787 3788 3789
	DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
	I915_WRITE(intel_dp->output_reg, DP);
	POSTING_READ(intel_dp->output_reg);

	/*
	 * HW workaround for IBX, we need to move the port
	 * to transcoder A after disabling it to allow the
	 * matching HDMI port to be enabled on transcoder A.
	 */
	if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
3790 3791 3792 3793 3794 3795 3796
		/*
		 * We get CPU/PCH FIFO underruns on the other pipe when
		 * doing the workaround. Sweep them under the rug.
		 */
		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);

3797 3798 3799 3800 3801 3802 3803
		/* always enable with pattern 1 (as per spec) */
		DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
		DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
		I915_WRITE(intel_dp->output_reg, DP);
		POSTING_READ(intel_dp->output_reg);

		DP &= ~DP_PORT_EN;
3804
		I915_WRITE(intel_dp->output_reg, DP);
3805
		POSTING_READ(intel_dp->output_reg);
3806 3807 3808 3809

		intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);
		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3810 3811
	}

3812
	msleep(intel_dp->panel_power_down_delay);
3813 3814

	intel_dp->DP = DP;
3815 3816
}

3817 3818
static bool
intel_dp_get_dpcd(struct intel_dp *intel_dp)
3819
{
R
Rodrigo Vivi 已提交
3820 3821 3822
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
3823
	uint8_t rev;
R
Rodrigo Vivi 已提交
3824

3825 3826
	if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
				    sizeof(intel_dp->dpcd)) < 0)
3827
		return false; /* aux transfer failed */
3828

3829
	DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3830

3831 3832 3833
	if (intel_dp->dpcd[DP_DPCD_REV] == 0)
		return false; /* DPCD not present */

3834 3835
	/* Check if the panel supports PSR */
	memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3836
	if (is_edp(intel_dp)) {
3837 3838 3839
		intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
					intel_dp->psr_dpcd,
					sizeof(intel_dp->psr_dpcd));
R
Rodrigo Vivi 已提交
3840 3841
		if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
			dev_priv->psr.sink_support = true;
3842
			DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
R
Rodrigo Vivi 已提交
3843
		}
3844 3845 3846 3847 3848 3849 3850 3851 3852 3853 3854 3855 3856 3857 3858

		if (INTEL_INFO(dev)->gen >= 9 &&
			(intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
			uint8_t frame_sync_cap;

			dev_priv->psr.sink_support = true;
			intel_dp_dpcd_read_wake(&intel_dp->aux,
					DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
					&frame_sync_cap, 1);
			dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
			/* PSR2 needs frame sync as well */
			dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
			DRM_DEBUG_KMS("PSR2 %s on sink",
				dev_priv->psr.psr2_support ? "supported" : "not supported");
		}
3859 3860
	}

3861
	DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
3862
		      yesno(intel_dp_source_supports_hbr2(intel_dp)),
3863
		      yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
3864

3865 3866 3867 3868 3869
	/* Intermediate frequency support */
	if (is_edp(intel_dp) &&
	    (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] &	DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
	    (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
	    (rev >= 0x03)) { /* eDp v1.4 or higher */
3870
		__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3871 3872
		int i;

3873 3874
		intel_dp_dpcd_read_wake(&intel_dp->aux,
				DP_SUPPORTED_LINK_RATES,
3875 3876
				sink_rates,
				sizeof(sink_rates));
3877

3878 3879
		for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
			int val = le16_to_cpu(sink_rates[i]);
3880 3881 3882 3883

			if (val == 0)
				break;

3884 3885
			/* Value read is in kHz while drm clock is saved in deca-kHz */
			intel_dp->sink_rates[i] = (val * 200) / 10;
3886
		}
3887
		intel_dp->num_sink_rates = i;
3888
	}
3889 3890 3891

	intel_dp_print_rates(intel_dp);

3892 3893 3894 3895 3896 3897 3898
	if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
	      DP_DWN_STRM_PORT_PRESENT))
		return true; /* native DP sink */

	if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
		return true; /* no per-port downstream info */

3899 3900 3901
	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
				    intel_dp->downstream_ports,
				    DP_MAX_DOWNSTREAM_PORTS) < 0)
3902 3903 3904
		return false; /* downstream port status fetch failed */

	return true;
3905 3906
}

3907 3908 3909 3910 3911 3912 3913 3914
static void
intel_dp_probe_oui(struct intel_dp *intel_dp)
{
	u8 buf[3];

	if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
		return;

3915
	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3916 3917 3918
		DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
			      buf[0], buf[1], buf[2]);

3919
	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3920 3921 3922 3923
		DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
			      buf[0], buf[1], buf[2]);
}

3924 3925 3926 3927 3928 3929 3930 3931 3932 3933 3934 3935 3936 3937 3938 3939 3940 3941 3942 3943 3944 3945 3946 3947 3948
static bool
intel_dp_probe_mst(struct intel_dp *intel_dp)
{
	u8 buf[1];

	if (!intel_dp->can_mst)
		return false;

	if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
		return false;

	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
		if (buf[0] & DP_MST_CAP) {
			DRM_DEBUG_KMS("Sink is MST capable\n");
			intel_dp->is_mst = true;
		} else {
			DRM_DEBUG_KMS("Sink is not MST capable\n");
			intel_dp->is_mst = false;
		}
	}

	drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
	return intel_dp->is_mst;
}

3949
static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
3950
{
3951
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3952
	struct drm_device *dev = dig_port->base.base.dev;
3953
	struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
R
Rodrigo Vivi 已提交
3954
	u8 buf;
3955
	int ret = 0;
3956 3957
	int count = 0;
	int attempts = 10;
3958

3959 3960
	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
		DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3961 3962
		ret = -EIO;
		goto out;
3963 3964
	}

3965
	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3966
			       buf & ~DP_TEST_SINK_START) < 0) {
3967
		DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3968 3969 3970
		ret = -EIO;
		goto out;
	}
3971

3972 3973 3974 3975 3976 3977 3978 3979 3980 3981 3982 3983 3984 3985 3986 3987
	do {
		intel_wait_for_vblank(dev, intel_crtc->pipe);

		if (drm_dp_dpcd_readb(&intel_dp->aux,
				      DP_TEST_SINK_MISC, &buf) < 0) {
			ret = -EIO;
			goto out;
		}
		count = buf & DP_TEST_COUNT_MASK;
	} while (--attempts && count);

	if (attempts == 0) {
		DRM_ERROR("TIMEOUT: Sink CRC counter is not zeroed\n");
		ret = -ETIMEDOUT;
	}

3988
	intel_dp->sink_crc.started = false;
3989
 out:
3990
	hsw_enable_ips(intel_crtc);
3991
	return ret;
3992 3993 3994 3995 3996
}

static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3997
	struct drm_device *dev = dig_port->base.base.dev;
3998 3999
	struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
	u8 buf;
4000 4001
	int ret;

4002
	if (intel_dp->sink_crc.started) {
4003 4004 4005 4006
		ret = intel_dp_sink_crc_stop(intel_dp);
		if (ret)
			return ret;
	}
4007 4008 4009 4010 4011 4012 4013

	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
		return -EIO;

	if (!(buf & DP_TEST_CRC_SUPPORTED))
		return -ENOTTY;

4014 4015
	intel_dp->sink_crc.last_count = buf & DP_TEST_COUNT_MASK;

4016 4017 4018 4019
	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
		return -EIO;

	hsw_disable_ips(intel_crtc);
4020

4021
	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
4022 4023 4024
			       buf | DP_TEST_SINK_START) < 0) {
		hsw_enable_ips(intel_crtc);
		return -EIO;
4025 4026
	}

4027
	intel_wait_for_vblank(dev, intel_crtc->pipe);
4028
	intel_dp->sink_crc.started = true;
4029 4030 4031 4032 4033 4034 4035 4036 4037
	return 0;
}

int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
	struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
	u8 buf;
4038
	int count, ret;
4039
	int attempts = 6;
4040
	bool old_equal_new;
4041 4042 4043 4044 4045

	ret = intel_dp_sink_crc_start(intel_dp);
	if (ret)
		return ret;

R
Rodrigo Vivi 已提交
4046
	do {
4047 4048
		intel_wait_for_vblank(dev, intel_crtc->pipe);

4049
		if (drm_dp_dpcd_readb(&intel_dp->aux,
4050 4051
				      DP_TEST_SINK_MISC, &buf) < 0) {
			ret = -EIO;
4052
			goto stop;
4053
		}
4054
		count = buf & DP_TEST_COUNT_MASK;
4055

4056 4057 4058 4059 4060 4061 4062 4063 4064 4065 4066
		/*
		 * Count might be reset during the loop. In this case
		 * last known count needs to be reset as well.
		 */
		if (count == 0)
			intel_dp->sink_crc.last_count = 0;

		if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
			ret = -EIO;
			goto stop;
		}
4067 4068 4069 4070 4071 4072

		old_equal_new = (count == intel_dp->sink_crc.last_count &&
				 !memcmp(intel_dp->sink_crc.last_crc, crc,
					 6 * sizeof(u8)));

	} while (--attempts && (count == 0 || old_equal_new));
4073 4074 4075

	intel_dp->sink_crc.last_count = buf & DP_TEST_COUNT_MASK;
	memcpy(intel_dp->sink_crc.last_crc, crc, 6 * sizeof(u8));
R
Rodrigo Vivi 已提交
4076 4077

	if (attempts == 0) {
4078 4079 4080 4081 4082 4083 4084
		if (old_equal_new) {
			DRM_DEBUG_KMS("Unreliable Sink CRC counter: Current returned CRC is identical to the previous one\n");
		} else {
			DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
			ret = -ETIMEDOUT;
			goto stop;
		}
R
Rodrigo Vivi 已提交
4085
	}
4086

4087
stop:
4088
	intel_dp_sink_crc_stop(intel_dp);
4089
	return ret;
4090 4091
}

4092 4093 4094
static bool
intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
{
4095 4096 4097
	return intel_dp_dpcd_read_wake(&intel_dp->aux,
				       DP_DEVICE_SERVICE_IRQ_VECTOR,
				       sink_irq_vector, 1) == 1;
4098 4099
}

4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 4110 4111 4112 4113
static bool
intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
{
	int ret;

	ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
					     DP_SINK_COUNT_ESI,
					     sink_irq_vector, 14);
	if (ret != 14)
		return false;

	return true;
}

4114 4115 4116 4117 4118 4119 4120 4121 4122 4123 4124 4125 4126
static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
{
	uint8_t test_result = DP_TEST_ACK;
	return test_result;
}

static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
{
	uint8_t test_result = DP_TEST_NAK;
	return test_result;
}

static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4127
{
4128
	uint8_t test_result = DP_TEST_NAK;
4129 4130 4131 4132
	struct intel_connector *intel_connector = intel_dp->attached_connector;
	struct drm_connector *connector = &intel_connector->base;

	if (intel_connector->detect_edid == NULL ||
4133
	    connector->edid_corrupt ||
4134 4135 4136 4137 4138 4139 4140 4141 4142 4143 4144 4145 4146 4147 4148
	    intel_dp->aux.i2c_defer_count > 6) {
		/* Check EDID read for NACKs, DEFERs and corruption
		 * (DP CTS 1.2 Core r1.1)
		 *    4.2.2.4 : Failed EDID read, I2C_NAK
		 *    4.2.2.5 : Failed EDID read, I2C_DEFER
		 *    4.2.2.6 : EDID corruption detected
		 * Use failsafe mode for all cases
		 */
		if (intel_dp->aux.i2c_nack_count > 0 ||
			intel_dp->aux.i2c_defer_count > 0)
			DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
				      intel_dp->aux.i2c_nack_count,
				      intel_dp->aux.i2c_defer_count);
		intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
	} else {
4149 4150 4151 4152 4153 4154 4155
		struct edid *block = intel_connector->detect_edid;

		/* We have to write the checksum
		 * of the last block read
		 */
		block += intel_connector->detect_edid->extensions;

4156 4157
		if (!drm_dp_dpcd_write(&intel_dp->aux,
					DP_TEST_EDID_CHECKSUM,
4158
					&block->checksum,
D
Dan Carpenter 已提交
4159
					1))
4160 4161 4162 4163 4164 4165 4166 4167 4168
			DRM_DEBUG_KMS("Failed to write EDID checksum\n");

		test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
		intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
	}

	/* Set test active flag here so userspace doesn't interrupt things */
	intel_dp->compliance_test_active = 1;

4169 4170 4171 4172
	return test_result;
}

static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4173
{
4174 4175 4176 4177 4178 4179 4180 4181 4182 4183 4184 4185 4186 4187 4188 4189 4190 4191 4192 4193 4194 4195 4196 4197 4198 4199 4200 4201 4202 4203 4204 4205 4206 4207 4208 4209 4210 4211 4212 4213 4214 4215 4216 4217 4218 4219 4220 4221
	uint8_t test_result = DP_TEST_NAK;
	return test_result;
}

static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
{
	uint8_t response = DP_TEST_NAK;
	uint8_t rxdata = 0;
	int status = 0;

	status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
	if (status <= 0) {
		DRM_DEBUG_KMS("Could not read test request from sink\n");
		goto update_status;
	}

	switch (rxdata) {
	case DP_TEST_LINK_TRAINING:
		DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
		intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
		response = intel_dp_autotest_link_training(intel_dp);
		break;
	case DP_TEST_LINK_VIDEO_PATTERN:
		DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
		intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
		response = intel_dp_autotest_video_pattern(intel_dp);
		break;
	case DP_TEST_LINK_EDID_READ:
		DRM_DEBUG_KMS("EDID test requested\n");
		intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
		response = intel_dp_autotest_edid(intel_dp);
		break;
	case DP_TEST_LINK_PHY_TEST_PATTERN:
		DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
		intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
		response = intel_dp_autotest_phy_pattern(intel_dp);
		break;
	default:
		DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
		break;
	}

update_status:
	status = drm_dp_dpcd_write(&intel_dp->aux,
				   DP_TEST_RESPONSE,
				   &response, 1);
	if (status <= 0)
		DRM_DEBUG_KMS("Could not write test response to sink\n");
4222 4223
}

4224 4225 4226 4227 4228 4229 4230 4231 4232 4233 4234 4235 4236 4237 4238
static int
intel_dp_check_mst_status(struct intel_dp *intel_dp)
{
	bool bret;

	if (intel_dp->is_mst) {
		u8 esi[16] = { 0 };
		int ret = 0;
		int retry;
		bool handled;
		bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
go_again:
		if (bret == true) {

			/* check link status - esi[10] = 0x200c */
4239
			if (intel_dp->active_mst_links &&
4240
			    !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4241 4242 4243 4244 4245
				DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
				intel_dp_start_link_train(intel_dp);
				intel_dp_stop_link_train(intel_dp);
			}

4246
			DRM_DEBUG_KMS("got esi %3ph\n", esi);
4247 4248 4249 4250 4251 4252 4253 4254 4255 4256 4257 4258 4259 4260 4261
			ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);

			if (handled) {
				for (retry = 0; retry < 3; retry++) {
					int wret;
					wret = drm_dp_dpcd_write(&intel_dp->aux,
								 DP_SINK_COUNT_ESI+1,
								 &esi[1], 3);
					if (wret == 3) {
						break;
					}
				}

				bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
				if (bret == true) {
4262
					DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4263 4264 4265 4266 4267 4268 4269 4270 4271 4272 4273 4274 4275 4276 4277 4278 4279 4280
					goto go_again;
				}
			} else
				ret = 0;

			return ret;
		} else {
			struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
			DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
			intel_dp->is_mst = false;
			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
			/* send a hotplug event */
			drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
		}
	}
	return -EINVAL;
}

4281 4282 4283 4284 4285 4286 4287 4288
/*
 * According to DP spec
 * 5.1.2:
 *  1. Read DPCD
 *  2. Configure link according to Receiver Capabilities
 *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
 *  4. Check link status on receipt of hot-plug interrupt
 */
4289
static void
C
Chris Wilson 已提交
4290
intel_dp_check_link_status(struct intel_dp *intel_dp)
4291
{
4292
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
4293
	struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4294
	u8 sink_irq_vector;
4295
	u8 link_status[DP_LINK_STATUS_SIZE];
4296

4297 4298
	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));

4299 4300 4301 4302 4303 4304 4305 4306
	/*
	 * Clearing compliance test variables to allow capturing
	 * of values for next automated test request.
	 */
	intel_dp->compliance_test_active = 0;
	intel_dp->compliance_test_type = 0;
	intel_dp->compliance_test_data = 0;

4307
	if (!intel_encoder->base.crtc)
4308 4309
		return;

4310 4311 4312
	if (!to_intel_crtc(intel_encoder->base.crtc)->active)
		return;

4313
	/* Try to read receiver status if the link appears to be up */
4314
	if (!intel_dp_get_link_status(intel_dp, link_status)) {
4315 4316 4317
		return;
	}

4318
	/* Now read the DPCD to see if it's actually running */
4319
	if (!intel_dp_get_dpcd(intel_dp)) {
4320 4321 4322
		return;
	}

4323 4324 4325 4326
	/* Try to read the source of the interrupt */
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
		/* Clear interrupt source */
4327 4328 4329
		drm_dp_dpcd_writeb(&intel_dp->aux,
				   DP_DEVICE_SERVICE_IRQ_VECTOR,
				   sink_irq_vector);
4330 4331

		if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4332
			DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
4333 4334 4335 4336
		if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
			DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
	}

4337 4338 4339
	/* if link training is requested we should perform it always */
	if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) ||
		(!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
4340
		DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4341
			      intel_encoder->base.name);
4342
		intel_dp_start_link_train(intel_dp);
4343
		intel_dp_stop_link_train(intel_dp);
4344
	}
4345 4346
}

4347
/* XXX this is probably wrong for multiple downstream ports */
4348
static enum drm_connector_status
4349
intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4350
{
4351 4352 4353 4354 4355 4356 4357 4358
	uint8_t *dpcd = intel_dp->dpcd;
	uint8_t type;

	if (!intel_dp_get_dpcd(intel_dp))
		return connector_status_disconnected;

	/* if there's no downstream port, we're done */
	if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
4359
		return connector_status_connected;
4360 4361

	/* If we're HPD-aware, SINK_COUNT changes dynamically */
4362 4363
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4364
		uint8_t reg;
4365 4366 4367

		if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
					    &reg, 1) < 0)
4368
			return connector_status_unknown;
4369

4370 4371
		return DP_GET_SINK_COUNT(reg) ? connector_status_connected
					      : connector_status_disconnected;
4372 4373 4374
	}

	/* If no HPD, poke DDC gently */
4375
	if (drm_probe_ddc(&intel_dp->aux.ddc))
4376
		return connector_status_connected;
4377 4378

	/* Well we tried, say unknown for unreliable port types */
4379 4380 4381 4382 4383 4384 4385 4386 4387 4388 4389 4390
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
		type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
		if (type == DP_DS_PORT_TYPE_VGA ||
		    type == DP_DS_PORT_TYPE_NON_EDID)
			return connector_status_unknown;
	} else {
		type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
			DP_DWN_STRM_PORT_TYPE_MASK;
		if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
		    type == DP_DWN_STRM_PORT_TYPE_OTHER)
			return connector_status_unknown;
	}
4391 4392 4393

	/* Anything else is out of spec, warn and ignore */
	DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4394
	return connector_status_disconnected;
4395 4396
}

4397 4398 4399 4400 4401 4402 4403 4404 4405 4406 4407 4408 4409
static enum drm_connector_status
edp_detect(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	enum drm_connector_status status;

	status = intel_panel_detect(dev);
	if (status == connector_status_unknown)
		status = connector_status_connected;

	return status;
}

4410 4411
static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
				       struct intel_digital_port *port)
4412
{
4413
	u32 bit;
4414

4415 4416 4417 4418 4419 4420 4421 4422 4423 4424 4425 4426 4427 4428 4429 4430 4431 4432 4433 4434 4435 4436 4437 4438 4439 4440 4441 4442 4443 4444 4445 4446 4447 4448 4449 4450 4451
	switch (port->port) {
	case PORT_A:
		return true;
	case PORT_B:
		bit = SDE_PORTB_HOTPLUG;
		break;
	case PORT_C:
		bit = SDE_PORTC_HOTPLUG;
		break;
	case PORT_D:
		bit = SDE_PORTD_HOTPLUG;
		break;
	default:
		MISSING_CASE(port->port);
		return false;
	}

	return I915_READ(SDEISR) & bit;
}

static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
				       struct intel_digital_port *port)
{
	u32 bit;

	switch (port->port) {
	case PORT_A:
		return true;
	case PORT_B:
		bit = SDE_PORTB_HOTPLUG_CPT;
		break;
	case PORT_C:
		bit = SDE_PORTC_HOTPLUG_CPT;
		break;
	case PORT_D:
		bit = SDE_PORTD_HOTPLUG_CPT;
		break;
4452 4453 4454
	case PORT_E:
		bit = SDE_PORTE_HOTPLUG_SPT;
		break;
4455 4456 4457
	default:
		MISSING_CASE(port->port);
		return false;
4458
	}
4459

4460
	return I915_READ(SDEISR) & bit;
4461 4462
}

4463
static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
4464
				       struct intel_digital_port *port)
4465
{
4466
	u32 bit;
4467

4468 4469 4470 4471 4472 4473 4474 4475 4476 4477 4478 4479 4480 4481 4482 4483 4484 4485 4486 4487 4488 4489 4490 4491 4492 4493 4494 4495 4496 4497 4498 4499 4500 4501 4502 4503
	switch (port->port) {
	case PORT_B:
		bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
		break;
	case PORT_C:
		bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
		break;
	case PORT_D:
		bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
		break;
	default:
		MISSING_CASE(port->port);
		return false;
	}

	return I915_READ(PORT_HOTPLUG_STAT) & bit;
}

static bool vlv_digital_port_connected(struct drm_i915_private *dev_priv,
				       struct intel_digital_port *port)
{
	u32 bit;

	switch (port->port) {
	case PORT_B:
		bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
		break;
	case PORT_C:
		bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
		break;
	case PORT_D:
		bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
		break;
	default:
		MISSING_CASE(port->port);
		return false;
4504 4505
	}

4506
	return I915_READ(PORT_HOTPLUG_STAT) & bit;
4507 4508
}

4509
static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
4510
				       struct intel_digital_port *intel_dig_port)
4511
{
4512 4513
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	enum port port;
4514 4515
	u32 bit;

4516 4517
	intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
	switch (port) {
4518 4519 4520 4521 4522 4523 4524 4525 4526 4527
	case PORT_A:
		bit = BXT_DE_PORT_HP_DDIA;
		break;
	case PORT_B:
		bit = BXT_DE_PORT_HP_DDIB;
		break;
	case PORT_C:
		bit = BXT_DE_PORT_HP_DDIC;
		break;
	default:
4528
		MISSING_CASE(port);
4529 4530 4531 4532 4533 4534
		return false;
	}

	return I915_READ(GEN8_DE_PORT_ISR) & bit;
}

4535 4536 4537 4538 4539 4540 4541
/*
 * intel_digital_port_connected - is the specified port connected?
 * @dev_priv: i915 private structure
 * @port: the port to test
 *
 * Return %true if @port is connected, %false otherwise.
 */
4542
bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
4543 4544
					 struct intel_digital_port *port)
{
4545
	if (HAS_PCH_IBX(dev_priv))
4546
		return ibx_digital_port_connected(dev_priv, port);
4547 4548
	if (HAS_PCH_SPLIT(dev_priv))
		return cpt_digital_port_connected(dev_priv, port);
4549 4550
	else if (IS_BROXTON(dev_priv))
		return bxt_digital_port_connected(dev_priv, port);
4551 4552
	else if (IS_VALLEYVIEW(dev_priv))
		return vlv_digital_port_connected(dev_priv, port);
4553 4554 4555 4556
	else
		return g4x_digital_port_connected(dev_priv, port);
}

4557 4558 4559 4560 4561 4562 4563
static enum drm_connector_status
ironlake_dp_detect(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

4564
	if (!intel_digital_port_connected(dev_priv, intel_dig_port))
4565 4566 4567 4568 4569
		return connector_status_disconnected;

	return intel_dp_detect_dpcd(intel_dp);
}

4570 4571 4572 4573 4574 4575 4576 4577 4578 4579 4580 4581 4582 4583 4584 4585
static enum drm_connector_status
g4x_dp_detect(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	/* Can't disconnect eDP, but you can close the lid... */
	if (is_edp(intel_dp)) {
		enum drm_connector_status status;

		status = intel_panel_detect(dev);
		if (status == connector_status_unknown)
			status = connector_status_connected;
		return status;
	}

4586
	if (!intel_digital_port_connected(dev->dev_private, intel_dig_port))
4587 4588
		return connector_status_disconnected;

4589
	return intel_dp_detect_dpcd(intel_dp);
Z
Zhenyu Wang 已提交
4590 4591
}

4592
static struct edid *
4593
intel_dp_get_edid(struct intel_dp *intel_dp)
4594
{
4595
	struct intel_connector *intel_connector = intel_dp->attached_connector;
4596

4597 4598 4599 4600
	/* use cached edid if we have one */
	if (intel_connector->edid) {
		/* invalid edid */
		if (IS_ERR(intel_connector->edid))
4601 4602
			return NULL;

J
Jani Nikula 已提交
4603
		return drm_edid_duplicate(intel_connector->edid);
4604 4605 4606 4607
	} else
		return drm_get_edid(&intel_connector->base,
				    &intel_dp->aux.ddc);
}
4608

4609 4610 4611 4612 4613
static void
intel_dp_set_edid(struct intel_dp *intel_dp)
{
	struct intel_connector *intel_connector = intel_dp->attached_connector;
	struct edid *edid;
4614

4615 4616 4617 4618 4619 4620 4621
	edid = intel_dp_get_edid(intel_dp);
	intel_connector->detect_edid = edid;

	if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
		intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
	else
		intel_dp->has_audio = drm_detect_monitor_audio(edid);
4622 4623
}

4624 4625
static void
intel_dp_unset_edid(struct intel_dp *intel_dp)
4626
{
4627
	struct intel_connector *intel_connector = intel_dp->attached_connector;
4628

4629 4630
	kfree(intel_connector->detect_edid);
	intel_connector->detect_edid = NULL;
4631

4632 4633
	intel_dp->has_audio = false;
}
4634

Z
Zhenyu Wang 已提交
4635 4636 4637 4638
static enum drm_connector_status
intel_dp_detect(struct drm_connector *connector, bool force)
{
	struct intel_dp *intel_dp = intel_attached_dp(connector);
4639 4640
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
4641
	struct drm_device *dev = connector->dev;
Z
Zhenyu Wang 已提交
4642
	enum drm_connector_status status;
4643
	enum intel_display_power_domain power_domain;
4644
	bool ret;
4645
	u8 sink_irq_vector;
Z
Zhenyu Wang 已提交
4646

4647
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4648
		      connector->base.id, connector->name);
4649
	intel_dp_unset_edid(intel_dp);
4650

4651 4652 4653 4654
	if (intel_dp->is_mst) {
		/* MST devices are disconnected from a monitor POV */
		if (intel_encoder->type != INTEL_OUTPUT_EDP)
			intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4655
		return connector_status_disconnected;
4656 4657
	}

4658 4659
	power_domain = intel_display_port_aux_power_domain(intel_encoder);
	intel_display_power_get(to_i915(dev), power_domain);
Z
Zhenyu Wang 已提交
4660

4661 4662 4663 4664
	/* Can't disconnect eDP, but you can close the lid... */
	if (is_edp(intel_dp))
		status = edp_detect(intel_dp);
	else if (HAS_PCH_SPLIT(dev))
Z
Zhenyu Wang 已提交
4665 4666 4667
		status = ironlake_dp_detect(intel_dp);
	else
		status = g4x_dp_detect(intel_dp);
4668 4669 4670 4671 4672
	if (status != connector_status_connected) {
		intel_dp->compliance_test_active = 0;
		intel_dp->compliance_test_type = 0;
		intel_dp->compliance_test_data = 0;

4673
		goto out;
4674
	}
Z
Zhenyu Wang 已提交
4675

4676 4677
	intel_dp_probe_oui(intel_dp);

4678 4679 4680 4681 4682 4683 4684 4685 4686 4687
	ret = intel_dp_probe_mst(intel_dp);
	if (ret) {
		/* if we are in MST mode then this connector
		   won't appear connected or have anything with EDID on it */
		if (intel_encoder->type != INTEL_OUTPUT_EDP)
			intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
		status = connector_status_disconnected;
		goto out;
	}

4688 4689 4690 4691 4692 4693 4694 4695
	/*
	 * Clearing NACK and defer counts to get their exact values
	 * while reading EDID which are required by Compliance tests
	 * 4.2.2.4 and 4.2.2.5
	 */
	intel_dp->aux.i2c_nack_count = 0;
	intel_dp->aux.i2c_defer_count = 0;

4696
	intel_dp_set_edid(intel_dp);
Z
Zhenyu Wang 已提交
4697

4698 4699
	if (intel_encoder->type != INTEL_OUTPUT_EDP)
		intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4700 4701
	status = connector_status_connected;

4702 4703 4704 4705 4706 4707 4708 4709 4710 4711 4712 4713 4714 4715
	/* Try to read the source of the interrupt */
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
		/* Clear interrupt source */
		drm_dp_dpcd_writeb(&intel_dp->aux,
				   DP_DEVICE_SERVICE_IRQ_VECTOR,
				   sink_irq_vector);

		if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
			intel_dp_handle_test_request(intel_dp);
		if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
			DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
	}

4716
out:
4717
	intel_display_power_put(to_i915(dev), power_domain);
4718
	return status;
4719 4720
}

4721 4722
static void
intel_dp_force(struct drm_connector *connector)
4723
{
4724
	struct intel_dp *intel_dp = intel_attached_dp(connector);
4725
	struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4726
	struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4727
	enum intel_display_power_domain power_domain;
4728

4729 4730 4731
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
		      connector->base.id, connector->name);
	intel_dp_unset_edid(intel_dp);
4732

4733 4734
	if (connector->status != connector_status_connected)
		return;
4735

4736 4737
	power_domain = intel_display_port_aux_power_domain(intel_encoder);
	intel_display_power_get(dev_priv, power_domain);
4738 4739 4740

	intel_dp_set_edid(intel_dp);

4741
	intel_display_power_put(dev_priv, power_domain);
4742 4743 4744 4745 4746 4747 4748 4749 4750 4751 4752 4753 4754 4755 4756 4757

	if (intel_encoder->type != INTEL_OUTPUT_EDP)
		intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
}

static int intel_dp_get_modes(struct drm_connector *connector)
{
	struct intel_connector *intel_connector = to_intel_connector(connector);
	struct edid *edid;

	edid = intel_connector->detect_edid;
	if (edid) {
		int ret = intel_connector_update_modes(connector, edid);
		if (ret)
			return ret;
	}
4758

4759
	/* if eDP has no EDID, fall back to fixed mode */
4760 4761
	if (is_edp(intel_attached_dp(connector)) &&
	    intel_connector->panel.fixed_mode) {
4762
		struct drm_display_mode *mode;
4763 4764

		mode = drm_mode_duplicate(connector->dev,
4765
					  intel_connector->panel.fixed_mode);
4766
		if (mode) {
4767 4768 4769 4770
			drm_mode_probed_add(connector, mode);
			return 1;
		}
	}
4771

4772
	return 0;
4773 4774
}

4775 4776 4777 4778
static bool
intel_dp_detect_audio(struct drm_connector *connector)
{
	bool has_audio = false;
4779
	struct edid *edid;
4780

4781 4782
	edid = to_intel_connector(connector)->detect_edid;
	if (edid)
4783
		has_audio = drm_detect_monitor_audio(edid);
4784

4785 4786 4787
	return has_audio;
}

4788 4789 4790 4791 4792
static int
intel_dp_set_property(struct drm_connector *connector,
		      struct drm_property *property,
		      uint64_t val)
{
4793
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
4794
	struct intel_connector *intel_connector = to_intel_connector(connector);
4795 4796
	struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4797 4798
	int ret;

4799
	ret = drm_object_property_set_value(&connector->base, property, val);
4800 4801 4802
	if (ret)
		return ret;

4803
	if (property == dev_priv->force_audio_property) {
4804 4805 4806 4807
		int i = val;
		bool has_audio;

		if (i == intel_dp->force_audio)
4808 4809
			return 0;

4810
		intel_dp->force_audio = i;
4811

4812
		if (i == HDMI_AUDIO_AUTO)
4813 4814
			has_audio = intel_dp_detect_audio(connector);
		else
4815
			has_audio = (i == HDMI_AUDIO_ON);
4816 4817

		if (has_audio == intel_dp->has_audio)
4818 4819
			return 0;

4820
		intel_dp->has_audio = has_audio;
4821 4822 4823
		goto done;
	}

4824
	if (property == dev_priv->broadcast_rgb_property) {
4825
		bool old_auto = intel_dp->color_range_auto;
4826
		bool old_range = intel_dp->limited_color_range;
4827

4828 4829 4830 4831 4832 4833
		switch (val) {
		case INTEL_BROADCAST_RGB_AUTO:
			intel_dp->color_range_auto = true;
			break;
		case INTEL_BROADCAST_RGB_FULL:
			intel_dp->color_range_auto = false;
4834
			intel_dp->limited_color_range = false;
4835 4836 4837
			break;
		case INTEL_BROADCAST_RGB_LIMITED:
			intel_dp->color_range_auto = false;
4838
			intel_dp->limited_color_range = true;
4839 4840 4841 4842
			break;
		default:
			return -EINVAL;
		}
4843 4844

		if (old_auto == intel_dp->color_range_auto &&
4845
		    old_range == intel_dp->limited_color_range)
4846 4847
			return 0;

4848 4849 4850
		goto done;
	}

4851 4852 4853 4854 4855 4856 4857 4858 4859 4860 4861 4862 4863 4864 4865 4866
	if (is_edp(intel_dp) &&
	    property == connector->dev->mode_config.scaling_mode_property) {
		if (val == DRM_MODE_SCALE_NONE) {
			DRM_DEBUG_KMS("no scaling not supported\n");
			return -EINVAL;
		}

		if (intel_connector->panel.fitting_mode == val) {
			/* the eDP scaling property is not changed */
			return 0;
		}
		intel_connector->panel.fitting_mode = val;

		goto done;
	}

4867 4868 4869
	return -EINVAL;

done:
4870 4871
	if (intel_encoder->base.crtc)
		intel_crtc_restore_mode(intel_encoder->base.crtc);
4872 4873 4874 4875

	return 0;
}

4876
static void
4877
intel_dp_connector_destroy(struct drm_connector *connector)
4878
{
4879
	struct intel_connector *intel_connector = to_intel_connector(connector);
4880

4881
	kfree(intel_connector->detect_edid);
4882

4883 4884 4885
	if (!IS_ERR_OR_NULL(intel_connector->edid))
		kfree(intel_connector->edid);

4886 4887 4888
	/* Can't call is_edp() since the encoder may have been destroyed
	 * already. */
	if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4889
		intel_panel_fini(&intel_connector->panel);
4890

4891
	drm_connector_cleanup(connector);
4892
	kfree(connector);
4893 4894
}

P
Paulo Zanoni 已提交
4895
void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4896
{
4897 4898
	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
	struct intel_dp *intel_dp = &intel_dig_port->dp;
4899

4900
	intel_dp_aux_fini(intel_dp);
4901
	intel_dp_mst_encoder_cleanup(intel_dig_port);
4902 4903
	if (is_edp(intel_dp)) {
		cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4904 4905 4906 4907
		/*
		 * vdd might still be enabled do to the delayed vdd off.
		 * Make sure vdd is actually turned off here.
		 */
4908
		pps_lock(intel_dp);
4909
		edp_panel_vdd_off_sync(intel_dp);
4910 4911
		pps_unlock(intel_dp);

4912 4913 4914 4915
		if (intel_dp->edp_notifier.notifier_call) {
			unregister_reboot_notifier(&intel_dp->edp_notifier);
			intel_dp->edp_notifier.notifier_call = NULL;
		}
4916
	}
4917
	drm_encoder_cleanup(encoder);
4918
	kfree(intel_dig_port);
4919 4920
}

4921 4922 4923 4924 4925 4926 4927
static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);

	if (!is_edp(intel_dp))
		return;

4928 4929 4930 4931
	/*
	 * vdd might still be enabled do to the delayed vdd off.
	 * Make sure vdd is actually turned off here.
	 */
4932
	cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4933
	pps_lock(intel_dp);
4934
	edp_panel_vdd_off_sync(intel_dp);
4935
	pps_unlock(intel_dp);
4936 4937
}

4938 4939 4940 4941 4942 4943 4944 4945 4946 4947 4948 4949 4950 4951 4952 4953 4954 4955 4956
static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum intel_display_power_domain power_domain;

	lockdep_assert_held(&dev_priv->pps_mutex);

	if (!edp_have_panel_vdd(intel_dp))
		return;

	/*
	 * The VDD bit needs a power domain reference, so if the bit is
	 * already enabled when we boot or resume, grab this reference and
	 * schedule a vdd off, so we don't hold on to the reference
	 * indefinitely.
	 */
	DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4957
	power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base);
4958 4959 4960 4961 4962
	intel_display_power_get(dev_priv, power_domain);

	edp_panel_vdd_schedule_off(intel_dp);
}

4963 4964
static void intel_dp_encoder_reset(struct drm_encoder *encoder)
{
4965 4966 4967 4968 4969 4970 4971 4972 4973 4974 4975 4976 4977 4978 4979 4980 4981 4982 4983
	struct intel_dp *intel_dp;

	if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
		return;

	intel_dp = enc_to_intel_dp(encoder);

	pps_lock(intel_dp);

	/*
	 * Read out the current power sequencer assignment,
	 * in case the BIOS did something with it.
	 */
	if (IS_VALLEYVIEW(encoder->dev))
		vlv_initial_power_sequencer_setup(intel_dp);

	intel_edp_panel_vdd_sanitize(intel_dp);

	pps_unlock(intel_dp);
4984 4985
}

4986
static const struct drm_connector_funcs intel_dp_connector_funcs = {
4987
	.dpms = drm_atomic_helper_connector_dpms,
4988
	.detect = intel_dp_detect,
4989
	.force = intel_dp_force,
4990
	.fill_modes = drm_helper_probe_single_connector_modes,
4991
	.set_property = intel_dp_set_property,
4992
	.atomic_get_property = intel_connector_atomic_get_property,
4993
	.destroy = intel_dp_connector_destroy,
4994
	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4995
	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
4996 4997 4998 4999 5000
};

static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
	.get_modes = intel_dp_get_modes,
	.mode_valid = intel_dp_mode_valid,
5001
	.best_encoder = intel_best_encoder,
5002 5003 5004
};

static const struct drm_encoder_funcs intel_dp_enc_funcs = {
5005
	.reset = intel_dp_encoder_reset,
5006
	.destroy = intel_dp_encoder_destroy,
5007 5008
};

5009
enum irqreturn
5010 5011 5012
intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
{
	struct intel_dp *intel_dp = &intel_dig_port->dp;
5013
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
5014 5015
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
5016
	enum intel_display_power_domain power_domain;
5017
	enum irqreturn ret = IRQ_NONE;
5018

5019 5020
	if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
		intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
5021

5022 5023 5024 5025 5026 5027 5028 5029 5030
	if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
		/*
		 * vdd off can generate a long pulse on eDP which
		 * would require vdd on to handle it, and thus we
		 * would end up in an endless cycle of
		 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
		 */
		DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
			      port_name(intel_dig_port->port));
5031
		return IRQ_HANDLED;
5032 5033
	}

5034 5035
	DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
		      port_name(intel_dig_port->port),
5036
		      long_hpd ? "long" : "short");
5037

5038
	power_domain = intel_display_port_aux_power_domain(intel_encoder);
5039 5040
	intel_display_power_get(dev_priv, power_domain);

5041
	if (long_hpd) {
5042 5043
		/* indicate that we need to restart link training */
		intel_dp->train_set_valid = false;
5044

5045 5046
		if (!intel_digital_port_connected(dev_priv, intel_dig_port))
			goto mst_fail;
5047 5048 5049 5050 5051 5052 5053

		if (!intel_dp_get_dpcd(intel_dp)) {
			goto mst_fail;
		}

		intel_dp_probe_oui(intel_dp);

5054 5055 5056 5057
		if (!intel_dp_probe_mst(intel_dp)) {
			drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
			intel_dp_check_link_status(intel_dp);
			drm_modeset_unlock(&dev->mode_config.connection_mutex);
5058
			goto mst_fail;
5059
		}
5060 5061
	} else {
		if (intel_dp->is_mst) {
5062
			if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
5063 5064 5065 5066
				goto mst_fail;
		}

		if (!intel_dp->is_mst) {
5067
			drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
5068
			intel_dp_check_link_status(intel_dp);
5069
			drm_modeset_unlock(&dev->mode_config.connection_mutex);
5070 5071
		}
	}
5072 5073 5074

	ret = IRQ_HANDLED;

5075
	goto put_power;
5076 5077 5078 5079 5080 5081 5082
mst_fail:
	/* if we were in MST mode, and device is not there get out of MST mode */
	if (intel_dp->is_mst) {
		DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
		intel_dp->is_mst = false;
		drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
	}
5083 5084 5085 5086
put_power:
	intel_display_power_put(dev_priv, power_domain);

	return ret;
5087 5088
}

5089 5090
/* Return which DP Port should be selected for Transcoder DP control */
int
5091
intel_trans_dp_port_sel(struct drm_crtc *crtc)
5092 5093
{
	struct drm_device *dev = crtc->dev;
5094 5095
	struct intel_encoder *intel_encoder;
	struct intel_dp *intel_dp;
5096

5097 5098
	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		intel_dp = enc_to_intel_dp(&intel_encoder->base);
5099

5100 5101
		if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
		    intel_encoder->type == INTEL_OUTPUT_EDP)
C
Chris Wilson 已提交
5102
			return intel_dp->output_reg;
5103
	}
C
Chris Wilson 已提交
5104

5105 5106 5107
	return -1;
}

5108
/* check the VBT to see whether the eDP is on another port */
5109
bool intel_dp_is_edp(struct drm_device *dev, enum port port)
5110 5111
{
	struct drm_i915_private *dev_priv = dev->dev_private;
5112
	union child_device_config *p_child;
5113
	int i;
5114
	static const short port_mapping[] = {
5115 5116 5117 5118
		[PORT_B] = DVO_PORT_DPB,
		[PORT_C] = DVO_PORT_DPC,
		[PORT_D] = DVO_PORT_DPD,
		[PORT_E] = DVO_PORT_DPE,
5119
	};
5120

5121 5122 5123 5124 5125 5126 5127
	/*
	 * eDP not supported on g4x. so bail out early just
	 * for a bit extra safety in case the VBT is bonkers.
	 */
	if (INTEL_INFO(dev)->gen < 5)
		return false;

5128 5129 5130
	if (port == PORT_A)
		return true;

5131
	if (!dev_priv->vbt.child_dev_num)
5132 5133
		return false;

5134 5135
	for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
		p_child = dev_priv->vbt.child_dev + i;
5136

5137
		if (p_child->common.dvo_port == port_mapping[port] &&
5138 5139
		    (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
		    (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
5140 5141 5142 5143 5144
			return true;
	}
	return false;
}

5145
void
5146 5147
intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
{
5148 5149
	struct intel_connector *intel_connector = to_intel_connector(connector);

5150
	intel_attach_force_audio_property(connector);
5151
	intel_attach_broadcast_rgb_property(connector);
5152
	intel_dp->color_range_auto = true;
5153 5154 5155

	if (is_edp(intel_dp)) {
		drm_mode_create_scaling_mode_property(connector->dev);
5156 5157
		drm_object_attach_property(
			&connector->base,
5158
			connector->dev->mode_config.scaling_mode_property,
5159 5160
			DRM_MODE_SCALE_ASPECT);
		intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
5161
	}
5162 5163
}

5164 5165 5166 5167 5168 5169 5170
static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
{
	intel_dp->last_power_cycle = jiffies;
	intel_dp->last_power_on = jiffies;
	intel_dp->last_backlight_off = jiffies;
}

5171 5172
static void
intel_dp_init_panel_power_sequencer(struct drm_device *dev,
5173
				    struct intel_dp *intel_dp)
5174 5175
{
	struct drm_i915_private *dev_priv = dev->dev_private;
5176 5177
	struct edp_power_seq cur, vbt, spec,
		*final = &intel_dp->pps_delays;
5178 5179
	u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
	int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg = 0;
5180

V
Ville Syrjälä 已提交
5181 5182
	lockdep_assert_held(&dev_priv->pps_mutex);

5183 5184 5185 5186
	/* already initialized? */
	if (final->t11_t12 != 0)
		return;

5187 5188 5189 5190 5191 5192 5193 5194 5195 5196
	if (IS_BROXTON(dev)) {
		/*
		 * TODO: BXT has 2 sets of PPS registers.
		 * Correct Register for Broxton need to be identified
		 * using VBT. hardcoding for now
		 */
		pp_ctrl_reg = BXT_PP_CONTROL(0);
		pp_on_reg = BXT_PP_ON_DELAYS(0);
		pp_off_reg = BXT_PP_OFF_DELAYS(0);
	} else if (HAS_PCH_SPLIT(dev)) {
5197
		pp_ctrl_reg = PCH_PP_CONTROL;
5198 5199 5200 5201
		pp_on_reg = PCH_PP_ON_DELAYS;
		pp_off_reg = PCH_PP_OFF_DELAYS;
		pp_div_reg = PCH_PP_DIVISOR;
	} else {
5202 5203 5204 5205 5206 5207
		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);

		pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
		pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
		pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
		pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
5208
	}
5209 5210 5211

	/* Workaround: Need to write PP_CONTROL with the unlock key as
	 * the very first thing. */
5212
	pp_ctl = ironlake_get_pp_control(intel_dp);
5213

5214 5215
	pp_on = I915_READ(pp_on_reg);
	pp_off = I915_READ(pp_off_reg);
5216 5217 5218 5219
	if (!IS_BROXTON(dev)) {
		I915_WRITE(pp_ctrl_reg, pp_ctl);
		pp_div = I915_READ(pp_div_reg);
	}
5220 5221 5222 5223 5224 5225 5226 5227 5228 5229 5230 5231 5232 5233

	/* Pull timing values out of registers */
	cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
		PANEL_POWER_UP_DELAY_SHIFT;

	cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
		PANEL_LIGHT_ON_DELAY_SHIFT;

	cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
		PANEL_LIGHT_OFF_DELAY_SHIFT;

	cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
		PANEL_POWER_DOWN_DELAY_SHIFT;

5234 5235 5236 5237 5238 5239 5240 5241 5242
	if (IS_BROXTON(dev)) {
		u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
			BXT_POWER_CYCLE_DELAY_SHIFT;
		if (tmp > 0)
			cur.t11_t12 = (tmp - 1) * 1000;
		else
			cur.t11_t12 = 0;
	} else {
		cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5243
		       PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5244
	}
5245 5246 5247 5248

	DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		      cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);

5249
	vbt = dev_priv->vbt.edp_pps;
5250 5251 5252 5253 5254 5255 5256 5257 5258 5259 5260 5261 5262 5263 5264 5265 5266 5267

	/* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
	 * our hw here, which are all in 100usec. */
	spec.t1_t3 = 210 * 10;
	spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
	spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
	spec.t10 = 500 * 10;
	/* This one is special and actually in units of 100ms, but zero
	 * based in the hw (so we need to add 100 ms). But the sw vbt
	 * table multiplies it with 1000 to make it in units of 100usec,
	 * too. */
	spec.t11_t12 = (510 + 100) * 10;

	DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		      vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);

	/* Use the max of the register settings and vbt. If both are
	 * unset, fall back to the spec limits. */
5268
#define assign_final(field)	final->field = (max(cur.field, vbt.field) == 0 ? \
5269 5270 5271 5272 5273 5274 5275 5276 5277
				       spec.field : \
				       max(cur.field, vbt.field))
	assign_final(t1_t3);
	assign_final(t8);
	assign_final(t9);
	assign_final(t10);
	assign_final(t11_t12);
#undef assign_final

5278
#define get_delay(field)	(DIV_ROUND_UP(final->field, 10))
5279 5280 5281 5282 5283 5284 5285
	intel_dp->panel_power_up_delay = get_delay(t1_t3);
	intel_dp->backlight_on_delay = get_delay(t8);
	intel_dp->backlight_off_delay = get_delay(t9);
	intel_dp->panel_power_down_delay = get_delay(t10);
	intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
#undef get_delay

5286 5287 5288 5289 5290 5291 5292 5293 5294 5295
	DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
		      intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
		      intel_dp->panel_power_cycle_delay);

	DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
		      intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
}

static void
intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
5296
					      struct intel_dp *intel_dp)
5297 5298
{
	struct drm_i915_private *dev_priv = dev->dev_private;
5299 5300
	u32 pp_on, pp_off, pp_div, port_sel = 0;
	int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
5301
	int pp_on_reg, pp_off_reg, pp_div_reg = 0, pp_ctrl_reg;
5302
	enum port port = dp_to_dig_port(intel_dp)->port;
5303
	const struct edp_power_seq *seq = &intel_dp->pps_delays;
5304

V
Ville Syrjälä 已提交
5305
	lockdep_assert_held(&dev_priv->pps_mutex);
5306

5307 5308 5309 5310 5311 5312 5313 5314 5315 5316 5317
	if (IS_BROXTON(dev)) {
		/*
		 * TODO: BXT has 2 sets of PPS registers.
		 * Correct Register for Broxton need to be identified
		 * using VBT. hardcoding for now
		 */
		pp_ctrl_reg = BXT_PP_CONTROL(0);
		pp_on_reg = BXT_PP_ON_DELAYS(0);
		pp_off_reg = BXT_PP_OFF_DELAYS(0);

	} else if (HAS_PCH_SPLIT(dev)) {
5318 5319 5320 5321
		pp_on_reg = PCH_PP_ON_DELAYS;
		pp_off_reg = PCH_PP_OFF_DELAYS;
		pp_div_reg = PCH_PP_DIVISOR;
	} else {
5322 5323 5324 5325 5326
		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);

		pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
		pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
		pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
5327 5328
	}

5329 5330 5331 5332 5333 5334 5335 5336
	/*
	 * And finally store the new values in the power sequencer. The
	 * backlight delays are set to 1 because we do manual waits on them. For
	 * T8, even BSpec recommends doing it. For T9, if we don't do this,
	 * we'll end up waiting for the backlight off delay twice: once when we
	 * do the manual sleep, and once when we disable the panel and wait for
	 * the PP_STATUS bit to become zero.
	 */
5337
	pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5338 5339
		(1 << PANEL_LIGHT_ON_DELAY_SHIFT);
	pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5340
		 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5341 5342
	/* Compute the divisor for the pp clock, simply match the Bspec
	 * formula. */
5343 5344 5345 5346 5347 5348 5349 5350 5351 5352
	if (IS_BROXTON(dev)) {
		pp_div = I915_READ(pp_ctrl_reg);
		pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
		pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
				<< BXT_POWER_CYCLE_DELAY_SHIFT);
	} else {
		pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
		pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
				<< PANEL_POWER_CYCLE_DELAY_SHIFT);
	}
5353 5354 5355

	/* Haswell doesn't have any port selection bits for the panel
	 * power sequencer any more. */
5356
	if (IS_VALLEYVIEW(dev)) {
5357
		port_sel = PANEL_PORT_SELECT_VLV(port);
5358
	} else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5359
		if (port == PORT_A)
5360
			port_sel = PANEL_PORT_SELECT_DPA;
5361
		else
5362
			port_sel = PANEL_PORT_SELECT_DPD;
5363 5364
	}

5365 5366 5367 5368
	pp_on |= port_sel;

	I915_WRITE(pp_on_reg, pp_on);
	I915_WRITE(pp_off_reg, pp_off);
5369 5370 5371 5372
	if (IS_BROXTON(dev))
		I915_WRITE(pp_ctrl_reg, pp_div);
	else
		I915_WRITE(pp_div_reg, pp_div);
5373 5374

	DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5375 5376
		      I915_READ(pp_on_reg),
		      I915_READ(pp_off_reg),
5377 5378
		      IS_BROXTON(dev) ?
		      (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) :
5379
		      I915_READ(pp_div_reg));
5380 5381
}

5382 5383 5384 5385 5386 5387 5388 5389 5390 5391 5392 5393
/**
 * intel_dp_set_drrs_state - program registers for RR switch to take effect
 * @dev: DRM device
 * @refresh_rate: RR to be programmed
 *
 * This function gets called when refresh rate (RR) has to be changed from
 * one frequency to another. Switches can be between high and low RR
 * supported by the panel or to any other RR based on media playback (in
 * this case, RR value needs to be passed from user space).
 *
 * The caller of this function needs to take a lock on dev_priv->drrs.
 */
5394
static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
5395 5396 5397
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_encoder *encoder;
5398 5399
	struct intel_digital_port *dig_port = NULL;
	struct intel_dp *intel_dp = dev_priv->drrs.dp;
5400
	struct intel_crtc_state *config = NULL;
5401
	struct intel_crtc *intel_crtc = NULL;
5402
	enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5403 5404 5405 5406 5407 5408

	if (refresh_rate <= 0) {
		DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
		return;
	}

5409 5410
	if (intel_dp == NULL) {
		DRM_DEBUG_KMS("DRRS not supported.\n");
5411 5412 5413
		return;
	}

5414
	/*
5415 5416
	 * FIXME: This needs proper synchronization with psr state for some
	 * platforms that cannot have PSR and DRRS enabled at the same time.
5417
	 */
5418

5419 5420
	dig_port = dp_to_dig_port(intel_dp);
	encoder = &dig_port->base;
5421
	intel_crtc = to_intel_crtc(encoder->base.crtc);
5422 5423 5424 5425 5426 5427

	if (!intel_crtc) {
		DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
		return;
	}

5428
	config = intel_crtc->config;
5429

5430
	if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5431 5432 5433 5434
		DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
		return;
	}

5435 5436
	if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
			refresh_rate)
5437 5438
		index = DRRS_LOW_RR;

5439
	if (index == dev_priv->drrs.refresh_rate_type) {
5440 5441 5442 5443 5444 5445 5446 5447 5448 5449
		DRM_DEBUG_KMS(
			"DRRS requested for previously set RR...ignoring\n");
		return;
	}

	if (!intel_crtc->active) {
		DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
		return;
	}

D
Durgadoss R 已提交
5450
	if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
5451 5452 5453 5454 5455 5456 5457 5458 5459 5460 5461 5462
		switch (index) {
		case DRRS_HIGH_RR:
			intel_dp_set_m_n(intel_crtc, M1_N1);
			break;
		case DRRS_LOW_RR:
			intel_dp_set_m_n(intel_crtc, M2_N2);
			break;
		case DRRS_MAX_RR:
		default:
			DRM_ERROR("Unsupported refreshrate type\n");
		}
	} else if (INTEL_INFO(dev)->gen > 6) {
5463 5464
		u32 reg = PIPECONF(intel_crtc->config->cpu_transcoder);
		u32 val;
5465

5466
		val = I915_READ(reg);
5467
		if (index > DRRS_HIGH_RR) {
5468 5469 5470 5471
			if (IS_VALLEYVIEW(dev))
				val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
			else
				val |= PIPECONF_EDP_RR_MODE_SWITCH;
5472
		} else {
5473 5474 5475 5476
			if (IS_VALLEYVIEW(dev))
				val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
			else
				val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5477 5478 5479 5480
		}
		I915_WRITE(reg, val);
	}

5481 5482 5483 5484 5485
	dev_priv->drrs.refresh_rate_type = index;

	DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
}

5486 5487 5488 5489 5490 5491
/**
 * intel_edp_drrs_enable - init drrs struct if supported
 * @intel_dp: DP struct
 *
 * Initializes frontbuffer_bits and drrs.dp
 */
V
Vandana Kannan 已提交
5492 5493 5494 5495 5496 5497 5498 5499 5500 5501 5502 5503 5504 5505 5506 5507 5508 5509 5510 5511 5512 5513 5514 5515 5516 5517 5518
void intel_edp_drrs_enable(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = dig_port->base.base.crtc;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	if (!intel_crtc->config->has_drrs) {
		DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
		return;
	}

	mutex_lock(&dev_priv->drrs.mutex);
	if (WARN_ON(dev_priv->drrs.dp)) {
		DRM_ERROR("DRRS already enabled\n");
		goto unlock;
	}

	dev_priv->drrs.busy_frontbuffer_bits = 0;

	dev_priv->drrs.dp = intel_dp;

unlock:
	mutex_unlock(&dev_priv->drrs.mutex);
}

5519 5520 5521 5522 5523
/**
 * intel_edp_drrs_disable - Disable DRRS
 * @intel_dp: DP struct
 *
 */
V
Vandana Kannan 已提交
5524 5525 5526 5527 5528 5529 5530 5531 5532 5533 5534 5535 5536 5537 5538 5539 5540 5541 5542 5543 5544 5545 5546 5547 5548 5549 5550 5551
void intel_edp_drrs_disable(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = dig_port->base.base.crtc;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	if (!intel_crtc->config->has_drrs)
		return;

	mutex_lock(&dev_priv->drrs.mutex);
	if (!dev_priv->drrs.dp) {
		mutex_unlock(&dev_priv->drrs.mutex);
		return;
	}

	if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
		intel_dp_set_drrs_state(dev_priv->dev,
			intel_dp->attached_connector->panel.
			fixed_mode->vrefresh);

	dev_priv->drrs.dp = NULL;
	mutex_unlock(&dev_priv->drrs.mutex);

	cancel_delayed_work_sync(&dev_priv->drrs.work);
}

5552 5553 5554 5555 5556 5557 5558 5559 5560 5561 5562 5563 5564
static void intel_edp_drrs_downclock_work(struct work_struct *work)
{
	struct drm_i915_private *dev_priv =
		container_of(work, typeof(*dev_priv), drrs.work.work);
	struct intel_dp *intel_dp;

	mutex_lock(&dev_priv->drrs.mutex);

	intel_dp = dev_priv->drrs.dp;

	if (!intel_dp)
		goto unlock;

5565
	/*
5566 5567
	 * The delayed work can race with an invalidate hence we need to
	 * recheck.
5568 5569
	 */

5570 5571
	if (dev_priv->drrs.busy_frontbuffer_bits)
		goto unlock;
5572

5573 5574 5575 5576
	if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
		intel_dp_set_drrs_state(dev_priv->dev,
			intel_dp->attached_connector->panel.
			downclock_mode->vrefresh);
5577

5578 5579
unlock:
	mutex_unlock(&dev_priv->drrs.mutex);
5580 5581
}

5582
/**
5583
 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5584 5585 5586
 * @dev: DRM device
 * @frontbuffer_bits: frontbuffer plane tracking bits
 *
5587 5588
 * This function gets called everytime rendering on the given planes start.
 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5589 5590 5591
 *
 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
 */
5592 5593 5594 5595 5596 5597 5598
void intel_edp_drrs_invalidate(struct drm_device *dev,
		unsigned frontbuffer_bits)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc;
	enum pipe pipe;

5599
	if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5600 5601
		return;

5602
	cancel_delayed_work(&dev_priv->drrs.work);
5603

5604
	mutex_lock(&dev_priv->drrs.mutex);
5605 5606 5607 5608 5609
	if (!dev_priv->drrs.dp) {
		mutex_unlock(&dev_priv->drrs.mutex);
		return;
	}

5610 5611 5612
	crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
	pipe = to_intel_crtc(crtc)->pipe;

5613 5614 5615
	frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
	dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;

5616
	/* invalidate means busy screen hence upclock */
5617
	if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5618 5619 5620 5621 5622 5623 5624
		intel_dp_set_drrs_state(dev_priv->dev,
				dev_priv->drrs.dp->attached_connector->panel.
				fixed_mode->vrefresh);

	mutex_unlock(&dev_priv->drrs.mutex);
}

5625
/**
5626
 * intel_edp_drrs_flush - Restart Idleness DRRS
5627 5628 5629
 * @dev: DRM device
 * @frontbuffer_bits: frontbuffer plane tracking bits
 *
5630 5631 5632 5633
 * This function gets called every time rendering on the given planes has
 * completed or flip on a crtc is completed. So DRRS should be upclocked
 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
 * if no other planes are dirty.
5634 5635 5636
 *
 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
 */
5637 5638 5639 5640 5641 5642 5643
void intel_edp_drrs_flush(struct drm_device *dev,
		unsigned frontbuffer_bits)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc;
	enum pipe pipe;

5644
	if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5645 5646
		return;

5647
	cancel_delayed_work(&dev_priv->drrs.work);
5648

5649
	mutex_lock(&dev_priv->drrs.mutex);
5650 5651 5652 5653 5654
	if (!dev_priv->drrs.dp) {
		mutex_unlock(&dev_priv->drrs.mutex);
		return;
	}

5655 5656
	crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
	pipe = to_intel_crtc(crtc)->pipe;
5657 5658

	frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5659 5660
	dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;

5661
	/* flush means busy screen hence upclock */
5662
	if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5663 5664 5665 5666 5667 5668 5669 5670 5671
		intel_dp_set_drrs_state(dev_priv->dev,
				dev_priv->drrs.dp->attached_connector->panel.
				fixed_mode->vrefresh);

	/*
	 * flush also means no more activity hence schedule downclock, if all
	 * other fbs are quiescent too
	 */
	if (!dev_priv->drrs.busy_frontbuffer_bits)
5672 5673 5674 5675 5676
		schedule_delayed_work(&dev_priv->drrs.work,
				msecs_to_jiffies(1000));
	mutex_unlock(&dev_priv->drrs.mutex);
}

5677 5678 5679 5680 5681 5682 5683 5684 5685 5686 5687 5688 5689 5690 5691 5692 5693 5694 5695 5696 5697 5698 5699 5700 5701 5702 5703 5704 5705 5706 5707 5708 5709 5710 5711 5712 5713 5714 5715 5716 5717 5718 5719 5720 5721 5722 5723 5724 5725 5726
/**
 * DOC: Display Refresh Rate Switching (DRRS)
 *
 * Display Refresh Rate Switching (DRRS) is a power conservation feature
 * which enables swtching between low and high refresh rates,
 * dynamically, based on the usage scenario. This feature is applicable
 * for internal panels.
 *
 * Indication that the panel supports DRRS is given by the panel EDID, which
 * would list multiple refresh rates for one resolution.
 *
 * DRRS is of 2 types - static and seamless.
 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
 * (may appear as a blink on screen) and is used in dock-undock scenario.
 * Seamless DRRS involves changing RR without any visual effect to the user
 * and can be used during normal system usage. This is done by programming
 * certain registers.
 *
 * Support for static/seamless DRRS may be indicated in the VBT based on
 * inputs from the panel spec.
 *
 * DRRS saves power by switching to low RR based on usage scenarios.
 *
 * eDP DRRS:-
 *        The implementation is based on frontbuffer tracking implementation.
 * When there is a disturbance on the screen triggered by user activity or a
 * periodic system activity, DRRS is disabled (RR is changed to high RR).
 * When there is no movement on screen, after a timeout of 1 second, a switch
 * to low RR is made.
 *        For integration with frontbuffer tracking code,
 * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
 *
 * DRRS can be further extended to support other internal panels and also
 * the scenario of video playback wherein RR is set based on the rate
 * requested by userspace.
 */

/**
 * intel_dp_drrs_init - Init basic DRRS work and mutex.
 * @intel_connector: eDP connector
 * @fixed_mode: preferred mode of panel
 *
 * This function is  called only once at driver load to initialize basic
 * DRRS stuff.
 *
 * Returns:
 * Downclock mode if panel supports it, else return NULL.
 * DRRS support is determined by the presence of downclock mode (apart
 * from VBT setting).
 */
5727
static struct drm_display_mode *
5728 5729
intel_dp_drrs_init(struct intel_connector *intel_connector,
		struct drm_display_mode *fixed_mode)
5730 5731
{
	struct drm_connector *connector = &intel_connector->base;
5732
	struct drm_device *dev = connector->dev;
5733 5734 5735
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_display_mode *downclock_mode = NULL;

5736 5737 5738
	INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
	mutex_init(&dev_priv->drrs.mutex);

5739 5740 5741 5742 5743 5744
	if (INTEL_INFO(dev)->gen <= 6) {
		DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
		return NULL;
	}

	if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5745
		DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5746 5747 5748 5749 5750 5751 5752
		return NULL;
	}

	downclock_mode = intel_find_panel_downclock
					(dev, fixed_mode, connector);

	if (!downclock_mode) {
5753
		DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5754 5755 5756
		return NULL;
	}

5757
	dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5758

5759
	dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5760
	DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5761 5762 5763
	return downclock_mode;
}

5764
static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5765
				     struct intel_connector *intel_connector)
5766 5767 5768
{
	struct drm_connector *connector = &intel_connector->base;
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5769 5770
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct drm_device *dev = intel_encoder->base.dev;
5771 5772
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_display_mode *fixed_mode = NULL;
5773
	struct drm_display_mode *downclock_mode = NULL;
5774 5775 5776
	bool has_dpcd;
	struct drm_display_mode *scan;
	struct edid *edid;
5777
	enum pipe pipe = INVALID_PIPE;
5778 5779 5780 5781

	if (!is_edp(intel_dp))
		return true;

5782 5783 5784
	pps_lock(intel_dp);
	intel_edp_panel_vdd_sanitize(intel_dp);
	pps_unlock(intel_dp);
5785

5786 5787 5788 5789 5790 5791 5792 5793 5794 5795 5796 5797 5798 5799 5800
	/* Cache DPCD and EDID for edp. */
	has_dpcd = intel_dp_get_dpcd(intel_dp);

	if (has_dpcd) {
		if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
			dev_priv->no_aux_handshake =
				intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
				DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
	} else {
		/* if this fails, presume the device is a ghost */
		DRM_INFO("failed to retrieve link info, disabling eDP\n");
		return false;
	}

	/* We now know it's not a ghost, init power sequence regs. */
5801
	pps_lock(intel_dp);
5802
	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5803
	pps_unlock(intel_dp);
5804

5805
	mutex_lock(&dev->mode_config.mutex);
5806
	edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5807 5808 5809 5810 5811 5812 5813 5814 5815 5816 5817 5818 5819 5820 5821 5822 5823 5824
	if (edid) {
		if (drm_add_edid_modes(connector, edid)) {
			drm_mode_connector_update_edid_property(connector,
								edid);
			drm_edid_to_eld(connector, edid);
		} else {
			kfree(edid);
			edid = ERR_PTR(-EINVAL);
		}
	} else {
		edid = ERR_PTR(-ENOENT);
	}
	intel_connector->edid = edid;

	/* prefer fixed mode from EDID if available */
	list_for_each_entry(scan, &connector->probed_modes, head) {
		if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
			fixed_mode = drm_mode_duplicate(dev, scan);
5825 5826
			downclock_mode = intel_dp_drrs_init(
						intel_connector, fixed_mode);
5827 5828 5829 5830 5831 5832 5833 5834 5835 5836 5837
			break;
		}
	}

	/* fallback to VBT if available for eDP */
	if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
		fixed_mode = drm_mode_duplicate(dev,
					dev_priv->vbt.lfp_lvds_vbt_mode);
		if (fixed_mode)
			fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
	}
5838
	mutex_unlock(&dev->mode_config.mutex);
5839

5840 5841 5842
	if (IS_VALLEYVIEW(dev)) {
		intel_dp->edp_notifier.notifier_call = edp_notify_handler;
		register_reboot_notifier(&intel_dp->edp_notifier);
5843 5844 5845 5846 5847 5848 5849 5850 5851 5852 5853 5854 5855 5856 5857 5858 5859 5860 5861

		/*
		 * Figure out the current pipe for the initial backlight setup.
		 * If the current pipe isn't valid, try the PPS pipe, and if that
		 * fails just assume pipe A.
		 */
		if (IS_CHERRYVIEW(dev))
			pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
		else
			pipe = PORT_TO_PIPE(intel_dp->DP);

		if (pipe != PIPE_A && pipe != PIPE_B)
			pipe = intel_dp->pps_pipe;

		if (pipe != PIPE_A && pipe != PIPE_B)
			pipe = PIPE_A;

		DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
			      pipe_name(pipe));
5862 5863
	}

5864
	intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5865
	intel_connector->panel.backlight.power = intel_edp_backlight_power;
5866
	intel_panel_setup_backlight(connector, pipe);
5867 5868 5869 5870

	return true;
}

5871
bool
5872 5873
intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
			struct intel_connector *intel_connector)
5874
{
5875 5876 5877 5878
	struct drm_connector *connector = &intel_connector->base;
	struct intel_dp *intel_dp = &intel_dig_port->dp;
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct drm_device *dev = intel_encoder->base.dev;
5879
	struct drm_i915_private *dev_priv = dev->dev_private;
5880
	enum port port = intel_dig_port->port;
5881
	int type, ret;
5882

5883 5884
	intel_dp->pps_pipe = INVALID_PIPE;

5885
	/* intel_dp vfuncs */
5886 5887 5888
	if (INTEL_INFO(dev)->gen >= 9)
		intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
	else if (IS_VALLEYVIEW(dev))
5889 5890 5891 5892 5893 5894 5895 5896
		intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
		intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
	else if (HAS_PCH_SPLIT(dev))
		intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
	else
		intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;

5897 5898 5899 5900
	if (INTEL_INFO(dev)->gen >= 9)
		intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
	else
		intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
5901

5902 5903 5904
	if (HAS_DDI(dev))
		intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;

5905 5906
	/* Preserve the current hw state. */
	intel_dp->DP = I915_READ(intel_dp->output_reg);
5907
	intel_dp->attached_connector = intel_connector;
5908

5909
	if (intel_dp_is_edp(dev, port))
5910
		type = DRM_MODE_CONNECTOR_eDP;
5911 5912
	else
		type = DRM_MODE_CONNECTOR_DisplayPort;
5913

5914 5915 5916 5917 5918 5919 5920 5921
	/*
	 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
	 * for DP the encoder type can be set by the caller to
	 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
	 */
	if (type == DRM_MODE_CONNECTOR_eDP)
		intel_encoder->type = INTEL_OUTPUT_EDP;

5922 5923 5924 5925 5926
	/* eDP only on port B and/or C on vlv/chv */
	if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
		    port != PORT_B && port != PORT_C))
		return false;

5927 5928 5929 5930
	DRM_DEBUG_KMS("Adding %s connector on port %c\n",
			type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
			port_name(port));

5931
	drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5932 5933 5934 5935 5936
	drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);

	connector->interlace_allowed = true;
	connector->doublescan_allowed = 0;

5937
	INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5938
			  edp_panel_vdd_work);
5939

5940
	intel_connector_attach_encoder(intel_connector, intel_encoder);
5941
	drm_connector_register(connector);
5942

P
Paulo Zanoni 已提交
5943
	if (HAS_DDI(dev))
5944 5945 5946
		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
	else
		intel_connector->get_hw_state = intel_connector_get_hw_state;
5947
	intel_connector->unregister = intel_dp_connector_unregister;
5948

5949
	/* Set up the hotplug pin. */
5950 5951
	switch (port) {
	case PORT_A:
5952
		intel_encoder->hpd_pin = HPD_PORT_A;
5953 5954
		break;
	case PORT_B:
5955
		intel_encoder->hpd_pin = HPD_PORT_B;
5956
		if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
5957
			intel_encoder->hpd_pin = HPD_PORT_A;
5958 5959
		break;
	case PORT_C:
5960
		intel_encoder->hpd_pin = HPD_PORT_C;
5961 5962
		break;
	case PORT_D:
5963
		intel_encoder->hpd_pin = HPD_PORT_D;
5964
		break;
X
Xiong Zhang 已提交
5965 5966 5967
	case PORT_E:
		intel_encoder->hpd_pin = HPD_PORT_E;
		break;
5968
	default:
5969
		BUG();
5970 5971
	}

5972
	if (is_edp(intel_dp)) {
5973
		pps_lock(intel_dp);
5974 5975
		intel_dp_init_panel_power_timestamps(intel_dp);
		if (IS_VALLEYVIEW(dev))
5976
			vlv_initial_power_sequencer_setup(intel_dp);
5977
		else
5978
			intel_dp_init_panel_power_sequencer(dev, intel_dp);
5979
		pps_unlock(intel_dp);
5980
	}
5981

5982 5983 5984
	ret = intel_dp_aux_init(intel_dp, intel_connector);
	if (ret)
		goto fail;
5985

5986
	/* init MST on ports that can support it */
5987 5988 5989 5990
	if (HAS_DP_MST(dev) &&
	    (port == PORT_B || port == PORT_C || port == PORT_D))
		intel_dp_mst_encoder_init(intel_dig_port,
					  intel_connector->base.base.id);
5991

5992
	if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5993 5994 5995
		intel_dp_aux_fini(intel_dp);
		intel_dp_mst_encoder_cleanup(intel_dig_port);
		goto fail;
5996
	}
5997

5998 5999
	intel_dp_add_properties(intel_dp, connector);

6000 6001 6002 6003 6004 6005 6006 6007
	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
	 * 0xd.  Failure to do so will result in spurious interrupts being
	 * generated on the port when a cable is not attached.
	 */
	if (IS_G4X(dev) && !IS_GM45(dev)) {
		u32 temp = I915_READ(PEG_BAND_GAP_DATA);
		I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
	}
6008

6009 6010
	i915_debugfs_connector_add(connector);

6011
	return true;
6012 6013 6014 6015 6016 6017 6018 6019 6020 6021 6022 6023 6024 6025 6026 6027

fail:
	if (is_edp(intel_dp)) {
		cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
		/*
		 * vdd might still be enabled do to the delayed vdd off.
		 * Make sure vdd is actually turned off here.
		 */
		pps_lock(intel_dp);
		edp_panel_vdd_off_sync(intel_dp);
		pps_unlock(intel_dp);
	}
	drm_connector_unregister(connector);
	drm_connector_cleanup(connector);

	return false;
6028
}
6029 6030 6031 6032

void
intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
{
6033
	struct drm_i915_private *dev_priv = dev->dev_private;
6034 6035 6036 6037 6038
	struct intel_digital_port *intel_dig_port;
	struct intel_encoder *intel_encoder;
	struct drm_encoder *encoder;
	struct intel_connector *intel_connector;

6039
	intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
6040 6041 6042
	if (!intel_dig_port)
		return;

6043
	intel_connector = intel_connector_alloc();
S
Sudip Mukherjee 已提交
6044 6045
	if (!intel_connector)
		goto err_connector_alloc;
6046 6047 6048 6049 6050 6051 6052

	intel_encoder = &intel_dig_port->base;
	encoder = &intel_encoder->base;

	drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
			 DRM_MODE_ENCODER_TMDS);

6053
	intel_encoder->compute_config = intel_dp_compute_config;
P
Paulo Zanoni 已提交
6054 6055
	intel_encoder->disable = intel_disable_dp;
	intel_encoder->get_hw_state = intel_dp_get_hw_state;
6056
	intel_encoder->get_config = intel_dp_get_config;
6057
	intel_encoder->suspend = intel_dp_encoder_suspend;
6058
	if (IS_CHERRYVIEW(dev)) {
6059
		intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
6060 6061
		intel_encoder->pre_enable = chv_pre_enable_dp;
		intel_encoder->enable = vlv_enable_dp;
6062
		intel_encoder->post_disable = chv_post_disable_dp;
6063
		intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
6064
	} else if (IS_VALLEYVIEW(dev)) {
6065
		intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
6066 6067
		intel_encoder->pre_enable = vlv_pre_enable_dp;
		intel_encoder->enable = vlv_enable_dp;
6068
		intel_encoder->post_disable = vlv_post_disable_dp;
6069
	} else {
6070 6071
		intel_encoder->pre_enable = g4x_pre_enable_dp;
		intel_encoder->enable = g4x_enable_dp;
6072 6073
		if (INTEL_INFO(dev)->gen >= 5)
			intel_encoder->post_disable = ilk_post_disable_dp;
6074
	}
6075

6076
	intel_dig_port->port = port;
6077 6078
	intel_dig_port->dp.output_reg = output_reg;

P
Paulo Zanoni 已提交
6079
	intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
6080 6081 6082 6083 6084 6085 6086 6087
	if (IS_CHERRYVIEW(dev)) {
		if (port == PORT_D)
			intel_encoder->crtc_mask = 1 << 2;
		else
			intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
	} else {
		intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
	}
6088
	intel_encoder->cloneable = 0;
6089

6090
	intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6091
	dev_priv->hotplug.irq_port[port] = intel_dig_port;
6092

S
Sudip Mukherjee 已提交
6093 6094 6095 6096 6097 6098 6099 6100 6101 6102 6103 6104
	if (!intel_dp_init_connector(intel_dig_port, intel_connector))
		goto err_init_connector;

	return;

err_init_connector:
	drm_encoder_cleanup(encoder);
	kfree(intel_connector);
err_connector_alloc:
	kfree(intel_dig_port);

	return;
6105
}
6106 6107 6108 6109 6110 6111 6112 6113

void intel_dp_mst_suspend(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;

	/* disable MST */
	for (i = 0; i < I915_MAX_PORTS; i++) {
6114
		struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6115 6116 6117 6118 6119 6120 6121 6122 6123 6124 6125 6126 6127 6128 6129 6130 6131 6132
		if (!intel_dig_port)
			continue;

		if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
			if (!intel_dig_port->dp.can_mst)
				continue;
			if (intel_dig_port->dp.is_mst)
				drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
		}
	}
}

void intel_dp_mst_resume(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;

	for (i = 0; i < I915_MAX_PORTS; i++) {
6133
		struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6134 6135 6136 6137 6138 6139 6140 6141 6142 6143 6144 6145 6146 6147 6148
		if (!intel_dig_port)
			continue;
		if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
			int ret;

			if (!intel_dig_port->dp.can_mst)
				continue;

			ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
			if (ret != 0) {
				intel_dp_check_mst_status(&intel_dig_port->dp);
			}
		}
	}
}