intel_dp.c 169.7 KB
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/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Keith Packard <keithp@keithp.com>
 *
 */

#include <linux/i2c.h>
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#include <linux/slab.h>
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#include <linux/export.h>
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#include <linux/notifier.h>
#include <linux/reboot.h>
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#include <drm/drmP.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_edid.h>
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#include "intel_drv.h"
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#include <drm/i915_drm.h>
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#include "i915_drv.h"

#define DP_LINK_CHECK_TIMEOUT	(10 * 1000)

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/* Compliance test status bits  */
#define INTEL_DP_RESOLUTION_SHIFT_MASK	0
#define INTEL_DP_RESOLUTION_PREFERRED	(1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
#define INTEL_DP_RESOLUTION_STANDARD	(2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
#define INTEL_DP_RESOLUTION_FAILSAFE	(3 << INTEL_DP_RESOLUTION_SHIFT_MASK)

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struct dp_link_dpll {
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	int clock;
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	struct dpll dpll;
};

static const struct dp_link_dpll gen4_dpll[] = {
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	{ 162000,
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		{ .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
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	{ 270000,
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		{ .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
};

static const struct dp_link_dpll pch_dpll[] = {
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	{ 162000,
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		{ .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
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	{ 270000,
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		{ .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
};

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static const struct dp_link_dpll vlv_dpll[] = {
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	{ 162000,
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		{ .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
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	{ 270000,
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		{ .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
};

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/*
 * CHV supports eDP 1.4 that have  more link rates.
 * Below only provides the fixed rate but exclude variable rate.
 */
static const struct dp_link_dpll chv_dpll[] = {
	/*
	 * CHV requires to program fractional division for m2.
	 * m2 is stored in fixed point format using formula below
	 * (m2_int << 22) | m2_fraction
	 */
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	{ 162000,	/* m2_int = 32, m2_fraction = 1677722 */
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		{ .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
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	{ 270000,	/* m2_int = 27, m2_fraction = 0 */
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		{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
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	{ 540000,	/* m2_int = 27, m2_fraction = 0 */
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		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
};
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static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
				  324000, 432000, 540000 };
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static const int skl_rates[] = { 162000, 216000, 270000,
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				  324000, 432000, 540000 };
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static const int chv_rates[] = { 162000, 202500, 210000, 216000,
				 243000, 270000, 324000, 405000,
				 420000, 432000, 540000 };
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static const int default_rates[] = { 162000, 270000, 540000 };
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/**
 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 * @intel_dp: DP struct
 *
 * If a CPU or PCH DP output is attached to an eDP panel, this function
 * will return true, and false otherwise.
 */
static bool is_edp(struct intel_dp *intel_dp)
{
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	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
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}

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static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
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{
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	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	return intel_dig_port->base.base.dev;
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}

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static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
{
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	return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
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}

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static void intel_dp_link_down(struct intel_dp *intel_dp);
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static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
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static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
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static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
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static void vlv_steal_power_sequencer(struct drm_device *dev,
				      enum pipe pipe);
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static int
intel_dp_max_link_bw(struct intel_dp  *intel_dp)
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{
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	int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
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	switch (max_link_bw) {
	case DP_LINK_BW_1_62:
	case DP_LINK_BW_2_7:
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	case DP_LINK_BW_5_4:
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		break;
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	default:
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		WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
		     max_link_bw);
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		max_link_bw = DP_LINK_BW_1_62;
		break;
	}
	return max_link_bw;
}

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static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	u8 source_max, sink_max;

	source_max = 4;
	if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
	    (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
		source_max = 2;

	sink_max = drm_dp_max_lane_count(intel_dp->dpcd);

	return min(source_max, sink_max);
}

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/*
 * The units on the numbers in the next two are... bizarre.  Examples will
 * make it clearer; this one parallels an example in the eDP spec.
 *
 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 *
 *     270000 * 1 * 8 / 10 == 216000
 *
 * The actual data capacity of that configuration is 2.16Gbit/s, so the
 * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 * 119000.  At 18bpp that's 2142000 kilobits per second.
 *
 * Thus the strange-looking division by 10 in intel_dp_link_required, to
 * get the result in decakilobits instead of kilobits.
 */

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static int
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intel_dp_link_required(int pixel_clock, int bpp)
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{
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	return (pixel_clock * bpp + 9) / 10;
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}

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static int
intel_dp_max_data_rate(int max_link_clock, int max_lanes)
{
	return (max_link_clock * max_lanes * 8) / 10;
}

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static enum drm_mode_status
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intel_dp_mode_valid(struct drm_connector *connector,
		    struct drm_display_mode *mode)
{
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	struct intel_dp *intel_dp = intel_attached_dp(connector);
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	struct intel_connector *intel_connector = to_intel_connector(connector);
	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
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	int target_clock = mode->clock;
	int max_rate, mode_rate, max_lanes, max_link_clock;
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	if (is_edp(intel_dp) && fixed_mode) {
		if (mode->hdisplay > fixed_mode->hdisplay)
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			return MODE_PANEL;

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		if (mode->vdisplay > fixed_mode->vdisplay)
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			return MODE_PANEL;
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		target_clock = fixed_mode->clock;
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	}

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	max_link_clock = intel_dp_max_link_rate(intel_dp);
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	max_lanes = intel_dp_max_lane_count(intel_dp);
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	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
	mode_rate = intel_dp_link_required(target_clock, 18);

	if (mode_rate > max_rate)
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		return MODE_CLOCK_HIGH;
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	if (mode->clock < 10000)
		return MODE_CLOCK_LOW;

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	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
		return MODE_H_ILLEGAL;

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	return MODE_OK;
}

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uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
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{
	int	i;
	uint32_t v = 0;

	if (src_bytes > 4)
		src_bytes = 4;
	for (i = 0; i < src_bytes; i++)
		v |= ((uint32_t) src[i]) << ((3-i) * 8);
	return v;
}

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static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
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{
	int i;
	if (dst_bytes > 4)
		dst_bytes = 4;
	for (i = 0; i < dst_bytes; i++)
		dst[i] = src >> ((3-i) * 8);
}

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/* hrawclock is 1/4 the FSB frequency */
static int
intel_hrawclk(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t clkcfg;

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	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
	if (IS_VALLEYVIEW(dev))
		return 200;

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	clkcfg = I915_READ(CLKCFG);
	switch (clkcfg & CLKCFG_FSB_MASK) {
	case CLKCFG_FSB_400:
		return 100;
	case CLKCFG_FSB_533:
		return 133;
	case CLKCFG_FSB_667:
		return 166;
	case CLKCFG_FSB_800:
		return 200;
	case CLKCFG_FSB_1067:
		return 266;
	case CLKCFG_FSB_1333:
		return 333;
	/* these two are just a guess; one of them might be right */
	case CLKCFG_FSB_1600:
	case CLKCFG_FSB_1600_ALT:
		return 400;
	default:
		return 133;
	}
}

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static void
intel_dp_init_panel_power_sequencer(struct drm_device *dev,
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				    struct intel_dp *intel_dp);
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static void
intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
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					      struct intel_dp *intel_dp);
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static void pps_lock(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *encoder = &intel_dig_port->base;
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum intel_display_power_domain power_domain;

	/*
	 * See vlv_power_sequencer_reset() why we need
	 * a power domain reference here.
	 */
	power_domain = intel_display_port_power_domain(encoder);
	intel_display_power_get(dev_priv, power_domain);

	mutex_lock(&dev_priv->pps_mutex);
}

static void pps_unlock(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *encoder = &intel_dig_port->base;
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum intel_display_power_domain power_domain;

	mutex_unlock(&dev_priv->pps_mutex);

	power_domain = intel_display_port_power_domain(encoder);
	intel_display_power_put(dev_priv, power_domain);
}

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static void
vlv_power_sequencer_kick(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum pipe pipe = intel_dp->pps_pipe;
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	bool pll_enabled;
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	uint32_t DP;

	if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
		 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
		 pipe_name(pipe), port_name(intel_dig_port->port)))
		return;

	DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
		      pipe_name(pipe), port_name(intel_dig_port->port));

	/* Preserve the BIOS-computed detected bit. This is
	 * supposed to be read-only.
	 */
	DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
	DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
	DP |= DP_PORT_WIDTH(1);
	DP |= DP_LINK_TRAIN_PAT_1;

	if (IS_CHERRYVIEW(dev))
		DP |= DP_PIPE_SELECT_CHV(pipe);
	else if (pipe == PIPE_B)
		DP |= DP_PIPEB_SELECT;

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	pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;

	/*
	 * The DPLL for the pipe must be enabled for this to work.
	 * So enable temporarily it if it's not already enabled.
	 */
	if (!pll_enabled)
		vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
				 &chv_dpll[0].dpll : &vlv_dpll[0].dpll);

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	/*
	 * Similar magic as in intel_dp_enable_port().
	 * We _must_ do this port enable + disable trick
	 * to make this power seqeuencer lock onto the port.
	 * Otherwise even VDD force bit won't work.
	 */
	I915_WRITE(intel_dp->output_reg, DP);
	POSTING_READ(intel_dp->output_reg);

	I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
	POSTING_READ(intel_dp->output_reg);

	I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
	POSTING_READ(intel_dp->output_reg);
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	if (!pll_enabled)
		vlv_force_pll_off(dev, pipe);
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}

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static enum pipe
vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct intel_encoder *encoder;
	unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
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	enum pipe pipe;
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	lockdep_assert_held(&dev_priv->pps_mutex);
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	/* We should never land here with regular DP ports */
	WARN_ON(!is_edp(intel_dp));

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	if (intel_dp->pps_pipe != INVALID_PIPE)
		return intel_dp->pps_pipe;

	/*
	 * We don't have power sequencer currently.
	 * Pick one that's not used by other ports.
	 */
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		struct intel_dp *tmp;

		if (encoder->type != INTEL_OUTPUT_EDP)
			continue;

		tmp = enc_to_intel_dp(&encoder->base);

		if (tmp->pps_pipe != INVALID_PIPE)
			pipes &= ~(1 << tmp->pps_pipe);
	}

	/*
	 * Didn't find one. This should not happen since there
	 * are two power sequencers and up to two eDP ports.
	 */
	if (WARN_ON(pipes == 0))
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		pipe = PIPE_A;
	else
		pipe = ffs(pipes) - 1;
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	vlv_steal_power_sequencer(dev, pipe);
	intel_dp->pps_pipe = pipe;
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	DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
		      pipe_name(intel_dp->pps_pipe),
		      port_name(intel_dig_port->port));

	/* init power sequencer on this pipe and port */
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	intel_dp_init_panel_power_sequencer(dev, intel_dp);
	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
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	/*
	 * Even vdd force doesn't work until we've made
	 * the power sequencer lock in on the port.
	 */
	vlv_power_sequencer_kick(intel_dp);
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	return intel_dp->pps_pipe;
}

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typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
			       enum pipe pipe);

static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
			       enum pipe pipe)
{
	return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
}

static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
				enum pipe pipe)
{
	return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
}

static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
			 enum pipe pipe)
{
	return true;
}
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static enum pipe
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vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
		     enum port port,
		     vlv_pipe_check pipe_check)
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{
	enum pipe pipe;
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	for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
		u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
			PANEL_PORT_SELECT_MASK;
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		if (port_sel != PANEL_PORT_SELECT_VLV(port))
			continue;

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		if (!pipe_check(dev_priv, pipe))
			continue;

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		return pipe;
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	}

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	return INVALID_PIPE;
}

static void
vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = intel_dig_port->port;

	lockdep_assert_held(&dev_priv->pps_mutex);

	/* try to find a pipe with this port selected */
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	/* first pick one where the panel is on */
	intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
						  vlv_pipe_has_pp_on);
	/* didn't find one? pick one where vdd is on */
	if (intel_dp->pps_pipe == INVALID_PIPE)
		intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
							  vlv_pipe_has_vdd_on);
	/* didn't find one? pick one with just the correct port */
	if (intel_dp->pps_pipe == INVALID_PIPE)
		intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
							  vlv_pipe_any);
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	/* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
	if (intel_dp->pps_pipe == INVALID_PIPE) {
		DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
			      port_name(port));
		return;
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	}

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	DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
		      port_name(port), pipe_name(intel_dp->pps_pipe));

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	intel_dp_init_panel_power_sequencer(dev, intel_dp);
	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
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}

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void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
{
	struct drm_device *dev = dev_priv->dev;
	struct intel_encoder *encoder;

	if (WARN_ON(!IS_VALLEYVIEW(dev)))
		return;

	/*
	 * We can't grab pps_mutex here due to deadlock with power_domain
	 * mutex when power_domain functions are called while holding pps_mutex.
	 * That also means that in order to use pps_pipe the code needs to
	 * hold both a power domain reference and pps_mutex, and the power domain
	 * reference get/put must be done while _not_ holding pps_mutex.
	 * pps_{lock,unlock}() do these steps in the correct order, so one
	 * should use them always.
	 */

	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		struct intel_dp *intel_dp;

		if (encoder->type != INTEL_OUTPUT_EDP)
			continue;

		intel_dp = enc_to_intel_dp(&encoder->base);
		intel_dp->pps_pipe = INVALID_PIPE;
	}
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}

static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);

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	if (IS_BROXTON(dev))
		return BXT_PP_CONTROL(0);
	else if (HAS_PCH_SPLIT(dev))
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		return PCH_PP_CONTROL;
	else
		return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
}

static u32 _pp_stat_reg(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);

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	if (IS_BROXTON(dev))
		return BXT_PP_STATUS(0);
	else if (HAS_PCH_SPLIT(dev))
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		return PCH_PP_STATUS;
	else
		return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
}

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/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
   This function only applicable when panel PM state is not to be tracked */
static int edp_notify_handler(struct notifier_block *this, unsigned long code,
			      void *unused)
{
	struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
						 edp_notifier);
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp_div;
	u32 pp_ctrl_reg, pp_div_reg;

	if (!is_edp(intel_dp) || code != SYS_RESTART)
		return 0;

605
	pps_lock(intel_dp);
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606

607
	if (IS_VALLEYVIEW(dev)) {
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608 609
		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);

610 611 612 613 614 615 616 617 618 619 620
		pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
		pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
		pp_div = I915_READ(pp_div_reg);
		pp_div &= PP_REFERENCE_DIVIDER_MASK;

		/* 0x1F write to PP_DIV_REG sets max cycle delay */
		I915_WRITE(pp_div_reg, pp_div | 0x1F);
		I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
		msleep(intel_dp->panel_power_cycle_delay);
	}

621
	pps_unlock(intel_dp);
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622

623 624 625
	return 0;
}

626
static bool edp_have_panel_power(struct intel_dp *intel_dp)
627
{
628
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
629 630
	struct drm_i915_private *dev_priv = dev->dev_private;

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631 632
	lockdep_assert_held(&dev_priv->pps_mutex);

633 634 635 636
	if (IS_VALLEYVIEW(dev) &&
	    intel_dp->pps_pipe == INVALID_PIPE)
		return false;

637
	return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
638 639
}

640
static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
641
{
642
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
643 644
	struct drm_i915_private *dev_priv = dev->dev_private;

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645 646
	lockdep_assert_held(&dev_priv->pps_mutex);

647 648 649 650
	if (IS_VALLEYVIEW(dev) &&
	    intel_dp->pps_pipe == INVALID_PIPE)
		return false;

651
	return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
652 653
}

654 655 656
static void
intel_dp_check_edp(struct intel_dp *intel_dp)
{
657
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
658
	struct drm_i915_private *dev_priv = dev->dev_private;
659

660 661
	if (!is_edp(intel_dp))
		return;
662

663
	if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
664 665
		WARN(1, "eDP powered off while attempting aux channel communication.\n");
		DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
666 667
			      I915_READ(_pp_stat_reg(intel_dp)),
			      I915_READ(_pp_ctrl_reg(intel_dp)));
668 669 670
	}
}

671 672 673 674 675 676
static uint32_t
intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
677
	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
678 679 680
	uint32_t status;
	bool done;

681
#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
682
	if (has_aux_irq)
683
		done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
684
					  msecs_to_jiffies_timeout(10));
685 686 687 688 689 690 691 692 693 694
	else
		done = wait_for_atomic(C, 10) == 0;
	if (!done)
		DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
			  has_aux_irq);
#undef C

	return status;
}

695
static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
696
{
697 698
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
699

700 701 702
	/*
	 * The clock divider is based off the hrawclk, and would like to run at
	 * 2MHz.  So, take the hrawclk value and divide by 2 and use that
703
	 */
704 705 706 707 708 709 710
	return index ? 0 : intel_hrawclk(dev) / 2;
}

static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
711
	struct drm_i915_private *dev_priv = dev->dev_private;
712 713 714 715 716

	if (index)
		return 0;

	if (intel_dig_port->port == PORT_A) {
717 718
		return DIV_ROUND_UP(dev_priv->cdclk_freq, 2000);

719 720 721 722 723 724 725 726 727 728 729 730 731 732
	} else {
		return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
	}
}

static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (intel_dig_port->port == PORT_A) {
		if (index)
			return 0;
733
		return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
734 735
	} else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
		/* Workaround for non-ULT HSW */
736 737 738 739 740
		switch (index) {
		case 0: return 63;
		case 1: return 72;
		default: return 0;
		}
741
	} else  {
742
		return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
743
	}
744 745
}

746 747 748 749 750
static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
	return index ? 0 : 100;
}

751 752 753 754 755 756 757 758 759 760
static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
	/*
	 * SKL doesn't need us to program the AUX clock divider (Hardware will
	 * derive the clock from CDCLK automatically). We still implement the
	 * get_aux_clock_divider vfunc to plug-in into the existing code.
	 */
	return index ? 0 : 1;
}

761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780
static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
				      bool has_aux_irq,
				      int send_bytes,
				      uint32_t aux_clock_divider)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	uint32_t precharge, timeout;

	if (IS_GEN6(dev))
		precharge = 3;
	else
		precharge = 5;

	if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
		timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
	else
		timeout = DP_AUX_CH_CTL_TIME_OUT_400us;

	return DP_AUX_CH_CTL_SEND_BUSY |
781
	       DP_AUX_CH_CTL_DONE |
782
	       (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
783
	       DP_AUX_CH_CTL_TIME_OUT_ERROR |
784
	       timeout |
785
	       DP_AUX_CH_CTL_RECEIVE_ERROR |
786 787
	       (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
	       (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788
	       (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
789 790
}

791 792 793 794 795 796 797 798 799 800 801 802 803 804 805
static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
				      bool has_aux_irq,
				      int send_bytes,
				      uint32_t unused)
{
	return DP_AUX_CH_CTL_SEND_BUSY |
	       DP_AUX_CH_CTL_DONE |
	       (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
	       DP_AUX_CH_CTL_TIME_OUT_ERROR |
	       DP_AUX_CH_CTL_TIME_OUT_1600us |
	       DP_AUX_CH_CTL_RECEIVE_ERROR |
	       (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
	       DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
}

806 807
static int
intel_dp_aux_ch(struct intel_dp *intel_dp,
808
		const uint8_t *send, int send_bytes,
809 810 811 812 813 814 815
		uint8_t *recv, int recv_size)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
	uint32_t ch_data = ch_ctl + 4;
816
	uint32_t aux_clock_divider;
817 818
	int i, ret, recv_bytes;
	uint32_t status;
819
	int try, clock = 0;
820
	bool has_aux_irq = HAS_AUX_IRQ(dev);
821 822
	bool vdd;

823
	pps_lock(intel_dp);
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824

825 826 827 828 829 830
	/*
	 * We will be called with VDD already enabled for dpcd/edid/oui reads.
	 * In such cases we want to leave VDD enabled and it's up to upper layers
	 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
	 * ourselves.
	 */
831
	vdd = edp_panel_vdd_on(intel_dp);
832 833 834 835 836 837 838 839

	/* dp aux is extremely sensitive to irq latency, hence request the
	 * lowest possible wakeup latency and so prevent the cpu from going into
	 * deep sleep states.
	 */
	pm_qos_update_request(&dev_priv->pm_qos, 0);

	intel_dp_check_edp(intel_dp);
840

841 842
	intel_aux_display_runtime_get(dev_priv);

843 844
	/* Try to wait for any previous AUX channel activity */
	for (try = 0; try < 3; try++) {
845
		status = I915_READ_NOTRACE(ch_ctl);
846 847 848 849 850 851
		if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
			break;
		msleep(1);
	}

	if (try == 3) {
852 853 854 855 856 857 858 859 860
		static u32 last_status = -1;
		const u32 status = I915_READ(ch_ctl);

		if (status != last_status) {
			WARN(1, "dp_aux_ch not started status 0x%08x\n",
			     status);
			last_status = status;
		}

861 862
		ret = -EBUSY;
		goto out;
863 864
	}

865 866 867 868 869 870
	/* Only 5 data registers! */
	if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
		ret = -E2BIG;
		goto out;
	}

871
	while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
872 873 874 875
		u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
							  has_aux_irq,
							  send_bytes,
							  aux_clock_divider);
876

877 878 879 880 881
		/* Must try at least 3 times according to DP spec */
		for (try = 0; try < 5; try++) {
			/* Load the send data into the aux channel data registers */
			for (i = 0; i < send_bytes; i += 4)
				I915_WRITE(ch_data + i,
882 883
					   intel_dp_pack_aux(send + i,
							     send_bytes - i));
884 885

			/* Send the command and wait for it to complete */
886
			I915_WRITE(ch_ctl, send_ctl);
887 888 889 890 891 892 893 894 895 896

			status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);

			/* Clear done status and any errors */
			I915_WRITE(ch_ctl,
				   status |
				   DP_AUX_CH_CTL_DONE |
				   DP_AUX_CH_CTL_TIME_OUT_ERROR |
				   DP_AUX_CH_CTL_RECEIVE_ERROR);

897
			if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
898
				continue;
899 900 901 902 903 904 905 906

			/* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
			 *   400us delay required for errors and timeouts
			 *   Timeout errors from the HW already meet this
			 *   requirement so skip to next iteration
			 */
			if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
				usleep_range(400, 500);
907
				continue;
908
			}
909
			if (status & DP_AUX_CH_CTL_DONE)
910
				goto done;
911
		}
912 913 914
	}

	if ((status & DP_AUX_CH_CTL_DONE) == 0) {
915
		DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
916 917
		ret = -EBUSY;
		goto out;
918 919
	}

920
done:
921 922 923
	/* Check for timeout or receive error.
	 * Timeouts occur when the sink is not connected
	 */
924
	if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
925
		DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
926 927
		ret = -EIO;
		goto out;
928
	}
929 930 931

	/* Timeouts occur when the device isn't connected, so they're
	 * "normal" -- don't fill the kernel log with these */
932
	if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
933
		DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
934 935
		ret = -ETIMEDOUT;
		goto out;
936 937 938 939 940 941 942
	}

	/* Unload any bytes sent back from the other side */
	recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
		      DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
	if (recv_bytes > recv_size)
		recv_bytes = recv_size;
943

944
	for (i = 0; i < recv_bytes; i += 4)
945 946
		intel_dp_unpack_aux(I915_READ(ch_data + i),
				    recv + i, recv_bytes - i);
947

948 949 950
	ret = recv_bytes;
out:
	pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
951
	intel_aux_display_runtime_put(dev_priv);
952

953 954 955
	if (vdd)
		edp_panel_vdd_off(intel_dp, false);

956
	pps_unlock(intel_dp);
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957

958
	return ret;
959 960
}

961 962
#define BARE_ADDRESS_SIZE	3
#define HEADER_SIZE		(BARE_ADDRESS_SIZE + 1)
963 964
static ssize_t
intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
965
{
966 967 968
	struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
	uint8_t txbuf[20], rxbuf[20];
	size_t txsize, rxsize;
969 970
	int ret;

971 972 973
	txbuf[0] = (msg->request << 4) |
		((msg->address >> 16) & 0xf);
	txbuf[1] = (msg->address >> 8) & 0xff;
974 975
	txbuf[2] = msg->address & 0xff;
	txbuf[3] = msg->size - 1;
976

977 978 979
	switch (msg->request & ~DP_AUX_I2C_MOT) {
	case DP_AUX_NATIVE_WRITE:
	case DP_AUX_I2C_WRITE:
980
		txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
981
		rxsize = 2; /* 0 or 1 data bytes */
982

983 984
		if (WARN_ON(txsize > 20))
			return -E2BIG;
985

986
		memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
987

988 989 990
		ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
		if (ret > 0) {
			msg->reply = rxbuf[0] >> 4;
991

992 993 994 995 996 997 998
			if (ret > 1) {
				/* Number of bytes written in a short write. */
				ret = clamp_t(int, rxbuf[1], 0, msg->size);
			} else {
				/* Return payload size. */
				ret = msg->size;
			}
999 1000
		}
		break;
1001

1002 1003
	case DP_AUX_NATIVE_READ:
	case DP_AUX_I2C_READ:
1004
		txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1005
		rxsize = msg->size + 1;
1006

1007 1008
		if (WARN_ON(rxsize > 20))
			return -E2BIG;
1009

1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020
		ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
		if (ret > 0) {
			msg->reply = rxbuf[0] >> 4;
			/*
			 * Assume happy day, and copy the data. The caller is
			 * expected to check msg->reply before touching it.
			 *
			 * Return payload size.
			 */
			ret--;
			memcpy(msg->buffer, rxbuf + 1, ret);
1021
		}
1022 1023 1024 1025 1026
		break;

	default:
		ret = -EINVAL;
		break;
1027
	}
1028

1029
	return ret;
1030 1031
}

1032 1033 1034 1035
static void
intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1036
	struct drm_i915_private *dev_priv = dev->dev_private;
1037 1038
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	enum port port = intel_dig_port->port;
1039
	struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port];
1040
	const char *name = NULL;
1041
	uint32_t porte_aux_ctl_reg = DPA_AUX_CH_CTL;
1042 1043
	int ret;

1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063
	/* On SKL we don't have Aux for port E so we rely on VBT to set
	 * a proper alternate aux channel.
	 */
	if (IS_SKYLAKE(dev) && port == PORT_E) {
		switch (info->alternate_aux_channel) {
		case DP_AUX_B:
			porte_aux_ctl_reg = DPB_AUX_CH_CTL;
			break;
		case DP_AUX_C:
			porte_aux_ctl_reg = DPC_AUX_CH_CTL;
			break;
		case DP_AUX_D:
			porte_aux_ctl_reg = DPD_AUX_CH_CTL;
			break;
		case DP_AUX_A:
		default:
			porte_aux_ctl_reg = DPA_AUX_CH_CTL;
		}
	}

1064 1065 1066
	switch (port) {
	case PORT_A:
		intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
1067
		name = "DPDDC-A";
1068
		break;
1069 1070
	case PORT_B:
		intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
1071
		name = "DPDDC-B";
1072
		break;
1073 1074
	case PORT_C:
		intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
1075
		name = "DPDDC-C";
1076
		break;
1077 1078
	case PORT_D:
		intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
1079
		name = "DPDDC-D";
1080
		break;
1081 1082 1083 1084
	case PORT_E:
		intel_dp->aux_ch_ctl_reg = porte_aux_ctl_reg;
		name = "DPDDC-E";
		break;
1085 1086
	default:
		BUG();
1087 1088
	}

1089 1090 1091 1092 1093 1094 1095 1096 1097
	/*
	 * The AUX_CTL register is usually DP_CTL + 0x10.
	 *
	 * On Haswell and Broadwell though:
	 *   - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
	 *   - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
	 *
	 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
	 */
1098
	if (!IS_HASWELL(dev) && !IS_BROADWELL(dev) && port != PORT_E)
1099
		intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
1100

1101
	intel_dp->aux.name = name;
1102 1103
	intel_dp->aux.dev = dev->dev;
	intel_dp->aux.transfer = intel_dp_aux_transfer;
1104

1105 1106
	DRM_DEBUG_KMS("registering %s bus for %s\n", name,
		      connector->base.kdev->kobj.name);
1107

1108
	ret = drm_dp_aux_register(&intel_dp->aux);
1109
	if (ret < 0) {
1110
		DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1111 1112
			  name, ret);
		return;
1113
	}
1114

1115 1116 1117 1118 1119
	ret = sysfs_create_link(&connector->base.kdev->kobj,
				&intel_dp->aux.ddc.dev.kobj,
				intel_dp->aux.ddc.dev.kobj.name);
	if (ret < 0) {
		DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
1120
		drm_dp_aux_unregister(&intel_dp->aux);
1121
	}
1122 1123
}

1124 1125 1126 1127 1128
static void
intel_dp_connector_unregister(struct intel_connector *intel_connector)
{
	struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);

1129 1130 1131
	if (!intel_connector->mst_port)
		sysfs_remove_link(&intel_connector->base.kdev->kobj,
				  intel_dp->aux.ddc.dev.kobj.name);
1132 1133 1134
	intel_connector_unregister(intel_connector);
}

1135
static void
1136
skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
1137 1138 1139
{
	u32 ctrl1;

1140 1141 1142
	memset(&pipe_config->dpll_hw_state, 0,
	       sizeof(pipe_config->dpll_hw_state));

1143 1144 1145 1146 1147
	pipe_config->ddi_pll_sel = SKL_DPLL0;
	pipe_config->dpll_hw_state.cfgcr1 = 0;
	pipe_config->dpll_hw_state.cfgcr2 = 0;

	ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
1148
	switch (pipe_config->port_clock / 2) {
1149
	case 81000:
1150
		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
1151 1152
					      SKL_DPLL0);
		break;
1153
	case 135000:
1154
		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350,
1155 1156
					      SKL_DPLL0);
		break;
1157
	case 270000:
1158
		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700,
1159 1160
					      SKL_DPLL0);
		break;
1161
	case 162000:
1162
		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620,
1163 1164 1165 1166 1167 1168
					      SKL_DPLL0);
		break;
	/* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
	results in CDCLK change. Need to handle the change of CDCLK by
	disabling pipes and re-enabling them */
	case 108000:
1169
		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
1170 1171 1172
					      SKL_DPLL0);
		break;
	case 216000:
1173
		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
1174 1175 1176
					      SKL_DPLL0);
		break;

1177 1178 1179 1180
	}
	pipe_config->dpll_hw_state.ctrl1 = ctrl1;
}

1181
static void
1182
hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config)
1183
{
1184 1185 1186
	memset(&pipe_config->dpll_hw_state, 0,
	       sizeof(pipe_config->dpll_hw_state));

1187 1188
	switch (pipe_config->port_clock / 2) {
	case 81000:
1189 1190
		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
		break;
1191
	case 135000:
1192 1193
		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
		break;
1194
	case 270000:
1195 1196 1197 1198 1199
		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
		break;
	}
}

1200
static int
1201
intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
1202
{
1203 1204 1205
	if (intel_dp->num_sink_rates) {
		*sink_rates = intel_dp->sink_rates;
		return intel_dp->num_sink_rates;
1206
	}
1207 1208 1209 1210

	*sink_rates = default_rates;

	return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
1211 1212
}

1213
static int
1214
intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
1215
{
1216 1217 1218 1219
	if (IS_BROXTON(dev)) {
		*source_rates = bxt_rates;
		return ARRAY_SIZE(bxt_rates);
	} else if (IS_SKYLAKE(dev)) {
1220 1221
		*source_rates = skl_rates;
		return ARRAY_SIZE(skl_rates);
1222 1223 1224
	} else if (IS_CHERRYVIEW(dev)) {
		*source_rates = chv_rates;
		return ARRAY_SIZE(chv_rates);
1225
	}
1226 1227 1228

	*source_rates = default_rates;

1229 1230 1231 1232 1233 1234 1235 1236
	if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
		/* WaDisableHBR2:skl */
		return (DP_LINK_BW_2_7 >> 3) + 1;
	else if (INTEL_INFO(dev)->gen >= 8 ||
	    (IS_HASWELL(dev) && !IS_HSW_ULX(dev)))
		return (DP_LINK_BW_5_4 >> 3) + 1;
	else
		return (DP_LINK_BW_2_7 >> 3) + 1;
1237 1238
}

1239 1240
static void
intel_dp_set_clock(struct intel_encoder *encoder,
1241
		   struct intel_crtc_state *pipe_config)
1242 1243
{
	struct drm_device *dev = encoder->base.dev;
1244 1245
	const struct dp_link_dpll *divisor = NULL;
	int i, count = 0;
1246 1247

	if (IS_G4X(dev)) {
1248 1249
		divisor = gen4_dpll;
		count = ARRAY_SIZE(gen4_dpll);
1250
	} else if (HAS_PCH_SPLIT(dev)) {
1251 1252
		divisor = pch_dpll;
		count = ARRAY_SIZE(pch_dpll);
1253 1254 1255
	} else if (IS_CHERRYVIEW(dev)) {
		divisor = chv_dpll;
		count = ARRAY_SIZE(chv_dpll);
1256
	} else if (IS_VALLEYVIEW(dev)) {
1257 1258
		divisor = vlv_dpll;
		count = ARRAY_SIZE(vlv_dpll);
1259
	}
1260 1261 1262

	if (divisor && count) {
		for (i = 0; i < count; i++) {
1263
			if (pipe_config->port_clock == divisor[i].clock) {
1264 1265 1266 1267 1268
				pipe_config->dpll = divisor[i].dpll;
				pipe_config->clock_set = true;
				break;
			}
		}
1269 1270 1271
	}
}

1272 1273
static int intersect_rates(const int *source_rates, int source_len,
			   const int *sink_rates, int sink_len,
1274
			   int *common_rates)
1275 1276 1277 1278 1279
{
	int i = 0, j = 0, k = 0;

	while (i < source_len && j < sink_len) {
		if (source_rates[i] == sink_rates[j]) {
1280 1281
			if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
				return k;
1282
			common_rates[k] = source_rates[i];
1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294
			++k;
			++i;
			++j;
		} else if (source_rates[i] < sink_rates[j]) {
			++i;
		} else {
			++j;
		}
	}
	return k;
}

1295 1296
static int intel_dp_common_rates(struct intel_dp *intel_dp,
				 int *common_rates)
1297 1298 1299 1300 1301 1302 1303 1304 1305 1306
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	const int *source_rates, *sink_rates;
	int source_len, sink_len;

	sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
	source_len = intel_dp_source_rates(dev, &source_rates);

	return intersect_rates(source_rates, source_len,
			       sink_rates, sink_len,
1307
			       common_rates);
1308 1309
}

1310 1311 1312 1313 1314 1315 1316 1317
static void snprintf_int_array(char *str, size_t len,
			       const int *array, int nelem)
{
	int i;

	str[0] = '\0';

	for (i = 0; i < nelem; i++) {
1318
		int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329
		if (r >= len)
			return;
		str += r;
		len -= r;
	}
}

static void intel_dp_print_rates(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	const int *source_rates, *sink_rates;
1330 1331
	int source_len, sink_len, common_len;
	int common_rates[DP_MAX_SUPPORTED_RATES];
1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344
	char str[128]; /* FIXME: too big for stack? */

	if ((drm_debug & DRM_UT_KMS) == 0)
		return;

	source_len = intel_dp_source_rates(dev, &source_rates);
	snprintf_int_array(str, sizeof(str), source_rates, source_len);
	DRM_DEBUG_KMS("source rates: %s\n", str);

	sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
	snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
	DRM_DEBUG_KMS("sink rates: %s\n", str);

1345 1346 1347
	common_len = intel_dp_common_rates(intel_dp, common_rates);
	snprintf_int_array(str, sizeof(str), common_rates, common_len);
	DRM_DEBUG_KMS("common rates: %s\n", str);
1348 1349
}

1350
static int rate_to_index(int find, const int *rates)
1351 1352 1353 1354 1355 1356 1357 1358 1359 1360
{
	int i = 0;

	for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
		if (find == rates[i])
			break;

	return i;
}

1361 1362 1363 1364 1365 1366
int
intel_dp_max_link_rate(struct intel_dp *intel_dp)
{
	int rates[DP_MAX_SUPPORTED_RATES] = {};
	int len;

1367
	len = intel_dp_common_rates(intel_dp, rates);
1368 1369 1370 1371 1372 1373
	if (WARN_ON(len <= 0))
		return 162000;

	return rates[rate_to_index(0, rates) - 1];
}

1374 1375
int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
{
1376
	return rate_to_index(rate, intel_dp->sink_rates);
1377 1378
}

1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391
static void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
				  uint8_t *link_bw, uint8_t *rate_select)
{
	if (intel_dp->num_sink_rates) {
		*link_bw = 0;
		*rate_select =
			intel_dp_rate_select(intel_dp, port_clock);
	} else {
		*link_bw = drm_dp_link_rate_to_bw_code(port_clock);
		*rate_select = 0;
	}
}

P
Paulo Zanoni 已提交
1392
bool
1393
intel_dp_compute_config(struct intel_encoder *encoder,
1394
			struct intel_crtc_state *pipe_config)
1395
{
1396
	struct drm_device *dev = encoder->base.dev;
1397
	struct drm_i915_private *dev_priv = dev->dev_private;
1398
	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1399
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1400
	enum port port = dp_to_dig_port(intel_dp)->port;
1401
	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1402
	struct intel_connector *intel_connector = intel_dp->attached_connector;
1403
	int lane_count, clock;
1404
	int min_lane_count = 1;
1405
	int max_lane_count = intel_dp_max_lane_count(intel_dp);
1406
	/* Conveniently, the link BW constants become indices with a shift...*/
1407
	int min_clock = 0;
1408
	int max_clock;
1409
	int bpp, mode_rate;
1410
	int link_avail, link_clock;
1411 1412
	int common_rates[DP_MAX_SUPPORTED_RATES] = {};
	int common_len;
1413
	uint8_t link_bw, rate_select;
1414

1415
	common_len = intel_dp_common_rates(intel_dp, common_rates);
1416 1417

	/* No common link rates between source and sink */
1418
	WARN_ON(common_len <= 0);
1419

1420
	max_clock = common_len - 1;
1421

1422
	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
1423 1424
		pipe_config->has_pch_encoder = true;

1425
	pipe_config->has_dp_encoder = true;
1426
	pipe_config->has_drrs = false;
1427
	pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
1428

1429 1430 1431
	if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
		intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
				       adjusted_mode);
1432 1433 1434

		if (INTEL_INFO(dev)->gen >= 9) {
			int ret;
1435
			ret = skl_update_scaler_crtc(pipe_config);
1436 1437 1438 1439
			if (ret)
				return ret;
		}

1440 1441 1442 1443
		if (!HAS_PCH_SPLIT(dev))
			intel_gmch_panel_fitting(intel_crtc, pipe_config,
						 intel_connector->panel.fitting_mode);
		else
1444 1445
			intel_pch_panel_fitting(intel_crtc, pipe_config,
						intel_connector->panel.fitting_mode);
1446 1447
	}

1448
	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1449 1450
		return false;

1451
	DRM_DEBUG_KMS("DP link computation with max lane count %i "
1452
		      "max bw %d pixel clock %iKHz\n",
1453
		      max_lane_count, common_rates[max_clock],
1454
		      adjusted_mode->crtc_clock);
1455

1456 1457
	/* Walk through all bpp values. Luckily they're all nicely spaced with 2
	 * bpc in between. */
1458
	bpp = pipe_config->pipe_bpp;
1459
	if (is_edp(intel_dp)) {
1460 1461 1462 1463

		/* Get bpp from vbt only for panels that dont have bpp in edid */
		if (intel_connector->base.display_info.bpc == 0 &&
			(dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp)) {
1464 1465 1466 1467 1468
			DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
				      dev_priv->vbt.edp_bpp);
			bpp = dev_priv->vbt.edp_bpp;
		}

1469 1470 1471 1472 1473 1474 1475 1476 1477
		/*
		 * Use the maximum clock and number of lanes the eDP panel
		 * advertizes being capable of. The panels are generally
		 * designed to support only a single clock and lane
		 * configuration, and typically these values correspond to the
		 * native resolution of the panel.
		 */
		min_lane_count = max_lane_count;
		min_clock = max_clock;
1478
	}
1479

1480
	for (; bpp >= 6*3; bpp -= 2*3) {
1481 1482
		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
						   bpp);
1483

1484
		for (clock = min_clock; clock <= max_clock; clock++) {
1485 1486 1487 1488
			for (lane_count = min_lane_count;
				lane_count <= max_lane_count;
				lane_count <<= 1) {

1489
				link_clock = common_rates[clock];
1490 1491 1492 1493 1494 1495 1496 1497 1498
				link_avail = intel_dp_max_data_rate(link_clock,
								    lane_count);

				if (mode_rate <= link_avail) {
					goto found;
				}
			}
		}
	}
1499

1500
	return false;
1501

1502
found:
1503 1504 1505 1506 1507 1508
	if (intel_dp->color_range_auto) {
		/*
		 * See:
		 * CEA-861-E - 5.1 Default Encoding Parameters
		 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
		 */
1509 1510 1511 1512 1513
		pipe_config->limited_color_range =
			bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
	} else {
		pipe_config->limited_color_range =
			intel_dp->limited_color_range;
1514 1515
	}

1516
	pipe_config->lane_count = lane_count;
1517

1518
	pipe_config->pipe_bpp = bpp;
1519
	pipe_config->port_clock = common_rates[clock];
1520

1521 1522 1523 1524 1525
	intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
			      &link_bw, &rate_select);

	DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
		      link_bw, rate_select, pipe_config->lane_count,
1526
		      pipe_config->port_clock, bpp);
1527 1528
	DRM_DEBUG_KMS("DP link bw required %i available %i\n",
		      mode_rate, link_avail);
1529

1530
	intel_link_compute_m_n(bpp, lane_count,
1531 1532
			       adjusted_mode->crtc_clock,
			       pipe_config->port_clock,
1533
			       &pipe_config->dp_m_n);
1534

1535
	if (intel_connector->panel.downclock_mode != NULL &&
1536
		dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1537
			pipe_config->has_drrs = true;
1538 1539 1540 1541 1542 1543
			intel_link_compute_m_n(bpp, lane_count,
				intel_connector->panel.downclock_mode->clock,
				pipe_config->port_clock,
				&pipe_config->dp_m2_n2);
	}

1544
	if (IS_SKYLAKE(dev) && is_edp(intel_dp))
1545
		skl_edp_set_pll_config(pipe_config);
1546 1547
	else if (IS_BROXTON(dev))
		/* handled in ddi */;
1548
	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1549
		hsw_dp_set_ddi_pll_sel(pipe_config);
1550
	else
1551
		intel_dp_set_clock(encoder, pipe_config);
1552

1553
	return true;
1554 1555
}

1556
static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
1557
{
1558 1559 1560
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
	struct drm_device *dev = crtc->base.dev;
1561 1562 1563
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

1564 1565
	DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
		      crtc->config->port_clock);
1566 1567 1568
	dpa_ctl = I915_READ(DP_A);
	dpa_ctl &= ~DP_PLL_FREQ_MASK;

1569
	if (crtc->config->port_clock == 162000) {
1570 1571 1572 1573
		/* For a long time we've carried around a ILK-DevA w/a for the
		 * 160MHz clock. If we're really unlucky, it's still required.
		 */
		DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1574
		dpa_ctl |= DP_PLL_FREQ_160MHZ;
1575
		intel_dp->DP |= DP_PLL_FREQ_160MHZ;
1576 1577
	} else {
		dpa_ctl |= DP_PLL_FREQ_270MHZ;
1578
		intel_dp->DP |= DP_PLL_FREQ_270MHZ;
1579
	}
1580

1581 1582 1583 1584 1585 1586
	I915_WRITE(DP_A, dpa_ctl);

	POSTING_READ(DP_A);
	udelay(500);
}

1587 1588 1589 1590 1591 1592 1593
void intel_dp_set_link_params(struct intel_dp *intel_dp,
			      const struct intel_crtc_state *pipe_config)
{
	intel_dp->link_rate = pipe_config->port_clock;
	intel_dp->lane_count = pipe_config->lane_count;
}

1594
static void intel_dp_prepare(struct intel_encoder *encoder)
1595
{
1596
	struct drm_device *dev = encoder->base.dev;
1597
	struct drm_i915_private *dev_priv = dev->dev_private;
1598
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1599
	enum port port = dp_to_dig_port(intel_dp)->port;
1600
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1601
	struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
1602

1603 1604
	intel_dp_set_link_params(intel_dp, crtc->config);

1605
	/*
K
Keith Packard 已提交
1606
	 * There are four kinds of DP registers:
1607 1608
	 *
	 * 	IBX PCH
K
Keith Packard 已提交
1609 1610
	 * 	SNB CPU
	 *	IVB CPU
1611 1612 1613 1614 1615 1616 1617 1618 1619 1620
	 * 	CPT PCH
	 *
	 * IBX PCH and CPU are the same for almost everything,
	 * except that the CPU DP PLL is configured in this
	 * register
	 *
	 * CPT PCH is quite different, having many bits moved
	 * to the TRANS_DP_CTL register instead. That
	 * configuration happens (oddly) in ironlake_pch_enable
	 */
1621

1622 1623 1624 1625
	/* Preserve the BIOS-computed detected bit. This is
	 * supposed to be read-only.
	 */
	intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1626

1627 1628
	/* Handle DP bits in common between all three register formats */
	intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1629
	intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count);
1630

1631
	if (crtc->config->has_audio)
C
Chris Wilson 已提交
1632
		intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1633

1634
	/* Split out the IBX/CPU vs CPT settings */
1635

1636
	if (IS_GEN7(dev) && port == PORT_A) {
K
Keith Packard 已提交
1637 1638 1639 1640 1641 1642
		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
			intel_dp->DP |= DP_SYNC_HS_HIGH;
		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
			intel_dp->DP |= DP_SYNC_VS_HIGH;
		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;

1643
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
K
Keith Packard 已提交
1644 1645
			intel_dp->DP |= DP_ENHANCED_FRAMING;

1646
		intel_dp->DP |= crtc->pipe << 29;
1647
	} else if (HAS_PCH_CPT(dev) && port != PORT_A) {
1648 1649
		u32 trans_dp;

1650
		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1651 1652 1653 1654 1655 1656 1657

		trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
			trans_dp |= TRANS_DP_ENH_FRAMING;
		else
			trans_dp &= ~TRANS_DP_ENH_FRAMING;
		I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1658
	} else {
1659 1660 1661
		if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
		    crtc->config->limited_color_range)
			intel_dp->DP |= DP_COLOR_RANGE_16_235;
1662 1663 1664 1665 1666 1667 1668

		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
			intel_dp->DP |= DP_SYNC_HS_HIGH;
		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
			intel_dp->DP |= DP_SYNC_VS_HIGH;
		intel_dp->DP |= DP_LINK_TRAIN_OFF;

1669
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1670 1671
			intel_dp->DP |= DP_ENHANCED_FRAMING;

1672
		if (IS_CHERRYVIEW(dev))
1673
			intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1674 1675
		else if (crtc->pipe == PIPE_B)
			intel_dp->DP |= DP_PIPEB_SELECT;
1676
	}
1677 1678
}

1679 1680
#define IDLE_ON_MASK		(PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
#define IDLE_ON_VALUE   	(PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1681

1682 1683
#define IDLE_OFF_MASK		(PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
#define IDLE_OFF_VALUE		(0     | PP_SEQUENCE_NONE | 0                     | 0)
1684

1685 1686
#define IDLE_CYCLE_MASK		(PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
#define IDLE_CYCLE_VALUE	(0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1687

1688
static void wait_panel_status(struct intel_dp *intel_dp,
1689 1690
				       u32 mask,
				       u32 value)
1691
{
1692
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1693
	struct drm_i915_private *dev_priv = dev->dev_private;
1694 1695
	u32 pp_stat_reg, pp_ctrl_reg;

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1696 1697
	lockdep_assert_held(&dev_priv->pps_mutex);

1698 1699
	pp_stat_reg = _pp_stat_reg(intel_dp);
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1700

1701
	DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1702 1703 1704
			mask, value,
			I915_READ(pp_stat_reg),
			I915_READ(pp_ctrl_reg));
1705

1706
	if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1707
		DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1708 1709
				I915_READ(pp_stat_reg),
				I915_READ(pp_ctrl_reg));
1710
	}
1711 1712

	DRM_DEBUG_KMS("Wait complete\n");
1713
}
1714

1715
static void wait_panel_on(struct intel_dp *intel_dp)
1716 1717
{
	DRM_DEBUG_KMS("Wait for panel power on\n");
1718
	wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1719 1720
}

1721
static void wait_panel_off(struct intel_dp *intel_dp)
1722 1723
{
	DRM_DEBUG_KMS("Wait for panel power off time\n");
1724
	wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1725 1726
}

1727
static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1728 1729
{
	DRM_DEBUG_KMS("Wait for panel power cycle\n");
1730 1731 1732 1733 1734 1735

	/* When we disable the VDD override bit last we have to do the manual
	 * wait. */
	wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
				       intel_dp->panel_power_cycle_delay);

1736
	wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1737 1738
}

1739
static void wait_backlight_on(struct intel_dp *intel_dp)
1740 1741 1742 1743 1744
{
	wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
				       intel_dp->backlight_on_delay);
}

1745
static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1746 1747 1748 1749
{
	wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
				       intel_dp->backlight_off_delay);
}
1750

1751 1752 1753 1754
/* Read the current pp_control value, unlocking the register if it
 * is locked
 */

1755
static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1756
{
1757 1758 1759
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 control;
1760

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1761 1762
	lockdep_assert_held(&dev_priv->pps_mutex);

1763
	control = I915_READ(_pp_ctrl_reg(intel_dp));
1764 1765 1766 1767
	if (!IS_BROXTON(dev)) {
		control &= ~PANEL_UNLOCK_MASK;
		control |= PANEL_UNLOCK_REGS;
	}
1768
	return control;
1769 1770
}

1771 1772 1773 1774 1775
/*
 * Must be paired with edp_panel_vdd_off().
 * Must hold pps_mutex around the whole on/off sequence.
 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
 */
1776
static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1777
{
1778
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1779 1780
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
1781
	struct drm_i915_private *dev_priv = dev->dev_private;
1782
	enum intel_display_power_domain power_domain;
1783
	u32 pp;
1784
	u32 pp_stat_reg, pp_ctrl_reg;
1785
	bool need_to_disable = !intel_dp->want_panel_vdd;
1786

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1787 1788
	lockdep_assert_held(&dev_priv->pps_mutex);

1789
	if (!is_edp(intel_dp))
1790
		return false;
1791

1792
	cancel_delayed_work(&intel_dp->panel_vdd_work);
1793
	intel_dp->want_panel_vdd = true;
1794

1795
	if (edp_have_panel_vdd(intel_dp))
1796
		return need_to_disable;
1797

1798 1799
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_get(dev_priv, power_domain);
1800

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1801 1802
	DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
		      port_name(intel_dig_port->port));
1803

1804 1805
	if (!edp_have_panel_power(intel_dp))
		wait_panel_power_cycle(intel_dp);
1806

1807
	pp = ironlake_get_pp_control(intel_dp);
1808
	pp |= EDP_FORCE_VDD;
1809

1810 1811
	pp_stat_reg = _pp_stat_reg(intel_dp);
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1812 1813 1814 1815 1816

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
	DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
			I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1817 1818 1819
	/*
	 * If the panel wasn't on, delay before accessing aux channel
	 */
1820
	if (!edp_have_panel_power(intel_dp)) {
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1821 1822
		DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
			      port_name(intel_dig_port->port));
1823 1824
		msleep(intel_dp->panel_power_up_delay);
	}
1825 1826 1827 1828

	return need_to_disable;
}

1829 1830 1831 1832 1833 1834 1835
/*
 * Must be paired with intel_edp_panel_vdd_off() or
 * intel_edp_panel_off().
 * Nested calls to these functions are not allowed since
 * we drop the lock. Caller must use some higher level
 * locking to prevent nested calls from other threads.
 */
1836
void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1837
{
1838
	bool vdd;
1839

1840 1841 1842
	if (!is_edp(intel_dp))
		return;

1843
	pps_lock(intel_dp);
1844
	vdd = edp_panel_vdd_on(intel_dp);
1845
	pps_unlock(intel_dp);
1846

R
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1847
	I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
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1848
	     port_name(dp_to_dig_port(intel_dp)->port));
1849 1850
}

1851
static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1852
{
1853
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1854
	struct drm_i915_private *dev_priv = dev->dev_private;
1855 1856 1857 1858
	struct intel_digital_port *intel_dig_port =
		dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	enum intel_display_power_domain power_domain;
1859
	u32 pp;
1860
	u32 pp_stat_reg, pp_ctrl_reg;
1861

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1862
	lockdep_assert_held(&dev_priv->pps_mutex);
1863

1864
	WARN_ON(intel_dp->want_panel_vdd);
1865

1866
	if (!edp_have_panel_vdd(intel_dp))
1867
		return;
1868

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1869 1870
	DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
		      port_name(intel_dig_port->port));
1871

1872 1873
	pp = ironlake_get_pp_control(intel_dp);
	pp &= ~EDP_FORCE_VDD;
1874

1875 1876
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
	pp_stat_reg = _pp_stat_reg(intel_dp);
1877

1878 1879
	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
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1880

1881 1882 1883
	/* Make sure sequencer is idle before allowing subsequent activity */
	DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
	I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1884

1885 1886
	if ((pp & POWER_TARGET_ON) == 0)
		intel_dp->last_power_cycle = jiffies;
1887

1888 1889
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_put(dev_priv, power_domain);
1890
}
1891

1892
static void edp_panel_vdd_work(struct work_struct *__work)
1893 1894 1895 1896
{
	struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
						 struct intel_dp, panel_vdd_work);

1897
	pps_lock(intel_dp);
1898 1899
	if (!intel_dp->want_panel_vdd)
		edp_panel_vdd_off_sync(intel_dp);
1900
	pps_unlock(intel_dp);
1901 1902
}

1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915
static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
{
	unsigned long delay;

	/*
	 * Queue the timer to fire a long time from now (relative to the power
	 * down delay) to keep the panel power up across a sequence of
	 * operations.
	 */
	delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
	schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
}

1916 1917 1918 1919 1920
/*
 * Must be paired with edp_panel_vdd_on().
 * Must hold pps_mutex around the whole on/off sequence.
 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
 */
1921
static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1922
{
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1923 1924 1925 1926 1927
	struct drm_i915_private *dev_priv =
		intel_dp_to_dev(intel_dp)->dev_private;

	lockdep_assert_held(&dev_priv->pps_mutex);

1928 1929
	if (!is_edp(intel_dp))
		return;
1930

R
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1931
	I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
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1932
	     port_name(dp_to_dig_port(intel_dp)->port));
1933

1934 1935
	intel_dp->want_panel_vdd = false;

1936
	if (sync)
1937
		edp_panel_vdd_off_sync(intel_dp);
1938 1939
	else
		edp_panel_vdd_schedule_off(intel_dp);
1940 1941
}

1942
static void edp_panel_on(struct intel_dp *intel_dp)
1943
{
1944
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1945
	struct drm_i915_private *dev_priv = dev->dev_private;
1946
	u32 pp;
1947
	u32 pp_ctrl_reg;
1948

1949 1950
	lockdep_assert_held(&dev_priv->pps_mutex);

1951
	if (!is_edp(intel_dp))
1952
		return;
1953

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1954 1955
	DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
		      port_name(dp_to_dig_port(intel_dp)->port));
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1956

1957 1958 1959
	if (WARN(edp_have_panel_power(intel_dp),
		 "eDP port %c panel power already on\n",
		 port_name(dp_to_dig_port(intel_dp)->port)))
1960
		return;
1961

1962
	wait_panel_power_cycle(intel_dp);
1963

1964
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1965
	pp = ironlake_get_pp_control(intel_dp);
1966 1967 1968
	if (IS_GEN5(dev)) {
		/* ILK workaround: disable reset around power sequence */
		pp &= ~PANEL_POWER_RESET;
1969 1970
		I915_WRITE(pp_ctrl_reg, pp);
		POSTING_READ(pp_ctrl_reg);
1971
	}
1972

1973
	pp |= POWER_TARGET_ON;
1974 1975 1976
	if (!IS_GEN5(dev))
		pp |= PANEL_POWER_RESET;

1977 1978
	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1979

1980
	wait_panel_on(intel_dp);
1981
	intel_dp->last_power_on = jiffies;
1982

1983 1984
	if (IS_GEN5(dev)) {
		pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1985 1986
		I915_WRITE(pp_ctrl_reg, pp);
		POSTING_READ(pp_ctrl_reg);
1987
	}
1988
}
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1989

1990 1991 1992 1993 1994 1995 1996
void intel_edp_panel_on(struct intel_dp *intel_dp)
{
	if (!is_edp(intel_dp))
		return;

	pps_lock(intel_dp);
	edp_panel_on(intel_dp);
1997
	pps_unlock(intel_dp);
1998 1999
}

2000 2001

static void edp_panel_off(struct intel_dp *intel_dp)
2002
{
2003 2004
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
2005
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2006
	struct drm_i915_private *dev_priv = dev->dev_private;
2007
	enum intel_display_power_domain power_domain;
2008
	u32 pp;
2009
	u32 pp_ctrl_reg;
2010

2011 2012
	lockdep_assert_held(&dev_priv->pps_mutex);

2013 2014
	if (!is_edp(intel_dp))
		return;
2015

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2016 2017
	DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
		      port_name(dp_to_dig_port(intel_dp)->port));
2018

V
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2019 2020
	WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
	     port_name(dp_to_dig_port(intel_dp)->port));
2021

2022
	pp = ironlake_get_pp_control(intel_dp);
2023 2024
	/* We need to switch off panel power _and_ force vdd, for otherwise some
	 * panels get very unhappy and cease to work. */
2025 2026
	pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
		EDP_BLC_ENABLE);
2027

2028
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2029

2030 2031
	intel_dp->want_panel_vdd = false;

2032 2033
	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
2034

2035
	intel_dp->last_power_cycle = jiffies;
2036
	wait_panel_off(intel_dp);
2037 2038

	/* We got a reference when we enabled the VDD. */
2039 2040
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_put(dev_priv, power_domain);
2041
}
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2042

2043 2044 2045 2046
void intel_edp_panel_off(struct intel_dp *intel_dp)
{
	if (!is_edp(intel_dp))
		return;
V
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2047

2048 2049
	pps_lock(intel_dp);
	edp_panel_off(intel_dp);
2050
	pps_unlock(intel_dp);
2051 2052
}

2053 2054
/* Enable backlight in the panel power control. */
static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2055
{
2056 2057
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
2058 2059
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
2060
	u32 pp_ctrl_reg;
2061

2062 2063 2064 2065 2066 2067
	/*
	 * If we enable the backlight right away following a panel power
	 * on, we may see slight flicker as the panel syncs with the eDP
	 * link.  So delay a bit to make sure the image is solid before
	 * allowing it to appear.
	 */
2068
	wait_backlight_on(intel_dp);
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2069

2070
	pps_lock(intel_dp);
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2071

2072
	pp = ironlake_get_pp_control(intel_dp);
2073
	pp |= EDP_BLC_ENABLE;
2074

2075
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2076 2077 2078

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
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2079

2080
	pps_unlock(intel_dp);
2081 2082
}

2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096
/* Enable backlight PWM and backlight PP control. */
void intel_edp_backlight_on(struct intel_dp *intel_dp)
{
	if (!is_edp(intel_dp))
		return;

	DRM_DEBUG_KMS("\n");

	intel_panel_enable_backlight(intel_dp->attached_connector);
	_intel_edp_backlight_on(intel_dp);
}

/* Disable backlight in the panel power control. */
static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2097
{
2098
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2099 2100
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
2101
	u32 pp_ctrl_reg;
2102

2103 2104 2105
	if (!is_edp(intel_dp))
		return;

2106
	pps_lock(intel_dp);
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2107

2108
	pp = ironlake_get_pp_control(intel_dp);
2109
	pp &= ~EDP_BLC_ENABLE;
2110

2111
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2112 2113 2114

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
2115

2116
	pps_unlock(intel_dp);
V
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2117 2118

	intel_dp->last_backlight_off = jiffies;
2119
	edp_wait_backlight_off(intel_dp);
2120
}
2121

2122 2123 2124 2125 2126 2127 2128
/* Disable backlight PP control and backlight PWM. */
void intel_edp_backlight_off(struct intel_dp *intel_dp)
{
	if (!is_edp(intel_dp))
		return;

	DRM_DEBUG_KMS("\n");
2129

2130
	_intel_edp_backlight_off(intel_dp);
2131
	intel_panel_disable_backlight(intel_dp->attached_connector);
2132
}
2133

2134 2135 2136 2137 2138 2139 2140 2141
/*
 * Hook for controlling the panel power control backlight through the bl_power
 * sysfs attribute. Take care to handle multiple calls.
 */
static void intel_edp_backlight_power(struct intel_connector *connector,
				      bool enable)
{
	struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
V
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2142 2143
	bool is_enabled;

2144
	pps_lock(intel_dp);
V
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2145
	is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2146
	pps_unlock(intel_dp);
2147 2148 2149 2150

	if (is_enabled == enable)
		return;

2151 2152
	DRM_DEBUG_KMS("panel power control backlight %s\n",
		      enable ? "enable" : "disable");
2153 2154 2155 2156 2157 2158 2159

	if (enable)
		_intel_edp_backlight_on(intel_dp);
	else
		_intel_edp_backlight_off(intel_dp);
}

2160
static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
2161
{
2162 2163 2164
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
	struct drm_device *dev = crtc->dev;
2165 2166 2167
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

2168 2169 2170
	assert_pipe_disabled(dev_priv,
			     to_intel_crtc(crtc)->pipe);

2171 2172
	DRM_DEBUG_KMS("\n");
	dpa_ctl = I915_READ(DP_A);
2173 2174 2175 2176 2177 2178 2179 2180 2181
	WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
	WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");

	/* We don't adjust intel_dp->DP while tearing down the link, to
	 * facilitate link retraining (e.g. after hotplug). Hence clear all
	 * enable bits here to ensure that we don't enable too much. */
	intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
	intel_dp->DP |= DP_PLL_ENABLE;
	I915_WRITE(DP_A, intel_dp->DP);
2182 2183
	POSTING_READ(DP_A);
	udelay(200);
2184 2185
}

2186
static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2187
{
2188 2189 2190
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
	struct drm_device *dev = crtc->dev;
2191 2192 2193
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

2194 2195 2196
	assert_pipe_disabled(dev_priv,
			     to_intel_crtc(crtc)->pipe);

2197
	dpa_ctl = I915_READ(DP_A);
2198 2199 2200 2201 2202 2203 2204
	WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
	     "dp pll off, should be on\n");
	WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");

	/* We can't rely on the value tracked for the DP register in
	 * intel_dp->DP because link_down must not change that (otherwise link
	 * re-training will fail. */
2205
	dpa_ctl &= ~DP_PLL_ENABLE;
2206
	I915_WRITE(DP_A, dpa_ctl);
2207
	POSTING_READ(DP_A);
2208 2209 2210
	udelay(200);
}

2211
/* If the sink supports it, try to set the power state appropriately */
2212
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2213 2214 2215 2216 2217 2218 2219 2220
{
	int ret, i;

	/* Should have a valid DPCD by this point */
	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
		return;

	if (mode != DRM_MODE_DPMS_ON) {
2221 2222
		ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
					 DP_SET_POWER_D3);
2223 2224 2225 2226 2227 2228
	} else {
		/*
		 * When turning on, we need to retry for 1ms to give the sink
		 * time to wake up.
		 */
		for (i = 0; i < 3; i++) {
2229 2230
			ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
						 DP_SET_POWER_D0);
2231 2232 2233 2234 2235
			if (ret == 1)
				break;
			msleep(1);
		}
	}
2236 2237 2238 2239

	if (ret != 1)
		DRM_DEBUG_KMS("failed to %s sink power state\n",
			      mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2240 2241
}

2242 2243
static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
				  enum pipe *pipe)
2244
{
2245
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2246
	enum port port = dp_to_dig_port(intel_dp)->port;
2247 2248
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2249 2250 2251 2252
	enum intel_display_power_domain power_domain;
	u32 tmp;

	power_domain = intel_display_port_power_domain(encoder);
2253
	if (!intel_display_power_is_enabled(dev_priv, power_domain))
2254 2255 2256
		return false;

	tmp = I915_READ(intel_dp->output_reg);
2257 2258 2259 2260

	if (!(tmp & DP_PORT_EN))
		return false;

2261
	if (IS_GEN7(dev) && port == PORT_A) {
2262
		*pipe = PORT_TO_PIPE_CPT(tmp);
2263
	} else if (HAS_PCH_CPT(dev) && port != PORT_A) {
2264
		enum pipe p;
2265

2266 2267 2268 2269
		for_each_pipe(dev_priv, p) {
			u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
			if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
				*pipe = p;
2270 2271 2272 2273
				return true;
			}
		}

2274 2275
		DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
			      intel_dp->output_reg);
2276 2277 2278 2279
	} else if (IS_CHERRYVIEW(dev)) {
		*pipe = DP_PORT_TO_PIPE_CHV(tmp);
	} else {
		*pipe = PORT_TO_PIPE(tmp);
2280
	}
2281

2282 2283
	return true;
}
2284

2285
static void intel_dp_get_config(struct intel_encoder *encoder,
2286
				struct intel_crtc_state *pipe_config)
2287 2288 2289
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	u32 tmp, flags = 0;
2290 2291 2292 2293
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = dp_to_dig_port(intel_dp)->port;
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2294
	int dotclock;
2295

2296
	tmp = I915_READ(intel_dp->output_reg);
2297 2298

	pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2299

2300
	if (HAS_PCH_CPT(dev) && port != PORT_A) {
2301 2302 2303
		u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));

		if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2304 2305 2306
			flags |= DRM_MODE_FLAG_PHSYNC;
		else
			flags |= DRM_MODE_FLAG_NHSYNC;
2307

2308
		if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2309 2310 2311 2312
			flags |= DRM_MODE_FLAG_PVSYNC;
		else
			flags |= DRM_MODE_FLAG_NVSYNC;
	} else {
2313
		if (tmp & DP_SYNC_HS_HIGH)
2314 2315 2316
			flags |= DRM_MODE_FLAG_PHSYNC;
		else
			flags |= DRM_MODE_FLAG_NHSYNC;
2317

2318
		if (tmp & DP_SYNC_VS_HIGH)
2319 2320 2321 2322
			flags |= DRM_MODE_FLAG_PVSYNC;
		else
			flags |= DRM_MODE_FLAG_NVSYNC;
	}
2323

2324
	pipe_config->base.adjusted_mode.flags |= flags;
2325

2326 2327 2328 2329
	if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
	    tmp & DP_COLOR_RANGE_16_235)
		pipe_config->limited_color_range = true;

2330 2331
	pipe_config->has_dp_encoder = true;

2332 2333 2334
	pipe_config->lane_count =
		((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;

2335 2336
	intel_dp_get_m_n(crtc, pipe_config);

2337
	if (port == PORT_A) {
2338 2339 2340 2341 2342
		if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
			pipe_config->port_clock = 162000;
		else
			pipe_config->port_clock = 270000;
	}
2343 2344 2345 2346 2347 2348 2349

	dotclock = intel_dotclock_calculate(pipe_config->port_clock,
					    &pipe_config->dp_m_n);

	if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
		ironlake_check_encoder_dotclock(pipe_config, dotclock);

2350
	pipe_config->base.adjusted_mode.crtc_clock = dotclock;
2351

2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370
	if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
	    pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
		/*
		 * This is a big fat ugly hack.
		 *
		 * Some machines in UEFI boot mode provide us a VBT that has 18
		 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
		 * unknown we fail to light up. Yet the same BIOS boots up with
		 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
		 * max, not what it tells us to use.
		 *
		 * Note: This will still be broken if the eDP panel is not lit
		 * up by the BIOS, and thus we can't get the mode at module
		 * load.
		 */
		DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
			      pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
		dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
	}
2371 2372
}

2373
static void intel_disable_dp(struct intel_encoder *encoder)
2374
{
2375
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2376
	struct drm_device *dev = encoder->base.dev;
2377 2378
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);

2379
	if (crtc->config->has_audio)
2380
		intel_audio_codec_disable(encoder);
2381

2382 2383 2384
	if (HAS_PSR(dev) && !HAS_DDI(dev))
		intel_psr_disable(intel_dp);

2385 2386
	/* Make sure the panel is off before trying to change the mode. But also
	 * ensure that we have vdd while we switch off the panel. */
2387
	intel_edp_panel_vdd_on(intel_dp);
2388
	intel_edp_backlight_off(intel_dp);
2389
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2390
	intel_edp_panel_off(intel_dp);
2391

2392 2393
	/* disable the port before the pipe on g4x */
	if (INTEL_INFO(dev)->gen < 5)
2394
		intel_dp_link_down(intel_dp);
2395 2396
}

2397
static void ilk_post_disable_dp(struct intel_encoder *encoder)
2398
{
2399
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2400
	enum port port = dp_to_dig_port(intel_dp)->port;
2401

2402
	intel_dp_link_down(intel_dp);
2403 2404
	if (port == PORT_A)
		ironlake_edp_pll_off(intel_dp);
2405 2406 2407 2408 2409 2410 2411
}

static void vlv_post_disable_dp(struct intel_encoder *encoder)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

	intel_dp_link_down(intel_dp);
2412 2413
}

2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427
static void chv_post_disable_dp(struct intel_encoder *encoder)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
	enum dpio_channel ch = vlv_dport_to_channel(dport);
	enum pipe pipe = intel_crtc->pipe;
	u32 val;

	intel_dp_link_down(intel_dp);

V
Ville Syrjälä 已提交
2428
	mutex_lock(&dev_priv->sb_lock);
2429 2430

	/* Propagate soft reset to data lane reset */
2431
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2432
	val |= CHV_PCS_REQ_SOFTRESET_EN;
2433
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2434

2435 2436 2437 2438 2439 2440 2441 2442 2443
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
	val |= CHV_PCS_REQ_SOFTRESET_EN;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2444
	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2445
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2446

V
Ville Syrjälä 已提交
2447
	mutex_unlock(&dev_priv->sb_lock);
2448 2449
}

2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485
static void
_intel_dp_set_link_train(struct intel_dp *intel_dp,
			 uint32_t *DP,
			 uint8_t dp_train_pat)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = intel_dig_port->port;

	if (HAS_DDI(dev)) {
		uint32_t temp = I915_READ(DP_TP_CTL(port));

		if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
			temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
		else
			temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;

		temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
			temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;

			break;
		case DP_TRAINING_PATTERN_1:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
			break;
		case DP_TRAINING_PATTERN_2:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
			break;
		case DP_TRAINING_PATTERN_3:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
			break;
		}
		I915_WRITE(DP_TP_CTL(port), temp);

2486 2487
	} else if ((IS_GEN7(dev) && port == PORT_A) ||
		   (HAS_PCH_CPT(dev) && port != PORT_A)) {
2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544
		*DP &= ~DP_LINK_TRAIN_MASK_CPT;

		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
			*DP |= DP_LINK_TRAIN_OFF_CPT;
			break;
		case DP_TRAINING_PATTERN_1:
			*DP |= DP_LINK_TRAIN_PAT_1_CPT;
			break;
		case DP_TRAINING_PATTERN_2:
			*DP |= DP_LINK_TRAIN_PAT_2_CPT;
			break;
		case DP_TRAINING_PATTERN_3:
			DRM_ERROR("DP training pattern 3 not supported\n");
			*DP |= DP_LINK_TRAIN_PAT_2_CPT;
			break;
		}

	} else {
		if (IS_CHERRYVIEW(dev))
			*DP &= ~DP_LINK_TRAIN_MASK_CHV;
		else
			*DP &= ~DP_LINK_TRAIN_MASK;

		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
			*DP |= DP_LINK_TRAIN_OFF;
			break;
		case DP_TRAINING_PATTERN_1:
			*DP |= DP_LINK_TRAIN_PAT_1;
			break;
		case DP_TRAINING_PATTERN_2:
			*DP |= DP_LINK_TRAIN_PAT_2;
			break;
		case DP_TRAINING_PATTERN_3:
			if (IS_CHERRYVIEW(dev)) {
				*DP |= DP_LINK_TRAIN_PAT_3_CHV;
			} else {
				DRM_ERROR("DP training pattern 3 not supported\n");
				*DP |= DP_LINK_TRAIN_PAT_2;
			}
			break;
		}
	}
}

static void intel_dp_enable_port(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;

	/* enable with pattern 1 (as per spec) */
	_intel_dp_set_link_train(intel_dp, &intel_dp->DP,
				 DP_TRAINING_PATTERN_1);

	I915_WRITE(intel_dp->output_reg, intel_dp->DP);
	POSTING_READ(intel_dp->output_reg);
2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555

	/*
	 * Magic for VLV/CHV. We _must_ first set up the register
	 * without actually enabling the port, and then do another
	 * write to enable the port. Otherwise link training will
	 * fail when the power sequencer is freshly used for this port.
	 */
	intel_dp->DP |= DP_PORT_EN;

	I915_WRITE(intel_dp->output_reg, intel_dp->DP);
	POSTING_READ(intel_dp->output_reg);
2556 2557
}

2558
static void intel_enable_dp(struct intel_encoder *encoder)
2559
{
2560 2561 2562
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2563
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2564
	uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2565
	unsigned int lane_mask = 0x0;
2566

2567 2568
	if (WARN_ON(dp_reg & DP_PORT_EN))
		return;
2569

2570 2571 2572 2573 2574
	pps_lock(intel_dp);

	if (IS_VALLEYVIEW(dev))
		vlv_init_panel_power_sequencer(intel_dp);

2575
	intel_dp_enable_port(intel_dp);
2576 2577 2578 2579 2580 2581 2582

	edp_panel_vdd_on(intel_dp);
	edp_panel_on(intel_dp);
	edp_panel_vdd_off(intel_dp, true);

	pps_unlock(intel_dp);

2583
	if (IS_VALLEYVIEW(dev))
2584 2585
		vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
				    lane_mask);
2586

2587
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2588 2589
	intel_dp_start_link_train(intel_dp);
	intel_dp_complete_link_train(intel_dp);
2590
	intel_dp_stop_link_train(intel_dp);
2591

2592
	if (crtc->config->has_audio) {
2593 2594 2595 2596
		DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
				 pipe_name(crtc->pipe));
		intel_audio_codec_enable(encoder);
	}
2597
}
2598

2599 2600
static void g4x_enable_dp(struct intel_encoder *encoder)
{
2601 2602
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

2603
	intel_enable_dp(encoder);
2604
	intel_edp_backlight_on(intel_dp);
2605
}
2606

2607 2608
static void vlv_enable_dp(struct intel_encoder *encoder)
{
2609 2610
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

2611
	intel_edp_backlight_on(intel_dp);
2612
	intel_psr_enable(intel_dp);
2613 2614
}

2615
static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2616 2617 2618 2619
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);

2620 2621
	intel_dp_prepare(encoder);

2622 2623 2624
	/* Only ilk+ has port A */
	if (dport->port == PORT_A) {
		ironlake_set_pll_cpu_edp(intel_dp);
2625
		ironlake_edp_pll_on(intel_dp);
2626
	}
2627 2628
}

2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654
static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
	enum pipe pipe = intel_dp->pps_pipe;
	int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);

	edp_panel_vdd_off_sync(intel_dp);

	/*
	 * VLV seems to get confused when multiple power seqeuencers
	 * have the same port selected (even if only one has power/vdd
	 * enabled). The failure manifests as vlv_wait_port_ready() failing
	 * CHV on the other hand doesn't seem to mind having the same port
	 * selected in multiple power seqeuencers, but let's clear the
	 * port select always when logically disconnecting a power sequencer
	 * from a port.
	 */
	DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
		      pipe_name(pipe), port_name(intel_dig_port->port));
	I915_WRITE(pp_on_reg, 0);
	POSTING_READ(pp_on_reg);

	intel_dp->pps_pipe = INVALID_PIPE;
}

2655 2656 2657 2658 2659 2660 2661 2662
static void vlv_steal_power_sequencer(struct drm_device *dev,
				      enum pipe pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_encoder *encoder;

	lockdep_assert_held(&dev_priv->pps_mutex);

2663 2664 2665
	if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
		return;

2666 2667 2668
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		struct intel_dp *intel_dp;
2669
		enum port port;
2670 2671 2672 2673 2674

		if (encoder->type != INTEL_OUTPUT_EDP)
			continue;

		intel_dp = enc_to_intel_dp(&encoder->base);
2675
		port = dp_to_dig_port(intel_dp)->port;
2676 2677 2678 2679 2680

		if (intel_dp->pps_pipe != pipe)
			continue;

		DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2681
			      pipe_name(pipe), port_name(port));
2682

2683
		WARN(encoder->base.crtc,
2684 2685
		     "stealing pipe %c power sequencer from active eDP port %c\n",
		     pipe_name(pipe), port_name(port));
2686 2687

		/* make sure vdd is off before we steal it */
2688
		vlv_detach_power_sequencer(intel_dp);
2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701
	}
}

static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *encoder = &intel_dig_port->base;
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);

	lockdep_assert_held(&dev_priv->pps_mutex);

2702 2703 2704
	if (!is_edp(intel_dp))
		return;

2705 2706 2707 2708 2709 2710 2711 2712 2713
	if (intel_dp->pps_pipe == crtc->pipe)
		return;

	/*
	 * If another power sequencer was being used on this
	 * port previously make sure to turn off vdd there while
	 * we still have control of it.
	 */
	if (intel_dp->pps_pipe != INVALID_PIPE)
2714
		vlv_detach_power_sequencer(intel_dp);
2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728

	/*
	 * We may be stealing the power
	 * sequencer from another port.
	 */
	vlv_steal_power_sequencer(dev, crtc->pipe);

	/* now it's all ours */
	intel_dp->pps_pipe = crtc->pipe;

	DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
		      pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));

	/* init power sequencer on this pipe and port */
2729 2730
	intel_dp_init_panel_power_sequencer(dev, intel_dp);
	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
2731 2732
}

2733
static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2734
{
2735
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2736
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2737
	struct drm_device *dev = encoder->base.dev;
2738
	struct drm_i915_private *dev_priv = dev->dev_private;
2739
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2740
	enum dpio_channel port = vlv_dport_to_channel(dport);
2741 2742
	int pipe = intel_crtc->pipe;
	u32 val;
2743

V
Ville Syrjälä 已提交
2744
	mutex_lock(&dev_priv->sb_lock);
2745

2746
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2747 2748 2749 2750 2751 2752
	val = 0;
	if (pipe)
		val |= (1<<21);
	else
		val &= ~(1<<21);
	val |= 0x001000c4;
2753 2754 2755
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2756

V
Ville Syrjälä 已提交
2757
	mutex_unlock(&dev_priv->sb_lock);
2758 2759

	intel_enable_dp(encoder);
2760 2761
}

2762
static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2763 2764 2765 2766
{
	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2767 2768
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
2769
	enum dpio_channel port = vlv_dport_to_channel(dport);
2770
	int pipe = intel_crtc->pipe;
2771

2772 2773
	intel_dp_prepare(encoder);

2774
	/* Program Tx lane resets to default */
V
Ville Syrjälä 已提交
2775
	mutex_lock(&dev_priv->sb_lock);
2776
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2777 2778
			 DPIO_PCS_TX_LANE2_RESET |
			 DPIO_PCS_TX_LANE1_RESET);
2779
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2780 2781 2782 2783 2784 2785
			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
			 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
			 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
				 DPIO_PCS_CLK_SOFT_RESET);

	/* Fix up inter-pair skew failure */
2786 2787 2788
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
V
Ville Syrjälä 已提交
2789
	mutex_unlock(&dev_priv->sb_lock);
2790 2791
}

2792 2793 2794 2795 2796 2797 2798 2799 2800 2801
static void chv_pre_enable_dp(struct intel_encoder *encoder)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
	enum dpio_channel ch = vlv_dport_to_channel(dport);
	int pipe = intel_crtc->pipe;
2802
	int data, i, stagger;
2803
	u32 val;
2804

V
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2805
	mutex_lock(&dev_priv->sb_lock);
2806

2807 2808 2809 2810 2811 2812 2813 2814 2815
	/* allow hardware to manage TX FIFO reset source */
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);

2816
	/* Deassert soft data lane reset*/
2817
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2818
	val |= CHV_PCS_REQ_SOFTRESET_EN;
2819 2820 2821 2822 2823 2824 2825 2826 2827
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
	val |= CHV_PCS_REQ_SOFTRESET_EN;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2828

2829
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2830
	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2831
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2832 2833

	/* Program Tx lane latency optimal setting*/
2834 2835 2836 2837 2838 2839 2840 2841
	for (i = 0; i < 4; i++) {
		/* Set the upar bit */
		data = (i == 1) ? 0x0 : 0x1;
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
				data << DPIO_UPAR_SHIFT);
	}

	/* Data lane stagger programming */
2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869 2870 2871 2872 2873
	if (intel_crtc->config->port_clock > 270000)
		stagger = 0x18;
	else if (intel_crtc->config->port_clock > 135000)
		stagger = 0xd;
	else if (intel_crtc->config->port_clock > 67500)
		stagger = 0x7;
	else if (intel_crtc->config->port_clock > 33750)
		stagger = 0x4;
	else
		stagger = 0x2;

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
	val |= DPIO_TX2_STAGGER_MASK(0x1f);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
	val |= DPIO_TX2_STAGGER_MASK(0x1f);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);

	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
		       DPIO_LANESTAGGER_STRAP(stagger) |
		       DPIO_LANESTAGGER_STRAP_OVRD |
		       DPIO_TX1_STAGGER_MASK(0x1f) |
		       DPIO_TX1_STAGGER_MULT(6) |
		       DPIO_TX2_STAGGER_MULT(0));

	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
		       DPIO_LANESTAGGER_STRAP(stagger) |
		       DPIO_LANESTAGGER_STRAP_OVRD |
		       DPIO_TX1_STAGGER_MASK(0x1f) |
		       DPIO_TX1_STAGGER_MULT(7) |
		       DPIO_TX2_STAGGER_MULT(5));
2874

V
Ville Syrjälä 已提交
2875
	mutex_unlock(&dev_priv->sb_lock);
2876 2877 2878 2879

	intel_enable_dp(encoder);
}

2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890
static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
{
	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
	enum dpio_channel ch = vlv_dport_to_channel(dport);
	enum pipe pipe = intel_crtc->pipe;
	u32 val;

2891 2892
	intel_dp_prepare(encoder);

V
Ville Syrjälä 已提交
2893
	mutex_lock(&dev_priv->sb_lock);
2894

2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913
	/* program left/right clock distribution */
	if (pipe != PIPE_B) {
		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
		if (ch == DPIO_CH0)
			val |= CHV_BUFLEFTENA1_FORCE;
		if (ch == DPIO_CH1)
			val |= CHV_BUFRIGHTENA1_FORCE;
		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
	} else {
		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
		if (ch == DPIO_CH0)
			val |= CHV_BUFLEFTENA2_FORCE;
		if (ch == DPIO_CH1)
			val |= CHV_BUFRIGHTENA2_FORCE;
		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
	}

2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942
	/* program clock channel usage */
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
	if (pipe != PIPE_B)
		val &= ~CHV_PCS_USEDCLKCHANNEL;
	else
		val |= CHV_PCS_USEDCLKCHANNEL;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
	if (pipe != PIPE_B)
		val &= ~CHV_PCS_USEDCLKCHANNEL;
	else
		val |= CHV_PCS_USEDCLKCHANNEL;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);

	/*
	 * This a a bit weird since generally CL
	 * matches the pipe, but here we need to
	 * pick the CL based on the port.
	 */
	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
	if (pipe != PIPE_B)
		val &= ~CHV_CMN_USEDCLKCHANNEL;
	else
		val |= CHV_CMN_USEDCLKCHANNEL;
	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);

V
Ville Syrjälä 已提交
2943
	mutex_unlock(&dev_priv->sb_lock);
2944 2945
}

2946
/*
2947 2948
 * Native read with retry for link status and receiver capability reads for
 * cases where the sink may still be asleep.
2949 2950 2951
 *
 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
 * supposed to retry 3 times per the spec.
2952
 */
2953 2954 2955
static ssize_t
intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
			void *buffer, size_t size)
2956
{
2957 2958
	ssize_t ret;
	int i;
2959

2960 2961 2962 2963 2964 2965 2966
	/*
	 * Sometime we just get the same incorrect byte repeated
	 * over the entire buffer. Doing just one throw away read
	 * initially seems to "solve" it.
	 */
	drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);

2967
	for (i = 0; i < 3; i++) {
2968 2969 2970
		ret = drm_dp_dpcd_read(aux, offset, buffer, size);
		if (ret == size)
			return ret;
2971 2972
		msleep(1);
	}
2973

2974
	return ret;
2975 2976 2977 2978 2979 2980 2981
}

/*
 * Fetch AUX CH registers 0x202 - 0x207 which contain
 * link status information
 */
static bool
2982
intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2983
{
2984 2985 2986 2987
	return intel_dp_dpcd_read_wake(&intel_dp->aux,
				       DP_LANE0_1_STATUS,
				       link_status,
				       DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2988 2989
}

2990
/* These are source-specific values. */
2991
static uint8_t
K
Keith Packard 已提交
2992
intel_dp_voltage_max(struct intel_dp *intel_dp)
2993
{
2994
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2995
	struct drm_i915_private *dev_priv = dev->dev_private;
2996
	enum port port = dp_to_dig_port(intel_dp)->port;
K
Keith Packard 已提交
2997

2998 2999 3000
	if (IS_BROXTON(dev))
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
	else if (INTEL_INFO(dev)->gen >= 9) {
3001
		if (dev_priv->edp_low_vswing && port == PORT_A)
3002
			return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3003
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3004
	} else if (IS_VALLEYVIEW(dev))
3005
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3006
	else if (IS_GEN7(dev) && port == PORT_A)
3007
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3008
	else if (HAS_PCH_CPT(dev) && port != PORT_A)
3009
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
K
Keith Packard 已提交
3010
	else
3011
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
K
Keith Packard 已提交
3012 3013 3014 3015 3016
}

static uint8_t
intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
{
3017
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
3018
	enum port port = dp_to_dig_port(intel_dp)->port;
K
Keith Packard 已提交
3019

3020 3021 3022 3023 3024 3025 3026 3027
	if (INTEL_INFO(dev)->gen >= 9) {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
			return DP_TRAIN_PRE_EMPH_LEVEL_3;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
			return DP_TRAIN_PRE_EMPH_LEVEL_1;
3028 3029
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
3030 3031 3032 3033
		default:
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
		}
	} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3034
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3035 3036 3037 3038 3039 3040 3041
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
			return DP_TRAIN_PRE_EMPH_LEVEL_3;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
			return DP_TRAIN_PRE_EMPH_LEVEL_1;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3042
		default:
3043
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
3044
		}
3045 3046
	} else if (IS_VALLEYVIEW(dev)) {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3047 3048 3049 3050 3051 3052 3053
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
			return DP_TRAIN_PRE_EMPH_LEVEL_3;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
			return DP_TRAIN_PRE_EMPH_LEVEL_1;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3054
		default:
3055
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
3056
		}
3057
	} else if (IS_GEN7(dev) && port == PORT_A) {
K
Keith Packard 已提交
3058
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3059 3060 3061 3062 3063
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
			return DP_TRAIN_PRE_EMPH_LEVEL_1;
K
Keith Packard 已提交
3064
		default:
3065
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
K
Keith Packard 已提交
3066 3067 3068
		}
	} else {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3069 3070 3071 3072 3073 3074 3075
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
			return DP_TRAIN_PRE_EMPH_LEVEL_1;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
K
Keith Packard 已提交
3076
		default:
3077
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
K
Keith Packard 已提交
3078
		}
3079 3080 3081
	}
}

3082
static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3083 3084 3085 3086
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3087 3088
	struct intel_crtc *intel_crtc =
		to_intel_crtc(dport->base.base.crtc);
3089 3090 3091
	unsigned long demph_reg_value, preemph_reg_value,
		uniqtranscale_reg_value;
	uint8_t train_set = intel_dp->train_set[0];
3092
	enum dpio_channel port = vlv_dport_to_channel(dport);
3093
	int pipe = intel_crtc->pipe;
3094 3095

	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3096
	case DP_TRAIN_PRE_EMPH_LEVEL_0:
3097 3098
		preemph_reg_value = 0x0004000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3099
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3100 3101 3102
			demph_reg_value = 0x2B405555;
			uniqtranscale_reg_value = 0x552AB83A;
			break;
3103
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3104 3105 3106
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x5548B83A;
			break;
3107
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3108 3109 3110
			demph_reg_value = 0x2B245555;
			uniqtranscale_reg_value = 0x5560B83A;
			break;
3111
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3112 3113 3114 3115 3116 3117 3118
			demph_reg_value = 0x2B405555;
			uniqtranscale_reg_value = 0x5598DA3A;
			break;
		default:
			return 0;
		}
		break;
3119
	case DP_TRAIN_PRE_EMPH_LEVEL_1:
3120 3121
		preemph_reg_value = 0x0002000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3122
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3123 3124 3125
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x5552B83A;
			break;
3126
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3127 3128 3129
			demph_reg_value = 0x2B404848;
			uniqtranscale_reg_value = 0x5580B83A;
			break;
3130
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3131 3132 3133 3134 3135 3136 3137
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
3138
	case DP_TRAIN_PRE_EMPH_LEVEL_2:
3139 3140
		preemph_reg_value = 0x0000000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3141
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3142 3143 3144
			demph_reg_value = 0x2B305555;
			uniqtranscale_reg_value = 0x5570B83A;
			break;
3145
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3146 3147 3148 3149 3150 3151 3152
			demph_reg_value = 0x2B2B4040;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
3153
	case DP_TRAIN_PRE_EMPH_LEVEL_3:
3154 3155
		preemph_reg_value = 0x0006000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3156
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167
			demph_reg_value = 0x1B405555;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
	default:
		return 0;
	}

V
Ville Syrjälä 已提交
3168
	mutex_lock(&dev_priv->sb_lock);
3169 3170 3171
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
3172
			 uniqtranscale_reg_value);
3173 3174 3175 3176
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
V
Ville Syrjälä 已提交
3177
	mutex_unlock(&dev_priv->sb_lock);
3178 3179 3180 3181

	return 0;
}

3182 3183 3184 3185 3186 3187
static bool chv_need_uniq_trans_scale(uint8_t train_set)
{
	return (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) == DP_TRAIN_PRE_EMPH_LEVEL_0 &&
		(train_set & DP_TRAIN_VOLTAGE_SWING_MASK) == DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
}

3188
static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3189 3190 3191 3192 3193
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
	struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
3194
	u32 deemph_reg_value, margin_reg_value, val;
3195 3196
	uint8_t train_set = intel_dp->train_set[0];
	enum dpio_channel ch = vlv_dport_to_channel(dport);
3197 3198
	enum pipe pipe = intel_crtc->pipe;
	int i;
3199 3200

	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3201
	case DP_TRAIN_PRE_EMPH_LEVEL_0:
3202
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3203
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3204 3205 3206
			deemph_reg_value = 128;
			margin_reg_value = 52;
			break;
3207
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3208 3209 3210
			deemph_reg_value = 128;
			margin_reg_value = 77;
			break;
3211
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3212 3213 3214
			deemph_reg_value = 128;
			margin_reg_value = 102;
			break;
3215
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3216 3217 3218 3219 3220 3221 3222 3223
			deemph_reg_value = 128;
			margin_reg_value = 154;
			/* FIXME extra to set for 1200 */
			break;
		default:
			return 0;
		}
		break;
3224
	case DP_TRAIN_PRE_EMPH_LEVEL_1:
3225
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3226
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3227 3228 3229
			deemph_reg_value = 85;
			margin_reg_value = 78;
			break;
3230
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3231 3232 3233
			deemph_reg_value = 85;
			margin_reg_value = 116;
			break;
3234
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3235 3236 3237 3238 3239 3240 3241
			deemph_reg_value = 85;
			margin_reg_value = 154;
			break;
		default:
			return 0;
		}
		break;
3242
	case DP_TRAIN_PRE_EMPH_LEVEL_2:
3243
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3244
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3245 3246 3247
			deemph_reg_value = 64;
			margin_reg_value = 104;
			break;
3248
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3249 3250 3251 3252 3253 3254 3255
			deemph_reg_value = 64;
			margin_reg_value = 154;
			break;
		default:
			return 0;
		}
		break;
3256
	case DP_TRAIN_PRE_EMPH_LEVEL_3:
3257
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3258
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3259 3260 3261 3262 3263 3264 3265 3266 3267 3268 3269
			deemph_reg_value = 43;
			margin_reg_value = 154;
			break;
		default:
			return 0;
		}
		break;
	default:
		return 0;
	}

V
Ville Syrjälä 已提交
3270
	mutex_lock(&dev_priv->sb_lock);
3271 3272

	/* Clear calc init */
3273 3274
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3275 3276
	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3277 3278 3279 3280
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3281 3282
	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3283
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3284

3285 3286 3287 3288 3289 3290 3291 3292 3293 3294
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);

3295
	/* Program swing deemph */
3296 3297 3298 3299 3300 3301
	for (i = 0; i < 4; i++) {
		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
		val &= ~DPIO_SWING_DEEMPH9P5_MASK;
		val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
	}
3302 3303

	/* Program swing margin */
3304 3305
	for (i = 0; i < 4; i++) {
		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3306

3307 3308
		val &= ~DPIO_SWING_MARGIN000_MASK;
		val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
3309 3310 3311 3312 3313 3314 3315 3316 3317

		/*
		 * Supposedly this value shouldn't matter when unique transition
		 * scale is disabled, but in fact it does matter. Let's just
		 * always program the same value and hope it's OK.
		 */
		val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
		val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;

3318 3319
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
	}
3320

3321 3322 3323 3324 3325 3326
	/*
	 * The document said it needs to set bit 27 for ch0 and bit 26
	 * for ch1. Might be a typo in the doc.
	 * For now, for this unique transition scale selection, set bit
	 * 27 for ch0 and ch1.
	 */
3327 3328
	for (i = 0; i < 4; i++) {
		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3329
		if (chv_need_uniq_trans_scale(train_set))
3330
			val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3331 3332 3333
		else
			val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3334 3335 3336
	}

	/* Start swing calculation */
3337 3338 3339 3340 3341 3342 3343
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3344 3345 3346 3347 3348 3349

	/* LRC Bypass */
	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
	val |= DPIO_LRC_BYPASS;
	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);

V
Ville Syrjälä 已提交
3350
	mutex_unlock(&dev_priv->sb_lock);
3351 3352 3353 3354

	return 0;
}

3355
static void
J
Jani Nikula 已提交
3356 3357
intel_get_adjust_train(struct intel_dp *intel_dp,
		       const uint8_t link_status[DP_LINK_STATUS_SIZE])
3358 3359 3360 3361
{
	uint8_t v = 0;
	uint8_t p = 0;
	int lane;
K
Keith Packard 已提交
3362 3363
	uint8_t voltage_max;
	uint8_t preemph_max;
3364

3365
	for (lane = 0; lane < intel_dp->lane_count; lane++) {
3366 3367
		uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
		uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
3368 3369 3370 3371 3372 3373 3374

		if (this_v > v)
			v = this_v;
		if (this_p > p)
			p = this_p;
	}

K
Keith Packard 已提交
3375
	voltage_max = intel_dp_voltage_max(intel_dp);
3376 3377
	if (v >= voltage_max)
		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
3378

K
Keith Packard 已提交
3379 3380 3381
	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
	if (p >= preemph_max)
		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
3382 3383

	for (lane = 0; lane < 4; lane++)
3384
		intel_dp->train_set[lane] = v | p;
3385 3386 3387
}

static uint32_t
3388
gen4_signal_levels(uint8_t train_set)
3389
{
3390
	uint32_t	signal_levels = 0;
3391

3392
	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3393
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3394 3395 3396
	default:
		signal_levels |= DP_VOLTAGE_0_4;
		break;
3397
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3398 3399
		signal_levels |= DP_VOLTAGE_0_6;
		break;
3400
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3401 3402
		signal_levels |= DP_VOLTAGE_0_8;
		break;
3403
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3404 3405 3406
		signal_levels |= DP_VOLTAGE_1_2;
		break;
	}
3407
	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3408
	case DP_TRAIN_PRE_EMPH_LEVEL_0:
3409 3410 3411
	default:
		signal_levels |= DP_PRE_EMPHASIS_0;
		break;
3412
	case DP_TRAIN_PRE_EMPH_LEVEL_1:
3413 3414
		signal_levels |= DP_PRE_EMPHASIS_3_5;
		break;
3415
	case DP_TRAIN_PRE_EMPH_LEVEL_2:
3416 3417
		signal_levels |= DP_PRE_EMPHASIS_6;
		break;
3418
	case DP_TRAIN_PRE_EMPH_LEVEL_3:
3419 3420 3421 3422 3423 3424
		signal_levels |= DP_PRE_EMPHASIS_9_5;
		break;
	}
	return signal_levels;
}

3425 3426
/* Gen6's DP voltage swing and pre-emphasis control */
static uint32_t
3427
gen6_edp_signal_levels(uint8_t train_set)
3428
{
3429 3430 3431
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
3432 3433
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3434
		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3435
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3436
		return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3437 3438
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3439
		return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3440 3441
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3442
		return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3443 3444
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3445
		return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3446
	default:
3447 3448 3449
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3450 3451 3452
	}
}

K
Keith Packard 已提交
3453 3454
/* Gen7's DP voltage swing and pre-emphasis control */
static uint32_t
3455
gen7_edp_signal_levels(uint8_t train_set)
K
Keith Packard 已提交
3456 3457 3458 3459
{
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
3460
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
K
Keith Packard 已提交
3461
		return EDP_LINK_TRAIN_400MV_0DB_IVB;
3462
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
K
Keith Packard 已提交
3463
		return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3464
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
K
Keith Packard 已提交
3465 3466
		return EDP_LINK_TRAIN_400MV_6DB_IVB;

3467
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
K
Keith Packard 已提交
3468
		return EDP_LINK_TRAIN_600MV_0DB_IVB;
3469
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
K
Keith Packard 已提交
3470 3471
		return EDP_LINK_TRAIN_600MV_3_5DB_IVB;

3472
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
K
Keith Packard 已提交
3473
		return EDP_LINK_TRAIN_800MV_0DB_IVB;
3474
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
K
Keith Packard 已提交
3475 3476 3477 3478 3479 3480 3481 3482 3483
		return EDP_LINK_TRAIN_800MV_3_5DB_IVB;

	default:
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return EDP_LINK_TRAIN_500MV_0DB_IVB;
	}
}

3484 3485 3486 3487 3488
/* Properly updates "DP" with the correct signal levels. */
static void
intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3489
	enum port port = intel_dig_port->port;
3490
	struct drm_device *dev = intel_dig_port->base.base.dev;
3491
	uint32_t signal_levels, mask = 0;
3492 3493
	uint8_t train_set = intel_dp->train_set[0];

3494 3495 3496 3497 3498 3499 3500
	if (HAS_DDI(dev)) {
		signal_levels = ddi_signal_levels(intel_dp);

		if (IS_BROXTON(dev))
			signal_levels = 0;
		else
			mask = DDI_BUF_EMP_MASK;
3501
	} else if (IS_CHERRYVIEW(dev)) {
3502
		signal_levels = chv_signal_levels(intel_dp);
3503
	} else if (IS_VALLEYVIEW(dev)) {
3504
		signal_levels = vlv_signal_levels(intel_dp);
3505
	} else if (IS_GEN7(dev) && port == PORT_A) {
3506
		signal_levels = gen7_edp_signal_levels(train_set);
3507
		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3508
	} else if (IS_GEN6(dev) && port == PORT_A) {
3509
		signal_levels = gen6_edp_signal_levels(train_set);
3510 3511
		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
	} else {
3512
		signal_levels = gen4_signal_levels(train_set);
3513 3514 3515
		mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
	}

3516 3517 3518 3519 3520 3521 3522 3523
	if (mask)
		DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);

	DRM_DEBUG_KMS("Using vswing level %d\n",
		train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
	DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
		(train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
			DP_TRAIN_PRE_EMPHASIS_SHIFT);
3524 3525 3526 3527

	*DP = (*DP & ~mask) | signal_levels;
}

3528
static bool
C
Chris Wilson 已提交
3529
intel_dp_set_link_train(struct intel_dp *intel_dp,
3530
			uint32_t *DP,
3531
			uint8_t dp_train_pat)
3532
{
3533
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3534 3535
	struct drm_i915_private *dev_priv =
		to_i915(intel_dig_port->base.base.dev);
3536 3537
	uint8_t buf[sizeof(intel_dp->train_set) + 1];
	int ret, len;
3538

3539
	_intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3540

3541
	I915_WRITE(intel_dp->output_reg, *DP);
C
Chris Wilson 已提交
3542
	POSTING_READ(intel_dp->output_reg);
3543

3544 3545
	buf[0] = dp_train_pat;
	if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
3546
	    DP_TRAINING_PATTERN_DISABLE) {
3547 3548 3549 3550
		/* don't write DP_TRAINING_LANEx_SET on disable */
		len = 1;
	} else {
		/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3551 3552
		memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
		len = intel_dp->lane_count + 1;
3553
	}
3554

3555 3556
	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
				buf, len);
3557 3558

	return ret == len;
3559 3560
}

3561 3562 3563 3564
static bool
intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
			uint8_t dp_train_pat)
{
3565 3566
	if (!intel_dp->train_set_valid)
		memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
3567 3568 3569 3570 3571 3572
	intel_dp_set_signal_levels(intel_dp, DP);
	return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
}

static bool
intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
J
Jani Nikula 已提交
3573
			   const uint8_t link_status[DP_LINK_STATUS_SIZE])
3574 3575
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3576 3577
	struct drm_i915_private *dev_priv =
		to_i915(intel_dig_port->base.base.dev);
3578 3579 3580 3581 3582 3583 3584 3585
	int ret;

	intel_get_adjust_train(intel_dp, link_status);
	intel_dp_set_signal_levels(intel_dp, DP);

	I915_WRITE(intel_dp->output_reg, *DP);
	POSTING_READ(intel_dp->output_reg);

3586
	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3587
				intel_dp->train_set, intel_dp->lane_count);
3588

3589
	return ret == intel_dp->lane_count;
3590 3591
}

3592 3593 3594 3595 3596 3597 3598 3599 3600 3601 3602 3603 3604 3605 3606 3607 3608 3609 3610 3611 3612 3613 3614 3615 3616 3617 3618 3619 3620 3621 3622
static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = intel_dig_port->port;
	uint32_t val;

	if (!HAS_DDI(dev))
		return;

	val = I915_READ(DP_TP_CTL(port));
	val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
	val |= DP_TP_CTL_LINK_TRAIN_IDLE;
	I915_WRITE(DP_TP_CTL(port), val);

	/*
	 * On PORT_A we can have only eDP in SST mode. There the only reason
	 * we need to set idle transmission mode is to work around a HW issue
	 * where we enable the pipe while not in idle link-training mode.
	 * In this case there is requirement to wait for a minimum number of
	 * idle patterns to be sent.
	 */
	if (port == PORT_A)
		return;

	if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
		     1))
		DRM_ERROR("Timed out waiting for DP idle patterns\n");
}

3623
/* Enable corresponding port and start training pattern 1 */
3624
void
3625
intel_dp_start_link_train(struct intel_dp *intel_dp)
3626
{
3627
	struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
3628
	struct drm_device *dev = encoder->dev;
3629 3630
	int i;
	uint8_t voltage;
3631
	int voltage_tries, loop_tries;
C
Chris Wilson 已提交
3632
	uint32_t DP = intel_dp->DP;
3633
	uint8_t link_config[2];
3634
	uint8_t link_bw, rate_select;
3635

P
Paulo Zanoni 已提交
3636
	if (HAS_DDI(dev))
3637 3638
		intel_ddi_prepare_link_retrain(encoder);

3639
	intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
3640 3641
			      &link_bw, &rate_select);

3642
	/* Write the link configuration data */
3643
	link_config[0] = link_bw;
3644
	link_config[1] = intel_dp->lane_count;
3645 3646
	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
3647
	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
3648
	if (intel_dp->num_sink_rates)
3649
		drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
3650
				  &rate_select, 1);
3651 3652 3653

	link_config[0] = 0;
	link_config[1] = DP_SET_ANSI_8B10B;
3654
	drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
3655 3656

	DP |= DP_PORT_EN;
K
Keith Packard 已提交
3657

3658 3659 3660 3661 3662 3663 3664 3665
	/* clock recovery */
	if (!intel_dp_reset_link_train(intel_dp, &DP,
				       DP_TRAINING_PATTERN_1 |
				       DP_LINK_SCRAMBLING_DISABLE)) {
		DRM_ERROR("failed to enable link training\n");
		return;
	}

3666
	voltage = 0xff;
3667 3668
	voltage_tries = 0;
	loop_tries = 0;
3669
	for (;;) {
3670
		uint8_t link_status[DP_LINK_STATUS_SIZE];
3671

3672
		drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
3673 3674
		if (!intel_dp_get_link_status(intel_dp, link_status)) {
			DRM_ERROR("failed to get link status\n");
3675
			break;
3676
		}
3677

3678
		if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3679
			DRM_DEBUG_KMS("clock recovery OK\n");
3680 3681 3682
			break;
		}

3683 3684 3685 3686 3687 3688 3689 3690 3691 3692 3693 3694 3695 3696 3697 3698 3699
		/*
		 * if we used previously trained voltage and pre-emphasis values
		 * and we don't get clock recovery, reset link training values
		 */
		if (intel_dp->train_set_valid) {
			DRM_DEBUG_KMS("clock recovery not ok, reset");
			/* clear the flag as we are not reusing train set */
			intel_dp->train_set_valid = false;
			if (!intel_dp_reset_link_train(intel_dp, &DP,
						       DP_TRAINING_PATTERN_1 |
						       DP_LINK_SCRAMBLING_DISABLE)) {
				DRM_ERROR("failed to enable link training\n");
				return;
			}
			continue;
		}

3700
		/* Check to see if we've tried the max voltage */
3701
		for (i = 0; i < intel_dp->lane_count; i++)
3702
			if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
3703
				break;
3704
		if (i == intel_dp->lane_count) {
3705 3706
			++loop_tries;
			if (loop_tries == 5) {
3707
				DRM_ERROR("too many full retries, give up\n");
3708 3709
				break;
			}
3710 3711 3712
			intel_dp_reset_link_train(intel_dp, &DP,
						  DP_TRAINING_PATTERN_1 |
						  DP_LINK_SCRAMBLING_DISABLE);
3713 3714 3715
			voltage_tries = 0;
			continue;
		}
3716

3717
		/* Check to see if we've tried the same voltage 5 times */
3718
		if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
3719
			++voltage_tries;
3720
			if (voltage_tries == 5) {
3721
				DRM_ERROR("too many voltage retries, give up\n");
3722 3723 3724 3725 3726
				break;
			}
		} else
			voltage_tries = 0;
		voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
3727

3728 3729 3730 3731 3732
		/* Update training set as requested by target */
		if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
			DRM_ERROR("failed to update link training\n");
			break;
		}
3733 3734
	}

3735 3736 3737
	intel_dp->DP = DP;
}

3738
void
3739 3740 3741
intel_dp_complete_link_train(struct intel_dp *intel_dp)
{
	bool channel_eq = false;
3742
	int tries, cr_tries;
3743
	uint32_t DP = intel_dp->DP;
3744 3745
	uint32_t training_pattern = DP_TRAINING_PATTERN_2;

3746
	/* Training Pattern 3 for HBR2 or 1.2 devices that support it*/
3747
	if (intel_dp->link_rate == 540000 || intel_dp->use_tps3)
3748
		training_pattern = DP_TRAINING_PATTERN_3;
3749

3750
	/* channel equalization */
3751
	if (!intel_dp_set_link_train(intel_dp, &DP,
3752
				     training_pattern |
3753 3754 3755 3756 3757
				     DP_LINK_SCRAMBLING_DISABLE)) {
		DRM_ERROR("failed to start channel equalization\n");
		return;
	}

3758
	tries = 0;
3759
	cr_tries = 0;
3760 3761
	channel_eq = false;
	for (;;) {
3762
		uint8_t link_status[DP_LINK_STATUS_SIZE];
3763

3764 3765 3766 3767 3768
		if (cr_tries > 5) {
			DRM_ERROR("failed to train DP, aborting\n");
			break;
		}

3769
		drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
3770 3771
		if (!intel_dp_get_link_status(intel_dp, link_status)) {
			DRM_ERROR("failed to get link status\n");
3772
			break;
3773
		}
3774

3775
		/* Make sure clock is still ok */
3776
		if (!drm_dp_clock_recovery_ok(link_status,
3777
					      intel_dp->lane_count)) {
3778
			intel_dp->train_set_valid = false;
3779
			intel_dp_start_link_train(intel_dp);
3780
			intel_dp_set_link_train(intel_dp, &DP,
3781
						training_pattern |
3782
						DP_LINK_SCRAMBLING_DISABLE);
3783 3784 3785 3786
			cr_tries++;
			continue;
		}

3787
		if (drm_dp_channel_eq_ok(link_status,
3788
					 intel_dp->lane_count)) {
3789 3790 3791
			channel_eq = true;
			break;
		}
3792

3793 3794
		/* Try 5 times, then try clock recovery if that fails */
		if (tries > 5) {
3795
			intel_dp->train_set_valid = false;
3796
			intel_dp_start_link_train(intel_dp);
3797
			intel_dp_set_link_train(intel_dp, &DP,
3798
						training_pattern |
3799
						DP_LINK_SCRAMBLING_DISABLE);
3800 3801 3802 3803
			tries = 0;
			cr_tries++;
			continue;
		}
3804

3805 3806 3807 3808 3809
		/* Update training set as requested by target */
		if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
			DRM_ERROR("failed to update link training\n");
			break;
		}
3810
		++tries;
3811
	}
3812

3813 3814 3815 3816
	intel_dp_set_idle_link_train(intel_dp);

	intel_dp->DP = DP;

3817
	if (channel_eq) {
3818
		intel_dp->train_set_valid = true;
M
Masanari Iida 已提交
3819
		DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3820
	}
3821 3822 3823 3824
}

void intel_dp_stop_link_train(struct intel_dp *intel_dp)
{
3825
	intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3826
				DP_TRAINING_PATTERN_DISABLE);
3827 3828 3829
}

static void
C
Chris Wilson 已提交
3830
intel_dp_link_down(struct intel_dp *intel_dp)
3831
{
3832
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3833
	struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3834
	enum port port = intel_dig_port->port;
3835
	struct drm_device *dev = intel_dig_port->base.base.dev;
3836
	struct drm_i915_private *dev_priv = dev->dev_private;
C
Chris Wilson 已提交
3837
	uint32_t DP = intel_dp->DP;
3838

3839
	if (WARN_ON(HAS_DDI(dev)))
3840 3841
		return;

3842
	if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3843 3844
		return;

3845
	DRM_DEBUG_KMS("\n");
3846

3847 3848
	if ((IS_GEN7(dev) && port == PORT_A) ||
	    (HAS_PCH_CPT(dev) && port != PORT_A)) {
3849
		DP &= ~DP_LINK_TRAIN_MASK_CPT;
3850
		DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3851
	} else {
3852 3853 3854 3855
		if (IS_CHERRYVIEW(dev))
			DP &= ~DP_LINK_TRAIN_MASK_CHV;
		else
			DP &= ~DP_LINK_TRAIN_MASK;
3856
		DP |= DP_LINK_TRAIN_PAT_IDLE;
3857
	}
3858
	I915_WRITE(intel_dp->output_reg, DP);
3859
	POSTING_READ(intel_dp->output_reg);
3860

3861 3862 3863 3864 3865 3866 3867 3868 3869 3870 3871 3872 3873 3874 3875 3876 3877
	DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
	I915_WRITE(intel_dp->output_reg, DP);
	POSTING_READ(intel_dp->output_reg);

	/*
	 * HW workaround for IBX, we need to move the port
	 * to transcoder A after disabling it to allow the
	 * matching HDMI port to be enabled on transcoder A.
	 */
	if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
		/* always enable with pattern 1 (as per spec) */
		DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
		DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
		I915_WRITE(intel_dp->output_reg, DP);
		POSTING_READ(intel_dp->output_reg);

		DP &= ~DP_PORT_EN;
3878
		I915_WRITE(intel_dp->output_reg, DP);
3879
		POSTING_READ(intel_dp->output_reg);
3880 3881
	}

3882
	msleep(intel_dp->panel_power_down_delay);
3883 3884
}

3885 3886
static bool
intel_dp_get_dpcd(struct intel_dp *intel_dp)
3887
{
R
Rodrigo Vivi 已提交
3888 3889 3890
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
3891
	uint8_t rev;
R
Rodrigo Vivi 已提交
3892

3893 3894
	if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
				    sizeof(intel_dp->dpcd)) < 0)
3895
		return false; /* aux transfer failed */
3896

3897
	DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3898

3899 3900 3901
	if (intel_dp->dpcd[DP_DPCD_REV] == 0)
		return false; /* DPCD not present */

3902 3903
	/* Check if the panel supports PSR */
	memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3904
	if (is_edp(intel_dp)) {
3905 3906 3907
		intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
					intel_dp->psr_dpcd,
					sizeof(intel_dp->psr_dpcd));
R
Rodrigo Vivi 已提交
3908 3909
		if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
			dev_priv->psr.sink_support = true;
3910
			DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
R
Rodrigo Vivi 已提交
3911
		}
3912 3913 3914 3915 3916 3917 3918 3919 3920 3921 3922 3923 3924 3925 3926

		if (INTEL_INFO(dev)->gen >= 9 &&
			(intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
			uint8_t frame_sync_cap;

			dev_priv->psr.sink_support = true;
			intel_dp_dpcd_read_wake(&intel_dp->aux,
					DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
					&frame_sync_cap, 1);
			dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
			/* PSR2 needs frame sync as well */
			dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
			DRM_DEBUG_KMS("PSR2 %s on sink",
				dev_priv->psr.psr2_support ? "supported" : "not supported");
		}
3927 3928
	}

3929
	/* Training Pattern 3 support, both source and sink */
3930
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3931 3932
	    intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
	    (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {
3933
		intel_dp->use_tps3 = true;
3934
		DRM_DEBUG_KMS("Displayport TPS3 supported\n");
3935 3936 3937
	} else
		intel_dp->use_tps3 = false;

3938 3939 3940 3941 3942
	/* Intermediate frequency support */
	if (is_edp(intel_dp) &&
	    (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] &	DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
	    (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
	    (rev >= 0x03)) { /* eDp v1.4 or higher */
3943
		__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3944 3945
		int i;

3946 3947
		intel_dp_dpcd_read_wake(&intel_dp->aux,
				DP_SUPPORTED_LINK_RATES,
3948 3949
				sink_rates,
				sizeof(sink_rates));
3950

3951 3952
		for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
			int val = le16_to_cpu(sink_rates[i]);
3953 3954 3955 3956

			if (val == 0)
				break;

3957 3958
			/* Value read is in kHz while drm clock is saved in deca-kHz */
			intel_dp->sink_rates[i] = (val * 200) / 10;
3959
		}
3960
		intel_dp->num_sink_rates = i;
3961
	}
3962 3963 3964

	intel_dp_print_rates(intel_dp);

3965 3966 3967 3968 3969 3970 3971
	if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
	      DP_DWN_STRM_PORT_PRESENT))
		return true; /* native DP sink */

	if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
		return true; /* no per-port downstream info */

3972 3973 3974
	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
				    intel_dp->downstream_ports,
				    DP_MAX_DOWNSTREAM_PORTS) < 0)
3975 3976 3977
		return false; /* downstream port status fetch failed */

	return true;
3978 3979
}

3980 3981 3982 3983 3984 3985 3986 3987
static void
intel_dp_probe_oui(struct intel_dp *intel_dp)
{
	u8 buf[3];

	if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
		return;

3988
	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3989 3990 3991
		DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
			      buf[0], buf[1], buf[2]);

3992
	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3993 3994 3995 3996
		DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
			      buf[0], buf[1], buf[2]);
}

3997 3998 3999 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012 4013 4014 4015 4016 4017 4018 4019 4020 4021
static bool
intel_dp_probe_mst(struct intel_dp *intel_dp)
{
	u8 buf[1];

	if (!intel_dp->can_mst)
		return false;

	if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
		return false;

	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
		if (buf[0] & DP_MST_CAP) {
			DRM_DEBUG_KMS("Sink is MST capable\n");
			intel_dp->is_mst = true;
		} else {
			DRM_DEBUG_KMS("Sink is not MST capable\n");
			intel_dp->is_mst = false;
		}
	}

	drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
	return intel_dp->is_mst;
}

4022
static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
4023
{
4024 4025
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
R
Rodrigo Vivi 已提交
4026
	u8 buf;
4027
	int ret = 0;
4028

4029 4030
	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
		DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
4031 4032
		ret = -EIO;
		goto out;
4033 4034
	}

4035
	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
4036
			       buf & ~DP_TEST_SINK_START) < 0) {
4037
		DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
4038 4039 4040
		ret = -EIO;
		goto out;
	}
4041

4042
	intel_dp->sink_crc.started = false;
4043
 out:
4044
	hsw_enable_ips(intel_crtc);
4045
	return ret;
4046 4047 4048 4049 4050 4051 4052
}

static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
	u8 buf;
4053 4054
	int ret;

4055
	if (intel_dp->sink_crc.started) {
4056 4057 4058 4059
		ret = intel_dp_sink_crc_stop(intel_dp);
		if (ret)
			return ret;
	}
4060 4061 4062 4063 4064 4065 4066

	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
		return -EIO;

	if (!(buf & DP_TEST_CRC_SUPPORTED))
		return -ENOTTY;

4067 4068
	intel_dp->sink_crc.last_count = buf & DP_TEST_COUNT_MASK;

4069 4070 4071 4072
	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
		return -EIO;

	hsw_disable_ips(intel_crtc);
4073

4074
	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
4075 4076 4077
			       buf | DP_TEST_SINK_START) < 0) {
		hsw_enable_ips(intel_crtc);
		return -EIO;
4078 4079
	}

4080
	intel_dp->sink_crc.started = true;
4081 4082 4083 4084 4085 4086 4087 4088 4089
	return 0;
}

int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
	struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
	u8 buf;
4090
	int count, ret;
4091
	int attempts = 6;
4092
	bool old_equal_new;
4093 4094 4095 4096 4097

	ret = intel_dp_sink_crc_start(intel_dp);
	if (ret)
		return ret;

R
Rodrigo Vivi 已提交
4098
	do {
4099 4100
		intel_wait_for_vblank(dev, intel_crtc->pipe);

4101
		if (drm_dp_dpcd_readb(&intel_dp->aux,
4102 4103
				      DP_TEST_SINK_MISC, &buf) < 0) {
			ret = -EIO;
4104
			goto stop;
4105
		}
4106
		count = buf & DP_TEST_COUNT_MASK;
4107

4108 4109 4110 4111 4112 4113 4114 4115 4116 4117 4118
		/*
		 * Count might be reset during the loop. In this case
		 * last known count needs to be reset as well.
		 */
		if (count == 0)
			intel_dp->sink_crc.last_count = 0;

		if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
			ret = -EIO;
			goto stop;
		}
4119 4120 4121 4122 4123 4124

		old_equal_new = (count == intel_dp->sink_crc.last_count &&
				 !memcmp(intel_dp->sink_crc.last_crc, crc,
					 6 * sizeof(u8)));

	} while (--attempts && (count == 0 || old_equal_new));
4125 4126 4127

	intel_dp->sink_crc.last_count = buf & DP_TEST_COUNT_MASK;
	memcpy(intel_dp->sink_crc.last_crc, crc, 6 * sizeof(u8));
R
Rodrigo Vivi 已提交
4128 4129

	if (attempts == 0) {
4130 4131 4132 4133 4134 4135 4136
		if (old_equal_new) {
			DRM_DEBUG_KMS("Unreliable Sink CRC counter: Current returned CRC is identical to the previous one\n");
		} else {
			DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
			ret = -ETIMEDOUT;
			goto stop;
		}
R
Rodrigo Vivi 已提交
4137
	}
4138

4139
stop:
4140
	intel_dp_sink_crc_stop(intel_dp);
4141
	return ret;
4142 4143
}

4144 4145 4146
static bool
intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
{
4147 4148 4149
	return intel_dp_dpcd_read_wake(&intel_dp->aux,
				       DP_DEVICE_SERVICE_IRQ_VECTOR,
				       sink_irq_vector, 1) == 1;
4150 4151
}

4152 4153 4154 4155 4156 4157 4158 4159 4160 4161 4162 4163 4164 4165
static bool
intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
{
	int ret;

	ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
					     DP_SINK_COUNT_ESI,
					     sink_irq_vector, 14);
	if (ret != 14)
		return false;

	return true;
}

4166 4167 4168 4169 4170 4171 4172 4173 4174 4175 4176 4177 4178
static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
{
	uint8_t test_result = DP_TEST_ACK;
	return test_result;
}

static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
{
	uint8_t test_result = DP_TEST_NAK;
	return test_result;
}

static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4179
{
4180
	uint8_t test_result = DP_TEST_NAK;
4181 4182 4183 4184
	struct intel_connector *intel_connector = intel_dp->attached_connector;
	struct drm_connector *connector = &intel_connector->base;

	if (intel_connector->detect_edid == NULL ||
4185
	    connector->edid_corrupt ||
4186 4187 4188 4189 4190 4191 4192 4193 4194 4195 4196 4197 4198 4199 4200
	    intel_dp->aux.i2c_defer_count > 6) {
		/* Check EDID read for NACKs, DEFERs and corruption
		 * (DP CTS 1.2 Core r1.1)
		 *    4.2.2.4 : Failed EDID read, I2C_NAK
		 *    4.2.2.5 : Failed EDID read, I2C_DEFER
		 *    4.2.2.6 : EDID corruption detected
		 * Use failsafe mode for all cases
		 */
		if (intel_dp->aux.i2c_nack_count > 0 ||
			intel_dp->aux.i2c_defer_count > 0)
			DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
				      intel_dp->aux.i2c_nack_count,
				      intel_dp->aux.i2c_defer_count);
		intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
	} else {
4201 4202 4203 4204 4205 4206 4207
		struct edid *block = intel_connector->detect_edid;

		/* We have to write the checksum
		 * of the last block read
		 */
		block += intel_connector->detect_edid->extensions;

4208 4209
		if (!drm_dp_dpcd_write(&intel_dp->aux,
					DP_TEST_EDID_CHECKSUM,
4210
					&block->checksum,
D
Dan Carpenter 已提交
4211
					1))
4212 4213 4214 4215 4216 4217 4218 4219 4220
			DRM_DEBUG_KMS("Failed to write EDID checksum\n");

		test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
		intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
	}

	/* Set test active flag here so userspace doesn't interrupt things */
	intel_dp->compliance_test_active = 1;

4221 4222 4223 4224
	return test_result;
}

static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4225
{
4226 4227 4228 4229 4230 4231 4232 4233 4234 4235
	uint8_t test_result = DP_TEST_NAK;
	return test_result;
}

static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
{
	uint8_t response = DP_TEST_NAK;
	uint8_t rxdata = 0;
	int status = 0;

4236
	intel_dp->compliance_test_active = 0;
4237
	intel_dp->compliance_test_type = 0;
4238 4239
	intel_dp->compliance_test_data = 0;

4240 4241 4242 4243 4244 4245 4246 4247 4248 4249 4250 4251 4252 4253 4254 4255 4256 4257 4258 4259 4260 4261 4262 4263 4264 4265 4266 4267 4268 4269 4270 4271 4272 4273 4274 4275 4276 4277 4278 4279 4280
	intel_dp->aux.i2c_nack_count = 0;
	intel_dp->aux.i2c_defer_count = 0;

	status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
	if (status <= 0) {
		DRM_DEBUG_KMS("Could not read test request from sink\n");
		goto update_status;
	}

	switch (rxdata) {
	case DP_TEST_LINK_TRAINING:
		DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
		intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
		response = intel_dp_autotest_link_training(intel_dp);
		break;
	case DP_TEST_LINK_VIDEO_PATTERN:
		DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
		intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
		response = intel_dp_autotest_video_pattern(intel_dp);
		break;
	case DP_TEST_LINK_EDID_READ:
		DRM_DEBUG_KMS("EDID test requested\n");
		intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
		response = intel_dp_autotest_edid(intel_dp);
		break;
	case DP_TEST_LINK_PHY_TEST_PATTERN:
		DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
		intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
		response = intel_dp_autotest_phy_pattern(intel_dp);
		break;
	default:
		DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
		break;
	}

update_status:
	status = drm_dp_dpcd_write(&intel_dp->aux,
				   DP_TEST_RESPONSE,
				   &response, 1);
	if (status <= 0)
		DRM_DEBUG_KMS("Could not write test response to sink\n");
4281 4282
}

4283 4284 4285 4286 4287 4288 4289 4290 4291 4292 4293 4294 4295 4296 4297
static int
intel_dp_check_mst_status(struct intel_dp *intel_dp)
{
	bool bret;

	if (intel_dp->is_mst) {
		u8 esi[16] = { 0 };
		int ret = 0;
		int retry;
		bool handled;
		bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
go_again:
		if (bret == true) {

			/* check link status - esi[10] = 0x200c */
4298
			if (intel_dp->active_mst_links &&
4299
			    !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4300 4301 4302 4303 4304 4305
				DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
				intel_dp_start_link_train(intel_dp);
				intel_dp_complete_link_train(intel_dp);
				intel_dp_stop_link_train(intel_dp);
			}

4306
			DRM_DEBUG_KMS("got esi %3ph\n", esi);
4307 4308 4309 4310 4311 4312 4313 4314 4315 4316 4317 4318 4319 4320 4321
			ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);

			if (handled) {
				for (retry = 0; retry < 3; retry++) {
					int wret;
					wret = drm_dp_dpcd_write(&intel_dp->aux,
								 DP_SINK_COUNT_ESI+1,
								 &esi[1], 3);
					if (wret == 3) {
						break;
					}
				}

				bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
				if (bret == true) {
4322
					DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4323 4324 4325 4326 4327 4328 4329 4330 4331 4332 4333 4334 4335 4336 4337 4338 4339 4340
					goto go_again;
				}
			} else
				ret = 0;

			return ret;
		} else {
			struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
			DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
			intel_dp->is_mst = false;
			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
			/* send a hotplug event */
			drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
		}
	}
	return -EINVAL;
}

4341 4342 4343 4344 4345 4346 4347 4348
/*
 * According to DP spec
 * 5.1.2:
 *  1. Read DPCD
 *  2. Configure link according to Receiver Capabilities
 *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
 *  4. Check link status on receipt of hot-plug interrupt
 */
4349
static void
C
Chris Wilson 已提交
4350
intel_dp_check_link_status(struct intel_dp *intel_dp)
4351
{
4352
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
4353
	struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4354
	u8 sink_irq_vector;
4355
	u8 link_status[DP_LINK_STATUS_SIZE];
4356

4357 4358
	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));

4359
	if (!intel_encoder->base.crtc)
4360 4361
		return;

4362 4363 4364
	if (!to_intel_crtc(intel_encoder->base.crtc)->active)
		return;

4365
	/* Try to read receiver status if the link appears to be up */
4366
	if (!intel_dp_get_link_status(intel_dp, link_status)) {
4367 4368 4369
		return;
	}

4370
	/* Now read the DPCD to see if it's actually running */
4371
	if (!intel_dp_get_dpcd(intel_dp)) {
4372 4373 4374
		return;
	}

4375 4376 4377 4378
	/* Try to read the source of the interrupt */
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
		/* Clear interrupt source */
4379 4380 4381
		drm_dp_dpcd_writeb(&intel_dp->aux,
				   DP_DEVICE_SERVICE_IRQ_VECTOR,
				   sink_irq_vector);
4382 4383

		if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4384
			DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
4385 4386 4387 4388
		if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
			DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
	}

4389
	if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
4390
		DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4391
			      intel_encoder->base.name);
4392 4393
		intel_dp_start_link_train(intel_dp);
		intel_dp_complete_link_train(intel_dp);
4394
		intel_dp_stop_link_train(intel_dp);
4395
	}
4396 4397
}

4398
/* XXX this is probably wrong for multiple downstream ports */
4399
static enum drm_connector_status
4400
intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4401
{
4402 4403 4404 4405 4406 4407 4408 4409
	uint8_t *dpcd = intel_dp->dpcd;
	uint8_t type;

	if (!intel_dp_get_dpcd(intel_dp))
		return connector_status_disconnected;

	/* if there's no downstream port, we're done */
	if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
4410
		return connector_status_connected;
4411 4412

	/* If we're HPD-aware, SINK_COUNT changes dynamically */
4413 4414
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4415
		uint8_t reg;
4416 4417 4418

		if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
					    &reg, 1) < 0)
4419
			return connector_status_unknown;
4420

4421 4422
		return DP_GET_SINK_COUNT(reg) ? connector_status_connected
					      : connector_status_disconnected;
4423 4424 4425
	}

	/* If no HPD, poke DDC gently */
4426
	if (drm_probe_ddc(&intel_dp->aux.ddc))
4427
		return connector_status_connected;
4428 4429

	/* Well we tried, say unknown for unreliable port types */
4430 4431 4432 4433 4434 4435 4436 4437 4438 4439 4440 4441
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
		type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
		if (type == DP_DS_PORT_TYPE_VGA ||
		    type == DP_DS_PORT_TYPE_NON_EDID)
			return connector_status_unknown;
	} else {
		type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
			DP_DWN_STRM_PORT_TYPE_MASK;
		if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
		    type == DP_DWN_STRM_PORT_TYPE_OTHER)
			return connector_status_unknown;
	}
4442 4443 4444

	/* Anything else is out of spec, warn and ignore */
	DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4445
	return connector_status_disconnected;
4446 4447
}

4448 4449 4450 4451 4452 4453 4454 4455 4456 4457 4458 4459 4460
static enum drm_connector_status
edp_detect(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	enum drm_connector_status status;

	status = intel_panel_detect(dev);
	if (status == connector_status_unknown)
		status = connector_status_connected;

	return status;
}

4461
static enum drm_connector_status
Z
Zhenyu Wang 已提交
4462
ironlake_dp_detect(struct intel_dp *intel_dp)
4463
{
4464
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
4465 4466
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4467

4468 4469 4470
	if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
		return connector_status_disconnected;

4471
	return intel_dp_detect_dpcd(intel_dp);
4472 4473
}

4474 4475
static int g4x_digital_port_connected(struct drm_device *dev,
				       struct intel_digital_port *intel_dig_port)
4476 4477
{
	struct drm_i915_private *dev_priv = dev->dev_private;
4478
	uint32_t bit;
4479

4480 4481 4482 4483 4484 4485 4486 4487 4488 4489 4490 4491
	if (IS_VALLEYVIEW(dev)) {
		switch (intel_dig_port->port) {
		case PORT_B:
			bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
			break;
		case PORT_C:
			bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
			break;
		case PORT_D:
			bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
			break;
		default:
4492
			return -EINVAL;
4493 4494 4495 4496 4497 4498 4499 4500 4501 4502 4503 4504 4505
		}
	} else {
		switch (intel_dig_port->port) {
		case PORT_B:
			bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
			break;
		case PORT_C:
			bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
			break;
		case PORT_D:
			bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
			break;
		default:
4506
			return -EINVAL;
4507
		}
4508 4509
	}

4510
	if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
4511 4512 4513 4514 4515 4516 4517 4518 4519 4520 4521 4522 4523 4524 4525 4526 4527 4528 4529 4530 4531 4532 4533 4534 4535
		return 0;
	return 1;
}

static enum drm_connector_status
g4x_dp_detect(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	int ret;

	/* Can't disconnect eDP, but you can close the lid... */
	if (is_edp(intel_dp)) {
		enum drm_connector_status status;

		status = intel_panel_detect(dev);
		if (status == connector_status_unknown)
			status = connector_status_connected;
		return status;
	}

	ret = g4x_digital_port_connected(dev, intel_dig_port);
	if (ret == -EINVAL)
		return connector_status_unknown;
	else if (ret == 0)
4536 4537
		return connector_status_disconnected;

4538
	return intel_dp_detect_dpcd(intel_dp);
Z
Zhenyu Wang 已提交
4539 4540
}

4541
static struct edid *
4542
intel_dp_get_edid(struct intel_dp *intel_dp)
4543
{
4544
	struct intel_connector *intel_connector = intel_dp->attached_connector;
4545

4546 4547 4548 4549
	/* use cached edid if we have one */
	if (intel_connector->edid) {
		/* invalid edid */
		if (IS_ERR(intel_connector->edid))
4550 4551
			return NULL;

J
Jani Nikula 已提交
4552
		return drm_edid_duplicate(intel_connector->edid);
4553 4554 4555 4556
	} else
		return drm_get_edid(&intel_connector->base,
				    &intel_dp->aux.ddc);
}
4557

4558 4559 4560 4561 4562
static void
intel_dp_set_edid(struct intel_dp *intel_dp)
{
	struct intel_connector *intel_connector = intel_dp->attached_connector;
	struct edid *edid;
4563

4564 4565 4566 4567 4568 4569 4570
	edid = intel_dp_get_edid(intel_dp);
	intel_connector->detect_edid = edid;

	if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
		intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
	else
		intel_dp->has_audio = drm_detect_monitor_audio(edid);
4571 4572
}

4573 4574
static void
intel_dp_unset_edid(struct intel_dp *intel_dp)
4575
{
4576
	struct intel_connector *intel_connector = intel_dp->attached_connector;
4577

4578 4579
	kfree(intel_connector->detect_edid);
	intel_connector->detect_edid = NULL;
4580

4581 4582
	intel_dp->has_audio = false;
}
4583

4584 4585 4586 4587 4588 4589 4590 4591 4592 4593 4594
static enum intel_display_power_domain
intel_dp_power_get(struct intel_dp *dp)
{
	struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
	enum intel_display_power_domain power_domain;

	power_domain = intel_display_port_power_domain(encoder);
	intel_display_power_get(to_i915(encoder->base.dev), power_domain);

	return power_domain;
}
4595

4596 4597 4598 4599 4600 4601
static void
intel_dp_power_put(struct intel_dp *dp,
		   enum intel_display_power_domain power_domain)
{
	struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
	intel_display_power_put(to_i915(encoder->base.dev), power_domain);
4602 4603
}

Z
Zhenyu Wang 已提交
4604 4605 4606 4607
static enum drm_connector_status
intel_dp_detect(struct drm_connector *connector, bool force)
{
	struct intel_dp *intel_dp = intel_attached_dp(connector);
4608 4609
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
4610
	struct drm_device *dev = connector->dev;
Z
Zhenyu Wang 已提交
4611
	enum drm_connector_status status;
4612
	enum intel_display_power_domain power_domain;
4613
	bool ret;
4614
	u8 sink_irq_vector;
Z
Zhenyu Wang 已提交
4615

4616
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4617
		      connector->base.id, connector->name);
4618
	intel_dp_unset_edid(intel_dp);
4619

4620 4621 4622 4623
	if (intel_dp->is_mst) {
		/* MST devices are disconnected from a monitor POV */
		if (intel_encoder->type != INTEL_OUTPUT_EDP)
			intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4624
		return connector_status_disconnected;
4625 4626
	}

4627
	power_domain = intel_dp_power_get(intel_dp);
Z
Zhenyu Wang 已提交
4628

4629 4630 4631 4632
	/* Can't disconnect eDP, but you can close the lid... */
	if (is_edp(intel_dp))
		status = edp_detect(intel_dp);
	else if (HAS_PCH_SPLIT(dev))
Z
Zhenyu Wang 已提交
4633 4634 4635 4636
		status = ironlake_dp_detect(intel_dp);
	else
		status = g4x_dp_detect(intel_dp);
	if (status != connector_status_connected)
4637
		goto out;
Z
Zhenyu Wang 已提交
4638

4639 4640
	intel_dp_probe_oui(intel_dp);

4641 4642 4643 4644 4645 4646 4647 4648 4649 4650
	ret = intel_dp_probe_mst(intel_dp);
	if (ret) {
		/* if we are in MST mode then this connector
		   won't appear connected or have anything with EDID on it */
		if (intel_encoder->type != INTEL_OUTPUT_EDP)
			intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
		status = connector_status_disconnected;
		goto out;
	}

4651
	intel_dp_set_edid(intel_dp);
Z
Zhenyu Wang 已提交
4652

4653 4654
	if (intel_encoder->type != INTEL_OUTPUT_EDP)
		intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4655 4656
	status = connector_status_connected;

4657 4658 4659 4660 4661 4662 4663 4664 4665 4666 4667 4668 4669 4670
	/* Try to read the source of the interrupt */
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
		/* Clear interrupt source */
		drm_dp_dpcd_writeb(&intel_dp->aux,
				   DP_DEVICE_SERVICE_IRQ_VECTOR,
				   sink_irq_vector);

		if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
			intel_dp_handle_test_request(intel_dp);
		if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
			DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
	}

4671
out:
4672
	intel_dp_power_put(intel_dp, power_domain);
4673
	return status;
4674 4675
}

4676 4677
static void
intel_dp_force(struct drm_connector *connector)
4678
{
4679
	struct intel_dp *intel_dp = intel_attached_dp(connector);
4680
	struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4681
	enum intel_display_power_domain power_domain;
4682

4683 4684 4685
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
		      connector->base.id, connector->name);
	intel_dp_unset_edid(intel_dp);
4686

4687 4688
	if (connector->status != connector_status_connected)
		return;
4689

4690 4691 4692 4693 4694 4695 4696 4697 4698 4699 4700 4701 4702 4703 4704 4705 4706 4707 4708 4709 4710
	power_domain = intel_dp_power_get(intel_dp);

	intel_dp_set_edid(intel_dp);

	intel_dp_power_put(intel_dp, power_domain);

	if (intel_encoder->type != INTEL_OUTPUT_EDP)
		intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
}

static int intel_dp_get_modes(struct drm_connector *connector)
{
	struct intel_connector *intel_connector = to_intel_connector(connector);
	struct edid *edid;

	edid = intel_connector->detect_edid;
	if (edid) {
		int ret = intel_connector_update_modes(connector, edid);
		if (ret)
			return ret;
	}
4711

4712
	/* if eDP has no EDID, fall back to fixed mode */
4713 4714
	if (is_edp(intel_attached_dp(connector)) &&
	    intel_connector->panel.fixed_mode) {
4715
		struct drm_display_mode *mode;
4716 4717

		mode = drm_mode_duplicate(connector->dev,
4718
					  intel_connector->panel.fixed_mode);
4719
		if (mode) {
4720 4721 4722 4723
			drm_mode_probed_add(connector, mode);
			return 1;
		}
	}
4724

4725
	return 0;
4726 4727
}

4728 4729 4730 4731
static bool
intel_dp_detect_audio(struct drm_connector *connector)
{
	bool has_audio = false;
4732
	struct edid *edid;
4733

4734 4735
	edid = to_intel_connector(connector)->detect_edid;
	if (edid)
4736
		has_audio = drm_detect_monitor_audio(edid);
4737

4738 4739 4740
	return has_audio;
}

4741 4742 4743 4744 4745
static int
intel_dp_set_property(struct drm_connector *connector,
		      struct drm_property *property,
		      uint64_t val)
{
4746
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
4747
	struct intel_connector *intel_connector = to_intel_connector(connector);
4748 4749
	struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4750 4751
	int ret;

4752
	ret = drm_object_property_set_value(&connector->base, property, val);
4753 4754 4755
	if (ret)
		return ret;

4756
	if (property == dev_priv->force_audio_property) {
4757 4758 4759 4760
		int i = val;
		bool has_audio;

		if (i == intel_dp->force_audio)
4761 4762
			return 0;

4763
		intel_dp->force_audio = i;
4764

4765
		if (i == HDMI_AUDIO_AUTO)
4766 4767
			has_audio = intel_dp_detect_audio(connector);
		else
4768
			has_audio = (i == HDMI_AUDIO_ON);
4769 4770

		if (has_audio == intel_dp->has_audio)
4771 4772
			return 0;

4773
		intel_dp->has_audio = has_audio;
4774 4775 4776
		goto done;
	}

4777
	if (property == dev_priv->broadcast_rgb_property) {
4778
		bool old_auto = intel_dp->color_range_auto;
4779
		bool old_range = intel_dp->limited_color_range;
4780

4781 4782 4783 4784 4785 4786
		switch (val) {
		case INTEL_BROADCAST_RGB_AUTO:
			intel_dp->color_range_auto = true;
			break;
		case INTEL_BROADCAST_RGB_FULL:
			intel_dp->color_range_auto = false;
4787
			intel_dp->limited_color_range = false;
4788 4789 4790
			break;
		case INTEL_BROADCAST_RGB_LIMITED:
			intel_dp->color_range_auto = false;
4791
			intel_dp->limited_color_range = true;
4792 4793 4794 4795
			break;
		default:
			return -EINVAL;
		}
4796 4797

		if (old_auto == intel_dp->color_range_auto &&
4798
		    old_range == intel_dp->limited_color_range)
4799 4800
			return 0;

4801 4802 4803
		goto done;
	}

4804 4805 4806 4807 4808 4809 4810 4811 4812 4813 4814 4815 4816 4817 4818 4819
	if (is_edp(intel_dp) &&
	    property == connector->dev->mode_config.scaling_mode_property) {
		if (val == DRM_MODE_SCALE_NONE) {
			DRM_DEBUG_KMS("no scaling not supported\n");
			return -EINVAL;
		}

		if (intel_connector->panel.fitting_mode == val) {
			/* the eDP scaling property is not changed */
			return 0;
		}
		intel_connector->panel.fitting_mode = val;

		goto done;
	}

4820 4821 4822
	return -EINVAL;

done:
4823 4824
	if (intel_encoder->base.crtc)
		intel_crtc_restore_mode(intel_encoder->base.crtc);
4825 4826 4827 4828

	return 0;
}

4829
static void
4830
intel_dp_connector_destroy(struct drm_connector *connector)
4831
{
4832
	struct intel_connector *intel_connector = to_intel_connector(connector);
4833

4834
	kfree(intel_connector->detect_edid);
4835

4836 4837 4838
	if (!IS_ERR_OR_NULL(intel_connector->edid))
		kfree(intel_connector->edid);

4839 4840 4841
	/* Can't call is_edp() since the encoder may have been destroyed
	 * already. */
	if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4842
		intel_panel_fini(&intel_connector->panel);
4843

4844
	drm_connector_cleanup(connector);
4845
	kfree(connector);
4846 4847
}

P
Paulo Zanoni 已提交
4848
void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4849
{
4850 4851
	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
	struct intel_dp *intel_dp = &intel_dig_port->dp;
4852

4853
	drm_dp_aux_unregister(&intel_dp->aux);
4854
	intel_dp_mst_encoder_cleanup(intel_dig_port);
4855 4856
	if (is_edp(intel_dp)) {
		cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4857 4858 4859 4860
		/*
		 * vdd might still be enabled do to the delayed vdd off.
		 * Make sure vdd is actually turned off here.
		 */
4861
		pps_lock(intel_dp);
4862
		edp_panel_vdd_off_sync(intel_dp);
4863 4864
		pps_unlock(intel_dp);

4865 4866 4867 4868
		if (intel_dp->edp_notifier.notifier_call) {
			unregister_reboot_notifier(&intel_dp->edp_notifier);
			intel_dp->edp_notifier.notifier_call = NULL;
		}
4869
	}
4870
	drm_encoder_cleanup(encoder);
4871
	kfree(intel_dig_port);
4872 4873
}

4874 4875 4876 4877 4878 4879 4880
static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);

	if (!is_edp(intel_dp))
		return;

4881 4882 4883 4884
	/*
	 * vdd might still be enabled do to the delayed vdd off.
	 * Make sure vdd is actually turned off here.
	 */
4885
	cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4886
	pps_lock(intel_dp);
4887
	edp_panel_vdd_off_sync(intel_dp);
4888
	pps_unlock(intel_dp);
4889 4890
}

4891 4892 4893 4894 4895 4896 4897 4898 4899 4900 4901 4902 4903 4904 4905 4906 4907 4908 4909 4910 4911 4912 4913 4914 4915
static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum intel_display_power_domain power_domain;

	lockdep_assert_held(&dev_priv->pps_mutex);

	if (!edp_have_panel_vdd(intel_dp))
		return;

	/*
	 * The VDD bit needs a power domain reference, so if the bit is
	 * already enabled when we boot or resume, grab this reference and
	 * schedule a vdd off, so we don't hold on to the reference
	 * indefinitely.
	 */
	DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
	power_domain = intel_display_port_power_domain(&intel_dig_port->base);
	intel_display_power_get(dev_priv, power_domain);

	edp_panel_vdd_schedule_off(intel_dp);
}

4916 4917
static void intel_dp_encoder_reset(struct drm_encoder *encoder)
{
4918 4919 4920 4921 4922 4923 4924 4925 4926 4927 4928 4929 4930 4931 4932 4933 4934 4935 4936
	struct intel_dp *intel_dp;

	if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
		return;

	intel_dp = enc_to_intel_dp(encoder);

	pps_lock(intel_dp);

	/*
	 * Read out the current power sequencer assignment,
	 * in case the BIOS did something with it.
	 */
	if (IS_VALLEYVIEW(encoder->dev))
		vlv_initial_power_sequencer_setup(intel_dp);

	intel_edp_panel_vdd_sanitize(intel_dp);

	pps_unlock(intel_dp);
4937 4938
}

4939
static const struct drm_connector_funcs intel_dp_connector_funcs = {
4940
	.dpms = drm_atomic_helper_connector_dpms,
4941
	.detect = intel_dp_detect,
4942
	.force = intel_dp_force,
4943
	.fill_modes = drm_helper_probe_single_connector_modes,
4944
	.set_property = intel_dp_set_property,
4945
	.atomic_get_property = intel_connector_atomic_get_property,
4946
	.destroy = intel_dp_connector_destroy,
4947
	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4948
	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
4949 4950 4951 4952 4953
};

static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
	.get_modes = intel_dp_get_modes,
	.mode_valid = intel_dp_mode_valid,
4954
	.best_encoder = intel_best_encoder,
4955 4956 4957
};

static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4958
	.reset = intel_dp_encoder_reset,
4959
	.destroy = intel_dp_encoder_destroy,
4960 4961
};

4962
enum irqreturn
4963 4964 4965
intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
{
	struct intel_dp *intel_dp = &intel_dig_port->dp;
4966
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
4967 4968
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
4969
	enum intel_display_power_domain power_domain;
4970
	enum irqreturn ret = IRQ_NONE;
4971

4972 4973
	if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
		intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
4974

4975 4976 4977 4978 4979 4980 4981 4982 4983
	if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
		/*
		 * vdd off can generate a long pulse on eDP which
		 * would require vdd on to handle it, and thus we
		 * would end up in an endless cycle of
		 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
		 */
		DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
			      port_name(intel_dig_port->port));
4984
		return IRQ_HANDLED;
4985 4986
	}

4987 4988
	DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
		      port_name(intel_dig_port->port),
4989
		      long_hpd ? "long" : "short");
4990

4991 4992 4993
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_get(dev_priv, power_domain);

4994
	if (long_hpd) {
4995 4996
		/* indicate that we need to restart link training */
		intel_dp->train_set_valid = false;
4997 4998 4999 5000 5001 5002 5003 5004

		if (HAS_PCH_SPLIT(dev)) {
			if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
				goto mst_fail;
		} else {
			if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
				goto mst_fail;
		}
5005 5006 5007 5008 5009 5010 5011 5012 5013 5014 5015 5016

		if (!intel_dp_get_dpcd(intel_dp)) {
			goto mst_fail;
		}

		intel_dp_probe_oui(intel_dp);

		if (!intel_dp_probe_mst(intel_dp))
			goto mst_fail;

	} else {
		if (intel_dp->is_mst) {
5017
			if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
5018 5019 5020 5021 5022 5023 5024 5025
				goto mst_fail;
		}

		if (!intel_dp->is_mst) {
			/*
			 * we'll check the link status via the normal hot plug path later -
			 * but for short hpds we should check it now
			 */
5026
			drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
5027
			intel_dp_check_link_status(intel_dp);
5028
			drm_modeset_unlock(&dev->mode_config.connection_mutex);
5029 5030
		}
	}
5031 5032 5033

	ret = IRQ_HANDLED;

5034
	goto put_power;
5035 5036 5037 5038 5039 5040 5041
mst_fail:
	/* if we were in MST mode, and device is not there get out of MST mode */
	if (intel_dp->is_mst) {
		DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
		intel_dp->is_mst = false;
		drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
	}
5042 5043 5044 5045
put_power:
	intel_display_power_put(dev_priv, power_domain);

	return ret;
5046 5047
}

5048 5049
/* Return which DP Port should be selected for Transcoder DP control */
int
5050
intel_trans_dp_port_sel(struct drm_crtc *crtc)
5051 5052
{
	struct drm_device *dev = crtc->dev;
5053 5054
	struct intel_encoder *intel_encoder;
	struct intel_dp *intel_dp;
5055

5056 5057
	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		intel_dp = enc_to_intel_dp(&intel_encoder->base);
5058

5059 5060
		if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
		    intel_encoder->type == INTEL_OUTPUT_EDP)
C
Chris Wilson 已提交
5061
			return intel_dp->output_reg;
5062
	}
C
Chris Wilson 已提交
5063

5064 5065 5066
	return -1;
}

5067
/* check the VBT to see whether the eDP is on DP-D port */
5068
bool intel_dp_is_edp(struct drm_device *dev, enum port port)
5069 5070
{
	struct drm_i915_private *dev_priv = dev->dev_private;
5071
	union child_device_config *p_child;
5072
	int i;
5073 5074 5075 5076 5077
	static const short port_mapping[] = {
		[PORT_B] = PORT_IDPB,
		[PORT_C] = PORT_IDPC,
		[PORT_D] = PORT_IDPD,
	};
5078

5079 5080 5081
	if (port == PORT_A)
		return true;

5082
	if (!dev_priv->vbt.child_dev_num)
5083 5084
		return false;

5085 5086
	for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
		p_child = dev_priv->vbt.child_dev + i;
5087

5088
		if (p_child->common.dvo_port == port_mapping[port] &&
5089 5090
		    (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
		    (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
5091 5092 5093 5094 5095
			return true;
	}
	return false;
}

5096
void
5097 5098
intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
{
5099 5100
	struct intel_connector *intel_connector = to_intel_connector(connector);

5101
	intel_attach_force_audio_property(connector);
5102
	intel_attach_broadcast_rgb_property(connector);
5103
	intel_dp->color_range_auto = true;
5104 5105 5106

	if (is_edp(intel_dp)) {
		drm_mode_create_scaling_mode_property(connector->dev);
5107 5108
		drm_object_attach_property(
			&connector->base,
5109
			connector->dev->mode_config.scaling_mode_property,
5110 5111
			DRM_MODE_SCALE_ASPECT);
		intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
5112
	}
5113 5114
}

5115 5116 5117 5118 5119 5120 5121
static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
{
	intel_dp->last_power_cycle = jiffies;
	intel_dp->last_power_on = jiffies;
	intel_dp->last_backlight_off = jiffies;
}

5122 5123
static void
intel_dp_init_panel_power_sequencer(struct drm_device *dev,
5124
				    struct intel_dp *intel_dp)
5125 5126
{
	struct drm_i915_private *dev_priv = dev->dev_private;
5127 5128
	struct edp_power_seq cur, vbt, spec,
		*final = &intel_dp->pps_delays;
5129 5130
	u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
	int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg = 0;
5131

V
Ville Syrjälä 已提交
5132 5133
	lockdep_assert_held(&dev_priv->pps_mutex);

5134 5135 5136 5137
	/* already initialized? */
	if (final->t11_t12 != 0)
		return;

5138 5139 5140 5141 5142 5143 5144 5145 5146 5147
	if (IS_BROXTON(dev)) {
		/*
		 * TODO: BXT has 2 sets of PPS registers.
		 * Correct Register for Broxton need to be identified
		 * using VBT. hardcoding for now
		 */
		pp_ctrl_reg = BXT_PP_CONTROL(0);
		pp_on_reg = BXT_PP_ON_DELAYS(0);
		pp_off_reg = BXT_PP_OFF_DELAYS(0);
	} else if (HAS_PCH_SPLIT(dev)) {
5148
		pp_ctrl_reg = PCH_PP_CONTROL;
5149 5150 5151 5152
		pp_on_reg = PCH_PP_ON_DELAYS;
		pp_off_reg = PCH_PP_OFF_DELAYS;
		pp_div_reg = PCH_PP_DIVISOR;
	} else {
5153 5154 5155 5156 5157 5158
		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);

		pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
		pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
		pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
		pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
5159
	}
5160 5161 5162

	/* Workaround: Need to write PP_CONTROL with the unlock key as
	 * the very first thing. */
5163
	pp_ctl = ironlake_get_pp_control(intel_dp);
5164

5165 5166
	pp_on = I915_READ(pp_on_reg);
	pp_off = I915_READ(pp_off_reg);
5167 5168 5169 5170
	if (!IS_BROXTON(dev)) {
		I915_WRITE(pp_ctrl_reg, pp_ctl);
		pp_div = I915_READ(pp_div_reg);
	}
5171 5172 5173 5174 5175 5176 5177 5178 5179 5180 5181 5182 5183 5184

	/* Pull timing values out of registers */
	cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
		PANEL_POWER_UP_DELAY_SHIFT;

	cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
		PANEL_LIGHT_ON_DELAY_SHIFT;

	cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
		PANEL_LIGHT_OFF_DELAY_SHIFT;

	cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
		PANEL_POWER_DOWN_DELAY_SHIFT;

5185 5186 5187 5188 5189 5190 5191 5192 5193
	if (IS_BROXTON(dev)) {
		u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
			BXT_POWER_CYCLE_DELAY_SHIFT;
		if (tmp > 0)
			cur.t11_t12 = (tmp - 1) * 1000;
		else
			cur.t11_t12 = 0;
	} else {
		cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5194
		       PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5195
	}
5196 5197 5198 5199

	DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		      cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);

5200
	vbt = dev_priv->vbt.edp_pps;
5201 5202 5203 5204 5205 5206 5207 5208 5209 5210 5211 5212 5213 5214 5215 5216 5217 5218

	/* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
	 * our hw here, which are all in 100usec. */
	spec.t1_t3 = 210 * 10;
	spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
	spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
	spec.t10 = 500 * 10;
	/* This one is special and actually in units of 100ms, but zero
	 * based in the hw (so we need to add 100 ms). But the sw vbt
	 * table multiplies it with 1000 to make it in units of 100usec,
	 * too. */
	spec.t11_t12 = (510 + 100) * 10;

	DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		      vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);

	/* Use the max of the register settings and vbt. If both are
	 * unset, fall back to the spec limits. */
5219
#define assign_final(field)	final->field = (max(cur.field, vbt.field) == 0 ? \
5220 5221 5222 5223 5224 5225 5226 5227 5228
				       spec.field : \
				       max(cur.field, vbt.field))
	assign_final(t1_t3);
	assign_final(t8);
	assign_final(t9);
	assign_final(t10);
	assign_final(t11_t12);
#undef assign_final

5229
#define get_delay(field)	(DIV_ROUND_UP(final->field, 10))
5230 5231 5232 5233 5234 5235 5236
	intel_dp->panel_power_up_delay = get_delay(t1_t3);
	intel_dp->backlight_on_delay = get_delay(t8);
	intel_dp->backlight_off_delay = get_delay(t9);
	intel_dp->panel_power_down_delay = get_delay(t10);
	intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
#undef get_delay

5237 5238 5239 5240 5241 5242 5243 5244 5245 5246
	DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
		      intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
		      intel_dp->panel_power_cycle_delay);

	DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
		      intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
}

static void
intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
5247
					      struct intel_dp *intel_dp)
5248 5249
{
	struct drm_i915_private *dev_priv = dev->dev_private;
5250 5251
	u32 pp_on, pp_off, pp_div, port_sel = 0;
	int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
5252
	int pp_on_reg, pp_off_reg, pp_div_reg = 0, pp_ctrl_reg;
5253
	enum port port = dp_to_dig_port(intel_dp)->port;
5254
	const struct edp_power_seq *seq = &intel_dp->pps_delays;
5255

V
Ville Syrjälä 已提交
5256
	lockdep_assert_held(&dev_priv->pps_mutex);
5257

5258 5259 5260 5261 5262 5263 5264 5265 5266 5267 5268
	if (IS_BROXTON(dev)) {
		/*
		 * TODO: BXT has 2 sets of PPS registers.
		 * Correct Register for Broxton need to be identified
		 * using VBT. hardcoding for now
		 */
		pp_ctrl_reg = BXT_PP_CONTROL(0);
		pp_on_reg = BXT_PP_ON_DELAYS(0);
		pp_off_reg = BXT_PP_OFF_DELAYS(0);

	} else if (HAS_PCH_SPLIT(dev)) {
5269 5270 5271 5272
		pp_on_reg = PCH_PP_ON_DELAYS;
		pp_off_reg = PCH_PP_OFF_DELAYS;
		pp_div_reg = PCH_PP_DIVISOR;
	} else {
5273 5274 5275 5276 5277
		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);

		pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
		pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
		pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
5278 5279
	}

5280 5281 5282 5283 5284 5285 5286 5287
	/*
	 * And finally store the new values in the power sequencer. The
	 * backlight delays are set to 1 because we do manual waits on them. For
	 * T8, even BSpec recommends doing it. For T9, if we don't do this,
	 * we'll end up waiting for the backlight off delay twice: once when we
	 * do the manual sleep, and once when we disable the panel and wait for
	 * the PP_STATUS bit to become zero.
	 */
5288
	pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5289 5290
		(1 << PANEL_LIGHT_ON_DELAY_SHIFT);
	pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5291
		 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5292 5293
	/* Compute the divisor for the pp clock, simply match the Bspec
	 * formula. */
5294 5295 5296 5297 5298 5299 5300 5301 5302 5303
	if (IS_BROXTON(dev)) {
		pp_div = I915_READ(pp_ctrl_reg);
		pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
		pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
				<< BXT_POWER_CYCLE_DELAY_SHIFT);
	} else {
		pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
		pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
				<< PANEL_POWER_CYCLE_DELAY_SHIFT);
	}
5304 5305 5306

	/* Haswell doesn't have any port selection bits for the panel
	 * power sequencer any more. */
5307
	if (IS_VALLEYVIEW(dev)) {
5308
		port_sel = PANEL_PORT_SELECT_VLV(port);
5309
	} else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5310
		if (port == PORT_A)
5311
			port_sel = PANEL_PORT_SELECT_DPA;
5312
		else
5313
			port_sel = PANEL_PORT_SELECT_DPD;
5314 5315
	}

5316 5317 5318 5319
	pp_on |= port_sel;

	I915_WRITE(pp_on_reg, pp_on);
	I915_WRITE(pp_off_reg, pp_off);
5320 5321 5322 5323
	if (IS_BROXTON(dev))
		I915_WRITE(pp_ctrl_reg, pp_div);
	else
		I915_WRITE(pp_div_reg, pp_div);
5324 5325

	DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5326 5327
		      I915_READ(pp_on_reg),
		      I915_READ(pp_off_reg),
5328 5329
		      IS_BROXTON(dev) ?
		      (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) :
5330
		      I915_READ(pp_div_reg));
5331 5332
}

5333 5334 5335 5336 5337 5338 5339 5340 5341 5342 5343 5344
/**
 * intel_dp_set_drrs_state - program registers for RR switch to take effect
 * @dev: DRM device
 * @refresh_rate: RR to be programmed
 *
 * This function gets called when refresh rate (RR) has to be changed from
 * one frequency to another. Switches can be between high and low RR
 * supported by the panel or to any other RR based on media playback (in
 * this case, RR value needs to be passed from user space).
 *
 * The caller of this function needs to take a lock on dev_priv->drrs.
 */
5345
static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
5346 5347 5348
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_encoder *encoder;
5349 5350
	struct intel_digital_port *dig_port = NULL;
	struct intel_dp *intel_dp = dev_priv->drrs.dp;
5351
	struct intel_crtc_state *config = NULL;
5352 5353
	struct intel_crtc *intel_crtc = NULL;
	u32 reg, val;
5354
	enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5355 5356 5357 5358 5359 5360

	if (refresh_rate <= 0) {
		DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
		return;
	}

5361 5362
	if (intel_dp == NULL) {
		DRM_DEBUG_KMS("DRRS not supported.\n");
5363 5364 5365
		return;
	}

5366
	/*
5367 5368
	 * FIXME: This needs proper synchronization with psr state for some
	 * platforms that cannot have PSR and DRRS enabled at the same time.
5369
	 */
5370

5371 5372
	dig_port = dp_to_dig_port(intel_dp);
	encoder = &dig_port->base;
5373
	intel_crtc = to_intel_crtc(encoder->base.crtc);
5374 5375 5376 5377 5378 5379

	if (!intel_crtc) {
		DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
		return;
	}

5380
	config = intel_crtc->config;
5381

5382
	if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5383 5384 5385 5386
		DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
		return;
	}

5387 5388
	if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
			refresh_rate)
5389 5390
		index = DRRS_LOW_RR;

5391
	if (index == dev_priv->drrs.refresh_rate_type) {
5392 5393 5394 5395 5396 5397 5398 5399 5400 5401
		DRM_DEBUG_KMS(
			"DRRS requested for previously set RR...ignoring\n");
		return;
	}

	if (!intel_crtc->active) {
		DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
		return;
	}

D
Durgadoss R 已提交
5402
	if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
5403 5404 5405 5406 5407 5408 5409 5410 5411 5412 5413 5414
		switch (index) {
		case DRRS_HIGH_RR:
			intel_dp_set_m_n(intel_crtc, M1_N1);
			break;
		case DRRS_LOW_RR:
			intel_dp_set_m_n(intel_crtc, M2_N2);
			break;
		case DRRS_MAX_RR:
		default:
			DRM_ERROR("Unsupported refreshrate type\n");
		}
	} else if (INTEL_INFO(dev)->gen > 6) {
5415
		reg = PIPECONF(intel_crtc->config->cpu_transcoder);
5416
		val = I915_READ(reg);
5417

5418
		if (index > DRRS_HIGH_RR) {
5419 5420 5421 5422
			if (IS_VALLEYVIEW(dev))
				val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
			else
				val |= PIPECONF_EDP_RR_MODE_SWITCH;
5423
		} else {
5424 5425 5426 5427
			if (IS_VALLEYVIEW(dev))
				val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
			else
				val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5428 5429 5430 5431
		}
		I915_WRITE(reg, val);
	}

5432 5433 5434 5435 5436
	dev_priv->drrs.refresh_rate_type = index;

	DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
}

5437 5438 5439 5440 5441 5442
/**
 * intel_edp_drrs_enable - init drrs struct if supported
 * @intel_dp: DP struct
 *
 * Initializes frontbuffer_bits and drrs.dp
 */
V
Vandana Kannan 已提交
5443 5444 5445 5446 5447 5448 5449 5450 5451 5452 5453 5454 5455 5456 5457 5458 5459 5460 5461 5462 5463 5464 5465 5466 5467 5468 5469
void intel_edp_drrs_enable(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = dig_port->base.base.crtc;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	if (!intel_crtc->config->has_drrs) {
		DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
		return;
	}

	mutex_lock(&dev_priv->drrs.mutex);
	if (WARN_ON(dev_priv->drrs.dp)) {
		DRM_ERROR("DRRS already enabled\n");
		goto unlock;
	}

	dev_priv->drrs.busy_frontbuffer_bits = 0;

	dev_priv->drrs.dp = intel_dp;

unlock:
	mutex_unlock(&dev_priv->drrs.mutex);
}

5470 5471 5472 5473 5474
/**
 * intel_edp_drrs_disable - Disable DRRS
 * @intel_dp: DP struct
 *
 */
V
Vandana Kannan 已提交
5475 5476 5477 5478 5479 5480 5481 5482 5483 5484 5485 5486 5487 5488 5489 5490 5491 5492 5493 5494 5495 5496 5497 5498 5499 5500 5501 5502
void intel_edp_drrs_disable(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = dig_port->base.base.crtc;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	if (!intel_crtc->config->has_drrs)
		return;

	mutex_lock(&dev_priv->drrs.mutex);
	if (!dev_priv->drrs.dp) {
		mutex_unlock(&dev_priv->drrs.mutex);
		return;
	}

	if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
		intel_dp_set_drrs_state(dev_priv->dev,
			intel_dp->attached_connector->panel.
			fixed_mode->vrefresh);

	dev_priv->drrs.dp = NULL;
	mutex_unlock(&dev_priv->drrs.mutex);

	cancel_delayed_work_sync(&dev_priv->drrs.work);
}

5503 5504 5505 5506 5507 5508 5509 5510 5511 5512 5513 5514 5515
static void intel_edp_drrs_downclock_work(struct work_struct *work)
{
	struct drm_i915_private *dev_priv =
		container_of(work, typeof(*dev_priv), drrs.work.work);
	struct intel_dp *intel_dp;

	mutex_lock(&dev_priv->drrs.mutex);

	intel_dp = dev_priv->drrs.dp;

	if (!intel_dp)
		goto unlock;

5516
	/*
5517 5518
	 * The delayed work can race with an invalidate hence we need to
	 * recheck.
5519 5520
	 */

5521 5522
	if (dev_priv->drrs.busy_frontbuffer_bits)
		goto unlock;
5523

5524 5525 5526 5527
	if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
		intel_dp_set_drrs_state(dev_priv->dev,
			intel_dp->attached_connector->panel.
			downclock_mode->vrefresh);
5528

5529 5530
unlock:
	mutex_unlock(&dev_priv->drrs.mutex);
5531 5532
}

5533
/**
5534
 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5535 5536 5537
 * @dev: DRM device
 * @frontbuffer_bits: frontbuffer plane tracking bits
 *
5538 5539
 * This function gets called everytime rendering on the given planes start.
 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5540 5541 5542
 *
 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
 */
5543 5544 5545 5546 5547 5548 5549
void intel_edp_drrs_invalidate(struct drm_device *dev,
		unsigned frontbuffer_bits)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc;
	enum pipe pipe;

5550
	if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5551 5552
		return;

5553
	cancel_delayed_work(&dev_priv->drrs.work);
5554

5555
	mutex_lock(&dev_priv->drrs.mutex);
5556 5557 5558 5559 5560
	if (!dev_priv->drrs.dp) {
		mutex_unlock(&dev_priv->drrs.mutex);
		return;
	}

5561 5562 5563
	crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
	pipe = to_intel_crtc(crtc)->pipe;

5564 5565 5566
	frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
	dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;

5567
	/* invalidate means busy screen hence upclock */
5568
	if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5569 5570 5571 5572 5573 5574 5575
		intel_dp_set_drrs_state(dev_priv->dev,
				dev_priv->drrs.dp->attached_connector->panel.
				fixed_mode->vrefresh);

	mutex_unlock(&dev_priv->drrs.mutex);
}

5576
/**
5577
 * intel_edp_drrs_flush - Restart Idleness DRRS
5578 5579 5580
 * @dev: DRM device
 * @frontbuffer_bits: frontbuffer plane tracking bits
 *
5581 5582 5583 5584
 * This function gets called every time rendering on the given planes has
 * completed or flip on a crtc is completed. So DRRS should be upclocked
 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
 * if no other planes are dirty.
5585 5586 5587
 *
 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
 */
5588 5589 5590 5591 5592 5593 5594
void intel_edp_drrs_flush(struct drm_device *dev,
		unsigned frontbuffer_bits)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc;
	enum pipe pipe;

5595
	if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5596 5597
		return;

5598
	cancel_delayed_work(&dev_priv->drrs.work);
5599

5600
	mutex_lock(&dev_priv->drrs.mutex);
5601 5602 5603 5604 5605
	if (!dev_priv->drrs.dp) {
		mutex_unlock(&dev_priv->drrs.mutex);
		return;
	}

5606 5607
	crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
	pipe = to_intel_crtc(crtc)->pipe;
5608 5609

	frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5610 5611
	dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;

5612
	/* flush means busy screen hence upclock */
5613
	if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5614 5615 5616 5617 5618 5619 5620 5621 5622
		intel_dp_set_drrs_state(dev_priv->dev,
				dev_priv->drrs.dp->attached_connector->panel.
				fixed_mode->vrefresh);

	/*
	 * flush also means no more activity hence schedule downclock, if all
	 * other fbs are quiescent too
	 */
	if (!dev_priv->drrs.busy_frontbuffer_bits)
5623 5624 5625 5626 5627
		schedule_delayed_work(&dev_priv->drrs.work,
				msecs_to_jiffies(1000));
	mutex_unlock(&dev_priv->drrs.mutex);
}

5628 5629 5630 5631 5632 5633 5634 5635 5636 5637 5638 5639 5640 5641 5642 5643 5644 5645 5646 5647 5648 5649 5650 5651 5652 5653 5654 5655 5656 5657 5658 5659 5660 5661 5662 5663 5664 5665 5666 5667 5668 5669 5670 5671 5672 5673 5674 5675 5676 5677
/**
 * DOC: Display Refresh Rate Switching (DRRS)
 *
 * Display Refresh Rate Switching (DRRS) is a power conservation feature
 * which enables swtching between low and high refresh rates,
 * dynamically, based on the usage scenario. This feature is applicable
 * for internal panels.
 *
 * Indication that the panel supports DRRS is given by the panel EDID, which
 * would list multiple refresh rates for one resolution.
 *
 * DRRS is of 2 types - static and seamless.
 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
 * (may appear as a blink on screen) and is used in dock-undock scenario.
 * Seamless DRRS involves changing RR without any visual effect to the user
 * and can be used during normal system usage. This is done by programming
 * certain registers.
 *
 * Support for static/seamless DRRS may be indicated in the VBT based on
 * inputs from the panel spec.
 *
 * DRRS saves power by switching to low RR based on usage scenarios.
 *
 * eDP DRRS:-
 *        The implementation is based on frontbuffer tracking implementation.
 * When there is a disturbance on the screen triggered by user activity or a
 * periodic system activity, DRRS is disabled (RR is changed to high RR).
 * When there is no movement on screen, after a timeout of 1 second, a switch
 * to low RR is made.
 *        For integration with frontbuffer tracking code,
 * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
 *
 * DRRS can be further extended to support other internal panels and also
 * the scenario of video playback wherein RR is set based on the rate
 * requested by userspace.
 */

/**
 * intel_dp_drrs_init - Init basic DRRS work and mutex.
 * @intel_connector: eDP connector
 * @fixed_mode: preferred mode of panel
 *
 * This function is  called only once at driver load to initialize basic
 * DRRS stuff.
 *
 * Returns:
 * Downclock mode if panel supports it, else return NULL.
 * DRRS support is determined by the presence of downclock mode (apart
 * from VBT setting).
 */
5678
static struct drm_display_mode *
5679 5680
intel_dp_drrs_init(struct intel_connector *intel_connector,
		struct drm_display_mode *fixed_mode)
5681 5682
{
	struct drm_connector *connector = &intel_connector->base;
5683
	struct drm_device *dev = connector->dev;
5684 5685 5686
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_display_mode *downclock_mode = NULL;

5687 5688 5689
	INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
	mutex_init(&dev_priv->drrs.mutex);

5690 5691 5692 5693 5694 5695
	if (INTEL_INFO(dev)->gen <= 6) {
		DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
		return NULL;
	}

	if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5696
		DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5697 5698 5699 5700 5701 5702 5703
		return NULL;
	}

	downclock_mode = intel_find_panel_downclock
					(dev, fixed_mode, connector);

	if (!downclock_mode) {
5704
		DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5705 5706 5707
		return NULL;
	}

5708
	dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5709

5710
	dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5711
	DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5712 5713 5714
	return downclock_mode;
}

5715
static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5716
				     struct intel_connector *intel_connector)
5717 5718 5719
{
	struct drm_connector *connector = &intel_connector->base;
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5720 5721
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct drm_device *dev = intel_encoder->base.dev;
5722 5723
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_display_mode *fixed_mode = NULL;
5724
	struct drm_display_mode *downclock_mode = NULL;
5725 5726 5727
	bool has_dpcd;
	struct drm_display_mode *scan;
	struct edid *edid;
5728
	enum pipe pipe = INVALID_PIPE;
5729 5730 5731 5732

	if (!is_edp(intel_dp))
		return true;

5733 5734 5735
	pps_lock(intel_dp);
	intel_edp_panel_vdd_sanitize(intel_dp);
	pps_unlock(intel_dp);
5736

5737 5738 5739 5740 5741 5742 5743 5744 5745 5746 5747 5748 5749 5750 5751
	/* Cache DPCD and EDID for edp. */
	has_dpcd = intel_dp_get_dpcd(intel_dp);

	if (has_dpcd) {
		if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
			dev_priv->no_aux_handshake =
				intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
				DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
	} else {
		/* if this fails, presume the device is a ghost */
		DRM_INFO("failed to retrieve link info, disabling eDP\n");
		return false;
	}

	/* We now know it's not a ghost, init power sequence regs. */
5752
	pps_lock(intel_dp);
5753
	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5754
	pps_unlock(intel_dp);
5755

5756
	mutex_lock(&dev->mode_config.mutex);
5757
	edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5758 5759 5760 5761 5762 5763 5764 5765 5766 5767 5768 5769 5770 5771 5772 5773 5774 5775
	if (edid) {
		if (drm_add_edid_modes(connector, edid)) {
			drm_mode_connector_update_edid_property(connector,
								edid);
			drm_edid_to_eld(connector, edid);
		} else {
			kfree(edid);
			edid = ERR_PTR(-EINVAL);
		}
	} else {
		edid = ERR_PTR(-ENOENT);
	}
	intel_connector->edid = edid;

	/* prefer fixed mode from EDID if available */
	list_for_each_entry(scan, &connector->probed_modes, head) {
		if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
			fixed_mode = drm_mode_duplicate(dev, scan);
5776 5777
			downclock_mode = intel_dp_drrs_init(
						intel_connector, fixed_mode);
5778 5779 5780 5781 5782 5783 5784 5785 5786 5787 5788
			break;
		}
	}

	/* fallback to VBT if available for eDP */
	if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
		fixed_mode = drm_mode_duplicate(dev,
					dev_priv->vbt.lfp_lvds_vbt_mode);
		if (fixed_mode)
			fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
	}
5789
	mutex_unlock(&dev->mode_config.mutex);
5790

5791 5792 5793
	if (IS_VALLEYVIEW(dev)) {
		intel_dp->edp_notifier.notifier_call = edp_notify_handler;
		register_reboot_notifier(&intel_dp->edp_notifier);
5794 5795 5796 5797 5798 5799 5800 5801 5802 5803 5804 5805 5806 5807 5808 5809 5810 5811 5812

		/*
		 * Figure out the current pipe for the initial backlight setup.
		 * If the current pipe isn't valid, try the PPS pipe, and if that
		 * fails just assume pipe A.
		 */
		if (IS_CHERRYVIEW(dev))
			pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
		else
			pipe = PORT_TO_PIPE(intel_dp->DP);

		if (pipe != PIPE_A && pipe != PIPE_B)
			pipe = intel_dp->pps_pipe;

		if (pipe != PIPE_A && pipe != PIPE_B)
			pipe = PIPE_A;

		DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
			      pipe_name(pipe));
5813 5814
	}

5815
	intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5816
	intel_connector->panel.backlight_power = intel_edp_backlight_power;
5817
	intel_panel_setup_backlight(connector, pipe);
5818 5819 5820 5821

	return true;
}

5822
bool
5823 5824
intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
			struct intel_connector *intel_connector)
5825
{
5826 5827 5828 5829
	struct drm_connector *connector = &intel_connector->base;
	struct intel_dp *intel_dp = &intel_dig_port->dp;
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct drm_device *dev = intel_encoder->base.dev;
5830
	struct drm_i915_private *dev_priv = dev->dev_private;
5831
	enum port port = intel_dig_port->port;
5832
	int type;
5833

5834 5835
	intel_dp->pps_pipe = INVALID_PIPE;

5836
	/* intel_dp vfuncs */
5837 5838 5839
	if (INTEL_INFO(dev)->gen >= 9)
		intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
	else if (IS_VALLEYVIEW(dev))
5840 5841 5842 5843 5844 5845 5846 5847
		intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
		intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
	else if (HAS_PCH_SPLIT(dev))
		intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
	else
		intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;

5848 5849 5850 5851
	if (INTEL_INFO(dev)->gen >= 9)
		intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
	else
		intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
5852

5853 5854
	/* Preserve the current hw state. */
	intel_dp->DP = I915_READ(intel_dp->output_reg);
5855
	intel_dp->attached_connector = intel_connector;
5856

5857
	if (intel_dp_is_edp(dev, port))
5858
		type = DRM_MODE_CONNECTOR_eDP;
5859 5860
	else
		type = DRM_MODE_CONNECTOR_DisplayPort;
5861

5862 5863 5864 5865 5866 5867 5868 5869
	/*
	 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
	 * for DP the encoder type can be set by the caller to
	 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
	 */
	if (type == DRM_MODE_CONNECTOR_eDP)
		intel_encoder->type = INTEL_OUTPUT_EDP;

5870 5871 5872 5873 5874
	/* eDP only on port B and/or C on vlv/chv */
	if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
		    port != PORT_B && port != PORT_C))
		return false;

5875 5876 5877 5878
	DRM_DEBUG_KMS("Adding %s connector on port %c\n",
			type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
			port_name(port));

5879
	drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5880 5881 5882 5883 5884
	drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);

	connector->interlace_allowed = true;
	connector->doublescan_allowed = 0;

5885
	INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5886
			  edp_panel_vdd_work);
5887

5888
	intel_connector_attach_encoder(intel_connector, intel_encoder);
5889
	drm_connector_register(connector);
5890

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Paulo Zanoni 已提交
5891
	if (HAS_DDI(dev))
5892 5893 5894
		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
	else
		intel_connector->get_hw_state = intel_connector_get_hw_state;
5895
	intel_connector->unregister = intel_dp_connector_unregister;
5896

5897
	/* Set up the hotplug pin. */
5898 5899
	switch (port) {
	case PORT_A:
5900
		intel_encoder->hpd_pin = HPD_PORT_A;
5901 5902
		break;
	case PORT_B:
5903
		intel_encoder->hpd_pin = HPD_PORT_B;
5904 5905
		if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0))
			intel_encoder->hpd_pin = HPD_PORT_A;
5906 5907
		break;
	case PORT_C:
5908
		intel_encoder->hpd_pin = HPD_PORT_C;
5909 5910
		break;
	case PORT_D:
5911
		intel_encoder->hpd_pin = HPD_PORT_D;
5912 5913
		break;
	default:
5914
		BUG();
5915 5916
	}

5917
	if (is_edp(intel_dp)) {
5918
		pps_lock(intel_dp);
5919 5920
		intel_dp_init_panel_power_timestamps(intel_dp);
		if (IS_VALLEYVIEW(dev))
5921
			vlv_initial_power_sequencer_setup(intel_dp);
5922
		else
5923
			intel_dp_init_panel_power_sequencer(dev, intel_dp);
5924
		pps_unlock(intel_dp);
5925
	}
5926

5927
	intel_dp_aux_init(intel_dp, intel_connector);
5928

5929
	/* init MST on ports that can support it */
5930 5931 5932 5933
	if (HAS_DP_MST(dev) &&
	    (port == PORT_B || port == PORT_C || port == PORT_D))
		intel_dp_mst_encoder_init(intel_dig_port,
					  intel_connector->base.base.id);
5934

5935
	if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5936
		drm_dp_aux_unregister(&intel_dp->aux);
5937 5938
		if (is_edp(intel_dp)) {
			cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5939 5940 5941 5942
			/*
			 * vdd might still be enabled do to the delayed vdd off.
			 * Make sure vdd is actually turned off here.
			 */
5943
			pps_lock(intel_dp);
5944
			edp_panel_vdd_off_sync(intel_dp);
5945
			pps_unlock(intel_dp);
5946
		}
5947
		drm_connector_unregister(connector);
5948
		drm_connector_cleanup(connector);
5949
		return false;
5950
	}
5951

5952 5953
	intel_dp_add_properties(intel_dp, connector);

5954 5955 5956 5957 5958 5959 5960 5961
	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
	 * 0xd.  Failure to do so will result in spurious interrupts being
	 * generated on the port when a cable is not attached.
	 */
	if (IS_G4X(dev) && !IS_GM45(dev)) {
		u32 temp = I915_READ(PEG_BAND_GAP_DATA);
		I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
	}
5962

5963 5964
	i915_debugfs_connector_add(connector);

5965
	return true;
5966
}
5967 5968 5969 5970

void
intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
{
5971
	struct drm_i915_private *dev_priv = dev->dev_private;
5972 5973 5974 5975 5976
	struct intel_digital_port *intel_dig_port;
	struct intel_encoder *intel_encoder;
	struct drm_encoder *encoder;
	struct intel_connector *intel_connector;

5977
	intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
5978 5979 5980
	if (!intel_dig_port)
		return;

5981
	intel_connector = intel_connector_alloc();
5982 5983 5984 5985 5986 5987 5988 5989 5990 5991 5992
	if (!intel_connector) {
		kfree(intel_dig_port);
		return;
	}

	intel_encoder = &intel_dig_port->base;
	encoder = &intel_encoder->base;

	drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
			 DRM_MODE_ENCODER_TMDS);

5993
	intel_encoder->compute_config = intel_dp_compute_config;
P
Paulo Zanoni 已提交
5994 5995
	intel_encoder->disable = intel_disable_dp;
	intel_encoder->get_hw_state = intel_dp_get_hw_state;
5996
	intel_encoder->get_config = intel_dp_get_config;
5997
	intel_encoder->suspend = intel_dp_encoder_suspend;
5998
	if (IS_CHERRYVIEW(dev)) {
5999
		intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
6000 6001
		intel_encoder->pre_enable = chv_pre_enable_dp;
		intel_encoder->enable = vlv_enable_dp;
6002
		intel_encoder->post_disable = chv_post_disable_dp;
6003
	} else if (IS_VALLEYVIEW(dev)) {
6004
		intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
6005 6006
		intel_encoder->pre_enable = vlv_pre_enable_dp;
		intel_encoder->enable = vlv_enable_dp;
6007
		intel_encoder->post_disable = vlv_post_disable_dp;
6008
	} else {
6009 6010
		intel_encoder->pre_enable = g4x_pre_enable_dp;
		intel_encoder->enable = g4x_enable_dp;
6011 6012
		if (INTEL_INFO(dev)->gen >= 5)
			intel_encoder->post_disable = ilk_post_disable_dp;
6013
	}
6014

6015
	intel_dig_port->port = port;
6016 6017
	intel_dig_port->dp.output_reg = output_reg;

P
Paulo Zanoni 已提交
6018
	intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
6019 6020 6021 6022 6023 6024 6025 6026
	if (IS_CHERRYVIEW(dev)) {
		if (port == PORT_D)
			intel_encoder->crtc_mask = 1 << 2;
		else
			intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
	} else {
		intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
	}
6027
	intel_encoder->cloneable = 0;
6028

6029
	intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6030
	dev_priv->hotplug.irq_port[port] = intel_dig_port;
6031

6032 6033 6034
	if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
		drm_encoder_cleanup(encoder);
		kfree(intel_dig_port);
6035
		kfree(intel_connector);
6036
	}
6037
}
6038 6039 6040 6041 6042 6043 6044 6045

void intel_dp_mst_suspend(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;

	/* disable MST */
	for (i = 0; i < I915_MAX_PORTS; i++) {
6046
		struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6047 6048 6049 6050 6051 6052 6053 6054 6055 6056 6057 6058 6059 6060 6061 6062 6063 6064
		if (!intel_dig_port)
			continue;

		if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
			if (!intel_dig_port->dp.can_mst)
				continue;
			if (intel_dig_port->dp.is_mst)
				drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
		}
	}
}

void intel_dp_mst_resume(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;

	for (i = 0; i < I915_MAX_PORTS; i++) {
6065
		struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6066 6067 6068 6069 6070 6071 6072 6073 6074 6075 6076 6077 6078 6079 6080
		if (!intel_dig_port)
			continue;
		if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
			int ret;

			if (!intel_dig_port->dp.can_mst)
				continue;

			ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
			if (ret != 0) {
				intel_dp_check_mst_status(&intel_dig_port->dp);
			}
		}
	}
}