intel_dp.c 174.4 KB
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/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Keith Packard <keithp@keithp.com>
 *
 */

#include <linux/i2c.h>
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#include <linux/slab.h>
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#include <linux/export.h>
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#include <linux/notifier.h>
#include <linux/reboot.h>
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#include <drm/drmP.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_edid.h>
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#include "intel_drv.h"
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#include <drm/i915_drm.h>
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#include "i915_drv.h"

#define DP_LINK_CHECK_TIMEOUT	(10 * 1000)

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/* Compliance test status bits  */
#define INTEL_DP_RESOLUTION_SHIFT_MASK	0
#define INTEL_DP_RESOLUTION_PREFERRED	(1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
#define INTEL_DP_RESOLUTION_STANDARD	(2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
#define INTEL_DP_RESOLUTION_FAILSAFE	(3 << INTEL_DP_RESOLUTION_SHIFT_MASK)

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struct dp_link_dpll {
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	int clock;
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	struct dpll dpll;
};

static const struct dp_link_dpll gen4_dpll[] = {
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	{ 162000,
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		{ .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
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	{ 270000,
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		{ .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
};

static const struct dp_link_dpll pch_dpll[] = {
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	{ 162000,
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		{ .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
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	{ 270000,
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		{ .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
};

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static const struct dp_link_dpll vlv_dpll[] = {
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	{ 162000,
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		{ .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
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	{ 270000,
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		{ .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
};

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/*
 * CHV supports eDP 1.4 that have  more link rates.
 * Below only provides the fixed rate but exclude variable rate.
 */
static const struct dp_link_dpll chv_dpll[] = {
	/*
	 * CHV requires to program fractional division for m2.
	 * m2 is stored in fixed point format using formula below
	 * (m2_int << 22) | m2_fraction
	 */
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	{ 162000,	/* m2_int = 32, m2_fraction = 1677722 */
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		{ .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
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	{ 270000,	/* m2_int = 27, m2_fraction = 0 */
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		{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
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	{ 540000,	/* m2_int = 27, m2_fraction = 0 */
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		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
};
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static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
				  324000, 432000, 540000 };
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static const int skl_rates[] = { 162000, 216000, 270000,
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				  324000, 432000, 540000 };
static const int default_rates[] = { 162000, 270000, 540000 };
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/**
 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 * @intel_dp: DP struct
 *
 * If a CPU or PCH DP output is attached to an eDP panel, this function
 * will return true, and false otherwise.
 */
static bool is_edp(struct intel_dp *intel_dp)
{
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	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
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}

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static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
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{
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	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	return intel_dig_port->base.base.dev;
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}

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static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
{
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	return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
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}

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static void intel_dp_link_down(struct intel_dp *intel_dp);
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static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
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static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
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static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
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static void vlv_steal_power_sequencer(struct drm_device *dev,
				      enum pipe pipe);
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static unsigned int intel_dp_unused_lane_mask(int lane_count)
{
	return ~((1 << lane_count) - 1) & 0xf;
}

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static int
intel_dp_max_link_bw(struct intel_dp  *intel_dp)
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{
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	int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
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	switch (max_link_bw) {
	case DP_LINK_BW_1_62:
	case DP_LINK_BW_2_7:
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	case DP_LINK_BW_5_4:
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		break;
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	default:
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		WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
		     max_link_bw);
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		max_link_bw = DP_LINK_BW_1_62;
		break;
	}
	return max_link_bw;
}

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static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	u8 source_max, sink_max;

	source_max = 4;
	if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
	    (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
		source_max = 2;

	sink_max = drm_dp_max_lane_count(intel_dp->dpcd);

	return min(source_max, sink_max);
}

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/*
 * The units on the numbers in the next two are... bizarre.  Examples will
 * make it clearer; this one parallels an example in the eDP spec.
 *
 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 *
 *     270000 * 1 * 8 / 10 == 216000
 *
 * The actual data capacity of that configuration is 2.16Gbit/s, so the
 * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 * 119000.  At 18bpp that's 2142000 kilobits per second.
 *
 * Thus the strange-looking division by 10 in intel_dp_link_required, to
 * get the result in decakilobits instead of kilobits.
 */

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static int
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intel_dp_link_required(int pixel_clock, int bpp)
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{
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	return (pixel_clock * bpp + 9) / 10;
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}

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static int
intel_dp_max_data_rate(int max_link_clock, int max_lanes)
{
	return (max_link_clock * max_lanes * 8) / 10;
}

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static enum drm_mode_status
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intel_dp_mode_valid(struct drm_connector *connector,
		    struct drm_display_mode *mode)
{
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	struct intel_dp *intel_dp = intel_attached_dp(connector);
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	struct intel_connector *intel_connector = to_intel_connector(connector);
	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
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	int target_clock = mode->clock;
	int max_rate, mode_rate, max_lanes, max_link_clock;
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	if (is_edp(intel_dp) && fixed_mode) {
		if (mode->hdisplay > fixed_mode->hdisplay)
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			return MODE_PANEL;

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		if (mode->vdisplay > fixed_mode->vdisplay)
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			return MODE_PANEL;
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		target_clock = fixed_mode->clock;
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	}

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	max_link_clock = intel_dp_max_link_rate(intel_dp);
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	max_lanes = intel_dp_max_lane_count(intel_dp);
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	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
	mode_rate = intel_dp_link_required(target_clock, 18);

	if (mode_rate > max_rate)
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		return MODE_CLOCK_HIGH;
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	if (mode->clock < 10000)
		return MODE_CLOCK_LOW;

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	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
		return MODE_H_ILLEGAL;

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	return MODE_OK;
}

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uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
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{
	int	i;
	uint32_t v = 0;

	if (src_bytes > 4)
		src_bytes = 4;
	for (i = 0; i < src_bytes; i++)
		v |= ((uint32_t) src[i]) << ((3-i) * 8);
	return v;
}

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static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
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{
	int i;
	if (dst_bytes > 4)
		dst_bytes = 4;
	for (i = 0; i < dst_bytes; i++)
		dst[i] = src >> ((3-i) * 8);
}

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static void
intel_dp_init_panel_power_sequencer(struct drm_device *dev,
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				    struct intel_dp *intel_dp);
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static void
intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
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					      struct intel_dp *intel_dp);
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static void pps_lock(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *encoder = &intel_dig_port->base;
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum intel_display_power_domain power_domain;

	/*
	 * See vlv_power_sequencer_reset() why we need
	 * a power domain reference here.
	 */
	power_domain = intel_display_port_power_domain(encoder);
	intel_display_power_get(dev_priv, power_domain);

	mutex_lock(&dev_priv->pps_mutex);
}

static void pps_unlock(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *encoder = &intel_dig_port->base;
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum intel_display_power_domain power_domain;

	mutex_unlock(&dev_priv->pps_mutex);

	power_domain = intel_display_port_power_domain(encoder);
	intel_display_power_put(dev_priv, power_domain);
}

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static void
vlv_power_sequencer_kick(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum pipe pipe = intel_dp->pps_pipe;
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	bool pll_enabled, release_cl_override = false;
	enum dpio_phy phy = DPIO_PHY(pipe);
	enum dpio_channel ch = vlv_pipe_to_channel(pipe);
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	uint32_t DP;

	if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
		 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
		 pipe_name(pipe), port_name(intel_dig_port->port)))
		return;

	DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
		      pipe_name(pipe), port_name(intel_dig_port->port));

	/* Preserve the BIOS-computed detected bit. This is
	 * supposed to be read-only.
	 */
	DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
	DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
	DP |= DP_PORT_WIDTH(1);
	DP |= DP_LINK_TRAIN_PAT_1;

	if (IS_CHERRYVIEW(dev))
		DP |= DP_PIPE_SELECT_CHV(pipe);
	else if (pipe == PIPE_B)
		DP |= DP_PIPEB_SELECT;

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	pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;

	/*
	 * The DPLL for the pipe must be enabled for this to work.
	 * So enable temporarily it if it's not already enabled.
	 */
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	if (!pll_enabled) {
		release_cl_override = IS_CHERRYVIEW(dev) &&
			!chv_phy_powergate_ch(dev_priv, phy, ch, true);

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		vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
				 &chv_dpll[0].dpll : &vlv_dpll[0].dpll);
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	}
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	/*
	 * Similar magic as in intel_dp_enable_port().
	 * We _must_ do this port enable + disable trick
	 * to make this power seqeuencer lock onto the port.
	 * Otherwise even VDD force bit won't work.
	 */
	I915_WRITE(intel_dp->output_reg, DP);
	POSTING_READ(intel_dp->output_reg);

	I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
	POSTING_READ(intel_dp->output_reg);

	I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
	POSTING_READ(intel_dp->output_reg);
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	if (!pll_enabled) {
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		vlv_force_pll_off(dev, pipe);
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		if (release_cl_override)
			chv_phy_powergate_ch(dev_priv, phy, ch, false);
	}
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}

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static enum pipe
vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct intel_encoder *encoder;
	unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
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	enum pipe pipe;
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	lockdep_assert_held(&dev_priv->pps_mutex);
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	/* We should never land here with regular DP ports */
	WARN_ON(!is_edp(intel_dp));

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	if (intel_dp->pps_pipe != INVALID_PIPE)
		return intel_dp->pps_pipe;

	/*
	 * We don't have power sequencer currently.
	 * Pick one that's not used by other ports.
	 */
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		struct intel_dp *tmp;

		if (encoder->type != INTEL_OUTPUT_EDP)
			continue;

		tmp = enc_to_intel_dp(&encoder->base);

		if (tmp->pps_pipe != INVALID_PIPE)
			pipes &= ~(1 << tmp->pps_pipe);
	}

	/*
	 * Didn't find one. This should not happen since there
	 * are two power sequencers and up to two eDP ports.
	 */
	if (WARN_ON(pipes == 0))
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		pipe = PIPE_A;
	else
		pipe = ffs(pipes) - 1;
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	vlv_steal_power_sequencer(dev, pipe);
	intel_dp->pps_pipe = pipe;
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	DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
		      pipe_name(intel_dp->pps_pipe),
		      port_name(intel_dig_port->port));

	/* init power sequencer on this pipe and port */
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	intel_dp_init_panel_power_sequencer(dev, intel_dp);
	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
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	/*
	 * Even vdd force doesn't work until we've made
	 * the power sequencer lock in on the port.
	 */
	vlv_power_sequencer_kick(intel_dp);
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	return intel_dp->pps_pipe;
}

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typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
			       enum pipe pipe);

static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
			       enum pipe pipe)
{
	return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
}

static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
				enum pipe pipe)
{
	return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
}

static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
			 enum pipe pipe)
{
	return true;
}
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static enum pipe
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vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
		     enum port port,
		     vlv_pipe_check pipe_check)
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{
	enum pipe pipe;
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	for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
		u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
			PANEL_PORT_SELECT_MASK;
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		if (port_sel != PANEL_PORT_SELECT_VLV(port))
			continue;

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		if (!pipe_check(dev_priv, pipe))
			continue;

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		return pipe;
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	}

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	return INVALID_PIPE;
}

static void
vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = intel_dig_port->port;

	lockdep_assert_held(&dev_priv->pps_mutex);

	/* try to find a pipe with this port selected */
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	/* first pick one where the panel is on */
	intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
						  vlv_pipe_has_pp_on);
	/* didn't find one? pick one where vdd is on */
	if (intel_dp->pps_pipe == INVALID_PIPE)
		intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
							  vlv_pipe_has_vdd_on);
	/* didn't find one? pick one with just the correct port */
	if (intel_dp->pps_pipe == INVALID_PIPE)
		intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
							  vlv_pipe_any);
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	/* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
	if (intel_dp->pps_pipe == INVALID_PIPE) {
		DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
			      port_name(port));
		return;
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	}

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	DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
		      port_name(port), pipe_name(intel_dp->pps_pipe));

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	intel_dp_init_panel_power_sequencer(dev, intel_dp);
	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
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}

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void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
{
	struct drm_device *dev = dev_priv->dev;
	struct intel_encoder *encoder;

	if (WARN_ON(!IS_VALLEYVIEW(dev)))
		return;

	/*
	 * We can't grab pps_mutex here due to deadlock with power_domain
	 * mutex when power_domain functions are called while holding pps_mutex.
	 * That also means that in order to use pps_pipe the code needs to
	 * hold both a power domain reference and pps_mutex, and the power domain
	 * reference get/put must be done while _not_ holding pps_mutex.
	 * pps_{lock,unlock}() do these steps in the correct order, so one
	 * should use them always.
	 */

	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		struct intel_dp *intel_dp;

		if (encoder->type != INTEL_OUTPUT_EDP)
			continue;

		intel_dp = enc_to_intel_dp(&encoder->base);
		intel_dp->pps_pipe = INVALID_PIPE;
	}
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}

static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);

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	if (IS_BROXTON(dev))
		return BXT_PP_CONTROL(0);
	else if (HAS_PCH_SPLIT(dev))
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		return PCH_PP_CONTROL;
	else
		return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
}

static u32 _pp_stat_reg(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);

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	if (IS_BROXTON(dev))
		return BXT_PP_STATUS(0);
	else if (HAS_PCH_SPLIT(dev))
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		return PCH_PP_STATUS;
	else
		return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
}

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/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
   This function only applicable when panel PM state is not to be tracked */
static int edp_notify_handler(struct notifier_block *this, unsigned long code,
			      void *unused)
{
	struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
						 edp_notifier);
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp_div;
	u32 pp_ctrl_reg, pp_div_reg;

	if (!is_edp(intel_dp) || code != SYS_RESTART)
		return 0;

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	pps_lock(intel_dp);
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	if (IS_VALLEYVIEW(dev)) {
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		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);

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		pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
		pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
		pp_div = I915_READ(pp_div_reg);
		pp_div &= PP_REFERENCE_DIVIDER_MASK;

		/* 0x1F write to PP_DIV_REG sets max cycle delay */
		I915_WRITE(pp_div_reg, pp_div | 0x1F);
		I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
		msleep(intel_dp->panel_power_cycle_delay);
	}

599
	pps_unlock(intel_dp);
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600

601 602 603
	return 0;
}

604
static bool edp_have_panel_power(struct intel_dp *intel_dp)
605
{
606
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
607 608
	struct drm_i915_private *dev_priv = dev->dev_private;

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609 610
	lockdep_assert_held(&dev_priv->pps_mutex);

611 612 613 614
	if (IS_VALLEYVIEW(dev) &&
	    intel_dp->pps_pipe == INVALID_PIPE)
		return false;

615
	return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
616 617
}

618
static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
619
{
620
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
621 622
	struct drm_i915_private *dev_priv = dev->dev_private;

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623 624
	lockdep_assert_held(&dev_priv->pps_mutex);

625 626 627 628
	if (IS_VALLEYVIEW(dev) &&
	    intel_dp->pps_pipe == INVALID_PIPE)
		return false;

629
	return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
630 631
}

632 633 634
static void
intel_dp_check_edp(struct intel_dp *intel_dp)
{
635
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
636
	struct drm_i915_private *dev_priv = dev->dev_private;
637

638 639
	if (!is_edp(intel_dp))
		return;
640

641
	if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
642 643
		WARN(1, "eDP powered off while attempting aux channel communication.\n");
		DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
644 645
			      I915_READ(_pp_stat_reg(intel_dp)),
			      I915_READ(_pp_ctrl_reg(intel_dp)));
646 647 648
	}
}

649 650 651 652 653 654
static uint32_t
intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
655
	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
656 657 658
	uint32_t status;
	bool done;

659
#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
660
	if (has_aux_irq)
661
		done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
662
					  msecs_to_jiffies_timeout(10));
663 664 665 666 667 668 669 670 671 672
	else
		done = wait_for_atomic(C, 10) == 0;
	if (!done)
		DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
			  has_aux_irq);
#undef C

	return status;
}

673
static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
674
{
675 676
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
677

678 679 680
	/*
	 * The clock divider is based off the hrawclk, and would like to run at
	 * 2MHz.  So, take the hrawclk value and divide by 2 and use that
681
	 */
682 683 684 685 686 687 688
	return index ? 0 : intel_hrawclk(dev) / 2;
}

static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
689
	struct drm_i915_private *dev_priv = dev->dev_private;
690 691 692 693 694

	if (index)
		return 0;

	if (intel_dig_port->port == PORT_A) {
695 696
		return DIV_ROUND_UP(dev_priv->cdclk_freq, 2000);

697 698 699 700 701 702 703 704 705 706 707 708 709 710
	} else {
		return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
	}
}

static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (intel_dig_port->port == PORT_A) {
		if (index)
			return 0;
711
		return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
712 713
	} else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
		/* Workaround for non-ULT HSW */
714 715 716 717 718
		switch (index) {
		case 0: return 63;
		case 1: return 72;
		default: return 0;
		}
719
	} else  {
720
		return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
721
	}
722 723
}

724 725 726 727 728
static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
	return index ? 0 : 100;
}

729 730 731 732 733 734 735 736 737 738
static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
	/*
	 * SKL doesn't need us to program the AUX clock divider (Hardware will
	 * derive the clock from CDCLK automatically). We still implement the
	 * get_aux_clock_divider vfunc to plug-in into the existing code.
	 */
	return index ? 0 : 1;
}

739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758
static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
				      bool has_aux_irq,
				      int send_bytes,
				      uint32_t aux_clock_divider)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	uint32_t precharge, timeout;

	if (IS_GEN6(dev))
		precharge = 3;
	else
		precharge = 5;

	if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
		timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
	else
		timeout = DP_AUX_CH_CTL_TIME_OUT_400us;

	return DP_AUX_CH_CTL_SEND_BUSY |
759
	       DP_AUX_CH_CTL_DONE |
760
	       (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
761
	       DP_AUX_CH_CTL_TIME_OUT_ERROR |
762
	       timeout |
763
	       DP_AUX_CH_CTL_RECEIVE_ERROR |
764 765
	       (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
	       (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
766
	       (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
767 768
}

769 770 771 772 773 774 775 776 777 778 779 780 781 782 783
static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
				      bool has_aux_irq,
				      int send_bytes,
				      uint32_t unused)
{
	return DP_AUX_CH_CTL_SEND_BUSY |
	       DP_AUX_CH_CTL_DONE |
	       (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
	       DP_AUX_CH_CTL_TIME_OUT_ERROR |
	       DP_AUX_CH_CTL_TIME_OUT_1600us |
	       DP_AUX_CH_CTL_RECEIVE_ERROR |
	       (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
	       DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
}

784 785
static int
intel_dp_aux_ch(struct intel_dp *intel_dp,
786
		const uint8_t *send, int send_bytes,
787 788 789 790 791 792 793
		uint8_t *recv, int recv_size)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
	uint32_t ch_data = ch_ctl + 4;
794
	uint32_t aux_clock_divider;
795 796
	int i, ret, recv_bytes;
	uint32_t status;
797
	int try, clock = 0;
798
	bool has_aux_irq = HAS_AUX_IRQ(dev);
799 800
	bool vdd;

801
	pps_lock(intel_dp);
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802

803 804 805 806 807 808
	/*
	 * We will be called with VDD already enabled for dpcd/edid/oui reads.
	 * In such cases we want to leave VDD enabled and it's up to upper layers
	 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
	 * ourselves.
	 */
809
	vdd = edp_panel_vdd_on(intel_dp);
810 811 812 813 814 815 816 817

	/* dp aux is extremely sensitive to irq latency, hence request the
	 * lowest possible wakeup latency and so prevent the cpu from going into
	 * deep sleep states.
	 */
	pm_qos_update_request(&dev_priv->pm_qos, 0);

	intel_dp_check_edp(intel_dp);
818

819 820
	intel_aux_display_runtime_get(dev_priv);

821 822
	/* Try to wait for any previous AUX channel activity */
	for (try = 0; try < 3; try++) {
823
		status = I915_READ_NOTRACE(ch_ctl);
824 825 826 827 828 829
		if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
			break;
		msleep(1);
	}

	if (try == 3) {
830 831 832 833 834 835 836 837 838
		static u32 last_status = -1;
		const u32 status = I915_READ(ch_ctl);

		if (status != last_status) {
			WARN(1, "dp_aux_ch not started status 0x%08x\n",
			     status);
			last_status = status;
		}

839 840
		ret = -EBUSY;
		goto out;
841 842
	}

843 844 845 846 847 848
	/* Only 5 data registers! */
	if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
		ret = -E2BIG;
		goto out;
	}

849
	while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
850 851 852 853
		u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
							  has_aux_irq,
							  send_bytes,
							  aux_clock_divider);
854

855 856 857 858 859
		/* Must try at least 3 times according to DP spec */
		for (try = 0; try < 5; try++) {
			/* Load the send data into the aux channel data registers */
			for (i = 0; i < send_bytes; i += 4)
				I915_WRITE(ch_data + i,
860 861
					   intel_dp_pack_aux(send + i,
							     send_bytes - i));
862 863

			/* Send the command and wait for it to complete */
864
			I915_WRITE(ch_ctl, send_ctl);
865 866 867 868 869 870 871 872 873 874

			status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);

			/* Clear done status and any errors */
			I915_WRITE(ch_ctl,
				   status |
				   DP_AUX_CH_CTL_DONE |
				   DP_AUX_CH_CTL_TIME_OUT_ERROR |
				   DP_AUX_CH_CTL_RECEIVE_ERROR);

875
			if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
876
				continue;
877 878 879 880 881 882 883 884

			/* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
			 *   400us delay required for errors and timeouts
			 *   Timeout errors from the HW already meet this
			 *   requirement so skip to next iteration
			 */
			if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
				usleep_range(400, 500);
885
				continue;
886
			}
887
			if (status & DP_AUX_CH_CTL_DONE)
888
				goto done;
889
		}
890 891 892
	}

	if ((status & DP_AUX_CH_CTL_DONE) == 0) {
893
		DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
894 895
		ret = -EBUSY;
		goto out;
896 897
	}

898
done:
899 900 901
	/* Check for timeout or receive error.
	 * Timeouts occur when the sink is not connected
	 */
902
	if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
903
		DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
904 905
		ret = -EIO;
		goto out;
906
	}
907 908 909

	/* Timeouts occur when the device isn't connected, so they're
	 * "normal" -- don't fill the kernel log with these */
910
	if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
911
		DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
912 913
		ret = -ETIMEDOUT;
		goto out;
914 915 916 917 918 919 920
	}

	/* Unload any bytes sent back from the other side */
	recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
		      DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
	if (recv_bytes > recv_size)
		recv_bytes = recv_size;
921

922
	for (i = 0; i < recv_bytes; i += 4)
923 924
		intel_dp_unpack_aux(I915_READ(ch_data + i),
				    recv + i, recv_bytes - i);
925

926 927 928
	ret = recv_bytes;
out:
	pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
929
	intel_aux_display_runtime_put(dev_priv);
930

931 932 933
	if (vdd)
		edp_panel_vdd_off(intel_dp, false);

934
	pps_unlock(intel_dp);
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935

936
	return ret;
937 938
}

939 940
#define BARE_ADDRESS_SIZE	3
#define HEADER_SIZE		(BARE_ADDRESS_SIZE + 1)
941 942
static ssize_t
intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
943
{
944 945 946
	struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
	uint8_t txbuf[20], rxbuf[20];
	size_t txsize, rxsize;
947 948
	int ret;

949 950 951
	txbuf[0] = (msg->request << 4) |
		((msg->address >> 16) & 0xf);
	txbuf[1] = (msg->address >> 8) & 0xff;
952 953
	txbuf[2] = msg->address & 0xff;
	txbuf[3] = msg->size - 1;
954

955 956 957
	switch (msg->request & ~DP_AUX_I2C_MOT) {
	case DP_AUX_NATIVE_WRITE:
	case DP_AUX_I2C_WRITE:
958
	case DP_AUX_I2C_WRITE_STATUS_UPDATE:
959
		txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
960
		rxsize = 2; /* 0 or 1 data bytes */
961

962 963
		if (WARN_ON(txsize > 20))
			return -E2BIG;
964

965
		memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
966

967 968 969
		ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
		if (ret > 0) {
			msg->reply = rxbuf[0] >> 4;
970

971 972 973 974 975 976 977
			if (ret > 1) {
				/* Number of bytes written in a short write. */
				ret = clamp_t(int, rxbuf[1], 0, msg->size);
			} else {
				/* Return payload size. */
				ret = msg->size;
			}
978 979
		}
		break;
980

981 982
	case DP_AUX_NATIVE_READ:
	case DP_AUX_I2C_READ:
983
		txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
984
		rxsize = msg->size + 1;
985

986 987
		if (WARN_ON(rxsize > 20))
			return -E2BIG;
988

989 990 991 992 993 994 995 996 997 998 999
		ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
		if (ret > 0) {
			msg->reply = rxbuf[0] >> 4;
			/*
			 * Assume happy day, and copy the data. The caller is
			 * expected to check msg->reply before touching it.
			 *
			 * Return payload size.
			 */
			ret--;
			memcpy(msg->buffer, rxbuf + 1, ret);
1000
		}
1001 1002 1003 1004 1005
		break;

	default:
		ret = -EINVAL;
		break;
1006
	}
1007

1008
	return ret;
1009 1010
}

1011 1012 1013 1014
static void
intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1015
	struct drm_i915_private *dev_priv = dev->dev_private;
1016 1017
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	enum port port = intel_dig_port->port;
1018
	struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port];
1019
	const char *name = NULL;
1020
	uint32_t porte_aux_ctl_reg = DPA_AUX_CH_CTL;
1021 1022
	int ret;

1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042
	/* On SKL we don't have Aux for port E so we rely on VBT to set
	 * a proper alternate aux channel.
	 */
	if (IS_SKYLAKE(dev) && port == PORT_E) {
		switch (info->alternate_aux_channel) {
		case DP_AUX_B:
			porte_aux_ctl_reg = DPB_AUX_CH_CTL;
			break;
		case DP_AUX_C:
			porte_aux_ctl_reg = DPC_AUX_CH_CTL;
			break;
		case DP_AUX_D:
			porte_aux_ctl_reg = DPD_AUX_CH_CTL;
			break;
		case DP_AUX_A:
		default:
			porte_aux_ctl_reg = DPA_AUX_CH_CTL;
		}
	}

1043 1044 1045
	switch (port) {
	case PORT_A:
		intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
1046
		name = "DPDDC-A";
1047
		break;
1048 1049
	case PORT_B:
		intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
1050
		name = "DPDDC-B";
1051
		break;
1052 1053
	case PORT_C:
		intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
1054
		name = "DPDDC-C";
1055
		break;
1056 1057
	case PORT_D:
		intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
1058
		name = "DPDDC-D";
1059
		break;
1060 1061 1062 1063
	case PORT_E:
		intel_dp->aux_ch_ctl_reg = porte_aux_ctl_reg;
		name = "DPDDC-E";
		break;
1064 1065
	default:
		BUG();
1066 1067
	}

1068 1069 1070 1071 1072 1073 1074 1075 1076
	/*
	 * The AUX_CTL register is usually DP_CTL + 0x10.
	 *
	 * On Haswell and Broadwell though:
	 *   - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
	 *   - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
	 *
	 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
	 */
1077
	if (!IS_HASWELL(dev) && !IS_BROADWELL(dev) && port != PORT_E)
1078
		intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
1079

1080
	intel_dp->aux.name = name;
1081 1082
	intel_dp->aux.dev = dev->dev;
	intel_dp->aux.transfer = intel_dp_aux_transfer;
1083

1084 1085
	DRM_DEBUG_KMS("registering %s bus for %s\n", name,
		      connector->base.kdev->kobj.name);
1086

1087
	ret = drm_dp_aux_register(&intel_dp->aux);
1088
	if (ret < 0) {
1089
		DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1090 1091
			  name, ret);
		return;
1092
	}
1093

1094 1095 1096 1097 1098
	ret = sysfs_create_link(&connector->base.kdev->kobj,
				&intel_dp->aux.ddc.dev.kobj,
				intel_dp->aux.ddc.dev.kobj.name);
	if (ret < 0) {
		DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
1099
		drm_dp_aux_unregister(&intel_dp->aux);
1100
	}
1101 1102
}

1103 1104 1105 1106 1107
static void
intel_dp_connector_unregister(struct intel_connector *intel_connector)
{
	struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);

1108 1109 1110
	if (!intel_connector->mst_port)
		sysfs_remove_link(&intel_connector->base.kdev->kobj,
				  intel_dp->aux.ddc.dev.kobj.name);
1111 1112 1113
	intel_connector_unregister(intel_connector);
}

1114
static void
1115
skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
1116 1117 1118
{
	u32 ctrl1;

1119 1120 1121
	memset(&pipe_config->dpll_hw_state, 0,
	       sizeof(pipe_config->dpll_hw_state));

1122 1123 1124 1125 1126
	pipe_config->ddi_pll_sel = SKL_DPLL0;
	pipe_config->dpll_hw_state.cfgcr1 = 0;
	pipe_config->dpll_hw_state.cfgcr2 = 0;

	ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
1127
	switch (pipe_config->port_clock / 2) {
1128
	case 81000:
1129
		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
1130 1131
					      SKL_DPLL0);
		break;
1132
	case 135000:
1133
		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350,
1134 1135
					      SKL_DPLL0);
		break;
1136
	case 270000:
1137
		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700,
1138 1139
					      SKL_DPLL0);
		break;
1140
	case 162000:
1141
		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620,
1142 1143 1144 1145 1146 1147
					      SKL_DPLL0);
		break;
	/* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
	results in CDCLK change. Need to handle the change of CDCLK by
	disabling pipes and re-enabling them */
	case 108000:
1148
		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
1149 1150 1151
					      SKL_DPLL0);
		break;
	case 216000:
1152
		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
1153 1154 1155
					      SKL_DPLL0);
		break;

1156 1157 1158 1159
	}
	pipe_config->dpll_hw_state.ctrl1 = ctrl1;
}

1160
void
1161
hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config)
1162
{
1163 1164 1165
	memset(&pipe_config->dpll_hw_state, 0,
	       sizeof(pipe_config->dpll_hw_state));

1166 1167
	switch (pipe_config->port_clock / 2) {
	case 81000:
1168 1169
		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
		break;
1170
	case 135000:
1171 1172
		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
		break;
1173
	case 270000:
1174 1175 1176 1177 1178
		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
		break;
	}
}

1179
static int
1180
intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
1181
{
1182 1183 1184
	if (intel_dp->num_sink_rates) {
		*sink_rates = intel_dp->sink_rates;
		return intel_dp->num_sink_rates;
1185
	}
1186 1187 1188 1189

	*sink_rates = default_rates;

	return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
1190 1191
}

1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204
static bool intel_dp_source_supports_hbr2(struct drm_device *dev)
{
	/* WaDisableHBR2:skl */
	if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
		return false;

	if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
	    (INTEL_INFO(dev)->gen >= 9))
		return true;
	else
		return false;
}

1205
static int
1206
intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
1207
{
1208 1209
	int size;

1210 1211
	if (IS_BROXTON(dev)) {
		*source_rates = bxt_rates;
1212
		size = ARRAY_SIZE(bxt_rates);
1213
	} else if (IS_SKYLAKE(dev)) {
1214
		*source_rates = skl_rates;
1215 1216 1217 1218
		size = ARRAY_SIZE(skl_rates);
	} else {
		*source_rates = default_rates;
		size = ARRAY_SIZE(default_rates);
1219
	}
1220

1221
	/* This depends on the fact that 5.4 is last value in the array */
1222 1223
	if (!intel_dp_source_supports_hbr2(dev))
		size--;
1224

1225
	return size;
1226 1227
}

1228 1229
static void
intel_dp_set_clock(struct intel_encoder *encoder,
1230
		   struct intel_crtc_state *pipe_config)
1231 1232
{
	struct drm_device *dev = encoder->base.dev;
1233 1234
	const struct dp_link_dpll *divisor = NULL;
	int i, count = 0;
1235 1236

	if (IS_G4X(dev)) {
1237 1238
		divisor = gen4_dpll;
		count = ARRAY_SIZE(gen4_dpll);
1239
	} else if (HAS_PCH_SPLIT(dev)) {
1240 1241
		divisor = pch_dpll;
		count = ARRAY_SIZE(pch_dpll);
1242 1243 1244
	} else if (IS_CHERRYVIEW(dev)) {
		divisor = chv_dpll;
		count = ARRAY_SIZE(chv_dpll);
1245
	} else if (IS_VALLEYVIEW(dev)) {
1246 1247
		divisor = vlv_dpll;
		count = ARRAY_SIZE(vlv_dpll);
1248
	}
1249 1250 1251

	if (divisor && count) {
		for (i = 0; i < count; i++) {
1252
			if (pipe_config->port_clock == divisor[i].clock) {
1253 1254 1255 1256 1257
				pipe_config->dpll = divisor[i].dpll;
				pipe_config->clock_set = true;
				break;
			}
		}
1258 1259 1260
	}
}

1261 1262
static int intersect_rates(const int *source_rates, int source_len,
			   const int *sink_rates, int sink_len,
1263
			   int *common_rates)
1264 1265 1266 1267 1268
{
	int i = 0, j = 0, k = 0;

	while (i < source_len && j < sink_len) {
		if (source_rates[i] == sink_rates[j]) {
1269 1270
			if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
				return k;
1271
			common_rates[k] = source_rates[i];
1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283
			++k;
			++i;
			++j;
		} else if (source_rates[i] < sink_rates[j]) {
			++i;
		} else {
			++j;
		}
	}
	return k;
}

1284 1285
static int intel_dp_common_rates(struct intel_dp *intel_dp,
				 int *common_rates)
1286 1287 1288 1289 1290 1291 1292 1293 1294 1295
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	const int *source_rates, *sink_rates;
	int source_len, sink_len;

	sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
	source_len = intel_dp_source_rates(dev, &source_rates);

	return intersect_rates(source_rates, source_len,
			       sink_rates, sink_len,
1296
			       common_rates);
1297 1298
}

1299 1300 1301 1302 1303 1304 1305 1306
static void snprintf_int_array(char *str, size_t len,
			       const int *array, int nelem)
{
	int i;

	str[0] = '\0';

	for (i = 0; i < nelem; i++) {
1307
		int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318
		if (r >= len)
			return;
		str += r;
		len -= r;
	}
}

static void intel_dp_print_rates(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	const int *source_rates, *sink_rates;
1319 1320
	int source_len, sink_len, common_len;
	int common_rates[DP_MAX_SUPPORTED_RATES];
1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333
	char str[128]; /* FIXME: too big for stack? */

	if ((drm_debug & DRM_UT_KMS) == 0)
		return;

	source_len = intel_dp_source_rates(dev, &source_rates);
	snprintf_int_array(str, sizeof(str), source_rates, source_len);
	DRM_DEBUG_KMS("source rates: %s\n", str);

	sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
	snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
	DRM_DEBUG_KMS("sink rates: %s\n", str);

1334 1335 1336
	common_len = intel_dp_common_rates(intel_dp, common_rates);
	snprintf_int_array(str, sizeof(str), common_rates, common_len);
	DRM_DEBUG_KMS("common rates: %s\n", str);
1337 1338
}

1339
static int rate_to_index(int find, const int *rates)
1340 1341 1342 1343 1344 1345 1346 1347 1348 1349
{
	int i = 0;

	for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
		if (find == rates[i])
			break;

	return i;
}

1350 1351 1352 1353 1354 1355
int
intel_dp_max_link_rate(struct intel_dp *intel_dp)
{
	int rates[DP_MAX_SUPPORTED_RATES] = {};
	int len;

1356
	len = intel_dp_common_rates(intel_dp, rates);
1357 1358 1359 1360 1361 1362
	if (WARN_ON(len <= 0))
		return 162000;

	return rates[rate_to_index(0, rates) - 1];
}

1363 1364
int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
{
1365
	return rate_to_index(rate, intel_dp->sink_rates);
1366 1367
}

1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380
static void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
				  uint8_t *link_bw, uint8_t *rate_select)
{
	if (intel_dp->num_sink_rates) {
		*link_bw = 0;
		*rate_select =
			intel_dp_rate_select(intel_dp, port_clock);
	} else {
		*link_bw = drm_dp_link_rate_to_bw_code(port_clock);
		*rate_select = 0;
	}
}

P
Paulo Zanoni 已提交
1381
bool
1382
intel_dp_compute_config(struct intel_encoder *encoder,
1383
			struct intel_crtc_state *pipe_config)
1384
{
1385
	struct drm_device *dev = encoder->base.dev;
1386
	struct drm_i915_private *dev_priv = dev->dev_private;
1387
	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1388
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1389
	enum port port = dp_to_dig_port(intel_dp)->port;
1390
	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1391
	struct intel_connector *intel_connector = intel_dp->attached_connector;
1392
	int lane_count, clock;
1393
	int min_lane_count = 1;
1394
	int max_lane_count = intel_dp_max_lane_count(intel_dp);
1395
	/* Conveniently, the link BW constants become indices with a shift...*/
1396
	int min_clock = 0;
1397
	int max_clock;
1398
	int bpp, mode_rate;
1399
	int link_avail, link_clock;
1400 1401
	int common_rates[DP_MAX_SUPPORTED_RATES] = {};
	int common_len;
1402
	uint8_t link_bw, rate_select;
1403

1404
	common_len = intel_dp_common_rates(intel_dp, common_rates);
1405 1406

	/* No common link rates between source and sink */
1407
	WARN_ON(common_len <= 0);
1408

1409
	max_clock = common_len - 1;
1410

1411
	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
1412 1413
		pipe_config->has_pch_encoder = true;

1414
	pipe_config->has_dp_encoder = true;
1415
	pipe_config->has_drrs = false;
1416
	pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
1417

1418 1419 1420
	if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
		intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
				       adjusted_mode);
1421 1422 1423

		if (INTEL_INFO(dev)->gen >= 9) {
			int ret;
1424
			ret = skl_update_scaler_crtc(pipe_config);
1425 1426 1427 1428
			if (ret)
				return ret;
		}

1429 1430 1431 1432
		if (!HAS_PCH_SPLIT(dev))
			intel_gmch_panel_fitting(intel_crtc, pipe_config,
						 intel_connector->panel.fitting_mode);
		else
1433 1434
			intel_pch_panel_fitting(intel_crtc, pipe_config,
						intel_connector->panel.fitting_mode);
1435 1436
	}

1437
	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1438 1439
		return false;

1440
	DRM_DEBUG_KMS("DP link computation with max lane count %i "
1441
		      "max bw %d pixel clock %iKHz\n",
1442
		      max_lane_count, common_rates[max_clock],
1443
		      adjusted_mode->crtc_clock);
1444

1445 1446
	/* Walk through all bpp values. Luckily they're all nicely spaced with 2
	 * bpc in between. */
1447
	bpp = pipe_config->pipe_bpp;
1448
	if (is_edp(intel_dp)) {
1449 1450 1451 1452

		/* Get bpp from vbt only for panels that dont have bpp in edid */
		if (intel_connector->base.display_info.bpc == 0 &&
			(dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp)) {
1453 1454 1455 1456 1457
			DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
				      dev_priv->vbt.edp_bpp);
			bpp = dev_priv->vbt.edp_bpp;
		}

1458 1459 1460 1461 1462 1463 1464 1465 1466
		/*
		 * Use the maximum clock and number of lanes the eDP panel
		 * advertizes being capable of. The panels are generally
		 * designed to support only a single clock and lane
		 * configuration, and typically these values correspond to the
		 * native resolution of the panel.
		 */
		min_lane_count = max_lane_count;
		min_clock = max_clock;
1467
	}
1468

1469
	for (; bpp >= 6*3; bpp -= 2*3) {
1470 1471
		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
						   bpp);
1472

1473
		for (clock = min_clock; clock <= max_clock; clock++) {
1474 1475 1476 1477
			for (lane_count = min_lane_count;
				lane_count <= max_lane_count;
				lane_count <<= 1) {

1478
				link_clock = common_rates[clock];
1479 1480 1481 1482 1483 1484 1485 1486 1487
				link_avail = intel_dp_max_data_rate(link_clock,
								    lane_count);

				if (mode_rate <= link_avail) {
					goto found;
				}
			}
		}
	}
1488

1489
	return false;
1490

1491
found:
1492 1493 1494 1495 1496 1497
	if (intel_dp->color_range_auto) {
		/*
		 * See:
		 * CEA-861-E - 5.1 Default Encoding Parameters
		 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
		 */
1498 1499 1500 1501 1502
		pipe_config->limited_color_range =
			bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
	} else {
		pipe_config->limited_color_range =
			intel_dp->limited_color_range;
1503 1504
	}

1505
	pipe_config->lane_count = lane_count;
1506

1507
	pipe_config->pipe_bpp = bpp;
1508
	pipe_config->port_clock = common_rates[clock];
1509

1510 1511 1512 1513 1514
	intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
			      &link_bw, &rate_select);

	DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
		      link_bw, rate_select, pipe_config->lane_count,
1515
		      pipe_config->port_clock, bpp);
1516 1517
	DRM_DEBUG_KMS("DP link bw required %i available %i\n",
		      mode_rate, link_avail);
1518

1519
	intel_link_compute_m_n(bpp, lane_count,
1520 1521
			       adjusted_mode->crtc_clock,
			       pipe_config->port_clock,
1522
			       &pipe_config->dp_m_n);
1523

1524
	if (intel_connector->panel.downclock_mode != NULL &&
1525
		dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1526
			pipe_config->has_drrs = true;
1527 1528 1529 1530 1531 1532
			intel_link_compute_m_n(bpp, lane_count,
				intel_connector->panel.downclock_mode->clock,
				pipe_config->port_clock,
				&pipe_config->dp_m2_n2);
	}

1533
	if (IS_SKYLAKE(dev) && is_edp(intel_dp))
1534
		skl_edp_set_pll_config(pipe_config);
1535 1536
	else if (IS_BROXTON(dev))
		/* handled in ddi */;
1537
	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1538
		hsw_dp_set_ddi_pll_sel(pipe_config);
1539
	else
1540
		intel_dp_set_clock(encoder, pipe_config);
1541

1542
	return true;
1543 1544
}

1545
static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
1546
{
1547 1548 1549
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
	struct drm_device *dev = crtc->base.dev;
1550 1551 1552
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

1553 1554
	DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
		      crtc->config->port_clock);
1555 1556 1557
	dpa_ctl = I915_READ(DP_A);
	dpa_ctl &= ~DP_PLL_FREQ_MASK;

1558
	if (crtc->config->port_clock == 162000) {
1559 1560 1561 1562
		/* For a long time we've carried around a ILK-DevA w/a for the
		 * 160MHz clock. If we're really unlucky, it's still required.
		 */
		DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1563
		dpa_ctl |= DP_PLL_FREQ_160MHZ;
1564
		intel_dp->DP |= DP_PLL_FREQ_160MHZ;
1565 1566
	} else {
		dpa_ctl |= DP_PLL_FREQ_270MHZ;
1567
		intel_dp->DP |= DP_PLL_FREQ_270MHZ;
1568
	}
1569

1570 1571 1572 1573 1574 1575
	I915_WRITE(DP_A, dpa_ctl);

	POSTING_READ(DP_A);
	udelay(500);
}

1576 1577 1578 1579 1580 1581 1582
void intel_dp_set_link_params(struct intel_dp *intel_dp,
			      const struct intel_crtc_state *pipe_config)
{
	intel_dp->link_rate = pipe_config->port_clock;
	intel_dp->lane_count = pipe_config->lane_count;
}

1583
static void intel_dp_prepare(struct intel_encoder *encoder)
1584
{
1585
	struct drm_device *dev = encoder->base.dev;
1586
	struct drm_i915_private *dev_priv = dev->dev_private;
1587
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1588
	enum port port = dp_to_dig_port(intel_dp)->port;
1589
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1590
	const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
1591

1592 1593
	intel_dp_set_link_params(intel_dp, crtc->config);

1594
	/*
K
Keith Packard 已提交
1595
	 * There are four kinds of DP registers:
1596 1597
	 *
	 * 	IBX PCH
K
Keith Packard 已提交
1598 1599
	 * 	SNB CPU
	 *	IVB CPU
1600 1601 1602 1603 1604 1605 1606 1607 1608 1609
	 * 	CPT PCH
	 *
	 * IBX PCH and CPU are the same for almost everything,
	 * except that the CPU DP PLL is configured in this
	 * register
	 *
	 * CPT PCH is quite different, having many bits moved
	 * to the TRANS_DP_CTL register instead. That
	 * configuration happens (oddly) in ironlake_pch_enable
	 */
1610

1611 1612 1613 1614
	/* Preserve the BIOS-computed detected bit. This is
	 * supposed to be read-only.
	 */
	intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1615

1616 1617
	/* Handle DP bits in common between all three register formats */
	intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1618
	intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count);
1619

1620
	if (crtc->config->has_audio)
C
Chris Wilson 已提交
1621
		intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1622

1623
	/* Split out the IBX/CPU vs CPT settings */
1624

1625
	if (IS_GEN7(dev) && port == PORT_A) {
K
Keith Packard 已提交
1626 1627 1628 1629 1630 1631
		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
			intel_dp->DP |= DP_SYNC_HS_HIGH;
		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
			intel_dp->DP |= DP_SYNC_VS_HIGH;
		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;

1632
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
K
Keith Packard 已提交
1633 1634
			intel_dp->DP |= DP_ENHANCED_FRAMING;

1635
		intel_dp->DP |= crtc->pipe << 29;
1636
	} else if (HAS_PCH_CPT(dev) && port != PORT_A) {
1637 1638
		u32 trans_dp;

1639
		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1640 1641 1642 1643 1644 1645 1646

		trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
			trans_dp |= TRANS_DP_ENH_FRAMING;
		else
			trans_dp &= ~TRANS_DP_ENH_FRAMING;
		I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1647
	} else {
1648 1649 1650
		if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
		    crtc->config->limited_color_range)
			intel_dp->DP |= DP_COLOR_RANGE_16_235;
1651 1652 1653 1654 1655 1656 1657

		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
			intel_dp->DP |= DP_SYNC_HS_HIGH;
		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
			intel_dp->DP |= DP_SYNC_VS_HIGH;
		intel_dp->DP |= DP_LINK_TRAIN_OFF;

1658
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1659 1660
			intel_dp->DP |= DP_ENHANCED_FRAMING;

1661
		if (IS_CHERRYVIEW(dev))
1662
			intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1663 1664
		else if (crtc->pipe == PIPE_B)
			intel_dp->DP |= DP_PIPEB_SELECT;
1665
	}
1666 1667
}

1668 1669
#define IDLE_ON_MASK		(PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
#define IDLE_ON_VALUE   	(PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1670

1671 1672
#define IDLE_OFF_MASK		(PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
#define IDLE_OFF_VALUE		(0     | PP_SEQUENCE_NONE | 0                     | 0)
1673

1674 1675
#define IDLE_CYCLE_MASK		(PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
#define IDLE_CYCLE_VALUE	(0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1676

1677
static void wait_panel_status(struct intel_dp *intel_dp,
1678 1679
				       u32 mask,
				       u32 value)
1680
{
1681
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1682
	struct drm_i915_private *dev_priv = dev->dev_private;
1683 1684
	u32 pp_stat_reg, pp_ctrl_reg;

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1685 1686
	lockdep_assert_held(&dev_priv->pps_mutex);

1687 1688
	pp_stat_reg = _pp_stat_reg(intel_dp);
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1689

1690
	DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1691 1692 1693
			mask, value,
			I915_READ(pp_stat_reg),
			I915_READ(pp_ctrl_reg));
1694

1695
	if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1696
		DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1697 1698
				I915_READ(pp_stat_reg),
				I915_READ(pp_ctrl_reg));
1699
	}
1700 1701

	DRM_DEBUG_KMS("Wait complete\n");
1702
}
1703

1704
static void wait_panel_on(struct intel_dp *intel_dp)
1705 1706
{
	DRM_DEBUG_KMS("Wait for panel power on\n");
1707
	wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1708 1709
}

1710
static void wait_panel_off(struct intel_dp *intel_dp)
1711 1712
{
	DRM_DEBUG_KMS("Wait for panel power off time\n");
1713
	wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1714 1715
}

1716
static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1717 1718
{
	DRM_DEBUG_KMS("Wait for panel power cycle\n");
1719 1720 1721 1722 1723 1724

	/* When we disable the VDD override bit last we have to do the manual
	 * wait. */
	wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
				       intel_dp->panel_power_cycle_delay);

1725
	wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1726 1727
}

1728
static void wait_backlight_on(struct intel_dp *intel_dp)
1729 1730 1731 1732 1733
{
	wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
				       intel_dp->backlight_on_delay);
}

1734
static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1735 1736 1737 1738
{
	wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
				       intel_dp->backlight_off_delay);
}
1739

1740 1741 1742 1743
/* Read the current pp_control value, unlocking the register if it
 * is locked
 */

1744
static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1745
{
1746 1747 1748
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 control;
1749

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1750 1751
	lockdep_assert_held(&dev_priv->pps_mutex);

1752
	control = I915_READ(_pp_ctrl_reg(intel_dp));
1753 1754 1755 1756
	if (!IS_BROXTON(dev)) {
		control &= ~PANEL_UNLOCK_MASK;
		control |= PANEL_UNLOCK_REGS;
	}
1757
	return control;
1758 1759
}

1760 1761 1762 1763 1764
/*
 * Must be paired with edp_panel_vdd_off().
 * Must hold pps_mutex around the whole on/off sequence.
 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
 */
1765
static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1766
{
1767
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1768 1769
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
1770
	struct drm_i915_private *dev_priv = dev->dev_private;
1771
	enum intel_display_power_domain power_domain;
1772
	u32 pp;
1773
	u32 pp_stat_reg, pp_ctrl_reg;
1774
	bool need_to_disable = !intel_dp->want_panel_vdd;
1775

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1776 1777
	lockdep_assert_held(&dev_priv->pps_mutex);

1778
	if (!is_edp(intel_dp))
1779
		return false;
1780

1781
	cancel_delayed_work(&intel_dp->panel_vdd_work);
1782
	intel_dp->want_panel_vdd = true;
1783

1784
	if (edp_have_panel_vdd(intel_dp))
1785
		return need_to_disable;
1786

1787 1788
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_get(dev_priv, power_domain);
1789

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1790 1791
	DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
		      port_name(intel_dig_port->port));
1792

1793 1794
	if (!edp_have_panel_power(intel_dp))
		wait_panel_power_cycle(intel_dp);
1795

1796
	pp = ironlake_get_pp_control(intel_dp);
1797
	pp |= EDP_FORCE_VDD;
1798

1799 1800
	pp_stat_reg = _pp_stat_reg(intel_dp);
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1801 1802 1803 1804 1805

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
	DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
			I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1806 1807 1808
	/*
	 * If the panel wasn't on, delay before accessing aux channel
	 */
1809
	if (!edp_have_panel_power(intel_dp)) {
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1810 1811
		DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
			      port_name(intel_dig_port->port));
1812 1813
		msleep(intel_dp->panel_power_up_delay);
	}
1814 1815 1816 1817

	return need_to_disable;
}

1818 1819 1820 1821 1822 1823 1824
/*
 * Must be paired with intel_edp_panel_vdd_off() or
 * intel_edp_panel_off().
 * Nested calls to these functions are not allowed since
 * we drop the lock. Caller must use some higher level
 * locking to prevent nested calls from other threads.
 */
1825
void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1826
{
1827
	bool vdd;
1828

1829 1830 1831
	if (!is_edp(intel_dp))
		return;

1832
	pps_lock(intel_dp);
1833
	vdd = edp_panel_vdd_on(intel_dp);
1834
	pps_unlock(intel_dp);
1835

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1836
	I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
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1837
	     port_name(dp_to_dig_port(intel_dp)->port));
1838 1839
}

1840
static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1841
{
1842
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1843
	struct drm_i915_private *dev_priv = dev->dev_private;
1844 1845 1846 1847
	struct intel_digital_port *intel_dig_port =
		dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	enum intel_display_power_domain power_domain;
1848
	u32 pp;
1849
	u32 pp_stat_reg, pp_ctrl_reg;
1850

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1851
	lockdep_assert_held(&dev_priv->pps_mutex);
1852

1853
	WARN_ON(intel_dp->want_panel_vdd);
1854

1855
	if (!edp_have_panel_vdd(intel_dp))
1856
		return;
1857

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1858 1859
	DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
		      port_name(intel_dig_port->port));
1860

1861 1862
	pp = ironlake_get_pp_control(intel_dp);
	pp &= ~EDP_FORCE_VDD;
1863

1864 1865
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
	pp_stat_reg = _pp_stat_reg(intel_dp);
1866

1867 1868
	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
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1869

1870 1871 1872
	/* Make sure sequencer is idle before allowing subsequent activity */
	DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
	I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1873

1874 1875
	if ((pp & POWER_TARGET_ON) == 0)
		intel_dp->last_power_cycle = jiffies;
1876

1877 1878
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_put(dev_priv, power_domain);
1879
}
1880

1881
static void edp_panel_vdd_work(struct work_struct *__work)
1882 1883 1884 1885
{
	struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
						 struct intel_dp, panel_vdd_work);

1886
	pps_lock(intel_dp);
1887 1888
	if (!intel_dp->want_panel_vdd)
		edp_panel_vdd_off_sync(intel_dp);
1889
	pps_unlock(intel_dp);
1890 1891
}

1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904
static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
{
	unsigned long delay;

	/*
	 * Queue the timer to fire a long time from now (relative to the power
	 * down delay) to keep the panel power up across a sequence of
	 * operations.
	 */
	delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
	schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
}

1905 1906 1907 1908 1909
/*
 * Must be paired with edp_panel_vdd_on().
 * Must hold pps_mutex around the whole on/off sequence.
 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
 */
1910
static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1911
{
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1912 1913 1914 1915 1916
	struct drm_i915_private *dev_priv =
		intel_dp_to_dev(intel_dp)->dev_private;

	lockdep_assert_held(&dev_priv->pps_mutex);

1917 1918
	if (!is_edp(intel_dp))
		return;
1919

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1920
	I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
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1921
	     port_name(dp_to_dig_port(intel_dp)->port));
1922

1923 1924
	intel_dp->want_panel_vdd = false;

1925
	if (sync)
1926
		edp_panel_vdd_off_sync(intel_dp);
1927 1928
	else
		edp_panel_vdd_schedule_off(intel_dp);
1929 1930
}

1931
static void edp_panel_on(struct intel_dp *intel_dp)
1932
{
1933
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1934
	struct drm_i915_private *dev_priv = dev->dev_private;
1935
	u32 pp;
1936
	u32 pp_ctrl_reg;
1937

1938 1939
	lockdep_assert_held(&dev_priv->pps_mutex);

1940
	if (!is_edp(intel_dp))
1941
		return;
1942

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1943 1944
	DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
		      port_name(dp_to_dig_port(intel_dp)->port));
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1945

1946 1947 1948
	if (WARN(edp_have_panel_power(intel_dp),
		 "eDP port %c panel power already on\n",
		 port_name(dp_to_dig_port(intel_dp)->port)))
1949
		return;
1950

1951
	wait_panel_power_cycle(intel_dp);
1952

1953
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1954
	pp = ironlake_get_pp_control(intel_dp);
1955 1956 1957
	if (IS_GEN5(dev)) {
		/* ILK workaround: disable reset around power sequence */
		pp &= ~PANEL_POWER_RESET;
1958 1959
		I915_WRITE(pp_ctrl_reg, pp);
		POSTING_READ(pp_ctrl_reg);
1960
	}
1961

1962
	pp |= POWER_TARGET_ON;
1963 1964 1965
	if (!IS_GEN5(dev))
		pp |= PANEL_POWER_RESET;

1966 1967
	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1968

1969
	wait_panel_on(intel_dp);
1970
	intel_dp->last_power_on = jiffies;
1971

1972 1973
	if (IS_GEN5(dev)) {
		pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1974 1975
		I915_WRITE(pp_ctrl_reg, pp);
		POSTING_READ(pp_ctrl_reg);
1976
	}
1977
}
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1978

1979 1980 1981 1982 1983 1984 1985
void intel_edp_panel_on(struct intel_dp *intel_dp)
{
	if (!is_edp(intel_dp))
		return;

	pps_lock(intel_dp);
	edp_panel_on(intel_dp);
1986
	pps_unlock(intel_dp);
1987 1988
}

1989 1990

static void edp_panel_off(struct intel_dp *intel_dp)
1991
{
1992 1993
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
1994
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1995
	struct drm_i915_private *dev_priv = dev->dev_private;
1996
	enum intel_display_power_domain power_domain;
1997
	u32 pp;
1998
	u32 pp_ctrl_reg;
1999

2000 2001
	lockdep_assert_held(&dev_priv->pps_mutex);

2002 2003
	if (!is_edp(intel_dp))
		return;
2004

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2005 2006
	DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
		      port_name(dp_to_dig_port(intel_dp)->port));
2007

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2008 2009
	WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
	     port_name(dp_to_dig_port(intel_dp)->port));
2010

2011
	pp = ironlake_get_pp_control(intel_dp);
2012 2013
	/* We need to switch off panel power _and_ force vdd, for otherwise some
	 * panels get very unhappy and cease to work. */
2014 2015
	pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
		EDP_BLC_ENABLE);
2016

2017
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2018

2019 2020
	intel_dp->want_panel_vdd = false;

2021 2022
	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
2023

2024
	intel_dp->last_power_cycle = jiffies;
2025
	wait_panel_off(intel_dp);
2026 2027

	/* We got a reference when we enabled the VDD. */
2028 2029
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_put(dev_priv, power_domain);
2030
}
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2031

2032 2033 2034 2035
void intel_edp_panel_off(struct intel_dp *intel_dp)
{
	if (!is_edp(intel_dp))
		return;
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2036

2037 2038
	pps_lock(intel_dp);
	edp_panel_off(intel_dp);
2039
	pps_unlock(intel_dp);
2040 2041
}

2042 2043
/* Enable backlight in the panel power control. */
static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2044
{
2045 2046
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
2047 2048
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
2049
	u32 pp_ctrl_reg;
2050

2051 2052 2053 2054 2055 2056
	/*
	 * If we enable the backlight right away following a panel power
	 * on, we may see slight flicker as the panel syncs with the eDP
	 * link.  So delay a bit to make sure the image is solid before
	 * allowing it to appear.
	 */
2057
	wait_backlight_on(intel_dp);
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2058

2059
	pps_lock(intel_dp);
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2060

2061
	pp = ironlake_get_pp_control(intel_dp);
2062
	pp |= EDP_BLC_ENABLE;
2063

2064
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2065 2066 2067

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
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2068

2069
	pps_unlock(intel_dp);
2070 2071
}

2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085
/* Enable backlight PWM and backlight PP control. */
void intel_edp_backlight_on(struct intel_dp *intel_dp)
{
	if (!is_edp(intel_dp))
		return;

	DRM_DEBUG_KMS("\n");

	intel_panel_enable_backlight(intel_dp->attached_connector);
	_intel_edp_backlight_on(intel_dp);
}

/* Disable backlight in the panel power control. */
static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2086
{
2087
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2088 2089
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
2090
	u32 pp_ctrl_reg;
2091

2092 2093 2094
	if (!is_edp(intel_dp))
		return;

2095
	pps_lock(intel_dp);
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2096

2097
	pp = ironlake_get_pp_control(intel_dp);
2098
	pp &= ~EDP_BLC_ENABLE;
2099

2100
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2101 2102 2103

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
2104

2105
	pps_unlock(intel_dp);
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2106 2107

	intel_dp->last_backlight_off = jiffies;
2108
	edp_wait_backlight_off(intel_dp);
2109
}
2110

2111 2112 2113 2114 2115 2116 2117
/* Disable backlight PP control and backlight PWM. */
void intel_edp_backlight_off(struct intel_dp *intel_dp)
{
	if (!is_edp(intel_dp))
		return;

	DRM_DEBUG_KMS("\n");
2118

2119
	_intel_edp_backlight_off(intel_dp);
2120
	intel_panel_disable_backlight(intel_dp->attached_connector);
2121
}
2122

2123 2124 2125 2126 2127 2128 2129 2130
/*
 * Hook for controlling the panel power control backlight through the bl_power
 * sysfs attribute. Take care to handle multiple calls.
 */
static void intel_edp_backlight_power(struct intel_connector *connector,
				      bool enable)
{
	struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
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2131 2132
	bool is_enabled;

2133
	pps_lock(intel_dp);
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2134
	is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2135
	pps_unlock(intel_dp);
2136 2137 2138 2139

	if (is_enabled == enable)
		return;

2140 2141
	DRM_DEBUG_KMS("panel power control backlight %s\n",
		      enable ? "enable" : "disable");
2142 2143 2144 2145 2146 2147 2148

	if (enable)
		_intel_edp_backlight_on(intel_dp);
	else
		_intel_edp_backlight_off(intel_dp);
}

2149
static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
2150
{
2151 2152 2153
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
	struct drm_device *dev = crtc->dev;
2154 2155 2156
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

2157 2158 2159
	assert_pipe_disabled(dev_priv,
			     to_intel_crtc(crtc)->pipe);

2160 2161
	DRM_DEBUG_KMS("\n");
	dpa_ctl = I915_READ(DP_A);
2162 2163 2164 2165 2166 2167 2168 2169 2170
	WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
	WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");

	/* We don't adjust intel_dp->DP while tearing down the link, to
	 * facilitate link retraining (e.g. after hotplug). Hence clear all
	 * enable bits here to ensure that we don't enable too much. */
	intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
	intel_dp->DP |= DP_PLL_ENABLE;
	I915_WRITE(DP_A, intel_dp->DP);
2171 2172
	POSTING_READ(DP_A);
	udelay(200);
2173 2174
}

2175
static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2176
{
2177 2178 2179
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
	struct drm_device *dev = crtc->dev;
2180 2181 2182
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

2183 2184 2185
	assert_pipe_disabled(dev_priv,
			     to_intel_crtc(crtc)->pipe);

2186
	dpa_ctl = I915_READ(DP_A);
2187 2188 2189 2190 2191 2192 2193
	WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
	     "dp pll off, should be on\n");
	WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");

	/* We can't rely on the value tracked for the DP register in
	 * intel_dp->DP because link_down must not change that (otherwise link
	 * re-training will fail. */
2194
	dpa_ctl &= ~DP_PLL_ENABLE;
2195
	I915_WRITE(DP_A, dpa_ctl);
2196
	POSTING_READ(DP_A);
2197 2198 2199
	udelay(200);
}

2200
/* If the sink supports it, try to set the power state appropriately */
2201
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2202 2203 2204 2205 2206 2207 2208 2209
{
	int ret, i;

	/* Should have a valid DPCD by this point */
	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
		return;

	if (mode != DRM_MODE_DPMS_ON) {
2210 2211
		ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
					 DP_SET_POWER_D3);
2212 2213 2214 2215 2216 2217
	} else {
		/*
		 * When turning on, we need to retry for 1ms to give the sink
		 * time to wake up.
		 */
		for (i = 0; i < 3; i++) {
2218 2219
			ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
						 DP_SET_POWER_D0);
2220 2221 2222 2223 2224
			if (ret == 1)
				break;
			msleep(1);
		}
	}
2225 2226 2227 2228

	if (ret != 1)
		DRM_DEBUG_KMS("failed to %s sink power state\n",
			      mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2229 2230
}

2231 2232
static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
				  enum pipe *pipe)
2233
{
2234
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2235
	enum port port = dp_to_dig_port(intel_dp)->port;
2236 2237
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2238 2239 2240 2241
	enum intel_display_power_domain power_domain;
	u32 tmp;

	power_domain = intel_display_port_power_domain(encoder);
2242
	if (!intel_display_power_is_enabled(dev_priv, power_domain))
2243 2244 2245
		return false;

	tmp = I915_READ(intel_dp->output_reg);
2246 2247 2248 2249

	if (!(tmp & DP_PORT_EN))
		return false;

2250
	if (IS_GEN7(dev) && port == PORT_A) {
2251
		*pipe = PORT_TO_PIPE_CPT(tmp);
2252
	} else if (HAS_PCH_CPT(dev) && port != PORT_A) {
2253
		enum pipe p;
2254

2255 2256 2257 2258
		for_each_pipe(dev_priv, p) {
			u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
			if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
				*pipe = p;
2259 2260 2261 2262
				return true;
			}
		}

2263 2264
		DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
			      intel_dp->output_reg);
2265 2266 2267 2268
	} else if (IS_CHERRYVIEW(dev)) {
		*pipe = DP_PORT_TO_PIPE_CHV(tmp);
	} else {
		*pipe = PORT_TO_PIPE(tmp);
2269
	}
2270

2271 2272
	return true;
}
2273

2274
static void intel_dp_get_config(struct intel_encoder *encoder,
2275
				struct intel_crtc_state *pipe_config)
2276 2277 2278
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	u32 tmp, flags = 0;
2279 2280 2281 2282
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = dp_to_dig_port(intel_dp)->port;
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2283
	int dotclock;
2284

2285
	tmp = I915_READ(intel_dp->output_reg);
2286 2287

	pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2288

2289
	if (HAS_PCH_CPT(dev) && port != PORT_A) {
2290 2291 2292
		u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));

		if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2293 2294 2295
			flags |= DRM_MODE_FLAG_PHSYNC;
		else
			flags |= DRM_MODE_FLAG_NHSYNC;
2296

2297
		if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2298 2299 2300 2301
			flags |= DRM_MODE_FLAG_PVSYNC;
		else
			flags |= DRM_MODE_FLAG_NVSYNC;
	} else {
2302
		if (tmp & DP_SYNC_HS_HIGH)
2303 2304 2305
			flags |= DRM_MODE_FLAG_PHSYNC;
		else
			flags |= DRM_MODE_FLAG_NHSYNC;
2306

2307
		if (tmp & DP_SYNC_VS_HIGH)
2308 2309 2310 2311
			flags |= DRM_MODE_FLAG_PVSYNC;
		else
			flags |= DRM_MODE_FLAG_NVSYNC;
	}
2312

2313
	pipe_config->base.adjusted_mode.flags |= flags;
2314

2315 2316 2317 2318
	if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
	    tmp & DP_COLOR_RANGE_16_235)
		pipe_config->limited_color_range = true;

2319 2320
	pipe_config->has_dp_encoder = true;

2321 2322 2323
	pipe_config->lane_count =
		((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;

2324 2325
	intel_dp_get_m_n(crtc, pipe_config);

2326
	if (port == PORT_A) {
2327 2328 2329 2330 2331
		if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
			pipe_config->port_clock = 162000;
		else
			pipe_config->port_clock = 270000;
	}
2332 2333 2334 2335 2336 2337 2338

	dotclock = intel_dotclock_calculate(pipe_config->port_clock,
					    &pipe_config->dp_m_n);

	if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
		ironlake_check_encoder_dotclock(pipe_config, dotclock);

2339
	pipe_config->base.adjusted_mode.crtc_clock = dotclock;
2340

2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359
	if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
	    pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
		/*
		 * This is a big fat ugly hack.
		 *
		 * Some machines in UEFI boot mode provide us a VBT that has 18
		 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
		 * unknown we fail to light up. Yet the same BIOS boots up with
		 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
		 * max, not what it tells us to use.
		 *
		 * Note: This will still be broken if the eDP panel is not lit
		 * up by the BIOS, and thus we can't get the mode at module
		 * load.
		 */
		DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
			      pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
		dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
	}
2360 2361
}

2362
static void intel_disable_dp(struct intel_encoder *encoder)
2363
{
2364
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2365
	struct drm_device *dev = encoder->base.dev;
2366 2367
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);

2368
	if (crtc->config->has_audio)
2369
		intel_audio_codec_disable(encoder);
2370

2371 2372 2373
	if (HAS_PSR(dev) && !HAS_DDI(dev))
		intel_psr_disable(intel_dp);

2374 2375
	/* Make sure the panel is off before trying to change the mode. But also
	 * ensure that we have vdd while we switch off the panel. */
2376
	intel_edp_panel_vdd_on(intel_dp);
2377
	intel_edp_backlight_off(intel_dp);
2378
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2379
	intel_edp_panel_off(intel_dp);
2380

2381 2382
	/* disable the port before the pipe on g4x */
	if (INTEL_INFO(dev)->gen < 5)
2383
		intel_dp_link_down(intel_dp);
2384 2385
}

2386
static void ilk_post_disable_dp(struct intel_encoder *encoder)
2387
{
2388
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2389
	enum port port = dp_to_dig_port(intel_dp)->port;
2390

2391
	intel_dp_link_down(intel_dp);
2392 2393
	if (port == PORT_A)
		ironlake_edp_pll_off(intel_dp);
2394 2395 2396 2397 2398 2399 2400
}

static void vlv_post_disable_dp(struct intel_encoder *encoder)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

	intel_dp_link_down(intel_dp);
2401 2402
}

2403 2404
static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
				     bool reset)
2405
{
2406 2407 2408 2409 2410
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
	enum pipe pipe = crtc->pipe;
	uint32_t val;
2411

2412 2413 2414 2415 2416 2417
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
	if (reset)
		val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
	else
		val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2418

2419 2420 2421 2422 2423 2424 2425 2426
	if (crtc->config->lane_count > 2) {
		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
		if (reset)
			val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
		else
			val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
	}
2427

2428
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2429
	val |= CHV_PCS_REQ_SOFTRESET_EN;
2430 2431 2432 2433
	if (reset)
		val &= ~DPIO_PCS_CLK_SOFT_RESET;
	else
		val |= DPIO_PCS_CLK_SOFT_RESET;
2434
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2435

2436
	if (crtc->config->lane_count > 2) {
2437 2438
		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
		val |= CHV_PCS_REQ_SOFTRESET_EN;
2439 2440 2441 2442
		if (reset)
			val &= ~DPIO_PCS_CLK_SOFT_RESET;
		else
			val |= DPIO_PCS_CLK_SOFT_RESET;
2443 2444
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
	}
2445
}
2446

2447 2448 2449 2450 2451
static void chv_post_disable_dp(struct intel_encoder *encoder)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2452

2453 2454 2455 2456 2457 2458
	intel_dp_link_down(intel_dp);

	mutex_lock(&dev_priv->sb_lock);

	/* Assert data lane reset */
	chv_data_lane_soft_reset(encoder, true);
2459

V
Ville Syrjälä 已提交
2460
	mutex_unlock(&dev_priv->sb_lock);
2461 2462
}

2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498
static void
_intel_dp_set_link_train(struct intel_dp *intel_dp,
			 uint32_t *DP,
			 uint8_t dp_train_pat)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = intel_dig_port->port;

	if (HAS_DDI(dev)) {
		uint32_t temp = I915_READ(DP_TP_CTL(port));

		if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
			temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
		else
			temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;

		temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
			temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;

			break;
		case DP_TRAINING_PATTERN_1:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
			break;
		case DP_TRAINING_PATTERN_2:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
			break;
		case DP_TRAINING_PATTERN_3:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
			break;
		}
		I915_WRITE(DP_TP_CTL(port), temp);

2499 2500
	} else if ((IS_GEN7(dev) && port == PORT_A) ||
		   (HAS_PCH_CPT(dev) && port != PORT_A)) {
2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557
		*DP &= ~DP_LINK_TRAIN_MASK_CPT;

		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
			*DP |= DP_LINK_TRAIN_OFF_CPT;
			break;
		case DP_TRAINING_PATTERN_1:
			*DP |= DP_LINK_TRAIN_PAT_1_CPT;
			break;
		case DP_TRAINING_PATTERN_2:
			*DP |= DP_LINK_TRAIN_PAT_2_CPT;
			break;
		case DP_TRAINING_PATTERN_3:
			DRM_ERROR("DP training pattern 3 not supported\n");
			*DP |= DP_LINK_TRAIN_PAT_2_CPT;
			break;
		}

	} else {
		if (IS_CHERRYVIEW(dev))
			*DP &= ~DP_LINK_TRAIN_MASK_CHV;
		else
			*DP &= ~DP_LINK_TRAIN_MASK;

		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
			*DP |= DP_LINK_TRAIN_OFF;
			break;
		case DP_TRAINING_PATTERN_1:
			*DP |= DP_LINK_TRAIN_PAT_1;
			break;
		case DP_TRAINING_PATTERN_2:
			*DP |= DP_LINK_TRAIN_PAT_2;
			break;
		case DP_TRAINING_PATTERN_3:
			if (IS_CHERRYVIEW(dev)) {
				*DP |= DP_LINK_TRAIN_PAT_3_CHV;
			} else {
				DRM_ERROR("DP training pattern 3 not supported\n");
				*DP |= DP_LINK_TRAIN_PAT_2;
			}
			break;
		}
	}
}

static void intel_dp_enable_port(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;

	/* enable with pattern 1 (as per spec) */
	_intel_dp_set_link_train(intel_dp, &intel_dp->DP,
				 DP_TRAINING_PATTERN_1);

	I915_WRITE(intel_dp->output_reg, intel_dp->DP);
	POSTING_READ(intel_dp->output_reg);
2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568

	/*
	 * Magic for VLV/CHV. We _must_ first set up the register
	 * without actually enabling the port, and then do another
	 * write to enable the port. Otherwise link training will
	 * fail when the power sequencer is freshly used for this port.
	 */
	intel_dp->DP |= DP_PORT_EN;

	I915_WRITE(intel_dp->output_reg, intel_dp->DP);
	POSTING_READ(intel_dp->output_reg);
2569 2570
}

2571
static void intel_enable_dp(struct intel_encoder *encoder)
2572
{
2573 2574 2575
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2576
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2577
	uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2578

2579 2580
	if (WARN_ON(dp_reg & DP_PORT_EN))
		return;
2581

2582 2583 2584 2585 2586
	pps_lock(intel_dp);

	if (IS_VALLEYVIEW(dev))
		vlv_init_panel_power_sequencer(intel_dp);

2587
	intel_dp_enable_port(intel_dp);
2588 2589 2590 2591 2592 2593 2594

	edp_panel_vdd_on(intel_dp);
	edp_panel_on(intel_dp);
	edp_panel_vdd_off(intel_dp, true);

	pps_unlock(intel_dp);

2595 2596 2597 2598 2599 2600
	if (IS_VALLEYVIEW(dev)) {
		unsigned int lane_mask = 0x0;

		if (IS_CHERRYVIEW(dev))
			lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count);

2601 2602
		vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
				    lane_mask);
2603
	}
2604

2605
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2606
	intel_dp_start_link_train(intel_dp);
2607
	intel_dp_stop_link_train(intel_dp);
2608

2609
	if (crtc->config->has_audio) {
2610 2611 2612 2613
		DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
				 pipe_name(crtc->pipe));
		intel_audio_codec_enable(encoder);
	}
2614
}
2615

2616 2617
static void g4x_enable_dp(struct intel_encoder *encoder)
{
2618 2619
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

2620
	intel_enable_dp(encoder);
2621
	intel_edp_backlight_on(intel_dp);
2622
}
2623

2624 2625
static void vlv_enable_dp(struct intel_encoder *encoder)
{
2626 2627
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

2628
	intel_edp_backlight_on(intel_dp);
2629
	intel_psr_enable(intel_dp);
2630 2631
}

2632
static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2633 2634 2635 2636
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);

2637 2638
	intel_dp_prepare(encoder);

2639 2640 2641
	/* Only ilk+ has port A */
	if (dport->port == PORT_A) {
		ironlake_set_pll_cpu_edp(intel_dp);
2642
		ironlake_edp_pll_on(intel_dp);
2643
	}
2644 2645
}

2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671
static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
	enum pipe pipe = intel_dp->pps_pipe;
	int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);

	edp_panel_vdd_off_sync(intel_dp);

	/*
	 * VLV seems to get confused when multiple power seqeuencers
	 * have the same port selected (even if only one has power/vdd
	 * enabled). The failure manifests as vlv_wait_port_ready() failing
	 * CHV on the other hand doesn't seem to mind having the same port
	 * selected in multiple power seqeuencers, but let's clear the
	 * port select always when logically disconnecting a power sequencer
	 * from a port.
	 */
	DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
		      pipe_name(pipe), port_name(intel_dig_port->port));
	I915_WRITE(pp_on_reg, 0);
	POSTING_READ(pp_on_reg);

	intel_dp->pps_pipe = INVALID_PIPE;
}

2672 2673 2674 2675 2676 2677 2678 2679
static void vlv_steal_power_sequencer(struct drm_device *dev,
				      enum pipe pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_encoder *encoder;

	lockdep_assert_held(&dev_priv->pps_mutex);

2680 2681 2682
	if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
		return;

2683 2684 2685
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		struct intel_dp *intel_dp;
2686
		enum port port;
2687 2688 2689 2690 2691

		if (encoder->type != INTEL_OUTPUT_EDP)
			continue;

		intel_dp = enc_to_intel_dp(&encoder->base);
2692
		port = dp_to_dig_port(intel_dp)->port;
2693 2694 2695 2696 2697

		if (intel_dp->pps_pipe != pipe)
			continue;

		DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2698
			      pipe_name(pipe), port_name(port));
2699

2700
		WARN(encoder->base.crtc,
2701 2702
		     "stealing pipe %c power sequencer from active eDP port %c\n",
		     pipe_name(pipe), port_name(port));
2703 2704

		/* make sure vdd is off before we steal it */
2705
		vlv_detach_power_sequencer(intel_dp);
2706 2707 2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718
	}
}

static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *encoder = &intel_dig_port->base;
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);

	lockdep_assert_held(&dev_priv->pps_mutex);

2719 2720 2721
	if (!is_edp(intel_dp))
		return;

2722 2723 2724 2725 2726 2727 2728 2729 2730
	if (intel_dp->pps_pipe == crtc->pipe)
		return;

	/*
	 * If another power sequencer was being used on this
	 * port previously make sure to turn off vdd there while
	 * we still have control of it.
	 */
	if (intel_dp->pps_pipe != INVALID_PIPE)
2731
		vlv_detach_power_sequencer(intel_dp);
2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745

	/*
	 * We may be stealing the power
	 * sequencer from another port.
	 */
	vlv_steal_power_sequencer(dev, crtc->pipe);

	/* now it's all ours */
	intel_dp->pps_pipe = crtc->pipe;

	DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
		      pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));

	/* init power sequencer on this pipe and port */
2746 2747
	intel_dp_init_panel_power_sequencer(dev, intel_dp);
	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
2748 2749
}

2750
static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2751
{
2752
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2753
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2754
	struct drm_device *dev = encoder->base.dev;
2755
	struct drm_i915_private *dev_priv = dev->dev_private;
2756
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2757
	enum dpio_channel port = vlv_dport_to_channel(dport);
2758 2759
	int pipe = intel_crtc->pipe;
	u32 val;
2760

V
Ville Syrjälä 已提交
2761
	mutex_lock(&dev_priv->sb_lock);
2762

2763
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2764 2765 2766 2767 2768 2769
	val = 0;
	if (pipe)
		val |= (1<<21);
	else
		val &= ~(1<<21);
	val |= 0x001000c4;
2770 2771 2772
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2773

V
Ville Syrjälä 已提交
2774
	mutex_unlock(&dev_priv->sb_lock);
2775 2776

	intel_enable_dp(encoder);
2777 2778
}

2779
static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2780 2781 2782 2783
{
	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2784 2785
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
2786
	enum dpio_channel port = vlv_dport_to_channel(dport);
2787
	int pipe = intel_crtc->pipe;
2788

2789 2790
	intel_dp_prepare(encoder);

2791
	/* Program Tx lane resets to default */
V
Ville Syrjälä 已提交
2792
	mutex_lock(&dev_priv->sb_lock);
2793
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2794 2795
			 DPIO_PCS_TX_LANE2_RESET |
			 DPIO_PCS_TX_LANE1_RESET);
2796
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2797 2798 2799 2800 2801 2802
			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
			 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
			 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
				 DPIO_PCS_CLK_SOFT_RESET);

	/* Fix up inter-pair skew failure */
2803 2804 2805
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
V
Ville Syrjälä 已提交
2806
	mutex_unlock(&dev_priv->sb_lock);
2807 2808
}

2809 2810 2811 2812 2813 2814 2815 2816 2817 2818
static void chv_pre_enable_dp(struct intel_encoder *encoder)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
	enum dpio_channel ch = vlv_dport_to_channel(dport);
	int pipe = intel_crtc->pipe;
2819
	int data, i, stagger;
2820
	u32 val;
2821

V
Ville Syrjälä 已提交
2822
	mutex_lock(&dev_priv->sb_lock);
2823

2824 2825 2826 2827 2828
	/* allow hardware to manage TX FIFO reset source */
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);

2829 2830 2831 2832 2833
	if (intel_crtc->config->lane_count > 2) {
		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
		val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
	}
2834

2835
	/* Program Tx lane latency optimal setting*/
2836
	for (i = 0; i < intel_crtc->config->lane_count; i++) {
2837
		/* Set the upar bit */
2838 2839 2840 2841
		if (intel_crtc->config->lane_count == 1)
			data = 0x0;
		else
			data = (i == 1) ? 0x0 : 0x1;
2842 2843 2844 2845 2846
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
				data << DPIO_UPAR_SHIFT);
	}

	/* Data lane stagger programming */
2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861
	if (intel_crtc->config->port_clock > 270000)
		stagger = 0x18;
	else if (intel_crtc->config->port_clock > 135000)
		stagger = 0xd;
	else if (intel_crtc->config->port_clock > 67500)
		stagger = 0x7;
	else if (intel_crtc->config->port_clock > 33750)
		stagger = 0x4;
	else
		stagger = 0x2;

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
	val |= DPIO_TX2_STAGGER_MASK(0x1f);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);

2862 2863 2864 2865 2866
	if (intel_crtc->config->lane_count > 2) {
		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
		val |= DPIO_TX2_STAGGER_MASK(0x1f);
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
	}
2867 2868 2869 2870 2871 2872 2873 2874

	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
		       DPIO_LANESTAGGER_STRAP(stagger) |
		       DPIO_LANESTAGGER_STRAP_OVRD |
		       DPIO_TX1_STAGGER_MASK(0x1f) |
		       DPIO_TX1_STAGGER_MULT(6) |
		       DPIO_TX2_STAGGER_MULT(0));

2875 2876 2877 2878 2879 2880 2881 2882
	if (intel_crtc->config->lane_count > 2) {
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
			       DPIO_LANESTAGGER_STRAP(stagger) |
			       DPIO_LANESTAGGER_STRAP_OVRD |
			       DPIO_TX1_STAGGER_MASK(0x1f) |
			       DPIO_TX1_STAGGER_MULT(7) |
			       DPIO_TX2_STAGGER_MULT(5));
	}
2883

2884 2885 2886
	/* Deassert data lane reset */
	chv_data_lane_soft_reset(encoder, false);

V
Ville Syrjälä 已提交
2887
	mutex_unlock(&dev_priv->sb_lock);
2888 2889

	intel_enable_dp(encoder);
2890 2891 2892 2893 2894 2895

	/* Second common lane will stay alive on its own now */
	if (dport->release_cl2_override) {
		chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
		dport->release_cl2_override = false;
	}
2896 2897
}

2898 2899 2900 2901 2902 2903 2904 2905 2906
static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
{
	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
	enum dpio_channel ch = vlv_dport_to_channel(dport);
	enum pipe pipe = intel_crtc->pipe;
2907 2908
	unsigned int lane_mask =
		intel_dp_unused_lane_mask(intel_crtc->config->lane_count);
2909 2910
	u32 val;

2911 2912
	intel_dp_prepare(encoder);

2913 2914 2915 2916 2917 2918 2919 2920
	/*
	 * Must trick the second common lane into life.
	 * Otherwise we can't even access the PLL.
	 */
	if (ch == DPIO_CH0 && pipe == PIPE_B)
		dport->release_cl2_override =
			!chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);

2921 2922
	chv_phy_powergate_lanes(encoder, true, lane_mask);

V
Ville Syrjälä 已提交
2923
	mutex_lock(&dev_priv->sb_lock);
2924

2925 2926 2927
	/* Assert data lane reset */
	chv_data_lane_soft_reset(encoder, true);

2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946
	/* program left/right clock distribution */
	if (pipe != PIPE_B) {
		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
		if (ch == DPIO_CH0)
			val |= CHV_BUFLEFTENA1_FORCE;
		if (ch == DPIO_CH1)
			val |= CHV_BUFRIGHTENA1_FORCE;
		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
	} else {
		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
		if (ch == DPIO_CH0)
			val |= CHV_BUFLEFTENA2_FORCE;
		if (ch == DPIO_CH1)
			val |= CHV_BUFRIGHTENA2_FORCE;
		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
	}

2947 2948 2949 2950 2951 2952 2953 2954 2955
	/* program clock channel usage */
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
	if (pipe != PIPE_B)
		val &= ~CHV_PCS_USEDCLKCHANNEL;
	else
		val |= CHV_PCS_USEDCLKCHANNEL;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);

2956 2957 2958 2959 2960 2961 2962 2963 2964
	if (intel_crtc->config->lane_count > 2) {
		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
		val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
		if (pipe != PIPE_B)
			val &= ~CHV_PCS_USEDCLKCHANNEL;
		else
			val |= CHV_PCS_USEDCLKCHANNEL;
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
	}
2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 2976 2977

	/*
	 * This a a bit weird since generally CL
	 * matches the pipe, but here we need to
	 * pick the CL based on the port.
	 */
	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
	if (pipe != PIPE_B)
		val &= ~CHV_CMN_USEDCLKCHANNEL;
	else
		val |= CHV_CMN_USEDCLKCHANNEL;
	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);

V
Ville Syrjälä 已提交
2978
	mutex_unlock(&dev_priv->sb_lock);
2979 2980
}

2981 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991 2992 2993 2994 2995 2996 2997 2998 2999 3000
static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
	u32 val;

	mutex_lock(&dev_priv->sb_lock);

	/* disable left/right clock distribution */
	if (pipe != PIPE_B) {
		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
	} else {
		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
	}

	mutex_unlock(&dev_priv->sb_lock);
3001

3002 3003 3004 3005 3006 3007 3008 3009 3010
	/*
	 * Leave the power down bit cleared for at least one
	 * lane so that chv_powergate_phy_ch() will power
	 * on something when the channel is otherwise unused.
	 * When the port is off and the override is removed
	 * the lanes power down anyway, so otherwise it doesn't
	 * really matter what the state of power down bits is
	 * after this.
	 */
3011
	chv_phy_powergate_lanes(encoder, false, 0x0);
3012 3013
}

3014
/*
3015 3016
 * Native read with retry for link status and receiver capability reads for
 * cases where the sink may still be asleep.
3017 3018 3019
 *
 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
 * supposed to retry 3 times per the spec.
3020
 */
3021 3022 3023
static ssize_t
intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
			void *buffer, size_t size)
3024
{
3025 3026
	ssize_t ret;
	int i;
3027

3028 3029 3030 3031 3032 3033 3034
	/*
	 * Sometime we just get the same incorrect byte repeated
	 * over the entire buffer. Doing just one throw away read
	 * initially seems to "solve" it.
	 */
	drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);

3035
	for (i = 0; i < 3; i++) {
3036 3037 3038
		ret = drm_dp_dpcd_read(aux, offset, buffer, size);
		if (ret == size)
			return ret;
3039 3040
		msleep(1);
	}
3041

3042
	return ret;
3043 3044 3045 3046 3047 3048 3049
}

/*
 * Fetch AUX CH registers 0x202 - 0x207 which contain
 * link status information
 */
static bool
3050
intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3051
{
3052 3053 3054 3055
	return intel_dp_dpcd_read_wake(&intel_dp->aux,
				       DP_LANE0_1_STATUS,
				       link_status,
				       DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3056 3057
}

3058
/* These are source-specific values. */
3059
static uint8_t
K
Keith Packard 已提交
3060
intel_dp_voltage_max(struct intel_dp *intel_dp)
3061
{
3062
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
3063
	struct drm_i915_private *dev_priv = dev->dev_private;
3064
	enum port port = dp_to_dig_port(intel_dp)->port;
K
Keith Packard 已提交
3065

3066 3067 3068
	if (IS_BROXTON(dev))
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
	else if (INTEL_INFO(dev)->gen >= 9) {
3069
		if (dev_priv->edp_low_vswing && port == PORT_A)
3070
			return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3071
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3072
	} else if (IS_VALLEYVIEW(dev))
3073
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3074
	else if (IS_GEN7(dev) && port == PORT_A)
3075
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3076
	else if (HAS_PCH_CPT(dev) && port != PORT_A)
3077
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
K
Keith Packard 已提交
3078
	else
3079
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
K
Keith Packard 已提交
3080 3081 3082 3083 3084
}

static uint8_t
intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
{
3085
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
3086
	enum port port = dp_to_dig_port(intel_dp)->port;
K
Keith Packard 已提交
3087

3088 3089 3090 3091 3092 3093 3094 3095
	if (INTEL_INFO(dev)->gen >= 9) {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
			return DP_TRAIN_PRE_EMPH_LEVEL_3;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
			return DP_TRAIN_PRE_EMPH_LEVEL_1;
3096 3097
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
3098 3099 3100 3101
		default:
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
		}
	} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3102
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3103 3104 3105 3106 3107 3108 3109
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
			return DP_TRAIN_PRE_EMPH_LEVEL_3;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
			return DP_TRAIN_PRE_EMPH_LEVEL_1;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3110
		default:
3111
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
3112
		}
3113 3114
	} else if (IS_VALLEYVIEW(dev)) {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3115 3116 3117 3118 3119 3120 3121
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
			return DP_TRAIN_PRE_EMPH_LEVEL_3;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
			return DP_TRAIN_PRE_EMPH_LEVEL_1;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3122
		default:
3123
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
3124
		}
3125
	} else if (IS_GEN7(dev) && port == PORT_A) {
K
Keith Packard 已提交
3126
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3127 3128 3129 3130 3131
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
			return DP_TRAIN_PRE_EMPH_LEVEL_1;
K
Keith Packard 已提交
3132
		default:
3133
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
K
Keith Packard 已提交
3134 3135 3136
		}
	} else {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3137 3138 3139 3140 3141 3142 3143
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
			return DP_TRAIN_PRE_EMPH_LEVEL_1;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
K
Keith Packard 已提交
3144
		default:
3145
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
K
Keith Packard 已提交
3146
		}
3147 3148 3149
	}
}

3150
static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3151 3152 3153 3154
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3155 3156
	struct intel_crtc *intel_crtc =
		to_intel_crtc(dport->base.base.crtc);
3157 3158 3159
	unsigned long demph_reg_value, preemph_reg_value,
		uniqtranscale_reg_value;
	uint8_t train_set = intel_dp->train_set[0];
3160
	enum dpio_channel port = vlv_dport_to_channel(dport);
3161
	int pipe = intel_crtc->pipe;
3162 3163

	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3164
	case DP_TRAIN_PRE_EMPH_LEVEL_0:
3165 3166
		preemph_reg_value = 0x0004000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3167
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3168 3169 3170
			demph_reg_value = 0x2B405555;
			uniqtranscale_reg_value = 0x552AB83A;
			break;
3171
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3172 3173 3174
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x5548B83A;
			break;
3175
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3176 3177 3178
			demph_reg_value = 0x2B245555;
			uniqtranscale_reg_value = 0x5560B83A;
			break;
3179
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3180 3181 3182 3183 3184 3185 3186
			demph_reg_value = 0x2B405555;
			uniqtranscale_reg_value = 0x5598DA3A;
			break;
		default:
			return 0;
		}
		break;
3187
	case DP_TRAIN_PRE_EMPH_LEVEL_1:
3188 3189
		preemph_reg_value = 0x0002000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3190
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3191 3192 3193
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x5552B83A;
			break;
3194
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3195 3196 3197
			demph_reg_value = 0x2B404848;
			uniqtranscale_reg_value = 0x5580B83A;
			break;
3198
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3199 3200 3201 3202 3203 3204 3205
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
3206
	case DP_TRAIN_PRE_EMPH_LEVEL_2:
3207 3208
		preemph_reg_value = 0x0000000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3209
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3210 3211 3212
			demph_reg_value = 0x2B305555;
			uniqtranscale_reg_value = 0x5570B83A;
			break;
3213
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3214 3215 3216 3217 3218 3219 3220
			demph_reg_value = 0x2B2B4040;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
3221
	case DP_TRAIN_PRE_EMPH_LEVEL_3:
3222 3223
		preemph_reg_value = 0x0006000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3224
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235
			demph_reg_value = 0x1B405555;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
	default:
		return 0;
	}

V
Ville Syrjälä 已提交
3236
	mutex_lock(&dev_priv->sb_lock);
3237 3238 3239
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
3240
			 uniqtranscale_reg_value);
3241 3242 3243 3244
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
V
Ville Syrjälä 已提交
3245
	mutex_unlock(&dev_priv->sb_lock);
3246 3247 3248 3249

	return 0;
}

3250 3251 3252 3253 3254 3255
static bool chv_need_uniq_trans_scale(uint8_t train_set)
{
	return (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) == DP_TRAIN_PRE_EMPH_LEVEL_0 &&
		(train_set & DP_TRAIN_VOLTAGE_SWING_MASK) == DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
}

3256
static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3257 3258 3259 3260 3261
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
	struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
3262
	u32 deemph_reg_value, margin_reg_value, val;
3263 3264
	uint8_t train_set = intel_dp->train_set[0];
	enum dpio_channel ch = vlv_dport_to_channel(dport);
3265 3266
	enum pipe pipe = intel_crtc->pipe;
	int i;
3267 3268

	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3269
	case DP_TRAIN_PRE_EMPH_LEVEL_0:
3270
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3271
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3272 3273 3274
			deemph_reg_value = 128;
			margin_reg_value = 52;
			break;
3275
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3276 3277 3278
			deemph_reg_value = 128;
			margin_reg_value = 77;
			break;
3279
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3280 3281 3282
			deemph_reg_value = 128;
			margin_reg_value = 102;
			break;
3283
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3284 3285 3286 3287 3288 3289 3290 3291
			deemph_reg_value = 128;
			margin_reg_value = 154;
			/* FIXME extra to set for 1200 */
			break;
		default:
			return 0;
		}
		break;
3292
	case DP_TRAIN_PRE_EMPH_LEVEL_1:
3293
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3294
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3295 3296 3297
			deemph_reg_value = 85;
			margin_reg_value = 78;
			break;
3298
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3299 3300 3301
			deemph_reg_value = 85;
			margin_reg_value = 116;
			break;
3302
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3303 3304 3305 3306 3307 3308 3309
			deemph_reg_value = 85;
			margin_reg_value = 154;
			break;
		default:
			return 0;
		}
		break;
3310
	case DP_TRAIN_PRE_EMPH_LEVEL_2:
3311
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3312
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3313 3314 3315
			deemph_reg_value = 64;
			margin_reg_value = 104;
			break;
3316
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3317 3318 3319 3320 3321 3322 3323
			deemph_reg_value = 64;
			margin_reg_value = 154;
			break;
		default:
			return 0;
		}
		break;
3324
	case DP_TRAIN_PRE_EMPH_LEVEL_3:
3325
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3326
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3327 3328 3329 3330 3331 3332 3333 3334 3335 3336 3337
			deemph_reg_value = 43;
			margin_reg_value = 154;
			break;
		default:
			return 0;
		}
		break;
	default:
		return 0;
	}

V
Ville Syrjälä 已提交
3338
	mutex_lock(&dev_priv->sb_lock);
3339 3340

	/* Clear calc init */
3341 3342
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3343 3344
	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3345 3346
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);

3347 3348 3349 3350 3351 3352 3353
	if (intel_crtc->config->lane_count > 2) {
		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
		val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
		val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
		val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
	}
3354

3355 3356 3357 3358 3359
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);

3360 3361 3362 3363 3364 3365
	if (intel_crtc->config->lane_count > 2) {
		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
		val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
		val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
	}
3366

3367
	/* Program swing deemph */
3368
	for (i = 0; i < intel_crtc->config->lane_count; i++) {
3369 3370 3371 3372 3373
		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
		val &= ~DPIO_SWING_DEEMPH9P5_MASK;
		val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
	}
3374 3375

	/* Program swing margin */
3376
	for (i = 0; i < intel_crtc->config->lane_count; i++) {
3377
		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3378

3379 3380
		val &= ~DPIO_SWING_MARGIN000_MASK;
		val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
3381 3382 3383 3384 3385 3386 3387 3388 3389

		/*
		 * Supposedly this value shouldn't matter when unique transition
		 * scale is disabled, but in fact it does matter. Let's just
		 * always program the same value and hope it's OK.
		 */
		val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
		val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;

3390 3391
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
	}
3392

3393 3394 3395 3396 3397 3398
	/*
	 * The document said it needs to set bit 27 for ch0 and bit 26
	 * for ch1. Might be a typo in the doc.
	 * For now, for this unique transition scale selection, set bit
	 * 27 for ch0 and ch1.
	 */
3399
	for (i = 0; i < intel_crtc->config->lane_count; i++) {
3400
		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3401
		if (chv_need_uniq_trans_scale(train_set))
3402
			val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3403 3404 3405
		else
			val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3406 3407 3408
	}

	/* Start swing calculation */
3409 3410 3411 3412
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);

3413 3414 3415 3416 3417
	if (intel_crtc->config->lane_count > 2) {
		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
		val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
	}
3418

V
Ville Syrjälä 已提交
3419
	mutex_unlock(&dev_priv->sb_lock);
3420 3421 3422 3423

	return 0;
}

3424
static void
J
Jani Nikula 已提交
3425 3426
intel_get_adjust_train(struct intel_dp *intel_dp,
		       const uint8_t link_status[DP_LINK_STATUS_SIZE])
3427 3428 3429 3430
{
	uint8_t v = 0;
	uint8_t p = 0;
	int lane;
K
Keith Packard 已提交
3431 3432
	uint8_t voltage_max;
	uint8_t preemph_max;
3433

3434
	for (lane = 0; lane < intel_dp->lane_count; lane++) {
3435 3436
		uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
		uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
3437 3438 3439 3440 3441 3442 3443

		if (this_v > v)
			v = this_v;
		if (this_p > p)
			p = this_p;
	}

K
Keith Packard 已提交
3444
	voltage_max = intel_dp_voltage_max(intel_dp);
3445 3446
	if (v >= voltage_max)
		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
3447

K
Keith Packard 已提交
3448 3449 3450
	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
	if (p >= preemph_max)
		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
3451 3452

	for (lane = 0; lane < 4; lane++)
3453
		intel_dp->train_set[lane] = v | p;
3454 3455 3456
}

static uint32_t
3457
gen4_signal_levels(uint8_t train_set)
3458
{
3459
	uint32_t	signal_levels = 0;
3460

3461
	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3462
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3463 3464 3465
	default:
		signal_levels |= DP_VOLTAGE_0_4;
		break;
3466
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3467 3468
		signal_levels |= DP_VOLTAGE_0_6;
		break;
3469
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3470 3471
		signal_levels |= DP_VOLTAGE_0_8;
		break;
3472
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3473 3474 3475
		signal_levels |= DP_VOLTAGE_1_2;
		break;
	}
3476
	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3477
	case DP_TRAIN_PRE_EMPH_LEVEL_0:
3478 3479 3480
	default:
		signal_levels |= DP_PRE_EMPHASIS_0;
		break;
3481
	case DP_TRAIN_PRE_EMPH_LEVEL_1:
3482 3483
		signal_levels |= DP_PRE_EMPHASIS_3_5;
		break;
3484
	case DP_TRAIN_PRE_EMPH_LEVEL_2:
3485 3486
		signal_levels |= DP_PRE_EMPHASIS_6;
		break;
3487
	case DP_TRAIN_PRE_EMPH_LEVEL_3:
3488 3489 3490 3491 3492 3493
		signal_levels |= DP_PRE_EMPHASIS_9_5;
		break;
	}
	return signal_levels;
}

3494 3495
/* Gen6's DP voltage swing and pre-emphasis control */
static uint32_t
3496
gen6_edp_signal_levels(uint8_t train_set)
3497
{
3498 3499 3500
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
3501 3502
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3503
		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3504
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3505
		return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3506 3507
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3508
		return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3509 3510
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3511
		return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3512 3513
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3514
		return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3515
	default:
3516 3517 3518
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3519 3520 3521
	}
}

K
Keith Packard 已提交
3522 3523
/* Gen7's DP voltage swing and pre-emphasis control */
static uint32_t
3524
gen7_edp_signal_levels(uint8_t train_set)
K
Keith Packard 已提交
3525 3526 3527 3528
{
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
3529
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
K
Keith Packard 已提交
3530
		return EDP_LINK_TRAIN_400MV_0DB_IVB;
3531
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
K
Keith Packard 已提交
3532
		return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3533
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
K
Keith Packard 已提交
3534 3535
		return EDP_LINK_TRAIN_400MV_6DB_IVB;

3536
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
K
Keith Packard 已提交
3537
		return EDP_LINK_TRAIN_600MV_0DB_IVB;
3538
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
K
Keith Packard 已提交
3539 3540
		return EDP_LINK_TRAIN_600MV_3_5DB_IVB;

3541
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
K
Keith Packard 已提交
3542
		return EDP_LINK_TRAIN_800MV_0DB_IVB;
3543
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
K
Keith Packard 已提交
3544 3545 3546 3547 3548 3549 3550 3551 3552
		return EDP_LINK_TRAIN_800MV_3_5DB_IVB;

	default:
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return EDP_LINK_TRAIN_500MV_0DB_IVB;
	}
}

3553 3554 3555 3556 3557
/* Properly updates "DP" with the correct signal levels. */
static void
intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3558
	enum port port = intel_dig_port->port;
3559
	struct drm_device *dev = intel_dig_port->base.base.dev;
3560
	uint32_t signal_levels, mask = 0;
3561 3562
	uint8_t train_set = intel_dp->train_set[0];

3563 3564 3565 3566 3567 3568 3569
	if (HAS_DDI(dev)) {
		signal_levels = ddi_signal_levels(intel_dp);

		if (IS_BROXTON(dev))
			signal_levels = 0;
		else
			mask = DDI_BUF_EMP_MASK;
3570
	} else if (IS_CHERRYVIEW(dev)) {
3571
		signal_levels = chv_signal_levels(intel_dp);
3572
	} else if (IS_VALLEYVIEW(dev)) {
3573
		signal_levels = vlv_signal_levels(intel_dp);
3574
	} else if (IS_GEN7(dev) && port == PORT_A) {
3575
		signal_levels = gen7_edp_signal_levels(train_set);
3576
		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3577
	} else if (IS_GEN6(dev) && port == PORT_A) {
3578
		signal_levels = gen6_edp_signal_levels(train_set);
3579 3580
		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
	} else {
3581
		signal_levels = gen4_signal_levels(train_set);
3582 3583 3584
		mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
	}

3585 3586 3587 3588 3589 3590 3591 3592
	if (mask)
		DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);

	DRM_DEBUG_KMS("Using vswing level %d\n",
		train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
	DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
		(train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
			DP_TRAIN_PRE_EMPHASIS_SHIFT);
3593 3594 3595 3596

	*DP = (*DP & ~mask) | signal_levels;
}

3597
static bool
C
Chris Wilson 已提交
3598
intel_dp_set_link_train(struct intel_dp *intel_dp,
3599
			uint32_t *DP,
3600
			uint8_t dp_train_pat)
3601
{
3602
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3603 3604
	struct drm_i915_private *dev_priv =
		to_i915(intel_dig_port->base.base.dev);
3605 3606
	uint8_t buf[sizeof(intel_dp->train_set) + 1];
	int ret, len;
3607

3608
	_intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3609

3610
	I915_WRITE(intel_dp->output_reg, *DP);
C
Chris Wilson 已提交
3611
	POSTING_READ(intel_dp->output_reg);
3612

3613 3614
	buf[0] = dp_train_pat;
	if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
3615
	    DP_TRAINING_PATTERN_DISABLE) {
3616 3617 3618 3619
		/* don't write DP_TRAINING_LANEx_SET on disable */
		len = 1;
	} else {
		/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3620 3621
		memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
		len = intel_dp->lane_count + 1;
3622
	}
3623

3624 3625
	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
				buf, len);
3626 3627

	return ret == len;
3628 3629
}

3630 3631 3632 3633
static bool
intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
			uint8_t dp_train_pat)
{
3634 3635
	if (!intel_dp->train_set_valid)
		memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
3636 3637 3638 3639 3640 3641
	intel_dp_set_signal_levels(intel_dp, DP);
	return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
}

static bool
intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
J
Jani Nikula 已提交
3642
			   const uint8_t link_status[DP_LINK_STATUS_SIZE])
3643 3644
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3645 3646
	struct drm_i915_private *dev_priv =
		to_i915(intel_dig_port->base.base.dev);
3647 3648 3649 3650 3651 3652 3653 3654
	int ret;

	intel_get_adjust_train(intel_dp, link_status);
	intel_dp_set_signal_levels(intel_dp, DP);

	I915_WRITE(intel_dp->output_reg, *DP);
	POSTING_READ(intel_dp->output_reg);

3655
	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3656
				intel_dp->train_set, intel_dp->lane_count);
3657

3658
	return ret == intel_dp->lane_count;
3659 3660
}

3661 3662 3663 3664 3665 3666 3667 3668 3669 3670 3671 3672 3673 3674 3675 3676 3677 3678 3679 3680 3681 3682 3683 3684 3685 3686 3687 3688 3689 3690 3691
static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = intel_dig_port->port;
	uint32_t val;

	if (!HAS_DDI(dev))
		return;

	val = I915_READ(DP_TP_CTL(port));
	val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
	val |= DP_TP_CTL_LINK_TRAIN_IDLE;
	I915_WRITE(DP_TP_CTL(port), val);

	/*
	 * On PORT_A we can have only eDP in SST mode. There the only reason
	 * we need to set idle transmission mode is to work around a HW issue
	 * where we enable the pipe while not in idle link-training mode.
	 * In this case there is requirement to wait for a minimum number of
	 * idle patterns to be sent.
	 */
	if (port == PORT_A)
		return;

	if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
		     1))
		DRM_ERROR("Timed out waiting for DP idle patterns\n");
}

3692
/* Enable corresponding port and start training pattern 1 */
3693 3694
static void
intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
3695
{
3696
	struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
3697
	struct drm_device *dev = encoder->dev;
3698 3699
	int i;
	uint8_t voltage;
3700
	int voltage_tries, loop_tries;
C
Chris Wilson 已提交
3701
	uint32_t DP = intel_dp->DP;
3702
	uint8_t link_config[2];
3703
	uint8_t link_bw, rate_select;
3704

P
Paulo Zanoni 已提交
3705
	if (HAS_DDI(dev))
3706 3707
		intel_ddi_prepare_link_retrain(encoder);

3708
	intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
3709 3710
			      &link_bw, &rate_select);

3711
	/* Write the link configuration data */
3712
	link_config[0] = link_bw;
3713
	link_config[1] = intel_dp->lane_count;
3714 3715
	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
3716
	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
3717
	if (intel_dp->num_sink_rates)
3718
		drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
3719
				  &rate_select, 1);
3720 3721 3722

	link_config[0] = 0;
	link_config[1] = DP_SET_ANSI_8B10B;
3723
	drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
3724 3725

	DP |= DP_PORT_EN;
K
Keith Packard 已提交
3726

3727 3728 3729 3730 3731 3732 3733 3734
	/* clock recovery */
	if (!intel_dp_reset_link_train(intel_dp, &DP,
				       DP_TRAINING_PATTERN_1 |
				       DP_LINK_SCRAMBLING_DISABLE)) {
		DRM_ERROR("failed to enable link training\n");
		return;
	}

3735
	voltage = 0xff;
3736 3737
	voltage_tries = 0;
	loop_tries = 0;
3738
	for (;;) {
3739
		uint8_t link_status[DP_LINK_STATUS_SIZE];
3740

3741
		drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
3742 3743
		if (!intel_dp_get_link_status(intel_dp, link_status)) {
			DRM_ERROR("failed to get link status\n");
3744
			break;
3745
		}
3746

3747
		if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3748
			DRM_DEBUG_KMS("clock recovery OK\n");
3749 3750 3751
			break;
		}

3752 3753 3754 3755 3756 3757 3758 3759 3760 3761 3762 3763 3764 3765 3766 3767 3768
		/*
		 * if we used previously trained voltage and pre-emphasis values
		 * and we don't get clock recovery, reset link training values
		 */
		if (intel_dp->train_set_valid) {
			DRM_DEBUG_KMS("clock recovery not ok, reset");
			/* clear the flag as we are not reusing train set */
			intel_dp->train_set_valid = false;
			if (!intel_dp_reset_link_train(intel_dp, &DP,
						       DP_TRAINING_PATTERN_1 |
						       DP_LINK_SCRAMBLING_DISABLE)) {
				DRM_ERROR("failed to enable link training\n");
				return;
			}
			continue;
		}

3769
		/* Check to see if we've tried the max voltage */
3770
		for (i = 0; i < intel_dp->lane_count; i++)
3771
			if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
3772
				break;
3773
		if (i == intel_dp->lane_count) {
3774 3775
			++loop_tries;
			if (loop_tries == 5) {
3776
				DRM_ERROR("too many full retries, give up\n");
3777 3778
				break;
			}
3779 3780 3781
			intel_dp_reset_link_train(intel_dp, &DP,
						  DP_TRAINING_PATTERN_1 |
						  DP_LINK_SCRAMBLING_DISABLE);
3782 3783 3784
			voltage_tries = 0;
			continue;
		}
3785

3786
		/* Check to see if we've tried the same voltage 5 times */
3787
		if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
3788
			++voltage_tries;
3789
			if (voltage_tries == 5) {
3790
				DRM_ERROR("too many voltage retries, give up\n");
3791 3792 3793 3794 3795
				break;
			}
		} else
			voltage_tries = 0;
		voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
3796

3797 3798 3799 3800 3801
		/* Update training set as requested by target */
		if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
			DRM_ERROR("failed to update link training\n");
			break;
		}
3802 3803
	}

3804 3805 3806
	intel_dp->DP = DP;
}

3807 3808
static void
intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
3809
{
3810 3811
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
3812
	bool channel_eq = false;
3813
	int tries, cr_tries;
3814
	uint32_t DP = intel_dp->DP;
3815 3816
	uint32_t training_pattern = DP_TRAINING_PATTERN_2;

3817 3818 3819 3820 3821 3822 3823 3824 3825
	/*
	 * Training Pattern 3 for HBR2 or 1.2 devices that support it.
	 *
	 * Intel platforms that support HBR2 also support TPS3. TPS3 support is
	 * also mandatory for downstream devices that support HBR2.
	 *
	 * Due to WaDisableHBR2 SKL < B0 is the only exception where TPS3 is
	 * supported but still not enabled.
	 */
3826 3827
	if (intel_dp_source_supports_hbr2(dev) &&
	    drm_dp_tps3_supported(intel_dp->dpcd))
3828
		training_pattern = DP_TRAINING_PATTERN_3;
3829 3830
	else if (intel_dp->link_rate == 540000)
		DRM_ERROR("5.4 Gbps link rate without HBR2/TPS3 support\n");
3831

3832
	/* channel equalization */
3833
	if (!intel_dp_set_link_train(intel_dp, &DP,
3834
				     training_pattern |
3835 3836 3837 3838 3839
				     DP_LINK_SCRAMBLING_DISABLE)) {
		DRM_ERROR("failed to start channel equalization\n");
		return;
	}

3840
	tries = 0;
3841
	cr_tries = 0;
3842 3843
	channel_eq = false;
	for (;;) {
3844
		uint8_t link_status[DP_LINK_STATUS_SIZE];
3845

3846 3847 3848 3849 3850
		if (cr_tries > 5) {
			DRM_ERROR("failed to train DP, aborting\n");
			break;
		}

3851
		drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
3852 3853
		if (!intel_dp_get_link_status(intel_dp, link_status)) {
			DRM_ERROR("failed to get link status\n");
3854
			break;
3855
		}
3856

3857
		/* Make sure clock is still ok */
3858
		if (!drm_dp_clock_recovery_ok(link_status,
3859
					      intel_dp->lane_count)) {
3860
			intel_dp->train_set_valid = false;
3861
			intel_dp_link_training_clock_recovery(intel_dp);
3862
			intel_dp_set_link_train(intel_dp, &DP,
3863
						training_pattern |
3864
						DP_LINK_SCRAMBLING_DISABLE);
3865 3866 3867 3868
			cr_tries++;
			continue;
		}

3869
		if (drm_dp_channel_eq_ok(link_status,
3870
					 intel_dp->lane_count)) {
3871 3872 3873
			channel_eq = true;
			break;
		}
3874

3875 3876
		/* Try 5 times, then try clock recovery if that fails */
		if (tries > 5) {
3877
			intel_dp->train_set_valid = false;
3878
			intel_dp_link_training_clock_recovery(intel_dp);
3879
			intel_dp_set_link_train(intel_dp, &DP,
3880
						training_pattern |
3881
						DP_LINK_SCRAMBLING_DISABLE);
3882 3883 3884 3885
			tries = 0;
			cr_tries++;
			continue;
		}
3886

3887 3888 3889 3890 3891
		/* Update training set as requested by target */
		if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
			DRM_ERROR("failed to update link training\n");
			break;
		}
3892
		++tries;
3893
	}
3894

3895 3896 3897 3898
	intel_dp_set_idle_link_train(intel_dp);

	intel_dp->DP = DP;

3899
	if (channel_eq) {
3900
		intel_dp->train_set_valid = true;
M
Masanari Iida 已提交
3901
		DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3902
	}
3903 3904 3905 3906
}

void intel_dp_stop_link_train(struct intel_dp *intel_dp)
{
3907
	intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3908
				DP_TRAINING_PATTERN_DISABLE);
3909 3910
}

3911 3912 3913 3914 3915 3916 3917
void
intel_dp_start_link_train(struct intel_dp *intel_dp)
{
	intel_dp_link_training_clock_recovery(intel_dp);
	intel_dp_link_training_channel_equalization(intel_dp);
}

3918
static void
C
Chris Wilson 已提交
3919
intel_dp_link_down(struct intel_dp *intel_dp)
3920
{
3921
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3922
	struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3923
	enum port port = intel_dig_port->port;
3924
	struct drm_device *dev = intel_dig_port->base.base.dev;
3925
	struct drm_i915_private *dev_priv = dev->dev_private;
C
Chris Wilson 已提交
3926
	uint32_t DP = intel_dp->DP;
3927

3928
	if (WARN_ON(HAS_DDI(dev)))
3929 3930
		return;

3931
	if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3932 3933
		return;

3934
	DRM_DEBUG_KMS("\n");
3935

3936 3937
	if ((IS_GEN7(dev) && port == PORT_A) ||
	    (HAS_PCH_CPT(dev) && port != PORT_A)) {
3938
		DP &= ~DP_LINK_TRAIN_MASK_CPT;
3939
		DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3940
	} else {
3941 3942 3943 3944
		if (IS_CHERRYVIEW(dev))
			DP &= ~DP_LINK_TRAIN_MASK_CHV;
		else
			DP &= ~DP_LINK_TRAIN_MASK;
3945
		DP |= DP_LINK_TRAIN_PAT_IDLE;
3946
	}
3947
	I915_WRITE(intel_dp->output_reg, DP);
3948
	POSTING_READ(intel_dp->output_reg);
3949

3950 3951 3952 3953 3954 3955 3956 3957 3958 3959 3960 3961 3962 3963 3964 3965 3966
	DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
	I915_WRITE(intel_dp->output_reg, DP);
	POSTING_READ(intel_dp->output_reg);

	/*
	 * HW workaround for IBX, we need to move the port
	 * to transcoder A after disabling it to allow the
	 * matching HDMI port to be enabled on transcoder A.
	 */
	if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
		/* always enable with pattern 1 (as per spec) */
		DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
		DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
		I915_WRITE(intel_dp->output_reg, DP);
		POSTING_READ(intel_dp->output_reg);

		DP &= ~DP_PORT_EN;
3967
		I915_WRITE(intel_dp->output_reg, DP);
3968
		POSTING_READ(intel_dp->output_reg);
3969 3970
	}

3971
	msleep(intel_dp->panel_power_down_delay);
3972 3973
}

3974 3975
static bool
intel_dp_get_dpcd(struct intel_dp *intel_dp)
3976
{
R
Rodrigo Vivi 已提交
3977 3978 3979
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
3980
	uint8_t rev;
R
Rodrigo Vivi 已提交
3981

3982 3983
	if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
				    sizeof(intel_dp->dpcd)) < 0)
3984
		return false; /* aux transfer failed */
3985

3986
	DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3987

3988 3989 3990
	if (intel_dp->dpcd[DP_DPCD_REV] == 0)
		return false; /* DPCD not present */

3991 3992
	/* Check if the panel supports PSR */
	memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3993
	if (is_edp(intel_dp)) {
3994 3995 3996
		intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
					intel_dp->psr_dpcd,
					sizeof(intel_dp->psr_dpcd));
R
Rodrigo Vivi 已提交
3997 3998
		if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
			dev_priv->psr.sink_support = true;
3999
			DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
R
Rodrigo Vivi 已提交
4000
		}
4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012 4013 4014 4015

		if (INTEL_INFO(dev)->gen >= 9 &&
			(intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
			uint8_t frame_sync_cap;

			dev_priv->psr.sink_support = true;
			intel_dp_dpcd_read_wake(&intel_dp->aux,
					DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
					&frame_sync_cap, 1);
			dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
			/* PSR2 needs frame sync as well */
			dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
			DRM_DEBUG_KMS("PSR2 %s on sink",
				dev_priv->psr.psr2_support ? "supported" : "not supported");
		}
4016 4017
	}

4018
	DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
4019 4020
		      yesno(intel_dp_source_supports_hbr2(dev)),
		      yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
4021

4022 4023 4024 4025 4026
	/* Intermediate frequency support */
	if (is_edp(intel_dp) &&
	    (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] &	DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
	    (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
	    (rev >= 0x03)) { /* eDp v1.4 or higher */
4027
		__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
4028 4029
		int i;

4030 4031
		intel_dp_dpcd_read_wake(&intel_dp->aux,
				DP_SUPPORTED_LINK_RATES,
4032 4033
				sink_rates,
				sizeof(sink_rates));
4034

4035 4036
		for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
			int val = le16_to_cpu(sink_rates[i]);
4037 4038 4039 4040

			if (val == 0)
				break;

4041 4042
			/* Value read is in kHz while drm clock is saved in deca-kHz */
			intel_dp->sink_rates[i] = (val * 200) / 10;
4043
		}
4044
		intel_dp->num_sink_rates = i;
4045
	}
4046 4047 4048

	intel_dp_print_rates(intel_dp);

4049 4050 4051 4052 4053 4054 4055
	if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
	      DP_DWN_STRM_PORT_PRESENT))
		return true; /* native DP sink */

	if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
		return true; /* no per-port downstream info */

4056 4057 4058
	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
				    intel_dp->downstream_ports,
				    DP_MAX_DOWNSTREAM_PORTS) < 0)
4059 4060 4061
		return false; /* downstream port status fetch failed */

	return true;
4062 4063
}

4064 4065 4066 4067 4068 4069 4070 4071
static void
intel_dp_probe_oui(struct intel_dp *intel_dp)
{
	u8 buf[3];

	if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
		return;

4072
	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
4073 4074 4075
		DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
			      buf[0], buf[1], buf[2]);

4076
	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
4077 4078 4079 4080
		DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
			      buf[0], buf[1], buf[2]);
}

4081 4082 4083 4084 4085 4086 4087 4088 4089 4090 4091 4092 4093 4094 4095 4096 4097 4098 4099 4100 4101 4102 4103 4104 4105
static bool
intel_dp_probe_mst(struct intel_dp *intel_dp)
{
	u8 buf[1];

	if (!intel_dp->can_mst)
		return false;

	if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
		return false;

	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
		if (buf[0] & DP_MST_CAP) {
			DRM_DEBUG_KMS("Sink is MST capable\n");
			intel_dp->is_mst = true;
		} else {
			DRM_DEBUG_KMS("Sink is not MST capable\n");
			intel_dp->is_mst = false;
		}
	}

	drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
	return intel_dp->is_mst;
}

4106
static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
4107
{
4108 4109
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
R
Rodrigo Vivi 已提交
4110
	u8 buf;
4111
	int ret = 0;
4112

4113 4114
	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
		DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
4115 4116
		ret = -EIO;
		goto out;
4117 4118
	}

4119
	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
4120
			       buf & ~DP_TEST_SINK_START) < 0) {
4121
		DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
4122 4123 4124
		ret = -EIO;
		goto out;
	}
4125

4126
	intel_dp->sink_crc.started = false;
4127
 out:
4128
	hsw_enable_ips(intel_crtc);
4129
	return ret;
4130 4131 4132 4133 4134 4135 4136
}

static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
	u8 buf;
4137 4138
	int ret;

4139
	if (intel_dp->sink_crc.started) {
4140 4141 4142 4143
		ret = intel_dp_sink_crc_stop(intel_dp);
		if (ret)
			return ret;
	}
4144 4145 4146 4147 4148 4149 4150

	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
		return -EIO;

	if (!(buf & DP_TEST_CRC_SUPPORTED))
		return -ENOTTY;

4151 4152
	intel_dp->sink_crc.last_count = buf & DP_TEST_COUNT_MASK;

4153 4154 4155 4156
	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
		return -EIO;

	hsw_disable_ips(intel_crtc);
4157

4158
	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
4159 4160 4161
			       buf | DP_TEST_SINK_START) < 0) {
		hsw_enable_ips(intel_crtc);
		return -EIO;
4162 4163
	}

4164
	intel_dp->sink_crc.started = true;
4165 4166 4167 4168 4169 4170 4171 4172 4173
	return 0;
}

int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
	struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
	u8 buf;
4174
	int count, ret;
4175
	int attempts = 6;
4176
	bool old_equal_new;
4177 4178 4179 4180 4181

	ret = intel_dp_sink_crc_start(intel_dp);
	if (ret)
		return ret;

R
Rodrigo Vivi 已提交
4182
	do {
4183 4184
		intel_wait_for_vblank(dev, intel_crtc->pipe);

4185
		if (drm_dp_dpcd_readb(&intel_dp->aux,
4186 4187
				      DP_TEST_SINK_MISC, &buf) < 0) {
			ret = -EIO;
4188
			goto stop;
4189
		}
4190
		count = buf & DP_TEST_COUNT_MASK;
4191

4192 4193 4194 4195 4196 4197 4198 4199 4200 4201 4202
		/*
		 * Count might be reset during the loop. In this case
		 * last known count needs to be reset as well.
		 */
		if (count == 0)
			intel_dp->sink_crc.last_count = 0;

		if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
			ret = -EIO;
			goto stop;
		}
4203 4204 4205 4206 4207 4208

		old_equal_new = (count == intel_dp->sink_crc.last_count &&
				 !memcmp(intel_dp->sink_crc.last_crc, crc,
					 6 * sizeof(u8)));

	} while (--attempts && (count == 0 || old_equal_new));
4209 4210 4211

	intel_dp->sink_crc.last_count = buf & DP_TEST_COUNT_MASK;
	memcpy(intel_dp->sink_crc.last_crc, crc, 6 * sizeof(u8));
R
Rodrigo Vivi 已提交
4212 4213

	if (attempts == 0) {
4214 4215 4216 4217 4218 4219 4220
		if (old_equal_new) {
			DRM_DEBUG_KMS("Unreliable Sink CRC counter: Current returned CRC is identical to the previous one\n");
		} else {
			DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
			ret = -ETIMEDOUT;
			goto stop;
		}
R
Rodrigo Vivi 已提交
4221
	}
4222

4223
stop:
4224
	intel_dp_sink_crc_stop(intel_dp);
4225
	return ret;
4226 4227
}

4228 4229 4230
static bool
intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
{
4231 4232 4233
	return intel_dp_dpcd_read_wake(&intel_dp->aux,
				       DP_DEVICE_SERVICE_IRQ_VECTOR,
				       sink_irq_vector, 1) == 1;
4234 4235
}

4236 4237 4238 4239 4240 4241 4242 4243 4244 4245 4246 4247 4248 4249
static bool
intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
{
	int ret;

	ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
					     DP_SINK_COUNT_ESI,
					     sink_irq_vector, 14);
	if (ret != 14)
		return false;

	return true;
}

4250 4251 4252 4253 4254 4255 4256 4257 4258 4259 4260 4261 4262
static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
{
	uint8_t test_result = DP_TEST_ACK;
	return test_result;
}

static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
{
	uint8_t test_result = DP_TEST_NAK;
	return test_result;
}

static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4263
{
4264
	uint8_t test_result = DP_TEST_NAK;
4265 4266 4267 4268
	struct intel_connector *intel_connector = intel_dp->attached_connector;
	struct drm_connector *connector = &intel_connector->base;

	if (intel_connector->detect_edid == NULL ||
4269
	    connector->edid_corrupt ||
4270 4271 4272 4273 4274 4275 4276 4277 4278 4279 4280 4281 4282 4283 4284
	    intel_dp->aux.i2c_defer_count > 6) {
		/* Check EDID read for NACKs, DEFERs and corruption
		 * (DP CTS 1.2 Core r1.1)
		 *    4.2.2.4 : Failed EDID read, I2C_NAK
		 *    4.2.2.5 : Failed EDID read, I2C_DEFER
		 *    4.2.2.6 : EDID corruption detected
		 * Use failsafe mode for all cases
		 */
		if (intel_dp->aux.i2c_nack_count > 0 ||
			intel_dp->aux.i2c_defer_count > 0)
			DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
				      intel_dp->aux.i2c_nack_count,
				      intel_dp->aux.i2c_defer_count);
		intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
	} else {
4285 4286 4287 4288 4289 4290 4291
		struct edid *block = intel_connector->detect_edid;

		/* We have to write the checksum
		 * of the last block read
		 */
		block += intel_connector->detect_edid->extensions;

4292 4293
		if (!drm_dp_dpcd_write(&intel_dp->aux,
					DP_TEST_EDID_CHECKSUM,
4294
					&block->checksum,
D
Dan Carpenter 已提交
4295
					1))
4296 4297 4298 4299 4300 4301 4302 4303 4304
			DRM_DEBUG_KMS("Failed to write EDID checksum\n");

		test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
		intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
	}

	/* Set test active flag here so userspace doesn't interrupt things */
	intel_dp->compliance_test_active = 1;

4305 4306 4307 4308
	return test_result;
}

static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4309
{
4310 4311 4312 4313 4314 4315 4316 4317 4318 4319
	uint8_t test_result = DP_TEST_NAK;
	return test_result;
}

static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
{
	uint8_t response = DP_TEST_NAK;
	uint8_t rxdata = 0;
	int status = 0;

4320
	intel_dp->compliance_test_active = 0;
4321
	intel_dp->compliance_test_type = 0;
4322 4323
	intel_dp->compliance_test_data = 0;

4324 4325 4326 4327 4328 4329 4330 4331 4332 4333 4334 4335 4336 4337 4338 4339 4340 4341 4342 4343 4344 4345 4346 4347 4348 4349 4350 4351 4352 4353 4354 4355 4356 4357 4358 4359 4360 4361 4362 4363 4364
	intel_dp->aux.i2c_nack_count = 0;
	intel_dp->aux.i2c_defer_count = 0;

	status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
	if (status <= 0) {
		DRM_DEBUG_KMS("Could not read test request from sink\n");
		goto update_status;
	}

	switch (rxdata) {
	case DP_TEST_LINK_TRAINING:
		DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
		intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
		response = intel_dp_autotest_link_training(intel_dp);
		break;
	case DP_TEST_LINK_VIDEO_PATTERN:
		DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
		intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
		response = intel_dp_autotest_video_pattern(intel_dp);
		break;
	case DP_TEST_LINK_EDID_READ:
		DRM_DEBUG_KMS("EDID test requested\n");
		intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
		response = intel_dp_autotest_edid(intel_dp);
		break;
	case DP_TEST_LINK_PHY_TEST_PATTERN:
		DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
		intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
		response = intel_dp_autotest_phy_pattern(intel_dp);
		break;
	default:
		DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
		break;
	}

update_status:
	status = drm_dp_dpcd_write(&intel_dp->aux,
				   DP_TEST_RESPONSE,
				   &response, 1);
	if (status <= 0)
		DRM_DEBUG_KMS("Could not write test response to sink\n");
4365 4366
}

4367 4368 4369 4370 4371 4372 4373 4374 4375 4376 4377 4378 4379 4380 4381
static int
intel_dp_check_mst_status(struct intel_dp *intel_dp)
{
	bool bret;

	if (intel_dp->is_mst) {
		u8 esi[16] = { 0 };
		int ret = 0;
		int retry;
		bool handled;
		bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
go_again:
		if (bret == true) {

			/* check link status - esi[10] = 0x200c */
4382
			if (intel_dp->active_mst_links &&
4383
			    !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4384 4385 4386 4387 4388
				DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
				intel_dp_start_link_train(intel_dp);
				intel_dp_stop_link_train(intel_dp);
			}

4389
			DRM_DEBUG_KMS("got esi %3ph\n", esi);
4390 4391 4392 4393 4394 4395 4396 4397 4398 4399 4400 4401 4402 4403 4404
			ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);

			if (handled) {
				for (retry = 0; retry < 3; retry++) {
					int wret;
					wret = drm_dp_dpcd_write(&intel_dp->aux,
								 DP_SINK_COUNT_ESI+1,
								 &esi[1], 3);
					if (wret == 3) {
						break;
					}
				}

				bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
				if (bret == true) {
4405
					DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4406 4407 4408 4409 4410 4411 4412 4413 4414 4415 4416 4417 4418 4419 4420 4421 4422 4423
					goto go_again;
				}
			} else
				ret = 0;

			return ret;
		} else {
			struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
			DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
			intel_dp->is_mst = false;
			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
			/* send a hotplug event */
			drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
		}
	}
	return -EINVAL;
}

4424 4425 4426 4427 4428 4429 4430 4431
/*
 * According to DP spec
 * 5.1.2:
 *  1. Read DPCD
 *  2. Configure link according to Receiver Capabilities
 *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
 *  4. Check link status on receipt of hot-plug interrupt
 */
4432
static void
C
Chris Wilson 已提交
4433
intel_dp_check_link_status(struct intel_dp *intel_dp)
4434
{
4435
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
4436
	struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4437
	u8 sink_irq_vector;
4438
	u8 link_status[DP_LINK_STATUS_SIZE];
4439

4440 4441
	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));

4442
	if (!intel_encoder->base.crtc)
4443 4444
		return;

4445 4446 4447
	if (!to_intel_crtc(intel_encoder->base.crtc)->active)
		return;

4448
	/* Try to read receiver status if the link appears to be up */
4449
	if (!intel_dp_get_link_status(intel_dp, link_status)) {
4450 4451 4452
		return;
	}

4453
	/* Now read the DPCD to see if it's actually running */
4454
	if (!intel_dp_get_dpcd(intel_dp)) {
4455 4456 4457
		return;
	}

4458 4459 4460 4461
	/* Try to read the source of the interrupt */
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
		/* Clear interrupt source */
4462 4463 4464
		drm_dp_dpcd_writeb(&intel_dp->aux,
				   DP_DEVICE_SERVICE_IRQ_VECTOR,
				   sink_irq_vector);
4465 4466

		if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4467
			DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
4468 4469 4470 4471
		if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
			DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
	}

4472
	if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
4473
		DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4474
			      intel_encoder->base.name);
4475
		intel_dp_start_link_train(intel_dp);
4476
		intel_dp_stop_link_train(intel_dp);
4477
	}
4478 4479
}

4480
/* XXX this is probably wrong for multiple downstream ports */
4481
static enum drm_connector_status
4482
intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4483
{
4484 4485 4486 4487 4488 4489 4490 4491
	uint8_t *dpcd = intel_dp->dpcd;
	uint8_t type;

	if (!intel_dp_get_dpcd(intel_dp))
		return connector_status_disconnected;

	/* if there's no downstream port, we're done */
	if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
4492
		return connector_status_connected;
4493 4494

	/* If we're HPD-aware, SINK_COUNT changes dynamically */
4495 4496
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4497
		uint8_t reg;
4498 4499 4500

		if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
					    &reg, 1) < 0)
4501
			return connector_status_unknown;
4502

4503 4504
		return DP_GET_SINK_COUNT(reg) ? connector_status_connected
					      : connector_status_disconnected;
4505 4506 4507
	}

	/* If no HPD, poke DDC gently */
4508
	if (drm_probe_ddc(&intel_dp->aux.ddc))
4509
		return connector_status_connected;
4510 4511

	/* Well we tried, say unknown for unreliable port types */
4512 4513 4514 4515 4516 4517 4518 4519 4520 4521 4522 4523
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
		type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
		if (type == DP_DS_PORT_TYPE_VGA ||
		    type == DP_DS_PORT_TYPE_NON_EDID)
			return connector_status_unknown;
	} else {
		type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
			DP_DWN_STRM_PORT_TYPE_MASK;
		if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
		    type == DP_DWN_STRM_PORT_TYPE_OTHER)
			return connector_status_unknown;
	}
4524 4525 4526

	/* Anything else is out of spec, warn and ignore */
	DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4527
	return connector_status_disconnected;
4528 4529
}

4530 4531 4532 4533 4534 4535 4536 4537 4538 4539 4540 4541 4542
static enum drm_connector_status
edp_detect(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	enum drm_connector_status status;

	status = intel_panel_detect(dev);
	if (status == connector_status_unknown)
		status = connector_status_connected;

	return status;
}

4543 4544
static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
				       struct intel_digital_port *port)
4545
{
4546
	u32 bit;
4547

4548 4549 4550 4551 4552 4553 4554 4555 4556 4557 4558 4559 4560 4561 4562 4563 4564 4565 4566 4567 4568 4569 4570 4571 4572 4573 4574 4575 4576 4577 4578 4579 4580 4581 4582 4583 4584
	switch (port->port) {
	case PORT_A:
		return true;
	case PORT_B:
		bit = SDE_PORTB_HOTPLUG;
		break;
	case PORT_C:
		bit = SDE_PORTC_HOTPLUG;
		break;
	case PORT_D:
		bit = SDE_PORTD_HOTPLUG;
		break;
	default:
		MISSING_CASE(port->port);
		return false;
	}

	return I915_READ(SDEISR) & bit;
}

static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
				       struct intel_digital_port *port)
{
	u32 bit;

	switch (port->port) {
	case PORT_A:
		return true;
	case PORT_B:
		bit = SDE_PORTB_HOTPLUG_CPT;
		break;
	case PORT_C:
		bit = SDE_PORTC_HOTPLUG_CPT;
		break;
	case PORT_D:
		bit = SDE_PORTD_HOTPLUG_CPT;
		break;
4585 4586 4587
	case PORT_E:
		bit = SDE_PORTE_HOTPLUG_SPT;
		break;
4588 4589 4590
	default:
		MISSING_CASE(port->port);
		return false;
4591
	}
4592

4593
	return I915_READ(SDEISR) & bit;
4594 4595
}

4596
static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
4597
				       struct intel_digital_port *port)
4598
{
4599
	u32 bit;
4600

4601 4602 4603 4604 4605 4606 4607 4608 4609 4610 4611 4612 4613 4614 4615 4616 4617 4618 4619 4620 4621 4622 4623 4624 4625 4626 4627 4628 4629 4630 4631 4632 4633 4634 4635 4636
	switch (port->port) {
	case PORT_B:
		bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
		break;
	case PORT_C:
		bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
		break;
	case PORT_D:
		bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
		break;
	default:
		MISSING_CASE(port->port);
		return false;
	}

	return I915_READ(PORT_HOTPLUG_STAT) & bit;
}

static bool vlv_digital_port_connected(struct drm_i915_private *dev_priv,
				       struct intel_digital_port *port)
{
	u32 bit;

	switch (port->port) {
	case PORT_B:
		bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
		break;
	case PORT_C:
		bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
		break;
	case PORT_D:
		bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
		break;
	default:
		MISSING_CASE(port->port);
		return false;
4637 4638
	}

4639
	return I915_READ(PORT_HOTPLUG_STAT) & bit;
4640 4641
}

4642
static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
4643
				       struct intel_digital_port *intel_dig_port)
4644
{
4645 4646
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	enum port port;
4647 4648
	u32 bit;

4649 4650
	intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
	switch (port) {
4651 4652 4653 4654 4655 4656 4657 4658 4659 4660
	case PORT_A:
		bit = BXT_DE_PORT_HP_DDIA;
		break;
	case PORT_B:
		bit = BXT_DE_PORT_HP_DDIB;
		break;
	case PORT_C:
		bit = BXT_DE_PORT_HP_DDIC;
		break;
	default:
4661
		MISSING_CASE(port);
4662 4663 4664 4665 4666 4667
		return false;
	}

	return I915_READ(GEN8_DE_PORT_ISR) & bit;
}

4668 4669 4670 4671 4672 4673 4674
/*
 * intel_digital_port_connected - is the specified port connected?
 * @dev_priv: i915 private structure
 * @port: the port to test
 *
 * Return %true if @port is connected, %false otherwise.
 */
4675
bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
4676 4677
					 struct intel_digital_port *port)
{
4678
	if (HAS_PCH_IBX(dev_priv))
4679
		return ibx_digital_port_connected(dev_priv, port);
4680 4681
	if (HAS_PCH_SPLIT(dev_priv))
		return cpt_digital_port_connected(dev_priv, port);
4682 4683
	else if (IS_BROXTON(dev_priv))
		return bxt_digital_port_connected(dev_priv, port);
4684 4685
	else if (IS_VALLEYVIEW(dev_priv))
		return vlv_digital_port_connected(dev_priv, port);
4686 4687 4688 4689
	else
		return g4x_digital_port_connected(dev_priv, port);
}

4690 4691 4692 4693 4694 4695 4696
static enum drm_connector_status
ironlake_dp_detect(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

4697
	if (!intel_digital_port_connected(dev_priv, intel_dig_port))
4698 4699 4700 4701 4702
		return connector_status_disconnected;

	return intel_dp_detect_dpcd(intel_dp);
}

4703 4704 4705 4706 4707 4708 4709 4710 4711 4712 4713 4714 4715 4716 4717 4718
static enum drm_connector_status
g4x_dp_detect(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	/* Can't disconnect eDP, but you can close the lid... */
	if (is_edp(intel_dp)) {
		enum drm_connector_status status;

		status = intel_panel_detect(dev);
		if (status == connector_status_unknown)
			status = connector_status_connected;
		return status;
	}

4719
	if (!intel_digital_port_connected(dev->dev_private, intel_dig_port))
4720 4721
		return connector_status_disconnected;

4722
	return intel_dp_detect_dpcd(intel_dp);
Z
Zhenyu Wang 已提交
4723 4724
}

4725
static struct edid *
4726
intel_dp_get_edid(struct intel_dp *intel_dp)
4727
{
4728
	struct intel_connector *intel_connector = intel_dp->attached_connector;
4729

4730 4731 4732 4733
	/* use cached edid if we have one */
	if (intel_connector->edid) {
		/* invalid edid */
		if (IS_ERR(intel_connector->edid))
4734 4735
			return NULL;

J
Jani Nikula 已提交
4736
		return drm_edid_duplicate(intel_connector->edid);
4737 4738 4739 4740
	} else
		return drm_get_edid(&intel_connector->base,
				    &intel_dp->aux.ddc);
}
4741

4742 4743 4744 4745 4746
static void
intel_dp_set_edid(struct intel_dp *intel_dp)
{
	struct intel_connector *intel_connector = intel_dp->attached_connector;
	struct edid *edid;
4747

4748 4749 4750 4751 4752 4753 4754
	edid = intel_dp_get_edid(intel_dp);
	intel_connector->detect_edid = edid;

	if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
		intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
	else
		intel_dp->has_audio = drm_detect_monitor_audio(edid);
4755 4756
}

4757 4758
static void
intel_dp_unset_edid(struct intel_dp *intel_dp)
4759
{
4760
	struct intel_connector *intel_connector = intel_dp->attached_connector;
4761

4762 4763
	kfree(intel_connector->detect_edid);
	intel_connector->detect_edid = NULL;
4764

4765 4766
	intel_dp->has_audio = false;
}
4767

4768 4769 4770 4771 4772 4773 4774 4775 4776 4777 4778
static enum intel_display_power_domain
intel_dp_power_get(struct intel_dp *dp)
{
	struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
	enum intel_display_power_domain power_domain;

	power_domain = intel_display_port_power_domain(encoder);
	intel_display_power_get(to_i915(encoder->base.dev), power_domain);

	return power_domain;
}
4779

4780 4781 4782 4783 4784 4785
static void
intel_dp_power_put(struct intel_dp *dp,
		   enum intel_display_power_domain power_domain)
{
	struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
	intel_display_power_put(to_i915(encoder->base.dev), power_domain);
4786 4787
}

Z
Zhenyu Wang 已提交
4788 4789 4790 4791
static enum drm_connector_status
intel_dp_detect(struct drm_connector *connector, bool force)
{
	struct intel_dp *intel_dp = intel_attached_dp(connector);
4792 4793
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
4794
	struct drm_device *dev = connector->dev;
Z
Zhenyu Wang 已提交
4795
	enum drm_connector_status status;
4796
	enum intel_display_power_domain power_domain;
4797
	bool ret;
4798
	u8 sink_irq_vector;
Z
Zhenyu Wang 已提交
4799

4800
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4801
		      connector->base.id, connector->name);
4802
	intel_dp_unset_edid(intel_dp);
4803

4804 4805 4806 4807
	if (intel_dp->is_mst) {
		/* MST devices are disconnected from a monitor POV */
		if (intel_encoder->type != INTEL_OUTPUT_EDP)
			intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4808
		return connector_status_disconnected;
4809 4810
	}

4811
	power_domain = intel_dp_power_get(intel_dp);
Z
Zhenyu Wang 已提交
4812

4813 4814 4815 4816
	/* Can't disconnect eDP, but you can close the lid... */
	if (is_edp(intel_dp))
		status = edp_detect(intel_dp);
	else if (HAS_PCH_SPLIT(dev))
Z
Zhenyu Wang 已提交
4817 4818 4819 4820
		status = ironlake_dp_detect(intel_dp);
	else
		status = g4x_dp_detect(intel_dp);
	if (status != connector_status_connected)
4821
		goto out;
Z
Zhenyu Wang 已提交
4822

4823 4824
	intel_dp_probe_oui(intel_dp);

4825 4826 4827 4828 4829 4830 4831 4832 4833 4834
	ret = intel_dp_probe_mst(intel_dp);
	if (ret) {
		/* if we are in MST mode then this connector
		   won't appear connected or have anything with EDID on it */
		if (intel_encoder->type != INTEL_OUTPUT_EDP)
			intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
		status = connector_status_disconnected;
		goto out;
	}

4835
	intel_dp_set_edid(intel_dp);
Z
Zhenyu Wang 已提交
4836

4837 4838
	if (intel_encoder->type != INTEL_OUTPUT_EDP)
		intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4839 4840
	status = connector_status_connected;

4841 4842 4843 4844 4845 4846 4847 4848 4849 4850 4851 4852 4853 4854
	/* Try to read the source of the interrupt */
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
		/* Clear interrupt source */
		drm_dp_dpcd_writeb(&intel_dp->aux,
				   DP_DEVICE_SERVICE_IRQ_VECTOR,
				   sink_irq_vector);

		if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
			intel_dp_handle_test_request(intel_dp);
		if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
			DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
	}

4855
out:
4856
	intel_dp_power_put(intel_dp, power_domain);
4857
	return status;
4858 4859
}

4860 4861
static void
intel_dp_force(struct drm_connector *connector)
4862
{
4863
	struct intel_dp *intel_dp = intel_attached_dp(connector);
4864
	struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4865
	enum intel_display_power_domain power_domain;
4866

4867 4868 4869
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
		      connector->base.id, connector->name);
	intel_dp_unset_edid(intel_dp);
4870

4871 4872
	if (connector->status != connector_status_connected)
		return;
4873

4874 4875 4876 4877 4878 4879 4880 4881 4882 4883 4884 4885 4886 4887 4888 4889 4890 4891 4892 4893 4894
	power_domain = intel_dp_power_get(intel_dp);

	intel_dp_set_edid(intel_dp);

	intel_dp_power_put(intel_dp, power_domain);

	if (intel_encoder->type != INTEL_OUTPUT_EDP)
		intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
}

static int intel_dp_get_modes(struct drm_connector *connector)
{
	struct intel_connector *intel_connector = to_intel_connector(connector);
	struct edid *edid;

	edid = intel_connector->detect_edid;
	if (edid) {
		int ret = intel_connector_update_modes(connector, edid);
		if (ret)
			return ret;
	}
4895

4896
	/* if eDP has no EDID, fall back to fixed mode */
4897 4898
	if (is_edp(intel_attached_dp(connector)) &&
	    intel_connector->panel.fixed_mode) {
4899
		struct drm_display_mode *mode;
4900 4901

		mode = drm_mode_duplicate(connector->dev,
4902
					  intel_connector->panel.fixed_mode);
4903
		if (mode) {
4904 4905 4906 4907
			drm_mode_probed_add(connector, mode);
			return 1;
		}
	}
4908

4909
	return 0;
4910 4911
}

4912 4913 4914 4915
static bool
intel_dp_detect_audio(struct drm_connector *connector)
{
	bool has_audio = false;
4916
	struct edid *edid;
4917

4918 4919
	edid = to_intel_connector(connector)->detect_edid;
	if (edid)
4920
		has_audio = drm_detect_monitor_audio(edid);
4921

4922 4923 4924
	return has_audio;
}

4925 4926 4927 4928 4929
static int
intel_dp_set_property(struct drm_connector *connector,
		      struct drm_property *property,
		      uint64_t val)
{
4930
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
4931
	struct intel_connector *intel_connector = to_intel_connector(connector);
4932 4933
	struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4934 4935
	int ret;

4936
	ret = drm_object_property_set_value(&connector->base, property, val);
4937 4938 4939
	if (ret)
		return ret;

4940
	if (property == dev_priv->force_audio_property) {
4941 4942 4943 4944
		int i = val;
		bool has_audio;

		if (i == intel_dp->force_audio)
4945 4946
			return 0;

4947
		intel_dp->force_audio = i;
4948

4949
		if (i == HDMI_AUDIO_AUTO)
4950 4951
			has_audio = intel_dp_detect_audio(connector);
		else
4952
			has_audio = (i == HDMI_AUDIO_ON);
4953 4954

		if (has_audio == intel_dp->has_audio)
4955 4956
			return 0;

4957
		intel_dp->has_audio = has_audio;
4958 4959 4960
		goto done;
	}

4961
	if (property == dev_priv->broadcast_rgb_property) {
4962
		bool old_auto = intel_dp->color_range_auto;
4963
		bool old_range = intel_dp->limited_color_range;
4964

4965 4966 4967 4968 4969 4970
		switch (val) {
		case INTEL_BROADCAST_RGB_AUTO:
			intel_dp->color_range_auto = true;
			break;
		case INTEL_BROADCAST_RGB_FULL:
			intel_dp->color_range_auto = false;
4971
			intel_dp->limited_color_range = false;
4972 4973 4974
			break;
		case INTEL_BROADCAST_RGB_LIMITED:
			intel_dp->color_range_auto = false;
4975
			intel_dp->limited_color_range = true;
4976 4977 4978 4979
			break;
		default:
			return -EINVAL;
		}
4980 4981

		if (old_auto == intel_dp->color_range_auto &&
4982
		    old_range == intel_dp->limited_color_range)
4983 4984
			return 0;

4985 4986 4987
		goto done;
	}

4988 4989 4990 4991 4992 4993 4994 4995 4996 4997 4998 4999 5000 5001 5002 5003
	if (is_edp(intel_dp) &&
	    property == connector->dev->mode_config.scaling_mode_property) {
		if (val == DRM_MODE_SCALE_NONE) {
			DRM_DEBUG_KMS("no scaling not supported\n");
			return -EINVAL;
		}

		if (intel_connector->panel.fitting_mode == val) {
			/* the eDP scaling property is not changed */
			return 0;
		}
		intel_connector->panel.fitting_mode = val;

		goto done;
	}

5004 5005 5006
	return -EINVAL;

done:
5007 5008
	if (intel_encoder->base.crtc)
		intel_crtc_restore_mode(intel_encoder->base.crtc);
5009 5010 5011 5012

	return 0;
}

5013
static void
5014
intel_dp_connector_destroy(struct drm_connector *connector)
5015
{
5016
	struct intel_connector *intel_connector = to_intel_connector(connector);
5017

5018
	kfree(intel_connector->detect_edid);
5019

5020 5021 5022
	if (!IS_ERR_OR_NULL(intel_connector->edid))
		kfree(intel_connector->edid);

5023 5024 5025
	/* Can't call is_edp() since the encoder may have been destroyed
	 * already. */
	if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5026
		intel_panel_fini(&intel_connector->panel);
5027

5028
	drm_connector_cleanup(connector);
5029
	kfree(connector);
5030 5031
}

P
Paulo Zanoni 已提交
5032
void intel_dp_encoder_destroy(struct drm_encoder *encoder)
5033
{
5034 5035
	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
	struct intel_dp *intel_dp = &intel_dig_port->dp;
5036

5037
	drm_dp_aux_unregister(&intel_dp->aux);
5038
	intel_dp_mst_encoder_cleanup(intel_dig_port);
5039 5040
	if (is_edp(intel_dp)) {
		cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5041 5042 5043 5044
		/*
		 * vdd might still be enabled do to the delayed vdd off.
		 * Make sure vdd is actually turned off here.
		 */
5045
		pps_lock(intel_dp);
5046
		edp_panel_vdd_off_sync(intel_dp);
5047 5048
		pps_unlock(intel_dp);

5049 5050 5051 5052
		if (intel_dp->edp_notifier.notifier_call) {
			unregister_reboot_notifier(&intel_dp->edp_notifier);
			intel_dp->edp_notifier.notifier_call = NULL;
		}
5053
	}
5054
	drm_encoder_cleanup(encoder);
5055
	kfree(intel_dig_port);
5056 5057
}

5058 5059 5060 5061 5062 5063 5064
static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);

	if (!is_edp(intel_dp))
		return;

5065 5066 5067 5068
	/*
	 * vdd might still be enabled do to the delayed vdd off.
	 * Make sure vdd is actually turned off here.
	 */
5069
	cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5070
	pps_lock(intel_dp);
5071
	edp_panel_vdd_off_sync(intel_dp);
5072
	pps_unlock(intel_dp);
5073 5074
}

5075 5076 5077 5078 5079 5080 5081 5082 5083 5084 5085 5086 5087 5088 5089 5090 5091 5092 5093 5094 5095 5096 5097 5098 5099
static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum intel_display_power_domain power_domain;

	lockdep_assert_held(&dev_priv->pps_mutex);

	if (!edp_have_panel_vdd(intel_dp))
		return;

	/*
	 * The VDD bit needs a power domain reference, so if the bit is
	 * already enabled when we boot or resume, grab this reference and
	 * schedule a vdd off, so we don't hold on to the reference
	 * indefinitely.
	 */
	DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
	power_domain = intel_display_port_power_domain(&intel_dig_port->base);
	intel_display_power_get(dev_priv, power_domain);

	edp_panel_vdd_schedule_off(intel_dp);
}

5100 5101
static void intel_dp_encoder_reset(struct drm_encoder *encoder)
{
5102 5103 5104 5105 5106 5107 5108 5109 5110 5111 5112 5113 5114 5115 5116 5117 5118 5119 5120
	struct intel_dp *intel_dp;

	if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
		return;

	intel_dp = enc_to_intel_dp(encoder);

	pps_lock(intel_dp);

	/*
	 * Read out the current power sequencer assignment,
	 * in case the BIOS did something with it.
	 */
	if (IS_VALLEYVIEW(encoder->dev))
		vlv_initial_power_sequencer_setup(intel_dp);

	intel_edp_panel_vdd_sanitize(intel_dp);

	pps_unlock(intel_dp);
5121 5122
}

5123
static const struct drm_connector_funcs intel_dp_connector_funcs = {
5124
	.dpms = drm_atomic_helper_connector_dpms,
5125
	.detect = intel_dp_detect,
5126
	.force = intel_dp_force,
5127
	.fill_modes = drm_helper_probe_single_connector_modes,
5128
	.set_property = intel_dp_set_property,
5129
	.atomic_get_property = intel_connector_atomic_get_property,
5130
	.destroy = intel_dp_connector_destroy,
5131
	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5132
	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
5133 5134 5135 5136 5137
};

static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
	.get_modes = intel_dp_get_modes,
	.mode_valid = intel_dp_mode_valid,
5138
	.best_encoder = intel_best_encoder,
5139 5140 5141
};

static const struct drm_encoder_funcs intel_dp_enc_funcs = {
5142
	.reset = intel_dp_encoder_reset,
5143
	.destroy = intel_dp_encoder_destroy,
5144 5145
};

5146
enum irqreturn
5147 5148 5149
intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
{
	struct intel_dp *intel_dp = &intel_dig_port->dp;
5150
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
5151 5152
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
5153
	enum intel_display_power_domain power_domain;
5154
	enum irqreturn ret = IRQ_NONE;
5155

5156 5157
	if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
		intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
5158

5159 5160 5161 5162 5163 5164 5165 5166 5167
	if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
		/*
		 * vdd off can generate a long pulse on eDP which
		 * would require vdd on to handle it, and thus we
		 * would end up in an endless cycle of
		 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
		 */
		DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
			      port_name(intel_dig_port->port));
5168
		return IRQ_HANDLED;
5169 5170
	}

5171 5172
	DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
		      port_name(intel_dig_port->port),
5173
		      long_hpd ? "long" : "short");
5174

5175 5176 5177
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_get(dev_priv, power_domain);

5178
	if (long_hpd) {
5179 5180
		/* indicate that we need to restart link training */
		intel_dp->train_set_valid = false;
5181

5182 5183
		if (!intel_digital_port_connected(dev_priv, intel_dig_port))
			goto mst_fail;
5184 5185 5186 5187 5188 5189 5190

		if (!intel_dp_get_dpcd(intel_dp)) {
			goto mst_fail;
		}

		intel_dp_probe_oui(intel_dp);

5191 5192 5193 5194
		if (!intel_dp_probe_mst(intel_dp)) {
			drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
			intel_dp_check_link_status(intel_dp);
			drm_modeset_unlock(&dev->mode_config.connection_mutex);
5195
			goto mst_fail;
5196
		}
5197 5198
	} else {
		if (intel_dp->is_mst) {
5199
			if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
5200 5201 5202 5203
				goto mst_fail;
		}

		if (!intel_dp->is_mst) {
5204
			drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
5205
			intel_dp_check_link_status(intel_dp);
5206
			drm_modeset_unlock(&dev->mode_config.connection_mutex);
5207 5208
		}
	}
5209 5210 5211

	ret = IRQ_HANDLED;

5212
	goto put_power;
5213 5214 5215 5216 5217 5218 5219
mst_fail:
	/* if we were in MST mode, and device is not there get out of MST mode */
	if (intel_dp->is_mst) {
		DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
		intel_dp->is_mst = false;
		drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
	}
5220 5221 5222 5223
put_power:
	intel_display_power_put(dev_priv, power_domain);

	return ret;
5224 5225
}

5226 5227
/* Return which DP Port should be selected for Transcoder DP control */
int
5228
intel_trans_dp_port_sel(struct drm_crtc *crtc)
5229 5230
{
	struct drm_device *dev = crtc->dev;
5231 5232
	struct intel_encoder *intel_encoder;
	struct intel_dp *intel_dp;
5233

5234 5235
	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		intel_dp = enc_to_intel_dp(&intel_encoder->base);
5236

5237 5238
		if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
		    intel_encoder->type == INTEL_OUTPUT_EDP)
C
Chris Wilson 已提交
5239
			return intel_dp->output_reg;
5240
	}
C
Chris Wilson 已提交
5241

5242 5243 5244
	return -1;
}

5245
/* check the VBT to see whether the eDP is on another port */
5246
bool intel_dp_is_edp(struct drm_device *dev, enum port port)
5247 5248
{
	struct drm_i915_private *dev_priv = dev->dev_private;
5249
	union child_device_config *p_child;
5250
	int i;
5251
	static const short port_mapping[] = {
5252 5253 5254 5255
		[PORT_B] = DVO_PORT_DPB,
		[PORT_C] = DVO_PORT_DPC,
		[PORT_D] = DVO_PORT_DPD,
		[PORT_E] = DVO_PORT_DPE,
5256
	};
5257

5258 5259 5260 5261 5262 5263 5264
	/*
	 * eDP not supported on g4x. so bail out early just
	 * for a bit extra safety in case the VBT is bonkers.
	 */
	if (INTEL_INFO(dev)->gen < 5)
		return false;

5265 5266 5267
	if (port == PORT_A)
		return true;

5268
	if (!dev_priv->vbt.child_dev_num)
5269 5270
		return false;

5271 5272
	for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
		p_child = dev_priv->vbt.child_dev + i;
5273

5274
		if (p_child->common.dvo_port == port_mapping[port] &&
5275 5276
		    (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
		    (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
5277 5278 5279 5280 5281
			return true;
	}
	return false;
}

5282
void
5283 5284
intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
{
5285 5286
	struct intel_connector *intel_connector = to_intel_connector(connector);

5287
	intel_attach_force_audio_property(connector);
5288
	intel_attach_broadcast_rgb_property(connector);
5289
	intel_dp->color_range_auto = true;
5290 5291 5292

	if (is_edp(intel_dp)) {
		drm_mode_create_scaling_mode_property(connector->dev);
5293 5294
		drm_object_attach_property(
			&connector->base,
5295
			connector->dev->mode_config.scaling_mode_property,
5296 5297
			DRM_MODE_SCALE_ASPECT);
		intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
5298
	}
5299 5300
}

5301 5302 5303 5304 5305 5306 5307
static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
{
	intel_dp->last_power_cycle = jiffies;
	intel_dp->last_power_on = jiffies;
	intel_dp->last_backlight_off = jiffies;
}

5308 5309
static void
intel_dp_init_panel_power_sequencer(struct drm_device *dev,
5310
				    struct intel_dp *intel_dp)
5311 5312
{
	struct drm_i915_private *dev_priv = dev->dev_private;
5313 5314
	struct edp_power_seq cur, vbt, spec,
		*final = &intel_dp->pps_delays;
5315 5316
	u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
	int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg = 0;
5317

V
Ville Syrjälä 已提交
5318 5319
	lockdep_assert_held(&dev_priv->pps_mutex);

5320 5321 5322 5323
	/* already initialized? */
	if (final->t11_t12 != 0)
		return;

5324 5325 5326 5327 5328 5329 5330 5331 5332 5333
	if (IS_BROXTON(dev)) {
		/*
		 * TODO: BXT has 2 sets of PPS registers.
		 * Correct Register for Broxton need to be identified
		 * using VBT. hardcoding for now
		 */
		pp_ctrl_reg = BXT_PP_CONTROL(0);
		pp_on_reg = BXT_PP_ON_DELAYS(0);
		pp_off_reg = BXT_PP_OFF_DELAYS(0);
	} else if (HAS_PCH_SPLIT(dev)) {
5334
		pp_ctrl_reg = PCH_PP_CONTROL;
5335 5336 5337 5338
		pp_on_reg = PCH_PP_ON_DELAYS;
		pp_off_reg = PCH_PP_OFF_DELAYS;
		pp_div_reg = PCH_PP_DIVISOR;
	} else {
5339 5340 5341 5342 5343 5344
		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);

		pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
		pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
		pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
		pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
5345
	}
5346 5347 5348

	/* Workaround: Need to write PP_CONTROL with the unlock key as
	 * the very first thing. */
5349
	pp_ctl = ironlake_get_pp_control(intel_dp);
5350

5351 5352
	pp_on = I915_READ(pp_on_reg);
	pp_off = I915_READ(pp_off_reg);
5353 5354 5355 5356
	if (!IS_BROXTON(dev)) {
		I915_WRITE(pp_ctrl_reg, pp_ctl);
		pp_div = I915_READ(pp_div_reg);
	}
5357 5358 5359 5360 5361 5362 5363 5364 5365 5366 5367 5368 5369 5370

	/* Pull timing values out of registers */
	cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
		PANEL_POWER_UP_DELAY_SHIFT;

	cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
		PANEL_LIGHT_ON_DELAY_SHIFT;

	cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
		PANEL_LIGHT_OFF_DELAY_SHIFT;

	cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
		PANEL_POWER_DOWN_DELAY_SHIFT;

5371 5372 5373 5374 5375 5376 5377 5378 5379
	if (IS_BROXTON(dev)) {
		u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
			BXT_POWER_CYCLE_DELAY_SHIFT;
		if (tmp > 0)
			cur.t11_t12 = (tmp - 1) * 1000;
		else
			cur.t11_t12 = 0;
	} else {
		cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5380
		       PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5381
	}
5382 5383 5384 5385

	DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		      cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);

5386
	vbt = dev_priv->vbt.edp_pps;
5387 5388 5389 5390 5391 5392 5393 5394 5395 5396 5397 5398 5399 5400 5401 5402 5403 5404

	/* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
	 * our hw here, which are all in 100usec. */
	spec.t1_t3 = 210 * 10;
	spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
	spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
	spec.t10 = 500 * 10;
	/* This one is special and actually in units of 100ms, but zero
	 * based in the hw (so we need to add 100 ms). But the sw vbt
	 * table multiplies it with 1000 to make it in units of 100usec,
	 * too. */
	spec.t11_t12 = (510 + 100) * 10;

	DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		      vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);

	/* Use the max of the register settings and vbt. If both are
	 * unset, fall back to the spec limits. */
5405
#define assign_final(field)	final->field = (max(cur.field, vbt.field) == 0 ? \
5406 5407 5408 5409 5410 5411 5412 5413 5414
				       spec.field : \
				       max(cur.field, vbt.field))
	assign_final(t1_t3);
	assign_final(t8);
	assign_final(t9);
	assign_final(t10);
	assign_final(t11_t12);
#undef assign_final

5415
#define get_delay(field)	(DIV_ROUND_UP(final->field, 10))
5416 5417 5418 5419 5420 5421 5422
	intel_dp->panel_power_up_delay = get_delay(t1_t3);
	intel_dp->backlight_on_delay = get_delay(t8);
	intel_dp->backlight_off_delay = get_delay(t9);
	intel_dp->panel_power_down_delay = get_delay(t10);
	intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
#undef get_delay

5423 5424 5425 5426 5427 5428 5429 5430 5431 5432
	DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
		      intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
		      intel_dp->panel_power_cycle_delay);

	DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
		      intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
}

static void
intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
5433
					      struct intel_dp *intel_dp)
5434 5435
{
	struct drm_i915_private *dev_priv = dev->dev_private;
5436 5437
	u32 pp_on, pp_off, pp_div, port_sel = 0;
	int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
5438
	int pp_on_reg, pp_off_reg, pp_div_reg = 0, pp_ctrl_reg;
5439
	enum port port = dp_to_dig_port(intel_dp)->port;
5440
	const struct edp_power_seq *seq = &intel_dp->pps_delays;
5441

V
Ville Syrjälä 已提交
5442
	lockdep_assert_held(&dev_priv->pps_mutex);
5443

5444 5445 5446 5447 5448 5449 5450 5451 5452 5453 5454
	if (IS_BROXTON(dev)) {
		/*
		 * TODO: BXT has 2 sets of PPS registers.
		 * Correct Register for Broxton need to be identified
		 * using VBT. hardcoding for now
		 */
		pp_ctrl_reg = BXT_PP_CONTROL(0);
		pp_on_reg = BXT_PP_ON_DELAYS(0);
		pp_off_reg = BXT_PP_OFF_DELAYS(0);

	} else if (HAS_PCH_SPLIT(dev)) {
5455 5456 5457 5458
		pp_on_reg = PCH_PP_ON_DELAYS;
		pp_off_reg = PCH_PP_OFF_DELAYS;
		pp_div_reg = PCH_PP_DIVISOR;
	} else {
5459 5460 5461 5462 5463
		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);

		pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
		pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
		pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
5464 5465
	}

5466 5467 5468 5469 5470 5471 5472 5473
	/*
	 * And finally store the new values in the power sequencer. The
	 * backlight delays are set to 1 because we do manual waits on them. For
	 * T8, even BSpec recommends doing it. For T9, if we don't do this,
	 * we'll end up waiting for the backlight off delay twice: once when we
	 * do the manual sleep, and once when we disable the panel and wait for
	 * the PP_STATUS bit to become zero.
	 */
5474
	pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5475 5476
		(1 << PANEL_LIGHT_ON_DELAY_SHIFT);
	pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5477
		 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5478 5479
	/* Compute the divisor for the pp clock, simply match the Bspec
	 * formula. */
5480 5481 5482 5483 5484 5485 5486 5487 5488 5489
	if (IS_BROXTON(dev)) {
		pp_div = I915_READ(pp_ctrl_reg);
		pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
		pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
				<< BXT_POWER_CYCLE_DELAY_SHIFT);
	} else {
		pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
		pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
				<< PANEL_POWER_CYCLE_DELAY_SHIFT);
	}
5490 5491 5492

	/* Haswell doesn't have any port selection bits for the panel
	 * power sequencer any more. */
5493
	if (IS_VALLEYVIEW(dev)) {
5494
		port_sel = PANEL_PORT_SELECT_VLV(port);
5495
	} else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5496
		if (port == PORT_A)
5497
			port_sel = PANEL_PORT_SELECT_DPA;
5498
		else
5499
			port_sel = PANEL_PORT_SELECT_DPD;
5500 5501
	}

5502 5503 5504 5505
	pp_on |= port_sel;

	I915_WRITE(pp_on_reg, pp_on);
	I915_WRITE(pp_off_reg, pp_off);
5506 5507 5508 5509
	if (IS_BROXTON(dev))
		I915_WRITE(pp_ctrl_reg, pp_div);
	else
		I915_WRITE(pp_div_reg, pp_div);
5510 5511

	DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5512 5513
		      I915_READ(pp_on_reg),
		      I915_READ(pp_off_reg),
5514 5515
		      IS_BROXTON(dev) ?
		      (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) :
5516
		      I915_READ(pp_div_reg));
5517 5518
}

5519 5520 5521 5522 5523 5524 5525 5526 5527 5528 5529 5530
/**
 * intel_dp_set_drrs_state - program registers for RR switch to take effect
 * @dev: DRM device
 * @refresh_rate: RR to be programmed
 *
 * This function gets called when refresh rate (RR) has to be changed from
 * one frequency to another. Switches can be between high and low RR
 * supported by the panel or to any other RR based on media playback (in
 * this case, RR value needs to be passed from user space).
 *
 * The caller of this function needs to take a lock on dev_priv->drrs.
 */
5531
static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
5532 5533 5534
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_encoder *encoder;
5535 5536
	struct intel_digital_port *dig_port = NULL;
	struct intel_dp *intel_dp = dev_priv->drrs.dp;
5537
	struct intel_crtc_state *config = NULL;
5538 5539
	struct intel_crtc *intel_crtc = NULL;
	u32 reg, val;
5540
	enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5541 5542 5543 5544 5545 5546

	if (refresh_rate <= 0) {
		DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
		return;
	}

5547 5548
	if (intel_dp == NULL) {
		DRM_DEBUG_KMS("DRRS not supported.\n");
5549 5550 5551
		return;
	}

5552
	/*
5553 5554
	 * FIXME: This needs proper synchronization with psr state for some
	 * platforms that cannot have PSR and DRRS enabled at the same time.
5555
	 */
5556

5557 5558
	dig_port = dp_to_dig_port(intel_dp);
	encoder = &dig_port->base;
5559
	intel_crtc = to_intel_crtc(encoder->base.crtc);
5560 5561 5562 5563 5564 5565

	if (!intel_crtc) {
		DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
		return;
	}

5566
	config = intel_crtc->config;
5567

5568
	if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5569 5570 5571 5572
		DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
		return;
	}

5573 5574
	if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
			refresh_rate)
5575 5576
		index = DRRS_LOW_RR;

5577
	if (index == dev_priv->drrs.refresh_rate_type) {
5578 5579 5580 5581 5582 5583 5584 5585 5586 5587
		DRM_DEBUG_KMS(
			"DRRS requested for previously set RR...ignoring\n");
		return;
	}

	if (!intel_crtc->active) {
		DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
		return;
	}

D
Durgadoss R 已提交
5588
	if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
5589 5590 5591 5592 5593 5594 5595 5596 5597 5598 5599 5600
		switch (index) {
		case DRRS_HIGH_RR:
			intel_dp_set_m_n(intel_crtc, M1_N1);
			break;
		case DRRS_LOW_RR:
			intel_dp_set_m_n(intel_crtc, M2_N2);
			break;
		case DRRS_MAX_RR:
		default:
			DRM_ERROR("Unsupported refreshrate type\n");
		}
	} else if (INTEL_INFO(dev)->gen > 6) {
5601
		reg = PIPECONF(intel_crtc->config->cpu_transcoder);
5602
		val = I915_READ(reg);
5603

5604
		if (index > DRRS_HIGH_RR) {
5605 5606 5607 5608
			if (IS_VALLEYVIEW(dev))
				val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
			else
				val |= PIPECONF_EDP_RR_MODE_SWITCH;
5609
		} else {
5610 5611 5612 5613
			if (IS_VALLEYVIEW(dev))
				val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
			else
				val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5614 5615 5616 5617
		}
		I915_WRITE(reg, val);
	}

5618 5619 5620 5621 5622
	dev_priv->drrs.refresh_rate_type = index;

	DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
}

5623 5624 5625 5626 5627 5628
/**
 * intel_edp_drrs_enable - init drrs struct if supported
 * @intel_dp: DP struct
 *
 * Initializes frontbuffer_bits and drrs.dp
 */
V
Vandana Kannan 已提交
5629 5630 5631 5632 5633 5634 5635 5636 5637 5638 5639 5640 5641 5642 5643 5644 5645 5646 5647 5648 5649 5650 5651 5652 5653 5654 5655
void intel_edp_drrs_enable(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = dig_port->base.base.crtc;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	if (!intel_crtc->config->has_drrs) {
		DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
		return;
	}

	mutex_lock(&dev_priv->drrs.mutex);
	if (WARN_ON(dev_priv->drrs.dp)) {
		DRM_ERROR("DRRS already enabled\n");
		goto unlock;
	}

	dev_priv->drrs.busy_frontbuffer_bits = 0;

	dev_priv->drrs.dp = intel_dp;

unlock:
	mutex_unlock(&dev_priv->drrs.mutex);
}

5656 5657 5658 5659 5660
/**
 * intel_edp_drrs_disable - Disable DRRS
 * @intel_dp: DP struct
 *
 */
V
Vandana Kannan 已提交
5661 5662 5663 5664 5665 5666 5667 5668 5669 5670 5671 5672 5673 5674 5675 5676 5677 5678 5679 5680 5681 5682 5683 5684 5685 5686 5687 5688
void intel_edp_drrs_disable(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = dig_port->base.base.crtc;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	if (!intel_crtc->config->has_drrs)
		return;

	mutex_lock(&dev_priv->drrs.mutex);
	if (!dev_priv->drrs.dp) {
		mutex_unlock(&dev_priv->drrs.mutex);
		return;
	}

	if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
		intel_dp_set_drrs_state(dev_priv->dev,
			intel_dp->attached_connector->panel.
			fixed_mode->vrefresh);

	dev_priv->drrs.dp = NULL;
	mutex_unlock(&dev_priv->drrs.mutex);

	cancel_delayed_work_sync(&dev_priv->drrs.work);
}

5689 5690 5691 5692 5693 5694 5695 5696 5697 5698 5699 5700 5701
static void intel_edp_drrs_downclock_work(struct work_struct *work)
{
	struct drm_i915_private *dev_priv =
		container_of(work, typeof(*dev_priv), drrs.work.work);
	struct intel_dp *intel_dp;

	mutex_lock(&dev_priv->drrs.mutex);

	intel_dp = dev_priv->drrs.dp;

	if (!intel_dp)
		goto unlock;

5702
	/*
5703 5704
	 * The delayed work can race with an invalidate hence we need to
	 * recheck.
5705 5706
	 */

5707 5708
	if (dev_priv->drrs.busy_frontbuffer_bits)
		goto unlock;
5709

5710 5711 5712 5713
	if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
		intel_dp_set_drrs_state(dev_priv->dev,
			intel_dp->attached_connector->panel.
			downclock_mode->vrefresh);
5714

5715 5716
unlock:
	mutex_unlock(&dev_priv->drrs.mutex);
5717 5718
}

5719
/**
5720
 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5721 5722 5723
 * @dev: DRM device
 * @frontbuffer_bits: frontbuffer plane tracking bits
 *
5724 5725
 * This function gets called everytime rendering on the given planes start.
 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5726 5727 5728
 *
 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
 */
5729 5730 5731 5732 5733 5734 5735
void intel_edp_drrs_invalidate(struct drm_device *dev,
		unsigned frontbuffer_bits)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc;
	enum pipe pipe;

5736
	if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5737 5738
		return;

5739
	cancel_delayed_work(&dev_priv->drrs.work);
5740

5741
	mutex_lock(&dev_priv->drrs.mutex);
5742 5743 5744 5745 5746
	if (!dev_priv->drrs.dp) {
		mutex_unlock(&dev_priv->drrs.mutex);
		return;
	}

5747 5748 5749
	crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
	pipe = to_intel_crtc(crtc)->pipe;

5750 5751 5752
	frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
	dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;

5753
	/* invalidate means busy screen hence upclock */
5754
	if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5755 5756 5757 5758 5759 5760 5761
		intel_dp_set_drrs_state(dev_priv->dev,
				dev_priv->drrs.dp->attached_connector->panel.
				fixed_mode->vrefresh);

	mutex_unlock(&dev_priv->drrs.mutex);
}

5762
/**
5763
 * intel_edp_drrs_flush - Restart Idleness DRRS
5764 5765 5766
 * @dev: DRM device
 * @frontbuffer_bits: frontbuffer plane tracking bits
 *
5767 5768 5769 5770
 * This function gets called every time rendering on the given planes has
 * completed or flip on a crtc is completed. So DRRS should be upclocked
 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
 * if no other planes are dirty.
5771 5772 5773
 *
 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
 */
5774 5775 5776 5777 5778 5779 5780
void intel_edp_drrs_flush(struct drm_device *dev,
		unsigned frontbuffer_bits)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc;
	enum pipe pipe;

5781
	if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5782 5783
		return;

5784
	cancel_delayed_work(&dev_priv->drrs.work);
5785

5786
	mutex_lock(&dev_priv->drrs.mutex);
5787 5788 5789 5790 5791
	if (!dev_priv->drrs.dp) {
		mutex_unlock(&dev_priv->drrs.mutex);
		return;
	}

5792 5793
	crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
	pipe = to_intel_crtc(crtc)->pipe;
5794 5795

	frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5796 5797
	dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;

5798
	/* flush means busy screen hence upclock */
5799
	if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5800 5801 5802 5803 5804 5805 5806 5807 5808
		intel_dp_set_drrs_state(dev_priv->dev,
				dev_priv->drrs.dp->attached_connector->panel.
				fixed_mode->vrefresh);

	/*
	 * flush also means no more activity hence schedule downclock, if all
	 * other fbs are quiescent too
	 */
	if (!dev_priv->drrs.busy_frontbuffer_bits)
5809 5810 5811 5812 5813
		schedule_delayed_work(&dev_priv->drrs.work,
				msecs_to_jiffies(1000));
	mutex_unlock(&dev_priv->drrs.mutex);
}

5814 5815 5816 5817 5818 5819 5820 5821 5822 5823 5824 5825 5826 5827 5828 5829 5830 5831 5832 5833 5834 5835 5836 5837 5838 5839 5840 5841 5842 5843 5844 5845 5846 5847 5848 5849 5850 5851 5852 5853 5854 5855 5856 5857 5858 5859 5860 5861 5862 5863
/**
 * DOC: Display Refresh Rate Switching (DRRS)
 *
 * Display Refresh Rate Switching (DRRS) is a power conservation feature
 * which enables swtching between low and high refresh rates,
 * dynamically, based on the usage scenario. This feature is applicable
 * for internal panels.
 *
 * Indication that the panel supports DRRS is given by the panel EDID, which
 * would list multiple refresh rates for one resolution.
 *
 * DRRS is of 2 types - static and seamless.
 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
 * (may appear as a blink on screen) and is used in dock-undock scenario.
 * Seamless DRRS involves changing RR without any visual effect to the user
 * and can be used during normal system usage. This is done by programming
 * certain registers.
 *
 * Support for static/seamless DRRS may be indicated in the VBT based on
 * inputs from the panel spec.
 *
 * DRRS saves power by switching to low RR based on usage scenarios.
 *
 * eDP DRRS:-
 *        The implementation is based on frontbuffer tracking implementation.
 * When there is a disturbance on the screen triggered by user activity or a
 * periodic system activity, DRRS is disabled (RR is changed to high RR).
 * When there is no movement on screen, after a timeout of 1 second, a switch
 * to low RR is made.
 *        For integration with frontbuffer tracking code,
 * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
 *
 * DRRS can be further extended to support other internal panels and also
 * the scenario of video playback wherein RR is set based on the rate
 * requested by userspace.
 */

/**
 * intel_dp_drrs_init - Init basic DRRS work and mutex.
 * @intel_connector: eDP connector
 * @fixed_mode: preferred mode of panel
 *
 * This function is  called only once at driver load to initialize basic
 * DRRS stuff.
 *
 * Returns:
 * Downclock mode if panel supports it, else return NULL.
 * DRRS support is determined by the presence of downclock mode (apart
 * from VBT setting).
 */
5864
static struct drm_display_mode *
5865 5866
intel_dp_drrs_init(struct intel_connector *intel_connector,
		struct drm_display_mode *fixed_mode)
5867 5868
{
	struct drm_connector *connector = &intel_connector->base;
5869
	struct drm_device *dev = connector->dev;
5870 5871 5872
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_display_mode *downclock_mode = NULL;

5873 5874 5875
	INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
	mutex_init(&dev_priv->drrs.mutex);

5876 5877 5878 5879 5880 5881
	if (INTEL_INFO(dev)->gen <= 6) {
		DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
		return NULL;
	}

	if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5882
		DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5883 5884 5885 5886 5887 5888 5889
		return NULL;
	}

	downclock_mode = intel_find_panel_downclock
					(dev, fixed_mode, connector);

	if (!downclock_mode) {
5890
		DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5891 5892 5893
		return NULL;
	}

5894
	dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5895

5896
	dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5897
	DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5898 5899 5900
	return downclock_mode;
}

5901
static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5902
				     struct intel_connector *intel_connector)
5903 5904 5905
{
	struct drm_connector *connector = &intel_connector->base;
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5906 5907
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct drm_device *dev = intel_encoder->base.dev;
5908 5909
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_display_mode *fixed_mode = NULL;
5910
	struct drm_display_mode *downclock_mode = NULL;
5911 5912 5913
	bool has_dpcd;
	struct drm_display_mode *scan;
	struct edid *edid;
5914
	enum pipe pipe = INVALID_PIPE;
5915 5916 5917 5918

	if (!is_edp(intel_dp))
		return true;

5919 5920 5921
	pps_lock(intel_dp);
	intel_edp_panel_vdd_sanitize(intel_dp);
	pps_unlock(intel_dp);
5922

5923 5924 5925 5926 5927 5928 5929 5930 5931 5932 5933 5934 5935 5936 5937
	/* Cache DPCD and EDID for edp. */
	has_dpcd = intel_dp_get_dpcd(intel_dp);

	if (has_dpcd) {
		if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
			dev_priv->no_aux_handshake =
				intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
				DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
	} else {
		/* if this fails, presume the device is a ghost */
		DRM_INFO("failed to retrieve link info, disabling eDP\n");
		return false;
	}

	/* We now know it's not a ghost, init power sequence regs. */
5938
	pps_lock(intel_dp);
5939
	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5940
	pps_unlock(intel_dp);
5941

5942
	mutex_lock(&dev->mode_config.mutex);
5943
	edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5944 5945 5946 5947 5948 5949 5950 5951 5952 5953 5954 5955 5956 5957 5958 5959 5960 5961
	if (edid) {
		if (drm_add_edid_modes(connector, edid)) {
			drm_mode_connector_update_edid_property(connector,
								edid);
			drm_edid_to_eld(connector, edid);
		} else {
			kfree(edid);
			edid = ERR_PTR(-EINVAL);
		}
	} else {
		edid = ERR_PTR(-ENOENT);
	}
	intel_connector->edid = edid;

	/* prefer fixed mode from EDID if available */
	list_for_each_entry(scan, &connector->probed_modes, head) {
		if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
			fixed_mode = drm_mode_duplicate(dev, scan);
5962 5963
			downclock_mode = intel_dp_drrs_init(
						intel_connector, fixed_mode);
5964 5965 5966 5967 5968 5969 5970 5971 5972 5973 5974
			break;
		}
	}

	/* fallback to VBT if available for eDP */
	if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
		fixed_mode = drm_mode_duplicate(dev,
					dev_priv->vbt.lfp_lvds_vbt_mode);
		if (fixed_mode)
			fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
	}
5975
	mutex_unlock(&dev->mode_config.mutex);
5976

5977 5978 5979
	if (IS_VALLEYVIEW(dev)) {
		intel_dp->edp_notifier.notifier_call = edp_notify_handler;
		register_reboot_notifier(&intel_dp->edp_notifier);
5980 5981 5982 5983 5984 5985 5986 5987 5988 5989 5990 5991 5992 5993 5994 5995 5996 5997 5998

		/*
		 * Figure out the current pipe for the initial backlight setup.
		 * If the current pipe isn't valid, try the PPS pipe, and if that
		 * fails just assume pipe A.
		 */
		if (IS_CHERRYVIEW(dev))
			pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
		else
			pipe = PORT_TO_PIPE(intel_dp->DP);

		if (pipe != PIPE_A && pipe != PIPE_B)
			pipe = intel_dp->pps_pipe;

		if (pipe != PIPE_A && pipe != PIPE_B)
			pipe = PIPE_A;

		DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
			      pipe_name(pipe));
5999 6000
	}

6001
	intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
6002
	intel_connector->panel.backlight.power = intel_edp_backlight_power;
6003
	intel_panel_setup_backlight(connector, pipe);
6004 6005 6006 6007

	return true;
}

6008
bool
6009 6010
intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
			struct intel_connector *intel_connector)
6011
{
6012 6013 6014 6015
	struct drm_connector *connector = &intel_connector->base;
	struct intel_dp *intel_dp = &intel_dig_port->dp;
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct drm_device *dev = intel_encoder->base.dev;
6016
	struct drm_i915_private *dev_priv = dev->dev_private;
6017
	enum port port = intel_dig_port->port;
6018
	int type;
6019

6020 6021
	intel_dp->pps_pipe = INVALID_PIPE;

6022
	/* intel_dp vfuncs */
6023 6024 6025
	if (INTEL_INFO(dev)->gen >= 9)
		intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
	else if (IS_VALLEYVIEW(dev))
6026 6027 6028 6029 6030 6031 6032 6033
		intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
		intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
	else if (HAS_PCH_SPLIT(dev))
		intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
	else
		intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;

6034 6035 6036 6037
	if (INTEL_INFO(dev)->gen >= 9)
		intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
	else
		intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
6038

6039 6040
	/* Preserve the current hw state. */
	intel_dp->DP = I915_READ(intel_dp->output_reg);
6041
	intel_dp->attached_connector = intel_connector;
6042

6043
	if (intel_dp_is_edp(dev, port))
6044
		type = DRM_MODE_CONNECTOR_eDP;
6045 6046
	else
		type = DRM_MODE_CONNECTOR_DisplayPort;
6047

6048 6049 6050 6051 6052 6053 6054 6055
	/*
	 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
	 * for DP the encoder type can be set by the caller to
	 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
	 */
	if (type == DRM_MODE_CONNECTOR_eDP)
		intel_encoder->type = INTEL_OUTPUT_EDP;

6056 6057 6058 6059 6060
	/* eDP only on port B and/or C on vlv/chv */
	if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
		    port != PORT_B && port != PORT_C))
		return false;

6061 6062 6063 6064
	DRM_DEBUG_KMS("Adding %s connector on port %c\n",
			type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
			port_name(port));

6065
	drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
6066 6067 6068 6069 6070
	drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);

	connector->interlace_allowed = true;
	connector->doublescan_allowed = 0;

6071
	INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
6072
			  edp_panel_vdd_work);
6073

6074
	intel_connector_attach_encoder(intel_connector, intel_encoder);
6075
	drm_connector_register(connector);
6076

P
Paulo Zanoni 已提交
6077
	if (HAS_DDI(dev))
6078 6079 6080
		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
	else
		intel_connector->get_hw_state = intel_connector_get_hw_state;
6081
	intel_connector->unregister = intel_dp_connector_unregister;
6082

6083
	/* Set up the hotplug pin. */
6084 6085
	switch (port) {
	case PORT_A:
6086
		intel_encoder->hpd_pin = HPD_PORT_A;
6087 6088
		break;
	case PORT_B:
6089
		intel_encoder->hpd_pin = HPD_PORT_B;
6090 6091
		if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0))
			intel_encoder->hpd_pin = HPD_PORT_A;
6092 6093
		break;
	case PORT_C:
6094
		intel_encoder->hpd_pin = HPD_PORT_C;
6095 6096
		break;
	case PORT_D:
6097
		intel_encoder->hpd_pin = HPD_PORT_D;
6098
		break;
X
Xiong Zhang 已提交
6099 6100 6101
	case PORT_E:
		intel_encoder->hpd_pin = HPD_PORT_E;
		break;
6102
	default:
6103
		BUG();
6104 6105
	}

6106
	if (is_edp(intel_dp)) {
6107
		pps_lock(intel_dp);
6108 6109
		intel_dp_init_panel_power_timestamps(intel_dp);
		if (IS_VALLEYVIEW(dev))
6110
			vlv_initial_power_sequencer_setup(intel_dp);
6111
		else
6112
			intel_dp_init_panel_power_sequencer(dev, intel_dp);
6113
		pps_unlock(intel_dp);
6114
	}
6115

6116
	intel_dp_aux_init(intel_dp, intel_connector);
6117

6118
	/* init MST on ports that can support it */
6119 6120 6121 6122
	if (HAS_DP_MST(dev) &&
	    (port == PORT_B || port == PORT_C || port == PORT_D))
		intel_dp_mst_encoder_init(intel_dig_port,
					  intel_connector->base.base.id);
6123

6124
	if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6125
		drm_dp_aux_unregister(&intel_dp->aux);
6126 6127
		if (is_edp(intel_dp)) {
			cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
6128 6129 6130 6131
			/*
			 * vdd might still be enabled do to the delayed vdd off.
			 * Make sure vdd is actually turned off here.
			 */
6132
			pps_lock(intel_dp);
6133
			edp_panel_vdd_off_sync(intel_dp);
6134
			pps_unlock(intel_dp);
6135
		}
6136
		drm_connector_unregister(connector);
6137
		drm_connector_cleanup(connector);
6138
		return false;
6139
	}
6140

6141 6142
	intel_dp_add_properties(intel_dp, connector);

6143 6144 6145 6146 6147 6148 6149 6150
	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
	 * 0xd.  Failure to do so will result in spurious interrupts being
	 * generated on the port when a cable is not attached.
	 */
	if (IS_G4X(dev) && !IS_GM45(dev)) {
		u32 temp = I915_READ(PEG_BAND_GAP_DATA);
		I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
	}
6151

6152 6153
	i915_debugfs_connector_add(connector);

6154
	return true;
6155
}
6156 6157 6158 6159

void
intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
{
6160
	struct drm_i915_private *dev_priv = dev->dev_private;
6161 6162 6163 6164 6165
	struct intel_digital_port *intel_dig_port;
	struct intel_encoder *intel_encoder;
	struct drm_encoder *encoder;
	struct intel_connector *intel_connector;

6166
	intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
6167 6168 6169
	if (!intel_dig_port)
		return;

6170
	intel_connector = intel_connector_alloc();
S
Sudip Mukherjee 已提交
6171 6172
	if (!intel_connector)
		goto err_connector_alloc;
6173 6174 6175 6176 6177 6178 6179

	intel_encoder = &intel_dig_port->base;
	encoder = &intel_encoder->base;

	drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
			 DRM_MODE_ENCODER_TMDS);

6180
	intel_encoder->compute_config = intel_dp_compute_config;
P
Paulo Zanoni 已提交
6181 6182
	intel_encoder->disable = intel_disable_dp;
	intel_encoder->get_hw_state = intel_dp_get_hw_state;
6183
	intel_encoder->get_config = intel_dp_get_config;
6184
	intel_encoder->suspend = intel_dp_encoder_suspend;
6185
	if (IS_CHERRYVIEW(dev)) {
6186
		intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
6187 6188
		intel_encoder->pre_enable = chv_pre_enable_dp;
		intel_encoder->enable = vlv_enable_dp;
6189
		intel_encoder->post_disable = chv_post_disable_dp;
6190
		intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
6191
	} else if (IS_VALLEYVIEW(dev)) {
6192
		intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
6193 6194
		intel_encoder->pre_enable = vlv_pre_enable_dp;
		intel_encoder->enable = vlv_enable_dp;
6195
		intel_encoder->post_disable = vlv_post_disable_dp;
6196
	} else {
6197 6198
		intel_encoder->pre_enable = g4x_pre_enable_dp;
		intel_encoder->enable = g4x_enable_dp;
6199 6200
		if (INTEL_INFO(dev)->gen >= 5)
			intel_encoder->post_disable = ilk_post_disable_dp;
6201
	}
6202

6203
	intel_dig_port->port = port;
6204 6205
	intel_dig_port->dp.output_reg = output_reg;

P
Paulo Zanoni 已提交
6206
	intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
6207 6208 6209 6210 6211 6212 6213 6214
	if (IS_CHERRYVIEW(dev)) {
		if (port == PORT_D)
			intel_encoder->crtc_mask = 1 << 2;
		else
			intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
	} else {
		intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
	}
6215
	intel_encoder->cloneable = 0;
6216

6217
	intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6218
	dev_priv->hotplug.irq_port[port] = intel_dig_port;
6219

S
Sudip Mukherjee 已提交
6220 6221 6222 6223 6224 6225 6226 6227 6228 6229 6230 6231
	if (!intel_dp_init_connector(intel_dig_port, intel_connector))
		goto err_init_connector;

	return;

err_init_connector:
	drm_encoder_cleanup(encoder);
	kfree(intel_connector);
err_connector_alloc:
	kfree(intel_dig_port);

	return;
6232
}
6233 6234 6235 6236 6237 6238 6239 6240

void intel_dp_mst_suspend(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;

	/* disable MST */
	for (i = 0; i < I915_MAX_PORTS; i++) {
6241
		struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6242 6243 6244 6245 6246 6247 6248 6249 6250 6251 6252 6253 6254 6255 6256 6257 6258 6259
		if (!intel_dig_port)
			continue;

		if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
			if (!intel_dig_port->dp.can_mst)
				continue;
			if (intel_dig_port->dp.is_mst)
				drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
		}
	}
}

void intel_dp_mst_resume(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;

	for (i = 0; i < I915_MAX_PORTS; i++) {
6260
		struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6261 6262 6263 6264 6265 6266 6267 6268 6269 6270 6271 6272 6273 6274 6275
		if (!intel_dig_port)
			continue;
		if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
			int ret;

			if (!intel_dig_port->dp.can_mst)
				continue;

			ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
			if (ret != 0) {
				intel_dp_check_mst_status(&intel_dig_port->dp);
			}
		}
	}
}