drm/i915/dp: Flush the PLL register write before sleeping

Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>

drivers/gpu/drm/i915/intel_dp.c

@@ -883,6 +883,7 @@ static void ironlake_edp_pll_off(struct drm_encoder *encoder)
 	dpa_ctl = I915_READ(DP_A);
 	dpa_ctl |= DP_PLL_ENABLE;
 	I915_WRITE(DP_A, dpa_ctl);
+	POSTING_READ(DP_A);
 	udelay(200);
 }