intel_dp.c 155.7 KB
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/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Keith Packard <keithp@keithp.com>
 *
 */

#include <linux/i2c.h>
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#include <linux/slab.h>
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#include <linux/export.h>
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#include <linux/notifier.h>
#include <linux/reboot.h>
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#include <drm/drmP.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_edid.h>
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#include "intel_drv.h"
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#include <drm/i915_drm.h>
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#include "i915_drv.h"

#define DP_LINK_CHECK_TIMEOUT	(10 * 1000)

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/* Compliance test status bits  */
#define INTEL_DP_RESOLUTION_SHIFT_MASK	0
#define INTEL_DP_RESOLUTION_PREFERRED	(1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
#define INTEL_DP_RESOLUTION_STANDARD	(2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
#define INTEL_DP_RESOLUTION_FAILSAFE	(3 << INTEL_DP_RESOLUTION_SHIFT_MASK)

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struct dp_link_dpll {
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	int clock;
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	struct dpll dpll;
};

static const struct dp_link_dpll gen4_dpll[] = {
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	{ 162000,
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		{ .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
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	{ 270000,
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		{ .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
};

static const struct dp_link_dpll pch_dpll[] = {
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	{ 162000,
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		{ .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
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	{ 270000,
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		{ .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
};

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static const struct dp_link_dpll vlv_dpll[] = {
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	{ 162000,
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		{ .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
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	{ 270000,
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		{ .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
};

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/*
 * CHV supports eDP 1.4 that have  more link rates.
 * Below only provides the fixed rate but exclude variable rate.
 */
static const struct dp_link_dpll chv_dpll[] = {
	/*
	 * CHV requires to program fractional division for m2.
	 * m2 is stored in fixed point format using formula below
	 * (m2_int << 22) | m2_fraction
	 */
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	{ 162000,	/* m2_int = 32, m2_fraction = 1677722 */
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		{ .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
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	{ 270000,	/* m2_int = 27, m2_fraction = 0 */
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		{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
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	{ 540000,	/* m2_int = 27, m2_fraction = 0 */
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		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
};
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static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
				  324000, 432000, 540000 };
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static const int skl_rates[] = { 162000, 216000, 270000,
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				  324000, 432000, 540000 };
static const int default_rates[] = { 162000, 270000, 540000 };
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/**
 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 * @intel_dp: DP struct
 *
 * If a CPU or PCH DP output is attached to an eDP panel, this function
 * will return true, and false otherwise.
 */
static bool is_edp(struct intel_dp *intel_dp)
{
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	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
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}

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static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
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{
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	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	return intel_dig_port->base.base.dev;
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}

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static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
{
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	return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
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}

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static void intel_dp_link_down(struct intel_dp *intel_dp);
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static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
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static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
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static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
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static void vlv_steal_power_sequencer(struct drm_device *dev,
				      enum pipe pipe);
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static void intel_dp_unset_edid(struct intel_dp *intel_dp);
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static int
intel_dp_max_link_bw(struct intel_dp  *intel_dp)
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{
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	int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
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	switch (max_link_bw) {
	case DP_LINK_BW_1_62:
	case DP_LINK_BW_2_7:
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	case DP_LINK_BW_5_4:
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		break;
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	default:
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		WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
		     max_link_bw);
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		max_link_bw = DP_LINK_BW_1_62;
		break;
	}
	return max_link_bw;
}

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static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	u8 source_max, sink_max;

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	source_max = intel_dig_port->max_lanes;
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	sink_max = drm_dp_max_lane_count(intel_dp->dpcd);

	return min(source_max, sink_max);
}

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/*
 * The units on the numbers in the next two are... bizarre.  Examples will
 * make it clearer; this one parallels an example in the eDP spec.
 *
 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 *
 *     270000 * 1 * 8 / 10 == 216000
 *
 * The actual data capacity of that configuration is 2.16Gbit/s, so the
 * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 * 119000.  At 18bpp that's 2142000 kilobits per second.
 *
 * Thus the strange-looking division by 10 in intel_dp_link_required, to
 * get the result in decakilobits instead of kilobits.
 */

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static int
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intel_dp_link_required(int pixel_clock, int bpp)
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{
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	return (pixel_clock * bpp + 9) / 10;
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}

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static int
intel_dp_max_data_rate(int max_link_clock, int max_lanes)
{
	return (max_link_clock * max_lanes * 8) / 10;
}

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static enum drm_mode_status
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intel_dp_mode_valid(struct drm_connector *connector,
		    struct drm_display_mode *mode)
{
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	struct intel_dp *intel_dp = intel_attached_dp(connector);
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	struct intel_connector *intel_connector = to_intel_connector(connector);
	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
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	int target_clock = mode->clock;
	int max_rate, mode_rate, max_lanes, max_link_clock;
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	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
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	if (is_edp(intel_dp) && fixed_mode) {
		if (mode->hdisplay > fixed_mode->hdisplay)
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			return MODE_PANEL;

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		if (mode->vdisplay > fixed_mode->vdisplay)
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			return MODE_PANEL;
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		target_clock = fixed_mode->clock;
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	}

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	max_link_clock = intel_dp_max_link_rate(intel_dp);
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	max_lanes = intel_dp_max_lane_count(intel_dp);
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	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
	mode_rate = intel_dp_link_required(target_clock, 18);

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	if (mode_rate > max_rate || target_clock > max_dotclk)
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		return MODE_CLOCK_HIGH;
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	if (mode->clock < 10000)
		return MODE_CLOCK_LOW;

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	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
		return MODE_H_ILLEGAL;

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	return MODE_OK;
}

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uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
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{
	int	i;
	uint32_t v = 0;

	if (src_bytes > 4)
		src_bytes = 4;
	for (i = 0; i < src_bytes; i++)
		v |= ((uint32_t) src[i]) << ((3-i) * 8);
	return v;
}

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static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
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{
	int i;
	if (dst_bytes > 4)
		dst_bytes = 4;
	for (i = 0; i < dst_bytes; i++)
		dst[i] = src >> ((3-i) * 8);
}

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static void
intel_dp_init_panel_power_sequencer(struct drm_device *dev,
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				    struct intel_dp *intel_dp);
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static void
intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
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					      struct intel_dp *intel_dp);
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static void pps_lock(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *encoder = &intel_dig_port->base;
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum intel_display_power_domain power_domain;

	/*
	 * See vlv_power_sequencer_reset() why we need
	 * a power domain reference here.
	 */
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	power_domain = intel_display_port_aux_power_domain(encoder);
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	intel_display_power_get(dev_priv, power_domain);

	mutex_lock(&dev_priv->pps_mutex);
}

static void pps_unlock(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *encoder = &intel_dig_port->base;
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum intel_display_power_domain power_domain;

	mutex_unlock(&dev_priv->pps_mutex);

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	power_domain = intel_display_port_aux_power_domain(encoder);
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	intel_display_power_put(dev_priv, power_domain);
}

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static void
vlv_power_sequencer_kick(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum pipe pipe = intel_dp->pps_pipe;
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	bool pll_enabled, release_cl_override = false;
	enum dpio_phy phy = DPIO_PHY(pipe);
	enum dpio_channel ch = vlv_pipe_to_channel(pipe);
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	uint32_t DP;

	if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
		 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
		 pipe_name(pipe), port_name(intel_dig_port->port)))
		return;

	DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
		      pipe_name(pipe), port_name(intel_dig_port->port));

	/* Preserve the BIOS-computed detected bit. This is
	 * supposed to be read-only.
	 */
	DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
	DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
	DP |= DP_PORT_WIDTH(1);
	DP |= DP_LINK_TRAIN_PAT_1;

	if (IS_CHERRYVIEW(dev))
		DP |= DP_PIPE_SELECT_CHV(pipe);
	else if (pipe == PIPE_B)
		DP |= DP_PIPEB_SELECT;

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	pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;

	/*
	 * The DPLL for the pipe must be enabled for this to work.
	 * So enable temporarily it if it's not already enabled.
	 */
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	if (!pll_enabled) {
		release_cl_override = IS_CHERRYVIEW(dev) &&
			!chv_phy_powergate_ch(dev_priv, phy, ch, true);

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		if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
				     &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
			DRM_ERROR("Failed to force on pll for pipe %c!\n",
				  pipe_name(pipe));
			return;
		}
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	}
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	/*
	 * Similar magic as in intel_dp_enable_port().
	 * We _must_ do this port enable + disable trick
	 * to make this power seqeuencer lock onto the port.
	 * Otherwise even VDD force bit won't work.
	 */
	I915_WRITE(intel_dp->output_reg, DP);
	POSTING_READ(intel_dp->output_reg);

	I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
	POSTING_READ(intel_dp->output_reg);

	I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
	POSTING_READ(intel_dp->output_reg);
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	if (!pll_enabled) {
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		vlv_force_pll_off(dev, pipe);
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		if (release_cl_override)
			chv_phy_powergate_ch(dev_priv, phy, ch, false);
	}
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}

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static enum pipe
vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct intel_encoder *encoder;
	unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
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	enum pipe pipe;
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	lockdep_assert_held(&dev_priv->pps_mutex);
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	/* We should never land here with regular DP ports */
	WARN_ON(!is_edp(intel_dp));

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	if (intel_dp->pps_pipe != INVALID_PIPE)
		return intel_dp->pps_pipe;

	/*
	 * We don't have power sequencer currently.
	 * Pick one that's not used by other ports.
	 */
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	for_each_intel_encoder(dev, encoder) {
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		struct intel_dp *tmp;

		if (encoder->type != INTEL_OUTPUT_EDP)
			continue;

		tmp = enc_to_intel_dp(&encoder->base);

		if (tmp->pps_pipe != INVALID_PIPE)
			pipes &= ~(1 << tmp->pps_pipe);
	}

	/*
	 * Didn't find one. This should not happen since there
	 * are two power sequencers and up to two eDP ports.
	 */
	if (WARN_ON(pipes == 0))
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		pipe = PIPE_A;
	else
		pipe = ffs(pipes) - 1;
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	vlv_steal_power_sequencer(dev, pipe);
	intel_dp->pps_pipe = pipe;
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	DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
		      pipe_name(intel_dp->pps_pipe),
		      port_name(intel_dig_port->port));

	/* init power sequencer on this pipe and port */
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	intel_dp_init_panel_power_sequencer(dev, intel_dp);
	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
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	/*
	 * Even vdd force doesn't work until we've made
	 * the power sequencer lock in on the port.
	 */
	vlv_power_sequencer_kick(intel_dp);
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	return intel_dp->pps_pipe;
}

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typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
			       enum pipe pipe);

static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
			       enum pipe pipe)
{
	return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
}

static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
				enum pipe pipe)
{
	return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
}

static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
			 enum pipe pipe)
{
	return true;
}
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static enum pipe
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vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
		     enum port port,
		     vlv_pipe_check pipe_check)
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{
	enum pipe pipe;
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	for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
		u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
			PANEL_PORT_SELECT_MASK;
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		if (port_sel != PANEL_PORT_SELECT_VLV(port))
			continue;

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		if (!pipe_check(dev_priv, pipe))
			continue;

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		return pipe;
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	}

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	return INVALID_PIPE;
}

static void
vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = intel_dig_port->port;

	lockdep_assert_held(&dev_priv->pps_mutex);

	/* try to find a pipe with this port selected */
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	/* first pick one where the panel is on */
	intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
						  vlv_pipe_has_pp_on);
	/* didn't find one? pick one where vdd is on */
	if (intel_dp->pps_pipe == INVALID_PIPE)
		intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
							  vlv_pipe_has_vdd_on);
	/* didn't find one? pick one with just the correct port */
	if (intel_dp->pps_pipe == INVALID_PIPE)
		intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
							  vlv_pipe_any);
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	/* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
	if (intel_dp->pps_pipe == INVALID_PIPE) {
		DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
			      port_name(port));
		return;
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	}

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	DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
		      port_name(port), pipe_name(intel_dp->pps_pipe));

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	intel_dp_init_panel_power_sequencer(dev, intel_dp);
	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
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}

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void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
{
	struct drm_device *dev = dev_priv->dev;
	struct intel_encoder *encoder;

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	if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)))
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		return;

	/*
	 * We can't grab pps_mutex here due to deadlock with power_domain
	 * mutex when power_domain functions are called while holding pps_mutex.
	 * That also means that in order to use pps_pipe the code needs to
	 * hold both a power domain reference and pps_mutex, and the power domain
	 * reference get/put must be done while _not_ holding pps_mutex.
	 * pps_{lock,unlock}() do these steps in the correct order, so one
	 * should use them always.
	 */

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	for_each_intel_encoder(dev, encoder) {
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		struct intel_dp *intel_dp;

		if (encoder->type != INTEL_OUTPUT_EDP)
			continue;

		intel_dp = enc_to_intel_dp(&encoder->base);
		intel_dp->pps_pipe = INVALID_PIPE;
	}
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}

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static i915_reg_t
_pp_ctrl_reg(struct intel_dp *intel_dp)
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{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);

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	if (IS_BROXTON(dev))
		return BXT_PP_CONTROL(0);
	else if (HAS_PCH_SPLIT(dev))
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		return PCH_PP_CONTROL;
	else
		return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
}

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static i915_reg_t
_pp_stat_reg(struct intel_dp *intel_dp)
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{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);

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	if (IS_BROXTON(dev))
		return BXT_PP_STATUS(0);
	else if (HAS_PCH_SPLIT(dev))
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		return PCH_PP_STATUS;
	else
		return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
}

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/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
   This function only applicable when panel PM state is not to be tracked */
static int edp_notify_handler(struct notifier_block *this, unsigned long code,
			      void *unused)
{
	struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
						 edp_notifier);
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (!is_edp(intel_dp) || code != SYS_RESTART)
		return 0;

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	pps_lock(intel_dp);
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	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
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		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
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		i915_reg_t pp_ctrl_reg, pp_div_reg;
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		u32 pp_div;
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		pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
		pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
		pp_div = I915_READ(pp_div_reg);
		pp_div &= PP_REFERENCE_DIVIDER_MASK;

		/* 0x1F write to PP_DIV_REG sets max cycle delay */
		I915_WRITE(pp_div_reg, pp_div | 0x1F);
		I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
		msleep(intel_dp->panel_power_cycle_delay);
	}

596
	pps_unlock(intel_dp);
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597

598 599 600
	return 0;
}

601
static bool edp_have_panel_power(struct intel_dp *intel_dp)
602
{
603
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
604 605
	struct drm_i915_private *dev_priv = dev->dev_private;

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606 607
	lockdep_assert_held(&dev_priv->pps_mutex);

608
	if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
609 610 611
	    intel_dp->pps_pipe == INVALID_PIPE)
		return false;

612
	return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
613 614
}

615
static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
616
{
617
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
618 619
	struct drm_i915_private *dev_priv = dev->dev_private;

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620 621
	lockdep_assert_held(&dev_priv->pps_mutex);

622
	if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
623 624 625
	    intel_dp->pps_pipe == INVALID_PIPE)
		return false;

626
	return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
627 628
}

629 630 631
static void
intel_dp_check_edp(struct intel_dp *intel_dp)
{
632
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
633
	struct drm_i915_private *dev_priv = dev->dev_private;
634

635 636
	if (!is_edp(intel_dp))
		return;
637

638
	if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
639 640
		WARN(1, "eDP powered off while attempting aux channel communication.\n");
		DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
641 642
			      I915_READ(_pp_stat_reg(intel_dp)),
			      I915_READ(_pp_ctrl_reg(intel_dp)));
643 644 645
	}
}

646 647 648 649 650 651
static uint32_t
intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
652
	i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
653 654 655
	uint32_t status;
	bool done;

656
#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
657
	if (has_aux_irq)
658
		done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
659
					  msecs_to_jiffies_timeout(10));
660 661 662 663 664 665 666 667 668 669
	else
		done = wait_for_atomic(C, 10) == 0;
	if (!done)
		DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
			  has_aux_irq);
#undef C

	return status;
}

670
static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
671
{
672
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
673
	struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
674

675 676 677
	if (index)
		return 0;

678 679
	/*
	 * The clock divider is based off the hrawclk, and would like to run at
680
	 * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
681
	 */
682
	return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
683 684 685 686 687
}

static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
688
	struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
689 690 691 692

	if (index)
		return 0;

693 694 695 696 697
	/*
	 * The clock divider is based off the cdclk or PCH rawclk, and would
	 * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
	 * divide by 2000 and use that
	 */
698
	if (intel_dig_port->port == PORT_A)
699
		return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
700 701
	else
		return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
702 703 704 705 706
}

static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
707
	struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
708

709
	if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
710
		/* Workaround for non-ULT HSW */
711 712 713 714 715
		switch (index) {
		case 0: return 63;
		case 1: return 72;
		default: return 0;
		}
716
	}
717 718

	return ilk_get_aux_clock_divider(intel_dp, index);
719 720
}

721 722 723 724 725 726 727 728 729 730
static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
	/*
	 * SKL doesn't need us to program the AUX clock divider (Hardware will
	 * derive the clock from CDCLK automatically). We still implement the
	 * get_aux_clock_divider vfunc to plug-in into the existing code.
	 */
	return index ? 0 : 1;
}

731 732 733 734
static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
				     bool has_aux_irq,
				     int send_bytes,
				     uint32_t aux_clock_divider)
735 736 737 738 739 740 741 742 743 744
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	uint32_t precharge, timeout;

	if (IS_GEN6(dev))
		precharge = 3;
	else
		precharge = 5;

745
	if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A)
746 747 748 749 750
		timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
	else
		timeout = DP_AUX_CH_CTL_TIME_OUT_400us;

	return DP_AUX_CH_CTL_SEND_BUSY |
751
	       DP_AUX_CH_CTL_DONE |
752
	       (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
753
	       DP_AUX_CH_CTL_TIME_OUT_ERROR |
754
	       timeout |
755
	       DP_AUX_CH_CTL_RECEIVE_ERROR |
756 757
	       (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
	       (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
758
	       (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
759 760
}

761 762 763 764 765 766 767 768 769 770 771 772
static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
				      bool has_aux_irq,
				      int send_bytes,
				      uint32_t unused)
{
	return DP_AUX_CH_CTL_SEND_BUSY |
	       DP_AUX_CH_CTL_DONE |
	       (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
	       DP_AUX_CH_CTL_TIME_OUT_ERROR |
	       DP_AUX_CH_CTL_TIME_OUT_1600us |
	       DP_AUX_CH_CTL_RECEIVE_ERROR |
	       (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
773
	       DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
774 775 776
	       DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
}

777 778
static int
intel_dp_aux_ch(struct intel_dp *intel_dp,
779
		const uint8_t *send, int send_bytes,
780 781 782 783 784
		uint8_t *recv, int recv_size)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
785
	i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
786
	uint32_t aux_clock_divider;
787 788
	int i, ret, recv_bytes;
	uint32_t status;
789
	int try, clock = 0;
790
	bool has_aux_irq = HAS_AUX_IRQ(dev);
791 792
	bool vdd;

793
	pps_lock(intel_dp);
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794

795 796 797 798 799 800
	/*
	 * We will be called with VDD already enabled for dpcd/edid/oui reads.
	 * In such cases we want to leave VDD enabled and it's up to upper layers
	 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
	 * ourselves.
	 */
801
	vdd = edp_panel_vdd_on(intel_dp);
802 803 804 805 806 807 808 809

	/* dp aux is extremely sensitive to irq latency, hence request the
	 * lowest possible wakeup latency and so prevent the cpu from going into
	 * deep sleep states.
	 */
	pm_qos_update_request(&dev_priv->pm_qos, 0);

	intel_dp_check_edp(intel_dp);
810

811 812
	/* Try to wait for any previous AUX channel activity */
	for (try = 0; try < 3; try++) {
813
		status = I915_READ_NOTRACE(ch_ctl);
814 815 816 817 818 819
		if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
			break;
		msleep(1);
	}

	if (try == 3) {
820 821 822 823 824 825 826 827 828
		static u32 last_status = -1;
		const u32 status = I915_READ(ch_ctl);

		if (status != last_status) {
			WARN(1, "dp_aux_ch not started status 0x%08x\n",
			     status);
			last_status = status;
		}

829 830
		ret = -EBUSY;
		goto out;
831 832
	}

833 834 835 836 837 838
	/* Only 5 data registers! */
	if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
		ret = -E2BIG;
		goto out;
	}

839
	while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
840 841 842 843
		u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
							  has_aux_irq,
							  send_bytes,
							  aux_clock_divider);
844

845 846 847 848
		/* Must try at least 3 times according to DP spec */
		for (try = 0; try < 5; try++) {
			/* Load the send data into the aux channel data registers */
			for (i = 0; i < send_bytes; i += 4)
849
				I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
850 851
					   intel_dp_pack_aux(send + i,
							     send_bytes - i));
852 853

			/* Send the command and wait for it to complete */
854
			I915_WRITE(ch_ctl, send_ctl);
855 856 857 858 859 860 861 862 863 864

			status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);

			/* Clear done status and any errors */
			I915_WRITE(ch_ctl,
				   status |
				   DP_AUX_CH_CTL_DONE |
				   DP_AUX_CH_CTL_TIME_OUT_ERROR |
				   DP_AUX_CH_CTL_RECEIVE_ERROR);

865
			if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
866
				continue;
867 868 869 870 871 872 873 874

			/* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
			 *   400us delay required for errors and timeouts
			 *   Timeout errors from the HW already meet this
			 *   requirement so skip to next iteration
			 */
			if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
				usleep_range(400, 500);
875
				continue;
876
			}
877
			if (status & DP_AUX_CH_CTL_DONE)
878
				goto done;
879
		}
880 881 882
	}

	if ((status & DP_AUX_CH_CTL_DONE) == 0) {
883
		DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
884 885
		ret = -EBUSY;
		goto out;
886 887
	}

888
done:
889 890 891
	/* Check for timeout or receive error.
	 * Timeouts occur when the sink is not connected
	 */
892
	if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
893
		DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
894 895
		ret = -EIO;
		goto out;
896
	}
897 898 899

	/* Timeouts occur when the device isn't connected, so they're
	 * "normal" -- don't fill the kernel log with these */
900
	if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
901
		DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
902 903
		ret = -ETIMEDOUT;
		goto out;
904 905 906 907 908
	}

	/* Unload any bytes sent back from the other side */
	recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
		      DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929

	/*
	 * By BSpec: "Message sizes of 0 or >20 are not allowed."
	 * We have no idea of what happened so we return -EBUSY so
	 * drm layer takes care for the necessary retries.
	 */
	if (recv_bytes == 0 || recv_bytes > 20) {
		DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
			      recv_bytes);
		/*
		 * FIXME: This patch was created on top of a series that
		 * organize the retries at drm level. There EBUSY should
		 * also take care for 1ms wait before retrying.
		 * That aux retries re-org is still needed and after that is
		 * merged we remove this sleep from here.
		 */
		usleep_range(1000, 1500);
		ret = -EBUSY;
		goto out;
	}

930 931
	if (recv_bytes > recv_size)
		recv_bytes = recv_size;
932

933
	for (i = 0; i < recv_bytes; i += 4)
934
		intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
935
				    recv + i, recv_bytes - i);
936

937 938 939 940
	ret = recv_bytes;
out:
	pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);

941 942 943
	if (vdd)
		edp_panel_vdd_off(intel_dp, false);

944
	pps_unlock(intel_dp);
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945

946
	return ret;
947 948
}

949 950
#define BARE_ADDRESS_SIZE	3
#define HEADER_SIZE		(BARE_ADDRESS_SIZE + 1)
951 952
static ssize_t
intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
953
{
954 955 956
	struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
	uint8_t txbuf[20], rxbuf[20];
	size_t txsize, rxsize;
957 958
	int ret;

959 960 961
	txbuf[0] = (msg->request << 4) |
		((msg->address >> 16) & 0xf);
	txbuf[1] = (msg->address >> 8) & 0xff;
962 963
	txbuf[2] = msg->address & 0xff;
	txbuf[3] = msg->size - 1;
964

965 966 967
	switch (msg->request & ~DP_AUX_I2C_MOT) {
	case DP_AUX_NATIVE_WRITE:
	case DP_AUX_I2C_WRITE:
968
	case DP_AUX_I2C_WRITE_STATUS_UPDATE:
969
		txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
970
		rxsize = 2; /* 0 or 1 data bytes */
971

972 973
		if (WARN_ON(txsize > 20))
			return -E2BIG;
974

975 976 977 978
		if (msg->buffer)
			memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
		else
			WARN_ON(msg->size);
979

980 981 982
		ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
		if (ret > 0) {
			msg->reply = rxbuf[0] >> 4;
983

984 985 986 987 988 989 990
			if (ret > 1) {
				/* Number of bytes written in a short write. */
				ret = clamp_t(int, rxbuf[1], 0, msg->size);
			} else {
				/* Return payload size. */
				ret = msg->size;
			}
991 992
		}
		break;
993

994 995
	case DP_AUX_NATIVE_READ:
	case DP_AUX_I2C_READ:
996
		txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
997
		rxsize = msg->size + 1;
998

999 1000
		if (WARN_ON(rxsize > 20))
			return -E2BIG;
1001

1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012
		ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
		if (ret > 0) {
			msg->reply = rxbuf[0] >> 4;
			/*
			 * Assume happy day, and copy the data. The caller is
			 * expected to check msg->reply before touching it.
			 *
			 * Return payload size.
			 */
			ret--;
			memcpy(msg->buffer, rxbuf + 1, ret);
1013
		}
1014 1015 1016 1017 1018
		break;

	default:
		ret = -EINVAL;
		break;
1019
	}
1020

1021
	return ret;
1022 1023
}

1024 1025
static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
				       enum port port)
1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037
{
	switch (port) {
	case PORT_B:
	case PORT_C:
	case PORT_D:
		return DP_AUX_CH_CTL(port);
	default:
		MISSING_CASE(port);
		return DP_AUX_CH_CTL(PORT_B);
	}
}

1038 1039
static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
					enum port port, int index)
1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051
{
	switch (port) {
	case PORT_B:
	case PORT_C:
	case PORT_D:
		return DP_AUX_CH_DATA(port, index);
	default:
		MISSING_CASE(port);
		return DP_AUX_CH_DATA(PORT_B, index);
	}
}

1052 1053
static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
				       enum port port)
1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067
{
	switch (port) {
	case PORT_A:
		return DP_AUX_CH_CTL(port);
	case PORT_B:
	case PORT_C:
	case PORT_D:
		return PCH_DP_AUX_CH_CTL(port);
	default:
		MISSING_CASE(port);
		return DP_AUX_CH_CTL(PORT_A);
	}
}

1068 1069
static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
					enum port port, int index)
1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083
{
	switch (port) {
	case PORT_A:
		return DP_AUX_CH_DATA(port, index);
	case PORT_B:
	case PORT_C:
	case PORT_D:
		return PCH_DP_AUX_CH_DATA(port, index);
	default:
		MISSING_CASE(port);
		return DP_AUX_CH_DATA(PORT_A, index);
	}
}

1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107
/*
 * On SKL we don't have Aux for port E so we rely
 * on VBT to set a proper alternate aux channel.
 */
static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
{
	const struct ddi_vbt_port_info *info =
		&dev_priv->vbt.ddi_port_info[PORT_E];

	switch (info->alternate_aux_channel) {
	case DP_AUX_A:
		return PORT_A;
	case DP_AUX_B:
		return PORT_B;
	case DP_AUX_C:
		return PORT_C;
	case DP_AUX_D:
		return PORT_D;
	default:
		MISSING_CASE(info->alternate_aux_channel);
		return PORT_A;
	}
}

1108 1109
static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
				       enum port port)
1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125
{
	if (port == PORT_E)
		port = skl_porte_aux_port(dev_priv);

	switch (port) {
	case PORT_A:
	case PORT_B:
	case PORT_C:
	case PORT_D:
		return DP_AUX_CH_CTL(port);
	default:
		MISSING_CASE(port);
		return DP_AUX_CH_CTL(PORT_A);
	}
}

1126 1127
static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
					enum port port, int index)
1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143
{
	if (port == PORT_E)
		port = skl_porte_aux_port(dev_priv);

	switch (port) {
	case PORT_A:
	case PORT_B:
	case PORT_C:
	case PORT_D:
		return DP_AUX_CH_DATA(port, index);
	default:
		MISSING_CASE(port);
		return DP_AUX_CH_DATA(PORT_A, index);
	}
}

1144 1145
static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
					 enum port port)
1146 1147 1148 1149 1150 1151 1152 1153 1154
{
	if (INTEL_INFO(dev_priv)->gen >= 9)
		return skl_aux_ctl_reg(dev_priv, port);
	else if (HAS_PCH_SPLIT(dev_priv))
		return ilk_aux_ctl_reg(dev_priv, port);
	else
		return g4x_aux_ctl_reg(dev_priv, port);
}

1155 1156
static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
					  enum port port, int index)
1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176
{
	if (INTEL_INFO(dev_priv)->gen >= 9)
		return skl_aux_data_reg(dev_priv, port, index);
	else if (HAS_PCH_SPLIT(dev_priv))
		return ilk_aux_data_reg(dev_priv, port, index);
	else
		return g4x_aux_data_reg(dev_priv, port, index);
}

static void intel_aux_reg_init(struct intel_dp *intel_dp)
{
	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
	enum port port = dp_to_dig_port(intel_dp)->port;
	int i;

	intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
	for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
		intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
}

1177
static void
1178 1179 1180 1181 1182 1183 1184
intel_dp_aux_fini(struct intel_dp *intel_dp)
{
	drm_dp_aux_unregister(&intel_dp->aux);
	kfree(intel_dp->aux.name);
}

static int
1185 1186
intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
{
1187 1188
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	enum port port = intel_dig_port->port;
1189 1190
	int ret;

1191
	intel_aux_reg_init(intel_dp);
1192

1193 1194 1195 1196
	intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
	if (!intel_dp->aux.name)
		return -ENOMEM;

1197
	intel_dp->aux.dev = connector->base.kdev;
1198
	intel_dp->aux.transfer = intel_dp_aux_transfer;
1199

1200 1201
	DRM_DEBUG_KMS("registering %s bus for %s\n",
		      intel_dp->aux.name,
1202
		      connector->base.kdev->kobj.name);
1203

1204
	ret = drm_dp_aux_register(&intel_dp->aux);
1205
	if (ret < 0) {
1206
		DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1207 1208 1209
			  intel_dp->aux.name, ret);
		kfree(intel_dp->aux.name);
		return ret;
1210
	}
1211

1212
	return 0;
1213 1214
}

1215 1216 1217 1218 1219
static void
intel_dp_connector_unregister(struct intel_connector *intel_connector)
{
	struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);

1220
	intel_dp_aux_fini(intel_dp);
1221 1222 1223
	intel_connector_unregister(intel_connector);
}

1224
static int
1225
intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
1226
{
1227 1228 1229
	if (intel_dp->num_sink_rates) {
		*sink_rates = intel_dp->sink_rates;
		return intel_dp->num_sink_rates;
1230
	}
1231 1232 1233 1234

	*sink_rates = default_rates;

	return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
1235 1236
}

1237
bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1238
{
1239 1240 1241
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;

1242
	/* WaDisableHBR2:skl */
1243
	if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
1244 1245 1246 1247 1248 1249 1250 1251 1252
		return false;

	if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
	    (INTEL_INFO(dev)->gen >= 9))
		return true;
	else
		return false;
}

1253
static int
1254
intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
1255
{
1256 1257
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
1258 1259
	int size;

1260 1261
	if (IS_BROXTON(dev)) {
		*source_rates = bxt_rates;
1262
		size = ARRAY_SIZE(bxt_rates);
1263
	} else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1264
		*source_rates = skl_rates;
1265 1266 1267 1268
		size = ARRAY_SIZE(skl_rates);
	} else {
		*source_rates = default_rates;
		size = ARRAY_SIZE(default_rates);
1269
	}
1270

1271
	/* This depends on the fact that 5.4 is last value in the array */
1272
	if (!intel_dp_source_supports_hbr2(intel_dp))
1273
		size--;
1274

1275
	return size;
1276 1277
}

1278 1279
static void
intel_dp_set_clock(struct intel_encoder *encoder,
1280
		   struct intel_crtc_state *pipe_config)
1281 1282
{
	struct drm_device *dev = encoder->base.dev;
1283 1284
	const struct dp_link_dpll *divisor = NULL;
	int i, count = 0;
1285 1286

	if (IS_G4X(dev)) {
1287 1288
		divisor = gen4_dpll;
		count = ARRAY_SIZE(gen4_dpll);
1289
	} else if (HAS_PCH_SPLIT(dev)) {
1290 1291
		divisor = pch_dpll;
		count = ARRAY_SIZE(pch_dpll);
1292 1293 1294
	} else if (IS_CHERRYVIEW(dev)) {
		divisor = chv_dpll;
		count = ARRAY_SIZE(chv_dpll);
1295
	} else if (IS_VALLEYVIEW(dev)) {
1296 1297
		divisor = vlv_dpll;
		count = ARRAY_SIZE(vlv_dpll);
1298
	}
1299 1300 1301

	if (divisor && count) {
		for (i = 0; i < count; i++) {
1302
			if (pipe_config->port_clock == divisor[i].clock) {
1303 1304 1305 1306 1307
				pipe_config->dpll = divisor[i].dpll;
				pipe_config->clock_set = true;
				break;
			}
		}
1308 1309 1310
	}
}

1311 1312
static int intersect_rates(const int *source_rates, int source_len,
			   const int *sink_rates, int sink_len,
1313
			   int *common_rates)
1314 1315 1316 1317 1318
{
	int i = 0, j = 0, k = 0;

	while (i < source_len && j < sink_len) {
		if (source_rates[i] == sink_rates[j]) {
1319 1320
			if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
				return k;
1321
			common_rates[k] = source_rates[i];
1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333
			++k;
			++i;
			++j;
		} else if (source_rates[i] < sink_rates[j]) {
			++i;
		} else {
			++j;
		}
	}
	return k;
}

1334 1335
static int intel_dp_common_rates(struct intel_dp *intel_dp,
				 int *common_rates)
1336 1337 1338 1339 1340
{
	const int *source_rates, *sink_rates;
	int source_len, sink_len;

	sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1341
	source_len = intel_dp_source_rates(intel_dp, &source_rates);
1342 1343 1344

	return intersect_rates(source_rates, source_len,
			       sink_rates, sink_len,
1345
			       common_rates);
1346 1347
}

1348 1349 1350 1351 1352 1353 1354 1355
static void snprintf_int_array(char *str, size_t len,
			       const int *array, int nelem)
{
	int i;

	str[0] = '\0';

	for (i = 0; i < nelem; i++) {
1356
		int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1357 1358 1359 1360 1361 1362 1363 1364 1365 1366
		if (r >= len)
			return;
		str += r;
		len -= r;
	}
}

static void intel_dp_print_rates(struct intel_dp *intel_dp)
{
	const int *source_rates, *sink_rates;
1367 1368
	int source_len, sink_len, common_len;
	int common_rates[DP_MAX_SUPPORTED_RATES];
1369 1370 1371 1372 1373
	char str[128]; /* FIXME: too big for stack? */

	if ((drm_debug & DRM_UT_KMS) == 0)
		return;

1374
	source_len = intel_dp_source_rates(intel_dp, &source_rates);
1375 1376 1377 1378 1379 1380 1381
	snprintf_int_array(str, sizeof(str), source_rates, source_len);
	DRM_DEBUG_KMS("source rates: %s\n", str);

	sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
	snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
	DRM_DEBUG_KMS("sink rates: %s\n", str);

1382 1383 1384
	common_len = intel_dp_common_rates(intel_dp, common_rates);
	snprintf_int_array(str, sizeof(str), common_rates, common_len);
	DRM_DEBUG_KMS("common rates: %s\n", str);
1385 1386
}

1387
static int rate_to_index(int find, const int *rates)
1388 1389 1390 1391 1392 1393 1394 1395 1396 1397
{
	int i = 0;

	for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
		if (find == rates[i])
			break;

	return i;
}

1398 1399 1400 1401 1402 1403
int
intel_dp_max_link_rate(struct intel_dp *intel_dp)
{
	int rates[DP_MAX_SUPPORTED_RATES] = {};
	int len;

1404
	len = intel_dp_common_rates(intel_dp, rates);
1405 1406 1407 1408 1409 1410
	if (WARN_ON(len <= 0))
		return 162000;

	return rates[rate_to_index(0, rates) - 1];
}

1411 1412
int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
{
1413
	return rate_to_index(rate, intel_dp->sink_rates);
1414 1415
}

1416 1417
void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
			   uint8_t *link_bw, uint8_t *rate_select)
1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428
{
	if (intel_dp->num_sink_rates) {
		*link_bw = 0;
		*rate_select =
			intel_dp_rate_select(intel_dp, port_clock);
	} else {
		*link_bw = drm_dp_link_rate_to_bw_code(port_clock);
		*rate_select = 0;
	}
}

P
Paulo Zanoni 已提交
1429
bool
1430
intel_dp_compute_config(struct intel_encoder *encoder,
1431
			struct intel_crtc_state *pipe_config)
1432
{
1433
	struct drm_device *dev = encoder->base.dev;
1434
	struct drm_i915_private *dev_priv = dev->dev_private;
1435
	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1436
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1437
	enum port port = dp_to_dig_port(intel_dp)->port;
1438
	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1439
	struct intel_connector *intel_connector = intel_dp->attached_connector;
1440
	int lane_count, clock;
1441
	int min_lane_count = 1;
1442
	int max_lane_count = intel_dp_max_lane_count(intel_dp);
1443
	/* Conveniently, the link BW constants become indices with a shift...*/
1444
	int min_clock = 0;
1445
	int max_clock;
1446
	int bpp, mode_rate;
1447
	int link_avail, link_clock;
1448 1449
	int common_rates[DP_MAX_SUPPORTED_RATES] = {};
	int common_len;
1450
	uint8_t link_bw, rate_select;
1451

1452
	common_len = intel_dp_common_rates(intel_dp, common_rates);
1453 1454

	/* No common link rates between source and sink */
1455
	WARN_ON(common_len <= 0);
1456

1457
	max_clock = common_len - 1;
1458

1459
	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
1460 1461
		pipe_config->has_pch_encoder = true;

1462
	pipe_config->has_dp_encoder = true;
1463
	pipe_config->has_drrs = false;
1464
	pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
1465

1466 1467 1468
	if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
		intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
				       adjusted_mode);
1469 1470 1471

		if (INTEL_INFO(dev)->gen >= 9) {
			int ret;
1472
			ret = skl_update_scaler_crtc(pipe_config);
1473 1474 1475 1476
			if (ret)
				return ret;
		}

1477
		if (HAS_GMCH_DISPLAY(dev))
1478 1479 1480
			intel_gmch_panel_fitting(intel_crtc, pipe_config,
						 intel_connector->panel.fitting_mode);
		else
1481 1482
			intel_pch_panel_fitting(intel_crtc, pipe_config,
						intel_connector->panel.fitting_mode);
1483 1484
	}

1485
	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1486 1487
		return false;

1488
	DRM_DEBUG_KMS("DP link computation with max lane count %i "
1489
		      "max bw %d pixel clock %iKHz\n",
1490
		      max_lane_count, common_rates[max_clock],
1491
		      adjusted_mode->crtc_clock);
1492

1493 1494
	/* Walk through all bpp values. Luckily they're all nicely spaced with 2
	 * bpc in between. */
1495
	bpp = pipe_config->pipe_bpp;
1496
	if (is_edp(intel_dp)) {
1497 1498 1499

		/* Get bpp from vbt only for panels that dont have bpp in edid */
		if (intel_connector->base.display_info.bpc == 0 &&
1500
			(dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
1501
			DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1502 1503
				      dev_priv->vbt.edp.bpp);
			bpp = dev_priv->vbt.edp.bpp;
1504 1505
		}

1506 1507 1508 1509 1510 1511 1512 1513 1514
		/*
		 * Use the maximum clock and number of lanes the eDP panel
		 * advertizes being capable of. The panels are generally
		 * designed to support only a single clock and lane
		 * configuration, and typically these values correspond to the
		 * native resolution of the panel.
		 */
		min_lane_count = max_lane_count;
		min_clock = max_clock;
1515
	}
1516

1517
	for (; bpp >= 6*3; bpp -= 2*3) {
1518 1519
		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
						   bpp);
1520

1521
		for (clock = min_clock; clock <= max_clock; clock++) {
1522 1523 1524 1525
			for (lane_count = min_lane_count;
				lane_count <= max_lane_count;
				lane_count <<= 1) {

1526
				link_clock = common_rates[clock];
1527 1528 1529 1530 1531 1532 1533 1534 1535
				link_avail = intel_dp_max_data_rate(link_clock,
								    lane_count);

				if (mode_rate <= link_avail) {
					goto found;
				}
			}
		}
	}
1536

1537
	return false;
1538

1539
found:
1540 1541 1542 1543 1544 1545
	if (intel_dp->color_range_auto) {
		/*
		 * See:
		 * CEA-861-E - 5.1 Default Encoding Parameters
		 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
		 */
1546 1547 1548 1549 1550
		pipe_config->limited_color_range =
			bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
	} else {
		pipe_config->limited_color_range =
			intel_dp->limited_color_range;
1551 1552
	}

1553
	pipe_config->lane_count = lane_count;
1554

1555
	pipe_config->pipe_bpp = bpp;
1556
	pipe_config->port_clock = common_rates[clock];
1557

1558 1559 1560 1561 1562
	intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
			      &link_bw, &rate_select);

	DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
		      link_bw, rate_select, pipe_config->lane_count,
1563
		      pipe_config->port_clock, bpp);
1564 1565
	DRM_DEBUG_KMS("DP link bw required %i available %i\n",
		      mode_rate, link_avail);
1566

1567
	intel_link_compute_m_n(bpp, lane_count,
1568 1569
			       adjusted_mode->crtc_clock,
			       pipe_config->port_clock,
1570
			       &pipe_config->dp_m_n);
1571

1572
	if (intel_connector->panel.downclock_mode != NULL &&
1573
		dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1574
			pipe_config->has_drrs = true;
1575 1576 1577 1578 1579 1580
			intel_link_compute_m_n(bpp, lane_count,
				intel_connector->panel.downclock_mode->clock,
				pipe_config->port_clock,
				&pipe_config->dp_m2_n2);
	}

1581
	if (!HAS_DDI(dev))
1582
		intel_dp_set_clock(encoder, pipe_config);
1583

1584
	return true;
1585 1586
}

1587 1588 1589 1590 1591 1592 1593
void intel_dp_set_link_params(struct intel_dp *intel_dp,
			      const struct intel_crtc_state *pipe_config)
{
	intel_dp->link_rate = pipe_config->port_clock;
	intel_dp->lane_count = pipe_config->lane_count;
}

1594
static void intel_dp_prepare(struct intel_encoder *encoder)
1595
{
1596
	struct drm_device *dev = encoder->base.dev;
1597
	struct drm_i915_private *dev_priv = dev->dev_private;
1598
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1599
	enum port port = dp_to_dig_port(intel_dp)->port;
1600
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1601
	const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
1602

1603 1604
	intel_dp_set_link_params(intel_dp, crtc->config);

1605
	/*
K
Keith Packard 已提交
1606
	 * There are four kinds of DP registers:
1607 1608
	 *
	 * 	IBX PCH
K
Keith Packard 已提交
1609 1610
	 * 	SNB CPU
	 *	IVB CPU
1611 1612 1613 1614 1615 1616 1617 1618 1619 1620
	 * 	CPT PCH
	 *
	 * IBX PCH and CPU are the same for almost everything,
	 * except that the CPU DP PLL is configured in this
	 * register
	 *
	 * CPT PCH is quite different, having many bits moved
	 * to the TRANS_DP_CTL register instead. That
	 * configuration happens (oddly) in ironlake_pch_enable
	 */
1621

1622 1623 1624 1625
	/* Preserve the BIOS-computed detected bit. This is
	 * supposed to be read-only.
	 */
	intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1626

1627 1628
	/* Handle DP bits in common between all three register formats */
	intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1629
	intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count);
1630

1631
	/* Split out the IBX/CPU vs CPT settings */
1632

1633
	if (IS_GEN7(dev) && port == PORT_A) {
K
Keith Packard 已提交
1634 1635 1636 1637 1638 1639
		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
			intel_dp->DP |= DP_SYNC_HS_HIGH;
		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
			intel_dp->DP |= DP_SYNC_VS_HIGH;
		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;

1640
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
K
Keith Packard 已提交
1641 1642
			intel_dp->DP |= DP_ENHANCED_FRAMING;

1643
		intel_dp->DP |= crtc->pipe << 29;
1644
	} else if (HAS_PCH_CPT(dev) && port != PORT_A) {
1645 1646
		u32 trans_dp;

1647
		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1648 1649 1650 1651 1652 1653 1654

		trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
			trans_dp |= TRANS_DP_ENH_FRAMING;
		else
			trans_dp &= ~TRANS_DP_ENH_FRAMING;
		I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1655
	} else {
1656
		if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
1657
		    !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range)
1658
			intel_dp->DP |= DP_COLOR_RANGE_16_235;
1659 1660 1661 1662 1663 1664 1665

		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
			intel_dp->DP |= DP_SYNC_HS_HIGH;
		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
			intel_dp->DP |= DP_SYNC_VS_HIGH;
		intel_dp->DP |= DP_LINK_TRAIN_OFF;

1666
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1667 1668
			intel_dp->DP |= DP_ENHANCED_FRAMING;

1669
		if (IS_CHERRYVIEW(dev))
1670
			intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1671 1672
		else if (crtc->pipe == PIPE_B)
			intel_dp->DP |= DP_PIPEB_SELECT;
1673
	}
1674 1675
}

1676 1677
#define IDLE_ON_MASK		(PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
#define IDLE_ON_VALUE   	(PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1678

1679 1680
#define IDLE_OFF_MASK		(PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
#define IDLE_OFF_VALUE		(0     | PP_SEQUENCE_NONE | 0                     | 0)
1681

1682 1683
#define IDLE_CYCLE_MASK		(PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
#define IDLE_CYCLE_VALUE	(0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1684

1685
static void wait_panel_status(struct intel_dp *intel_dp,
1686 1687
				       u32 mask,
				       u32 value)
1688
{
1689
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1690
	struct drm_i915_private *dev_priv = dev->dev_private;
1691
	i915_reg_t pp_stat_reg, pp_ctrl_reg;
1692

V
Ville Syrjälä 已提交
1693 1694
	lockdep_assert_held(&dev_priv->pps_mutex);

1695 1696
	pp_stat_reg = _pp_stat_reg(intel_dp);
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1697

1698
	DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1699 1700 1701
			mask, value,
			I915_READ(pp_stat_reg),
			I915_READ(pp_ctrl_reg));
1702

T
Tvrtko Ursulin 已提交
1703 1704
	if (_wait_for((I915_READ(pp_stat_reg) & mask) == value,
		      5 * USEC_PER_SEC, 10 * USEC_PER_MSEC))
1705
		DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1706 1707
				I915_READ(pp_stat_reg),
				I915_READ(pp_ctrl_reg));
1708 1709

	DRM_DEBUG_KMS("Wait complete\n");
1710
}
1711

1712
static void wait_panel_on(struct intel_dp *intel_dp)
1713 1714
{
	DRM_DEBUG_KMS("Wait for panel power on\n");
1715
	wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1716 1717
}

1718
static void wait_panel_off(struct intel_dp *intel_dp)
1719 1720
{
	DRM_DEBUG_KMS("Wait for panel power off time\n");
1721
	wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1722 1723
}

1724
static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1725
{
1726 1727 1728
	ktime_t panel_power_on_time;
	s64 panel_power_off_duration;

1729
	DRM_DEBUG_KMS("Wait for panel power cycle\n");
1730

1731 1732 1733 1734 1735
	/* take the difference of currrent time and panel power off time
	 * and then make panel wait for t11_t12 if needed. */
	panel_power_on_time = ktime_get_boottime();
	panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);

1736 1737
	/* When we disable the VDD override bit last we have to do the manual
	 * wait. */
1738 1739 1740
	if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
		wait_remaining_ms_from_jiffies(jiffies,
				       intel_dp->panel_power_cycle_delay - panel_power_off_duration);
1741

1742
	wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1743 1744
}

1745
static void wait_backlight_on(struct intel_dp *intel_dp)
1746 1747 1748 1749 1750
{
	wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
				       intel_dp->backlight_on_delay);
}

1751
static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1752 1753 1754 1755
{
	wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
				       intel_dp->backlight_off_delay);
}
1756

1757 1758 1759 1760
/* Read the current pp_control value, unlocking the register if it
 * is locked
 */

1761
static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1762
{
1763 1764 1765
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 control;
1766

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1767 1768
	lockdep_assert_held(&dev_priv->pps_mutex);

1769
	control = I915_READ(_pp_ctrl_reg(intel_dp));
1770 1771 1772 1773
	if (!IS_BROXTON(dev)) {
		control &= ~PANEL_UNLOCK_MASK;
		control |= PANEL_UNLOCK_REGS;
	}
1774
	return control;
1775 1776
}

1777 1778 1779 1780 1781
/*
 * Must be paired with edp_panel_vdd_off().
 * Must hold pps_mutex around the whole on/off sequence.
 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
 */
1782
static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1783
{
1784
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1785 1786
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
1787
	struct drm_i915_private *dev_priv = dev->dev_private;
1788
	enum intel_display_power_domain power_domain;
1789
	u32 pp;
1790
	i915_reg_t pp_stat_reg, pp_ctrl_reg;
1791
	bool need_to_disable = !intel_dp->want_panel_vdd;
1792

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1793 1794
	lockdep_assert_held(&dev_priv->pps_mutex);

1795
	if (!is_edp(intel_dp))
1796
		return false;
1797

1798
	cancel_delayed_work(&intel_dp->panel_vdd_work);
1799
	intel_dp->want_panel_vdd = true;
1800

1801
	if (edp_have_panel_vdd(intel_dp))
1802
		return need_to_disable;
1803

1804
	power_domain = intel_display_port_aux_power_domain(intel_encoder);
1805
	intel_display_power_get(dev_priv, power_domain);
1806

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1807 1808
	DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
		      port_name(intel_dig_port->port));
1809

1810 1811
	if (!edp_have_panel_power(intel_dp))
		wait_panel_power_cycle(intel_dp);
1812

1813
	pp = ironlake_get_pp_control(intel_dp);
1814
	pp |= EDP_FORCE_VDD;
1815

1816 1817
	pp_stat_reg = _pp_stat_reg(intel_dp);
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1818 1819 1820 1821 1822

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
	DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
			I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1823 1824 1825
	/*
	 * If the panel wasn't on, delay before accessing aux channel
	 */
1826
	if (!edp_have_panel_power(intel_dp)) {
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1827 1828
		DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
			      port_name(intel_dig_port->port));
1829 1830
		msleep(intel_dp->panel_power_up_delay);
	}
1831 1832 1833 1834

	return need_to_disable;
}

1835 1836 1837 1838 1839 1840 1841
/*
 * Must be paired with intel_edp_panel_vdd_off() or
 * intel_edp_panel_off().
 * Nested calls to these functions are not allowed since
 * we drop the lock. Caller must use some higher level
 * locking to prevent nested calls from other threads.
 */
1842
void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1843
{
1844
	bool vdd;
1845

1846 1847 1848
	if (!is_edp(intel_dp))
		return;

1849
	pps_lock(intel_dp);
1850
	vdd = edp_panel_vdd_on(intel_dp);
1851
	pps_unlock(intel_dp);
1852

R
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1853
	I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
V
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1854
	     port_name(dp_to_dig_port(intel_dp)->port));
1855 1856
}

1857
static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1858
{
1859
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1860
	struct drm_i915_private *dev_priv = dev->dev_private;
1861 1862 1863 1864
	struct intel_digital_port *intel_dig_port =
		dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	enum intel_display_power_domain power_domain;
1865
	u32 pp;
1866
	i915_reg_t pp_stat_reg, pp_ctrl_reg;
1867

V
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1868
	lockdep_assert_held(&dev_priv->pps_mutex);
1869

1870
	WARN_ON(intel_dp->want_panel_vdd);
1871

1872
	if (!edp_have_panel_vdd(intel_dp))
1873
		return;
1874

V
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1875 1876
	DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
		      port_name(intel_dig_port->port));
1877

1878 1879
	pp = ironlake_get_pp_control(intel_dp);
	pp &= ~EDP_FORCE_VDD;
1880

1881 1882
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
	pp_stat_reg = _pp_stat_reg(intel_dp);
1883

1884 1885
	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
P
Paulo Zanoni 已提交
1886

1887 1888 1889
	/* Make sure sequencer is idle before allowing subsequent activity */
	DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
	I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1890

1891
	if ((pp & POWER_TARGET_ON) == 0)
1892
		intel_dp->panel_power_off_time = ktime_get_boottime();
1893

1894
	power_domain = intel_display_port_aux_power_domain(intel_encoder);
1895
	intel_display_power_put(dev_priv, power_domain);
1896
}
1897

1898
static void edp_panel_vdd_work(struct work_struct *__work)
1899 1900 1901 1902
{
	struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
						 struct intel_dp, panel_vdd_work);

1903
	pps_lock(intel_dp);
1904 1905
	if (!intel_dp->want_panel_vdd)
		edp_panel_vdd_off_sync(intel_dp);
1906
	pps_unlock(intel_dp);
1907 1908
}

1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921
static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
{
	unsigned long delay;

	/*
	 * Queue the timer to fire a long time from now (relative to the power
	 * down delay) to keep the panel power up across a sequence of
	 * operations.
	 */
	delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
	schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
}

1922 1923 1924 1925 1926
/*
 * Must be paired with edp_panel_vdd_on().
 * Must hold pps_mutex around the whole on/off sequence.
 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
 */
1927
static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1928
{
V
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1929 1930 1931 1932 1933
	struct drm_i915_private *dev_priv =
		intel_dp_to_dev(intel_dp)->dev_private;

	lockdep_assert_held(&dev_priv->pps_mutex);

1934 1935
	if (!is_edp(intel_dp))
		return;
1936

R
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1937
	I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
V
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1938
	     port_name(dp_to_dig_port(intel_dp)->port));
1939

1940 1941
	intel_dp->want_panel_vdd = false;

1942
	if (sync)
1943
		edp_panel_vdd_off_sync(intel_dp);
1944 1945
	else
		edp_panel_vdd_schedule_off(intel_dp);
1946 1947
}

1948
static void edp_panel_on(struct intel_dp *intel_dp)
1949
{
1950
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1951
	struct drm_i915_private *dev_priv = dev->dev_private;
1952
	u32 pp;
1953
	i915_reg_t pp_ctrl_reg;
1954

1955 1956
	lockdep_assert_held(&dev_priv->pps_mutex);

1957
	if (!is_edp(intel_dp))
1958
		return;
1959

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1960 1961
	DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
		      port_name(dp_to_dig_port(intel_dp)->port));
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1962

1963 1964 1965
	if (WARN(edp_have_panel_power(intel_dp),
		 "eDP port %c panel power already on\n",
		 port_name(dp_to_dig_port(intel_dp)->port)))
1966
		return;
1967

1968
	wait_panel_power_cycle(intel_dp);
1969

1970
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1971
	pp = ironlake_get_pp_control(intel_dp);
1972 1973 1974
	if (IS_GEN5(dev)) {
		/* ILK workaround: disable reset around power sequence */
		pp &= ~PANEL_POWER_RESET;
1975 1976
		I915_WRITE(pp_ctrl_reg, pp);
		POSTING_READ(pp_ctrl_reg);
1977
	}
1978

1979
	pp |= POWER_TARGET_ON;
1980 1981 1982
	if (!IS_GEN5(dev))
		pp |= PANEL_POWER_RESET;

1983 1984
	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1985

1986
	wait_panel_on(intel_dp);
1987
	intel_dp->last_power_on = jiffies;
1988

1989 1990
	if (IS_GEN5(dev)) {
		pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1991 1992
		I915_WRITE(pp_ctrl_reg, pp);
		POSTING_READ(pp_ctrl_reg);
1993
	}
1994
}
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1995

1996 1997 1998 1999 2000 2001 2002
void intel_edp_panel_on(struct intel_dp *intel_dp)
{
	if (!is_edp(intel_dp))
		return;

	pps_lock(intel_dp);
	edp_panel_on(intel_dp);
2003
	pps_unlock(intel_dp);
2004 2005
}

2006 2007

static void edp_panel_off(struct intel_dp *intel_dp)
2008
{
2009 2010
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
2011
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2012
	struct drm_i915_private *dev_priv = dev->dev_private;
2013
	enum intel_display_power_domain power_domain;
2014
	u32 pp;
2015
	i915_reg_t pp_ctrl_reg;
2016

2017 2018
	lockdep_assert_held(&dev_priv->pps_mutex);

2019 2020
	if (!is_edp(intel_dp))
		return;
2021

V
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2022 2023
	DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
		      port_name(dp_to_dig_port(intel_dp)->port));
2024

V
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2025 2026
	WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
	     port_name(dp_to_dig_port(intel_dp)->port));
2027

2028
	pp = ironlake_get_pp_control(intel_dp);
2029 2030
	/* We need to switch off panel power _and_ force vdd, for otherwise some
	 * panels get very unhappy and cease to work. */
2031 2032
	pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
		EDP_BLC_ENABLE);
2033

2034
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2035

2036 2037
	intel_dp->want_panel_vdd = false;

2038 2039
	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
2040

2041
	intel_dp->panel_power_off_time = ktime_get_boottime();
2042
	wait_panel_off(intel_dp);
2043 2044

	/* We got a reference when we enabled the VDD. */
2045
	power_domain = intel_display_port_aux_power_domain(intel_encoder);
2046
	intel_display_power_put(dev_priv, power_domain);
2047
}
V
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2048

2049 2050 2051 2052
void intel_edp_panel_off(struct intel_dp *intel_dp)
{
	if (!is_edp(intel_dp))
		return;
V
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2053

2054 2055
	pps_lock(intel_dp);
	edp_panel_off(intel_dp);
2056
	pps_unlock(intel_dp);
2057 2058
}

2059 2060
/* Enable backlight in the panel power control. */
static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2061
{
2062 2063
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
2064 2065
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
2066
	i915_reg_t pp_ctrl_reg;
2067

2068 2069 2070 2071 2072 2073
	/*
	 * If we enable the backlight right away following a panel power
	 * on, we may see slight flicker as the panel syncs with the eDP
	 * link.  So delay a bit to make sure the image is solid before
	 * allowing it to appear.
	 */
2074
	wait_backlight_on(intel_dp);
V
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2075

2076
	pps_lock(intel_dp);
V
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2077

2078
	pp = ironlake_get_pp_control(intel_dp);
2079
	pp |= EDP_BLC_ENABLE;
2080

2081
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2082 2083 2084

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
V
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2085

2086
	pps_unlock(intel_dp);
2087 2088
}

2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102
/* Enable backlight PWM and backlight PP control. */
void intel_edp_backlight_on(struct intel_dp *intel_dp)
{
	if (!is_edp(intel_dp))
		return;

	DRM_DEBUG_KMS("\n");

	intel_panel_enable_backlight(intel_dp->attached_connector);
	_intel_edp_backlight_on(intel_dp);
}

/* Disable backlight in the panel power control. */
static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2103
{
2104
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2105 2106
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
2107
	i915_reg_t pp_ctrl_reg;
2108

2109 2110 2111
	if (!is_edp(intel_dp))
		return;

2112
	pps_lock(intel_dp);
V
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2113

2114
	pp = ironlake_get_pp_control(intel_dp);
2115
	pp &= ~EDP_BLC_ENABLE;
2116

2117
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2118 2119 2120

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
2121

2122
	pps_unlock(intel_dp);
V
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2123 2124

	intel_dp->last_backlight_off = jiffies;
2125
	edp_wait_backlight_off(intel_dp);
2126
}
2127

2128 2129 2130 2131 2132 2133 2134
/* Disable backlight PP control and backlight PWM. */
void intel_edp_backlight_off(struct intel_dp *intel_dp)
{
	if (!is_edp(intel_dp))
		return;

	DRM_DEBUG_KMS("\n");
2135

2136
	_intel_edp_backlight_off(intel_dp);
2137
	intel_panel_disable_backlight(intel_dp->attached_connector);
2138
}
2139

2140 2141 2142 2143 2144 2145 2146 2147
/*
 * Hook for controlling the panel power control backlight through the bl_power
 * sysfs attribute. Take care to handle multiple calls.
 */
static void intel_edp_backlight_power(struct intel_connector *connector,
				      bool enable)
{
	struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
V
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2148 2149
	bool is_enabled;

2150
	pps_lock(intel_dp);
V
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2151
	is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2152
	pps_unlock(intel_dp);
2153 2154 2155 2156

	if (is_enabled == enable)
		return;

2157 2158
	DRM_DEBUG_KMS("panel power control backlight %s\n",
		      enable ? "enable" : "disable");
2159 2160 2161 2162 2163 2164 2165

	if (enable)
		_intel_edp_backlight_on(intel_dp);
	else
		_intel_edp_backlight_off(intel_dp);
}

2166 2167 2168 2169 2170 2171 2172 2173 2174
static void assert_dp_port(struct intel_dp *intel_dp, bool state)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
	bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;

	I915_STATE_WARN(cur_state != state,
			"DP port %c state assertion failure (expected %s, current %s)\n",
			port_name(dig_port->port),
2175
			onoff(state), onoff(cur_state));
2176 2177 2178 2179 2180 2181 2182 2183 2184
}
#define assert_dp_port_disabled(d) assert_dp_port((d), false)

static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
{
	bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;

	I915_STATE_WARN(cur_state != state,
			"eDP PLL state assertion failure (expected %s, current %s)\n",
2185
			onoff(state), onoff(cur_state));
2186 2187 2188 2189
}
#define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
#define assert_edp_pll_disabled(d) assert_edp_pll((d), false)

2190
static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
2191
{
2192
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2193 2194
	struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2195

2196 2197 2198
	assert_pipe_disabled(dev_priv, crtc->pipe);
	assert_dp_port_disabled(intel_dp);
	assert_edp_pll_disabled(dev_priv);
2199

2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213
	DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
		      crtc->config->port_clock);

	intel_dp->DP &= ~DP_PLL_FREQ_MASK;

	if (crtc->config->port_clock == 162000)
		intel_dp->DP |= DP_PLL_FREQ_162MHZ;
	else
		intel_dp->DP |= DP_PLL_FREQ_270MHZ;

	I915_WRITE(DP_A, intel_dp->DP);
	POSTING_READ(DP_A);
	udelay(500);

2214 2215 2216 2217 2218 2219 2220 2221 2222
	/*
	 * [DevILK] Work around required when enabling DP PLL
	 * while a pipe is enabled going to FDI:
	 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
	 * 2. Program DP PLL enable
	 */
	if (IS_GEN5(dev_priv))
		intel_wait_for_vblank_if_active(dev_priv->dev, !crtc->pipe);

2223
	intel_dp->DP |= DP_PLL_ENABLE;
2224

2225
	I915_WRITE(DP_A, intel_dp->DP);
2226 2227
	POSTING_READ(DP_A);
	udelay(200);
2228 2229
}

2230
static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2231
{
2232
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2233 2234
	struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2235

2236 2237 2238
	assert_pipe_disabled(dev_priv, crtc->pipe);
	assert_dp_port_disabled(intel_dp);
	assert_edp_pll_enabled(dev_priv);
2239

2240 2241
	DRM_DEBUG_KMS("disabling eDP PLL\n");

2242
	intel_dp->DP &= ~DP_PLL_ENABLE;
2243

2244
	I915_WRITE(DP_A, intel_dp->DP);
2245
	POSTING_READ(DP_A);
2246 2247 2248
	udelay(200);
}

2249
/* If the sink supports it, try to set the power state appropriately */
2250
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2251 2252 2253 2254 2255 2256 2257 2258
{
	int ret, i;

	/* Should have a valid DPCD by this point */
	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
		return;

	if (mode != DRM_MODE_DPMS_ON) {
2259 2260
		ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
					 DP_SET_POWER_D3);
2261 2262 2263 2264 2265 2266
	} else {
		/*
		 * When turning on, we need to retry for 1ms to give the sink
		 * time to wake up.
		 */
		for (i = 0; i < 3; i++) {
2267 2268
			ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
						 DP_SET_POWER_D0);
2269 2270 2271 2272 2273
			if (ret == 1)
				break;
			msleep(1);
		}
	}
2274 2275 2276 2277

	if (ret != 1)
		DRM_DEBUG_KMS("failed to %s sink power state\n",
			      mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2278 2279
}

2280 2281
static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
				  enum pipe *pipe)
2282
{
2283
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2284
	enum port port = dp_to_dig_port(intel_dp)->port;
2285 2286
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2287 2288
	enum intel_display_power_domain power_domain;
	u32 tmp;
2289
	bool ret;
2290 2291

	power_domain = intel_display_port_power_domain(encoder);
2292
	if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
2293 2294
		return false;

2295 2296
	ret = false;

2297
	tmp = I915_READ(intel_dp->output_reg);
2298 2299

	if (!(tmp & DP_PORT_EN))
2300
		goto out;
2301

2302
	if (IS_GEN7(dev) && port == PORT_A) {
2303
		*pipe = PORT_TO_PIPE_CPT(tmp);
2304
	} else if (HAS_PCH_CPT(dev) && port != PORT_A) {
2305
		enum pipe p;
2306

2307 2308 2309 2310
		for_each_pipe(dev_priv, p) {
			u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
			if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
				*pipe = p;
2311 2312 2313
				ret = true;

				goto out;
2314 2315 2316
			}
		}

2317
		DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2318
			      i915_mmio_reg_offset(intel_dp->output_reg));
2319 2320 2321 2322
	} else if (IS_CHERRYVIEW(dev)) {
		*pipe = DP_PORT_TO_PIPE_CHV(tmp);
	} else {
		*pipe = PORT_TO_PIPE(tmp);
2323
	}
2324

2325 2326 2327 2328 2329 2330
	ret = true;

out:
	intel_display_power_put(dev_priv, power_domain);

	return ret;
2331
}
2332

2333
static void intel_dp_get_config(struct intel_encoder *encoder,
2334
				struct intel_crtc_state *pipe_config)
2335 2336 2337
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	u32 tmp, flags = 0;
2338 2339 2340 2341
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = dp_to_dig_port(intel_dp)->port;
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2342

2343
	tmp = I915_READ(intel_dp->output_reg);
2344 2345

	pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2346

2347
	if (HAS_PCH_CPT(dev) && port != PORT_A) {
2348 2349 2350
		u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));

		if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2351 2352 2353
			flags |= DRM_MODE_FLAG_PHSYNC;
		else
			flags |= DRM_MODE_FLAG_NHSYNC;
2354

2355
		if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2356 2357 2358 2359
			flags |= DRM_MODE_FLAG_PVSYNC;
		else
			flags |= DRM_MODE_FLAG_NVSYNC;
	} else {
2360
		if (tmp & DP_SYNC_HS_HIGH)
2361 2362 2363
			flags |= DRM_MODE_FLAG_PHSYNC;
		else
			flags |= DRM_MODE_FLAG_NHSYNC;
2364

2365
		if (tmp & DP_SYNC_VS_HIGH)
2366 2367 2368 2369
			flags |= DRM_MODE_FLAG_PVSYNC;
		else
			flags |= DRM_MODE_FLAG_NVSYNC;
	}
2370

2371
	pipe_config->base.adjusted_mode.flags |= flags;
2372

2373
	if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2374
	    !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235)
2375 2376
		pipe_config->limited_color_range = true;

2377 2378
	pipe_config->has_dp_encoder = true;

2379 2380 2381
	pipe_config->lane_count =
		((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;

2382 2383
	intel_dp_get_m_n(crtc, pipe_config);

2384
	if (port == PORT_A) {
2385
		if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2386 2387 2388 2389
			pipe_config->port_clock = 162000;
		else
			pipe_config->port_clock = 270000;
	}
2390

2391 2392 2393
	pipe_config->base.adjusted_mode.crtc_clock =
		intel_dotclock_calculate(pipe_config->port_clock,
					 &pipe_config->dp_m_n);
2394

2395 2396
	if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
	    pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410
		/*
		 * This is a big fat ugly hack.
		 *
		 * Some machines in UEFI boot mode provide us a VBT that has 18
		 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
		 * unknown we fail to light up. Yet the same BIOS boots up with
		 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
		 * max, not what it tells us to use.
		 *
		 * Note: This will still be broken if the eDP panel is not lit
		 * up by the BIOS, and thus we can't get the mode at module
		 * load.
		 */
		DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2411 2412
			      pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
		dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2413
	}
2414 2415
}

2416
static void intel_disable_dp(struct intel_encoder *encoder)
2417
{
2418
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2419
	struct drm_device *dev = encoder->base.dev;
2420 2421
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);

2422
	if (crtc->config->has_audio)
2423
		intel_audio_codec_disable(encoder);
2424

2425 2426 2427
	if (HAS_PSR(dev) && !HAS_DDI(dev))
		intel_psr_disable(intel_dp);

2428 2429
	/* Make sure the panel is off before trying to change the mode. But also
	 * ensure that we have vdd while we switch off the panel. */
2430
	intel_edp_panel_vdd_on(intel_dp);
2431
	intel_edp_backlight_off(intel_dp);
2432
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2433
	intel_edp_panel_off(intel_dp);
2434

2435 2436
	/* disable the port before the pipe on g4x */
	if (INTEL_INFO(dev)->gen < 5)
2437
		intel_dp_link_down(intel_dp);
2438 2439
}

2440
static void ilk_post_disable_dp(struct intel_encoder *encoder)
2441
{
2442
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2443
	enum port port = dp_to_dig_port(intel_dp)->port;
2444

2445
	intel_dp_link_down(intel_dp);
2446 2447

	/* Only ilk+ has port A */
2448 2449
	if (port == PORT_A)
		ironlake_edp_pll_off(intel_dp);
2450 2451 2452 2453 2454 2455 2456
}

static void vlv_post_disable_dp(struct intel_encoder *encoder)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

	intel_dp_link_down(intel_dp);
2457 2458
}

2459 2460 2461 2462 2463
static void chv_post_disable_dp(struct intel_encoder *encoder)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2464

2465 2466 2467 2468 2469 2470
	intel_dp_link_down(intel_dp);

	mutex_lock(&dev_priv->sb_lock);

	/* Assert data lane reset */
	chv_data_lane_soft_reset(encoder, true);
2471

V
Ville Syrjälä 已提交
2472
	mutex_unlock(&dev_priv->sb_lock);
2473 2474
}

2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510
static void
_intel_dp_set_link_train(struct intel_dp *intel_dp,
			 uint32_t *DP,
			 uint8_t dp_train_pat)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = intel_dig_port->port;

	if (HAS_DDI(dev)) {
		uint32_t temp = I915_READ(DP_TP_CTL(port));

		if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
			temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
		else
			temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;

		temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
			temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;

			break;
		case DP_TRAINING_PATTERN_1:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
			break;
		case DP_TRAINING_PATTERN_2:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
			break;
		case DP_TRAINING_PATTERN_3:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
			break;
		}
		I915_WRITE(DP_TP_CTL(port), temp);

2511 2512
	} else if ((IS_GEN7(dev) && port == PORT_A) ||
		   (HAS_PCH_CPT(dev) && port != PORT_A)) {
2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562
		*DP &= ~DP_LINK_TRAIN_MASK_CPT;

		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
			*DP |= DP_LINK_TRAIN_OFF_CPT;
			break;
		case DP_TRAINING_PATTERN_1:
			*DP |= DP_LINK_TRAIN_PAT_1_CPT;
			break;
		case DP_TRAINING_PATTERN_2:
			*DP |= DP_LINK_TRAIN_PAT_2_CPT;
			break;
		case DP_TRAINING_PATTERN_3:
			DRM_ERROR("DP training pattern 3 not supported\n");
			*DP |= DP_LINK_TRAIN_PAT_2_CPT;
			break;
		}

	} else {
		if (IS_CHERRYVIEW(dev))
			*DP &= ~DP_LINK_TRAIN_MASK_CHV;
		else
			*DP &= ~DP_LINK_TRAIN_MASK;

		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
			*DP |= DP_LINK_TRAIN_OFF;
			break;
		case DP_TRAINING_PATTERN_1:
			*DP |= DP_LINK_TRAIN_PAT_1;
			break;
		case DP_TRAINING_PATTERN_2:
			*DP |= DP_LINK_TRAIN_PAT_2;
			break;
		case DP_TRAINING_PATTERN_3:
			if (IS_CHERRYVIEW(dev)) {
				*DP |= DP_LINK_TRAIN_PAT_3_CHV;
			} else {
				DRM_ERROR("DP training pattern 3 not supported\n");
				*DP |= DP_LINK_TRAIN_PAT_2;
			}
			break;
		}
	}
}

static void intel_dp_enable_port(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
2563 2564
	struct intel_crtc *crtc =
		to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
2565 2566 2567 2568 2569 2570 2571

	/* enable with pattern 1 (as per spec) */
	_intel_dp_set_link_train(intel_dp, &intel_dp->DP,
				 DP_TRAINING_PATTERN_1);

	I915_WRITE(intel_dp->output_reg, intel_dp->DP);
	POSTING_READ(intel_dp->output_reg);
2572 2573 2574 2575 2576 2577 2578 2579

	/*
	 * Magic for VLV/CHV. We _must_ first set up the register
	 * without actually enabling the port, and then do another
	 * write to enable the port. Otherwise link training will
	 * fail when the power sequencer is freshly used for this port.
	 */
	intel_dp->DP |= DP_PORT_EN;
2580 2581
	if (crtc->config->has_audio)
		intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2582 2583 2584

	I915_WRITE(intel_dp->output_reg, intel_dp->DP);
	POSTING_READ(intel_dp->output_reg);
2585 2586
}

2587
static void intel_enable_dp(struct intel_encoder *encoder)
2588
{
2589 2590 2591
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2592
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2593
	uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2594
	enum pipe pipe = crtc->pipe;
2595

2596 2597
	if (WARN_ON(dp_reg & DP_PORT_EN))
		return;
2598

2599 2600
	pps_lock(intel_dp);

2601
	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2602 2603
		vlv_init_panel_power_sequencer(intel_dp);

2604
	intel_dp_enable_port(intel_dp);
2605 2606 2607 2608 2609 2610 2611

	edp_panel_vdd_on(intel_dp);
	edp_panel_on(intel_dp);
	edp_panel_vdd_off(intel_dp, true);

	pps_unlock(intel_dp);

2612
	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
2613 2614 2615 2616 2617
		unsigned int lane_mask = 0x0;

		if (IS_CHERRYVIEW(dev))
			lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count);

2618 2619
		vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
				    lane_mask);
2620
	}
2621

2622
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2623
	intel_dp_start_link_train(intel_dp);
2624
	intel_dp_stop_link_train(intel_dp);
2625

2626
	if (crtc->config->has_audio) {
2627
		DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2628
				 pipe_name(pipe));
2629 2630
		intel_audio_codec_enable(encoder);
	}
2631
}
2632

2633 2634
static void g4x_enable_dp(struct intel_encoder *encoder)
{
2635 2636
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

2637
	intel_enable_dp(encoder);
2638
	intel_edp_backlight_on(intel_dp);
2639
}
2640

2641 2642
static void vlv_enable_dp(struct intel_encoder *encoder)
{
2643 2644
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

2645
	intel_edp_backlight_on(intel_dp);
2646
	intel_psr_enable(intel_dp);
2647 2648
}

2649
static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2650 2651
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2652
	enum port port = dp_to_dig_port(intel_dp)->port;
2653

2654 2655
	intel_dp_prepare(encoder);

2656
	/* Only ilk+ has port A */
2657
	if (port == PORT_A)
2658 2659 2660
		ironlake_edp_pll_on(intel_dp);
}

2661 2662 2663 2664 2665
static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
	enum pipe pipe = intel_dp->pps_pipe;
2666
	i915_reg_t pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686

	edp_panel_vdd_off_sync(intel_dp);

	/*
	 * VLV seems to get confused when multiple power seqeuencers
	 * have the same port selected (even if only one has power/vdd
	 * enabled). The failure manifests as vlv_wait_port_ready() failing
	 * CHV on the other hand doesn't seem to mind having the same port
	 * selected in multiple power seqeuencers, but let's clear the
	 * port select always when logically disconnecting a power sequencer
	 * from a port.
	 */
	DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
		      pipe_name(pipe), port_name(intel_dig_port->port));
	I915_WRITE(pp_on_reg, 0);
	POSTING_READ(pp_on_reg);

	intel_dp->pps_pipe = INVALID_PIPE;
}

2687 2688 2689 2690 2691 2692 2693 2694
static void vlv_steal_power_sequencer(struct drm_device *dev,
				      enum pipe pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_encoder *encoder;

	lockdep_assert_held(&dev_priv->pps_mutex);

2695 2696 2697
	if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
		return;

2698
	for_each_intel_encoder(dev, encoder) {
2699
		struct intel_dp *intel_dp;
2700
		enum port port;
2701 2702 2703 2704 2705

		if (encoder->type != INTEL_OUTPUT_EDP)
			continue;

		intel_dp = enc_to_intel_dp(&encoder->base);
2706
		port = dp_to_dig_port(intel_dp)->port;
2707 2708 2709 2710 2711

		if (intel_dp->pps_pipe != pipe)
			continue;

		DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2712
			      pipe_name(pipe), port_name(port));
2713

2714
		WARN(encoder->base.crtc,
2715 2716
		     "stealing pipe %c power sequencer from active eDP port %c\n",
		     pipe_name(pipe), port_name(port));
2717 2718

		/* make sure vdd is off before we steal it */
2719
		vlv_detach_power_sequencer(intel_dp);
2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732
	}
}

static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *encoder = &intel_dig_port->base;
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);

	lockdep_assert_held(&dev_priv->pps_mutex);

2733 2734 2735
	if (!is_edp(intel_dp))
		return;

2736 2737 2738 2739 2740 2741 2742 2743 2744
	if (intel_dp->pps_pipe == crtc->pipe)
		return;

	/*
	 * If another power sequencer was being used on this
	 * port previously make sure to turn off vdd there while
	 * we still have control of it.
	 */
	if (intel_dp->pps_pipe != INVALID_PIPE)
2745
		vlv_detach_power_sequencer(intel_dp);
2746 2747 2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758 2759

	/*
	 * We may be stealing the power
	 * sequencer from another port.
	 */
	vlv_steal_power_sequencer(dev, crtc->pipe);

	/* now it's all ours */
	intel_dp->pps_pipe = crtc->pipe;

	DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
		      pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));

	/* init power sequencer on this pipe and port */
2760 2761
	intel_dp_init_panel_power_sequencer(dev, intel_dp);
	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
2762 2763
}

2764
static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2765
{
2766
	vlv_phy_pre_encoder_enable(encoder);
2767 2768

	intel_enable_dp(encoder);
2769 2770
}

2771
static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2772
{
2773 2774
	intel_dp_prepare(encoder);

2775
	vlv_phy_pre_pll_enable(encoder);
2776 2777
}

2778 2779
static void chv_pre_enable_dp(struct intel_encoder *encoder)
{
2780
	chv_phy_pre_encoder_enable(encoder);
2781 2782

	intel_enable_dp(encoder);
2783 2784

	/* Second common lane will stay alive on its own now */
2785
	chv_phy_release_cl2_override(encoder);
2786 2787
}

2788 2789
static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
{
2790 2791
	intel_dp_prepare(encoder);

2792
	chv_phy_pre_pll_enable(encoder);
2793 2794
}

2795 2796
static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
{
2797
	chv_phy_post_pll_disable(encoder);
2798 2799
}

2800 2801 2802 2803
/*
 * Fetch AUX CH registers 0x202 - 0x207 which contain
 * link status information
 */
2804
bool
2805
intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2806
{
2807 2808
	return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
				DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2809 2810
}

2811
/* These are source-specific values. */
2812
uint8_t
K
Keith Packard 已提交
2813
intel_dp_voltage_max(struct intel_dp *intel_dp)
2814
{
2815
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2816
	struct drm_i915_private *dev_priv = dev->dev_private;
2817
	enum port port = dp_to_dig_port(intel_dp)->port;
K
Keith Packard 已提交
2818

2819 2820 2821
	if (IS_BROXTON(dev))
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
	else if (INTEL_INFO(dev)->gen >= 9) {
2822
		if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
2823
			return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2824
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2825
	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2826
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2827
	else if (IS_GEN7(dev) && port == PORT_A)
2828
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2829
	else if (HAS_PCH_CPT(dev) && port != PORT_A)
2830
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
K
Keith Packard 已提交
2831
	else
2832
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
K
Keith Packard 已提交
2833 2834
}

2835
uint8_t
K
Keith Packard 已提交
2836 2837
intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
{
2838
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2839
	enum port port = dp_to_dig_port(intel_dp)->port;
K
Keith Packard 已提交
2840

2841 2842 2843 2844 2845 2846 2847 2848
	if (INTEL_INFO(dev)->gen >= 9) {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
			return DP_TRAIN_PRE_EMPH_LEVEL_3;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
			return DP_TRAIN_PRE_EMPH_LEVEL_1;
2849 2850
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
2851 2852 2853 2854
		default:
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
		}
	} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2855
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2856 2857 2858 2859 2860 2861 2862
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
			return DP_TRAIN_PRE_EMPH_LEVEL_3;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
			return DP_TRAIN_PRE_EMPH_LEVEL_1;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2863
		default:
2864
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
2865
		}
2866
	} else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
2867
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2868 2869 2870 2871 2872 2873 2874
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
			return DP_TRAIN_PRE_EMPH_LEVEL_3;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
			return DP_TRAIN_PRE_EMPH_LEVEL_1;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2875
		default:
2876
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
2877
		}
2878
	} else if (IS_GEN7(dev) && port == PORT_A) {
K
Keith Packard 已提交
2879
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2880 2881 2882 2883 2884
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
			return DP_TRAIN_PRE_EMPH_LEVEL_1;
K
Keith Packard 已提交
2885
		default:
2886
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
K
Keith Packard 已提交
2887 2888 2889
		}
	} else {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2890 2891 2892 2893 2894 2895 2896
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
			return DP_TRAIN_PRE_EMPH_LEVEL_1;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
K
Keith Packard 已提交
2897
		default:
2898
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
K
Keith Packard 已提交
2899
		}
2900 2901 2902
	}
}

2903
static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
2904
{
2905
	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2906 2907 2908 2909 2910
	unsigned long demph_reg_value, preemph_reg_value,
		uniqtranscale_reg_value;
	uint8_t train_set = intel_dp->train_set[0];

	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2911
	case DP_TRAIN_PRE_EMPH_LEVEL_0:
2912 2913
		preemph_reg_value = 0x0004000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2914
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2915 2916 2917
			demph_reg_value = 0x2B405555;
			uniqtranscale_reg_value = 0x552AB83A;
			break;
2918
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2919 2920 2921
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x5548B83A;
			break;
2922
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2923 2924 2925
			demph_reg_value = 0x2B245555;
			uniqtranscale_reg_value = 0x5560B83A;
			break;
2926
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2927 2928 2929 2930 2931 2932 2933
			demph_reg_value = 0x2B405555;
			uniqtranscale_reg_value = 0x5598DA3A;
			break;
		default:
			return 0;
		}
		break;
2934
	case DP_TRAIN_PRE_EMPH_LEVEL_1:
2935 2936
		preemph_reg_value = 0x0002000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2937
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2938 2939 2940
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x5552B83A;
			break;
2941
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2942 2943 2944
			demph_reg_value = 0x2B404848;
			uniqtranscale_reg_value = 0x5580B83A;
			break;
2945
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2946 2947 2948 2949 2950 2951 2952
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
2953
	case DP_TRAIN_PRE_EMPH_LEVEL_2:
2954 2955
		preemph_reg_value = 0x0000000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2956
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2957 2958 2959
			demph_reg_value = 0x2B305555;
			uniqtranscale_reg_value = 0x5570B83A;
			break;
2960
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2961 2962 2963 2964 2965 2966 2967
			demph_reg_value = 0x2B2B4040;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
2968
	case DP_TRAIN_PRE_EMPH_LEVEL_3:
2969 2970
		preemph_reg_value = 0x0006000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2971
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982
			demph_reg_value = 0x1B405555;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
	default:
		return 0;
	}

2983 2984
	vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
				 uniqtranscale_reg_value, 0);
2985 2986 2987 2988

	return 0;
}

2989
static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
2990
{
2991 2992 2993
	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
	u32 deemph_reg_value, margin_reg_value;
	bool uniq_trans_scale = false;
2994 2995 2996
	uint8_t train_set = intel_dp->train_set[0];

	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2997
	case DP_TRAIN_PRE_EMPH_LEVEL_0:
2998
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2999
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3000 3001 3002
			deemph_reg_value = 128;
			margin_reg_value = 52;
			break;
3003
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3004 3005 3006
			deemph_reg_value = 128;
			margin_reg_value = 77;
			break;
3007
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3008 3009 3010
			deemph_reg_value = 128;
			margin_reg_value = 102;
			break;
3011
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3012 3013
			deemph_reg_value = 128;
			margin_reg_value = 154;
3014
			uniq_trans_scale = true;
3015 3016 3017 3018 3019
			break;
		default:
			return 0;
		}
		break;
3020
	case DP_TRAIN_PRE_EMPH_LEVEL_1:
3021
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3022
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3023 3024 3025
			deemph_reg_value = 85;
			margin_reg_value = 78;
			break;
3026
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3027 3028 3029
			deemph_reg_value = 85;
			margin_reg_value = 116;
			break;
3030
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3031 3032 3033 3034 3035 3036 3037
			deemph_reg_value = 85;
			margin_reg_value = 154;
			break;
		default:
			return 0;
		}
		break;
3038
	case DP_TRAIN_PRE_EMPH_LEVEL_2:
3039
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3040
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3041 3042 3043
			deemph_reg_value = 64;
			margin_reg_value = 104;
			break;
3044
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3045 3046 3047 3048 3049 3050 3051
			deemph_reg_value = 64;
			margin_reg_value = 154;
			break;
		default:
			return 0;
		}
		break;
3052
	case DP_TRAIN_PRE_EMPH_LEVEL_3:
3053
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3054
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3055 3056 3057 3058 3059 3060 3061 3062 3063 3064 3065
			deemph_reg_value = 43;
			margin_reg_value = 154;
			break;
		default:
			return 0;
		}
		break;
	default:
		return 0;
	}

3066 3067
	chv_set_phy_signal_level(encoder, deemph_reg_value,
				 margin_reg_value, uniq_trans_scale);
3068 3069 3070 3071

	return 0;
}

3072
static uint32_t
3073
gen4_signal_levels(uint8_t train_set)
3074
{
3075
	uint32_t	signal_levels = 0;
3076

3077
	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3078
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3079 3080 3081
	default:
		signal_levels |= DP_VOLTAGE_0_4;
		break;
3082
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3083 3084
		signal_levels |= DP_VOLTAGE_0_6;
		break;
3085
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3086 3087
		signal_levels |= DP_VOLTAGE_0_8;
		break;
3088
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3089 3090 3091
		signal_levels |= DP_VOLTAGE_1_2;
		break;
	}
3092
	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3093
	case DP_TRAIN_PRE_EMPH_LEVEL_0:
3094 3095 3096
	default:
		signal_levels |= DP_PRE_EMPHASIS_0;
		break;
3097
	case DP_TRAIN_PRE_EMPH_LEVEL_1:
3098 3099
		signal_levels |= DP_PRE_EMPHASIS_3_5;
		break;
3100
	case DP_TRAIN_PRE_EMPH_LEVEL_2:
3101 3102
		signal_levels |= DP_PRE_EMPHASIS_6;
		break;
3103
	case DP_TRAIN_PRE_EMPH_LEVEL_3:
3104 3105 3106 3107 3108 3109
		signal_levels |= DP_PRE_EMPHASIS_9_5;
		break;
	}
	return signal_levels;
}

3110 3111
/* Gen6's DP voltage swing and pre-emphasis control */
static uint32_t
3112
gen6_edp_signal_levels(uint8_t train_set)
3113
{
3114 3115 3116
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
3117 3118
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3119
		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3120
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3121
		return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3122 3123
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3124
		return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3125 3126
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3127
		return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3128 3129
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3130
		return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3131
	default:
3132 3133 3134
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3135 3136 3137
	}
}

K
Keith Packard 已提交
3138 3139
/* Gen7's DP voltage swing and pre-emphasis control */
static uint32_t
3140
gen7_edp_signal_levels(uint8_t train_set)
K
Keith Packard 已提交
3141 3142 3143 3144
{
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
3145
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
K
Keith Packard 已提交
3146
		return EDP_LINK_TRAIN_400MV_0DB_IVB;
3147
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
K
Keith Packard 已提交
3148
		return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3149
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
K
Keith Packard 已提交
3150 3151
		return EDP_LINK_TRAIN_400MV_6DB_IVB;

3152
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
K
Keith Packard 已提交
3153
		return EDP_LINK_TRAIN_600MV_0DB_IVB;
3154
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
K
Keith Packard 已提交
3155 3156
		return EDP_LINK_TRAIN_600MV_3_5DB_IVB;

3157
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
K
Keith Packard 已提交
3158
		return EDP_LINK_TRAIN_800MV_0DB_IVB;
3159
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
K
Keith Packard 已提交
3160 3161 3162 3163 3164 3165 3166 3167 3168
		return EDP_LINK_TRAIN_800MV_3_5DB_IVB;

	default:
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return EDP_LINK_TRAIN_500MV_0DB_IVB;
	}
}

3169
void
3170
intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3171 3172
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3173
	enum port port = intel_dig_port->port;
3174
	struct drm_device *dev = intel_dig_port->base.base.dev;
3175
	struct drm_i915_private *dev_priv = to_i915(dev);
3176
	uint32_t signal_levels, mask = 0;
3177 3178
	uint8_t train_set = intel_dp->train_set[0];

3179 3180 3181 3182 3183 3184 3185
	if (HAS_DDI(dev)) {
		signal_levels = ddi_signal_levels(intel_dp);

		if (IS_BROXTON(dev))
			signal_levels = 0;
		else
			mask = DDI_BUF_EMP_MASK;
3186
	} else if (IS_CHERRYVIEW(dev)) {
3187
		signal_levels = chv_signal_levels(intel_dp);
3188
	} else if (IS_VALLEYVIEW(dev)) {
3189
		signal_levels = vlv_signal_levels(intel_dp);
3190
	} else if (IS_GEN7(dev) && port == PORT_A) {
3191
		signal_levels = gen7_edp_signal_levels(train_set);
3192
		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3193
	} else if (IS_GEN6(dev) && port == PORT_A) {
3194
		signal_levels = gen6_edp_signal_levels(train_set);
3195 3196
		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
	} else {
3197
		signal_levels = gen4_signal_levels(train_set);
3198 3199 3200
		mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
	}

3201 3202 3203 3204 3205 3206 3207 3208
	if (mask)
		DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);

	DRM_DEBUG_KMS("Using vswing level %d\n",
		train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
	DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
		(train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
			DP_TRAIN_PRE_EMPHASIS_SHIFT);
3209

3210
	intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3211 3212 3213

	I915_WRITE(intel_dp->output_reg, intel_dp->DP);
	POSTING_READ(intel_dp->output_reg);
3214 3215
}

3216
void
3217 3218
intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
				       uint8_t dp_train_pat)
3219
{
3220
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3221 3222
	struct drm_i915_private *dev_priv =
		to_i915(intel_dig_port->base.base.dev);
3223

3224
	_intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3225

3226
	I915_WRITE(intel_dp->output_reg, intel_dp->DP);
C
Chris Wilson 已提交
3227
	POSTING_READ(intel_dp->output_reg);
3228 3229
}

3230
void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3231 3232 3233 3234 3235 3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = intel_dig_port->port;
	uint32_t val;

	if (!HAS_DDI(dev))
		return;

	val = I915_READ(DP_TP_CTL(port));
	val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
	val |= DP_TP_CTL_LINK_TRAIN_IDLE;
	I915_WRITE(DP_TP_CTL(port), val);

	/*
	 * On PORT_A we can have only eDP in SST mode. There the only reason
	 * we need to set idle transmission mode is to work around a HW issue
	 * where we enable the pipe while not in idle link-training mode.
	 * In this case there is requirement to wait for a minimum number of
	 * idle patterns to be sent.
	 */
	if (port == PORT_A)
		return;

	if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
		     1))
		DRM_ERROR("Timed out waiting for DP idle patterns\n");
}

3261
static void
C
Chris Wilson 已提交
3262
intel_dp_link_down(struct intel_dp *intel_dp)
3263
{
3264
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3265
	struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3266
	enum port port = intel_dig_port->port;
3267
	struct drm_device *dev = intel_dig_port->base.base.dev;
3268
	struct drm_i915_private *dev_priv = dev->dev_private;
C
Chris Wilson 已提交
3269
	uint32_t DP = intel_dp->DP;
3270

3271
	if (WARN_ON(HAS_DDI(dev)))
3272 3273
		return;

3274
	if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3275 3276
		return;

3277
	DRM_DEBUG_KMS("\n");
3278

3279 3280
	if ((IS_GEN7(dev) && port == PORT_A) ||
	    (HAS_PCH_CPT(dev) && port != PORT_A)) {
3281
		DP &= ~DP_LINK_TRAIN_MASK_CPT;
3282
		DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3283
	} else {
3284 3285 3286 3287
		if (IS_CHERRYVIEW(dev))
			DP &= ~DP_LINK_TRAIN_MASK_CHV;
		else
			DP &= ~DP_LINK_TRAIN_MASK;
3288
		DP |= DP_LINK_TRAIN_PAT_IDLE;
3289
	}
3290
	I915_WRITE(intel_dp->output_reg, DP);
3291
	POSTING_READ(intel_dp->output_reg);
3292

3293 3294 3295 3296 3297 3298 3299 3300 3301 3302
	DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
	I915_WRITE(intel_dp->output_reg, DP);
	POSTING_READ(intel_dp->output_reg);

	/*
	 * HW workaround for IBX, we need to move the port
	 * to transcoder A after disabling it to allow the
	 * matching HDMI port to be enabled on transcoder A.
	 */
	if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
3303 3304 3305 3306 3307 3308 3309
		/*
		 * We get CPU/PCH FIFO underruns on the other pipe when
		 * doing the workaround. Sweep them under the rug.
		 */
		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);

3310 3311 3312 3313 3314 3315 3316
		/* always enable with pattern 1 (as per spec) */
		DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
		DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
		I915_WRITE(intel_dp->output_reg, DP);
		POSTING_READ(intel_dp->output_reg);

		DP &= ~DP_PORT_EN;
3317
		I915_WRITE(intel_dp->output_reg, DP);
3318
		POSTING_READ(intel_dp->output_reg);
3319 3320 3321 3322

		intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);
		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3323 3324
	}

3325
	msleep(intel_dp->panel_power_down_delay);
3326 3327

	intel_dp->DP = DP;
3328 3329
}

3330 3331
static bool
intel_dp_get_dpcd(struct intel_dp *intel_dp)
3332
{
R
Rodrigo Vivi 已提交
3333 3334 3335 3336
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

3337 3338
	if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
			     sizeof(intel_dp->dpcd)) < 0)
3339
		return false; /* aux transfer failed */
3340

3341
	DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3342

3343 3344 3345
	if (intel_dp->dpcd[DP_DPCD_REV] == 0)
		return false; /* DPCD not present */

3346 3347
	if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
			     &intel_dp->sink_count, 1) < 0)
3348 3349 3350 3351 3352 3353 3354 3355 3356 3357 3358 3359 3360 3361 3362 3363
		return false;

	/*
	 * Sink count can change between short pulse hpd hence
	 * a member variable in intel_dp will track any changes
	 * between short pulse interrupts.
	 */
	intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count);

	/*
	 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
	 * a dongle is present but no display. Unless we require to know
	 * if a dongle is present or not, we don't need to update
	 * downstream port information. So, an early return here saves
	 * time from performing other operations which are not required.
	 */
3364
	if (!is_edp(intel_dp) && !intel_dp->sink_count)
3365 3366
		return false;

3367 3368
	/* Check if the panel supports PSR */
	memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3369
	if (is_edp(intel_dp)) {
3370 3371 3372
		drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
				 intel_dp->psr_dpcd,
				 sizeof(intel_dp->psr_dpcd));
R
Rodrigo Vivi 已提交
3373 3374
		if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
			dev_priv->psr.sink_support = true;
3375
			DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
R
Rodrigo Vivi 已提交
3376
		}
3377 3378 3379 3380 3381 3382

		if (INTEL_INFO(dev)->gen >= 9 &&
			(intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
			uint8_t frame_sync_cap;

			dev_priv->psr.sink_support = true;
3383 3384 3385
			drm_dp_dpcd_read(&intel_dp->aux,
					 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
					 &frame_sync_cap, 1);
3386 3387 3388 3389 3390 3391
			dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
			/* PSR2 needs frame sync as well */
			dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
			DRM_DEBUG_KMS("PSR2 %s on sink",
				dev_priv->psr.psr2_support ? "supported" : "not supported");
		}
3392 3393 3394 3395

		/* Read the eDP Display control capabilities registers */
		memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd));
		if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3396
				(drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3397 3398 3399 3400
						intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
								sizeof(intel_dp->edp_dpcd)))
			DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
					intel_dp->edp_dpcd);
3401 3402
	}

3403
	DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
3404
		      yesno(intel_dp_source_supports_hbr2(intel_dp)),
3405
		      yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
3406

3407
	/* Intermediate frequency support */
3408
	if (is_edp(intel_dp) && (intel_dp->edp_dpcd[0] >= 0x03)) { /* eDp v1.4 or higher */
3409
		__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3410 3411
		int i;

3412 3413
		drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
				sink_rates, sizeof(sink_rates));
3414

3415 3416
		for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
			int val = le16_to_cpu(sink_rates[i]);
3417 3418 3419 3420

			if (val == 0)
				break;

3421 3422
			/* Value read is in kHz while drm clock is saved in deca-kHz */
			intel_dp->sink_rates[i] = (val * 200) / 10;
3423
		}
3424
		intel_dp->num_sink_rates = i;
3425
	}
3426 3427 3428

	intel_dp_print_rates(intel_dp);

3429 3430 3431 3432 3433 3434 3435
	if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
	      DP_DWN_STRM_PORT_PRESENT))
		return true; /* native DP sink */

	if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
		return true; /* no per-port downstream info */

3436 3437 3438
	if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
			     intel_dp->downstream_ports,
			     DP_MAX_DOWNSTREAM_PORTS) < 0)
3439 3440 3441
		return false; /* downstream port status fetch failed */

	return true;
3442 3443
}

3444 3445 3446 3447 3448 3449 3450 3451
static void
intel_dp_probe_oui(struct intel_dp *intel_dp)
{
	u8 buf[3];

	if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
		return;

3452
	if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3453 3454 3455
		DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
			      buf[0], buf[1], buf[2]);

3456
	if (drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3457 3458 3459 3460
		DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
			      buf[0], buf[1], buf[2]);
}

3461 3462 3463 3464 3465
static bool
intel_dp_probe_mst(struct intel_dp *intel_dp)
{
	u8 buf[1];

3466 3467 3468
	if (!i915.enable_dp_mst)
		return false;

3469 3470 3471 3472 3473 3474
	if (!intel_dp->can_mst)
		return false;

	if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
		return false;

3475
	if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3476 3477 3478 3479 3480 3481 3482 3483 3484 3485 3486 3487 3488
		if (buf[0] & DP_MST_CAP) {
			DRM_DEBUG_KMS("Sink is MST capable\n");
			intel_dp->is_mst = true;
		} else {
			DRM_DEBUG_KMS("Sink is not MST capable\n");
			intel_dp->is_mst = false;
		}
	}

	drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
	return intel_dp->is_mst;
}

3489
static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
3490
{
3491
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3492
	struct drm_device *dev = dig_port->base.base.dev;
3493
	struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
R
Rodrigo Vivi 已提交
3494
	u8 buf;
3495
	int ret = 0;
3496 3497
	int count = 0;
	int attempts = 10;
3498

3499 3500
	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
		DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3501 3502
		ret = -EIO;
		goto out;
3503 3504
	}

3505
	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3506
			       buf & ~DP_TEST_SINK_START) < 0) {
3507
		DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3508 3509 3510
		ret = -EIO;
		goto out;
	}
3511

3512 3513 3514 3515 3516 3517 3518 3519 3520 3521 3522 3523
	do {
		intel_wait_for_vblank(dev, intel_crtc->pipe);

		if (drm_dp_dpcd_readb(&intel_dp->aux,
				      DP_TEST_SINK_MISC, &buf) < 0) {
			ret = -EIO;
			goto out;
		}
		count = buf & DP_TEST_COUNT_MASK;
	} while (--attempts && count);

	if (attempts == 0) {
3524
		DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3525 3526 3527
		ret = -ETIMEDOUT;
	}

3528
 out:
3529
	hsw_enable_ips(intel_crtc);
3530
	return ret;
3531 3532 3533 3534 3535
}

static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3536
	struct drm_device *dev = dig_port->base.base.dev;
3537 3538
	struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
	u8 buf;
3539 3540
	int ret;

3541 3542 3543 3544 3545 3546 3547 3548 3549
	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
		return -EIO;

	if (!(buf & DP_TEST_CRC_SUPPORTED))
		return -ENOTTY;

	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
		return -EIO;

3550 3551 3552 3553 3554 3555
	if (buf & DP_TEST_SINK_START) {
		ret = intel_dp_sink_crc_stop(intel_dp);
		if (ret)
			return ret;
	}

3556
	hsw_disable_ips(intel_crtc);
3557

3558
	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3559 3560 3561
			       buf | DP_TEST_SINK_START) < 0) {
		hsw_enable_ips(intel_crtc);
		return -EIO;
3562 3563
	}

3564
	intel_wait_for_vblank(dev, intel_crtc->pipe);
3565 3566 3567 3568 3569 3570 3571 3572 3573
	return 0;
}

int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
	struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
	u8 buf;
3574
	int count, ret;
3575 3576 3577 3578 3579 3580
	int attempts = 6;

	ret = intel_dp_sink_crc_start(intel_dp);
	if (ret)
		return ret;

R
Rodrigo Vivi 已提交
3581
	do {
3582 3583
		intel_wait_for_vblank(dev, intel_crtc->pipe);

3584
		if (drm_dp_dpcd_readb(&intel_dp->aux,
3585 3586
				      DP_TEST_SINK_MISC, &buf) < 0) {
			ret = -EIO;
3587
			goto stop;
3588
		}
3589
		count = buf & DP_TEST_COUNT_MASK;
3590

3591
	} while (--attempts && count == 0);
R
Rodrigo Vivi 已提交
3592 3593

	if (attempts == 0) {
3594 3595 3596 3597 3598 3599 3600 3601
		DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
		ret = -ETIMEDOUT;
		goto stop;
	}

	if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
		ret = -EIO;
		goto stop;
R
Rodrigo Vivi 已提交
3602
	}
3603

3604
stop:
3605
	intel_dp_sink_crc_stop(intel_dp);
3606
	return ret;
3607 3608
}

3609 3610 3611
static bool
intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
{
3612
	return drm_dp_dpcd_read(&intel_dp->aux,
3613 3614
				       DP_DEVICE_SERVICE_IRQ_VECTOR,
				       sink_irq_vector, 1) == 1;
3615 3616
}

3617 3618 3619 3620 3621
static bool
intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
{
	int ret;

3622
	ret = drm_dp_dpcd_read(&intel_dp->aux,
3623 3624 3625 3626 3627 3628 3629 3630
					     DP_SINK_COUNT_ESI,
					     sink_irq_vector, 14);
	if (ret != 14)
		return false;

	return true;
}

3631 3632 3633 3634 3635 3636 3637 3638 3639 3640 3641 3642 3643
static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
{
	uint8_t test_result = DP_TEST_ACK;
	return test_result;
}

static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
{
	uint8_t test_result = DP_TEST_NAK;
	return test_result;
}

static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
3644
{
3645
	uint8_t test_result = DP_TEST_NAK;
3646 3647 3648 3649
	struct intel_connector *intel_connector = intel_dp->attached_connector;
	struct drm_connector *connector = &intel_connector->base;

	if (intel_connector->detect_edid == NULL ||
3650
	    connector->edid_corrupt ||
3651 3652 3653 3654 3655 3656 3657 3658 3659 3660 3661 3662 3663 3664 3665
	    intel_dp->aux.i2c_defer_count > 6) {
		/* Check EDID read for NACKs, DEFERs and corruption
		 * (DP CTS 1.2 Core r1.1)
		 *    4.2.2.4 : Failed EDID read, I2C_NAK
		 *    4.2.2.5 : Failed EDID read, I2C_DEFER
		 *    4.2.2.6 : EDID corruption detected
		 * Use failsafe mode for all cases
		 */
		if (intel_dp->aux.i2c_nack_count > 0 ||
			intel_dp->aux.i2c_defer_count > 0)
			DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
				      intel_dp->aux.i2c_nack_count,
				      intel_dp->aux.i2c_defer_count);
		intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
	} else {
3666 3667 3668 3669 3670 3671 3672
		struct edid *block = intel_connector->detect_edid;

		/* We have to write the checksum
		 * of the last block read
		 */
		block += intel_connector->detect_edid->extensions;

3673 3674
		if (!drm_dp_dpcd_write(&intel_dp->aux,
					DP_TEST_EDID_CHECKSUM,
3675
					&block->checksum,
D
Dan Carpenter 已提交
3676
					1))
3677 3678 3679 3680 3681 3682 3683 3684 3685
			DRM_DEBUG_KMS("Failed to write EDID checksum\n");

		test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
		intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
	}

	/* Set test active flag here so userspace doesn't interrupt things */
	intel_dp->compliance_test_active = 1;

3686 3687 3688 3689
	return test_result;
}

static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
3690
{
3691 3692 3693 3694 3695 3696 3697 3698 3699 3700 3701 3702 3703 3704 3705 3706 3707 3708 3709 3710 3711 3712 3713 3714 3715 3716 3717 3718 3719 3720 3721 3722 3723 3724 3725 3726 3727 3728 3729 3730 3731 3732 3733 3734 3735 3736 3737 3738
	uint8_t test_result = DP_TEST_NAK;
	return test_result;
}

static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
{
	uint8_t response = DP_TEST_NAK;
	uint8_t rxdata = 0;
	int status = 0;

	status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
	if (status <= 0) {
		DRM_DEBUG_KMS("Could not read test request from sink\n");
		goto update_status;
	}

	switch (rxdata) {
	case DP_TEST_LINK_TRAINING:
		DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
		intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
		response = intel_dp_autotest_link_training(intel_dp);
		break;
	case DP_TEST_LINK_VIDEO_PATTERN:
		DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
		intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
		response = intel_dp_autotest_video_pattern(intel_dp);
		break;
	case DP_TEST_LINK_EDID_READ:
		DRM_DEBUG_KMS("EDID test requested\n");
		intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
		response = intel_dp_autotest_edid(intel_dp);
		break;
	case DP_TEST_LINK_PHY_TEST_PATTERN:
		DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
		intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
		response = intel_dp_autotest_phy_pattern(intel_dp);
		break;
	default:
		DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
		break;
	}

update_status:
	status = drm_dp_dpcd_write(&intel_dp->aux,
				   DP_TEST_RESPONSE,
				   &response, 1);
	if (status <= 0)
		DRM_DEBUG_KMS("Could not write test response to sink\n");
3739 3740
}

3741 3742 3743 3744 3745 3746 3747 3748 3749 3750 3751 3752 3753 3754 3755
static int
intel_dp_check_mst_status(struct intel_dp *intel_dp)
{
	bool bret;

	if (intel_dp->is_mst) {
		u8 esi[16] = { 0 };
		int ret = 0;
		int retry;
		bool handled;
		bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
go_again:
		if (bret == true) {

			/* check link status - esi[10] = 0x200c */
3756
			if (intel_dp->active_mst_links &&
3757
			    !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3758 3759 3760 3761 3762
				DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
				intel_dp_start_link_train(intel_dp);
				intel_dp_stop_link_train(intel_dp);
			}

3763
			DRM_DEBUG_KMS("got esi %3ph\n", esi);
3764 3765 3766 3767 3768 3769 3770 3771 3772 3773 3774 3775 3776 3777 3778
			ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);

			if (handled) {
				for (retry = 0; retry < 3; retry++) {
					int wret;
					wret = drm_dp_dpcd_write(&intel_dp->aux,
								 DP_SINK_COUNT_ESI+1,
								 &esi[1], 3);
					if (wret == 3) {
						break;
					}
				}

				bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
				if (bret == true) {
3779
					DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
3780 3781 3782 3783 3784 3785 3786 3787 3788 3789 3790 3791 3792 3793 3794 3795 3796 3797
					goto go_again;
				}
			} else
				ret = 0;

			return ret;
		} else {
			struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
			DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
			intel_dp->is_mst = false;
			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
			/* send a hotplug event */
			drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
		}
	}
	return -EINVAL;
}

3798 3799 3800 3801 3802 3803 3804 3805 3806 3807 3808 3809 3810 3811 3812 3813 3814 3815 3816 3817 3818 3819 3820 3821 3822 3823 3824 3825 3826 3827
static void
intel_dp_check_link_status(struct intel_dp *intel_dp)
{
	struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	u8 link_status[DP_LINK_STATUS_SIZE];

	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));

	if (!intel_dp_get_link_status(intel_dp, link_status)) {
		DRM_ERROR("Failed to get link status\n");
		return;
	}

	if (!intel_encoder->base.crtc)
		return;

	if (!to_intel_crtc(intel_encoder->base.crtc)->active)
		return;

	/* if link training is requested we should perform it always */
	if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) ||
	    (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
		DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
			      intel_encoder->base.name);
		intel_dp_start_link_train(intel_dp);
		intel_dp_stop_link_train(intel_dp);
	}
}

3828 3829 3830 3831 3832 3833 3834
/*
 * According to DP spec
 * 5.1.2:
 *  1. Read DPCD
 *  2. Configure link according to Receiver Capabilities
 *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
 *  4. Check link status on receipt of hot-plug interrupt
3835 3836 3837 3838 3839
 *
 * intel_dp_short_pulse -  handles short pulse interrupts
 * when full detection is not required.
 * Returns %true if short pulse is handled and full detection
 * is NOT required and %false otherwise.
3840
 */
3841
static bool
3842
intel_dp_short_pulse(struct intel_dp *intel_dp)
3843
{
3844
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
3845
	u8 sink_irq_vector;
3846 3847
	u8 old_sink_count = intel_dp->sink_count;
	bool ret;
3848

3849 3850 3851 3852 3853 3854 3855 3856
	/*
	 * Clearing compliance test variables to allow capturing
	 * of values for next automated test request.
	 */
	intel_dp->compliance_test_active = 0;
	intel_dp->compliance_test_type = 0;
	intel_dp->compliance_test_data = 0;

3857 3858 3859 3860 3861 3862 3863 3864 3865 3866 3867
	/*
	 * Now read the DPCD to see if it's actually running
	 * If the current value of sink count doesn't match with
	 * the value that was stored earlier or dpcd read failed
	 * we need to do full detection
	 */
	ret = intel_dp_get_dpcd(intel_dp);

	if ((old_sink_count != intel_dp->sink_count) || !ret) {
		/* No need to proceed if we are going to do full detect */
		return false;
3868 3869
	}

3870 3871 3872 3873
	/* Try to read the source of the interrupt */
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
		/* Clear interrupt source */
3874 3875 3876
		drm_dp_dpcd_writeb(&intel_dp->aux,
				   DP_DEVICE_SERVICE_IRQ_VECTOR,
				   sink_irq_vector);
3877 3878

		if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3879
			DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
3880 3881 3882 3883
		if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
			DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
	}

3884 3885 3886
	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
	intel_dp_check_link_status(intel_dp);
	drm_modeset_unlock(&dev->mode_config.connection_mutex);
3887 3888

	return true;
3889 3890
}

3891
/* XXX this is probably wrong for multiple downstream ports */
3892
static enum drm_connector_status
3893
intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3894
{
3895 3896 3897 3898 3899 3900
	uint8_t *dpcd = intel_dp->dpcd;
	uint8_t type;

	if (!intel_dp_get_dpcd(intel_dp))
		return connector_status_disconnected;

3901 3902 3903
	if (is_edp(intel_dp))
		return connector_status_connected;

3904 3905
	/* if there's no downstream port, we're done */
	if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
3906
		return connector_status_connected;
3907 3908

	/* If we're HPD-aware, SINK_COUNT changes dynamically */
3909 3910
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3911

3912 3913
		return intel_dp->sink_count ?
		connector_status_connected : connector_status_disconnected;
3914 3915 3916
	}

	/* If no HPD, poke DDC gently */
3917
	if (drm_probe_ddc(&intel_dp->aux.ddc))
3918
		return connector_status_connected;
3919 3920

	/* Well we tried, say unknown for unreliable port types */
3921 3922 3923 3924 3925 3926 3927 3928 3929 3930 3931 3932
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
		type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
		if (type == DP_DS_PORT_TYPE_VGA ||
		    type == DP_DS_PORT_TYPE_NON_EDID)
			return connector_status_unknown;
	} else {
		type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
			DP_DWN_STRM_PORT_TYPE_MASK;
		if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
		    type == DP_DWN_STRM_PORT_TYPE_OTHER)
			return connector_status_unknown;
	}
3933 3934 3935

	/* Anything else is out of spec, warn and ignore */
	DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3936
	return connector_status_disconnected;
3937 3938
}

3939 3940 3941 3942 3943 3944 3945 3946 3947 3948 3949 3950 3951
static enum drm_connector_status
edp_detect(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	enum drm_connector_status status;

	status = intel_panel_detect(dev);
	if (status == connector_status_unknown)
		status = connector_status_connected;

	return status;
}

3952 3953
static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
				       struct intel_digital_port *port)
3954
{
3955
	u32 bit;
3956

3957 3958 3959 3960 3961 3962 3963 3964 3965 3966 3967 3968 3969 3970 3971 3972 3973 3974 3975 3976 3977 3978 3979 3980 3981 3982 3983 3984 3985 3986 3987 3988 3989 3990 3991 3992 3993
	switch (port->port) {
	case PORT_A:
		return true;
	case PORT_B:
		bit = SDE_PORTB_HOTPLUG;
		break;
	case PORT_C:
		bit = SDE_PORTC_HOTPLUG;
		break;
	case PORT_D:
		bit = SDE_PORTD_HOTPLUG;
		break;
	default:
		MISSING_CASE(port->port);
		return false;
	}

	return I915_READ(SDEISR) & bit;
}

static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
				       struct intel_digital_port *port)
{
	u32 bit;

	switch (port->port) {
	case PORT_A:
		return true;
	case PORT_B:
		bit = SDE_PORTB_HOTPLUG_CPT;
		break;
	case PORT_C:
		bit = SDE_PORTC_HOTPLUG_CPT;
		break;
	case PORT_D:
		bit = SDE_PORTD_HOTPLUG_CPT;
		break;
3994 3995 3996
	case PORT_E:
		bit = SDE_PORTE_HOTPLUG_SPT;
		break;
3997 3998 3999
	default:
		MISSING_CASE(port->port);
		return false;
4000
	}
4001

4002
	return I915_READ(SDEISR) & bit;
4003 4004
}

4005
static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
4006
				       struct intel_digital_port *port)
4007
{
4008
	u32 bit;
4009

4010 4011 4012 4013 4014 4015 4016 4017 4018 4019 4020 4021 4022 4023 4024 4025 4026 4027
	switch (port->port) {
	case PORT_B:
		bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
		break;
	case PORT_C:
		bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
		break;
	case PORT_D:
		bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
		break;
	default:
		MISSING_CASE(port->port);
		return false;
	}

	return I915_READ(PORT_HOTPLUG_STAT) & bit;
}

4028 4029
static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
					struct intel_digital_port *port)
4030 4031 4032 4033 4034
{
	u32 bit;

	switch (port->port) {
	case PORT_B:
4035
		bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4036 4037
		break;
	case PORT_C:
4038
		bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4039 4040
		break;
	case PORT_D:
4041
		bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4042 4043 4044 4045
		break;
	default:
		MISSING_CASE(port->port);
		return false;
4046 4047
	}

4048
	return I915_READ(PORT_HOTPLUG_STAT) & bit;
4049 4050
}

4051
static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
4052
				       struct intel_digital_port *intel_dig_port)
4053
{
4054 4055
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	enum port port;
4056 4057
	u32 bit;

4058 4059
	intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
	switch (port) {
4060 4061 4062 4063 4064 4065 4066 4067 4068 4069
	case PORT_A:
		bit = BXT_DE_PORT_HP_DDIA;
		break;
	case PORT_B:
		bit = BXT_DE_PORT_HP_DDIB;
		break;
	case PORT_C:
		bit = BXT_DE_PORT_HP_DDIC;
		break;
	default:
4070
		MISSING_CASE(port);
4071 4072 4073 4074 4075 4076
		return false;
	}

	return I915_READ(GEN8_DE_PORT_ISR) & bit;
}

4077 4078 4079 4080 4081 4082 4083
/*
 * intel_digital_port_connected - is the specified port connected?
 * @dev_priv: i915 private structure
 * @port: the port to test
 *
 * Return %true if @port is connected, %false otherwise.
 */
4084
bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
4085 4086
					 struct intel_digital_port *port)
{
4087
	if (HAS_PCH_IBX(dev_priv))
4088
		return ibx_digital_port_connected(dev_priv, port);
4089
	else if (HAS_PCH_SPLIT(dev_priv))
4090
		return cpt_digital_port_connected(dev_priv, port);
4091 4092
	else if (IS_BROXTON(dev_priv))
		return bxt_digital_port_connected(dev_priv, port);
4093 4094
	else if (IS_GM45(dev_priv))
		return gm45_digital_port_connected(dev_priv, port);
4095 4096 4097 4098
	else
		return g4x_digital_port_connected(dev_priv, port);
}

4099
static struct edid *
4100
intel_dp_get_edid(struct intel_dp *intel_dp)
4101
{
4102
	struct intel_connector *intel_connector = intel_dp->attached_connector;
4103

4104 4105 4106 4107
	/* use cached edid if we have one */
	if (intel_connector->edid) {
		/* invalid edid */
		if (IS_ERR(intel_connector->edid))
4108 4109
			return NULL;

J
Jani Nikula 已提交
4110
		return drm_edid_duplicate(intel_connector->edid);
4111 4112 4113 4114
	} else
		return drm_get_edid(&intel_connector->base,
				    &intel_dp->aux.ddc);
}
4115

4116 4117 4118 4119 4120
static void
intel_dp_set_edid(struct intel_dp *intel_dp)
{
	struct intel_connector *intel_connector = intel_dp->attached_connector;
	struct edid *edid;
4121

4122
	intel_dp_unset_edid(intel_dp);
4123 4124 4125 4126 4127 4128 4129
	edid = intel_dp_get_edid(intel_dp);
	intel_connector->detect_edid = edid;

	if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
		intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
	else
		intel_dp->has_audio = drm_detect_monitor_audio(edid);
4130 4131
}

4132 4133
static void
intel_dp_unset_edid(struct intel_dp *intel_dp)
4134
{
4135
	struct intel_connector *intel_connector = intel_dp->attached_connector;
4136

4137 4138
	kfree(intel_connector->detect_edid);
	intel_connector->detect_edid = NULL;
4139

4140 4141
	intel_dp->has_audio = false;
}
4142

4143 4144
static void
intel_dp_long_pulse(struct intel_connector *intel_connector)
Z
Zhenyu Wang 已提交
4145
{
4146
	struct drm_connector *connector = &intel_connector->base;
Z
Zhenyu Wang 已提交
4147
	struct intel_dp *intel_dp = intel_attached_dp(connector);
4148 4149
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
4150
	struct drm_device *dev = connector->dev;
Z
Zhenyu Wang 已提交
4151
	enum drm_connector_status status;
4152
	enum intel_display_power_domain power_domain;
4153
	bool ret;
4154
	u8 sink_irq_vector;
Z
Zhenyu Wang 已提交
4155

4156 4157
	power_domain = intel_display_port_aux_power_domain(intel_encoder);
	intel_display_power_get(to_i915(dev), power_domain);
Z
Zhenyu Wang 已提交
4158

4159 4160 4161
	/* Can't disconnect eDP, but you can close the lid... */
	if (is_edp(intel_dp))
		status = edp_detect(intel_dp);
4162 4163 4164
	else if (intel_digital_port_connected(to_i915(dev),
					      dp_to_dig_port(intel_dp)))
		status = intel_dp_detect_dpcd(intel_dp);
Z
Zhenyu Wang 已提交
4165
	else
4166 4167
		status = connector_status_disconnected;

4168 4169 4170 4171 4172
	if (status != connector_status_connected) {
		intel_dp->compliance_test_active = 0;
		intel_dp->compliance_test_type = 0;
		intel_dp->compliance_test_data = 0;

4173 4174 4175 4176 4177 4178 4179 4180 4181
		if (intel_dp->is_mst) {
			DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
				      intel_dp->is_mst,
				      intel_dp->mst_mgr.mst_state);
			intel_dp->is_mst = false;
			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
							intel_dp->is_mst);
		}

4182
		goto out;
4183
	}
Z
Zhenyu Wang 已提交
4184

4185 4186 4187
	if (intel_encoder->type != INTEL_OUTPUT_EDP)
		intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;

4188 4189
	intel_dp_probe_oui(intel_dp);

4190 4191
	ret = intel_dp_probe_mst(intel_dp);
	if (ret) {
4192 4193 4194 4195 4196
		/*
		 * If we are in MST mode then this connector
		 * won't appear connected or have anything
		 * with EDID on it
		 */
4197 4198
		status = connector_status_disconnected;
		goto out;
4199 4200 4201 4202 4203 4204 4205 4206 4207 4208
	} else if (connector->status == connector_status_connected) {
		/*
		 * If display was connected already and is still connected
		 * check links status, there has been known issues of
		 * link loss triggerring long pulse!!!!
		 */
		drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
		intel_dp_check_link_status(intel_dp);
		drm_modeset_unlock(&dev->mode_config.connection_mutex);
		goto out;
4209 4210
	}

4211 4212 4213 4214 4215 4216 4217 4218
	/*
	 * Clearing NACK and defer counts to get their exact values
	 * while reading EDID which are required by Compliance tests
	 * 4.2.2.4 and 4.2.2.5
	 */
	intel_dp->aux.i2c_nack_count = 0;
	intel_dp->aux.i2c_defer_count = 0;

4219
	intel_dp_set_edid(intel_dp);
Z
Zhenyu Wang 已提交
4220

4221
	status = connector_status_connected;
4222
	intel_dp->detect_done = true;
4223

4224 4225 4226 4227 4228 4229 4230 4231 4232 4233 4234 4235 4236 4237
	/* Try to read the source of the interrupt */
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
		/* Clear interrupt source */
		drm_dp_dpcd_writeb(&intel_dp->aux,
				   DP_DEVICE_SERVICE_IRQ_VECTOR,
				   sink_irq_vector);

		if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
			intel_dp_handle_test_request(intel_dp);
		if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
			DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
	}

4238
out:
4239 4240
	if ((status != connector_status_connected) &&
	    (intel_dp->is_mst == false))
4241
		intel_dp_unset_edid(intel_dp);
4242

4243
	intel_display_power_put(to_i915(dev), power_domain);
4244 4245 4246 4247 4248 4249 4250 4251 4252 4253 4254 4255 4256 4257 4258 4259 4260 4261 4262 4263 4264 4265
	return;
}

static enum drm_connector_status
intel_dp_detect(struct drm_connector *connector, bool force)
{
	struct intel_dp *intel_dp = intel_attached_dp(connector);
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct intel_connector *intel_connector = to_intel_connector(connector);

	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
		      connector->base.id, connector->name);

	if (intel_dp->is_mst) {
		/* MST devices are disconnected from a monitor POV */
		intel_dp_unset_edid(intel_dp);
		if (intel_encoder->type != INTEL_OUTPUT_EDP)
			intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
		return connector_status_disconnected;
	}

4266 4267 4268 4269 4270
	/* If full detect is not performed yet, do a full detect */
	if (!intel_dp->detect_done)
		intel_dp_long_pulse(intel_dp->attached_connector);

	intel_dp->detect_done = false;
4271 4272 4273 4274 4275

	if (intel_connector->detect_edid)
		return connector_status_connected;
	else
		return connector_status_disconnected;
4276 4277
}

4278 4279
static void
intel_dp_force(struct drm_connector *connector)
4280
{
4281
	struct intel_dp *intel_dp = intel_attached_dp(connector);
4282
	struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4283
	struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4284
	enum intel_display_power_domain power_domain;
4285

4286 4287 4288
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
		      connector->base.id, connector->name);
	intel_dp_unset_edid(intel_dp);
4289

4290 4291
	if (connector->status != connector_status_connected)
		return;
4292

4293 4294
	power_domain = intel_display_port_aux_power_domain(intel_encoder);
	intel_display_power_get(dev_priv, power_domain);
4295 4296 4297

	intel_dp_set_edid(intel_dp);

4298
	intel_display_power_put(dev_priv, power_domain);
4299 4300 4301 4302 4303 4304 4305 4306 4307 4308 4309 4310 4311 4312 4313 4314

	if (intel_encoder->type != INTEL_OUTPUT_EDP)
		intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
}

static int intel_dp_get_modes(struct drm_connector *connector)
{
	struct intel_connector *intel_connector = to_intel_connector(connector);
	struct edid *edid;

	edid = intel_connector->detect_edid;
	if (edid) {
		int ret = intel_connector_update_modes(connector, edid);
		if (ret)
			return ret;
	}
4315

4316
	/* if eDP has no EDID, fall back to fixed mode */
4317 4318
	if (is_edp(intel_attached_dp(connector)) &&
	    intel_connector->panel.fixed_mode) {
4319
		struct drm_display_mode *mode;
4320 4321

		mode = drm_mode_duplicate(connector->dev,
4322
					  intel_connector->panel.fixed_mode);
4323
		if (mode) {
4324 4325 4326 4327
			drm_mode_probed_add(connector, mode);
			return 1;
		}
	}
4328

4329
	return 0;
4330 4331
}

4332 4333 4334 4335
static bool
intel_dp_detect_audio(struct drm_connector *connector)
{
	bool has_audio = false;
4336
	struct edid *edid;
4337

4338 4339
	edid = to_intel_connector(connector)->detect_edid;
	if (edid)
4340
		has_audio = drm_detect_monitor_audio(edid);
4341

4342 4343 4344
	return has_audio;
}

4345 4346 4347 4348 4349
static int
intel_dp_set_property(struct drm_connector *connector,
		      struct drm_property *property,
		      uint64_t val)
{
4350
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
4351
	struct intel_connector *intel_connector = to_intel_connector(connector);
4352 4353
	struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4354 4355
	int ret;

4356
	ret = drm_object_property_set_value(&connector->base, property, val);
4357 4358 4359
	if (ret)
		return ret;

4360
	if (property == dev_priv->force_audio_property) {
4361 4362 4363 4364
		int i = val;
		bool has_audio;

		if (i == intel_dp->force_audio)
4365 4366
			return 0;

4367
		intel_dp->force_audio = i;
4368

4369
		if (i == HDMI_AUDIO_AUTO)
4370 4371
			has_audio = intel_dp_detect_audio(connector);
		else
4372
			has_audio = (i == HDMI_AUDIO_ON);
4373 4374

		if (has_audio == intel_dp->has_audio)
4375 4376
			return 0;

4377
		intel_dp->has_audio = has_audio;
4378 4379 4380
		goto done;
	}

4381
	if (property == dev_priv->broadcast_rgb_property) {
4382
		bool old_auto = intel_dp->color_range_auto;
4383
		bool old_range = intel_dp->limited_color_range;
4384

4385 4386 4387 4388 4389 4390
		switch (val) {
		case INTEL_BROADCAST_RGB_AUTO:
			intel_dp->color_range_auto = true;
			break;
		case INTEL_BROADCAST_RGB_FULL:
			intel_dp->color_range_auto = false;
4391
			intel_dp->limited_color_range = false;
4392 4393 4394
			break;
		case INTEL_BROADCAST_RGB_LIMITED:
			intel_dp->color_range_auto = false;
4395
			intel_dp->limited_color_range = true;
4396 4397 4398 4399
			break;
		default:
			return -EINVAL;
		}
4400 4401

		if (old_auto == intel_dp->color_range_auto &&
4402
		    old_range == intel_dp->limited_color_range)
4403 4404
			return 0;

4405 4406 4407
		goto done;
	}

4408 4409 4410 4411 4412 4413
	if (is_edp(intel_dp) &&
	    property == connector->dev->mode_config.scaling_mode_property) {
		if (val == DRM_MODE_SCALE_NONE) {
			DRM_DEBUG_KMS("no scaling not supported\n");
			return -EINVAL;
		}
4414 4415 4416 4417 4418
		if (HAS_GMCH_DISPLAY(dev_priv) &&
		    val == DRM_MODE_SCALE_CENTER) {
			DRM_DEBUG_KMS("centering not supported\n");
			return -EINVAL;
		}
4419 4420 4421 4422 4423 4424 4425 4426 4427 4428

		if (intel_connector->panel.fitting_mode == val) {
			/* the eDP scaling property is not changed */
			return 0;
		}
		intel_connector->panel.fitting_mode = val;

		goto done;
	}

4429 4430 4431
	return -EINVAL;

done:
4432 4433
	if (intel_encoder->base.crtc)
		intel_crtc_restore_mode(intel_encoder->base.crtc);
4434 4435 4436 4437

	return 0;
}

4438
static void
4439
intel_dp_connector_destroy(struct drm_connector *connector)
4440
{
4441
	struct intel_connector *intel_connector = to_intel_connector(connector);
4442

4443
	kfree(intel_connector->detect_edid);
4444

4445 4446 4447
	if (!IS_ERR_OR_NULL(intel_connector->edid))
		kfree(intel_connector->edid);

4448 4449 4450
	/* Can't call is_edp() since the encoder may have been destroyed
	 * already. */
	if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4451
		intel_panel_fini(&intel_connector->panel);
4452

4453
	drm_connector_cleanup(connector);
4454
	kfree(connector);
4455 4456
}

P
Paulo Zanoni 已提交
4457
void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4458
{
4459 4460
	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
	struct intel_dp *intel_dp = &intel_dig_port->dp;
4461

4462
	intel_dp_mst_encoder_cleanup(intel_dig_port);
4463 4464
	if (is_edp(intel_dp)) {
		cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4465 4466 4467 4468
		/*
		 * vdd might still be enabled do to the delayed vdd off.
		 * Make sure vdd is actually turned off here.
		 */
4469
		pps_lock(intel_dp);
4470
		edp_panel_vdd_off_sync(intel_dp);
4471 4472
		pps_unlock(intel_dp);

4473 4474 4475 4476
		if (intel_dp->edp_notifier.notifier_call) {
			unregister_reboot_notifier(&intel_dp->edp_notifier);
			intel_dp->edp_notifier.notifier_call = NULL;
		}
4477
	}
4478
	drm_encoder_cleanup(encoder);
4479
	kfree(intel_dig_port);
4480 4481
}

4482
void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4483 4484 4485 4486 4487 4488
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);

	if (!is_edp(intel_dp))
		return;

4489 4490 4491 4492
	/*
	 * vdd might still be enabled do to the delayed vdd off.
	 * Make sure vdd is actually turned off here.
	 */
4493
	cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4494
	pps_lock(intel_dp);
4495
	edp_panel_vdd_off_sync(intel_dp);
4496
	pps_unlock(intel_dp);
4497 4498
}

4499 4500 4501 4502 4503 4504 4505 4506 4507 4508 4509 4510 4511 4512 4513 4514 4515 4516 4517
static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum intel_display_power_domain power_domain;

	lockdep_assert_held(&dev_priv->pps_mutex);

	if (!edp_have_panel_vdd(intel_dp))
		return;

	/*
	 * The VDD bit needs a power domain reference, so if the bit is
	 * already enabled when we boot or resume, grab this reference and
	 * schedule a vdd off, so we don't hold on to the reference
	 * indefinitely.
	 */
	DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4518
	power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base);
4519 4520 4521 4522 4523
	intel_display_power_get(dev_priv, power_domain);

	edp_panel_vdd_schedule_off(intel_dp);
}

4524
void intel_dp_encoder_reset(struct drm_encoder *encoder)
4525
{
4526 4527 4528 4529 4530 4531 4532 4533 4534 4535 4536 4537 4538
	struct intel_dp *intel_dp;

	if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
		return;

	intel_dp = enc_to_intel_dp(encoder);

	pps_lock(intel_dp);

	/*
	 * Read out the current power sequencer assignment,
	 * in case the BIOS did something with it.
	 */
4539
	if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev))
4540 4541 4542 4543 4544
		vlv_initial_power_sequencer_setup(intel_dp);

	intel_edp_panel_vdd_sanitize(intel_dp);

	pps_unlock(intel_dp);
4545 4546
}

4547
static const struct drm_connector_funcs intel_dp_connector_funcs = {
4548
	.dpms = drm_atomic_helper_connector_dpms,
4549
	.detect = intel_dp_detect,
4550
	.force = intel_dp_force,
4551
	.fill_modes = drm_helper_probe_single_connector_modes,
4552
	.set_property = intel_dp_set_property,
4553
	.atomic_get_property = intel_connector_atomic_get_property,
4554
	.destroy = intel_dp_connector_destroy,
4555
	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4556
	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
4557 4558 4559 4560 4561
};

static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
	.get_modes = intel_dp_get_modes,
	.mode_valid = intel_dp_mode_valid,
4562
	.best_encoder = intel_best_encoder,
4563 4564 4565
};

static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4566
	.reset = intel_dp_encoder_reset,
4567
	.destroy = intel_dp_encoder_destroy,
4568 4569
};

4570
enum irqreturn
4571 4572 4573
intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
{
	struct intel_dp *intel_dp = &intel_dig_port->dp;
4574
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
4575 4576
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
4577
	enum intel_display_power_domain power_domain;
4578
	enum irqreturn ret = IRQ_NONE;
4579

4580 4581
	if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
	    intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
4582
		intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
4583

4584 4585 4586 4587 4588 4589 4590 4591 4592
	if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
		/*
		 * vdd off can generate a long pulse on eDP which
		 * would require vdd on to handle it, and thus we
		 * would end up in an endless cycle of
		 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
		 */
		DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
			      port_name(intel_dig_port->port));
4593
		return IRQ_HANDLED;
4594 4595
	}

4596 4597
	DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
		      port_name(intel_dig_port->port),
4598
		      long_hpd ? "long" : "short");
4599

4600
	power_domain = intel_display_port_aux_power_domain(intel_encoder);
4601 4602
	intel_display_power_get(dev_priv, power_domain);

4603
	if (long_hpd) {
4604 4605
		/* indicate that we need to restart link training */
		intel_dp->train_set_valid = false;
4606

4607 4608 4609 4610
		intel_dp_long_pulse(intel_dp->attached_connector);
		if (intel_dp->is_mst)
			ret = IRQ_HANDLED;
		goto put_power;
4611 4612 4613

	} else {
		if (intel_dp->is_mst) {
4614 4615 4616 4617 4618 4619 4620 4621 4622 4623 4624 4625
			if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
				/*
				 * If we were in MST mode, and device is not
				 * there, get out of MST mode
				 */
				DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
					      intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
				intel_dp->is_mst = false;
				drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
								intel_dp->is_mst);
				goto put_power;
			}
4626 4627
		}

4628 4629 4630 4631 4632 4633
		if (!intel_dp->is_mst) {
			if (!intel_dp_short_pulse(intel_dp)) {
				intel_dp_long_pulse(intel_dp->attached_connector);
				goto put_power;
			}
		}
4634
	}
4635 4636 4637

	ret = IRQ_HANDLED;

4638 4639 4640 4641
put_power:
	intel_display_power_put(dev_priv, power_domain);

	return ret;
4642 4643
}

4644
/* check the VBT to see whether the eDP is on another port */
4645
bool intel_dp_is_edp(struct drm_device *dev, enum port port)
4646 4647 4648
{
	struct drm_i915_private *dev_priv = dev->dev_private;

4649 4650 4651 4652 4653 4654 4655
	/*
	 * eDP not supported on g4x. so bail out early just
	 * for a bit extra safety in case the VBT is bonkers.
	 */
	if (INTEL_INFO(dev)->gen < 5)
		return false;

4656 4657 4658
	if (port == PORT_A)
		return true;

4659
	return intel_bios_is_port_edp(dev_priv, port);
4660 4661
}

4662
void
4663 4664
intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
{
4665 4666
	struct intel_connector *intel_connector = to_intel_connector(connector);

4667
	intel_attach_force_audio_property(connector);
4668
	intel_attach_broadcast_rgb_property(connector);
4669
	intel_dp->color_range_auto = true;
4670 4671 4672

	if (is_edp(intel_dp)) {
		drm_mode_create_scaling_mode_property(connector->dev);
4673 4674
		drm_object_attach_property(
			&connector->base,
4675
			connector->dev->mode_config.scaling_mode_property,
4676 4677
			DRM_MODE_SCALE_ASPECT);
		intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
4678
	}
4679 4680
}

4681 4682
static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
{
4683
	intel_dp->panel_power_off_time = ktime_get_boottime();
4684 4685 4686 4687
	intel_dp->last_power_on = jiffies;
	intel_dp->last_backlight_off = jiffies;
}

4688 4689
static void
intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4690
				    struct intel_dp *intel_dp)
4691 4692
{
	struct drm_i915_private *dev_priv = dev->dev_private;
4693 4694
	struct edp_power_seq cur, vbt, spec,
		*final = &intel_dp->pps_delays;
4695
	u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
4696
	i915_reg_t pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
4697

V
Ville Syrjälä 已提交
4698 4699
	lockdep_assert_held(&dev_priv->pps_mutex);

4700 4701 4702 4703
	/* already initialized? */
	if (final->t11_t12 != 0)
		return;

4704 4705 4706 4707 4708 4709 4710 4711 4712 4713
	if (IS_BROXTON(dev)) {
		/*
		 * TODO: BXT has 2 sets of PPS registers.
		 * Correct Register for Broxton need to be identified
		 * using VBT. hardcoding for now
		 */
		pp_ctrl_reg = BXT_PP_CONTROL(0);
		pp_on_reg = BXT_PP_ON_DELAYS(0);
		pp_off_reg = BXT_PP_OFF_DELAYS(0);
	} else if (HAS_PCH_SPLIT(dev)) {
4714
		pp_ctrl_reg = PCH_PP_CONTROL;
4715 4716 4717 4718
		pp_on_reg = PCH_PP_ON_DELAYS;
		pp_off_reg = PCH_PP_OFF_DELAYS;
		pp_div_reg = PCH_PP_DIVISOR;
	} else {
4719 4720 4721 4722 4723 4724
		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);

		pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
		pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
		pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
		pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4725
	}
4726 4727 4728

	/* Workaround: Need to write PP_CONTROL with the unlock key as
	 * the very first thing. */
4729
	pp_ctl = ironlake_get_pp_control(intel_dp);
4730

4731 4732
	pp_on = I915_READ(pp_on_reg);
	pp_off = I915_READ(pp_off_reg);
4733 4734 4735 4736
	if (!IS_BROXTON(dev)) {
		I915_WRITE(pp_ctrl_reg, pp_ctl);
		pp_div = I915_READ(pp_div_reg);
	}
4737 4738 4739 4740 4741 4742 4743 4744 4745 4746 4747 4748 4749 4750

	/* Pull timing values out of registers */
	cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
		PANEL_POWER_UP_DELAY_SHIFT;

	cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
		PANEL_LIGHT_ON_DELAY_SHIFT;

	cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
		PANEL_LIGHT_OFF_DELAY_SHIFT;

	cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
		PANEL_POWER_DOWN_DELAY_SHIFT;

4751 4752 4753 4754 4755 4756 4757 4758 4759
	if (IS_BROXTON(dev)) {
		u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
			BXT_POWER_CYCLE_DELAY_SHIFT;
		if (tmp > 0)
			cur.t11_t12 = (tmp - 1) * 1000;
		else
			cur.t11_t12 = 0;
	} else {
		cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4760
		       PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4761
	}
4762 4763 4764 4765

	DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		      cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);

4766
	vbt = dev_priv->vbt.edp.pps;
4767 4768 4769 4770 4771 4772 4773 4774 4775 4776 4777 4778 4779 4780 4781 4782 4783 4784

	/* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
	 * our hw here, which are all in 100usec. */
	spec.t1_t3 = 210 * 10;
	spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
	spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
	spec.t10 = 500 * 10;
	/* This one is special and actually in units of 100ms, but zero
	 * based in the hw (so we need to add 100 ms). But the sw vbt
	 * table multiplies it with 1000 to make it in units of 100usec,
	 * too. */
	spec.t11_t12 = (510 + 100) * 10;

	DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		      vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);

	/* Use the max of the register settings and vbt. If both are
	 * unset, fall back to the spec limits. */
4785
#define assign_final(field)	final->field = (max(cur.field, vbt.field) == 0 ? \
4786 4787 4788 4789 4790 4791 4792 4793 4794
				       spec.field : \
				       max(cur.field, vbt.field))
	assign_final(t1_t3);
	assign_final(t8);
	assign_final(t9);
	assign_final(t10);
	assign_final(t11_t12);
#undef assign_final

4795
#define get_delay(field)	(DIV_ROUND_UP(final->field, 10))
4796 4797 4798 4799 4800 4801 4802
	intel_dp->panel_power_up_delay = get_delay(t1_t3);
	intel_dp->backlight_on_delay = get_delay(t8);
	intel_dp->backlight_off_delay = get_delay(t9);
	intel_dp->panel_power_down_delay = get_delay(t10);
	intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
#undef get_delay

4803 4804 4805 4806 4807 4808 4809 4810 4811 4812
	DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
		      intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
		      intel_dp->panel_power_cycle_delay);

	DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
		      intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
}

static void
intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4813
					      struct intel_dp *intel_dp)
4814 4815
{
	struct drm_i915_private *dev_priv = dev->dev_private;
4816
	u32 pp_on, pp_off, pp_div, port_sel = 0;
4817
	int div = dev_priv->rawclk_freq / 1000;
4818
	i915_reg_t pp_on_reg, pp_off_reg, pp_div_reg, pp_ctrl_reg;
4819
	enum port port = dp_to_dig_port(intel_dp)->port;
4820
	const struct edp_power_seq *seq = &intel_dp->pps_delays;
4821

V
Ville Syrjälä 已提交
4822
	lockdep_assert_held(&dev_priv->pps_mutex);
4823

4824 4825 4826 4827 4828 4829 4830 4831 4832 4833 4834
	if (IS_BROXTON(dev)) {
		/*
		 * TODO: BXT has 2 sets of PPS registers.
		 * Correct Register for Broxton need to be identified
		 * using VBT. hardcoding for now
		 */
		pp_ctrl_reg = BXT_PP_CONTROL(0);
		pp_on_reg = BXT_PP_ON_DELAYS(0);
		pp_off_reg = BXT_PP_OFF_DELAYS(0);

	} else if (HAS_PCH_SPLIT(dev)) {
4835 4836 4837 4838
		pp_on_reg = PCH_PP_ON_DELAYS;
		pp_off_reg = PCH_PP_OFF_DELAYS;
		pp_div_reg = PCH_PP_DIVISOR;
	} else {
4839 4840 4841 4842 4843
		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);

		pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
		pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
		pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4844 4845
	}

4846 4847 4848 4849 4850 4851 4852 4853
	/*
	 * And finally store the new values in the power sequencer. The
	 * backlight delays are set to 1 because we do manual waits on them. For
	 * T8, even BSpec recommends doing it. For T9, if we don't do this,
	 * we'll end up waiting for the backlight off delay twice: once when we
	 * do the manual sleep, and once when we disable the panel and wait for
	 * the PP_STATUS bit to become zero.
	 */
4854
	pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
4855 4856
		(1 << PANEL_LIGHT_ON_DELAY_SHIFT);
	pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
4857
		 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
4858 4859
	/* Compute the divisor for the pp clock, simply match the Bspec
	 * formula. */
4860 4861 4862 4863 4864 4865 4866 4867 4868 4869
	if (IS_BROXTON(dev)) {
		pp_div = I915_READ(pp_ctrl_reg);
		pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
		pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
				<< BXT_POWER_CYCLE_DELAY_SHIFT);
	} else {
		pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
		pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
				<< PANEL_POWER_CYCLE_DELAY_SHIFT);
	}
4870 4871 4872

	/* Haswell doesn't have any port selection bits for the panel
	 * power sequencer any more. */
4873
	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
4874
		port_sel = PANEL_PORT_SELECT_VLV(port);
4875
	} else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4876
		if (port == PORT_A)
4877
			port_sel = PANEL_PORT_SELECT_DPA;
4878
		else
4879
			port_sel = PANEL_PORT_SELECT_DPD;
4880 4881
	}

4882 4883 4884 4885
	pp_on |= port_sel;

	I915_WRITE(pp_on_reg, pp_on);
	I915_WRITE(pp_off_reg, pp_off);
4886 4887 4888 4889
	if (IS_BROXTON(dev))
		I915_WRITE(pp_ctrl_reg, pp_div);
	else
		I915_WRITE(pp_div_reg, pp_div);
4890 4891

	DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4892 4893
		      I915_READ(pp_on_reg),
		      I915_READ(pp_off_reg),
4894 4895
		      IS_BROXTON(dev) ?
		      (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) :
4896
		      I915_READ(pp_div_reg));
4897 4898
}

4899 4900 4901 4902 4903 4904 4905 4906 4907 4908 4909 4910
/**
 * intel_dp_set_drrs_state - program registers for RR switch to take effect
 * @dev: DRM device
 * @refresh_rate: RR to be programmed
 *
 * This function gets called when refresh rate (RR) has to be changed from
 * one frequency to another. Switches can be between high and low RR
 * supported by the panel or to any other RR based on media playback (in
 * this case, RR value needs to be passed from user space).
 *
 * The caller of this function needs to take a lock on dev_priv->drrs.
 */
4911
static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4912 4913 4914
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_encoder *encoder;
4915 4916
	struct intel_digital_port *dig_port = NULL;
	struct intel_dp *intel_dp = dev_priv->drrs.dp;
4917
	struct intel_crtc_state *config = NULL;
4918
	struct intel_crtc *intel_crtc = NULL;
4919
	enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
4920 4921 4922 4923 4924 4925

	if (refresh_rate <= 0) {
		DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
		return;
	}

4926 4927
	if (intel_dp == NULL) {
		DRM_DEBUG_KMS("DRRS not supported.\n");
4928 4929 4930
		return;
	}

4931
	/*
4932 4933
	 * FIXME: This needs proper synchronization with psr state for some
	 * platforms that cannot have PSR and DRRS enabled at the same time.
4934
	 */
4935

4936 4937
	dig_port = dp_to_dig_port(intel_dp);
	encoder = &dig_port->base;
4938
	intel_crtc = to_intel_crtc(encoder->base.crtc);
4939 4940 4941 4942 4943 4944

	if (!intel_crtc) {
		DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
		return;
	}

4945
	config = intel_crtc->config;
4946

4947
	if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
4948 4949 4950 4951
		DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
		return;
	}

4952 4953
	if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
			refresh_rate)
4954 4955
		index = DRRS_LOW_RR;

4956
	if (index == dev_priv->drrs.refresh_rate_type) {
4957 4958 4959 4960 4961 4962 4963 4964 4965 4966
		DRM_DEBUG_KMS(
			"DRRS requested for previously set RR...ignoring\n");
		return;
	}

	if (!intel_crtc->active) {
		DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
		return;
	}

D
Durgadoss R 已提交
4967
	if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
4968 4969 4970 4971 4972 4973 4974 4975 4976 4977 4978 4979
		switch (index) {
		case DRRS_HIGH_RR:
			intel_dp_set_m_n(intel_crtc, M1_N1);
			break;
		case DRRS_LOW_RR:
			intel_dp_set_m_n(intel_crtc, M2_N2);
			break;
		case DRRS_MAX_RR:
		default:
			DRM_ERROR("Unsupported refreshrate type\n");
		}
	} else if (INTEL_INFO(dev)->gen > 6) {
4980
		i915_reg_t reg = PIPECONF(intel_crtc->config->cpu_transcoder);
4981
		u32 val;
4982

4983
		val = I915_READ(reg);
4984
		if (index > DRRS_HIGH_RR) {
4985
			if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4986 4987 4988
				val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
			else
				val |= PIPECONF_EDP_RR_MODE_SWITCH;
4989
		} else {
4990
			if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4991 4992 4993
				val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
			else
				val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4994 4995 4996 4997
		}
		I915_WRITE(reg, val);
	}

4998 4999 5000 5001 5002
	dev_priv->drrs.refresh_rate_type = index;

	DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
}

5003 5004 5005 5006 5007 5008
/**
 * intel_edp_drrs_enable - init drrs struct if supported
 * @intel_dp: DP struct
 *
 * Initializes frontbuffer_bits and drrs.dp
 */
V
Vandana Kannan 已提交
5009 5010 5011 5012 5013 5014 5015 5016 5017 5018 5019 5020 5021 5022 5023 5024 5025 5026 5027 5028 5029 5030 5031 5032 5033 5034 5035
void intel_edp_drrs_enable(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = dig_port->base.base.crtc;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	if (!intel_crtc->config->has_drrs) {
		DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
		return;
	}

	mutex_lock(&dev_priv->drrs.mutex);
	if (WARN_ON(dev_priv->drrs.dp)) {
		DRM_ERROR("DRRS already enabled\n");
		goto unlock;
	}

	dev_priv->drrs.busy_frontbuffer_bits = 0;

	dev_priv->drrs.dp = intel_dp;

unlock:
	mutex_unlock(&dev_priv->drrs.mutex);
}

5036 5037 5038 5039 5040
/**
 * intel_edp_drrs_disable - Disable DRRS
 * @intel_dp: DP struct
 *
 */
V
Vandana Kannan 已提交
5041 5042 5043 5044 5045 5046 5047 5048 5049 5050 5051 5052 5053 5054 5055 5056 5057 5058 5059 5060 5061 5062 5063 5064 5065 5066 5067 5068
void intel_edp_drrs_disable(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = dig_port->base.base.crtc;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	if (!intel_crtc->config->has_drrs)
		return;

	mutex_lock(&dev_priv->drrs.mutex);
	if (!dev_priv->drrs.dp) {
		mutex_unlock(&dev_priv->drrs.mutex);
		return;
	}

	if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
		intel_dp_set_drrs_state(dev_priv->dev,
			intel_dp->attached_connector->panel.
			fixed_mode->vrefresh);

	dev_priv->drrs.dp = NULL;
	mutex_unlock(&dev_priv->drrs.mutex);

	cancel_delayed_work_sync(&dev_priv->drrs.work);
}

5069 5070 5071 5072 5073 5074 5075 5076 5077 5078 5079 5080 5081
static void intel_edp_drrs_downclock_work(struct work_struct *work)
{
	struct drm_i915_private *dev_priv =
		container_of(work, typeof(*dev_priv), drrs.work.work);
	struct intel_dp *intel_dp;

	mutex_lock(&dev_priv->drrs.mutex);

	intel_dp = dev_priv->drrs.dp;

	if (!intel_dp)
		goto unlock;

5082
	/*
5083 5084
	 * The delayed work can race with an invalidate hence we need to
	 * recheck.
5085 5086
	 */

5087 5088
	if (dev_priv->drrs.busy_frontbuffer_bits)
		goto unlock;
5089

5090 5091 5092 5093
	if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
		intel_dp_set_drrs_state(dev_priv->dev,
			intel_dp->attached_connector->panel.
			downclock_mode->vrefresh);
5094

5095 5096
unlock:
	mutex_unlock(&dev_priv->drrs.mutex);
5097 5098
}

5099
/**
5100
 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5101 5102 5103
 * @dev: DRM device
 * @frontbuffer_bits: frontbuffer plane tracking bits
 *
5104 5105
 * This function gets called everytime rendering on the given planes start.
 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5106 5107 5108
 *
 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
 */
5109 5110 5111 5112 5113 5114 5115
void intel_edp_drrs_invalidate(struct drm_device *dev,
		unsigned frontbuffer_bits)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc;
	enum pipe pipe;

5116
	if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5117 5118
		return;

5119
	cancel_delayed_work(&dev_priv->drrs.work);
5120

5121
	mutex_lock(&dev_priv->drrs.mutex);
5122 5123 5124 5125 5126
	if (!dev_priv->drrs.dp) {
		mutex_unlock(&dev_priv->drrs.mutex);
		return;
	}

5127 5128 5129
	crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
	pipe = to_intel_crtc(crtc)->pipe;

5130 5131 5132
	frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
	dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;

5133
	/* invalidate means busy screen hence upclock */
5134
	if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5135 5136 5137 5138 5139 5140 5141
		intel_dp_set_drrs_state(dev_priv->dev,
				dev_priv->drrs.dp->attached_connector->panel.
				fixed_mode->vrefresh);

	mutex_unlock(&dev_priv->drrs.mutex);
}

5142
/**
5143
 * intel_edp_drrs_flush - Restart Idleness DRRS
5144 5145 5146
 * @dev: DRM device
 * @frontbuffer_bits: frontbuffer plane tracking bits
 *
5147 5148 5149 5150
 * This function gets called every time rendering on the given planes has
 * completed or flip on a crtc is completed. So DRRS should be upclocked
 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
 * if no other planes are dirty.
5151 5152 5153
 *
 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
 */
5154 5155 5156 5157 5158 5159 5160
void intel_edp_drrs_flush(struct drm_device *dev,
		unsigned frontbuffer_bits)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc;
	enum pipe pipe;

5161
	if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5162 5163
		return;

5164
	cancel_delayed_work(&dev_priv->drrs.work);
5165

5166
	mutex_lock(&dev_priv->drrs.mutex);
5167 5168 5169 5170 5171
	if (!dev_priv->drrs.dp) {
		mutex_unlock(&dev_priv->drrs.mutex);
		return;
	}

5172 5173
	crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
	pipe = to_intel_crtc(crtc)->pipe;
5174 5175

	frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5176 5177
	dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;

5178
	/* flush means busy screen hence upclock */
5179
	if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5180 5181 5182 5183 5184 5185 5186 5187 5188
		intel_dp_set_drrs_state(dev_priv->dev,
				dev_priv->drrs.dp->attached_connector->panel.
				fixed_mode->vrefresh);

	/*
	 * flush also means no more activity hence schedule downclock, if all
	 * other fbs are quiescent too
	 */
	if (!dev_priv->drrs.busy_frontbuffer_bits)
5189 5190 5191 5192 5193
		schedule_delayed_work(&dev_priv->drrs.work,
				msecs_to_jiffies(1000));
	mutex_unlock(&dev_priv->drrs.mutex);
}

5194 5195 5196 5197 5198 5199 5200 5201 5202 5203 5204 5205 5206 5207 5208 5209 5210 5211 5212 5213 5214 5215 5216
/**
 * DOC: Display Refresh Rate Switching (DRRS)
 *
 * Display Refresh Rate Switching (DRRS) is a power conservation feature
 * which enables swtching between low and high refresh rates,
 * dynamically, based on the usage scenario. This feature is applicable
 * for internal panels.
 *
 * Indication that the panel supports DRRS is given by the panel EDID, which
 * would list multiple refresh rates for one resolution.
 *
 * DRRS is of 2 types - static and seamless.
 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
 * (may appear as a blink on screen) and is used in dock-undock scenario.
 * Seamless DRRS involves changing RR without any visual effect to the user
 * and can be used during normal system usage. This is done by programming
 * certain registers.
 *
 * Support for static/seamless DRRS may be indicated in the VBT based on
 * inputs from the panel spec.
 *
 * DRRS saves power by switching to low RR based on usage scenarios.
 *
D
Daniel Vetter 已提交
5217 5218 5219 5220 5221 5222 5223 5224
 * The implementation is based on frontbuffer tracking implementation.  When
 * there is a disturbance on the screen triggered by user activity or a periodic
 * system activity, DRRS is disabled (RR is changed to high RR).  When there is
 * no movement on screen, after a timeout of 1 second, a switch to low RR is
 * made.
 *
 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
 * and intel_edp_drrs_flush() are called.
5225 5226 5227 5228 5229 5230 5231 5232 5233 5234 5235 5236 5237 5238 5239 5240 5241 5242 5243
 *
 * DRRS can be further extended to support other internal panels and also
 * the scenario of video playback wherein RR is set based on the rate
 * requested by userspace.
 */

/**
 * intel_dp_drrs_init - Init basic DRRS work and mutex.
 * @intel_connector: eDP connector
 * @fixed_mode: preferred mode of panel
 *
 * This function is  called only once at driver load to initialize basic
 * DRRS stuff.
 *
 * Returns:
 * Downclock mode if panel supports it, else return NULL.
 * DRRS support is determined by the presence of downclock mode (apart
 * from VBT setting).
 */
5244
static struct drm_display_mode *
5245 5246
intel_dp_drrs_init(struct intel_connector *intel_connector,
		struct drm_display_mode *fixed_mode)
5247 5248
{
	struct drm_connector *connector = &intel_connector->base;
5249
	struct drm_device *dev = connector->dev;
5250 5251 5252
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_display_mode *downclock_mode = NULL;

5253 5254 5255
	INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
	mutex_init(&dev_priv->drrs.mutex);

5256 5257 5258 5259 5260 5261
	if (INTEL_INFO(dev)->gen <= 6) {
		DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
		return NULL;
	}

	if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5262
		DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5263 5264 5265 5266 5267 5268 5269
		return NULL;
	}

	downclock_mode = intel_find_panel_downclock
					(dev, fixed_mode, connector);

	if (!downclock_mode) {
5270
		DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5271 5272 5273
		return NULL;
	}

5274
	dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5275

5276
	dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5277
	DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5278 5279 5280
	return downclock_mode;
}

5281
static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5282
				     struct intel_connector *intel_connector)
5283 5284 5285
{
	struct drm_connector *connector = &intel_connector->base;
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5286 5287
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct drm_device *dev = intel_encoder->base.dev;
5288 5289
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_display_mode *fixed_mode = NULL;
5290
	struct drm_display_mode *downclock_mode = NULL;
5291 5292 5293
	bool has_dpcd;
	struct drm_display_mode *scan;
	struct edid *edid;
5294
	enum pipe pipe = INVALID_PIPE;
5295 5296 5297 5298

	if (!is_edp(intel_dp))
		return true;

5299 5300 5301
	pps_lock(intel_dp);
	intel_edp_panel_vdd_sanitize(intel_dp);
	pps_unlock(intel_dp);
5302

5303 5304 5305 5306 5307 5308 5309 5310 5311 5312 5313 5314 5315 5316 5317
	/* Cache DPCD and EDID for edp. */
	has_dpcd = intel_dp_get_dpcd(intel_dp);

	if (has_dpcd) {
		if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
			dev_priv->no_aux_handshake =
				intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
				DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
	} else {
		/* if this fails, presume the device is a ghost */
		DRM_INFO("failed to retrieve link info, disabling eDP\n");
		return false;
	}

	/* We now know it's not a ghost, init power sequence regs. */
5318
	pps_lock(intel_dp);
5319
	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5320
	pps_unlock(intel_dp);
5321

5322
	mutex_lock(&dev->mode_config.mutex);
5323
	edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5324 5325 5326 5327 5328 5329 5330 5331 5332 5333 5334 5335 5336 5337 5338 5339 5340 5341
	if (edid) {
		if (drm_add_edid_modes(connector, edid)) {
			drm_mode_connector_update_edid_property(connector,
								edid);
			drm_edid_to_eld(connector, edid);
		} else {
			kfree(edid);
			edid = ERR_PTR(-EINVAL);
		}
	} else {
		edid = ERR_PTR(-ENOENT);
	}
	intel_connector->edid = edid;

	/* prefer fixed mode from EDID if available */
	list_for_each_entry(scan, &connector->probed_modes, head) {
		if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
			fixed_mode = drm_mode_duplicate(dev, scan);
5342 5343
			downclock_mode = intel_dp_drrs_init(
						intel_connector, fixed_mode);
5344 5345 5346 5347 5348 5349 5350 5351 5352 5353 5354
			break;
		}
	}

	/* fallback to VBT if available for eDP */
	if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
		fixed_mode = drm_mode_duplicate(dev,
					dev_priv->vbt.lfp_lvds_vbt_mode);
		if (fixed_mode)
			fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
	}
5355
	mutex_unlock(&dev->mode_config.mutex);
5356

5357
	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5358 5359
		intel_dp->edp_notifier.notifier_call = edp_notify_handler;
		register_reboot_notifier(&intel_dp->edp_notifier);
5360 5361 5362 5363 5364 5365 5366 5367 5368 5369 5370 5371 5372 5373 5374 5375 5376 5377 5378

		/*
		 * Figure out the current pipe for the initial backlight setup.
		 * If the current pipe isn't valid, try the PPS pipe, and if that
		 * fails just assume pipe A.
		 */
		if (IS_CHERRYVIEW(dev))
			pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
		else
			pipe = PORT_TO_PIPE(intel_dp->DP);

		if (pipe != PIPE_A && pipe != PIPE_B)
			pipe = intel_dp->pps_pipe;

		if (pipe != PIPE_A && pipe != PIPE_B)
			pipe = PIPE_A;

		DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
			      pipe_name(pipe));
5379 5380
	}

5381
	intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5382
	intel_connector->panel.backlight.power = intel_edp_backlight_power;
5383
	intel_panel_setup_backlight(connector, pipe);
5384 5385 5386 5387

	return true;
}

5388
bool
5389 5390
intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
			struct intel_connector *intel_connector)
5391
{
5392 5393 5394 5395
	struct drm_connector *connector = &intel_connector->base;
	struct intel_dp *intel_dp = &intel_dig_port->dp;
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct drm_device *dev = intel_encoder->base.dev;
5396
	struct drm_i915_private *dev_priv = dev->dev_private;
5397
	enum port port = intel_dig_port->port;
5398
	int type, ret;
5399

5400 5401 5402 5403 5404
	if (WARN(intel_dig_port->max_lanes < 1,
		 "Not enough lanes (%d) for DP on port %c\n",
		 intel_dig_port->max_lanes, port_name(port)))
		return false;

5405 5406
	intel_dp->pps_pipe = INVALID_PIPE;

5407
	/* intel_dp vfuncs */
5408 5409
	if (INTEL_INFO(dev)->gen >= 9)
		intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5410 5411 5412 5413 5414
	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
		intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
	else if (HAS_PCH_SPLIT(dev))
		intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
	else
5415
		intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
5416

5417 5418 5419
	if (INTEL_INFO(dev)->gen >= 9)
		intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
	else
5420
		intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
5421

5422 5423 5424
	if (HAS_DDI(dev))
		intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;

5425 5426
	/* Preserve the current hw state. */
	intel_dp->DP = I915_READ(intel_dp->output_reg);
5427
	intel_dp->attached_connector = intel_connector;
5428

5429
	if (intel_dp_is_edp(dev, port))
5430
		type = DRM_MODE_CONNECTOR_eDP;
5431 5432
	else
		type = DRM_MODE_CONNECTOR_DisplayPort;
5433

5434 5435 5436 5437 5438 5439 5440 5441
	/*
	 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
	 * for DP the encoder type can be set by the caller to
	 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
	 */
	if (type == DRM_MODE_CONNECTOR_eDP)
		intel_encoder->type = INTEL_OUTPUT_EDP;

5442
	/* eDP only on port B and/or C on vlv/chv */
5443 5444
	if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
		    is_edp(intel_dp) && port != PORT_B && port != PORT_C))
5445 5446
		return false;

5447 5448 5449 5450
	DRM_DEBUG_KMS("Adding %s connector on port %c\n",
			type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
			port_name(port));

5451
	drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5452 5453 5454 5455 5456
	drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);

	connector->interlace_allowed = true;
	connector->doublescan_allowed = 0;

5457
	INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5458
			  edp_panel_vdd_work);
5459

5460
	intel_connector_attach_encoder(intel_connector, intel_encoder);
5461
	drm_connector_register(connector);
5462

P
Paulo Zanoni 已提交
5463
	if (HAS_DDI(dev))
5464 5465 5466
		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
	else
		intel_connector->get_hw_state = intel_connector_get_hw_state;
5467
	intel_connector->unregister = intel_dp_connector_unregister;
5468

5469
	/* Set up the hotplug pin. */
5470 5471
	switch (port) {
	case PORT_A:
5472
		intel_encoder->hpd_pin = HPD_PORT_A;
5473 5474
		break;
	case PORT_B:
5475
		intel_encoder->hpd_pin = HPD_PORT_B;
5476
		if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
5477
			intel_encoder->hpd_pin = HPD_PORT_A;
5478 5479
		break;
	case PORT_C:
5480
		intel_encoder->hpd_pin = HPD_PORT_C;
5481 5482
		break;
	case PORT_D:
5483
		intel_encoder->hpd_pin = HPD_PORT_D;
5484
		break;
X
Xiong Zhang 已提交
5485 5486 5487
	case PORT_E:
		intel_encoder->hpd_pin = HPD_PORT_E;
		break;
5488
	default:
5489
		BUG();
5490 5491
	}

5492
	if (is_edp(intel_dp)) {
5493
		pps_lock(intel_dp);
5494
		intel_dp_init_panel_power_timestamps(intel_dp);
5495
		if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
5496
			vlv_initial_power_sequencer_setup(intel_dp);
5497
		else
5498
			intel_dp_init_panel_power_sequencer(dev, intel_dp);
5499
		pps_unlock(intel_dp);
5500
	}
5501

5502 5503 5504
	ret = intel_dp_aux_init(intel_dp, intel_connector);
	if (ret)
		goto fail;
5505

5506
	/* init MST on ports that can support it */
5507 5508 5509 5510
	if (HAS_DP_MST(dev) &&
	    (port == PORT_B || port == PORT_C || port == PORT_D))
		intel_dp_mst_encoder_init(intel_dig_port,
					  intel_connector->base.base.id);
5511

5512
	if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5513 5514 5515
		intel_dp_aux_fini(intel_dp);
		intel_dp_mst_encoder_cleanup(intel_dig_port);
		goto fail;
5516
	}
5517

5518 5519
	intel_dp_add_properties(intel_dp, connector);

5520 5521 5522 5523 5524 5525 5526 5527
	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
	 * 0xd.  Failure to do so will result in spurious interrupts being
	 * generated on the port when a cable is not attached.
	 */
	if (IS_G4X(dev) && !IS_GM45(dev)) {
		u32 temp = I915_READ(PEG_BAND_GAP_DATA);
		I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
	}
5528

5529 5530
	i915_debugfs_connector_add(connector);

5531
	return true;
5532 5533 5534 5535 5536 5537 5538 5539 5540 5541 5542 5543 5544 5545 5546 5547

fail:
	if (is_edp(intel_dp)) {
		cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
		/*
		 * vdd might still be enabled do to the delayed vdd off.
		 * Make sure vdd is actually turned off here.
		 */
		pps_lock(intel_dp);
		edp_panel_vdd_off_sync(intel_dp);
		pps_unlock(intel_dp);
	}
	drm_connector_unregister(connector);
	drm_connector_cleanup(connector);

	return false;
5548
}
5549 5550

void
5551 5552
intel_dp_init(struct drm_device *dev,
	      i915_reg_t output_reg, enum port port)
5553
{
5554
	struct drm_i915_private *dev_priv = dev->dev_private;
5555 5556 5557 5558 5559
	struct intel_digital_port *intel_dig_port;
	struct intel_encoder *intel_encoder;
	struct drm_encoder *encoder;
	struct intel_connector *intel_connector;

5560
	intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
5561 5562 5563
	if (!intel_dig_port)
		return;

5564
	intel_connector = intel_connector_alloc();
S
Sudip Mukherjee 已提交
5565 5566
	if (!intel_connector)
		goto err_connector_alloc;
5567 5568 5569 5570

	intel_encoder = &intel_dig_port->base;
	encoder = &intel_encoder->base;

S
Sudip Mukherjee 已提交
5571
	if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5572
			     DRM_MODE_ENCODER_TMDS, NULL))
S
Sudip Mukherjee 已提交
5573
		goto err_encoder_init;
5574

5575
	intel_encoder->compute_config = intel_dp_compute_config;
P
Paulo Zanoni 已提交
5576 5577
	intel_encoder->disable = intel_disable_dp;
	intel_encoder->get_hw_state = intel_dp_get_hw_state;
5578
	intel_encoder->get_config = intel_dp_get_config;
5579
	intel_encoder->suspend = intel_dp_encoder_suspend;
5580
	if (IS_CHERRYVIEW(dev)) {
5581
		intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
5582 5583
		intel_encoder->pre_enable = chv_pre_enable_dp;
		intel_encoder->enable = vlv_enable_dp;
5584
		intel_encoder->post_disable = chv_post_disable_dp;
5585
		intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
5586
	} else if (IS_VALLEYVIEW(dev)) {
5587
		intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
5588 5589
		intel_encoder->pre_enable = vlv_pre_enable_dp;
		intel_encoder->enable = vlv_enable_dp;
5590
		intel_encoder->post_disable = vlv_post_disable_dp;
5591
	} else {
5592 5593
		intel_encoder->pre_enable = g4x_pre_enable_dp;
		intel_encoder->enable = g4x_enable_dp;
5594 5595
		if (INTEL_INFO(dev)->gen >= 5)
			intel_encoder->post_disable = ilk_post_disable_dp;
5596
	}
5597

5598
	intel_dig_port->port = port;
5599
	intel_dig_port->dp.output_reg = output_reg;
5600
	intel_dig_port->max_lanes = 4;
5601

P
Paulo Zanoni 已提交
5602
	intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
5603 5604 5605 5606 5607 5608 5609 5610
	if (IS_CHERRYVIEW(dev)) {
		if (port == PORT_D)
			intel_encoder->crtc_mask = 1 << 2;
		else
			intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
	} else {
		intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
	}
5611
	intel_encoder->cloneable = 0;
5612

5613
	intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5614
	dev_priv->hotplug.irq_port[port] = intel_dig_port;
5615

S
Sudip Mukherjee 已提交
5616 5617 5618 5619 5620 5621 5622
	if (!intel_dp_init_connector(intel_dig_port, intel_connector))
		goto err_init_connector;

	return;

err_init_connector:
	drm_encoder_cleanup(encoder);
S
Sudip Mukherjee 已提交
5623
err_encoder_init:
S
Sudip Mukherjee 已提交
5624 5625 5626 5627 5628
	kfree(intel_connector);
err_connector_alloc:
	kfree(intel_dig_port);

	return;
5629
}
5630 5631 5632 5633 5634 5635 5636 5637

void intel_dp_mst_suspend(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;

	/* disable MST */
	for (i = 0; i < I915_MAX_PORTS; i++) {
5638
		struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
5639 5640 5641 5642 5643 5644 5645 5646 5647 5648 5649 5650 5651 5652 5653 5654 5655 5656
		if (!intel_dig_port)
			continue;

		if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
			if (!intel_dig_port->dp.can_mst)
				continue;
			if (intel_dig_port->dp.is_mst)
				drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
		}
	}
}

void intel_dp_mst_resume(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;

	for (i = 0; i < I915_MAX_PORTS; i++) {
5657
		struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
5658 5659 5660 5661 5662 5663 5664 5665 5666 5667 5668 5669 5670 5671 5672
		if (!intel_dig_port)
			continue;
		if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
			int ret;

			if (!intel_dig_port->dp.can_mst)
				continue;

			ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
			if (ret != 0) {
				intel_dp_check_mst_status(&intel_dig_port->dp);
			}
		}
	}
}