ohci.c 101.1 KB
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/*
 * Driver for OHCI 1394 controllers
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 *
 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 */

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#include <linux/bitops.h>
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#include <linux/bug.h>
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#include <linux/compiler.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/firewire.h>
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#include <linux/firewire-constants.h>
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#include <linux/init.h>
#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/mutex.h>
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#include <linux/pci.h>
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#include <linux/pci_ids.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/string.h>
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#include <linux/time.h>
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#include <linux/vmalloc.h>
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#include <linux/workqueue.h>
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#include <asm/byteorder.h>
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#include <asm/page.h>
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#include <asm/system.h>
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#ifdef CONFIG_PPC_PMAC
#include <asm/pmac_feature.h>
#endif

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#include "core.h"
#include "ohci.h"
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#define DESCRIPTOR_OUTPUT_MORE		0
#define DESCRIPTOR_OUTPUT_LAST		(1 << 12)
#define DESCRIPTOR_INPUT_MORE		(2 << 12)
#define DESCRIPTOR_INPUT_LAST		(3 << 12)
#define DESCRIPTOR_STATUS		(1 << 11)
#define DESCRIPTOR_KEY_IMMEDIATE	(2 << 8)
#define DESCRIPTOR_PING			(1 << 7)
#define DESCRIPTOR_YY			(1 << 6)
#define DESCRIPTOR_NO_IRQ		(0 << 4)
#define DESCRIPTOR_IRQ_ERROR		(1 << 4)
#define DESCRIPTOR_IRQ_ALWAYS		(3 << 4)
#define DESCRIPTOR_BRANCH_ALWAYS	(3 << 2)
#define DESCRIPTOR_WAIT			(3 << 0)
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struct descriptor {
	__le16 req_count;
	__le16 control;
	__le32 data_address;
	__le32 branch_address;
	__le16 res_count;
	__le16 transfer_status;
} __attribute__((aligned(16)));

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#define CONTROL_SET(regs)	(regs)
#define CONTROL_CLEAR(regs)	((regs) + 4)
#define COMMAND_PTR(regs)	((regs) + 12)
#define CONTEXT_MATCH(regs)	((regs) + 16)
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#define AR_BUFFER_SIZE	(32*1024)
#define AR_BUFFERS_MIN	DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
/* we need at least two pages for proper list management */
#define AR_BUFFERS	(AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)

#define MAX_ASYNC_PAYLOAD	4096
#define MAX_AR_PACKET_SIZE	(16 + MAX_ASYNC_PAYLOAD + 4)
#define AR_WRAPAROUND_PAGES	DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
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struct ar_context {
	struct fw_ohci *ohci;
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	struct page *pages[AR_BUFFERS];
	void *buffer;
	struct descriptor *descriptors;
	dma_addr_t descriptors_bus;
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	void *pointer;
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	unsigned int last_buffer_index;
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	u32 regs;
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	struct tasklet_struct tasklet;
};

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struct context;

typedef int (*descriptor_callback_t)(struct context *ctx,
				     struct descriptor *d,
				     struct descriptor *last);
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/*
 * A buffer that contains a block of DMA-able coherent memory used for
 * storing a portion of a DMA descriptor program.
 */
struct descriptor_buffer {
	struct list_head list;
	dma_addr_t buffer_bus;
	size_t buffer_size;
	size_t used;
	struct descriptor buffer[0];
};

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struct context {
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	struct fw_ohci *ohci;
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	u32 regs;
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	int total_allocation;
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	u32 current_bus;
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	bool running;
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	bool flushing;
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	/*
	 * List of page-sized buffers for storing DMA descriptors.
	 * Head of list contains buffers in use and tail of list contains
	 * free buffers.
	 */
	struct list_head buffer_list;

	/*
	 * Pointer to a buffer inside buffer_list that contains the tail
	 * end of the current DMA program.
	 */
	struct descriptor_buffer *buffer_tail;

	/*
	 * The descriptor containing the branch address of the first
	 * descriptor that has not yet been filled by the device.
	 */
	struct descriptor *last;

	/*
	 * The last descriptor in the DMA program.  It contains the branch
	 * address that must be updated upon appending a new descriptor.
	 */
	struct descriptor *prev;
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	descriptor_callback_t callback;

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	struct tasklet_struct tasklet;
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};

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#define IT_HEADER_SY(v)          ((v) <<  0)
#define IT_HEADER_TCODE(v)       ((v) <<  4)
#define IT_HEADER_CHANNEL(v)     ((v) <<  8)
#define IT_HEADER_TAG(v)         ((v) << 14)
#define IT_HEADER_SPEED(v)       ((v) << 16)
#define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
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struct iso_context {
	struct fw_iso_context base;
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	struct context context;
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	int excess_bytes;
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	void *header;
	size_t header_length;
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	u8 sync;
	u8 tags;
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};

#define CONFIG_ROM_SIZE 1024

struct fw_ohci {
	struct fw_card card;

	__iomem char *registers;
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	int node_id;
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	int generation;
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	int request_generation;	/* for timestamping incoming requests */
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	unsigned quirks;
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	unsigned int pri_req_max;
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	u32 bus_time;
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	bool is_root;
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	bool csr_state_setclear_abdicate;
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	int n_ir;
	int n_it;
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	/*
	 * Spinlock for accessing fw_ohci data.  Never call out of
	 * this driver with this lock held.
	 */
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	spinlock_t lock;

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	struct mutex phy_reg_mutex;

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	void *misc_buffer;
	dma_addr_t misc_buffer_bus;

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	struct ar_context ar_request_ctx;
	struct ar_context ar_response_ctx;
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	struct context at_request_ctx;
	struct context at_response_ctx;
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	u32 it_context_support;
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	u32 it_context_mask;     /* unoccupied IT contexts */
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	struct iso_context *it_context_list;
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	u64 ir_context_channels; /* unoccupied channels */
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	u32 ir_context_support;
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	u32 ir_context_mask;     /* unoccupied IR contexts */
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	struct iso_context *ir_context_list;
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	u64 mc_channels; /* channels in use by the multichannel IR context */
	bool mc_allocated;
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	__be32    *config_rom;
	dma_addr_t config_rom_bus;
	__be32    *next_config_rom;
	dma_addr_t next_config_rom_bus;
	__be32     next_header;

	__le32    *self_id_cpu;
	dma_addr_t self_id_bus;
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	struct work_struct bus_reset_work;
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	u32 self_id_buffer[512];
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};

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static inline struct fw_ohci *fw_ohci(struct fw_card *card)
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{
	return container_of(card, struct fw_ohci, card);
}

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#define IT_CONTEXT_CYCLE_MATCH_ENABLE	0x80000000
#define IR_CONTEXT_BUFFER_FILL		0x80000000
#define IR_CONTEXT_ISOCH_HEADER		0x40000000
#define IR_CONTEXT_CYCLE_MATCH_ENABLE	0x20000000
#define IR_CONTEXT_MULTI_CHANNEL_MODE	0x10000000
#define IR_CONTEXT_DUAL_BUFFER_MODE	0x08000000
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#define CONTEXT_RUN	0x8000
#define CONTEXT_WAKE	0x1000
#define CONTEXT_DEAD	0x0800
#define CONTEXT_ACTIVE	0x0400

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#define OHCI1394_MAX_AT_REQ_RETRIES	0xf
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#define OHCI1394_MAX_AT_RESP_RETRIES	0x2
#define OHCI1394_MAX_PHYS_RESP_RETRIES	0x8

#define OHCI1394_REGISTER_SIZE		0x800
#define OHCI1394_PCI_HCI_Control	0x40
#define SELF_ID_BUF_SIZE		0x800
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#define OHCI_TCODE_PHY_PACKET		0x0e
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#define OHCI_VERSION_1_1		0x010010
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static char ohci_driver_name[] = KBUILD_MODNAME;

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#define PCI_DEVICE_ID_AGERE_FW643	0x5901
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#define PCI_DEVICE_ID_JMICRON_JMB38X_FW	0x2380
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#define PCI_DEVICE_ID_TI_TSB12LV22	0x8009
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#define PCI_DEVICE_ID_TI_TSB12LV26	0x8020
#define PCI_DEVICE_ID_TI_TSB82AA2	0x8025
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#define PCI_VENDOR_ID_PINNACLE_SYSTEMS	0x11bd
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#define QUIRK_CYCLE_TIMER		1
#define QUIRK_RESET_PACKET		2
#define QUIRK_BE_HEADERS		4
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#define QUIRK_NO_1394A			8
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#define QUIRK_NO_MSI			16
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#define QUIRK_TI_SLLZ059		32
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/* In case of multiple matches in ohci_quirks[], only the first one is used. */
static const struct {
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	unsigned short vendor, device, revision, flags;
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} ohci_quirks[] = {
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	{PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
		QUIRK_CYCLE_TIMER},

	{PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
		QUIRK_BE_HEADERS},

	{PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
		QUIRK_NO_MSI},

	{PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
		QUIRK_NO_MSI},

	{PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
		QUIRK_CYCLE_TIMER},

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	{PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID,
		QUIRK_NO_MSI},

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	{PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
		QUIRK_CYCLE_TIMER},

	{PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
		QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},

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	{PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID,
		QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},

	{PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID,
		QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},

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	{PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
		QUIRK_RESET_PACKET},

	{PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
		QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
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};

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/* This overrides anything that was found in ohci_quirks[]. */
static int param_quirks;
module_param_named(quirks, param_quirks, int, 0644);
MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
	", nonatomic cycle timer = "	__stringify(QUIRK_CYCLE_TIMER)
	", reset packet generation = "	__stringify(QUIRK_RESET_PACKET)
	", AR/selfID endianess = "	__stringify(QUIRK_BE_HEADERS)
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	", no 1394a enhancements = "	__stringify(QUIRK_NO_1394A)
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	", disable MSI = "		__stringify(QUIRK_NO_MSI)
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	", TI SLLZ059 erratum = "	__stringify(QUIRK_TI_SLLZ059)
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	")");

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#define OHCI_PARAM_DEBUG_AT_AR		1
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#define OHCI_PARAM_DEBUG_SELFIDS	2
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#define OHCI_PARAM_DEBUG_IRQS		4
#define OHCI_PARAM_DEBUG_BUSRESETS	8 /* only effective before chip init */
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#ifdef CONFIG_FIREWIRE_OHCI_DEBUG

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static int param_debug;
module_param_named(debug, param_debug, int, 0644);
MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
	", AT/AR events = "	__stringify(OHCI_PARAM_DEBUG_AT_AR)
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	", self-IDs = "		__stringify(OHCI_PARAM_DEBUG_SELFIDS)
	", IRQs = "		__stringify(OHCI_PARAM_DEBUG_IRQS)
	", busReset events = "	__stringify(OHCI_PARAM_DEBUG_BUSRESETS)
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	", or a combination, or all = -1)");

static void log_irqs(u32 evt)
{
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	if (likely(!(param_debug &
			(OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
		return;

	if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
	    !(evt & OHCI1394_busReset))
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		return;

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	fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
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	    evt & OHCI1394_selfIDComplete	? " selfID"		: "",
	    evt & OHCI1394_RQPkt		? " AR_req"		: "",
	    evt & OHCI1394_RSPkt		? " AR_resp"		: "",
	    evt & OHCI1394_reqTxComplete	? " AT_req"		: "",
	    evt & OHCI1394_respTxComplete	? " AT_resp"		: "",
	    evt & OHCI1394_isochRx		? " IR"			: "",
	    evt & OHCI1394_isochTx		? " IT"			: "",
	    evt & OHCI1394_postedWriteErr	? " postedWriteErr"	: "",
	    evt & OHCI1394_cycleTooLong		? " cycleTooLong"	: "",
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	    evt & OHCI1394_cycle64Seconds	? " cycle64Seconds"	: "",
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	    evt & OHCI1394_cycleInconsistent	? " cycleInconsistent"	: "",
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	    evt & OHCI1394_regAccessFail	? " regAccessFail"	: "",
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	    evt & OHCI1394_unrecoverableError	? " unrecoverableError"	: "",
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	    evt & OHCI1394_busReset		? " busReset"		: "",
	    evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
		    OHCI1394_RSPkt | OHCI1394_reqTxComplete |
		    OHCI1394_respTxComplete | OHCI1394_isochRx |
		    OHCI1394_isochTx | OHCI1394_postedWriteErr |
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		    OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
		    OHCI1394_cycleInconsistent |
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		    OHCI1394_regAccessFail | OHCI1394_busReset)
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						? " ?"			: "");
}

static const char *speed[] = {
	[0] = "S100", [1] = "S200", [2] = "S400",    [3] = "beta",
};
static const char *power[] = {
	[0] = "+0W",  [1] = "+15W", [2] = "+30W",    [3] = "+45W",
	[4] = "-3W",  [5] = " ?W",  [6] = "-3..-6W", [7] = "-3..-10W",
};
static const char port[] = { '.', '-', 'p', 'c', };

static char _p(u32 *s, int shift)
{
	return port[*s >> shift & 3];
}

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static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
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{
	if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
		return;

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	fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
		  self_id_count, generation, node_id);
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	for (; self_id_count--; ++s)
		if ((*s & 1 << 23) == 0)
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			fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
			    "%s gc=%d %s %s%s%s\n",
			    *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
			    speed[*s >> 14 & 3], *s >> 16 & 63,
			    power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
			    *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
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		else
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			fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
			    *s, *s >> 24 & 63,
			    _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
			    _p(s,  8), _p(s,  6), _p(s,  4), _p(s,  2));
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}

static const char *evts[] = {
	[0x00] = "evt_no_status",	[0x01] = "-reserved-",
	[0x02] = "evt_long_packet",	[0x03] = "evt_missing_ack",
	[0x04] = "evt_underrun",	[0x05] = "evt_overrun",
	[0x06] = "evt_descriptor_read",	[0x07] = "evt_data_read",
	[0x08] = "evt_data_write",	[0x09] = "evt_bus_reset",
	[0x0a] = "evt_timeout",		[0x0b] = "evt_tcode_err",
	[0x0c] = "-reserved-",		[0x0d] = "-reserved-",
	[0x0e] = "evt_unknown",		[0x0f] = "evt_flushed",
	[0x10] = "-reserved-",		[0x11] = "ack_complete",
	[0x12] = "ack_pending ",	[0x13] = "-reserved-",
	[0x14] = "ack_busy_X",		[0x15] = "ack_busy_A",
	[0x16] = "ack_busy_B",		[0x17] = "-reserved-",
	[0x18] = "-reserved-",		[0x19] = "-reserved-",
	[0x1a] = "-reserved-",		[0x1b] = "ack_tardy",
	[0x1c] = "-reserved-",		[0x1d] = "ack_data_error",
	[0x1e] = "ack_type_error",	[0x1f] = "-reserved-",
	[0x20] = "pending/cancelled",
};
static const char *tcodes[] = {
	[0x0] = "QW req",		[0x1] = "BW req",
	[0x2] = "W resp",		[0x3] = "-reserved-",
	[0x4] = "QR req",		[0x5] = "BR req",
	[0x6] = "QR resp",		[0x7] = "BR resp",
	[0x8] = "cycle start",		[0x9] = "Lk req",
	[0xa] = "async stream packet",	[0xb] = "Lk resp",
	[0xc] = "-reserved-",		[0xd] = "-reserved-",
	[0xe] = "link internal",	[0xf] = "-reserved-",
};

static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
{
	int tcode = header[0] >> 4 & 0xf;
	char specific[12];

	if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
		return;

	if (unlikely(evt >= ARRAY_SIZE(evts)))
			evt = 0x1f;

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	if (evt == OHCI1394_evt_bus_reset) {
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		fw_notify("A%c evt_bus_reset, generation %d\n",
		    dir, (header[2] >> 16) & 0xff);
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		return;
	}

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	switch (tcode) {
	case 0x0: case 0x6: case 0x8:
		snprintf(specific, sizeof(specific), " = %08x",
			 be32_to_cpu((__force __be32)header[3]));
		break;
	case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
		snprintf(specific, sizeof(specific), " %x,%x",
			 header[3] >> 16, header[3] & 0xffff);
		break;
	default:
		specific[0] = '\0';
	}

	switch (tcode) {
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	case 0xa:
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		fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
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		break;
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	case 0xe:
		fw_notify("A%c %s, PHY %08x %08x\n",
			  dir, evts[evt], header[1], header[2]);
		break;
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	case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
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		fw_notify("A%c spd %x tl %02x, "
		    "%04x -> %04x, %s, "
		    "%s, %04x%08x%s\n",
		    dir, speed, header[0] >> 10 & 0x3f,
		    header[1] >> 16, header[0] >> 16, evts[evt],
		    tcodes[tcode], header[1] & 0xffff, header[2], specific);
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		break;
	default:
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		fw_notify("A%c spd %x tl %02x, "
		    "%04x -> %04x, %s, "
		    "%s%s\n",
		    dir, speed, header[0] >> 10 & 0x3f,
		    header[1] >> 16, header[0] >> 16, evts[evt],
		    tcodes[tcode], specific);
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	}
}

#else

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#define param_debug 0
static inline void log_irqs(u32 evt) {}
static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
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#endif /* CONFIG_FIREWIRE_OHCI_DEBUG */

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static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
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{
	writel(data, ohci->registers + offset);
}

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static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
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{
	return readl(ohci->registers + offset);
}

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static inline void flush_writes(const struct fw_ohci *ohci)
526 527 528 529 530
{
	/* Do a dummy read to flush writes. */
	reg_read(ohci, OHCI1394_Version);
}

531 532 533 534 535 536
/*
 * Beware!  read_phy_reg(), write_phy_reg(), update_phy_reg(), and
 * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
 * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg()
 * directly.  Exceptions are intrinsically serialized contexts like pci_probe.
 */
537
static int read_phy_reg(struct fw_ohci *ohci, int addr)
538
{
539
	u32 val;
540
	int i;
541 542

	reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
543
	for (i = 0; i < 3 + 100; i++) {
544
		val = reg_read(ohci, OHCI1394_PhyControl);
545 546 547
		if (!~val)
			return -ENODEV; /* Card was ejected. */

548 549 550
		if (val & OHCI1394_PhyControl_ReadDone)
			return OHCI1394_PhyControl_ReadData(val);

551 552 553 554 555 556
		/*
		 * Try a few times without waiting.  Sleeping is necessary
		 * only when the link/PHY interface is busy.
		 */
		if (i >= 3)
			msleep(1);
557
	}
558
	fw_error("failed to read phy reg\n");
559

560 561
	return -EBUSY;
}
562

563 564 565
static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
{
	int i;
566 567

	reg_write(ohci, OHCI1394_PhyControl,
568
		  OHCI1394_PhyControl_Write(addr, val));
569
	for (i = 0; i < 3 + 100; i++) {
570
		val = reg_read(ohci, OHCI1394_PhyControl);
571 572 573
		if (!~val)
			return -ENODEV; /* Card was ejected. */

574 575
		if (!(val & OHCI1394_PhyControl_WritePending))
			return 0;
576

577 578
		if (i >= 3)
			msleep(1);
579 580 581 582
	}
	fw_error("failed to write phy reg\n");

	return -EBUSY;
583 584
}

585 586
static int update_phy_reg(struct fw_ohci *ohci, int addr,
			  int clear_bits, int set_bits)
587
{
588
	int ret = read_phy_reg(ohci, addr);
589 590
	if (ret < 0)
		return ret;
591

592 593 594 595 596 597 598
	/*
	 * The interrupt status bits are cleared by writing a one bit.
	 * Avoid clearing them unless explicitly requested in set_bits.
	 */
	if (addr == 5)
		clear_bits |= PHY_INT_STATUS_BITS;

599
	return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
600 601
}

602
static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
603
{
604
	int ret;
605

606
	ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
607 608
	if (ret < 0)
		return ret;
609

610
	return read_phy_reg(ohci, addr);
611 612
}

613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635
static int ohci_read_phy_reg(struct fw_card *card, int addr)
{
	struct fw_ohci *ohci = fw_ohci(card);
	int ret;

	mutex_lock(&ohci->phy_reg_mutex);
	ret = read_phy_reg(ohci, addr);
	mutex_unlock(&ohci->phy_reg_mutex);

	return ret;
}

static int ohci_update_phy_reg(struct fw_card *card, int addr,
			       int clear_bits, int set_bits)
{
	struct fw_ohci *ohci = fw_ohci(card);
	int ret;

	mutex_lock(&ohci->phy_reg_mutex);
	ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
	mutex_unlock(&ohci->phy_reg_mutex);

	return ret;
636 637
}

638 639 640 641 642 643
static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
{
	return page_private(ctx->pages[i]);
}

static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
644
{
645
	struct descriptor *d;
646

647 648 649 650
	d = &ctx->descriptors[index];
	d->branch_address  &= cpu_to_le32(~0xf);
	d->res_count       =  cpu_to_le16(PAGE_SIZE);
	d->transfer_status =  0;
651

652
	wmb(); /* finish init of new descriptors before branch_address update */
653 654 655 656
	d = &ctx->descriptors[ctx->last_buffer_index];
	d->branch_address  |= cpu_to_le32(1);

	ctx->last_buffer_index = index;
657

658
	reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
659 660
}

661
static void ar_context_release(struct ar_context *ctx)
662
{
663
	unsigned int i;
664

665 666
	if (ctx->buffer)
		vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES);
667

668 669 670 671 672 673 674
	for (i = 0; i < AR_BUFFERS; i++)
		if (ctx->pages[i]) {
			dma_unmap_page(ctx->ohci->card.device,
				       ar_buffer_bus(ctx, i),
				       PAGE_SIZE, DMA_FROM_DEVICE);
			__free_page(ctx->pages[i]);
		}
675 676
}

677
static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
678
{
679 680 681
	if (reg_read(ctx->ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
		reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
		flush_writes(ctx->ohci);
682

683
		fw_error("AR error: %s; DMA stopped\n", error_msg);
684
	}
685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780
	/* FIXME: restart? */
}

static inline unsigned int ar_next_buffer_index(unsigned int index)
{
	return (index + 1) % AR_BUFFERS;
}

static inline unsigned int ar_prev_buffer_index(unsigned int index)
{
	return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
}

static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
{
	return ar_next_buffer_index(ctx->last_buffer_index);
}

/*
 * We search for the buffer that contains the last AR packet DMA data written
 * by the controller.
 */
static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
						 unsigned int *buffer_offset)
{
	unsigned int i, next_i, last = ctx->last_buffer_index;
	__le16 res_count, next_res_count;

	i = ar_first_buffer_index(ctx);
	res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);

	/* A buffer that is not yet completely filled must be the last one. */
	while (i != last && res_count == 0) {

		/* Peek at the next descriptor. */
		next_i = ar_next_buffer_index(i);
		rmb(); /* read descriptors in order */
		next_res_count = ACCESS_ONCE(
				ctx->descriptors[next_i].res_count);
		/*
		 * If the next descriptor is still empty, we must stop at this
		 * descriptor.
		 */
		if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
			/*
			 * The exception is when the DMA data for one packet is
			 * split over three buffers; in this case, the middle
			 * buffer's descriptor might be never updated by the
			 * controller and look still empty, and we have to peek
			 * at the third one.
			 */
			if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
				next_i = ar_next_buffer_index(next_i);
				rmb();
				next_res_count = ACCESS_ONCE(
					ctx->descriptors[next_i].res_count);
				if (next_res_count != cpu_to_le16(PAGE_SIZE))
					goto next_buffer_is_active;
			}

			break;
		}

next_buffer_is_active:
		i = next_i;
		res_count = next_res_count;
	}

	rmb(); /* read res_count before the DMA data */

	*buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
	if (*buffer_offset > PAGE_SIZE) {
		*buffer_offset = 0;
		ar_context_abort(ctx, "corrupted descriptor");
	}

	return i;
}

static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
				    unsigned int end_buffer_index,
				    unsigned int end_buffer_offset)
{
	unsigned int i;

	i = ar_first_buffer_index(ctx);
	while (i != end_buffer_index) {
		dma_sync_single_for_cpu(ctx->ohci->card.device,
					ar_buffer_bus(ctx, i),
					PAGE_SIZE, DMA_FROM_DEVICE);
		i = ar_next_buffer_index(i);
	}
	if (end_buffer_offset > 0)
		dma_sync_single_for_cpu(ctx->ohci->card.device,
					ar_buffer_bus(ctx, i),
					end_buffer_offset, DMA_FROM_DEVICE);
781 782
}

783 784
#if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
#define cond_le32_to_cpu(v) \
785
	(ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
786 787 788 789
#else
#define cond_le32_to_cpu(v) le32_to_cpu(v)
#endif

790
static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
791 792
{
	struct fw_ohci *ohci = ctx->ohci;
793 794
	struct fw_packet p;
	u32 status, length, tcode;
795
	int evt;
796

797 798 799
	p.header[0] = cond_le32_to_cpu(buffer[0]);
	p.header[1] = cond_le32_to_cpu(buffer[1]);
	p.header[2] = cond_le32_to_cpu(buffer[2]);
800 801 802 803 804

	tcode = (p.header[0] >> 4) & 0x0f;
	switch (tcode) {
	case TCODE_WRITE_QUADLET_REQUEST:
	case TCODE_READ_QUADLET_RESPONSE:
805
		p.header[3] = (__force __u32) buffer[3];
806
		p.header_length = 16;
807
		p.payload_length = 0;
808 809 810
		break;

	case TCODE_READ_BLOCK_REQUEST :
811
		p.header[3] = cond_le32_to_cpu(buffer[3]);
812 813 814 815 816
		p.header_length = 16;
		p.payload_length = 0;
		break;

	case TCODE_WRITE_BLOCK_REQUEST:
817 818 819
	case TCODE_READ_BLOCK_RESPONSE:
	case TCODE_LOCK_REQUEST:
	case TCODE_LOCK_RESPONSE:
820
		p.header[3] = cond_le32_to_cpu(buffer[3]);
821
		p.header_length = 16;
822
		p.payload_length = p.header[3] >> 16;
823 824 825 826
		if (p.payload_length > MAX_ASYNC_PAYLOAD) {
			ar_context_abort(ctx, "invalid packet length");
			return NULL;
		}
827 828 829 830
		break;

	case TCODE_WRITE_RESPONSE:
	case TCODE_READ_QUADLET_REQUEST:
831
	case OHCI_TCODE_PHY_PACKET:
832
		p.header_length = 12;
833
		p.payload_length = 0;
834
		break;
835 836

	default:
837 838
		ar_context_abort(ctx, "invalid tcode");
		return NULL;
839
	}
840

841 842 843 844
	p.payload = (void *) buffer + p.header_length;

	/* FIXME: What to do about evt_* errors? */
	length = (p.header_length + p.payload_length + 3) / 4;
845
	status = cond_le32_to_cpu(buffer[length]);
846
	evt    = (status >> 16) & 0x1f;
847

848
	p.ack        = evt - 16;
849 850 851
	p.speed      = (status >> 21) & 0x7;
	p.timestamp  = status & 0xffff;
	p.generation = ohci->request_generation;
852

853
	log_ar_at_event('R', p.speed, p.header, evt);
854

855
	/*
856 857 858 859 860 861 862 863 864
	 * Several controllers, notably from NEC and VIA, forget to
	 * write ack_complete status at PHY packet reception.
	 */
	if (evt == OHCI1394_evt_no_status &&
	    (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
		p.ack = ACK_COMPLETE;

	/*
	 * The OHCI bus reset handler synthesizes a PHY packet with
865 866 867 868 869
	 * the new generation number when a bus reset happens (see
	 * section 8.4.2.3).  This helps us determine when a request
	 * was received and make sure we send the response in the same
	 * generation.  We only need this for requests; for responses
	 * we use the unique tlabel for finding the matching
870
	 * request.
871 872 873
	 *
	 * Alas some chips sometimes emit bus reset packets with a
	 * wrong generation.  We set the correct generation for these
874
	 * at a slightly incorrect time (in bus_reset_work).
875
	 */
876
	if (evt == OHCI1394_evt_bus_reset) {
877
		if (!(ohci->quirks & QUIRK_RESET_PACKET))
878 879
			ohci->request_generation = (p.header[2] >> 16) & 0xff;
	} else if (ctx == &ohci->ar_request_ctx) {
880
		fw_core_handle_request(&ohci->card, &p);
881
	} else {
882
		fw_core_handle_response(&ohci->card, &p);
883
	}
884

885 886
	return buffer + length + 1;
}
887

888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915
static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
{
	void *next;

	while (p < end) {
		next = handle_ar_packet(ctx, p);
		if (!next)
			return p;
		p = next;
	}

	return p;
}

static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
{
	unsigned int i;

	i = ar_first_buffer_index(ctx);
	while (i != end_buffer) {
		dma_sync_single_for_device(ctx->ohci->card.device,
					   ar_buffer_bus(ctx, i),
					   PAGE_SIZE, DMA_FROM_DEVICE);
		ar_context_link_page(ctx, i);
		i = ar_next_buffer_index(i);
	}
}

916 917 918
static void ar_context_tasklet(unsigned long data)
{
	struct ar_context *ctx = (struct ar_context *)data;
919 920
	unsigned int end_buffer_index, end_buffer_offset;
	void *p, *end;
921

922 923 924
	p = ctx->pointer;
	if (!p)
		return;
925

926 927 928 929
	end_buffer_index = ar_search_last_active_buffer(ctx,
							&end_buffer_offset);
	ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
	end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
930

931
	if (end_buffer_index < ar_first_buffer_index(ctx)) {
932
		/*
933 934 935 936
		 * The filled part of the overall buffer wraps around; handle
		 * all packets up to the buffer end here.  If the last packet
		 * wraps around, its tail will be visible after the buffer end
		 * because the buffer start pages are mapped there again.
937
		 */
938 939 940 941 942 943 944
		void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
		p = handle_ar_packets(ctx, p, buffer_end);
		if (p < buffer_end)
			goto error;
		/* adjust p to point back into the actual buffer */
		p -= AR_BUFFERS * PAGE_SIZE;
	}
945

946 947 948 949 950 951
	p = handle_ar_packets(ctx, p, end);
	if (p != end) {
		if (p > end)
			ar_context_abort(ctx, "inconsistent descriptor");
		goto error;
	}
952

953 954
	ctx->pointer = p;
	ar_recycle_buffers(ctx, end_buffer_index);
955

956
	return;
957

958 959
error:
	ctx->pointer = NULL;
960 961
}

962 963
static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
			   unsigned int descriptors_offset, u32 regs)
964
{
965 966 967 968
	unsigned int i;
	dma_addr_t dma_addr;
	struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
	struct descriptor *d;
969

970 971
	ctx->regs        = regs;
	ctx->ohci        = ohci;
972 973
	tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);

974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992
	for (i = 0; i < AR_BUFFERS; i++) {
		ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
		if (!ctx->pages[i])
			goto out_of_memory;
		dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
					0, PAGE_SIZE, DMA_FROM_DEVICE);
		if (dma_mapping_error(ohci->card.device, dma_addr)) {
			__free_page(ctx->pages[i]);
			ctx->pages[i] = NULL;
			goto out_of_memory;
		}
		set_page_private(ctx->pages[i], dma_addr);
	}

	for (i = 0; i < AR_BUFFERS; i++)
		pages[i]              = ctx->pages[i];
	for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
		pages[AR_BUFFERS + i] = ctx->pages[i];
	ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES,
993
				 -1, PAGE_KERNEL);
994 995 996
	if (!ctx->buffer)
		goto out_of_memory;

997 998
	ctx->descriptors     = ohci->misc_buffer     + descriptors_offset;
	ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009

	for (i = 0; i < AR_BUFFERS; i++) {
		d = &ctx->descriptors[i];
		d->req_count      = cpu_to_le16(PAGE_SIZE);
		d->control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
						DESCRIPTOR_STATUS |
						DESCRIPTOR_BRANCH_ALWAYS);
		d->data_address   = cpu_to_le32(ar_buffer_bus(ctx, i));
		d->branch_address = cpu_to_le32(ctx->descriptors_bus +
			ar_next_buffer_index(i) * sizeof(struct descriptor));
	}
1010

1011
	return 0;
1012 1013 1014 1015 1016

out_of_memory:
	ar_context_release(ctx);

	return -ENOMEM;
1017 1018 1019 1020
}

static void ar_context_run(struct ar_context *ctx)
{
1021 1022 1023 1024
	unsigned int i;

	for (i = 0; i < AR_BUFFERS; i++)
		ar_context_link_page(ctx, i);
1025

1026
	ctx->pointer = ctx->buffer;
1027

1028
	reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
1029
	reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
1030
}
S
Stefan Richter 已提交
1031

1032
static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
1033
{
1034
	__le16 branch;
1035

1036
	branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
1037 1038

	/* figure out which descriptor the branch address goes in */
1039
	if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
1040 1041 1042 1043 1044
		return d;
	else
		return d + z - 1;
}

1045 1046 1047 1048 1049 1050
static void context_tasklet(unsigned long data)
{
	struct context *ctx = (struct context *) data;
	struct descriptor *d, *last;
	u32 address;
	int z;
1051
	struct descriptor_buffer *desc;
1052

1053 1054 1055
	desc = list_entry(ctx->buffer_list.next,
			struct descriptor_buffer, list);
	last = ctx->last;
1056
	while (last->branch_address != 0) {
1057
		struct descriptor_buffer *old_desc = desc;
1058 1059
		address = le32_to_cpu(last->branch_address);
		z = address & 0xf;
1060
		address &= ~0xf;
1061
		ctx->current_bus = address;
1062 1063 1064 1065 1066 1067 1068 1069

		/* If the branch address points to a buffer outside of the
		 * current buffer, advance to the next buffer. */
		if (address < desc->buffer_bus ||
				address >= desc->buffer_bus + desc->used)
			desc = list_entry(desc->list.next,
					struct descriptor_buffer, list);
		d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
1070
		last = find_branch_descriptor(d, z);
1071 1072 1073 1074

		if (!ctx->callback(ctx, d, last))
			break;

1075 1076 1077 1078 1079 1080 1081 1082 1083 1084
		if (old_desc != desc) {
			/* If we've advanced to the next buffer, move the
			 * previous buffer to the free list. */
			unsigned long flags;
			old_desc->used = 0;
			spin_lock_irqsave(&ctx->ohci->lock, flags);
			list_move_tail(&old_desc->list, &ctx->buffer_list);
			spin_unlock_irqrestore(&ctx->ohci->lock, flags);
		}
		ctx->last = last;
1085 1086 1087
	}
}

1088 1089 1090 1091
/*
 * Allocate a new buffer and add it to the list of free buffers for this
 * context.  Must be called with ohci->lock held.
 */
1092
static int context_add_buffer(struct context *ctx)
1093 1094
{
	struct descriptor_buffer *desc;
1095
	dma_addr_t uninitialized_var(bus_addr);
1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120
	int offset;

	/*
	 * 16MB of descriptors should be far more than enough for any DMA
	 * program.  This will catch run-away userspace or DoS attacks.
	 */
	if (ctx->total_allocation >= 16*1024*1024)
		return -ENOMEM;

	desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
			&bus_addr, GFP_ATOMIC);
	if (!desc)
		return -ENOMEM;

	offset = (void *)&desc->buffer - (void *)desc;
	desc->buffer_size = PAGE_SIZE - offset;
	desc->buffer_bus = bus_addr + offset;
	desc->used = 0;

	list_add_tail(&desc->list, &ctx->buffer_list);
	ctx->total_allocation += PAGE_SIZE;

	return 0;
}

1121 1122
static int context_init(struct context *ctx, struct fw_ohci *ohci,
			u32 regs, descriptor_callback_t callback)
1123 1124 1125
{
	ctx->ohci = ohci;
	ctx->regs = regs;
1126 1127 1128 1129
	ctx->total_allocation = 0;

	INIT_LIST_HEAD(&ctx->buffer_list);
	if (context_add_buffer(ctx) < 0)
1130 1131
		return -ENOMEM;

1132 1133 1134
	ctx->buffer_tail = list_entry(ctx->buffer_list.next,
			struct descriptor_buffer, list);

1135 1136 1137
	tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
	ctx->callback = callback;

1138 1139
	/*
	 * We put a dummy descriptor in the buffer that has a NULL
1140
	 * branch address and looks like it's been sent.  That way we
1141
	 * have a descriptor to append DMA programs to.
1142
	 */
1143 1144 1145 1146 1147 1148
	memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
	ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
	ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
	ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
	ctx->last = ctx->buffer_tail->buffer;
	ctx->prev = ctx->buffer_tail->buffer;
1149 1150 1151 1152

	return 0;
}

1153
static void context_release(struct context *ctx)
1154 1155
{
	struct fw_card *card = &ctx->ohci->card;
1156
	struct descriptor_buffer *desc, *tmp;
1157

1158 1159 1160 1161
	list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
		dma_free_coherent(card->device, PAGE_SIZE, desc,
			desc->buffer_bus -
			((void *)&desc->buffer - (void *)desc));
1162 1163
}

1164
/* Must be called with ohci->lock held */
1165 1166
static struct descriptor *context_get_descriptors(struct context *ctx,
						  int z, dma_addr_t *d_bus)
1167
{
1168 1169 1170 1171 1172 1173 1174 1175 1176
	struct descriptor *d = NULL;
	struct descriptor_buffer *desc = ctx->buffer_tail;

	if (z * sizeof(*d) > desc->buffer_size)
		return NULL;

	if (z * sizeof(*d) > desc->buffer_size - desc->used) {
		/* No room for the descriptor in this buffer, so advance to the
		 * next one. */
1177

1178 1179 1180 1181 1182 1183 1184 1185 1186 1187
		if (desc->list.next == &ctx->buffer_list) {
			/* If there is no free buffer next in the list,
			 * allocate one. */
			if (context_add_buffer(ctx) < 0)
				return NULL;
		}
		desc = list_entry(desc->list.next,
				struct descriptor_buffer, list);
		ctx->buffer_tail = desc;
	}
1188

1189
	d = desc->buffer + desc->used / sizeof(*d);
1190
	memset(d, 0, z * sizeof(*d));
1191
	*d_bus = desc->buffer_bus + desc->used;
1192 1193 1194 1195

	return d;
}

1196
static void context_run(struct context *ctx, u32 extra)
1197 1198 1199
{
	struct fw_ohci *ohci = ctx->ohci;

1200
	reg_write(ohci, COMMAND_PTR(ctx->regs),
1201
		  le32_to_cpu(ctx->last->branch_address));
1202 1203
	reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
	reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1204
	ctx->running = true;
1205 1206 1207 1208 1209 1210 1211
	flush_writes(ohci);
}

static void context_append(struct context *ctx,
			   struct descriptor *d, int z, int extra)
{
	dma_addr_t d_bus;
1212
	struct descriptor_buffer *desc = ctx->buffer_tail;
1213

1214
	d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1215

1216
	desc->used += (z + extra) * sizeof(*d);
1217 1218

	wmb(); /* finish init of new descriptors before branch_address update */
1219 1220
	ctx->prev->branch_address = cpu_to_le32(d_bus | z);
	ctx->prev = find_branch_descriptor(d, z);
1221 1222 1223 1224 1225
}

static void context_stop(struct context *ctx)
{
	u32 reg;
1226
	int i;
1227

1228
	reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1229
	ctx->running = false;
1230

1231
	for (i = 0; i < 1000; i++) {
1232
		reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1233
		if ((reg & CONTEXT_ACTIVE) == 0)
1234
			return;
1235

1236 1237
		if (i)
			udelay(10);
1238
	}
1239
	fw_error("Error: DMA context still active (0x%08x)\n", reg);
1240
}
1241

1242
struct driver_data {
1243
	u8 inline_data[8];
1244 1245
	struct fw_packet *packet;
};
1246

1247 1248
/*
 * This function apppends a packet to the DMA queue for transmission.
1249
 * Must always be called with the ochi->lock held to ensure proper
1250 1251
 * generation handling and locking around packet queue manipulation.
 */
1252 1253
static int at_context_queue_packet(struct context *ctx,
				   struct fw_packet *packet)
1254 1255
{
	struct fw_ohci *ohci = ctx->ohci;
1256
	dma_addr_t d_bus, uninitialized_var(payload_bus);
1257 1258 1259
	struct driver_data *driver_data;
	struct descriptor *d, *last;
	__le32 *header;
1260 1261
	int z, tcode;

1262 1263 1264 1265
	d = context_get_descriptors(ctx, 4, &d_bus);
	if (d == NULL) {
		packet->ack = RCODE_SEND_ERROR;
		return -1;
1266 1267
	}

1268
	d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1269 1270
	d[0].res_count = cpu_to_le16(packet->timestamp);

1271 1272
	/*
	 * The DMA format for asyncronous link packets is different
1273
	 * from the IEEE1394 layout, so shift the fields around
1274
	 * accordingly.
1275
	 */
1276

1277
	tcode = (packet->header[0] >> 4) & 0x0f;
1278
	header = (__le32 *) &d[1];
1279 1280 1281 1282 1283 1284 1285 1286 1287 1288
	switch (tcode) {
	case TCODE_WRITE_QUADLET_REQUEST:
	case TCODE_WRITE_BLOCK_REQUEST:
	case TCODE_WRITE_RESPONSE:
	case TCODE_READ_QUADLET_REQUEST:
	case TCODE_READ_BLOCK_REQUEST:
	case TCODE_READ_QUADLET_RESPONSE:
	case TCODE_READ_BLOCK_RESPONSE:
	case TCODE_LOCK_REQUEST:
	case TCODE_LOCK_RESPONSE:
1289 1290 1291 1292 1293
		header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
					(packet->speed << 16));
		header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
					(packet->header[0] & 0xffff0000));
		header[2] = cpu_to_le32(packet->header[2]);
1294 1295

		if (TCODE_IS_BLOCK_PACKET(tcode))
1296
			header[3] = cpu_to_le32(packet->header[3]);
1297
		else
1298 1299 1300
			header[3] = (__force __le32) packet->header[3];

		d[0].req_count = cpu_to_le16(packet->header_length);
1301 1302
		break;

1303
	case TCODE_LINK_INTERNAL:
1304 1305
		header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
					(packet->speed << 16));
1306 1307
		header[1] = cpu_to_le32(packet->header[1]);
		header[2] = cpu_to_le32(packet->header[2]);
1308
		d[0].req_count = cpu_to_le16(12);
S
Stefan Richter 已提交
1309

1310
		if (is_ping_packet(&packet->header[1]))
S
Stefan Richter 已提交
1311
			d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1312 1313
		break;

1314
	case TCODE_STREAM_DATA:
1315 1316 1317 1318 1319 1320 1321 1322 1323 1324
		header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
					(packet->speed << 16));
		header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
		d[0].req_count = cpu_to_le16(8);
		break;

	default:
		/* BUG(); */
		packet->ack = RCODE_SEND_ERROR;
		return -1;
1325 1326
	}

1327
	BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
1328 1329
	driver_data = (struct driver_data *) &d[3];
	driver_data->packet = packet;
1330
	packet->driver_data = driver_data;
1331

1332
	if (packet->payload_length > 0) {
1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347
		if (packet->payload_length > sizeof(driver_data->inline_data)) {
			payload_bus = dma_map_single(ohci->card.device,
						     packet->payload,
						     packet->payload_length,
						     DMA_TO_DEVICE);
			if (dma_mapping_error(ohci->card.device, payload_bus)) {
				packet->ack = RCODE_SEND_ERROR;
				return -1;
			}
			packet->payload_bus	= payload_bus;
			packet->payload_mapped	= true;
		} else {
			memcpy(driver_data->inline_data, packet->payload,
			       packet->payload_length);
			payload_bus = d_bus + 3 * sizeof(*d);
1348 1349 1350 1351 1352 1353
		}

		d[2].req_count    = cpu_to_le16(packet->payload_length);
		d[2].data_address = cpu_to_le32(payload_bus);
		last = &d[2];
		z = 3;
1354
	} else {
1355 1356
		last = &d[0];
		z = 2;
1357 1358
	}

1359 1360 1361
	last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
				     DESCRIPTOR_IRQ_ALWAYS |
				     DESCRIPTOR_BRANCH_ALWAYS);
1362

1363 1364
	/* FIXME: Document how the locking works. */
	if (ohci->generation != packet->generation) {
1365
		if (packet->payload_mapped)
1366 1367
			dma_unmap_single(ohci->card.device, payload_bus,
					 packet->payload_length, DMA_TO_DEVICE);
1368 1369 1370 1371 1372
		packet->ack = RCODE_GENERATION;
		return -1;
	}

	context_append(ctx, d, z, 4 - z);
1373

1374
	if (ctx->running)
1375
		reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1376
	else
1377 1378 1379
		context_run(ctx, 0);

	return 0;
1380 1381
}

1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392
static void at_context_flush(struct context *ctx)
{
	tasklet_disable(&ctx->tasklet);

	ctx->flushing = true;
	context_tasklet((unsigned long)ctx);
	ctx->flushing = false;

	tasklet_enable(&ctx->tasklet);
}

1393 1394 1395
static int handle_at_packet(struct context *context,
			    struct descriptor *d,
			    struct descriptor *last)
1396
{
1397
	struct driver_data *driver_data;
1398
	struct fw_packet *packet;
1399
	struct fw_ohci *ohci = context->ohci;
1400 1401
	int evt;

1402
	if (last->transfer_status == 0 && !context->flushing)
1403 1404
		/* This descriptor isn't done yet, stop iteration. */
		return 0;
1405

1406 1407 1408 1409 1410
	driver_data = (struct driver_data *) &d[3];
	packet = driver_data->packet;
	if (packet == NULL)
		/* This packet was cancelled, just continue. */
		return 1;
1411

1412
	if (packet->payload_mapped)
1413
		dma_unmap_single(ohci->card.device, packet->payload_bus,
1414 1415
				 packet->payload_length, DMA_TO_DEVICE);

1416 1417
	evt = le16_to_cpu(last->transfer_status) & 0x1f;
	packet->timestamp = le16_to_cpu(last->res_count);
1418

1419 1420
	log_ar_at_event('T', packet->speed, packet->header, evt);

1421 1422 1423 1424 1425
	switch (evt) {
	case OHCI1394_evt_timeout:
		/* Async response transmit timed out. */
		packet->ack = RCODE_CANCELLED;
		break;
1426

1427
	case OHCI1394_evt_flushed:
1428 1429 1430 1431
		/*
		 * The packet was flushed should give same error as
		 * when we try to use a stale generation count.
		 */
1432 1433
		packet->ack = RCODE_GENERATION;
		break;
1434

1435
	case OHCI1394_evt_missing_ack:
1436 1437 1438 1439 1440 1441 1442 1443 1444
		if (context->flushing)
			packet->ack = RCODE_GENERATION;
		else {
			/*
			 * Using a valid (current) generation count, but the
			 * node is not on the bus or not sending acks.
			 */
			packet->ack = RCODE_NO_ACK;
		}
1445
		break;
1446

1447 1448 1449 1450 1451 1452 1453 1454 1455
	case ACK_COMPLETE + 0x10:
	case ACK_PENDING + 0x10:
	case ACK_BUSY_X + 0x10:
	case ACK_BUSY_A + 0x10:
	case ACK_BUSY_B + 0x10:
	case ACK_DATA_ERROR + 0x10:
	case ACK_TYPE_ERROR + 0x10:
		packet->ack = evt - 0x10;
		break;
1456

1457 1458 1459 1460 1461 1462 1463
	case OHCI1394_evt_no_status:
		if (context->flushing) {
			packet->ack = RCODE_GENERATION;
			break;
		}
		/* fall through */

1464 1465 1466 1467
	default:
		packet->ack = RCODE_SEND_ERROR;
		break;
	}
1468

1469
	packet->callback(packet, &ohci->card, packet->ack);
1470

1471
	return 1;
1472 1473
}

1474 1475 1476 1477 1478
#define HEADER_GET_DESTINATION(q)	(((q) >> 16) & 0xffff)
#define HEADER_GET_TCODE(q)		(((q) >> 4) & 0x0f)
#define HEADER_GET_OFFSET_HIGH(q)	(((q) >> 0) & 0xffff)
#define HEADER_GET_DATA_LENGTH(q)	(((q) >> 16) & 0xffff)
#define HEADER_GET_EXTENDED_TCODE(q)	(((q) >> 0) & 0xffff)
1479

1480 1481
static void handle_local_rom(struct fw_ohci *ohci,
			     struct fw_packet *packet, u32 csr)
1482 1483 1484 1485
{
	struct fw_packet response;
	int tcode, length, i;

1486
	tcode = HEADER_GET_TCODE(packet->header[0]);
1487
	if (TCODE_IS_BLOCK_PACKET(tcode))
1488
		length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506
	else
		length = 4;

	i = csr - CSR_CONFIG_ROM;
	if (i + length > CONFIG_ROM_SIZE) {
		fw_fill_response(&response, packet->header,
				 RCODE_ADDRESS_ERROR, NULL, 0);
	} else if (!TCODE_IS_READ_REQUEST(tcode)) {
		fw_fill_response(&response, packet->header,
				 RCODE_TYPE_ERROR, NULL, 0);
	} else {
		fw_fill_response(&response, packet->header, RCODE_COMPLETE,
				 (void *) ohci->config_rom + i, length);
	}

	fw_core_handle_response(&ohci->card, &response);
}

1507 1508
static void handle_local_lock(struct fw_ohci *ohci,
			      struct fw_packet *packet, u32 csr)
1509 1510
{
	struct fw_packet response;
1511
	int tcode, length, ext_tcode, sel, try;
1512 1513 1514
	__be32 *payload, lock_old;
	u32 lock_arg, lock_data;

1515 1516
	tcode = HEADER_GET_TCODE(packet->header[0]);
	length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1517
	payload = packet->payload;
1518
	ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537

	if (tcode == TCODE_LOCK_REQUEST &&
	    ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
		lock_arg = be32_to_cpu(payload[0]);
		lock_data = be32_to_cpu(payload[1]);
	} else if (tcode == TCODE_READ_QUADLET_REQUEST) {
		lock_arg = 0;
		lock_data = 0;
	} else {
		fw_fill_response(&response, packet->header,
				 RCODE_TYPE_ERROR, NULL, 0);
		goto out;
	}

	sel = (csr - CSR_BUS_MANAGER_ID) / 4;
	reg_write(ohci, OHCI1394_CSRData, lock_data);
	reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
	reg_write(ohci, OHCI1394_CSRControl, sel);

1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549
	for (try = 0; try < 20; try++)
		if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
			lock_old = cpu_to_be32(reg_read(ohci,
							OHCI1394_CSRData));
			fw_fill_response(&response, packet->header,
					 RCODE_COMPLETE,
					 &lock_old, sizeof(lock_old));
			goto out;
		}

	fw_error("swap not done (CSR lock timeout)\n");
	fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1550 1551 1552 1553 1554

 out:
	fw_core_handle_response(&ohci->card, &response);
}

1555
static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1556
{
1557
	u64 offset, csr;
1558

1559 1560 1561 1562
	if (ctx == &ctx->ohci->at_request_ctx) {
		packet->ack = ACK_PENDING;
		packet->callback(packet, &ctx->ohci->card, packet->ack);
	}
1563 1564 1565

	offset =
		((unsigned long long)
1566
		 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586
		packet->header[2];
	csr = offset - CSR_REGISTER_BASE;

	/* Handle config rom reads. */
	if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
		handle_local_rom(ctx->ohci, packet, csr);
	else switch (csr) {
	case CSR_BUS_MANAGER_ID:
	case CSR_BANDWIDTH_AVAILABLE:
	case CSR_CHANNELS_AVAILABLE_HI:
	case CSR_CHANNELS_AVAILABLE_LO:
		handle_local_lock(ctx->ohci, packet, csr);
		break;
	default:
		if (ctx == &ctx->ohci->at_request_ctx)
			fw_core_handle_request(&ctx->ohci->card, packet);
		else
			fw_core_handle_response(&ctx->ohci->card, packet);
		break;
	}
1587 1588 1589 1590 1591

	if (ctx == &ctx->ohci->at_response_ctx) {
		packet->ack = ACK_COMPLETE;
		packet->callback(packet, &ctx->ohci->card, packet->ack);
	}
1592
}
1593

1594
static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1595 1596
{
	unsigned long flags;
1597
	int ret;
1598 1599 1600

	spin_lock_irqsave(&ctx->ohci->lock, flags);

1601
	if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1602
	    ctx->ohci->generation == packet->generation) {
1603 1604 1605
		spin_unlock_irqrestore(&ctx->ohci->lock, flags);
		handle_local_request(ctx, packet);
		return;
1606
	}
1607

1608
	ret = at_context_queue_packet(ctx, packet);
1609 1610
	spin_unlock_irqrestore(&ctx->ohci->lock, flags);

1611
	if (ret < 0)
1612
		packet->callback(packet, &ctx->ohci->card, packet->ack);
1613

1614 1615
}

1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656
static void detect_dead_context(struct fw_ohci *ohci,
				const char *name, unsigned int regs)
{
	u32 ctl;

	ctl = reg_read(ohci, CONTROL_SET(regs));
	if (ctl & CONTEXT_DEAD) {
#ifdef CONFIG_FIREWIRE_OHCI_DEBUG
		fw_error("DMA context %s has stopped, error code: %s\n",
			 name, evts[ctl & 0x1f]);
#else
		fw_error("DMA context %s has stopped, error code: %#x\n",
			 name, ctl & 0x1f);
#endif
	}
}

static void handle_dead_contexts(struct fw_ohci *ohci)
{
	unsigned int i;
	char name[8];

	detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
	detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
	detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
	detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
	for (i = 0; i < 32; ++i) {
		if (!(ohci->it_context_support & (1 << i)))
			continue;
		sprintf(name, "IT%u", i);
		detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
	}
	for (i = 0; i < 32; ++i) {
		if (!(ohci->ir_context_support & (1 << i)))
			continue;
		sprintf(name, "IR%u", i);
		detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
	}
	/* TODO: maybe try to flush and restart the dead contexts */
}

1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728
static u32 cycle_timer_ticks(u32 cycle_timer)
{
	u32 ticks;

	ticks = cycle_timer & 0xfff;
	ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
	ticks += (3072 * 8000) * (cycle_timer >> 25);

	return ticks;
}

/*
 * Some controllers exhibit one or more of the following bugs when updating the
 * iso cycle timer register:
 *  - When the lowest six bits are wrapping around to zero, a read that happens
 *    at the same time will return garbage in the lowest ten bits.
 *  - When the cycleOffset field wraps around to zero, the cycleCount field is
 *    not incremented for about 60 ns.
 *  - Occasionally, the entire register reads zero.
 *
 * To catch these, we read the register three times and ensure that the
 * difference between each two consecutive reads is approximately the same, i.e.
 * less than twice the other.  Furthermore, any negative difference indicates an
 * error.  (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
 * execute, so we have enough precision to compute the ratio of the differences.)
 */
static u32 get_cycle_time(struct fw_ohci *ohci)
{
	u32 c0, c1, c2;
	u32 t0, t1, t2;
	s32 diff01, diff12;
	int i;

	c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);

	if (ohci->quirks & QUIRK_CYCLE_TIMER) {
		i = 0;
		c1 = c2;
		c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
		do {
			c0 = c1;
			c1 = c2;
			c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
			t0 = cycle_timer_ticks(c0);
			t1 = cycle_timer_ticks(c1);
			t2 = cycle_timer_ticks(c2);
			diff01 = t1 - t0;
			diff12 = t2 - t1;
		} while ((diff01 <= 0 || diff12 <= 0 ||
			  diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
			 && i++ < 20);
	}

	return c2;
}

/*
 * This function has to be called at least every 64 seconds.  The bus_time
 * field stores not only the upper 25 bits of the BUS_TIME register but also
 * the most significant bit of the cycle timer in bit 6 so that we can detect
 * changes in this bit.
 */
static u32 update_bus_time(struct fw_ohci *ohci)
{
	u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;

	if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
		ohci->bus_time += 0x40;

	return ohci->bus_time | cycle_time_seconds;
}

1729 1730 1731 1732 1733 1734
static int get_status_for_port(struct fw_ohci *ohci, int port_index)
{
	int reg;

	mutex_lock(&ohci->phy_reg_mutex);
	reg = write_phy_reg(ohci, 7, port_index);
1735 1736
	if (reg >= 0)
		reg = read_phy_reg(ohci, 8);
1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754
	mutex_unlock(&ohci->phy_reg_mutex);
	if (reg < 0)
		return reg;

	switch (reg & 0x0f) {
	case 0x06:
		return 2;	/* is child node (connected to parent node) */
	case 0x0e:
		return 3;	/* is parent node (connected to child node) */
	}
	return 1;		/* not connected */
}

static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id,
	int self_id_count)
{
	int i;
	u32 entry;
1755

1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766
	for (i = 0; i < self_id_count; i++) {
		entry = ohci->self_id_buffer[i];
		if ((self_id & 0xff000000) == (entry & 0xff000000))
			return -1;
		if ((self_id & 0xff000000) < (entry & 0xff000000))
			return i;
	}
	return i;
}

/*
1767 1768 1769 1770
 * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally
 * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059.
 * Construct the selfID from phy register contents.
 * FIXME:  How to determine the selfID.i flag?
1771 1772 1773
 */
static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count)
{
1774 1775 1776
	int reg, i, pos, status;
	/* link active 1, speed 3, bridge 0, contender 1, more packets 0 */
	u32 self_id = 0x8040c800;
1777 1778 1779 1780 1781 1782 1783 1784

	reg = reg_read(ohci, OHCI1394_NodeID);
	if (!(reg & OHCI1394_NodeID_idValid)) {
		fw_notify("node ID not valid, new bus reset in progress\n");
		return -EBUSY;
	}
	self_id |= ((reg & 0x3f) << 24); /* phy ID */

1785
	reg = ohci_read_phy_reg(&ohci->card, 4);
1786 1787 1788 1789
	if (reg < 0)
		return reg;
	self_id |= ((reg & 0x07) << 8); /* power class */

1790
	reg = ohci_read_phy_reg(&ohci->card, 1);
1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812
	if (reg < 0)
		return reg;
	self_id |= ((reg & 0x3f) << 16); /* gap count */

	for (i = 0; i < 3; i++) {
		status = get_status_for_port(ohci, i);
		if (status < 0)
			return status;
		self_id |= ((status & 0x3) << (6 - (i * 2)));
	}

	pos = get_self_id_pos(ohci, self_id, self_id_count);
	if (pos >= 0) {
		memmove(&(ohci->self_id_buffer[pos+1]),
			&(ohci->self_id_buffer[pos]),
			(self_id_count - pos) * sizeof(*ohci->self_id_buffer));
		ohci->self_id_buffer[pos] = self_id;
		self_id_count++;
	}
	return self_id_count;
}

1813
static void bus_reset_work(struct work_struct *work)
1814
{
1815 1816
	struct fw_ohci *ohci =
		container_of(work, struct fw_ohci, bus_reset_work);
1817
	int self_id_count, i, j, reg;
1818 1819
	int generation, new_generation;
	unsigned long flags;
1820 1821
	void *free_rom = NULL;
	dma_addr_t free_rom_bus = 0;
1822
	bool is_new_root;
1823 1824 1825

	reg = reg_read(ohci, OHCI1394_NodeID);
	if (!(reg & OHCI1394_NodeID_idValid)) {
1826
		fw_notify("node ID not valid, new bus reset in progress\n");
1827 1828
		return;
	}
1829 1830 1831 1832 1833 1834
	if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
		fw_notify("malconfigured bus\n");
		return;
	}
	ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
			       OHCI1394_NodeID_nodeNumber);
1835

1836 1837 1838 1839 1840 1841
	is_new_root = (reg & OHCI1394_NodeID_root) != 0;
	if (!(ohci->is_root && is_new_root))
		reg_write(ohci, OHCI1394_LinkControlSet,
			  OHCI1394_LinkControl_cycleMaster);
	ohci->is_root = is_new_root;

1842 1843 1844 1845 1846
	reg = reg_read(ohci, OHCI1394_SelfIDCount);
	if (reg & OHCI1394_SelfIDCount_selfIDError) {
		fw_notify("inconsistent self IDs\n");
		return;
	}
1847 1848
	/*
	 * The count in the SelfIDCount register is the number of
1849 1850
	 * bytes in the self ID receive buffer.  Since we also receive
	 * the inverted quadlets and a header quadlet, we shift one
1851 1852
	 * bit extra to get the actual number of self IDs.
	 */
1853
	self_id_count = (reg >> 3) & 0xff;
1854 1855

	if (self_id_count > 252) {
1856 1857 1858
		fw_notify("inconsistent self IDs\n");
		return;
	}
1859

1860
	generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1861
	rmb();
1862 1863

	for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1864
		if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880
			/*
			 * If the invalid data looks like a cycle start packet,
			 * it's likely to be the result of the cycle master
			 * having a wrong gap count.  In this case, the self IDs
			 * so far are valid and should be processed so that the
			 * bus manager can then correct the gap count.
			 */
			if (cond_le32_to_cpu(ohci->self_id_cpu[i])
							== 0xffff008f) {
				fw_notify("ignoring spurious self IDs\n");
				self_id_count = j;
				break;
			} else {
				fw_notify("inconsistent self IDs\n");
				return;
			}
1881
		}
1882 1883
		ohci->self_id_buffer[j] =
				cond_le32_to_cpu(ohci->self_id_cpu[i]);
1884
	}
1885 1886 1887 1888

	if (ohci->quirks & QUIRK_TI_SLLZ059) {
		self_id_count = find_and_insert_self_id(ohci, self_id_count);
		if (self_id_count < 0) {
1889
			fw_notify("could not construct local self ID\n");
1890 1891 1892 1893 1894 1895 1896 1897
			return;
		}
	}

	if (self_id_count == 0) {
		fw_notify("inconsistent self IDs\n");
		return;
	}
1898
	rmb();
1899

1900 1901
	/*
	 * Check the consistency of the self IDs we just read.  The
1902 1903 1904 1905 1906 1907 1908 1909 1910
	 * problem we face is that a new bus reset can start while we
	 * read out the self IDs from the DMA buffer. If this happens,
	 * the DMA buffer will be overwritten with new self IDs and we
	 * will read out inconsistent data.  The OHCI specification
	 * (section 11.2) recommends a technique similar to
	 * linux/seqlock.h, where we remember the generation of the
	 * self IDs in the buffer before reading them out and compare
	 * it to the current generation after reading them out.  If
	 * the two generations match we know we have a consistent set
1911 1912
	 * of self IDs.
	 */
1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923

	new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
	if (new_generation != generation) {
		fw_notify("recursive bus reset detected, "
			  "discarding self ids\n");
		return;
	}

	/* FIXME: Document how the locking works. */
	spin_lock_irqsave(&ohci->lock, flags);

1924
	ohci->generation = -1; /* prevent AT packet queueing */
1925 1926
	context_stop(&ohci->at_request_ctx);
	context_stop(&ohci->at_response_ctx);
1927 1928 1929

	spin_unlock_irqrestore(&ohci->lock, flags);

1930 1931 1932 1933 1934
	/*
	 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
	 * packets in the AT queues and software needs to drain them.
	 * Some OHCI 1.1 controllers (JMicron) apparently require this too.
	 */
1935 1936 1937 1938 1939 1940
	at_context_flush(&ohci->at_request_ctx);
	at_context_flush(&ohci->at_response_ctx);

	spin_lock_irqsave(&ohci->lock, flags);

	ohci->generation = generation;
1941 1942
	reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);

1943
	if (ohci->quirks & QUIRK_RESET_PACKET)
1944 1945
		ohci->request_generation = generation;

1946 1947
	/*
	 * This next bit is unrelated to the AT context stuff but we
1948 1949 1950 1951
	 * have to do it under the spinlock also.  If a new config rom
	 * was set up before this reset, the old one is now no longer
	 * in use and we can free it. Update the config rom pointers
	 * to point to the current config rom and clear the
T
Thomas Weber 已提交
1952
	 * next_config_rom pointer so a new update can take place.
1953
	 */
1954 1955

	if (ohci->next_config_rom != NULL) {
1956 1957 1958 1959
		if (ohci->next_config_rom != ohci->config_rom) {
			free_rom      = ohci->config_rom;
			free_rom_bus  = ohci->config_rom_bus;
		}
1960 1961 1962 1963
		ohci->config_rom      = ohci->next_config_rom;
		ohci->config_rom_bus  = ohci->next_config_rom_bus;
		ohci->next_config_rom = NULL;

1964 1965
		/*
		 * Restore config_rom image and manually update
1966 1967
		 * config_rom registers.  Writing the header quadlet
		 * will indicate that the config rom is ready, so we
1968 1969
		 * do that last.
		 */
1970 1971
		reg_write(ohci, OHCI1394_BusOptions,
			  be32_to_cpu(ohci->config_rom[2]));
1972 1973 1974
		ohci->config_rom[0] = ohci->next_header;
		reg_write(ohci, OHCI1394_ConfigROMhdr,
			  be32_to_cpu(ohci->next_header));
1975 1976
	}

1977 1978 1979 1980 1981
#ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
	reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
	reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
#endif

1982 1983
	spin_unlock_irqrestore(&ohci->lock, flags);

1984 1985 1986 1987
	if (free_rom)
		dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
				  free_rom, free_rom_bus);

1988 1989
	log_selfids(ohci->node_id, generation,
		    self_id_count, ohci->self_id_buffer);
1990

1991
	fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1992 1993 1994
				 self_id_count, ohci->self_id_buffer,
				 ohci->csr_state_setclear_abdicate);
	ohci->csr_state_setclear_abdicate = false;
1995 1996 1997 1998 1999
}

static irqreturn_t irq_handler(int irq, void *data)
{
	struct fw_ohci *ohci = data;
2000
	u32 event, iso_event;
2001 2002 2003 2004
	int i;

	event = reg_read(ohci, OHCI1394_IntEventClear);

2005
	if (!event || !~event)
2006 2007
		return IRQ_NONE;

2008 2009 2010 2011 2012 2013
	/*
	 * busReset and postedWriteErr must not be cleared yet
	 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
	 */
	reg_write(ohci, OHCI1394_IntEventClear,
		  event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
2014
	log_irqs(event);
2015 2016

	if (event & OHCI1394_selfIDComplete)
2017
		queue_work(fw_workqueue, &ohci->bus_reset_work);
2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030

	if (event & OHCI1394_RQPkt)
		tasklet_schedule(&ohci->ar_request_ctx.tasklet);

	if (event & OHCI1394_RSPkt)
		tasklet_schedule(&ohci->ar_response_ctx.tasklet);

	if (event & OHCI1394_reqTxComplete)
		tasklet_schedule(&ohci->at_request_ctx.tasklet);

	if (event & OHCI1394_respTxComplete)
		tasklet_schedule(&ohci->at_response_ctx.tasklet);

2031 2032 2033 2034 2035 2036 2037 2038 2039 2040
	if (event & OHCI1394_isochRx) {
		iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
		reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);

		while (iso_event) {
			i = ffs(iso_event) - 1;
			tasklet_schedule(
				&ohci->ir_context_list[i].context.tasklet);
			iso_event &= ~(1 << i);
		}
2041 2042
	}

2043 2044 2045
	if (event & OHCI1394_isochTx) {
		iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
		reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
2046

2047 2048 2049 2050 2051 2052
		while (iso_event) {
			i = ffs(iso_event) - 1;
			tasklet_schedule(
				&ohci->it_context_list[i].context.tasklet);
			iso_event &= ~(1 << i);
		}
2053 2054
	}

2055 2056 2057 2058
	if (unlikely(event & OHCI1394_regAccessFail))
		fw_error("Register access failure - "
			 "please notify linux1394-devel@lists.sf.net\n");

2059 2060 2061 2062 2063
	if (unlikely(event & OHCI1394_postedWriteErr)) {
		reg_read(ohci, OHCI1394_PostedWriteAddressHi);
		reg_read(ohci, OHCI1394_PostedWriteAddressLo);
		reg_write(ohci, OHCI1394_IntEventClear,
			  OHCI1394_postedWriteErr);
S
Stephan Gatzka 已提交
2064 2065
		if (printk_ratelimit())
			fw_error("PCI posted write error\n");
2066
	}
2067

2068 2069 2070 2071 2072 2073 2074
	if (unlikely(event & OHCI1394_cycleTooLong)) {
		if (printk_ratelimit())
			fw_notify("isochronous cycle too long\n");
		reg_write(ohci, OHCI1394_LinkControlSet,
			  OHCI1394_LinkControl_cycleMaster);
	}

2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085
	if (unlikely(event & OHCI1394_cycleInconsistent)) {
		/*
		 * We need to clear this event bit in order to make
		 * cycleMatch isochronous I/O work.  In theory we should
		 * stop active cycleMatch iso contexts now and restart
		 * them at least two cycles later.  (FIXME?)
		 */
		if (printk_ratelimit())
			fw_notify("isochronous cycle inconsistent\n");
	}

2086 2087 2088
	if (unlikely(event & OHCI1394_unrecoverableError))
		handle_dead_contexts(ohci);

2089 2090 2091 2092
	if (event & OHCI1394_cycle64Seconds) {
		spin_lock(&ohci->lock);
		update_bus_time(ohci);
		spin_unlock(&ohci->lock);
2093 2094
	} else
		flush_writes(ohci);
2095

2096 2097 2098
	return IRQ_HANDLED;
}

2099 2100
static int software_reset(struct fw_ohci *ohci)
{
2101
	u32 val;
2102 2103 2104
	int i;

	reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
2105 2106 2107 2108
	for (i = 0; i < 500; i++) {
		val = reg_read(ohci, OHCI1394_HCControlSet);
		if (!~val)
			return -ENODEV; /* Card was ejected. */
2109

2110
		if (!(val & OHCI1394_HCControl_softReset))
2111
			return 0;
2112

2113 2114 2115 2116 2117 2118
		msleep(1);
	}

	return -EBUSY;
}

2119 2120 2121 2122 2123 2124 2125 2126 2127
static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
{
	size_t size = length * 4;

	memcpy(dest, src, size);
	if (size < CONFIG_ROM_SIZE)
		memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
}

2128 2129 2130
static int configure_1394a_enhancements(struct fw_ohci *ohci)
{
	bool enable_1394a;
2131
	int ret, clear, set, offset;
2132 2133 2134 2135 2136 2137 2138 2139

	/* Check if the driver should configure link and PHY. */
	if (!(reg_read(ohci, OHCI1394_HCControlSet) &
	      OHCI1394_HCControl_programPhyEnable))
		return 0;

	/* Paranoia: check whether the PHY supports 1394a, too. */
	enable_1394a = false;
2140 2141 2142 2143 2144 2145 2146 2147
	ret = read_phy_reg(ohci, 2);
	if (ret < 0)
		return ret;
	if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
		ret = read_paged_phy_reg(ohci, 1, 8);
		if (ret < 0)
			return ret;
		if (ret >= 1)
2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161
			enable_1394a = true;
	}

	if (ohci->quirks & QUIRK_NO_1394A)
		enable_1394a = false;

	/* Configure PHY and link consistently. */
	if (enable_1394a) {
		clear = 0;
		set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
	} else {
		clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
		set = 0;
	}
2162
	ret = update_phy_reg(ohci, 5, clear, set);
2163 2164
	if (ret < 0)
		return ret;
2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178

	if (enable_1394a)
		offset = OHCI1394_HCControlSet;
	else
		offset = OHCI1394_HCControlClear;
	reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);

	/* Clean up: configuration has been taken care of. */
	reg_write(ohci, OHCI1394_HCControlClear,
		  OHCI1394_HCControl_programPhyEnable);

	return 0;
}

2179 2180
static int probe_tsb41ba3d(struct fw_ohci *ohci)
{
2181 2182 2183
	/* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */
	static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, };
	int reg, i;
2184 2185 2186 2187

	reg = read_phy_reg(ohci, 2);
	if (reg < 0)
		return reg;
2188 2189
	if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS)
		return 0;
2190

2191 2192 2193 2194 2195 2196
	for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) {
		reg = read_paged_phy_reg(ohci, 1, i + 10);
		if (reg < 0)
			return reg;
		if (reg != id[i])
			return 0;
2197
	}
2198
	return 1;
2199 2200
}

2201 2202
static int ohci_enable(struct fw_card *card,
		       const __be32 *config_rom, size_t length)
2203 2204 2205
{
	struct fw_ohci *ohci = fw_ohci(card);
	struct pci_dev *dev = to_pci_dev(card->device);
2206
	u32 lps, seconds, version, irqs;
2207
	int i, ret;
2208

2209 2210 2211 2212 2213 2214 2215 2216 2217 2218
	if (software_reset(ohci)) {
		fw_error("Failed to reset ohci card.\n");
		return -EBUSY;
	}

	/*
	 * Now enable LPS, which we need in order to start accessing
	 * most of the registers.  In fact, on some cards (ALI M5251),
	 * accessing registers in the SClk domain without LPS enabled
	 * will lock up the machine.  Wait 50msec to make sure we have
2219 2220
	 * full link enabled.  However, with some cards (well, at least
	 * a JMicron PCIe card), we have to try again sometimes.
2221 2222 2223 2224 2225
	 */
	reg_write(ohci, OHCI1394_HCControlSet,
		  OHCI1394_HCControl_LPS |
		  OHCI1394_HCControl_postedWriteEnable);
	flush_writes(ohci);
2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236

	for (lps = 0, i = 0; !lps && i < 3; i++) {
		msleep(50);
		lps = reg_read(ohci, OHCI1394_HCControlSet) &
		      OHCI1394_HCControl_LPS;
	}

	if (!lps) {
		fw_error("Failed to set Link Power Status\n");
		return -EIO;
	}
2237

2238
	if (ohci->quirks & QUIRK_TI_SLLZ059) {
2239 2240 2241 2242 2243 2244
		ret = probe_tsb41ba3d(ohci);
		if (ret < 0)
			return ret;
		if (ret)
			fw_notify("local TSB41BA3D phy\n");
		else
2245 2246 2247
			ohci->quirks &= ~QUIRK_TI_SLLZ059;
	}

2248 2249 2250
	reg_write(ohci, OHCI1394_HCControlClear,
		  OHCI1394_HCControl_noByteSwapData);

2251
	reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2252 2253 2254 2255 2256 2257 2258
	reg_write(ohci, OHCI1394_LinkControlSet,
		  OHCI1394_LinkControl_cycleTimerEnable |
		  OHCI1394_LinkControl_cycleMaster);

	reg_write(ohci, OHCI1394_ATRetries,
		  OHCI1394_MAX_AT_REQ_RETRIES |
		  (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
2259 2260
		  (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
		  (200 << 16));
2261

2262 2263 2264 2265
	seconds = lower_32_bits(get_seconds());
	reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
	ohci->bus_time = seconds & ~0x3f;

2266 2267 2268 2269
	version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
	if (version >= OHCI_VERSION_1_1) {
		reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
			  0xfffffffe);
2270
		card->broadcast_channel_auto_allocated = true;
2271 2272
	}

2273 2274 2275 2276
	/* Get implemented bits of the priority arbitration request counter. */
	reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
	ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
	reg_write(ohci, OHCI1394_FairnessControl, 0);
2277
	card->priority_budget_implemented = ohci->pri_req_max != 0;
2278 2279 2280 2281 2282

	reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
	reg_write(ohci, OHCI1394_IntEventClear, ~0);
	reg_write(ohci, OHCI1394_IntMaskClear, ~0);

2283 2284 2285
	ret = configure_1394a_enhancements(ohci);
	if (ret < 0)
		return ret;
2286

2287
	/* Activate link_on bit and contender bit in our self ID packets.*/
2288 2289 2290
	ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
	if (ret < 0)
		return ret;
2291

2292 2293
	/*
	 * When the link is not yet enabled, the atomic config rom
2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310
	 * update mechanism described below in ohci_set_config_rom()
	 * is not active.  We have to update ConfigRomHeader and
	 * BusOptions manually, and the write to ConfigROMmap takes
	 * effect immediately.  We tie this to the enabling of the
	 * link, so we have a valid config rom before enabling - the
	 * OHCI requires that ConfigROMhdr and BusOptions have valid
	 * values before enabling.
	 *
	 * However, when the ConfigROMmap is written, some controllers
	 * always read back quadlets 0 and 2 from the config rom to
	 * the ConfigRomHeader and BusOptions registers on bus reset.
	 * They shouldn't do that in this initial case where the link
	 * isn't enabled.  This means we have to use the same
	 * workaround here, setting the bus header to 0 and then write
	 * the right values in the bus reset tasklet.
	 */

2311 2312 2313 2314 2315 2316 2317
	if (config_rom) {
		ohci->next_config_rom =
			dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
					   &ohci->next_config_rom_bus,
					   GFP_KERNEL);
		if (ohci->next_config_rom == NULL)
			return -ENOMEM;
2318

2319
		copy_config_rom(ohci->next_config_rom, config_rom, length);
2320 2321 2322 2323 2324 2325 2326 2327
	} else {
		/*
		 * In the suspend case, config_rom is NULL, which
		 * means that we just reuse the old config rom.
		 */
		ohci->next_config_rom = ohci->config_rom;
		ohci->next_config_rom_bus = ohci->config_rom_bus;
	}
2328

2329
	ohci->next_header = ohci->next_config_rom[0];
2330 2331
	ohci->next_config_rom[0] = 0;
	reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
2332 2333
	reg_write(ohci, OHCI1394_BusOptions,
		  be32_to_cpu(ohci->next_config_rom[2]));
2334 2335 2336 2337
	reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);

	reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);

2338 2339
	if (!(ohci->quirks & QUIRK_NO_MSI))
		pci_enable_msi(dev);
2340
	if (request_irq(dev->irq, irq_handler,
2341 2342 2343 2344
			pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
			ohci_driver_name, ohci)) {
		fw_error("Failed to allocate interrupt %d.\n", dev->irq);
		pci_disable_msi(dev);
2345 2346 2347 2348 2349 2350 2351

		if (config_rom) {
			dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
					  ohci->next_config_rom,
					  ohci->next_config_rom_bus);
			ohci->next_config_rom = NULL;
		}
2352 2353 2354
		return -EIO;
	}

2355 2356 2357 2358 2359 2360
	irqs =	OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
		OHCI1394_RQPkt | OHCI1394_RSPkt |
		OHCI1394_isochTx | OHCI1394_isochRx |
		OHCI1394_postedWriteErr |
		OHCI1394_selfIDComplete |
		OHCI1394_regAccessFail |
2361
		OHCI1394_cycle64Seconds |
2362 2363 2364
		OHCI1394_cycleInconsistent |
		OHCI1394_unrecoverableError |
		OHCI1394_cycleTooLong |
2365 2366 2367 2368 2369
		OHCI1394_masterIntEnable;
	if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
		irqs |= OHCI1394_busReset;
	reg_write(ohci, OHCI1394_IntMaskSet, irqs);

2370 2371 2372
	reg_write(ohci, OHCI1394_HCControlSet,
		  OHCI1394_HCControl_linkEnable |
		  OHCI1394_HCControl_BIBimageValid);
2373 2374 2375 2376 2377 2378

	reg_write(ohci, OHCI1394_LinkControlSet,
		  OHCI1394_LinkControl_rcvSelfID |
		  OHCI1394_LinkControl_rcvPhyPkt);

	ar_context_run(&ohci->ar_request_ctx);
2379 2380 2381
	ar_context_run(&ohci->ar_response_ctx);

	flush_writes(ohci);
2382

2383 2384
	/* We are ready to go, reset bus to finish initialization. */
	fw_schedule_bus_reset(&ohci->card, false, true);
2385 2386 2387 2388

	return 0;
}

2389
static int ohci_set_config_rom(struct fw_card *card,
2390
			       const __be32 *config_rom, size_t length)
2391 2392 2393 2394
{
	struct fw_ohci *ohci;
	unsigned long flags;
	__be32 *next_config_rom;
2395
	dma_addr_t uninitialized_var(next_config_rom_bus);
2396 2397 2398

	ohci = fw_ohci(card);

2399 2400
	/*
	 * When the OHCI controller is enabled, the config rom update
2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422
	 * mechanism is a bit tricky, but easy enough to use.  See
	 * section 5.5.6 in the OHCI specification.
	 *
	 * The OHCI controller caches the new config rom address in a
	 * shadow register (ConfigROMmapNext) and needs a bus reset
	 * for the changes to take place.  When the bus reset is
	 * detected, the controller loads the new values for the
	 * ConfigRomHeader and BusOptions registers from the specified
	 * config rom and loads ConfigROMmap from the ConfigROMmapNext
	 * shadow register. All automatically and atomically.
	 *
	 * Now, there's a twist to this story.  The automatic load of
	 * ConfigRomHeader and BusOptions doesn't honor the
	 * noByteSwapData bit, so with a be32 config rom, the
	 * controller will load be32 values in to these registers
	 * during the atomic update, even on litte endian
	 * architectures.  The workaround we use is to put a 0 in the
	 * header quadlet; 0 is endian agnostic and means that the
	 * config rom isn't ready yet.  In the bus reset tasklet we
	 * then set up the real values for the two registers.
	 *
	 * We use ohci->lock to avoid racing with the code that sets
2423
	 * ohci->next_config_rom to NULL (see bus_reset_work).
2424 2425 2426 2427 2428 2429 2430 2431 2432 2433
	 */

	next_config_rom =
		dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
				   &next_config_rom_bus, GFP_KERNEL);
	if (next_config_rom == NULL)
		return -ENOMEM;

	spin_lock_irqsave(&ohci->lock, flags);

2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444
	/*
	 * If there is not an already pending config_rom update,
	 * push our new allocation into the ohci->next_config_rom
	 * and then mark the local variable as null so that we
	 * won't deallocate the new buffer.
	 *
	 * OTOH, if there is a pending config_rom update, just
	 * use that buffer with the new config_rom data, and
	 * let this routine free the unused DMA allocation.
	 */

2445 2446 2447
	if (ohci->next_config_rom == NULL) {
		ohci->next_config_rom = next_config_rom;
		ohci->next_config_rom_bus = next_config_rom_bus;
2448 2449
		next_config_rom = NULL;
	}
2450

2451
	copy_config_rom(ohci->next_config_rom, config_rom, length);
2452

2453 2454
	ohci->next_header = config_rom[0];
	ohci->next_config_rom[0] = 0;
2455

2456
	reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2457 2458 2459

	spin_unlock_irqrestore(&ohci->lock, flags);

2460 2461 2462 2463 2464
	/* If we didn't use the DMA allocation, delete it. */
	if (next_config_rom != NULL)
		dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
				  next_config_rom, next_config_rom_bus);

2465 2466
	/*
	 * Now initiate a bus reset to have the changes take
2467 2468 2469
	 * effect. We clean up the old config rom memory and DMA
	 * mappings in the bus reset tasklet, since the OHCI
	 * controller could need to access it before the bus reset
2470 2471
	 * takes effect.
	 */
2472

2473 2474 2475
	fw_schedule_bus_reset(&ohci->card, true, true);

	return 0;
2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491
}

static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
{
	struct fw_ohci *ohci = fw_ohci(card);

	at_context_transmit(&ohci->at_request_ctx, packet);
}

static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
{
	struct fw_ohci *ohci = fw_ohci(card);

	at_context_transmit(&ohci->at_response_ctx, packet);
}

2492 2493 2494
static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
{
	struct fw_ohci *ohci = fw_ohci(card);
2495 2496
	struct context *ctx = &ohci->at_request_ctx;
	struct driver_data *driver_data = packet->driver_data;
2497
	int ret = -ENOENT;
2498

2499
	tasklet_disable(&ctx->tasklet);
2500

2501 2502
	if (packet->ack != 0)
		goto out;
2503

2504
	if (packet->payload_mapped)
2505 2506 2507
		dma_unmap_single(ohci->card.device, packet->payload_bus,
				 packet->payload_length, DMA_TO_DEVICE);

2508
	log_ar_at_event('T', packet->speed, packet->header, 0x20);
2509 2510 2511
	driver_data->packet = NULL;
	packet->ack = RCODE_CANCELLED;
	packet->callback(packet, &ohci->card, packet->ack);
2512
	ret = 0;
2513 2514
 out:
	tasklet_enable(&ctx->tasklet);
2515

2516
	return ret;
2517 2518
}

2519 2520
static int ohci_enable_phys_dma(struct fw_card *card,
				int node_id, int generation)
2521
{
2522 2523 2524
#ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
	return 0;
#else
2525 2526
	struct fw_ohci *ohci = fw_ohci(card);
	unsigned long flags;
2527
	int n, ret = 0;
2528

2529 2530 2531 2532
	/*
	 * FIXME:  Make sure this bitmask is cleared when we clear the busReset
	 * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
	 */
2533 2534 2535 2536

	spin_lock_irqsave(&ohci->lock, flags);

	if (ohci->generation != generation) {
2537
		ret = -ESTALE;
2538 2539 2540
		goto out;
	}

2541 2542 2543 2544
	/*
	 * Note, if the node ID contains a non-local bus ID, physical DMA is
	 * enabled for _all_ nodes on remote buses.
	 */
2545 2546 2547 2548 2549 2550 2551

	n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
	if (n < 32)
		reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
	else
		reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));

2552 2553
	flush_writes(ohci);
 out:
2554
	spin_unlock_irqrestore(&ohci->lock, flags);
2555 2556

	return ret;
2557
#endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2558
}
S
Stefan Richter 已提交
2559

2560
static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2561
{
2562
	struct fw_ohci *ohci = fw_ohci(card);
2563 2564
	unsigned long flags;
	u32 value;
2565 2566

	switch (csr_offset) {
2567 2568 2569 2570 2571
	case CSR_STATE_CLEAR:
	case CSR_STATE_SET:
		if (ohci->is_root &&
		    (reg_read(ohci, OHCI1394_LinkControlSet) &
		     OHCI1394_LinkControl_cycleMaster))
2572
			value = CSR_STATE_BIT_CMSTR;
2573
		else
2574 2575 2576
			value = 0;
		if (ohci->csr_state_setclear_abdicate)
			value |= CSR_STATE_BIT_ABDICATE;
2577

2578
		return value;
2579

2580 2581 2582
	case CSR_NODE_IDS:
		return reg_read(ohci, OHCI1394_NodeID) << 16;

2583 2584 2585
	case CSR_CYCLE_TIME:
		return get_cycle_time(ohci);

2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596
	case CSR_BUS_TIME:
		/*
		 * We might be called just after the cycle timer has wrapped
		 * around but just before the cycle64Seconds handler, so we
		 * better check here, too, if the bus time needs to be updated.
		 */
		spin_lock_irqsave(&ohci->lock, flags);
		value = update_bus_time(ohci);
		spin_unlock_irqrestore(&ohci->lock, flags);
		return value;

2597 2598 2599 2600
	case CSR_BUSY_TIMEOUT:
		value = reg_read(ohci, OHCI1394_ATRetries);
		return (value >> 4) & 0x0ffff00f;

2601 2602 2603 2604
	case CSR_PRIORITY_BUDGET:
		return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
			(ohci->pri_req_max << 8);

2605 2606 2607 2608
	default:
		WARN_ON(1);
		return 0;
	}
2609 2610
}

2611
static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2612 2613
{
	struct fw_ohci *ohci = fw_ohci(card);
2614
	unsigned long flags;
2615

2616
	switch (csr_offset) {
2617 2618 2619 2620 2621 2622
	case CSR_STATE_CLEAR:
		if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
			reg_write(ohci, OHCI1394_LinkControlClear,
				  OHCI1394_LinkControl_cycleMaster);
			flush_writes(ohci);
		}
2623 2624
		if (value & CSR_STATE_BIT_ABDICATE)
			ohci->csr_state_setclear_abdicate = false;
2625
		break;
2626

2627 2628 2629 2630 2631 2632
	case CSR_STATE_SET:
		if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
			reg_write(ohci, OHCI1394_LinkControlSet,
				  OHCI1394_LinkControl_cycleMaster);
			flush_writes(ohci);
		}
2633 2634
		if (value & CSR_STATE_BIT_ABDICATE)
			ohci->csr_state_setclear_abdicate = true;
2635
		break;
2636

2637 2638 2639 2640 2641
	case CSR_NODE_IDS:
		reg_write(ohci, OHCI1394_NodeID, value >> 16);
		flush_writes(ohci);
		break;

2642 2643 2644 2645 2646 2647 2648
	case CSR_CYCLE_TIME:
		reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
		reg_write(ohci, OHCI1394_IntEventSet,
			  OHCI1394_cycleInconsistent);
		flush_writes(ohci);
		break;

2649 2650 2651 2652 2653 2654
	case CSR_BUS_TIME:
		spin_lock_irqsave(&ohci->lock, flags);
		ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
		spin_unlock_irqrestore(&ohci->lock, flags);
		break;

2655 2656 2657 2658 2659 2660 2661
	case CSR_BUSY_TIMEOUT:
		value = (value & 0xf) | ((value & 0xf) << 4) |
			((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
		reg_write(ohci, OHCI1394_ATRetries, value);
		flush_writes(ohci);
		break;

2662 2663 2664 2665 2666
	case CSR_PRIORITY_BUDGET:
		reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
		flush_writes(ohci);
		break;

2667 2668 2669 2670
	default:
		WARN_ON(1);
		break;
	}
2671 2672
}

2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694
static void copy_iso_headers(struct iso_context *ctx, void *p)
{
	int i = ctx->header_length;

	if (i + ctx->base.header_size > PAGE_SIZE)
		return;

	/*
	 * The iso header is byteswapped to little endian by
	 * the controller, but the remaining header quadlets
	 * are big endian.  We want to present all the headers
	 * as big endian, so we have to swap the first quadlet.
	 */
	if (ctx->base.header_size > 0)
		*(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
	if (ctx->base.header_size > 4)
		*(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
	if (ctx->base.header_size > 8)
		memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
	ctx->header_length += ctx->base.header_size;
}

2695 2696 2697 2698 2699 2700
static int handle_ir_packet_per_buffer(struct context *context,
				       struct descriptor *d,
				       struct descriptor *last)
{
	struct iso_context *ctx =
		container_of(context, struct iso_context, context);
2701
	struct descriptor *pd;
2702
	u32 buffer_dma;
2703
	__le32 *ir_header;
2704
	void *p;
2705

2706
	for (pd = d; pd <= last; pd++)
2707 2708 2709
		if (pd->transfer_status)
			break;
	if (pd > last)
2710 2711 2712
		/* Descriptor(s) not done yet, stop iteration */
		return 0;

2713 2714 2715 2716 2717 2718 2719 2720 2721 2722
	while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) {
		d++;
		buffer_dma = le32_to_cpu(d->data_address);
		dma_sync_single_range_for_cpu(context->ohci->card.device,
					      buffer_dma & PAGE_MASK,
					      buffer_dma & ~PAGE_MASK,
					      le16_to_cpu(d->req_count),
					      DMA_FROM_DEVICE);
	}

2723 2724
	p = last + 1;
	copy_iso_headers(ctx, p);
2725

2726 2727
	if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
		ir_header = (__le32 *) p;
2728 2729 2730 2731
		ctx->base.callback.sc(&ctx->base,
				      le32_to_cpu(ir_header[0]) & 0xffff,
				      ctx->header_length, ctx->header,
				      ctx->base.callback_data);
2732 2733 2734 2735 2736 2737
		ctx->header_length = 0;
	}

	return 1;
}

2738 2739 2740 2741 2742 2743 2744
/* d == last because each descriptor block is only a single descriptor. */
static int handle_ir_buffer_fill(struct context *context,
				 struct descriptor *d,
				 struct descriptor *last)
{
	struct iso_context *ctx =
		container_of(context, struct iso_context, context);
2745
	u32 buffer_dma;
2746 2747 2748 2749 2750

	if (!last->transfer_status)
		/* Descriptor(s) not done yet, stop iteration */
		return 0;

2751 2752 2753 2754 2755 2756 2757
	buffer_dma = le32_to_cpu(last->data_address);
	dma_sync_single_range_for_cpu(context->ohci->card.device,
				      buffer_dma & PAGE_MASK,
				      buffer_dma & ~PAGE_MASK,
				      le16_to_cpu(last->req_count),
				      DMA_FROM_DEVICE);

2758 2759 2760 2761 2762 2763 2764 2765 2766 2767
	if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
		ctx->base.callback.mc(&ctx->base,
				      le32_to_cpu(last->data_address) +
				      le16_to_cpu(last->req_count) -
				      le16_to_cpu(last->res_count),
				      ctx->base.callback_data);

	return 1;
}

2768 2769 2770 2771 2772 2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804
static inline void sync_it_packet_for_cpu(struct context *context,
					  struct descriptor *pd)
{
	__le16 control;
	u32 buffer_dma;

	/* only packets beginning with OUTPUT_MORE* have data buffers */
	if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
		return;

	/* skip over the OUTPUT_MORE_IMMEDIATE descriptor */
	pd += 2;

	/*
	 * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's
	 * data buffer is in the context program's coherent page and must not
	 * be synced.
	 */
	if ((le32_to_cpu(pd->data_address) & PAGE_MASK) ==
	    (context->current_bus          & PAGE_MASK)) {
		if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
			return;
		pd++;
	}

	do {
		buffer_dma = le32_to_cpu(pd->data_address);
		dma_sync_single_range_for_cpu(context->ohci->card.device,
					      buffer_dma & PAGE_MASK,
					      buffer_dma & ~PAGE_MASK,
					      le16_to_cpu(pd->req_count),
					      DMA_TO_DEVICE);
		control = pd->control;
		pd++;
	} while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)));
}

2805 2806 2807
static int handle_it_packet(struct context *context,
			    struct descriptor *d,
			    struct descriptor *last)
2808
{
2809 2810
	struct iso_context *ctx =
		container_of(context, struct iso_context, context);
2811 2812
	int i;
	struct descriptor *pd;
S
Stefan Richter 已提交
2813

2814 2815 2816 2817 2818
	for (pd = d; pd <= last; pd++)
		if (pd->transfer_status)
			break;
	if (pd > last)
		/* Descriptor(s) not done yet, stop iteration */
2819 2820
		return 0;

2821 2822
	sync_it_packet_for_cpu(context, d);

2823 2824 2825 2826 2827 2828 2829 2830 2831
	i = ctx->header_length;
	if (i + 4 < PAGE_SIZE) {
		/* Present this value as big-endian to match the receive code */
		*(__be32 *)(ctx->header + i) = cpu_to_be32(
				((u32)le16_to_cpu(pd->transfer_status) << 16) |
				le16_to_cpu(pd->res_count));
		ctx->header_length += 4;
	}
	if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2832 2833 2834
		ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count),
				      ctx->header_length, ctx->header,
				      ctx->base.callback_data);
2835 2836
		ctx->header_length = 0;
	}
2837
	return 1;
2838 2839
}

2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851
static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
{
	u32 hi = channels >> 32, lo = channels;

	reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
	reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
	reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
	reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
	mmiowb();
	ohci->mc_channels = channels;
}

2852
static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2853
				int type, int channel, size_t header_size)
2854 2855
{
	struct fw_ohci *ohci = fw_ohci(card);
2856 2857 2858 2859
	struct iso_context *uninitialized_var(ctx);
	descriptor_callback_t uninitialized_var(callback);
	u64 *uninitialized_var(channels);
	u32 *uninitialized_var(mask), uninitialized_var(regs);
2860
	unsigned long flags;
2861
	int index, ret = -EBUSY;
2862

2863
	spin_lock_irqsave(&ohci->lock, flags);
2864

2865 2866 2867
	switch (type) {
	case FW_ISO_CONTEXT_TRANSMIT:
		mask     = &ohci->it_context_mask;
2868
		callback = handle_it_packet;
2869 2870 2871 2872 2873 2874 2875 2876 2877
		index    = ffs(*mask) - 1;
		if (index >= 0) {
			*mask &= ~(1 << index);
			regs = OHCI1394_IsoXmitContextBase(index);
			ctx  = &ohci->it_context_list[index];
		}
		break;

	case FW_ISO_CONTEXT_RECEIVE:
2878
		channels = &ohci->ir_context_channels;
2879
		mask     = &ohci->ir_context_mask;
2880
		callback = handle_ir_packet_per_buffer;
2881 2882 2883 2884 2885 2886 2887 2888
		index    = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
		if (index >= 0) {
			*channels &= ~(1ULL << channel);
			*mask     &= ~(1 << index);
			regs = OHCI1394_IsoRcvContextBase(index);
			ctx  = &ohci->ir_context_list[index];
		}
		break;
2889

2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904
	case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
		mask     = &ohci->ir_context_mask;
		callback = handle_ir_buffer_fill;
		index    = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
		if (index >= 0) {
			ohci->mc_allocated = true;
			*mask &= ~(1 << index);
			regs = OHCI1394_IsoRcvContextBase(index);
			ctx  = &ohci->ir_context_list[index];
		}
		break;

	default:
		index = -1;
		ret = -ENOSYS;
2905
	}
2906

2907 2908 2909
	spin_unlock_irqrestore(&ohci->lock, flags);

	if (index < 0)
2910
		return ERR_PTR(ret);
S
Stefan Richter 已提交
2911

2912
	memset(ctx, 0, sizeof(*ctx));
2913 2914
	ctx->header_length = 0;
	ctx->header = (void *) __get_free_page(GFP_KERNEL);
2915 2916
	if (ctx->header == NULL) {
		ret = -ENOMEM;
2917
		goto out;
2918
	}
2919 2920
	ret = context_init(&ctx->context, ohci, regs, callback);
	if (ret < 0)
2921
		goto out_with_header;
2922

2923 2924 2925
	if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL)
		set_multichannel_mask(ohci, 0);

2926
	return &ctx->base;
2927 2928 2929 2930 2931

 out_with_header:
	free_page((unsigned long)ctx->header);
 out:
	spin_lock_irqsave(&ohci->lock, flags);
2932 2933 2934 2935 2936 2937 2938 2939 2940 2941

	switch (type) {
	case FW_ISO_CONTEXT_RECEIVE:
		*channels |= 1ULL << channel;
		break;

	case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
		ohci->mc_allocated = false;
		break;
	}
2942
	*mask |= 1 << index;
2943

2944 2945
	spin_unlock_irqrestore(&ohci->lock, flags);

2946
	return ERR_PTR(ret);
2947 2948
}

2949 2950
static int ohci_start_iso(struct fw_iso_context *base,
			  s32 cycle, u32 sync, u32 tags)
2951
{
S
Stefan Richter 已提交
2952
	struct iso_context *ctx = container_of(base, struct iso_context, base);
2953
	struct fw_ohci *ohci = ctx->context.ohci;
2954
	u32 control = IR_CONTEXT_ISOCH_HEADER, match;
2955 2956
	int index;

2957 2958 2959 2960
	/* the controller cannot start without any queued packets */
	if (ctx->context.last->branch_address == 0)
		return -ENODATA;

2961 2962
	switch (ctx->base.type) {
	case FW_ISO_CONTEXT_TRANSMIT:
2963
		index = ctx - ohci->it_context_list;
2964 2965 2966
		match = 0;
		if (cycle >= 0)
			match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2967
				(cycle & 0x7fff) << 16;
2968

2969 2970
		reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
		reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2971
		context_run(&ctx->context, match);
2972 2973 2974 2975 2976 2977
		break;

	case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
		control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
		/* fall through */
	case FW_ISO_CONTEXT_RECEIVE:
2978
		index = ctx - ohci->ir_context_list;
2979 2980 2981 2982 2983
		match = (tags << 28) | (sync << 8) | ctx->base.channel;
		if (cycle >= 0) {
			match |= (cycle & 0x07fff) << 12;
			control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
		}
2984

2985 2986
		reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
		reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2987
		reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2988
		context_run(&ctx->context, control);
2989 2990 2991 2992

		ctx->sync = sync;
		ctx->tags = tags;

2993
		break;
2994
	}
2995 2996 2997 2998

	return 0;
}

2999 3000 3001
static int ohci_stop_iso(struct fw_iso_context *base)
{
	struct fw_ohci *ohci = fw_ohci(base->card);
S
Stefan Richter 已提交
3002
	struct iso_context *ctx = container_of(base, struct iso_context, base);
3003 3004
	int index;

3005 3006
	switch (ctx->base.type) {
	case FW_ISO_CONTEXT_TRANSMIT:
3007 3008
		index = ctx - ohci->it_context_list;
		reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
3009 3010 3011 3012
		break;

	case FW_ISO_CONTEXT_RECEIVE:
	case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3013 3014
		index = ctx - ohci->ir_context_list;
		reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
3015
		break;
3016 3017 3018
	}
	flush_writes(ohci);
	context_stop(&ctx->context);
3019
	tasklet_kill(&ctx->context.tasklet);
3020 3021 3022 3023

	return 0;
}

3024 3025 3026
static void ohci_free_iso_context(struct fw_iso_context *base)
{
	struct fw_ohci *ohci = fw_ohci(base->card);
S
Stefan Richter 已提交
3027
	struct iso_context *ctx = container_of(base, struct iso_context, base);
3028 3029 3030
	unsigned long flags;
	int index;

3031 3032
	ohci_stop_iso(base);
	context_release(&ctx->context);
3033
	free_page((unsigned long)ctx->header);
3034

3035 3036
	spin_lock_irqsave(&ohci->lock, flags);

3037 3038
	switch (base->type) {
	case FW_ISO_CONTEXT_TRANSMIT:
3039 3040
		index = ctx - ohci->it_context_list;
		ohci->it_context_mask |= 1 << index;
3041 3042 3043
		break;

	case FW_ISO_CONTEXT_RECEIVE:
3044 3045
		index = ctx - ohci->ir_context_list;
		ohci->ir_context_mask |= 1 << index;
3046
		ohci->ir_context_channels |= 1ULL << base->channel;
3047 3048 3049 3050 3051 3052 3053 3054 3055
		break;

	case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
		index = ctx - ohci->ir_context_list;
		ohci->ir_context_mask |= 1 << index;
		ohci->ir_context_channels |= ohci->mc_channels;
		ohci->mc_channels = 0;
		ohci->mc_allocated = false;
		break;
3056 3057 3058 3059 3060
	}

	spin_unlock_irqrestore(&ohci->lock, flags);
}

3061 3062 3063 3064 3065 3066 3067 3068 3069 3070 3071 3072 3073 3074 3075 3076 3077 3078 3079 3080 3081 3082 3083 3084 3085 3086 3087 3088 3089 3090
static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
{
	struct fw_ohci *ohci = fw_ohci(base->card);
	unsigned long flags;
	int ret;

	switch (base->type) {
	case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:

		spin_lock_irqsave(&ohci->lock, flags);

		/* Don't allow multichannel to grab other contexts' channels. */
		if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
			*channels = ohci->ir_context_channels;
			ret = -EBUSY;
		} else {
			set_multichannel_mask(ohci, *channels);
			ret = 0;
		}

		spin_unlock_irqrestore(&ohci->lock, flags);

		break;
	default:
		ret = -EINVAL;
	}

	return ret;
}

3091 3092 3093 3094 3095 3096 3097 3098
#ifdef CONFIG_PM
static void ohci_resume_iso_dma(struct fw_ohci *ohci)
{
	int i;
	struct iso_context *ctx;

	for (i = 0 ; i < ohci->n_ir ; i++) {
		ctx = &ohci->ir_context_list[i];
3099
		if (ctx->context.running)
3100 3101 3102 3103 3104
			ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
	}

	for (i = 0 ; i < ohci->n_it ; i++) {
		ctx = &ohci->it_context_list[i];
3105
		if (ctx->context.running)
3106 3107 3108 3109 3110
			ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
	}
}
#endif

3111 3112 3113 3114
static int queue_iso_transmit(struct iso_context *ctx,
			      struct fw_iso_packet *packet,
			      struct fw_iso_buffer *buffer,
			      unsigned long payload)
3115
{
3116
	struct descriptor *d, *last, *pd;
3117 3118
	struct fw_iso_packet *p;
	__le32 *header;
3119
	dma_addr_t d_bus, page_bus;
3120 3121
	u32 z, header_z, payload_z, irq;
	u32 payload_index, payload_end_index, next_page_index;
3122
	int page, end_page, i, length, offset;
3123 3124

	p = packet;
3125
	payload_index = payload;
3126 3127 3128 3129 3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143

	if (p->skip)
		z = 1;
	else
		z = 2;
	if (p->header_length > 0)
		z++;

	/* Determine the first page the payload isn't contained in. */
	end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
	if (p->payload_length > 0)
		payload_z = end_page - (payload_index >> PAGE_SHIFT);
	else
		payload_z = 0;

	z += payload_z;

	/* Get header size in number of descriptors. */
3144
	header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
3145

3146 3147 3148
	d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
	if (d == NULL)
		return -ENOMEM;
3149 3150

	if (!p->skip) {
3151
		d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
3152
		d[0].req_count = cpu_to_le16(8);
3153 3154 3155 3156 3157 3158 3159 3160
		/*
		 * Link the skip address to this descriptor itself.  This causes
		 * a context to skip a cycle whenever lost cycles or FIFO
		 * overruns occur, without dropping the data.  The application
		 * should then decide whether this is an error condition or not.
		 * FIXME:  Make the context's cycle-lost behaviour configurable?
		 */
		d[0].branch_address = cpu_to_le32(d_bus | z);
3161 3162

		header = (__le32 *) &d[1];
3163 3164 3165 3166 3167
		header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
					IT_HEADER_TAG(p->tag) |
					IT_HEADER_TCODE(TCODE_STREAM_DATA) |
					IT_HEADER_CHANNEL(ctx->base.channel) |
					IT_HEADER_SPEED(ctx->base.speed));
3168
		header[1] =
3169
			cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
3170 3171 3172 3173 3174
							  p->payload_length));
	}

	if (p->header_length > 0) {
		d[2].req_count    = cpu_to_le16(p->header_length);
3175
		d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
3176 3177 3178 3179 3180 3181 3182 3183 3184 3185 3186 3187
		memcpy(&d[z], p->header, p->header_length);
	}

	pd = d + z - payload_z;
	payload_end_index = payload_index + p->payload_length;
	for (i = 0; i < payload_z; i++) {
		page               = payload_index >> PAGE_SHIFT;
		offset             = payload_index & ~PAGE_MASK;
		next_page_index    = (page + 1) << PAGE_SHIFT;
		length             =
			min(next_page_index, payload_end_index) - payload_index;
		pd[i].req_count    = cpu_to_le16(length);
3188 3189 3190

		page_bus = page_private(buffer->pages[page]);
		pd[i].data_address = cpu_to_le32(page_bus + offset);
3191

3192 3193 3194 3195
		dma_sync_single_range_for_device(ctx->context.ohci->card.device,
						 page_bus, offset, length,
						 DMA_TO_DEVICE);

3196 3197 3198 3199
		payload_index += length;
	}

	if (p->interrupt)
3200
		irq = DESCRIPTOR_IRQ_ALWAYS;
3201
	else
3202
		irq = DESCRIPTOR_NO_IRQ;
3203

3204
	last = z == 2 ? d : d + z - 1;
3205 3206 3207
	last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
				     DESCRIPTOR_STATUS |
				     DESCRIPTOR_BRANCH_ALWAYS |
3208
				     irq);
3209

3210
	context_append(&ctx->context, d, z, header_z);
3211 3212 3213

	return 0;
}
S
Stefan Richter 已提交
3214

3215 3216 3217 3218
static int queue_iso_packet_per_buffer(struct iso_context *ctx,
				       struct fw_iso_packet *packet,
				       struct fw_iso_buffer *buffer,
				       unsigned long payload)
3219
{
3220
	struct device *device = ctx->context.ohci->card.device;
3221
	struct descriptor *d, *pd;
3222 3223
	dma_addr_t d_bus, page_bus;
	u32 z, header_z, rest;
3224 3225
	int i, j, length;
	int page, offset, packet_count, header_size, payload_per_buffer;
3226 3227

	/*
3228 3229
	 * The OHCI controller puts the isochronous header and trailer in the
	 * buffer, so we need at least 8 bytes.
3230
	 */
3231
	packet_count = packet->header_length / ctx->base.header_size;
3232
	header_size  = max(ctx->base.header_size, (size_t)8);
3233 3234 3235 3236 3237

	/* Get header size in number of descriptors. */
	header_z = DIV_ROUND_UP(header_size, sizeof(*d));
	page     = payload >> PAGE_SHIFT;
	offset   = payload & ~PAGE_MASK;
3238
	payload_per_buffer = packet->payload_length / packet_count;
3239 3240 3241

	for (i = 0; i < packet_count; i++) {
		/* d points to the header descriptor */
3242
		z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
3243
		d = context_get_descriptors(&ctx->context,
3244
				z + header_z, &d_bus);
3245 3246 3247
		if (d == NULL)
			return -ENOMEM;

3248 3249
		d->control      = cpu_to_le16(DESCRIPTOR_STATUS |
					      DESCRIPTOR_INPUT_MORE);
3250
		if (packet->skip && i == 0)
3251
			d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3252 3253
		d->req_count    = cpu_to_le16(header_size);
		d->res_count    = d->req_count;
3254
		d->transfer_status = 0;
3255 3256
		d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));

3257
		rest = payload_per_buffer;
3258
		pd = d;
3259
		for (j = 1; j < z; j++) {
3260
			pd++;
3261 3262 3263 3264 3265 3266 3267 3268 3269 3270 3271 3272 3273 3274
			pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
						  DESCRIPTOR_INPUT_MORE);

			if (offset + rest < PAGE_SIZE)
				length = rest;
			else
				length = PAGE_SIZE - offset;
			pd->req_count = cpu_to_le16(length);
			pd->res_count = pd->req_count;
			pd->transfer_status = 0;

			page_bus = page_private(buffer->pages[page]);
			pd->data_address = cpu_to_le32(page_bus + offset);

3275 3276 3277 3278
			dma_sync_single_range_for_device(device, page_bus,
							 offset, length,
							 DMA_FROM_DEVICE);

3279 3280 3281 3282 3283
			offset = (offset + length) & ~PAGE_MASK;
			rest -= length;
			if (offset == 0)
				page++;
		}
3284 3285 3286
		pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
					  DESCRIPTOR_INPUT_LAST |
					  DESCRIPTOR_BRANCH_ALWAYS);
3287
		if (packet->interrupt && i == packet_count - 1)
3288 3289 3290 3291 3292 3293 3294 3295
			pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);

		context_append(&ctx->context, d, z, header_z);
	}

	return 0;
}

3296 3297 3298 3299 3300 3301 3302 3303 3304 3305 3306 3307 3308 3309 3310 3311 3312 3313 3314 3315 3316 3317 3318 3319 3320 3321 3322 3323 3324 3325 3326 3327 3328 3329 3330 3331 3332 3333 3334 3335 3336 3337
static int queue_iso_buffer_fill(struct iso_context *ctx,
				 struct fw_iso_packet *packet,
				 struct fw_iso_buffer *buffer,
				 unsigned long payload)
{
	struct descriptor *d;
	dma_addr_t d_bus, page_bus;
	int page, offset, rest, z, i, length;

	page   = payload >> PAGE_SHIFT;
	offset = payload & ~PAGE_MASK;
	rest   = packet->payload_length;

	/* We need one descriptor for each page in the buffer. */
	z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);

	if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
		return -EFAULT;

	for (i = 0; i < z; i++) {
		d = context_get_descriptors(&ctx->context, 1, &d_bus);
		if (d == NULL)
			return -ENOMEM;

		d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
					 DESCRIPTOR_BRANCH_ALWAYS);
		if (packet->skip && i == 0)
			d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
		if (packet->interrupt && i == z - 1)
			d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);

		if (offset + rest < PAGE_SIZE)
			length = rest;
		else
			length = PAGE_SIZE - offset;
		d->req_count = cpu_to_le16(length);
		d->res_count = d->req_count;
		d->transfer_status = 0;

		page_bus = page_private(buffer->pages[page]);
		d->data_address = cpu_to_le32(page_bus + offset);

3338 3339 3340 3341
		dma_sync_single_range_for_device(ctx->context.ohci->card.device,
						 page_bus, offset, length,
						 DMA_FROM_DEVICE);

3342 3343 3344 3345 3346 3347 3348 3349 3350 3351
		rest -= length;
		offset = 0;
		page++;

		context_append(&ctx->context, d, 1, 0);
	}

	return 0;
}

3352 3353 3354 3355
static int ohci_queue_iso(struct fw_iso_context *base,
			  struct fw_iso_packet *packet,
			  struct fw_iso_buffer *buffer,
			  unsigned long payload)
3356
{
3357
	struct iso_context *ctx = container_of(base, struct iso_context, base);
3358
	unsigned long flags;
3359
	int ret = -ENOSYS;
3360

3361
	spin_lock_irqsave(&ctx->context.ohci->lock, flags);
3362 3363 3364 3365 3366 3367 3368 3369 3370 3371 3372
	switch (base->type) {
	case FW_ISO_CONTEXT_TRANSMIT:
		ret = queue_iso_transmit(ctx, packet, buffer, payload);
		break;
	case FW_ISO_CONTEXT_RECEIVE:
		ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
		break;
	case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
		ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
		break;
	}
3373 3374
	spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);

3375
	return ret;
3376 3377
}

3378 3379 3380 3381 3382 3383 3384 3385
static void ohci_flush_queue_iso(struct fw_iso_context *base)
{
	struct context *ctx =
			&container_of(base, struct iso_context, base)->context;

	reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
}

3386
static const struct fw_card_driver ohci_driver = {
3387
	.enable			= ohci_enable,
3388
	.read_phy_reg		= ohci_read_phy_reg,
3389 3390 3391 3392
	.update_phy_reg		= ohci_update_phy_reg,
	.set_config_rom		= ohci_set_config_rom,
	.send_request		= ohci_send_request,
	.send_response		= ohci_send_response,
3393
	.cancel_packet		= ohci_cancel_packet,
3394
	.enable_phys_dma	= ohci_enable_phys_dma,
3395 3396
	.read_csr		= ohci_read_csr,
	.write_csr		= ohci_write_csr,
3397 3398 3399

	.allocate_iso_context	= ohci_allocate_iso_context,
	.free_iso_context	= ohci_free_iso_context,
3400
	.set_iso_channels	= ohci_set_iso_channels,
3401
	.queue_iso		= ohci_queue_iso,
3402
	.flush_queue_iso	= ohci_flush_queue_iso,
3403
	.start_iso		= ohci_start_iso,
3404
	.stop_iso		= ohci_stop_iso,
3405 3406
};

3407
#ifdef CONFIG_PPC_PMAC
3408
static void pmac_ohci_on(struct pci_dev *dev)
3409
{
3410 3411 3412 3413 3414 3415 3416 3417
	if (machine_is(powermac)) {
		struct device_node *ofn = pci_device_to_OF_node(dev);

		if (ofn) {
			pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
			pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
		}
	}
3418 3419
}

3420
static void pmac_ohci_off(struct pci_dev *dev)
3421 3422 3423 3424 3425 3426 3427 3428 3429 3430 3431
{
	if (machine_is(powermac)) {
		struct device_node *ofn = pci_device_to_OF_node(dev);

		if (ofn) {
			pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
			pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
		}
	}
}
#else
3432 3433
static inline void pmac_ohci_on(struct pci_dev *dev) {}
static inline void pmac_ohci_off(struct pci_dev *dev) {}
3434 3435
#endif /* CONFIG_PPC_PMAC */

3436 3437
static int __devinit pci_probe(struct pci_dev *dev,
			       const struct pci_device_id *ent)
3438 3439
{
	struct fw_ohci *ohci;
3440
	u32 bus_options, max_receive, link_speed, version;
3441
	u64 guid;
3442
	int i, err;
3443 3444
	size_t size;

3445 3446 3447 3448 3449
	if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) {
		dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n");
		return -ENOSYS;
	}

3450
	ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
3451
	if (ohci == NULL) {
3452 3453
		err = -ENOMEM;
		goto fail;
3454 3455 3456 3457
	}

	fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);

3458
	pmac_ohci_on(dev);
3459

3460 3461
	err = pci_enable_device(dev);
	if (err) {
3462
		fw_error("Failed to enable OHCI hardware\n");
3463
		goto fail_free;
3464 3465 3466 3467 3468 3469 3470
	}

	pci_set_master(dev);
	pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
	pci_set_drvdata(dev, ohci);

	spin_lock_init(&ohci->lock);
3471
	mutex_init(&ohci->phy_reg_mutex);
3472

3473
	INIT_WORK(&ohci->bus_reset_work, bus_reset_work);
3474

3475 3476
	err = pci_request_region(dev, 0, ohci_driver_name);
	if (err) {
3477
		fw_error("MMIO resource unavailable\n");
3478
		goto fail_disable;
3479 3480 3481 3482 3483
	}

	ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
	if (ohci->registers == NULL) {
		fw_error("Failed to remap registers\n");
3484 3485
		err = -ENXIO;
		goto fail_iomem;
3486 3487
	}

3488
	for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
3489 3490 3491 3492 3493
		if ((ohci_quirks[i].vendor == dev->vendor) &&
		    (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
		     ohci_quirks[i].device == dev->device) &&
		    (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
		     ohci_quirks[i].revision >= dev->revision)) {
3494 3495 3496
			ohci->quirks = ohci_quirks[i].flags;
			break;
		}
3497 3498
	if (param_quirks)
		ohci->quirks = param_quirks;
3499

3500 3501 3502 3503 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516
	/*
	 * Because dma_alloc_coherent() allocates at least one page,
	 * we save space by using a common buffer for the AR request/
	 * response descriptors and the self IDs buffer.
	 */
	BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
	BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
	ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
					       PAGE_SIZE,
					       &ohci->misc_buffer_bus,
					       GFP_KERNEL);
	if (!ohci->misc_buffer) {
		err = -ENOMEM;
		goto fail_iounmap;
	}

	err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
3517 3518
			      OHCI1394_AsReqRcvContextControlSet);
	if (err < 0)
3519
		goto fail_misc_buf;
3520

3521
	err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
3522 3523 3524
			      OHCI1394_AsRspRcvContextControlSet);
	if (err < 0)
		goto fail_arreq_ctx;
3525

3526 3527 3528 3529
	err = context_init(&ohci->at_request_ctx, ohci,
			   OHCI1394_AsReqTrContextControlSet, handle_at_packet);
	if (err < 0)
		goto fail_arrsp_ctx;
3530

3531 3532 3533 3534
	err = context_init(&ohci->at_response_ctx, ohci,
			   OHCI1394_AsRspTrContextControlSet, handle_at_packet);
	if (err < 0)
		goto fail_atreq_ctx;
3535 3536

	reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
3537
	ohci->ir_context_channels = ~0ULL;
3538
	ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
3539
	reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
3540
	ohci->ir_context_mask = ohci->ir_context_support;
3541 3542
	ohci->n_ir = hweight32(ohci->ir_context_mask);
	size = sizeof(struct iso_context) * ohci->n_ir;
3543
	ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
3544 3545

	reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
3546
	ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
3547
	reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
3548
	ohci->it_context_mask = ohci->it_context_support;
3549 3550
	ohci->n_it = hweight32(ohci->it_context_mask);
	size = sizeof(struct iso_context) * ohci->n_it;
3551
	ohci->it_context_list = kzalloc(size, GFP_KERNEL);
3552 3553

	if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
3554
		err = -ENOMEM;
3555
		goto fail_contexts;
3556 3557
	}

3558 3559
	ohci->self_id_cpu = ohci->misc_buffer     + PAGE_SIZE/2;
	ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
3560 3561 3562 3563 3564 3565 3566

	bus_options = reg_read(ohci, OHCI1394_BusOptions);
	max_receive = (bus_options >> 12) & 0xf;
	link_speed = bus_options & 0x7;
	guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
		reg_read(ohci, OHCI1394_GUIDLo);

3567
	err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
3568
	if (err)
3569
		goto fail_contexts;
3570

3571 3572 3573 3574
	version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
	fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
		  "%d IR + %d IT contexts, quirks 0x%x\n",
		  dev_name(&dev->dev), version >> 16, version & 0xff,
3575
		  ohci->n_ir, ohci->n_it, ohci->quirks);
3576

3577
	return 0;
3578

3579
 fail_contexts:
3580
	kfree(ohci->ir_context_list);
3581 3582
	kfree(ohci->it_context_list);
	context_release(&ohci->at_response_ctx);
3583
 fail_atreq_ctx:
3584
	context_release(&ohci->at_request_ctx);
3585
 fail_arrsp_ctx:
3586
	ar_context_release(&ohci->ar_response_ctx);
3587
 fail_arreq_ctx:
3588
	ar_context_release(&ohci->ar_request_ctx);
3589 3590 3591
 fail_misc_buf:
	dma_free_coherent(ohci->card.device, PAGE_SIZE,
			  ohci->misc_buffer, ohci->misc_buffer_bus);
3592
 fail_iounmap:
3593 3594 3595 3596 3597
	pci_iounmap(dev, ohci->registers);
 fail_iomem:
	pci_release_region(dev, 0);
 fail_disable:
	pci_disable_device(dev);
3598
 fail_free:
3599
	kfree(ohci);
3600
	pmac_ohci_off(dev);
3601 3602 3603
 fail:
	if (err == -ENOMEM)
		fw_error("Out of memory\n");
3604 3605

	return err;
3606 3607 3608 3609 3610 3611 3612
}

static void pci_remove(struct pci_dev *dev)
{
	struct fw_ohci *ohci;

	ohci = pci_get_drvdata(dev);
3613 3614
	reg_write(ohci, OHCI1394_IntMaskClear, ~0);
	flush_writes(ohci);
3615
	cancel_work_sync(&ohci->bus_reset_work);
3616 3617
	fw_core_remove_card(&ohci->card);

3618 3619 3620 3621
	/*
	 * FIXME: Fail all pending packets here, now that the upper
	 * layers can't queue any more.
	 */
3622 3623 3624

	software_reset(ohci);
	free_irq(dev->irq, ohci);
3625 3626 3627 3628 3629 3630 3631 3632 3633

	if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
		dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
				  ohci->next_config_rom, ohci->next_config_rom_bus);
	if (ohci->config_rom)
		dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
				  ohci->config_rom, ohci->config_rom_bus);
	ar_context_release(&ohci->ar_request_ctx);
	ar_context_release(&ohci->ar_response_ctx);
3634 3635
	dma_free_coherent(ohci->card.device, PAGE_SIZE,
			  ohci->misc_buffer, ohci->misc_buffer_bus);
3636 3637
	context_release(&ohci->at_request_ctx);
	context_release(&ohci->at_response_ctx);
3638 3639
	kfree(ohci->it_context_list);
	kfree(ohci->ir_context_list);
3640
	pci_disable_msi(dev);
3641 3642 3643
	pci_iounmap(dev, ohci->registers);
	pci_release_region(dev, 0);
	pci_disable_device(dev);
3644
	kfree(ohci);
3645
	pmac_ohci_off(dev);
3646

3647 3648 3649
	fw_notify("Removed fw-ohci device.\n");
}

3650
#ifdef CONFIG_PM
3651
static int pci_suspend(struct pci_dev *dev, pm_message_t state)
3652
{
3653
	struct fw_ohci *ohci = pci_get_drvdata(dev);
3654 3655 3656
	int err;

	software_reset(ohci);
3657
	free_irq(dev->irq, ohci);
3658
	pci_disable_msi(dev);
3659
	err = pci_save_state(dev);
3660
	if (err) {
3661
		fw_error("pci_save_state failed\n");
3662 3663
		return err;
	}
3664
	err = pci_set_power_state(dev, pci_choose_state(dev, state));
3665 3666
	if (err)
		fw_error("pci_set_power_state failed with %d\n", err);
3667
	pmac_ohci_off(dev);
3668

3669 3670 3671
	return 0;
}

3672
static int pci_resume(struct pci_dev *dev)
3673
{
3674
	struct fw_ohci *ohci = pci_get_drvdata(dev);
3675 3676
	int err;

3677
	pmac_ohci_on(dev);
3678 3679 3680
	pci_set_power_state(dev, PCI_D0);
	pci_restore_state(dev);
	err = pci_enable_device(dev);
3681
	if (err) {
3682
		fw_error("pci_enable_device failed\n");
3683 3684 3685
		return err;
	}

3686 3687 3688 3689 3690 3691 3692
	/* Some systems don't setup GUID register on resume from ram  */
	if (!reg_read(ohci, OHCI1394_GUIDLo) &&
					!reg_read(ohci, OHCI1394_GUIDHi)) {
		reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
		reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
	}

3693 3694 3695 3696 3697
	err = ohci_enable(&ohci->card, NULL, 0);
	if (err)
		return err;

	ohci_resume_iso_dma(ohci);
3698

3699
	return 0;
3700 3701 3702
}
#endif

3703
static const struct pci_device_id pci_table[] = {
3704 3705 3706 3707 3708 3709 3710 3711 3712 3713 3714
	{ PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
	{ }
};

MODULE_DEVICE_TABLE(pci, pci_table);

static struct pci_driver fw_ohci_pci_driver = {
	.name		= ohci_driver_name,
	.id_table	= pci_table,
	.probe		= pci_probe,
	.remove		= pci_remove,
3715 3716 3717 3718
#ifdef CONFIG_PM
	.resume		= pci_resume,
	.suspend	= pci_suspend,
#endif
3719 3720 3721 3722 3723 3724
};

MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
MODULE_LICENSE("GPL");

3725 3726 3727 3728 3729
/* Provide a module alias so root-on-sbp2 initrds don't break. */
#ifndef CONFIG_IEEE1394_OHCI1394_MODULE
MODULE_ALIAS("ohci1394");
#endif

3730 3731 3732 3733 3734 3735 3736 3737 3738 3739 3740 3741
static int __init fw_ohci_init(void)
{
	return pci_register_driver(&fw_ohci_pci_driver);
}

static void __exit fw_ohci_cleanup(void)
{
	pci_unregister_driver(&fw_ohci_pci_driver);
}

module_init(fw_ohci_init);
module_exit(fw_ohci_cleanup);