hw.c 80.8 KB
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/*
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 * Copyright (c) 2008-2011 Atheros Communications Inc.
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 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <asm/unaligned.h>

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#include "hw.h"
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#include "hw-ops.h"
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#include "rc.h"
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#include "ar9003_mac.h"
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#include "ar9003_mci.h"
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#include "debug.h"
#include "ath9k.h"
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static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
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MODULE_AUTHOR("Atheros Communications");
MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
MODULE_LICENSE("Dual BSD/GPL");

static int __init ath9k_init(void)
{
	return 0;
}
module_init(ath9k_init);

static void __exit ath9k_exit(void)
{
	return;
}
module_exit(ath9k_exit);

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/* Private hardware callbacks */

static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
{
	ath9k_hw_private_ops(ah)->init_cal_settings(ah);
}

static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
{
	ath9k_hw_private_ops(ah)->init_mode_regs(ah);
}

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static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
					struct ath9k_channel *chan)
{
	return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
}

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static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
{
	if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
		return;

	ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
}

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static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
{
	/* You will not have this callback if using the old ANI */
	if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
		return;

	ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
}

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/********************/
/* Helper Functions */
/********************/
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#ifdef CONFIG_ATH9K_DEBUGFS

void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause)
{
	struct ath_softc *sc = common->priv;
	if (sync_cause)
		sc->debug.stats.istats.sync_cause_all++;
	if (sync_cause & AR_INTR_SYNC_RTC_IRQ)
		sc->debug.stats.istats.sync_rtc_irq++;
	if (sync_cause & AR_INTR_SYNC_MAC_IRQ)
		sc->debug.stats.istats.sync_mac_irq++;
	if (sync_cause & AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS)
		sc->debug.stats.istats.eeprom_illegal_access++;
	if (sync_cause & AR_INTR_SYNC_APB_TIMEOUT)
		sc->debug.stats.istats.apb_timeout++;
	if (sync_cause & AR_INTR_SYNC_PCI_MODE_CONFLICT)
		sc->debug.stats.istats.pci_mode_conflict++;
	if (sync_cause & AR_INTR_SYNC_HOST1_FATAL)
		sc->debug.stats.istats.host1_fatal++;
	if (sync_cause & AR_INTR_SYNC_HOST1_PERR)
		sc->debug.stats.istats.host1_perr++;
	if (sync_cause & AR_INTR_SYNC_TRCV_FIFO_PERR)
		sc->debug.stats.istats.trcv_fifo_perr++;
	if (sync_cause & AR_INTR_SYNC_RADM_CPL_EP)
		sc->debug.stats.istats.radm_cpl_ep++;
	if (sync_cause & AR_INTR_SYNC_RADM_CPL_DLLP_ABORT)
		sc->debug.stats.istats.radm_cpl_dllp_abort++;
	if (sync_cause & AR_INTR_SYNC_RADM_CPL_TLP_ABORT)
		sc->debug.stats.istats.radm_cpl_tlp_abort++;
	if (sync_cause & AR_INTR_SYNC_RADM_CPL_ECRC_ERR)
		sc->debug.stats.istats.radm_cpl_ecrc_err++;
	if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT)
		sc->debug.stats.istats.radm_cpl_timeout++;
	if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
		sc->debug.stats.istats.local_timeout++;
	if (sync_cause & AR_INTR_SYNC_PM_ACCESS)
		sc->debug.stats.istats.pm_access++;
	if (sync_cause & AR_INTR_SYNC_MAC_AWAKE)
		sc->debug.stats.istats.mac_awake++;
	if (sync_cause & AR_INTR_SYNC_MAC_ASLEEP)
		sc->debug.stats.istats.mac_asleep++;
	if (sync_cause & AR_INTR_SYNC_MAC_SLEEP_ACCESS)
		sc->debug.stats.istats.mac_sleep_access++;
}
#endif


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static void ath9k_hw_set_clockrate(struct ath_hw *ah)
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{
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	struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
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	struct ath_common *common = ath9k_hw_common(ah);
	unsigned int clockrate;
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	/* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
	if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
		clockrate = 117;
	else if (!ah->curchan) /* should really check for CCK instead */
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		clockrate = ATH9K_CLOCK_RATE_CCK;
	else if (conf->channel->band == IEEE80211_BAND_2GHZ)
		clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
	else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
		clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
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	else
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		clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;

	if (conf_is_ht40(conf))
		clockrate *= 2;

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	if (ah->curchan) {
		if (IS_CHAN_HALF_RATE(ah->curchan))
			clockrate /= 2;
		if (IS_CHAN_QUARTER_RATE(ah->curchan))
			clockrate /= 4;
	}

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	common->clockrate = clockrate;
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}

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static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
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{
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	struct ath_common *common = ath9k_hw_common(ah);
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	return usecs * common->clockrate;
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}
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bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
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{
	int i;

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	BUG_ON(timeout < AH_TIME_QUANTUM);

	for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
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		if ((REG_READ(ah, reg) & mask) == val)
			return true;

		udelay(AH_TIME_QUANTUM);
	}
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	ath_dbg(ath9k_hw_common(ah), ANY,
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		"timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
		timeout, reg, REG_READ(ah, reg), mask, val);
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	return false;
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}
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EXPORT_SYMBOL(ath9k_hw_wait);
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void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
			  int hw_delay)
{
	if (IS_CHAN_B(chan))
		hw_delay = (4 * hw_delay) / 22;
	else
		hw_delay /= 10;

	if (IS_CHAN_HALF_RATE(chan))
		hw_delay *= 2;
	else if (IS_CHAN_QUARTER_RATE(chan))
		hw_delay *= 4;

	udelay(hw_delay + BASE_ACTIVATE_DELAY);
}

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void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
			  int column, unsigned int *writecnt)
{
	int r;

	ENABLE_REGWRITE_BUFFER(ah);
	for (r = 0; r < array->ia_rows; r++) {
		REG_WRITE(ah, INI_RA(array, r, 0),
			  INI_RA(array, r, column));
		DO_DELAY(*writecnt);
	}
	REGWRITE_BUFFER_FLUSH(ah);
}

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u32 ath9k_hw_reverse_bits(u32 val, u32 n)
{
	u32 retval;
	int i;

	for (i = 0, retval = 0; i < n; i++) {
		retval = (retval << 1) | (val & 1);
		val >>= 1;
	}
	return retval;
}

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u16 ath9k_hw_computetxtime(struct ath_hw *ah,
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			   u8 phy, int kbps,
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			   u32 frameLen, u16 rateix,
			   bool shortPreamble)
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{
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	u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
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	if (kbps == 0)
		return 0;
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	switch (phy) {
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	case WLAN_RC_PHY_CCK:
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		phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
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		if (shortPreamble)
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			phyTime >>= 1;
		numBits = frameLen << 3;
		txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
		break;
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	case WLAN_RC_PHY_OFDM:
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		if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
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			bitsPerSymbol =	(kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
			numBits = OFDM_PLCP_BITS + (frameLen << 3);
			numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
			txTime = OFDM_SIFS_TIME_QUARTER
				+ OFDM_PREAMBLE_TIME_QUARTER
				+ (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
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		} else if (ah->curchan &&
			   IS_CHAN_HALF_RATE(ah->curchan)) {
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			bitsPerSymbol =	(kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
			numBits = OFDM_PLCP_BITS + (frameLen << 3);
			numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
			txTime = OFDM_SIFS_TIME_HALF +
				OFDM_PREAMBLE_TIME_HALF
				+ (numSymbols * OFDM_SYMBOL_TIME_HALF);
		} else {
			bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
			numBits = OFDM_PLCP_BITS + (frameLen << 3);
			numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
			txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
				+ (numSymbols * OFDM_SYMBOL_TIME);
		}
		break;
	default:
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		ath_err(ath9k_hw_common(ah),
			"Unknown phy %u (rate ix %u)\n", phy, rateix);
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		txTime = 0;
		break;
	}
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	return txTime;
}
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EXPORT_SYMBOL(ath9k_hw_computetxtime);
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void ath9k_hw_get_channel_centers(struct ath_hw *ah,
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				  struct ath9k_channel *chan,
				  struct chan_centers *centers)
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{
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	int8_t extoff;
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	if (!IS_CHAN_HT40(chan)) {
		centers->ctl_center = centers->ext_center =
			centers->synth_center = chan->channel;
		return;
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	}

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	if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
	    (chan->chanmode == CHANNEL_G_HT40PLUS)) {
		centers->synth_center =
			chan->channel + HT40_CHANNEL_CENTER_SHIFT;
		extoff = 1;
	} else {
		centers->synth_center =
			chan->channel - HT40_CHANNEL_CENTER_SHIFT;
		extoff = -1;
	}
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	centers->ctl_center =
		centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
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	/* 25 MHz spacing is supported by hw but not on upper layers */
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	centers->ext_center =
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		centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
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}

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/******************/
/* Chip Revisions */
/******************/

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static void ath9k_hw_read_revisions(struct ath_hw *ah)
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{
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	u32 val;
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	switch (ah->hw_version.devid) {
	case AR5416_AR9100_DEVID:
		ah->hw_version.macVersion = AR_SREV_VERSION_9100;
		break;
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	case AR9300_DEVID_AR9330:
		ah->hw_version.macVersion = AR_SREV_VERSION_9330;
		if (ah->get_mac_revision) {
			ah->hw_version.macRev = ah->get_mac_revision();
		} else {
			val = REG_READ(ah, AR_SREV);
			ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
		}
		return;
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	case AR9300_DEVID_AR9340:
		ah->hw_version.macVersion = AR_SREV_VERSION_9340;
		val = REG_READ(ah, AR_SREV);
		ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
		return;
	}

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	val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
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	if (val == 0xFF) {
		val = REG_READ(ah, AR_SREV);
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		ah->hw_version.macVersion =
			(val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
		ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
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		if (AR_SREV_9462(ah))
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			ah->is_pciexpress = true;
		else
			ah->is_pciexpress = (val &
					     AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
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	} else {
		if (!AR_SREV_9100(ah))
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			ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
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		ah->hw_version.macRev = val & AR_SREV_REVISION;
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		if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
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			ah->is_pciexpress = true;
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	}
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}

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/************************************/
/* HW Attach, Detach, Init Routines */
/************************************/

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static void ath9k_hw_disablepcie(struct ath_hw *ah)
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{
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	if (!AR_SREV_5416(ah))
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		return;
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	REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
	REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
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	REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
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}

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/* This should work for all families including legacy */
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static bool ath9k_hw_chip_test(struct ath_hw *ah)
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{
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	struct ath_common *common = ath9k_hw_common(ah);
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	u32 regAddr[2] = { AR_STA_ID0 };
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	u32 regHold[2];
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	static const u32 patternData[4] = {
		0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
	};
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	int i, j, loop_max;
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	if (!AR_SREV_9300_20_OR_LATER(ah)) {
		loop_max = 2;
		regAddr[1] = AR_PHY_BASE + (8 << 2);
	} else
		loop_max = 1;

	for (i = 0; i < loop_max; i++) {
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		u32 addr = regAddr[i];
		u32 wrData, rdData;
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		regHold[i] = REG_READ(ah, addr);
		for (j = 0; j < 0x100; j++) {
			wrData = (j << 16) | j;
			REG_WRITE(ah, addr, wrData);
			rdData = REG_READ(ah, addr);
			if (rdData != wrData) {
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				ath_err(common,
					"address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
					addr, wrData, rdData);
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				return false;
			}
		}
		for (j = 0; j < 4; j++) {
			wrData = patternData[j];
			REG_WRITE(ah, addr, wrData);
			rdData = REG_READ(ah, addr);
			if (wrData != rdData) {
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				ath_err(common,
					"address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
					addr, wrData, rdData);
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				return false;
			}
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		}
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		REG_WRITE(ah, regAddr[i], regHold[i]);
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	}
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	udelay(100);
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	return true;
}

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static void ath9k_hw_init_config(struct ath_hw *ah)
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{
	int i;
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	ah->config.dma_beacon_response_time = 1;
	ah->config.sw_beacon_response_time = 6;
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	ah->config.additional_swba_backoff = 0;
	ah->config.ack_6mb = 0x0;
	ah->config.cwm_ignore_extcca = 0;
	ah->config.pcie_clock_req = 0;
	ah->config.pcie_waen = 0;
	ah->config.analog_shiftreg = 1;
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	ah->config.enable_ani = true;
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	for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
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		ah->config.spurchans[i][0] = AR_NO_SPUR;
		ah->config.spurchans[i][1] = AR_NO_SPUR;
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	}

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	/* PAPRD needs some more work to be enabled */
	ah->config.paprd_disable = 1;

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	ah->config.rx_intr_mitigation = true;
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	ah->config.pcieSerDesWrite = true;
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	/*
	 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
	 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
	 * This means we use it for all AR5416 devices, and the few
	 * minor PCI AR9280 devices out there.
	 *
	 * Serialization is required because these devices do not handle
	 * well the case of two concurrent reads/writes due to the latency
	 * involved. During one read/write another read/write can be issued
	 * on another CPU while the previous read/write may still be working
	 * on our hardware, if we hit this case the hardware poops in a loop.
	 * We prevent this by serializing reads and writes.
	 *
	 * This issue is not present on PCI-Express devices or pre-AR5416
	 * devices (legacy, 802.11abg).
	 */
	if (num_possible_cpus() > 1)
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		ah->config.serialize_regmode = SER_REG_MODE_AUTO;
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}

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static void ath9k_hw_init_defaults(struct ath_hw *ah)
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{
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	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);

	regulatory->country_code = CTRY_DEFAULT;
	regulatory->power_limit = MAX_RATE_POWER;

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	ah->hw_version.magic = AR5416_MAGIC;
	ah->hw_version.subvendorid = 0;
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	ah->atim_window = 0;
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	ah->sta_id1_defaults =
		AR_STA_ID1_CRPT_MIC_ENABLE |
		AR_STA_ID1_MCAST_KSRCH;
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	if (AR_SREV_9100(ah))
		ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
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	ah->slottime = ATH9K_SLOT_TIME_9;
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	ah->globaltxtimeout = (u32) -1;
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	ah->power_mode = ATH9K_PM_UNDEFINED;
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	ah->htc_reset_init = true;
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}

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static int ath9k_hw_init_macaddr(struct ath_hw *ah)
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{
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	struct ath_common *common = ath9k_hw_common(ah);
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	u32 sum;
	int i;
	u16 eeval;
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	static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
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	sum = 0;
	for (i = 0; i < 3; i++) {
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		eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
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		sum += eeval;
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		common->macaddr[2 * i] = eeval >> 8;
		common->macaddr[2 * i + 1] = eeval & 0xff;
525
	}
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	if (sum == 0 || sum == 0xffff * 3)
527 528 529 530 531
		return -EADDRNOTAVAIL;

	return 0;
}

532
static int ath9k_hw_post_init(struct ath_hw *ah)
533
{
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534
	struct ath_common *common = ath9k_hw_common(ah);
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535
	int ecode;
536

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537
	if (common->bus_ops->ath_bus_type != ATH_USB) {
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538 539 540
		if (!ath9k_hw_chip_test(ah))
			return -ENODEV;
	}
541

542 543 544 545 546
	if (!AR_SREV_9300_20_OR_LATER(ah)) {
		ecode = ar9002_hw_rf_claim(ah);
		if (ecode != 0)
			return ecode;
	}
547

548
	ecode = ath9k_hw_eeprom_init(ah);
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549 550
	if (ecode != 0)
		return ecode;
551

552
	ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
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		ah->eep_ops->get_eeprom_ver(ah),
		ah->eep_ops->get_eeprom_rev(ah));
555

556 557
	ecode = ath9k_hw_rf_alloc_ext_banks(ah);
	if (ecode) {
558 559
		ath_err(ath9k_hw_common(ah),
			"Failed allocating banks for external radio\n");
560
		ath9k_hw_rf_free_ext_banks(ah);
561
		return ecode;
562
	}
563

564
	if (ah->config.enable_ani) {
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		ath9k_hw_ani_setup(ah);
566
		ath9k_hw_ani_init(ah);
567 568 569 570 571
	}

	return 0;
}

572
static void ath9k_hw_attach_ops(struct ath_hw *ah)
573
{
574 575 576 577
	if (AR_SREV_9300_20_OR_LATER(ah))
		ar9003_hw_attach_ops(ah);
	else
		ar9002_hw_attach_ops(ah);
578 579
}

580 581
/* Called for all hardware families */
static int __ath9k_hw_init(struct ath_hw *ah)
582
{
583
	struct ath_common *common = ath9k_hw_common(ah);
584
	int r = 0;
585

586 587
	ath9k_hw_read_revisions(ah);

588 589 590 591 592 593 594 595 596
	/*
	 * Read back AR_WA into a permanent copy and set bits 14 and 17.
	 * We need to do this to avoid RMW of this register. We cannot
	 * read the reg when chip is asleep.
	 */
	ah->WARegVal = REG_READ(ah, AR_WA);
	ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
			 AR_WA_ASPM_TIMER_BASED_DISABLE);

597
	if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
598
		ath_err(common, "Couldn't reset chip\n");
599
		return -EIO;
600 601
	}

602
	if (AR_SREV_9462(ah))
603 604
		ah->WARegVal &= ~AR_WA_D3_L1_DISABLE;

605 606 607
	ath9k_hw_init_defaults(ah);
	ath9k_hw_init_config(ah);

608
	ath9k_hw_attach_ops(ah);
609

610
	if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
611
		ath_err(common, "Couldn't wakeup chip\n");
612
		return -EIO;
613 614
	}

615
	if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
616
		if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
617 618
		    ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
		     !ah->is_pciexpress)) {
619 620 621 622 623 624 625 626
			ah->config.serialize_regmode =
				SER_REG_MODE_ON;
		} else {
			ah->config.serialize_regmode =
				SER_REG_MODE_OFF;
		}
	}

627
	ath_dbg(common, RESET, "serialize_regmode is %d\n",
628 629
		ah->config.serialize_regmode);

630 631 632 633 634
	if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
		ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
	else
		ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;

635 636 637 638 639 640 641 642 643 644
	switch (ah->hw_version.macVersion) {
	case AR_SREV_VERSION_5416_PCI:
	case AR_SREV_VERSION_5416_PCIE:
	case AR_SREV_VERSION_9160:
	case AR_SREV_VERSION_9100:
	case AR_SREV_VERSION_9280:
	case AR_SREV_VERSION_9285:
	case AR_SREV_VERSION_9287:
	case AR_SREV_VERSION_9271:
	case AR_SREV_VERSION_9300:
645
	case AR_SREV_VERSION_9330:
646
	case AR_SREV_VERSION_9485:
647
	case AR_SREV_VERSION_9340:
648
	case AR_SREV_VERSION_9462:
649 650
		break;
	default:
651 652 653
		ath_err(common,
			"Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
			ah->hw_version.macVersion, ah->hw_version.macRev);
654
		return -EOPNOTSUPP;
655 656
	}

657 658
	if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
	    AR_SREV_9330(ah))
659 660
		ah->is_pciexpress = false;

661 662 663 664
	ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
	ath9k_hw_init_cal_settings(ah);

	ah->ani_function = ATH9K_ANI_ALL;
665
	if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
666
		ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
667 668
	if (!AR_SREV_9300_20_OR_LATER(ah))
		ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
669

670 671
	/* disable ANI for 9340 */
	if (AR_SREV_9340(ah))
672 673
		ah->config.enable_ani = false;

674 675
	ath9k_hw_init_mode_regs(ah);

676
	if (!ah->is_pciexpress)
677 678
		ath9k_hw_disablepcie(ah);

679
	r = ath9k_hw_post_init(ah);
680
	if (r)
681
		return r;
682 683

	ath9k_hw_init_mode_gain_regs(ah);
684 685 686 687
	r = ath9k_hw_fill_cap_info(ah);
	if (r)
		return r;

688 689
	r = ath9k_hw_init_macaddr(ah);
	if (r) {
690
		ath_err(common, "Failed to initialize MAC address\n");
691
		return r;
692 693
	}

694
	if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
695
		ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
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696
	else
697
		ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
698

699 700 701 702
	if (AR_SREV_9330(ah))
		ah->bb_watchdog_timeout_ms = 85;
	else
		ah->bb_watchdog_timeout_ms = 25;
703

704 705
	common->state = ATH_HW_INITIALIZED;

706
	return 0;
707 708
}

709
int ath9k_hw_init(struct ath_hw *ah)
710
{
711 712
	int ret;
	struct ath_common *common = ath9k_hw_common(ah);
713

714 715 716 717 718 719 720 721 722
	/* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
	switch (ah->hw_version.devid) {
	case AR5416_DEVID_PCI:
	case AR5416_DEVID_PCIE:
	case AR5416_AR9100_DEVID:
	case AR9160_DEVID_PCI:
	case AR9280_DEVID_PCI:
	case AR9280_DEVID_PCIE:
	case AR9285_DEVID_PCIE:
723 724
	case AR9287_DEVID_PCI:
	case AR9287_DEVID_PCIE:
725
	case AR2427_DEVID_PCIE:
726
	case AR9300_DEVID_PCIE:
727
	case AR9300_DEVID_AR9485_PCIE:
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728
	case AR9300_DEVID_AR9330:
729
	case AR9300_DEVID_AR9340:
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730
	case AR9300_DEVID_AR9580:
731
	case AR9300_DEVID_AR9462:
732 733 734 735
		break;
	default:
		if (common->bus_ops->ath_bus_type == ATH_USB)
			break;
736 737
		ath_err(common, "Hardware device ID 0x%04x not supported\n",
			ah->hw_version.devid);
738 739
		return -EOPNOTSUPP;
	}
740

741 742
	ret = __ath9k_hw_init(ah);
	if (ret) {
743 744 745
		ath_err(common,
			"Unable to initialize hardware; initialization status: %d\n",
			ret);
746 747
		return ret;
	}
748

749
	return 0;
750
}
751
EXPORT_SYMBOL(ath9k_hw_init);
752

753
static void ath9k_hw_init_qos(struct ath_hw *ah)
754
{
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755 756
	ENABLE_REGWRITE_BUFFER(ah);

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757 758
	REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
	REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
759

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760 761 762 763 764 765 766 767 768 769
	REG_WRITE(ah, AR_QOS_NO_ACK,
		  SM(2, AR_QOS_NO_ACK_TWO_BIT) |
		  SM(5, AR_QOS_NO_ACK_BIT_OFF) |
		  SM(0, AR_QOS_NO_ACK_BYTE_OFF));

	REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
	REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
	REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
	REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
	REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
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770 771

	REGWRITE_BUFFER_FLUSH(ah);
772 773
}

774
u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
775
{
776 777 778
	REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
	udelay(100);
	REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
779

780 781
	while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
		udelay(100);
782

783
	return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
784 785 786
}
EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);

787
static void ath9k_hw_init_pll(struct ath_hw *ah,
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788
			      struct ath9k_channel *chan)
789
{
790 791
	u32 pll;

792 793
	if (AR_SREV_9485(ah)) {

794 795 796 797 798 799 800
		/* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
			      AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
			      AR_CH0_DPLL2_KD, 0x40);
		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
			      AR_CH0_DPLL2_KI, 0x4);
801

802 803 804 805 806 807
		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
			      AR_CH0_BB_DPLL1_REFDIV, 0x5);
		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
			      AR_CH0_BB_DPLL1_NINI, 0x58);
		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
			      AR_CH0_BB_DPLL1_NFRAC, 0x0);
808 809

		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
810 811 812
			      AR_CH0_BB_DPLL2_OUTDIV, 0x1);
		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
			      AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
813
		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
814
			      AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
815

816
		/* program BB PLL phase_shift to 0x6 */
817
		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
818 819 820 821
			      AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);

		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
			      AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
822
		udelay(1000);
823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855
	} else if (AR_SREV_9330(ah)) {
		u32 ddr_dpll2, pll_control2, kd;

		if (ah->is_clk_25mhz) {
			ddr_dpll2 = 0x18e82f01;
			pll_control2 = 0xe04a3d;
			kd = 0x1d;
		} else {
			ddr_dpll2 = 0x19e82f01;
			pll_control2 = 0x886666;
			kd = 0x3d;
		}

		/* program DDR PLL ki and kd value */
		REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);

		/* program DDR PLL phase_shift */
		REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
			      AR_CH0_DPLL3_PHASE_SHIFT, 0x1);

		REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
		udelay(1000);

		/* program refdiv, nint, frac to RTC register */
		REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);

		/* program BB PLL kd and ki value */
		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);

		/* program BB PLL phase_shift */
		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
			      AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890
	} else if (AR_SREV_9340(ah)) {
		u32 regval, pll2_divint, pll2_divfrac, refdiv;

		REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
		udelay(1000);

		REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
		udelay(100);

		if (ah->is_clk_25mhz) {
			pll2_divint = 0x54;
			pll2_divfrac = 0x1eb85;
			refdiv = 3;
		} else {
			pll2_divint = 88;
			pll2_divfrac = 0;
			refdiv = 5;
		}

		regval = REG_READ(ah, AR_PHY_PLL_MODE);
		regval |= (0x1 << 16);
		REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
		udelay(100);

		REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
			  (pll2_divint << 18) | pll2_divfrac);
		udelay(100);

		regval = REG_READ(ah, AR_PHY_PLL_MODE);
		regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
			 (0x4 << 26) | (0x18 << 19);
		REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
		REG_WRITE(ah, AR_PHY_PLL_MODE,
			  REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
		udelay(1000);
891
	}
892 893

	pll = ath9k_hw_compute_pll_control(ah, chan);
894

895
	REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
896

897
	if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
898 899
		udelay(1000);

900 901
	/* Switch the core clock for ar9271 to 117Mhz */
	if (AR_SREV_9271(ah)) {
902 903
		udelay(500);
		REG_WRITE(ah, 0x50040, 0x304);
904 905
	}

S
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906 907 908
	udelay(RTC_PLL_SETTLE_DELAY);

	REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
909 910 911 912 913 914 915 916 917 918 919 920 921

	if (AR_SREV_9340(ah)) {
		if (ah->is_clk_25mhz) {
			REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
			REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
			REG_WRITE(ah,  AR_SLP32_INC, 0x0001e7ae);
		} else {
			REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
			REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
			REG_WRITE(ah,  AR_SLP32_INC, 0x0001e800);
		}
		udelay(100);
	}
922 923
}

924
static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
925
					  enum nl80211_iftype opmode)
926
{
927
	u32 sync_default = AR_INTR_SYNC_DEFAULT;
928
	u32 imr_reg = AR_IMR_TXERR |
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929 930 931 932
		AR_IMR_TXURN |
		AR_IMR_RXERR |
		AR_IMR_RXORN |
		AR_IMR_BCNMISC;
933

934 935 936
	if (AR_SREV_9340(ah))
		sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;

937 938 939 940 941 942
	if (AR_SREV_9300_20_OR_LATER(ah)) {
		imr_reg |= AR_IMR_RXOK_HP;
		if (ah->config.rx_intr_mitigation)
			imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
		else
			imr_reg |= AR_IMR_RXOK_LP;
943

944 945 946 947 948 949
	} else {
		if (ah->config.rx_intr_mitigation)
			imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
		else
			imr_reg |= AR_IMR_RXOK;
	}
950

951 952 953 954
	if (ah->config.tx_intr_mitigation)
		imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
	else
		imr_reg |= AR_IMR_TXOK;
955

956
	if (opmode == NL80211_IFTYPE_AP)
957
		imr_reg |= AR_IMR_MIB;
958

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959 960
	ENABLE_REGWRITE_BUFFER(ah);

961
	REG_WRITE(ah, AR_IMR, imr_reg);
962 963
	ah->imrs2_reg |= AR_IMR_S2_GTT;
	REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
964

S
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965 966
	if (!AR_SREV_9100(ah)) {
		REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
967
		REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
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968 969
		REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
	}
970

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971 972
	REGWRITE_BUFFER_FLUSH(ah);

973 974 975 976 977 978
	if (AR_SREV_9300_20_OR_LATER(ah)) {
		REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
		REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
		REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
		REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
	}
979 980
}

981 982 983 984 985 986 987
static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
{
	u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
	val = min(val, (u32) 0xFFFF);
	REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
}

988
static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
989
{
990 991 992
	u32 val = ath9k_hw_mac_to_clks(ah, us);
	val = min(val, (u32) 0xFFFF);
	REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
993 994
}

995
static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
996
{
997 998 999 1000 1001 1002 1003 1004 1005 1006
	u32 val = ath9k_hw_mac_to_clks(ah, us);
	val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
	REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
}

static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
{
	u32 val = ath9k_hw_mac_to_clks(ah, us);
	val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
	REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
1007
}
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1008

1009
static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1010 1011
{
	if (tu > 0xFFFF) {
1012 1013
		ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
			tu);
1014
		ah->globaltxtimeout = (u32) -1;
1015 1016 1017
		return false;
	} else {
		REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1018
		ah->globaltxtimeout = tu;
1019 1020 1021 1022
		return true;
	}
}

1023
void ath9k_hw_init_global_settings(struct ath_hw *ah)
1024
{
1025 1026 1027
	struct ath_common *common = ath9k_hw_common(ah);
	struct ieee80211_conf *conf = &common->hw->conf;
	const struct ath9k_channel *chan = ah->curchan;
1028
	int acktimeout, ctstimeout, ack_offset = 0;
1029
	int slottime;
1030
	int sifstime;
1031 1032
	int rx_lat = 0, tx_lat = 0, eifs = 0;
	u32 reg;
1033

1034
	ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
J
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1035
		ah->misc_mode);
1036

1037 1038 1039
	if (!chan)
		return;

1040
	if (ah->misc_mode != 0)
1041
		REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
1042

1043 1044 1045 1046
	if (IS_CHAN_A_FAST_CLOCK(ah, chan))
		rx_lat = 41;
	else
		rx_lat = 37;
1047 1048
	tx_lat = 54;

1049 1050 1051 1052 1053
	if (IS_CHAN_5GHZ(chan))
		sifstime = 16;
	else
		sifstime = 10;

1054 1055 1056 1057 1058 1059 1060
	if (IS_CHAN_HALF_RATE(chan)) {
		eifs = 175;
		rx_lat *= 2;
		tx_lat *= 2;
		if (IS_CHAN_A_FAST_CLOCK(ah, chan))
		    tx_lat += 11;

1061
		sifstime *= 2;
1062
		ack_offset = 16;
1063 1064 1065
		slottime = 13;
	} else if (IS_CHAN_QUARTER_RATE(chan)) {
		eifs = 340;
1066
		rx_lat = (rx_lat * 4) - 1;
1067 1068 1069 1070
		tx_lat *= 4;
		if (IS_CHAN_A_FAST_CLOCK(ah, chan))
		    tx_lat += 22;

1071
		sifstime *= 4;
1072
		ack_offset = 32;
1073 1074
		slottime = 21;
	} else {
1075 1076 1077 1078 1079 1080 1081 1082
		if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
			eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
			reg = AR_USEC_ASYNC_FIFO;
		} else {
			eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
				common->clockrate;
			reg = REG_READ(ah, AR_USEC);
		}
1083 1084 1085 1086 1087
		rx_lat = MS(reg, AR_USEC_RX_LAT);
		tx_lat = MS(reg, AR_USEC_TX_LAT);

		slottime = ah->slottime;
	}
1088

1089
	/* As defined by IEEE 802.11-2007 17.3.8.6 */
1090
	acktimeout = slottime + sifstime + 3 * ah->coverage_class + ack_offset;
1091
	ctstimeout = acktimeout;
1092 1093 1094

	/*
	 * Workaround for early ACK timeouts, add an offset to match the
1095
	 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
1096 1097 1098 1099
	 * This was initially only meant to work around an issue with delayed
	 * BA frames in some implementations, but it has been found to fix ACK
	 * timeout issues in other cases as well.
	 */
1100 1101
	if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ &&
	    !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
1102
		acktimeout += 64 - sifstime - ah->slottime;
1103 1104 1105
		ctstimeout += 48 - sifstime - ah->slottime;
	}

1106

1107 1108
	ath9k_hw_set_sifs_time(ah, sifstime);
	ath9k_hw_setslottime(ah, slottime);
1109
	ath9k_hw_set_ack_timeout(ah, acktimeout);
1110
	ath9k_hw_set_cts_timeout(ah, ctstimeout);
1111 1112
	if (ah->globaltxtimeout != (u32) -1)
		ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1113 1114 1115 1116 1117 1118 1119 1120

	REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
	REG_RMW(ah, AR_USEC,
		(common->clockrate - 1) |
		SM(rx_lat, AR_USEC_RX_LAT) |
		SM(tx_lat, AR_USEC_TX_LAT),
		AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);

S
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1121
}
1122
EXPORT_SYMBOL(ath9k_hw_init_global_settings);
S
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1123

S
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1124
void ath9k_hw_deinit(struct ath_hw *ah)
S
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1125
{
1126 1127
	struct ath_common *common = ath9k_hw_common(ah);

S
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1128
	if (common->state < ATH_HW_INITIALIZED)
1129 1130
		goto free_hw;

1131
	ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1132 1133

free_hw:
1134
	ath9k_hw_rf_free_ext_banks(ah);
S
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1135
}
S
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1136
EXPORT_SYMBOL(ath9k_hw_deinit);
S
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1137 1138 1139 1140 1141

/*******/
/* INI */
/*******/

1142
u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155
{
	u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);

	if (IS_CHAN_B(chan))
		ctl |= CTL_11B;
	else if (IS_CHAN_G(chan))
		ctl |= CTL_11G;
	else
		ctl |= CTL_11A;

	return ctl;
}

S
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1156 1157 1158 1159
/****************************************/
/* Reset and Channel Switching Routines */
/****************************************/

1160
static inline void ath9k_hw_set_dma(struct ath_hw *ah)
S
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1161
{
1162
	struct ath_common *common = ath9k_hw_common(ah);
S
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1163

S
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1164 1165
	ENABLE_REGWRITE_BUFFER(ah);

1166 1167 1168
	/*
	 * set AHB_MODE not to do cacheline prefetches
	*/
1169 1170
	if (!AR_SREV_9300_20_OR_LATER(ah))
		REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
S
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1171

1172 1173 1174
	/*
	 * let mac dma reads be in 128 byte chunks
	 */
1175
	REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
S
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1176

S
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1177 1178
	REGWRITE_BUFFER_FLUSH(ah);

1179 1180 1181 1182 1183
	/*
	 * Restore TX Trigger Level to its pre-reset value.
	 * The initial value depends on whether aggregation is enabled, and is
	 * adjusted whenever underruns are detected.
	 */
1184 1185
	if (!AR_SREV_9300_20_OR_LATER(ah))
		REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
S
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1186

S
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1187
	ENABLE_REGWRITE_BUFFER(ah);
S
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1188

1189 1190 1191
	/*
	 * let mac dma writes be in 128 byte chunks
	 */
1192
	REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
S
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1193

1194 1195 1196
	/*
	 * Setup receive FIFO threshold to hold off TX activities
	 */
S
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1197 1198
	REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);

1199 1200 1201 1202 1203 1204 1205 1206
	if (AR_SREV_9300_20_OR_LATER(ah)) {
		REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
		REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);

		ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
			ah->caps.rx_status_len);
	}

1207 1208 1209 1210
	/*
	 * reduce the number of usable entries in PCU TXBUF to avoid
	 * wrap around issues.
	 */
S
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1211
	if (AR_SREV_9285(ah)) {
1212 1213 1214 1215
		/* For AR9285 the number of Fifos are reduced to half.
		 * So set the usable tx buf size also to half to
		 * avoid data/delimiter underruns
		 */
S
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1216 1217
		REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
			  AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1218
	} else if (!AR_SREV_9271(ah)) {
S
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1219 1220 1221
		REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
			  AR_PCU_TXBUF_CTRL_USABLE_SIZE);
	}
1222

S
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1223 1224
	REGWRITE_BUFFER_FLUSH(ah);

1225 1226
	if (AR_SREV_9300_20_OR_LATER(ah))
		ath9k_hw_reset_txstatus_ring(ah);
S
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1227 1228
}

1229
static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
S
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1230
{
1231 1232
	u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
	u32 set = AR_STA_ID1_KSRCH_MODE;
S
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1233 1234

	switch (opmode) {
1235
	case NL80211_IFTYPE_ADHOC:
1236
	case NL80211_IFTYPE_MESH_POINT:
1237
		set |= AR_STA_ID1_ADHOC;
S
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1238
		REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1239
		break;
1240 1241 1242
	case NL80211_IFTYPE_AP:
		set |= AR_STA_ID1_STA_AP;
		/* fall through */
1243
	case NL80211_IFTYPE_STATION:
1244
		REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1245
		break;
1246
	default:
1247 1248
		if (!ah->is_monitoring)
			set = 0;
1249
		break;
S
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1250
	}
1251
	REG_RMW(ah, AR_STA_ID1, set, mask);
S
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1252 1253
}

1254 1255
void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
				   u32 *coef_mantissa, u32 *coef_exponent)
S
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1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270
{
	u32 coef_exp, coef_man;

	for (coef_exp = 31; coef_exp > 0; coef_exp--)
		if ((coef_scaled >> coef_exp) & 0x1)
			break;

	coef_exp = 14 - (coef_exp - COEF_SCALE_S);

	coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));

	*coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
	*coef_exponent = coef_exp - 16;
}

1271
static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
S
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1272 1273 1274 1275
{
	u32 rst_flags;
	u32 tmpReg;

1276
	if (AR_SREV_9100(ah)) {
1277 1278
		REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
			      AR_RTC_DERIVED_CLK_PERIOD, 1);
1279 1280 1281
		(void)REG_READ(ah, AR_RTC_DERIVED_CLK);
	}

S
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1282 1283
	ENABLE_REGWRITE_BUFFER(ah);

1284 1285 1286 1287 1288
	if (AR_SREV_9300_20_OR_LATER(ah)) {
		REG_WRITE(ah, AR_WA, ah->WARegVal);
		udelay(10);
	}

S
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1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299
	REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
		  AR_RTC_FORCE_WAKE_ON_INT);

	if (AR_SREV_9100(ah)) {
		rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
			AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
	} else {
		tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
		if (tmpReg &
		    (AR_INTR_SYNC_LOCAL_TIMEOUT |
		     AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1300
			u32 val;
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1301
			REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1302 1303 1304 1305 1306 1307 1308

			val = AR_RC_HOSTIF;
			if (!AR_SREV_9300_20_OR_LATER(ah))
				val |= AR_RC_AHB;
			REG_WRITE(ah, AR_RC, val);

		} else if (!AR_SREV_9300_20_OR_LATER(ah))
S
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1309 1310 1311 1312 1313 1314 1315
			REG_WRITE(ah, AR_RC, AR_RC_AHB);

		rst_flags = AR_RTC_RC_MAC_WARM;
		if (type == ATH9K_RESET_COLD)
			rst_flags |= AR_RTC_RC_MAC_COLD;
	}

1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335
	if (AR_SREV_9330(ah)) {
		int npend = 0;
		int i;

		/* AR9330 WAR:
		 * call external reset function to reset WMAC if:
		 * - doing a cold reset
		 * - we have pending frames in the TX queues
		 */

		for (i = 0; i < AR_NUM_QCU; i++) {
			npend = ath9k_hw_numtxpending(ah, i);
			if (npend)
				break;
		}

		if (ah->external_reset &&
		    (npend || type == ATH9K_RESET_COLD)) {
			int reset_err = 0;

1336
			ath_dbg(ath9k_hw_common(ah), RESET,
1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350
				"reset MAC via external reset\n");

			reset_err = ah->external_reset();
			if (reset_err) {
				ath_err(ath9k_hw_common(ah),
					"External reset failed, err=%d\n",
					reset_err);
				return false;
			}

			REG_WRITE(ah, AR_RTC_RESET, 1);
		}
	}

1351
	REG_WRITE(ah, AR_RTC_RC, rst_flags);
S
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1352 1353 1354

	REGWRITE_BUFFER_FLUSH(ah);

S
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1355 1356
	udelay(50);

1357
	REG_WRITE(ah, AR_RTC_RC, 0);
S
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1358
	if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1359
		ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
S
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1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371
		return false;
	}

	if (!AR_SREV_9100(ah))
		REG_WRITE(ah, AR_RC, 0);

	if (AR_SREV_9100(ah))
		udelay(50);

	return true;
}

1372
static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
S
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1373
{
S
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1374 1375
	ENABLE_REGWRITE_BUFFER(ah);

1376 1377 1378 1379 1380
	if (AR_SREV_9300_20_OR_LATER(ah)) {
		REG_WRITE(ah, AR_WA, ah->WARegVal);
		udelay(10);
	}

S
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1381 1382 1383
	REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
		  AR_RTC_FORCE_WAKE_ON_INT);

1384
	if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1385 1386
		REG_WRITE(ah, AR_RC, AR_RC_AHB);

1387
	REG_WRITE(ah, AR_RTC_RESET, 0);
1388

S
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1389 1390
	REGWRITE_BUFFER_FLUSH(ah);

1391 1392 1393 1394
	if (!AR_SREV_9300_20_OR_LATER(ah))
		udelay(2);

	if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1395 1396
		REG_WRITE(ah, AR_RC, 0);

1397
	REG_WRITE(ah, AR_RTC_RESET, 1);
S
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1398 1399 1400 1401

	if (!ath9k_hw_wait(ah,
			   AR_RTC_STATUS,
			   AR_RTC_STATUS_M,
S
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1402 1403
			   AR_RTC_STATUS_ON,
			   AH_WAIT_TIMEOUT)) {
1404
		ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
S
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1405
		return false;
1406 1407
	}

S
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1408 1409 1410
	return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
}

1411
static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
S
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1412
{
1413
	bool ret = false;
1414

1415 1416 1417 1418 1419
	if (AR_SREV_9300_20_OR_LATER(ah)) {
		REG_WRITE(ah, AR_WA, ah->WARegVal);
		udelay(10);
	}

S
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1420 1421 1422 1423 1424
	REG_WRITE(ah, AR_RTC_FORCE_WAKE,
		  AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);

	switch (type) {
	case ATH9K_RESET_POWER_ON:
1425 1426
		ret = ath9k_hw_set_reset_power_on(ah);
		break;
S
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1427 1428
	case ATH9K_RESET_WARM:
	case ATH9K_RESET_COLD:
1429 1430
		ret = ath9k_hw_set_reset(ah, type);
		break;
S
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1431
	default:
1432
		break;
S
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1433
	}
1434 1435

	return ret;
1436 1437
}

1438
static bool ath9k_hw_chip_reset(struct ath_hw *ah,
S
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1439
				struct ath9k_channel *chan)
1440
{
1441 1442 1443 1444 1445 1446 1447 1448 1449 1450
	int reset_type = ATH9K_RESET_WARM;

	if (AR_SREV_9280(ah)) {
		if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
			reset_type = ATH9K_RESET_POWER_ON;
		else
			reset_type = ATH9K_RESET_COLD;
	}

	if (!ath9k_hw_set_reset_reg(ah, reset_type))
S
Sujith 已提交
1451
		return false;
1452

1453
	if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
S
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1454
		return false;
1455

1456
	ah->chip_fullsleep = false;
1457 1458 1459

	if (AR_SREV_9330(ah))
		ar9003_hw_internal_regulator_apply(ah);
S
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1460 1461
	ath9k_hw_init_pll(ah, chan);
	ath9k_hw_set_rfmode(ah, chan);
1462

S
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1463
	return true;
1464 1465
}

1466
static bool ath9k_hw_channel_change(struct ath_hw *ah,
L
Luis R. Rodriguez 已提交
1467
				    struct ath9k_channel *chan)
1468
{
1469
	struct ath_common *common = ath9k_hw_common(ah);
1470
	u32 qnum;
1471
	int r;
1472 1473 1474 1475 1476 1477 1478 1479
	bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
	bool band_switch, mode_diff;
	u8 ini_reloaded;

	band_switch = (chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ)) !=
		      (ah->curchan->channelFlags & (CHANNEL_2GHZ |
						    CHANNEL_5GHZ));
	mode_diff = (chan->chanmode != ah->curchan->chanmode);
1480 1481 1482

	for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
		if (ath9k_hw_numtxpending(ah, qnum)) {
1483
			ath_dbg(common, QUEUE,
J
Joe Perches 已提交
1484
				"Transmit frames pending on queue %d\n", qnum);
1485 1486 1487 1488
			return false;
		}
	}

1489
	if (!ath9k_hw_rfbus_req(ah)) {
1490
		ath_err(common, "Could not kill baseband RX\n");
1491 1492 1493
		return false;
	}

1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505
	if (edma && (band_switch || mode_diff)) {
		ath9k_hw_mark_phy_inactive(ah);
		udelay(5);

		ath9k_hw_init_pll(ah, NULL);

		if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
			ath_err(common, "Failed to do fast channel change\n");
			return false;
		}
	}

1506
	ath9k_hw_set_channel_regs(ah, chan);
1507

1508
	r = ath9k_hw_rf_set_freq(ah, chan);
1509
	if (r) {
1510
		ath_err(common, "Failed to set channel\n");
1511
		return false;
1512
	}
1513
	ath9k_hw_set_clockrate(ah);
1514
	ath9k_hw_apply_txpower(ah, chan, false);
1515
	ath9k_hw_rfbus_done(ah);
1516

S
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1517 1518 1519
	if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
		ath9k_hw_set_delta_slope(ah, chan);

1520
	ath9k_hw_spur_mitigate_freq(ah, chan);
S
Sujith 已提交
1521

1522
	if (edma && (band_switch || mode_diff)) {
1523
		ah->ah_flags |= AH_FASTCC;
1524 1525 1526 1527 1528 1529 1530
		if (band_switch || ini_reloaded)
			ah->eep_ops->set_board_values(ah, chan);

		ath9k_hw_init_bb(ah, chan);

		if (band_switch || ini_reloaded)
			ath9k_hw_init_cal(ah, chan);
1531
		ah->ah_flags &= ~AH_FASTCC;
1532 1533
	}

S
Sujith 已提交
1534 1535 1536
	return true;
}

1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550
static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
{
	u32 gpio_mask = ah->gpio_mask;
	int i;

	for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
		if (!(gpio_mask & 1))
			continue;

		ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
		ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
	}
}

1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620
static bool ath9k_hw_check_dcs(u32 dma_dbg, u32 num_dcu_states,
			       int *hang_state, int *hang_pos)
{
	static u32 dcu_chain_state[] = {5, 6, 9}; /* DCU chain stuck states */
	u32 chain_state, dcs_pos, i;

	for (dcs_pos = 0; dcs_pos < num_dcu_states; dcs_pos++) {
		chain_state = (dma_dbg >> (5 * dcs_pos)) & 0x1f;
		for (i = 0; i < 3; i++) {
			if (chain_state == dcu_chain_state[i]) {
				*hang_state = chain_state;
				*hang_pos = dcs_pos;
				return true;
			}
		}
	}
	return false;
}

#define DCU_COMPLETE_STATE        1
#define DCU_COMPLETE_STATE_MASK 0x3
#define NUM_STATUS_READS         50
static bool ath9k_hw_detect_mac_hang(struct ath_hw *ah)
{
	u32 chain_state, comp_state, dcs_reg = AR_DMADBG_4;
	u32 i, hang_pos, hang_state, num_state = 6;

	comp_state = REG_READ(ah, AR_DMADBG_6);

	if ((comp_state & DCU_COMPLETE_STATE_MASK) != DCU_COMPLETE_STATE) {
		ath_dbg(ath9k_hw_common(ah), RESET,
			"MAC Hang signature not found at DCU complete\n");
		return false;
	}

	chain_state = REG_READ(ah, dcs_reg);
	if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
		goto hang_check_iter;

	dcs_reg = AR_DMADBG_5;
	num_state = 4;
	chain_state = REG_READ(ah, dcs_reg);
	if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
		goto hang_check_iter;

	ath_dbg(ath9k_hw_common(ah), RESET,
		"MAC Hang signature 1 not found\n");
	return false;

hang_check_iter:
	ath_dbg(ath9k_hw_common(ah), RESET,
		"DCU registers: chain %08x complete %08x Hang: state %d pos %d\n",
		chain_state, comp_state, hang_state, hang_pos);

	for (i = 0; i < NUM_STATUS_READS; i++) {
		chain_state = REG_READ(ah, dcs_reg);
		chain_state = (chain_state >> (5 * hang_pos)) & 0x1f;
		comp_state = REG_READ(ah, AR_DMADBG_6);

		if (((comp_state & DCU_COMPLETE_STATE_MASK) !=
					DCU_COMPLETE_STATE) ||
		    (chain_state != hang_state))
			return false;
	}

	ath_dbg(ath9k_hw_common(ah), RESET, "MAC Hang signature 1 found\n");

	return true;
}

1621
bool ath9k_hw_check_alive(struct ath_hw *ah)
J
Johannes Berg 已提交
1622
{
1623 1624 1625
	int count = 50;
	u32 reg;

1626 1627 1628
	if (AR_SREV_9300(ah))
		return !ath9k_hw_detect_mac_hang(ah);

1629
	if (AR_SREV_9285_12_OR_LATER(ah))
1630 1631 1632 1633
		return true;

	do {
		reg = REG_READ(ah, AR_OBS_BUS_1);
J
Johannes Berg 已提交
1634

1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646
		if ((reg & 0x7E7FFFEF) == 0x00702400)
			continue;

		switch (reg & 0x7E000B00) {
		case 0x1E000000:
		case 0x52000B00:
		case 0x18000B00:
			continue;
		default:
			return true;
		}
	} while (count-- > 0);
J
Johannes Berg 已提交
1647

1648
	return false;
J
Johannes Berg 已提交
1649
}
1650
EXPORT_SYMBOL(ath9k_hw_check_alive);
J
Johannes Berg 已提交
1651

1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678
/*
 * Fast channel change:
 * (Change synthesizer based on channel freq without resetting chip)
 *
 * Don't do FCC when
 *   - Flag is not set
 *   - Chip is just coming out of full sleep
 *   - Channel to be set is same as current channel
 *   - Channel flags are different, (eg.,moving from 2GHz to 5GHz channel)
 */
static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
{
	struct ath_common *common = ath9k_hw_common(ah);
	int ret;

	if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
		goto fail;

	if (ah->chip_fullsleep)
		goto fail;

	if (!ah->curchan)
		goto fail;

	if (chan->channel == ah->curchan->channel)
		goto fail;

1679 1680 1681 1682
	if ((ah->curchan->channelFlags | chan->channelFlags) &
	    (CHANNEL_HALF | CHANNEL_QUARTER))
		goto fail;

1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693
	if ((chan->channelFlags & CHANNEL_ALL) !=
	    (ah->curchan->channelFlags & CHANNEL_ALL))
		goto fail;

	if (!ath9k_hw_check_alive(ah))
		goto fail;

	/*
	 * For AR9462, make sure that calibration data for
	 * re-using are present.
	 */
S
Sujith Manoharan 已提交
1694 1695 1696 1697
	if (AR_SREV_9462(ah) && (ah->caldata &&
				 (!ah->caldata->done_txiqcal_once ||
				  !ah->caldata->done_txclcal_once ||
				  !ah->caldata->rtt_done)))
1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709
		goto fail;

	ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
		ah->curchan->channel, chan->channel);

	ret = ath9k_hw_channel_change(ah, chan);
	if (!ret)
		goto fail;

	ath9k_hw_loadnf(ah, ah->curchan);
	ath9k_hw_start_nfcal(ah, true);

S
Sujith Manoharan 已提交
1710
	if (ath9k_hw_mci_is_enabled(ah))
1711 1712 1713 1714 1715 1716 1717 1718 1719 1720
		ar9003_mci_2g5g_switch(ah, true);

	if (AR_SREV_9271(ah))
		ar9002_hw_load_ani_reg(ah, chan);

	return 0;
fail:
	return -EINVAL;
}

1721
int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1722
		   struct ath9k_hw_cal_data *caldata, bool fastcc)
1723
{
1724
	struct ath_common *common = ath9k_hw_common(ah);
1725 1726 1727
	u32 saveLedState;
	u32 saveDefAntenna;
	u32 macStaId1;
S
Sujith 已提交
1728
	u64 tsf = 0;
1729
	int i, r;
1730
	bool start_mci_reset = false;
1731 1732
	bool save_fullsleep = ah->chip_fullsleep;

S
Sujith Manoharan 已提交
1733
	if (ath9k_hw_mci_is_enabled(ah)) {
1734 1735 1736
		start_mci_reset = ar9003_mci_start_reset(ah, chan);
		if (start_mci_reset)
			return 0;
1737 1738
	}

1739
	if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1740
		return -EIO;
1741

1742 1743
	if (ah->curchan && !ah->chip_fullsleep)
		ath9k_hw_getnf(ah, ah->curchan);
1744

1745 1746 1747 1748 1749 1750 1751 1752 1753
	ah->caldata = caldata;
	if (caldata &&
	    (chan->channel != caldata->channel ||
	     (chan->channelFlags & ~CHANNEL_CW_INT) !=
	     (caldata->channelFlags & ~CHANNEL_CW_INT))) {
		/* Operating channel changed, reset channel calibration data */
		memset(caldata, 0, sizeof(*caldata));
		ath9k_init_nfcal_hist_buffer(ah, chan);
	}
1754
	ah->noise = ath9k_hw_getchan_noise(ah, chan);
1755

1756 1757 1758 1759
	if (fastcc) {
		r = ath9k_hw_do_fastcc(ah, chan);
		if (!r)
			return r;
1760 1761
	}

S
Sujith Manoharan 已提交
1762
	if (ath9k_hw_mci_is_enabled(ah))
1763
		ar9003_mci_stop_bt(ah, save_fullsleep);
1764

1765 1766 1767 1768 1769 1770
	saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
	if (saveDefAntenna == 0)
		saveDefAntenna = 1;

	macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;

S
Sujith 已提交
1771
	/* For chips on which RTC reset is done, save TSF before it gets cleared */
1772 1773
	if (AR_SREV_9100(ah) ||
	    (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
S
Sujith 已提交
1774 1775
		tsf = ath9k_hw_gettsf64(ah);

1776 1777 1778 1779 1780 1781
	saveLedState = REG_READ(ah, AR_CFG_LED) &
		(AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
		 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);

	ath9k_hw_mark_phy_inactive(ah);

1782 1783
	ah->paprd_table_write_done = false;

1784
	/* Only required on the first reset */
1785 1786 1787 1788 1789 1790 1791
	if (AR_SREV_9271(ah) && ah->htc_reset_init) {
		REG_WRITE(ah,
			  AR9271_RESET_POWER_DOWN_CONTROL,
			  AR9271_RADIO_RF_RST);
		udelay(50);
	}

1792
	if (!ath9k_hw_chip_reset(ah, chan)) {
1793
		ath_err(common, "Chip reset failed\n");
1794
		return -EINVAL;
1795 1796
	}

1797
	/* Only required on the first reset */
1798 1799 1800 1801 1802 1803 1804 1805
	if (AR_SREV_9271(ah) && ah->htc_reset_init) {
		ah->htc_reset_init = false;
		REG_WRITE(ah,
			  AR9271_RESET_POWER_DOWN_CONTROL,
			  AR9271_GATE_MAC_CTL);
		udelay(50);
	}

S
Sujith 已提交
1806
	/* Restore TSF */
1807
	if (tsf)
S
Sujith 已提交
1808 1809
		ath9k_hw_settsf64(ah, tsf);

1810
	if (AR_SREV_9280_20_OR_LATER(ah))
1811
		REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1812

S
Sujith 已提交
1813 1814 1815
	if (!AR_SREV_9300_20_OR_LATER(ah))
		ar9002_hw_enable_async_fifo(ah);

L
Luis R. Rodriguez 已提交
1816
	r = ath9k_hw_process_ini(ah, chan);
1817 1818
	if (r)
		return r;
1819

S
Sujith Manoharan 已提交
1820
	if (ath9k_hw_mci_is_enabled(ah))
1821 1822
		ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);

1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833
	/*
	 * Some AR91xx SoC devices frequently fail to accept TSF writes
	 * right after the chip reset. When that happens, write a new
	 * value after the initvals have been applied, with an offset
	 * based on measured time difference
	 */
	if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
		tsf += 1500;
		ath9k_hw_settsf64(ah, tsf);
	}

1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850
	/* Setup MFP options for CCMP */
	if (AR_SREV_9280_20_OR_LATER(ah)) {
		/* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
		 * frames when constructing CCMP AAD. */
		REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
			      0xc7ff);
		ah->sw_mgmt_crypto = false;
	} else if (AR_SREV_9160_10_OR_LATER(ah)) {
		/* Disable hardware crypto for management frames */
		REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
			    AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
		REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
			    AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
		ah->sw_mgmt_crypto = true;
	} else
		ah->sw_mgmt_crypto = true;

1851 1852 1853
	if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
		ath9k_hw_set_delta_slope(ah, chan);

1854
	ath9k_hw_spur_mitigate_freq(ah, chan);
1855
	ah->eep_ops->set_board_values(ah, chan);
1856

S
Sujith 已提交
1857 1858
	ENABLE_REGWRITE_BUFFER(ah);

1859 1860
	REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
	REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1861 1862
		  | macStaId1
		  | AR_STA_ID1_RTS_USE_DEF
1863
		  | (ah->config.
1864
		     ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1865
		  | ah->sta_id1_defaults);
1866
	ath_hw_setbssidmask(common);
1867
	REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1868
	ath9k_hw_write_associd(ah);
1869 1870 1871
	REG_WRITE(ah, AR_ISR, ~0);
	REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);

S
Sujith 已提交
1872 1873
	REGWRITE_BUFFER_FLUSH(ah);

1874 1875
	ath9k_hw_set_operating_mode(ah, ah->opmode);

1876
	r = ath9k_hw_rf_set_freq(ah, chan);
1877 1878
	if (r)
		return r;
1879

1880 1881
	ath9k_hw_set_clockrate(ah);

S
Sujith 已提交
1882 1883
	ENABLE_REGWRITE_BUFFER(ah);

1884 1885 1886
	for (i = 0; i < AR_NUM_DCU; i++)
		REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);

S
Sujith 已提交
1887 1888
	REGWRITE_BUFFER_FLUSH(ah);

1889
	ah->intr_txqs = 0;
1890
	for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1891 1892
		ath9k_hw_resettxqueue(ah, i);

1893
	ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1894
	ath9k_hw_ani_cache_ini_regs(ah);
1895 1896
	ath9k_hw_init_qos(ah);

1897
	if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1898
		ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
J
Johannes Berg 已提交
1899

1900
	ath9k_hw_init_global_settings(ah);
1901

1902 1903 1904 1905 1906 1907 1908
	if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
		REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
			    AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
		REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
			      AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
		REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
			    AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
1909 1910
	}

1911
	REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
1912 1913 1914 1915 1916

	ath9k_hw_set_dma(ah);

	REG_WRITE(ah, AR_OBS, 8);

S
Sujith 已提交
1917
	if (ah->config.rx_intr_mitigation) {
1918 1919 1920 1921
		REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
		REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
	}

1922 1923 1924 1925 1926
	if (ah->config.tx_intr_mitigation) {
		REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
		REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
	}

1927 1928
	ath9k_hw_init_bb(ah, chan);

1929
	if (caldata) {
1930
		caldata->done_txiqcal_once = false;
1931 1932
		caldata->done_txclcal_once = false;
	}
1933
	if (!ath9k_hw_init_cal(ah, chan))
1934
		return -EIO;
1935

1936 1937 1938
	ath9k_hw_loadnf(ah, chan);
	ath9k_hw_start_nfcal(ah, true);

S
Sujith Manoharan 已提交
1939
	if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))
1940
		return -EIO;
1941

S
Sujith 已提交
1942
	ENABLE_REGWRITE_BUFFER(ah);
1943

1944
	ath9k_hw_restore_chainmask(ah);
1945 1946
	REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);

S
Sujith 已提交
1947 1948
	REGWRITE_BUFFER_FLUSH(ah);

1949 1950 1951
	/*
	 * For big endian systems turn on swapping for descriptors
	 */
1952 1953 1954 1955
	if (AR_SREV_9100(ah)) {
		u32 mask;
		mask = REG_READ(ah, AR_CFG);
		if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1956 1957
			ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
				mask);
1958 1959 1960 1961
		} else {
			mask =
				INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
			REG_WRITE(ah, AR_CFG, mask);
1962 1963
			ath_dbg(common, RESET, "Setting CFG 0x%x\n",
				REG_READ(ah, AR_CFG));
1964 1965
		}
	} else {
1966 1967 1968 1969 1970 1971 1972
		if (common->bus_ops->ath_bus_type == ATH_USB) {
			/* Configure AR9271 target WLAN */
			if (AR_SREV_9271(ah))
				REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
			else
				REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
		}
1973
#ifdef __BIG_ENDIAN
1974
		else if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
1975 1976
			REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
		else
1977
			REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1978 1979 1980
#endif
	}

1981
	if (ath9k_hw_btcoex_is_enabled(ah))
1982 1983
		ath9k_hw_btcoex_enable(ah);

S
Sujith Manoharan 已提交
1984
	if (ath9k_hw_mci_is_enabled(ah))
1985
		ar9003_mci_check_bt(ah);
1986

1987
	if (AR_SREV_9300_20_OR_LATER(ah)) {
1988
		ar9003_hw_bb_watchdog_config(ah);
1989

1990 1991 1992
		ar9003_hw_disable_phy_restart(ah);
	}

1993 1994
	ath9k_hw_apply_gpio_override(ah);

1995
	return 0;
1996
}
1997
EXPORT_SYMBOL(ath9k_hw_reset);
1998

S
Sujith 已提交
1999 2000 2001 2002
/******************************/
/* Power Management (Chipset) */
/******************************/

2003 2004 2005 2006
/*
 * Notify Power Mgt is disabled in self-generated frames.
 * If requested, force chip to sleep.
 */
2007
static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2008
{
S
Sujith 已提交
2009 2010
	REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
	if (setChip) {
2011
		if (AR_SREV_9462(ah)) {
2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022
			REG_WRITE(ah, AR_TIMER_MODE,
				  REG_READ(ah, AR_TIMER_MODE) & 0xFFFFFF00);
			REG_WRITE(ah, AR_NDP2_TIMER_MODE, REG_READ(ah,
				  AR_NDP2_TIMER_MODE) & 0xFFFFFF00);
			REG_WRITE(ah, AR_SLP32_INC,
				  REG_READ(ah, AR_SLP32_INC) & 0xFFF00000);
			/* xxx Required for WLAN only case ? */
			REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
			udelay(100);
		}

2023 2024 2025 2026
		/*
		 * Clear the RTC force wake bit to allow the
		 * mac to go to sleep.
		 */
2027 2028
		REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);

2029
		if (AR_SREV_9462(ah))
2030 2031
			udelay(100);

2032
		if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
S
Sujith 已提交
2033
			REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2034

2035
		/* Shutdown chip. Active low */
2036
		if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
2037 2038 2039
			REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
			udelay(2);
		}
S
Sujith 已提交
2040
	}
2041 2042

	/* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
2043 2044
	if (AR_SREV_9300_20_OR_LATER(ah))
		REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2045 2046
}

2047 2048 2049 2050 2051
/*
 * Notify Power Management is enabled in self-generating
 * frames. If request, set power mode of chip to
 * auto/normal.  Duration in units of 128us (1/8 TU).
 */
2052
static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2053
{
2054 2055
	u32 val;

S
Sujith 已提交
2056 2057
	REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
	if (setChip) {
2058
		struct ath9k_hw_capabilities *pCap = &ah->caps;
2059

S
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2060
		if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2061
			/* Set WakeOnInterrupt bit; clear ForceWake bit */
S
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2062 2063 2064
			REG_WRITE(ah, AR_RTC_FORCE_WAKE,
				  AR_RTC_FORCE_WAKE_ON_INT);
		} else {
2065 2066 2067 2068 2069 2070 2071 2072 2073 2074

			/* When chip goes into network sleep, it could be waken
			 * up by MCI_INT interrupt caused by BT's HW messages
			 * (LNA_xxx, CONT_xxx) which chould be in a very fast
			 * rate (~100us). This will cause chip to leave and
			 * re-enter network sleep mode frequently, which in
			 * consequence will have WLAN MCI HW to generate lots of
			 * SYS_WAKING and SYS_SLEEPING messages which will make
			 * BT CPU to busy to process.
			 */
2075
			if (AR_SREV_9462(ah)) {
2076 2077 2078 2079
				val = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_EN) &
					~AR_MCI_INTERRUPT_RX_HW_MSG_MASK;
				REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, val);
			}
2080 2081 2082 2083
			/*
			 * Clear the RTC force wake bit to allow the
			 * mac to go to sleep.
			 */
S
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2084 2085
			REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
				    AR_RTC_FORCE_WAKE_EN);
2086

2087
			if (AR_SREV_9462(ah))
2088
				udelay(30);
2089 2090
		}
	}
2091 2092 2093 2094

	/* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
	if (AR_SREV_9300_20_OR_LATER(ah))
		REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2095 2096
}

2097
static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2098
{
S
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2099 2100
	u32 val;
	int i;
2101

2102 2103 2104 2105 2106 2107
	/* Set Bits 14 and 17 of AR_WA before powering on the chip. */
	if (AR_SREV_9300_20_OR_LATER(ah)) {
		REG_WRITE(ah, AR_WA, ah->WARegVal);
		udelay(10);
	}

S
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2108 2109 2110
	if (setChip) {
		if ((REG_READ(ah, AR_RTC_STATUS) &
		     AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2111
			if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
S
Sujith 已提交
2112 2113
				return false;
			}
2114 2115
			if (!AR_SREV_9300_20_OR_LATER(ah))
				ath9k_hw_init_pll(ah, NULL);
S
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2116 2117 2118 2119
		}
		if (AR_SREV_9100(ah))
			REG_SET_BIT(ah, AR_RTC_RESET,
				    AR_RTC_RESET_EN);
2120

S
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2121 2122 2123
		REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
			    AR_RTC_FORCE_WAKE_EN);
		udelay(50);
2124

S
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2125 2126 2127 2128 2129 2130 2131
		for (i = POWER_UP_TIME / 50; i > 0; i--) {
			val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
			if (val == AR_RTC_STATUS_ON)
				break;
			udelay(50);
			REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
				    AR_RTC_FORCE_WAKE_EN);
2132
		}
S
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2133
		if (i == 0) {
2134 2135 2136
			ath_err(ath9k_hw_common(ah),
				"Failed to wakeup in %uus\n",
				POWER_UP_TIME / 20);
S
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2137
			return false;
2138 2139 2140
		}
	}

S
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2141
	REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2142

S
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2143
	return true;
2144 2145
}

2146
bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2147
{
2148
	struct ath_common *common = ath9k_hw_common(ah);
2149
	int status = true, setChip = true;
S
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2150 2151 2152 2153 2154 2155 2156
	static const char *modes[] = {
		"AWAKE",
		"FULL-SLEEP",
		"NETWORK SLEEP",
		"UNDEFINED"
	};

2157 2158 2159
	if (ah->power_mode == mode)
		return status;

2160
	ath_dbg(common, RESET, "%s -> %s\n",
J
Joe Perches 已提交
2161
		modes[ah->power_mode], modes[mode]);
S
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2162 2163 2164 2165 2166 2167

	switch (mode) {
	case ATH9K_PM_AWAKE:
		status = ath9k_hw_set_power_awake(ah, setChip);
		break;
	case ATH9K_PM_FULL_SLEEP:
S
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2168
		if (ath9k_hw_mci_is_enabled(ah))
2169
			ar9003_mci_set_full_sleep(ah);
2170

S
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2171
		ath9k_set_power_sleep(ah, setChip);
2172
		ah->chip_fullsleep = true;
S
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2173 2174 2175 2176
		break;
	case ATH9K_PM_NETWORK_SLEEP:
		ath9k_set_power_network_sleep(ah, setChip);
		break;
2177
	default:
2178
		ath_err(common, "Unknown power mode %u\n", mode);
2179 2180
		return false;
	}
2181
	ah->power_mode = mode;
S
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2182

2183 2184 2185 2186 2187
	/*
	 * XXX: If this warning never comes up after a while then
	 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
	 * ath9k_hw_setpower() return type void.
	 */
2188 2189 2190

	if (!(ah->ah_flags & AH_UNPLUGGED))
		ATH_DBG_WARN_ON_ONCE(!status);
2191

S
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2192
	return status;
2193
}
2194
EXPORT_SYMBOL(ath9k_hw_setpower);
2195

S
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2196 2197 2198 2199
/*******************/
/* Beacon Handling */
/*******************/

2200
void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2201 2202 2203
{
	int flags = 0;

S
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2204 2205
	ENABLE_REGWRITE_BUFFER(ah);

2206
	switch (ah->opmode) {
2207
	case NL80211_IFTYPE_ADHOC:
2208
	case NL80211_IFTYPE_MESH_POINT:
2209 2210
		REG_SET_BIT(ah, AR_TXCFG,
			    AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2211 2212
		REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
			  TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
2213
		flags |= AR_NDP_TIMER_EN;
2214
	case NL80211_IFTYPE_AP:
2215 2216 2217 2218 2219
		REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
		REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
			  TU_TO_USEC(ah->config.dma_beacon_response_time));
		REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
			  TU_TO_USEC(ah->config.sw_beacon_response_time));
2220 2221 2222
		flags |=
			AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
		break;
2223
	default:
2224 2225
		ath_dbg(ath9k_hw_common(ah), BEACON,
			"%s: unsupported opmode: %d\n", __func__, ah->opmode);
2226 2227
		return;
		break;
2228 2229
	}

2230 2231 2232 2233
	REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
	REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
	REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
	REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
2234

S
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2235 2236
	REGWRITE_BUFFER_FLUSH(ah);

2237 2238
	REG_SET_BIT(ah, AR_TIMER_MODE, flags);
}
2239
EXPORT_SYMBOL(ath9k_hw_beaconinit);
2240

2241
void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
S
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2242
				    const struct ath9k_beacon_state *bs)
2243 2244
{
	u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2245
	struct ath9k_hw_capabilities *pCap = &ah->caps;
2246
	struct ath_common *common = ath9k_hw_common(ah);
2247

S
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2248 2249
	ENABLE_REGWRITE_BUFFER(ah);

2250 2251 2252
	REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));

	REG_WRITE(ah, AR_BEACON_PERIOD,
2253
		  TU_TO_USEC(bs->bs_intval));
2254
	REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
2255
		  TU_TO_USEC(bs->bs_intval));
2256

S
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2257 2258
	REGWRITE_BUFFER_FLUSH(ah);

2259 2260 2261
	REG_RMW_FIELD(ah, AR_RSSI_THR,
		      AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);

2262
	beaconintval = bs->bs_intval;
2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275

	if (bs->bs_sleepduration > beaconintval)
		beaconintval = bs->bs_sleepduration;

	dtimperiod = bs->bs_dtimperiod;
	if (bs->bs_sleepduration > dtimperiod)
		dtimperiod = bs->bs_sleepduration;

	if (beaconintval == dtimperiod)
		nextTbtt = bs->bs_nextdtim;
	else
		nextTbtt = bs->bs_nexttbtt;

2276 2277 2278 2279
	ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim);
	ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt);
	ath_dbg(common, BEACON, "beacon period %d\n", beaconintval);
	ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod);
2280

S
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2281 2282
	ENABLE_REGWRITE_BUFFER(ah);

S
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2283 2284 2285
	REG_WRITE(ah, AR_NEXT_DTIM,
		  TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
	REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
2286

S
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2287 2288 2289
	REG_WRITE(ah, AR_SLEEP1,
		  SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
		  | AR_SLEEP1_ASSUME_DTIM);
2290

S
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2291 2292 2293 2294
	if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
		beacontimeout = (BEACON_TIMEOUT_VAL << 3);
	else
		beacontimeout = MIN_BEACON_TIMEOUT_VAL;
2295

S
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2296 2297
	REG_WRITE(ah, AR_SLEEP2,
		  SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2298

S
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2299 2300
	REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
	REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
2301

S
Sujith 已提交
2302 2303
	REGWRITE_BUFFER_FLUSH(ah);

S
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2304 2305 2306
	REG_SET_BIT(ah, AR_TIMER_MODE,
		    AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
		    AR_DTIM_TIMER_EN);
2307

2308 2309
	/* TSF Out of Range Threshold */
	REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2310
}
2311
EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2312

S
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2313 2314 2315 2316
/*******************/
/* HW Capabilities */
/*******************/

2317 2318 2319 2320 2321 2322 2323 2324 2325
static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
{
	eeprom_chainmask &= chip_chainmask;
	if (eeprom_chainmask)
		return eeprom_chainmask;
	else
		return chip_chainmask;
}

Z
Zefir Kurtisi 已提交
2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349
/**
 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
 * @ah: the atheros hardware data structure
 *
 * We enable DFS support upstream on chipsets which have passed a series
 * of tests. The testing requirements are going to be documented. Desired
 * test requirements are documented at:
 *
 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
 *
 * Once a new chipset gets properly tested an individual commit can be used
 * to document the testing for DFS for that chipset.
 */
static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
{

	switch (ah->hw_version.macVersion) {
	/* AR9580 will likely be our first target to get testing on */
	case AR_SREV_VERSION_9580:
	default:
		return false;
	}
}

2350
int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2351
{
2352
	struct ath9k_hw_capabilities *pCap = &ah->caps;
2353
	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2354
	struct ath_common *common = ath9k_hw_common(ah);
2355
	unsigned int chip_chainmask;
2356

2357
	u16 eeval;
2358
	u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
2359

S
Sujith 已提交
2360
	eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2361
	regulatory->current_rd = eeval;
2362

2363
	if (ah->opmode != NL80211_IFTYPE_AP &&
2364
	    ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2365 2366 2367 2368 2369
		if (regulatory->current_rd == 0x64 ||
		    regulatory->current_rd == 0x65)
			regulatory->current_rd += 5;
		else if (regulatory->current_rd == 0x41)
			regulatory->current_rd = 0x43;
2370 2371
		ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
			regulatory->current_rd);
S
Sujith 已提交
2372
	}
2373

S
Sujith 已提交
2374
	eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2375
	if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2376 2377
		ath_err(common,
			"no band has been marked as supported in EEPROM\n");
2378 2379 2380
		return -EINVAL;
	}

2381 2382
	if (eeval & AR5416_OPFLAGS_11A)
		pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
2383

2384 2385
	if (eeval & AR5416_OPFLAGS_11G)
		pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
S
Sujith 已提交
2386

2387 2388
	if (AR_SREV_9485(ah) || AR_SREV_9285(ah) || AR_SREV_9330(ah))
		chip_chainmask = 1;
2389 2390
	else if (AR_SREV_9462(ah))
		chip_chainmask = 3;
2391 2392 2393 2394 2395 2396 2397
	else if (!AR_SREV_9280_20_OR_LATER(ah))
		chip_chainmask = 7;
	else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
		chip_chainmask = 3;
	else
		chip_chainmask = 7;

S
Sujith 已提交
2398
	pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2399 2400 2401 2402
	/*
	 * For AR9271 we will temporarilly uses the rx chainmax as read from
	 * the EEPROM.
	 */
2403
	if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2404 2405 2406
	    !(eeval & AR5416_OPFLAGS_11A) &&
	    !(AR_SREV_9271(ah)))
		/* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2407
		pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2408 2409
	else if (AR_SREV_9100(ah))
		pCap->rx_chainmask = 0x7;
2410
	else
2411
		/* Use rx_chainmask from EEPROM. */
2412
		pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2413

2414 2415
	pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
	pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
2416 2417
	ah->txchainmask = pCap->tx_chainmask;
	ah->rxchainmask = pCap->rx_chainmask;
2418

2419
	ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2420

2421 2422 2423 2424
	/* enable key search for every frame in an aggregate */
	if (AR_SREV_9300_20_OR_LATER(ah))
		ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;

2425 2426
	common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;

2427
	if (ah->hw_version.devid != AR2427_DEVID_PCIE)
S
Sujith 已提交
2428 2429 2430
		pCap->hw_caps |= ATH9K_HW_CAP_HT;
	else
		pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2431

2432 2433
	if (AR_SREV_9271(ah))
		pCap->num_gpio_pins = AR9271_NUM_GPIO;
S
Sujith 已提交
2434 2435
	else if (AR_DEVID_7010(ah))
		pCap->num_gpio_pins = AR7010_NUM_GPIO;
2436 2437 2438 2439
	else if (AR_SREV_9300_20_OR_LATER(ah))
		pCap->num_gpio_pins = AR9300_NUM_GPIO;
	else if (AR_SREV_9287_11_OR_LATER(ah))
		pCap->num_gpio_pins = AR9287_NUM_GPIO;
2440
	else if (AR_SREV_9285_12_OR_LATER(ah))
2441
		pCap->num_gpio_pins = AR9285_NUM_GPIO;
2442
	else if (AR_SREV_9280_20_OR_LATER(ah))
S
Sujith 已提交
2443 2444 2445
		pCap->num_gpio_pins = AR928X_NUM_GPIO;
	else
		pCap->num_gpio_pins = AR_NUM_GPIO;
2446

2447
	if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
S
Sujith 已提交
2448
		pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2449
	else
S
Sujith 已提交
2450
		pCap->rts_aggr_limit = (8 * 1024);
2451

2452
#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2453 2454 2455 2456 2457 2458
	ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
	if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
		ah->rfkill_gpio =
			MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
		ah->rfkill_polarity =
			MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
S
Sujith 已提交
2459 2460

		pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2461
	}
S
Sujith 已提交
2462
#endif
2463
	if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
2464 2465 2466
		pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
	else
		pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2467

2468
	if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
S
Sujith 已提交
2469 2470 2471
		pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
	else
		pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2472

2473
	if (AR_SREV_9300_20_OR_LATER(ah)) {
2474
		pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
2475
		if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah))
2476 2477
			pCap->hw_caps |= ATH9K_HW_CAP_LDPC;

2478 2479 2480
		pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
		pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
		pCap->rx_status_len = sizeof(struct ar9003_rxs);
2481
		pCap->tx_desc_len = sizeof(struct ar9003_txc);
2482
		pCap->txs_len = sizeof(struct ar9003_txs);
2483 2484
		if (!ah->config.paprd_disable &&
		    ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2485
			pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2486 2487
	} else {
		pCap->tx_desc_len = sizeof(struct ath_desc);
2488
		if (AR_SREV_9280_20(ah))
2489
			pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2490
	}
2491

2492 2493 2494
	if (AR_SREV_9300_20_OR_LATER(ah))
		pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;

2495 2496 2497
	if (AR_SREV_9300_20_OR_LATER(ah))
		ah->ent_mode = REG_READ(ah, AR_ENT_OTP);

2498
	if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
2499 2500
		pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;

2501 2502 2503 2504 2505 2506 2507
	if (AR_SREV_9285(ah))
		if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
			ant_div_ctl1 =
				ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
			if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
				pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
		}
2508 2509 2510 2511 2512 2513
	if (AR_SREV_9300_20_OR_LATER(ah)) {
		if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
			pCap->hw_caps |= ATH9K_HW_CAP_APM;
	}


2514
	if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529
		ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
		/*
		 * enable the diversity-combining algorithm only when
		 * both enable_lna_div and enable_fast_div are set
		 *		Table for Diversity
		 * ant_div_alt_lnaconf		bit 0-1
		 * ant_div_main_lnaconf		bit 2-3
		 * ant_div_alt_gaintb		bit 4
		 * ant_div_main_gaintb		bit 5
		 * enable_ant_div_lnadiv	bit 6
		 * enable_ant_fast_div		bit 7
		 */
		if ((ant_div_ctl1 >> 0x6) == 0x3)
			pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
	}
2530

2531 2532 2533 2534 2535
	if (AR_SREV_9485_10(ah)) {
		pCap->pcie_lcr_extsync_en = true;
		pCap->pcie_lcr_offset = 0x80;
	}

Z
Zefir Kurtisi 已提交
2536 2537 2538
	if (ath9k_hw_dfs_tested(ah))
		pCap->hw_caps |= ATH9K_HW_CAP_DFS;

2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550
	tx_chainmask = pCap->tx_chainmask;
	rx_chainmask = pCap->rx_chainmask;
	while (tx_chainmask || rx_chainmask) {
		if (tx_chainmask & BIT(0))
			pCap->max_txchains++;
		if (rx_chainmask & BIT(0))
			pCap->max_rxchains++;

		tx_chainmask >>= 1;
		rx_chainmask >>= 1;
	}

2551 2552
	if (AR_SREV_9300_20_OR_LATER(ah)) {
		ah->enabled_cals |= TX_IQ_CAL;
2553
		if (AR_SREV_9485_OR_LATER(ah))
2554 2555
			ah->enabled_cals |= TX_IQ_ON_AGC_CAL;
	}
2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566

	if (AR_SREV_9462(ah)) {

		if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
			pCap->hw_caps |= ATH9K_HW_CAP_MCI;

		if (AR_SREV_9462_20(ah))
			pCap->hw_caps |= ATH9K_HW_CAP_RTT;

	}

2567

2568
	return 0;
2569 2570
}

S
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2571 2572 2573
/****************************/
/* GPIO / RFKILL / Antennae */
/****************************/
2574

2575
static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
S
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2576 2577 2578 2579
					 u32 gpio, u32 type)
{
	int addr;
	u32 gpio_shift, tmp;
2580

S
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2581 2582 2583 2584 2585 2586
	if (gpio > 11)
		addr = AR_GPIO_OUTPUT_MUX3;
	else if (gpio > 5)
		addr = AR_GPIO_OUTPUT_MUX2;
	else
		addr = AR_GPIO_OUTPUT_MUX1;
2587

S
Sujith 已提交
2588
	gpio_shift = (gpio % 6) * 5;
2589

S
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2590 2591 2592 2593
	if (AR_SREV_9280_20_OR_LATER(ah)
	    || (addr != AR_GPIO_OUTPUT_MUX1)) {
		REG_RMW(ah, addr, (type << gpio_shift),
			(0x1f << gpio_shift));
2594
	} else {
S
Sujith 已提交
2595 2596 2597 2598 2599
		tmp = REG_READ(ah, addr);
		tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
		tmp &= ~(0x1f << gpio_shift);
		tmp |= (type << gpio_shift);
		REG_WRITE(ah, addr, tmp);
2600 2601 2602
	}
}

2603
void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2604
{
S
Sujith 已提交
2605
	u32 gpio_shift;
2606

2607
	BUG_ON(gpio >= ah->caps.num_gpio_pins);
2608

S
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2609 2610 2611 2612 2613 2614 2615
	if (AR_DEVID_7010(ah)) {
		gpio_shift = gpio;
		REG_RMW(ah, AR7010_GPIO_OE,
			(AR7010_GPIO_OE_AS_INPUT << gpio_shift),
			(AR7010_GPIO_OE_MASK << gpio_shift));
		return;
	}
2616

S
Sujith 已提交
2617
	gpio_shift = gpio << 1;
S
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2618 2619 2620 2621
	REG_RMW(ah,
		AR_GPIO_OE_OUT,
		(AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
		(AR_GPIO_OE_OUT_DRV << gpio_shift));
2622
}
2623
EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2624

2625
u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2626
{
2627 2628 2629
#define MS_REG_READ(x, y) \
	(MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))

2630
	if (gpio >= ah->caps.num_gpio_pins)
S
Sujith 已提交
2631
		return 0xffffffff;
2632

S
Sujith 已提交
2633 2634 2635 2636 2637
	if (AR_DEVID_7010(ah)) {
		u32 val;
		val = REG_READ(ah, AR7010_GPIO_IN);
		return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
	} else if (AR_SREV_9300_20_OR_LATER(ah))
2638 2639
		return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
			AR_GPIO_BIT(gpio)) != 0;
2640
	else if (AR_SREV_9271(ah))
2641
		return MS_REG_READ(AR9271, gpio) != 0;
2642
	else if (AR_SREV_9287_11_OR_LATER(ah))
2643
		return MS_REG_READ(AR9287, gpio) != 0;
2644
	else if (AR_SREV_9285_12_OR_LATER(ah))
2645
		return MS_REG_READ(AR9285, gpio) != 0;
2646
	else if (AR_SREV_9280_20_OR_LATER(ah))
2647 2648 2649
		return MS_REG_READ(AR928X, gpio) != 0;
	else
		return MS_REG_READ(AR, gpio) != 0;
2650
}
2651
EXPORT_SYMBOL(ath9k_hw_gpio_get);
2652

2653
void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
S
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2654
			 u32 ah_signal_type)
2655
{
S
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2656
	u32 gpio_shift;
2657

S
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2658 2659 2660 2661 2662 2663 2664
	if (AR_DEVID_7010(ah)) {
		gpio_shift = gpio;
		REG_RMW(ah, AR7010_GPIO_OE,
			(AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
			(AR7010_GPIO_OE_MASK << gpio_shift));
		return;
	}
2665

S
Sujith 已提交
2666
	ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
S
Sujith 已提交
2667 2668 2669 2670 2671
	gpio_shift = 2 * gpio;
	REG_RMW(ah,
		AR_GPIO_OE_OUT,
		(AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
		(AR_GPIO_OE_OUT_DRV << gpio_shift));
2672
}
2673
EXPORT_SYMBOL(ath9k_hw_cfg_output);
2674

2675
void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2676
{
S
Sujith 已提交
2677 2678 2679 2680 2681 2682 2683
	if (AR_DEVID_7010(ah)) {
		val = val ? 0 : 1;
		REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
			AR_GPIO_BIT(gpio));
		return;
	}

2684 2685 2686
	if (AR_SREV_9271(ah))
		val = ~val;

S
Sujith 已提交
2687 2688
	REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
		AR_GPIO_BIT(gpio));
2689
}
2690
EXPORT_SYMBOL(ath9k_hw_set_gpio);
2691

2692
void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2693
{
S
Sujith 已提交
2694
	REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2695
}
2696
EXPORT_SYMBOL(ath9k_hw_setantenna);
2697

S
Sujith 已提交
2698 2699 2700 2701
/*********************/
/* General Operation */
/*********************/

2702
u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2703
{
S
Sujith 已提交
2704 2705
	u32 bits = REG_READ(ah, AR_RX_FILTER);
	u32 phybits = REG_READ(ah, AR_PHY_ERR);
2706

S
Sujith 已提交
2707 2708 2709 2710
	if (phybits & AR_PHY_ERR_RADAR)
		bits |= ATH9K_RX_FILTER_PHYRADAR;
	if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
		bits |= ATH9K_RX_FILTER_PHYERR;
S
Sujith 已提交
2711

S
Sujith 已提交
2712
	return bits;
2713
}
2714
EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2715

2716
void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2717
{
S
Sujith 已提交
2718
	u32 phybits;
2719

S
Sujith 已提交
2720 2721
	ENABLE_REGWRITE_BUFFER(ah);

2722
	if (AR_SREV_9462(ah))
2723 2724
		bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;

S
Sujith 已提交
2725 2726
	REG_WRITE(ah, AR_RX_FILTER, bits);

S
Sujith 已提交
2727 2728 2729 2730 2731 2732
	phybits = 0;
	if (bits & ATH9K_RX_FILTER_PHYRADAR)
		phybits |= AR_PHY_ERR_RADAR;
	if (bits & ATH9K_RX_FILTER_PHYERR)
		phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
	REG_WRITE(ah, AR_PHY_ERR, phybits);
2733

S
Sujith 已提交
2734
	if (phybits)
2735
		REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
S
Sujith 已提交
2736
	else
2737
		REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
S
Sujith 已提交
2738 2739

	REGWRITE_BUFFER_FLUSH(ah);
S
Sujith 已提交
2740
}
2741
EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2742

2743
bool ath9k_hw_phy_disable(struct ath_hw *ah)
S
Sujith 已提交
2744
{
2745 2746 2747 2748
	if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
		return false;

	ath9k_hw_init_pll(ah, NULL);
2749
	ah->htc_reset_init = true;
2750
	return true;
S
Sujith 已提交
2751
}
2752
EXPORT_SYMBOL(ath9k_hw_phy_disable);
2753

2754
bool ath9k_hw_disable(struct ath_hw *ah)
S
Sujith 已提交
2755
{
2756
	if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
S
Sujith 已提交
2757
		return false;
2758

2759 2760 2761 2762 2763
	if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
		return false;

	ath9k_hw_init_pll(ah, NULL);
	return true;
2764
}
2765
EXPORT_SYMBOL(ath9k_hw_disable);
2766

2767 2768 2769 2770 2771 2772 2773 2774 2775 2776 2777 2778
static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
{
	enum eeprom_param gain_param;

	if (IS_CHAN_2GHZ(chan))
		gain_param = EEP_ANTENNA_GAIN_2G;
	else
		gain_param = EEP_ANTENNA_GAIN_5G;

	return ah->eep_ops->get_eeprom(ah, gain_param);
}

2779 2780
void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
			    bool test)
2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800
{
	struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
	struct ieee80211_channel *channel;
	int chan_pwr, new_pwr, max_gain;
	int ant_gain, ant_reduction = 0;

	if (!chan)
		return;

	channel = chan->chan;
	chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
	new_pwr = min_t(int, chan_pwr, reg->power_limit);
	max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;

	ant_gain = get_antenna_gain(ah, chan);
	if (ant_gain > max_gain)
		ant_reduction = ant_gain - max_gain;

	ah->eep_ops->set_txpower(ah, chan,
				 ath9k_regd_get_ctl(reg, chan),
2801
				 ant_reduction, new_pwr, test);
2802 2803
}

2804
void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2805
{
2806
	struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2807
	struct ath9k_channel *chan = ah->curchan;
2808
	struct ieee80211_channel *channel = chan->chan;
2809

D
Dan Carpenter 已提交
2810
	reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
2811
	if (test)
2812
		channel->max_power = MAX_RATE_POWER / 2;
2813

2814
	ath9k_hw_apply_txpower(ah, chan, test);
2815

2816 2817
	if (test)
		channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
2818
}
2819
EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2820

2821
void ath9k_hw_setopmode(struct ath_hw *ah)
2822
{
2823
	ath9k_hw_set_operating_mode(ah, ah->opmode);
2824
}
2825
EXPORT_SYMBOL(ath9k_hw_setopmode);
2826

2827
void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2828
{
S
Sujith 已提交
2829 2830
	REG_WRITE(ah, AR_MCAST_FIL0, filter0);
	REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2831
}
2832
EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2833

2834
void ath9k_hw_write_associd(struct ath_hw *ah)
2835
{
2836 2837 2838 2839 2840
	struct ath_common *common = ath9k_hw_common(ah);

	REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
	REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
		  ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2841
}
2842
EXPORT_SYMBOL(ath9k_hw_write_associd);
2843

2844 2845
#define ATH9K_MAX_TSF_READ 10

2846
u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2847
{
2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858
	u32 tsf_lower, tsf_upper1, tsf_upper2;
	int i;

	tsf_upper1 = REG_READ(ah, AR_TSF_U32);
	for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
		tsf_lower = REG_READ(ah, AR_TSF_L32);
		tsf_upper2 = REG_READ(ah, AR_TSF_U32);
		if (tsf_upper2 == tsf_upper1)
			break;
		tsf_upper1 = tsf_upper2;
	}
2859

2860
	WARN_ON( i == ATH9K_MAX_TSF_READ );
2861

2862
	return (((u64)tsf_upper1 << 32) | tsf_lower);
S
Sujith 已提交
2863
}
2864
EXPORT_SYMBOL(ath9k_hw_gettsf64);
2865

2866
void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2867 2868
{
	REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
A
Alina Friedrichsen 已提交
2869
	REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2870
}
2871
EXPORT_SYMBOL(ath9k_hw_settsf64);
2872

2873
void ath9k_hw_reset_tsf(struct ath_hw *ah)
S
Sujith 已提交
2874
{
2875 2876
	if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
			   AH_TSF_WRITE_TIMEOUT))
2877
		ath_dbg(ath9k_hw_common(ah), RESET,
J
Joe Perches 已提交
2878
			"AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2879

S
Sujith 已提交
2880 2881
	REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
}
2882
EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2883

S
Sujith 已提交
2884
void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
S
Sujith 已提交
2885 2886
{
	if (setting)
2887
		ah->misc_mode |= AR_PCU_TX_ADD_TSF;
S
Sujith 已提交
2888
	else
2889
		ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
S
Sujith 已提交
2890
}
2891
EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2892

L
Luis R. Rodriguez 已提交
2893
void ath9k_hw_set11nmac2040(struct ath_hw *ah)
S
Sujith 已提交
2894
{
L
Luis R. Rodriguez 已提交
2895
	struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
S
Sujith 已提交
2896 2897
	u32 macmode;

L
Luis R. Rodriguez 已提交
2898
	if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
S
Sujith 已提交
2899 2900 2901
		macmode = AR_2040_JOINED_RX_CLEAR;
	else
		macmode = 0;
2902

S
Sujith 已提交
2903
	REG_WRITE(ah, AR_2040_MODE, macmode);
2904
}
2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950

/* HW Generic timers configuration */

static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
{
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
	{AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
				AR_NDP2_TIMER_MODE, 0x0002},
	{AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
				AR_NDP2_TIMER_MODE, 0x0004},
	{AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
				AR_NDP2_TIMER_MODE, 0x0008},
	{AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
				AR_NDP2_TIMER_MODE, 0x0010},
	{AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
				AR_NDP2_TIMER_MODE, 0x0020},
	{AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
				AR_NDP2_TIMER_MODE, 0x0040},
	{AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
				AR_NDP2_TIMER_MODE, 0x0080}
};

/* HW generic timer primitives */

/* compute and clear index of rightmost 1 */
static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
{
	u32 b;

	b = *mask;
	b &= (0-b);
	*mask &= ~b;
	b *= debruijn32;
	b >>= 27;

	return timer_table->gen_timer_index[b];
}

2951
u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2952 2953 2954
{
	return REG_READ(ah, AR_TSF_L32);
}
2955
EXPORT_SYMBOL(ath9k_hw_gettsf32);
2956 2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968

struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
					  void (*trigger)(void *),
					  void (*overflow)(void *),
					  void *arg,
					  u8 timer_index)
{
	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
	struct ath_gen_timer *timer;

	timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);

	if (timer == NULL) {
2969 2970 2971
		ath_err(ath9k_hw_common(ah),
			"Failed to allocate memory for hw timer[%d]\n",
			timer_index);
2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982 2983
		return NULL;
	}

	/* allocate a hardware generic timer slot */
	timer_table->timers[timer_index] = timer;
	timer->index = timer_index;
	timer->trigger = trigger;
	timer->overflow = overflow;
	timer->arg = arg;

	return timer;
}
2984
EXPORT_SYMBOL(ath_gen_timer_alloc);
2985

2986 2987
void ath9k_hw_gen_timer_start(struct ath_hw *ah,
			      struct ath_gen_timer *timer,
2988
			      u32 trig_timeout,
2989
			      u32 timer_period)
2990 2991
{
	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2992
	u32 tsf, timer_next;
2993 2994 2995 2996 2997 2998 2999

	BUG_ON(!timer_period);

	set_bit(timer->index, &timer_table->timer_mask.timer_bits);

	tsf = ath9k_hw_gettsf32(ah);

3000 3001
	timer_next = tsf + trig_timeout;

3002
	ath_dbg(ath9k_hw_common(ah), HWTIMER,
J
Joe Perches 已提交
3003 3004
		"current tsf %x period %x timer_next %x\n",
		tsf, timer_period, timer_next);
3005 3006 3007 3008 3009 3010 3011 3012 3013 3014 3015

	/*
	 * Program generic timer registers
	 */
	REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
		 timer_next);
	REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
		  timer_period);
	REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
		    gen_tmr_configuration[timer->index].mode_mask);

3016
	if (AR_SREV_9462(ah)) {
3017
		/*
3018
		 * Starting from AR9462, each generic timer can select which tsf
3019 3020 3021 3022 3023 3024 3025 3026 3027 3028 3029
		 * to use. But we still follow the old rule, 0 - 7 use tsf and
		 * 8 - 15  use tsf2.
		 */
		if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
			REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
				       (1 << timer->index));
		else
			REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
				       (1 << timer->index));
	}

3030 3031 3032 3033 3034
	/* Enable both trigger and thresh interrupt masks */
	REG_SET_BIT(ah, AR_IMR_S5,
		(SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
		SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
}
3035
EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3036

3037
void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3038 3039 3040 3041 3042 3043 3044 3045 3046 3047 3048 3049 3050 3051 3052 3053 3054 3055 3056
{
	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;

	if ((timer->index < AR_FIRST_NDP_TIMER) ||
		(timer->index >= ATH_MAX_GEN_TIMER)) {
		return;
	}

	/* Clear generic timer enable bits. */
	REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
			gen_tmr_configuration[timer->index].mode_mask);

	/* Disable both trigger and thresh interrupt masks */
	REG_CLR_BIT(ah, AR_IMR_S5,
		(SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
		SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));

	clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
}
3057
EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3058 3059 3060 3061 3062 3063 3064 3065 3066

void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
{
	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;

	/* free the hardware generic timer slot */
	timer_table->timers[timer->index] = NULL;
	kfree(timer);
}
3067
EXPORT_SYMBOL(ath_gen_timer_free);
3068 3069 3070 3071 3072 3073 3074 3075

/*
 * Generic Timer Interrupts handling
 */
void ath_gen_timer_isr(struct ath_hw *ah)
{
	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
	struct ath_gen_timer *timer;
3076
	struct ath_common *common = ath9k_hw_common(ah);
3077 3078 3079 3080 3081 3082 3083 3084 3085 3086 3087 3088 3089 3090
	u32 trigger_mask, thresh_mask, index;

	/* get hardware generic timer interrupt status */
	trigger_mask = ah->intr_gen_timer_trigger;
	thresh_mask = ah->intr_gen_timer_thresh;
	trigger_mask &= timer_table->timer_mask.val;
	thresh_mask &= timer_table->timer_mask.val;

	trigger_mask &= ~thresh_mask;

	while (thresh_mask) {
		index = rightmost_index(timer_table, &thresh_mask);
		timer = timer_table->timers[index];
		BUG_ON(!timer);
3091 3092
		ath_dbg(common, HWTIMER, "TSF overflow for Gen timer %d\n",
			index);
3093 3094 3095 3096 3097 3098 3099
		timer->overflow(timer->arg);
	}

	while (trigger_mask) {
		index = rightmost_index(timer_table, &trigger_mask);
		timer = timer_table->timers[index];
		BUG_ON(!timer);
3100
		ath_dbg(common, HWTIMER,
J
Joe Perches 已提交
3101
			"Gen timer[%d] trigger\n", index);
3102 3103 3104
		timer->trigger(timer->arg);
	}
}
3105
EXPORT_SYMBOL(ath_gen_timer_isr);
3106

3107 3108 3109 3110
/********/
/* HTC  */
/********/

3111 3112 3113 3114 3115 3116 3117 3118 3119 3120 3121 3122
static struct {
	u32 version;
	const char * name;
} ath_mac_bb_names[] = {
	/* Devices with external radios */
	{ AR_SREV_VERSION_5416_PCI,	"5416" },
	{ AR_SREV_VERSION_5416_PCIE,	"5418" },
	{ AR_SREV_VERSION_9100,		"9100" },
	{ AR_SREV_VERSION_9160,		"9160" },
	/* Single-chip solutions */
	{ AR_SREV_VERSION_9280,		"9280" },
	{ AR_SREV_VERSION_9285,		"9285" },
3123 3124
	{ AR_SREV_VERSION_9287,         "9287" },
	{ AR_SREV_VERSION_9271,         "9271" },
3125
	{ AR_SREV_VERSION_9300,         "9300" },
3126
	{ AR_SREV_VERSION_9330,         "9330" },
3127
	{ AR_SREV_VERSION_9340,		"9340" },
3128
	{ AR_SREV_VERSION_9485,         "9485" },
3129
	{ AR_SREV_VERSION_9462,         "9462" },
3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146
};

/* For devices with external radios */
static struct {
	u16 version;
	const char * name;
} ath_rf_names[] = {
	{ 0,				"5133" },
	{ AR_RAD5133_SREV_MAJOR,	"5133" },
	{ AR_RAD5122_SREV_MAJOR,	"5122" },
	{ AR_RAD2133_SREV_MAJOR,	"2133" },
	{ AR_RAD2122_SREV_MAJOR,	"2122" }
};

/*
 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
 */
3147
static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163
{
	int i;

	for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
		if (ath_mac_bb_names[i].version == mac_bb_version) {
			return ath_mac_bb_names[i].name;
		}
	}

	return "????";
}

/*
 * Return the RF name. "????" is returned if the RF is unknown.
 * Used for devices with external radios.
 */
3164
static const char *ath9k_hw_rf_name(u16 rf_version)
3165 3166 3167 3168 3169 3170 3171 3172 3173 3174 3175
{
	int i;

	for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
		if (ath_rf_names[i].version == rf_version) {
			return ath_rf_names[i].name;
		}
	}

	return "????";
}
3176 3177 3178 3179 3180 3181

void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
{
	int used;

	/* chipsets >= AR9280 are single-chip */
3182
	if (AR_SREV_9280_20_OR_LATER(ah)) {
3183 3184 3185 3186 3187 3188 3189 3190 3191 3192 3193 3194 3195 3196 3197 3198 3199 3200
		used = snprintf(hw_name, len,
			       "Atheros AR%s Rev:%x",
			       ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
			       ah->hw_version.macRev);
	}
	else {
		used = snprintf(hw_name, len,
			       "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
			       ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
			       ah->hw_version.macRev,
			       ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
						AR_RADIO_SREV_MAJOR)),
			       ah->hw_version.phyRev);
	}

	hw_name[used] = '\0';
}
EXPORT_SYMBOL(ath9k_hw_name);