hw.c 64.9 KB
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/*
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 * Copyright (c) 2008-2010 Atheros Communications Inc.
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 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <linux/io.h>
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#include <linux/slab.h>
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#include <asm/unaligned.h>

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#include "hw.h"
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#include "hw-ops.h"
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#include "rc.h"
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#include "ar9003_mac.h"
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static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
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MODULE_AUTHOR("Atheros Communications");
MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
MODULE_LICENSE("Dual BSD/GPL");

static int __init ath9k_init(void)
{
	return 0;
}
module_init(ath9k_init);

static void __exit ath9k_exit(void)
{
	return;
}
module_exit(ath9k_exit);

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/* Private hardware callbacks */

static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
{
	ath9k_hw_private_ops(ah)->init_cal_settings(ah);
}

static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
{
	ath9k_hw_private_ops(ah)->init_mode_regs(ah);
}

static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
{
	struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);

	return priv_ops->macversion_supported(ah->hw_version.macVersion);
}

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static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
					struct ath9k_channel *chan)
{
	return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
}

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static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
{
	if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
		return;

	ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
}

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static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
{
	/* You will not have this callback if using the old ANI */
	if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
		return;

	ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
}

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/********************/
/* Helper Functions */
/********************/
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static void ath9k_hw_set_clockrate(struct ath_hw *ah)
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{
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	struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
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	struct ath_common *common = ath9k_hw_common(ah);
	unsigned int clockrate;
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	if (!ah->curchan) /* should really check for CCK instead */
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		clockrate = ATH9K_CLOCK_RATE_CCK;
	else if (conf->channel->band == IEEE80211_BAND_2GHZ)
		clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
	else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
		clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
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	else
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		clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;

	if (conf_is_ht40(conf))
		clockrate *= 2;

	common->clockrate = clockrate;
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}

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static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
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{
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	struct ath_common *common = ath9k_hw_common(ah);
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	return usecs * common->clockrate;
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}
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bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
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{
	int i;

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	BUG_ON(timeout < AH_TIME_QUANTUM);

	for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
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		if ((REG_READ(ah, reg) & mask) == val)
			return true;

		udelay(AH_TIME_QUANTUM);
	}
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	ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY,
		"timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
		timeout, reg, REG_READ(ah, reg), mask, val);
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	return false;
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}
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EXPORT_SYMBOL(ath9k_hw_wait);
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u32 ath9k_hw_reverse_bits(u32 val, u32 n)
{
	u32 retval;
	int i;

	for (i = 0, retval = 0; i < n; i++) {
		retval = (retval << 1) | (val & 1);
		val >>= 1;
	}
	return retval;
}

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bool ath9k_get_channel_edges(struct ath_hw *ah,
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			     u16 flags, u16 *low,
			     u16 *high)
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{
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	struct ath9k_hw_capabilities *pCap = &ah->caps;
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	if (flags & CHANNEL_5GHZ) {
		*low = pCap->low_5ghz_chan;
		*high = pCap->high_5ghz_chan;
		return true;
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	}
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	if ((flags & CHANNEL_2GHZ)) {
		*low = pCap->low_2ghz_chan;
		*high = pCap->high_2ghz_chan;
		return true;
	}
	return false;
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}

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u16 ath9k_hw_computetxtime(struct ath_hw *ah,
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			   u8 phy, int kbps,
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			   u32 frameLen, u16 rateix,
			   bool shortPreamble)
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{
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	u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
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	if (kbps == 0)
		return 0;
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	switch (phy) {
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	case WLAN_RC_PHY_CCK:
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		phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
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		if (shortPreamble)
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			phyTime >>= 1;
		numBits = frameLen << 3;
		txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
		break;
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	case WLAN_RC_PHY_OFDM:
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		if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
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			bitsPerSymbol =	(kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
			numBits = OFDM_PLCP_BITS + (frameLen << 3);
			numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
			txTime = OFDM_SIFS_TIME_QUARTER
				+ OFDM_PREAMBLE_TIME_QUARTER
				+ (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
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		} else if (ah->curchan &&
			   IS_CHAN_HALF_RATE(ah->curchan)) {
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			bitsPerSymbol =	(kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
			numBits = OFDM_PLCP_BITS + (frameLen << 3);
			numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
			txTime = OFDM_SIFS_TIME_HALF +
				OFDM_PREAMBLE_TIME_HALF
				+ (numSymbols * OFDM_SYMBOL_TIME_HALF);
		} else {
			bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
			numBits = OFDM_PLCP_BITS + (frameLen << 3);
			numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
			txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
				+ (numSymbols * OFDM_SYMBOL_TIME);
		}
		break;
	default:
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		ath_err(ath9k_hw_common(ah),
			"Unknown phy %u (rate ix %u)\n", phy, rateix);
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		txTime = 0;
		break;
	}
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	return txTime;
}
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EXPORT_SYMBOL(ath9k_hw_computetxtime);
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void ath9k_hw_get_channel_centers(struct ath_hw *ah,
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				  struct ath9k_channel *chan,
				  struct chan_centers *centers)
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{
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	int8_t extoff;
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	if (!IS_CHAN_HT40(chan)) {
		centers->ctl_center = centers->ext_center =
			centers->synth_center = chan->channel;
		return;
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	}

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	if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
	    (chan->chanmode == CHANNEL_G_HT40PLUS)) {
		centers->synth_center =
			chan->channel + HT40_CHANNEL_CENTER_SHIFT;
		extoff = 1;
	} else {
		centers->synth_center =
			chan->channel - HT40_CHANNEL_CENTER_SHIFT;
		extoff = -1;
	}
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	centers->ctl_center =
		centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
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	/* 25 MHz spacing is supported by hw but not on upper layers */
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	centers->ext_center =
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		centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
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}

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/******************/
/* Chip Revisions */
/******************/

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static void ath9k_hw_read_revisions(struct ath_hw *ah)
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{
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	u32 val;
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	val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
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	if (val == 0xFF) {
		val = REG_READ(ah, AR_SREV);
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		ah->hw_version.macVersion =
			(val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
		ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
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		ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
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	} else {
		if (!AR_SREV_9100(ah))
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			ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
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		ah->hw_version.macRev = val & AR_SREV_REVISION;
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		if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
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			ah->is_pciexpress = true;
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	}
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}

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/************************************/
/* HW Attach, Detach, Init Routines */
/************************************/

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static void ath9k_hw_disablepcie(struct ath_hw *ah)
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{
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	if (AR_SREV_9100(ah))
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		return;
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	ENABLE_REGWRITE_BUFFER(ah);

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	REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
	REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
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	REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
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	REGWRITE_BUFFER_FLUSH(ah);
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}

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/* This should work for all families including legacy */
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static bool ath9k_hw_chip_test(struct ath_hw *ah)
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{
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	struct ath_common *common = ath9k_hw_common(ah);
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	u32 regAddr[2] = { AR_STA_ID0 };
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	u32 regHold[2];
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	static const u32 patternData[4] = {
		0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
	};
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	int i, j, loop_max;
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	if (!AR_SREV_9300_20_OR_LATER(ah)) {
		loop_max = 2;
		regAddr[1] = AR_PHY_BASE + (8 << 2);
	} else
		loop_max = 1;

	for (i = 0; i < loop_max; i++) {
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		u32 addr = regAddr[i];
		u32 wrData, rdData;
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		regHold[i] = REG_READ(ah, addr);
		for (j = 0; j < 0x100; j++) {
			wrData = (j << 16) | j;
			REG_WRITE(ah, addr, wrData);
			rdData = REG_READ(ah, addr);
			if (rdData != wrData) {
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				ath_err(common,
					"address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
					addr, wrData, rdData);
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				return false;
			}
		}
		for (j = 0; j < 4; j++) {
			wrData = patternData[j];
			REG_WRITE(ah, addr, wrData);
			rdData = REG_READ(ah, addr);
			if (wrData != rdData) {
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				ath_err(common,
					"address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
					addr, wrData, rdData);
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				return false;
			}
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		}
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		REG_WRITE(ah, regAddr[i], regHold[i]);
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	}
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	udelay(100);
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	return true;
}

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static void ath9k_hw_init_config(struct ath_hw *ah)
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{
	int i;
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	ah->config.dma_beacon_response_time = 2;
	ah->config.sw_beacon_response_time = 10;
	ah->config.additional_swba_backoff = 0;
	ah->config.ack_6mb = 0x0;
	ah->config.cwm_ignore_extcca = 0;
	ah->config.pcie_powersave_enable = 0;
	ah->config.pcie_clock_req = 0;
	ah->config.pcie_waen = 0;
	ah->config.analog_shiftreg = 1;
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	ah->config.enable_ani = true;
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	for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
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		ah->config.spurchans[i][0] = AR_NO_SPUR;
		ah->config.spurchans[i][1] = AR_NO_SPUR;
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	}

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	if (ah->hw_version.devid != AR2427_DEVID_PCIE)
		ah->config.ht_enable = 1;
	else
		ah->config.ht_enable = 0;

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	ah->config.rx_intr_mitigation = true;
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	ah->config.pcieSerDesWrite = true;
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	/*
	 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
	 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
	 * This means we use it for all AR5416 devices, and the few
	 * minor PCI AR9280 devices out there.
	 *
	 * Serialization is required because these devices do not handle
	 * well the case of two concurrent reads/writes due to the latency
	 * involved. During one read/write another read/write can be issued
	 * on another CPU while the previous read/write may still be working
	 * on our hardware, if we hit this case the hardware poops in a loop.
	 * We prevent this by serializing reads and writes.
	 *
	 * This issue is not present on PCI-Express devices or pre-AR5416
	 * devices (legacy, 802.11abg).
	 */
	if (num_possible_cpus() > 1)
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		ah->config.serialize_regmode = SER_REG_MODE_AUTO;
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}

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static void ath9k_hw_init_defaults(struct ath_hw *ah)
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{
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	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);

	regulatory->country_code = CTRY_DEFAULT;
	regulatory->power_limit = MAX_RATE_POWER;
	regulatory->tp_scale = ATH9K_TP_SCALE_MAX;

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	ah->hw_version.magic = AR5416_MAGIC;
	ah->hw_version.subvendorid = 0;
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	ah->atim_window = 0;
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	ah->sta_id1_defaults =
		AR_STA_ID1_CRPT_MIC_ENABLE |
		AR_STA_ID1_MCAST_KSRCH;
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	ah->beacon_interval = 100;
	ah->enable_32kHz_clock = DONT_USE_32KHZ;
	ah->slottime = (u32) -1;
	ah->globaltxtimeout = (u32) -1;
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	ah->power_mode = ATH9K_PM_UNDEFINED;
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}

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static int ath9k_hw_init_macaddr(struct ath_hw *ah)
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{
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	struct ath_common *common = ath9k_hw_common(ah);
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	u32 sum;
	int i;
	u16 eeval;
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	static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
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	sum = 0;
	for (i = 0; i < 3; i++) {
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		eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
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		sum += eeval;
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		common->macaddr[2 * i] = eeval >> 8;
		common->macaddr[2 * i + 1] = eeval & 0xff;
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	}
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	if (sum == 0 || sum == 0xffff * 3)
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		return -EADDRNOTAVAIL;

	return 0;
}

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static int ath9k_hw_post_init(struct ath_hw *ah)
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{
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	int ecode;
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	if (!AR_SREV_9271(ah)) {
		if (!ath9k_hw_chip_test(ah))
			return -ENODEV;
	}
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	if (!AR_SREV_9300_20_OR_LATER(ah)) {
		ecode = ar9002_hw_rf_claim(ah);
		if (ecode != 0)
			return ecode;
	}
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	ecode = ath9k_hw_eeprom_init(ah);
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	if (ecode != 0)
		return ecode;
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	ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG,
		"Eeprom VER: %d, REV: %d\n",
		ah->eep_ops->get_eeprom_ver(ah),
		ah->eep_ops->get_eeprom_rev(ah));
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	ecode = ath9k_hw_rf_alloc_ext_banks(ah);
	if (ecode) {
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		ath_err(ath9k_hw_common(ah),
			"Failed allocating banks for external radio\n");
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		ath9k_hw_rf_free_ext_banks(ah);
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		return ecode;
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	}
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	if (!AR_SREV_9100(ah)) {
		ath9k_hw_ani_setup(ah);
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		ath9k_hw_ani_init(ah);
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	}

	return 0;
}

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static void ath9k_hw_attach_ops(struct ath_hw *ah)
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{
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	if (AR_SREV_9300_20_OR_LATER(ah))
		ar9003_hw_attach_ops(ah);
	else
		ar9002_hw_attach_ops(ah);
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}

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/* Called for all hardware families */
static int __ath9k_hw_init(struct ath_hw *ah)
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{
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	struct ath_common *common = ath9k_hw_common(ah);
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	int r = 0;
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	if (ah->hw_version.devid == AR5416_AR9100_DEVID)
		ah->hw_version.macVersion = AR_SREV_VERSION_9100;
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	if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
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		ath_err(common, "Couldn't reset chip\n");
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		return -EIO;
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	}

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	ath9k_hw_init_defaults(ah);
	ath9k_hw_init_config(ah);

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	ath9k_hw_attach_ops(ah);
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	if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
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		ath_err(common, "Couldn't wakeup chip\n");
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		return -EIO;
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	}

	if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
		if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
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		    ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
		     !ah->is_pciexpress)) {
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			ah->config.serialize_regmode =
				SER_REG_MODE_ON;
		} else {
			ah->config.serialize_regmode =
				SER_REG_MODE_OFF;
		}
	}

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	ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
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		ah->config.serialize_regmode);

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	if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
		ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
	else
		ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;

541
	if (!ath9k_hw_macversion_supported(ah)) {
542 543 544
		ath_err(common,
			"Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
			ah->hw_version.macVersion, ah->hw_version.macRev);
545
		return -EOPNOTSUPP;
546 547
	}

548
	if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
549 550
		ah->is_pciexpress = false;

551 552 553 554
	ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
	ath9k_hw_init_cal_settings(ah);

	ah->ani_function = ATH9K_ANI_ALL;
555
	if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
556
		ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
557 558
	if (!AR_SREV_9300_20_OR_LATER(ah))
		ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
559 560 561

	ath9k_hw_init_mode_regs(ah);

562 563 564 565 566 567 568 569 570
	/*
	 * Read back AR_WA into a permanent copy and set bits 14 and 17.
	 * We need to do this to avoid RMW of this register. We cannot
	 * read the reg when chip is asleep.
	 */
	ah->WARegVal = REG_READ(ah, AR_WA);
	ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
			 AR_WA_ASPM_TIMER_BASED_DISABLE);

571
	if (ah->is_pciexpress)
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		ath9k_hw_configpcipowersave(ah, 0, 0);
573 574 575
	else
		ath9k_hw_disablepcie(ah);

576 577
	if (!AR_SREV_9300_20_OR_LATER(ah))
		ar9002_hw_cck_chan14_spread(ah);
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578

579
	r = ath9k_hw_post_init(ah);
580
	if (r)
581
		return r;
582 583

	ath9k_hw_init_mode_gain_regs(ah);
584 585 586 587
	r = ath9k_hw_fill_cap_info(ah);
	if (r)
		return r;

588 589
	r = ath9k_hw_init_macaddr(ah);
	if (r) {
590
		ath_err(common, "Failed to initialize MAC address\n");
591
		return r;
592 593
	}

594
	if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
595
		ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
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	else
597
		ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
598

599
	ah->bb_watchdog_timeout_ms = 25;
600

601 602
	common->state = ATH_HW_INITIALIZED;

603
	return 0;
604 605
}

606
int ath9k_hw_init(struct ath_hw *ah)
607
{
608 609
	int ret;
	struct ath_common *common = ath9k_hw_common(ah);
610

611 612 613 614 615 616 617 618 619
	/* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
	switch (ah->hw_version.devid) {
	case AR5416_DEVID_PCI:
	case AR5416_DEVID_PCIE:
	case AR5416_AR9100_DEVID:
	case AR9160_DEVID_PCI:
	case AR9280_DEVID_PCI:
	case AR9280_DEVID_PCIE:
	case AR9285_DEVID_PCIE:
620 621
	case AR9287_DEVID_PCI:
	case AR9287_DEVID_PCIE:
622
	case AR2427_DEVID_PCIE:
623
	case AR9300_DEVID_PCIE:
624
	case AR9300_DEVID_AR9485_PCIE:
625 626 627 628
		break;
	default:
		if (common->bus_ops->ath_bus_type == ATH_USB)
			break;
629 630
		ath_err(common, "Hardware device ID 0x%04x not supported\n",
			ah->hw_version.devid);
631 632
		return -EOPNOTSUPP;
	}
633

634 635
	ret = __ath9k_hw_init(ah);
	if (ret) {
636 637 638
		ath_err(common,
			"Unable to initialize hardware; initialization status: %d\n",
			ret);
639 640
		return ret;
	}
641

642
	return 0;
643
}
644
EXPORT_SYMBOL(ath9k_hw_init);
645

646
static void ath9k_hw_init_qos(struct ath_hw *ah)
647
{
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	ENABLE_REGWRITE_BUFFER(ah);

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	REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
	REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
652

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	REG_WRITE(ah, AR_QOS_NO_ACK,
		  SM(2, AR_QOS_NO_ACK_TWO_BIT) |
		  SM(5, AR_QOS_NO_ACK_BIT_OFF) |
		  SM(0, AR_QOS_NO_ACK_BYTE_OFF));

	REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
	REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
	REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
	REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
	REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
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663 664

	REGWRITE_BUFFER_FLUSH(ah);
665 666
}

667
static void ath9k_hw_init_pll(struct ath_hw *ah,
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668
			      struct ath9k_channel *chan)
669
{
670
	u32 pll = ath9k_hw_compute_pll_control(ah, chan);
671

672
	REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
673

674 675
	/* Switch the core clock for ar9271 to 117Mhz */
	if (AR_SREV_9271(ah)) {
676 677
		udelay(500);
		REG_WRITE(ah, 0x50040, 0x304);
678 679
	}

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	udelay(RTC_PLL_SETTLE_DELAY);

	REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
683 684
}

685
static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
686
					  enum nl80211_iftype opmode)
687
{
688
	u32 imr_reg = AR_IMR_TXERR |
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689 690 691 692
		AR_IMR_TXURN |
		AR_IMR_RXERR |
		AR_IMR_RXORN |
		AR_IMR_BCNMISC;
693

694 695 696 697 698 699
	if (AR_SREV_9300_20_OR_LATER(ah)) {
		imr_reg |= AR_IMR_RXOK_HP;
		if (ah->config.rx_intr_mitigation)
			imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
		else
			imr_reg |= AR_IMR_RXOK_LP;
700

701 702 703 704 705 706
	} else {
		if (ah->config.rx_intr_mitigation)
			imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
		else
			imr_reg |= AR_IMR_RXOK;
	}
707

708 709 710 711
	if (ah->config.tx_intr_mitigation)
		imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
	else
		imr_reg |= AR_IMR_TXOK;
712

713
	if (opmode == NL80211_IFTYPE_AP)
714
		imr_reg |= AR_IMR_MIB;
715

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716 717
	ENABLE_REGWRITE_BUFFER(ah);

718
	REG_WRITE(ah, AR_IMR, imr_reg);
719 720
	ah->imrs2_reg |= AR_IMR_S2_GTT;
	REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
721

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722 723 724 725 726
	if (!AR_SREV_9100(ah)) {
		REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
		REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
		REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
	}
727

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728 729
	REGWRITE_BUFFER_FLUSH(ah);

730 731 732 733 734 735
	if (AR_SREV_9300_20_OR_LATER(ah)) {
		REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
		REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
		REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
		REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
	}
736 737
}

738
static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
739
{
740 741 742
	u32 val = ath9k_hw_mac_to_clks(ah, us);
	val = min(val, (u32) 0xFFFF);
	REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
743 744
}

745
static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
746
{
747 748 749 750 751 752 753 754 755 756
	u32 val = ath9k_hw_mac_to_clks(ah, us);
	val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
	REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
}

static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
{
	u32 val = ath9k_hw_mac_to_clks(ah, us);
	val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
	REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
757
}
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758

759
static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
760 761
{
	if (tu > 0xFFFF) {
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762 763
		ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
			"bad global tx timeout %u\n", tu);
764
		ah->globaltxtimeout = (u32) -1;
765 766 767
		return false;
	} else {
		REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
768
		ah->globaltxtimeout = tu;
769 770 771 772
		return true;
	}
}

773
void ath9k_hw_init_global_settings(struct ath_hw *ah)
774
{
775 776
	struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
	int acktimeout;
777
	int slottime;
778 779
	int sifstime;

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780 781
	ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
		ah->misc_mode);
782

783
	if (ah->misc_mode != 0)
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		REG_WRITE(ah, AR_PCU_MISC,
785
			  REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
786 787 788 789 790 791

	if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
		sifstime = 16;
	else
		sifstime = 10;

792 793 794
	/* As defined by IEEE 802.11-2007 17.3.8.6 */
	slottime = ah->slottime + 3 * ah->coverage_class;
	acktimeout = slottime + sifstime;
795 796 797 798 799 800 801 802 803 804 805

	/*
	 * Workaround for early ACK timeouts, add an offset to match the
	 * initval's 64us ack timeout value.
	 * This was initially only meant to work around an issue with delayed
	 * BA frames in some implementations, but it has been found to fix ACK
	 * timeout issues in other cases as well.
	 */
	if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
		acktimeout += 64 - sifstime - ah->slottime;

806
	ath9k_hw_setslottime(ah, slottime);
807 808
	ath9k_hw_set_ack_timeout(ah, acktimeout);
	ath9k_hw_set_cts_timeout(ah, acktimeout);
809 810
	if (ah->globaltxtimeout != (u32) -1)
		ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
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811
}
812
EXPORT_SYMBOL(ath9k_hw_init_global_settings);
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813

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814
void ath9k_hw_deinit(struct ath_hw *ah)
S
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815
{
816 817
	struct ath_common *common = ath9k_hw_common(ah);

S
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818
	if (common->state < ATH_HW_INITIALIZED)
819 820
		goto free_hw;

821
	ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
822 823

free_hw:
824
	ath9k_hw_rf_free_ext_banks(ah);
S
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825
}
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826
EXPORT_SYMBOL(ath9k_hw_deinit);
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827 828 829 830 831

/*******/
/* INI */
/*******/

832
u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
833 834 835 836 837 838 839 840 841 842 843 844 845
{
	u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);

	if (IS_CHAN_B(chan))
		ctl |= CTL_11B;
	else if (IS_CHAN_G(chan))
		ctl |= CTL_11G;
	else
		ctl |= CTL_11A;

	return ctl;
}

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846 847 848 849
/****************************************/
/* Reset and Channel Switching Routines */
/****************************************/

850
static inline void ath9k_hw_set_dma(struct ath_hw *ah)
S
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851
{
852
	struct ath_common *common = ath9k_hw_common(ah);
S
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853 854
	u32 regval;

S
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855 856
	ENABLE_REGWRITE_BUFFER(ah);

857 858 859
	/*
	 * set AHB_MODE not to do cacheline prefetches
	*/
860 861 862 863
	if (!AR_SREV_9300_20_OR_LATER(ah)) {
		regval = REG_READ(ah, AR_AHB_MODE);
		REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
	}
S
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864

865 866 867
	/*
	 * let mac dma reads be in 128 byte chunks
	 */
S
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868 869 870
	regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
	REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);

S
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871 872
	REGWRITE_BUFFER_FLUSH(ah);

873 874 875 876 877
	/*
	 * Restore TX Trigger Level to its pre-reset value.
	 * The initial value depends on whether aggregation is enabled, and is
	 * adjusted whenever underruns are detected.
	 */
878 879
	if (!AR_SREV_9300_20_OR_LATER(ah))
		REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
S
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880

S
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881
	ENABLE_REGWRITE_BUFFER(ah);
S
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882

883 884 885
	/*
	 * let mac dma writes be in 128 byte chunks
	 */
S
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886 887 888
	regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
	REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);

889 890 891
	/*
	 * Setup receive FIFO threshold to hold off TX activities
	 */
S
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892 893
	REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);

894 895 896 897 898 899 900 901
	if (AR_SREV_9300_20_OR_LATER(ah)) {
		REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
		REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);

		ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
			ah->caps.rx_status_len);
	}

902 903 904 905
	/*
	 * reduce the number of usable entries in PCU TXBUF to avoid
	 * wrap around issues.
	 */
S
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906
	if (AR_SREV_9285(ah)) {
907 908 909 910
		/* For AR9285 the number of Fifos are reduced to half.
		 * So set the usable tx buf size also to half to
		 * avoid data/delimiter underruns
		 */
S
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911 912
		REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
			  AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
913
	} else if (!AR_SREV_9271(ah)) {
S
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914 915 916
		REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
			  AR_PCU_TXBUF_CTRL_USABLE_SIZE);
	}
917

S
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918 919
	REGWRITE_BUFFER_FLUSH(ah);

920 921
	if (AR_SREV_9300_20_OR_LATER(ah))
		ath9k_hw_reset_txstatus_ring(ah);
S
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922 923
}

924
static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
S
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925 926 927 928 929 930
{
	u32 val;

	val = REG_READ(ah, AR_STA_ID1);
	val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
	switch (opmode) {
931
	case NL80211_IFTYPE_AP:
S
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932 933 934
		REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
			  | AR_STA_ID1_KSRCH_MODE);
		REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
935
		break;
936
	case NL80211_IFTYPE_ADHOC:
937
	case NL80211_IFTYPE_MESH_POINT:
S
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938 939 940
		REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
			  | AR_STA_ID1_KSRCH_MODE);
		REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
941
		break;
942
	case NL80211_IFTYPE_STATION:
S
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943
		REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
944
		break;
945 946 947 948
	default:
		if (ah->is_monitoring)
			REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
		break;
S
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949 950 951
	}
}

952 953
void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
				   u32 *coef_mantissa, u32 *coef_exponent)
S
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954 955 956 957 958 959 960 961 962 963 964 965 966 967 968
{
	u32 coef_exp, coef_man;

	for (coef_exp = 31; coef_exp > 0; coef_exp--)
		if ((coef_scaled >> coef_exp) & 0x1)
			break;

	coef_exp = 14 - (coef_exp - COEF_SCALE_S);

	coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));

	*coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
	*coef_exponent = coef_exp - 16;
}

969
static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
S
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970 971 972 973
{
	u32 rst_flags;
	u32 tmpReg;

974 975 976 977 978 979 980 981
	if (AR_SREV_9100(ah)) {
		u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
		val &= ~AR_RTC_DERIVED_CLK_PERIOD;
		val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
		REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
		(void)REG_READ(ah, AR_RTC_DERIVED_CLK);
	}

S
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982 983
	ENABLE_REGWRITE_BUFFER(ah);

984 985 986 987 988
	if (AR_SREV_9300_20_OR_LATER(ah)) {
		REG_WRITE(ah, AR_WA, ah->WARegVal);
		udelay(10);
	}

S
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989 990 991 992 993 994 995 996 997 998 999
	REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
		  AR_RTC_FORCE_WAKE_ON_INT);

	if (AR_SREV_9100(ah)) {
		rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
			AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
	} else {
		tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
		if (tmpReg &
		    (AR_INTR_SYNC_LOCAL_TIMEOUT |
		     AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1000
			u32 val;
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1001
			REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1002 1003 1004 1005 1006 1007 1008

			val = AR_RC_HOSTIF;
			if (!AR_SREV_9300_20_OR_LATER(ah))
				val |= AR_RC_AHB;
			REG_WRITE(ah, AR_RC, val);

		} else if (!AR_SREV_9300_20_OR_LATER(ah))
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1009 1010 1011 1012 1013 1014 1015
			REG_WRITE(ah, AR_RC, AR_RC_AHB);

		rst_flags = AR_RTC_RC_MAC_WARM;
		if (type == ATH9K_RESET_COLD)
			rst_flags |= AR_RTC_RC_MAC_COLD;
	}

1016
	REG_WRITE(ah, AR_RTC_RC, rst_flags);
S
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1017 1018 1019

	REGWRITE_BUFFER_FLUSH(ah);

S
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1020 1021
	udelay(50);

1022
	REG_WRITE(ah, AR_RTC_RC, 0);
S
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1023
	if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
J
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1024 1025
		ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
			"RTC stuck in MAC reset\n");
S
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1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037
		return false;
	}

	if (!AR_SREV_9100(ah))
		REG_WRITE(ah, AR_RC, 0);

	if (AR_SREV_9100(ah))
		udelay(50);

	return true;
}

1038
static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
S
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1039
{
S
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1040 1041
	ENABLE_REGWRITE_BUFFER(ah);

1042 1043 1044 1045 1046
	if (AR_SREV_9300_20_OR_LATER(ah)) {
		REG_WRITE(ah, AR_WA, ah->WARegVal);
		udelay(10);
	}

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1047 1048 1049
	REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
		  AR_RTC_FORCE_WAKE_ON_INT);

1050
	if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1051 1052
		REG_WRITE(ah, AR_RC, AR_RC_AHB);

1053
	REG_WRITE(ah, AR_RTC_RESET, 0);
1054
	udelay(2);
1055

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1056 1057
	REGWRITE_BUFFER_FLUSH(ah);

1058 1059 1060 1061
	if (!AR_SREV_9300_20_OR_LATER(ah))
		udelay(2);

	if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1062 1063
		REG_WRITE(ah, AR_RC, 0);

1064
	REG_WRITE(ah, AR_RTC_RESET, 1);
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1065 1066 1067 1068

	if (!ath9k_hw_wait(ah,
			   AR_RTC_STATUS,
			   AR_RTC_STATUS_M,
S
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1069 1070
			   AR_RTC_STATUS_ON,
			   AH_WAIT_TIMEOUT)) {
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1071 1072
		ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
			"RTC not waking up\n");
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1073
		return false;
1074 1075
	}

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1076 1077 1078 1079 1080
	ath9k_hw_read_revisions(ah);

	return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
}

1081
static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
S
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1082
{
1083 1084 1085 1086 1087
	if (AR_SREV_9300_20_OR_LATER(ah)) {
		REG_WRITE(ah, AR_WA, ah->WARegVal);
		udelay(10);
	}

S
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1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099
	REG_WRITE(ah, AR_RTC_FORCE_WAKE,
		  AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);

	switch (type) {
	case ATH9K_RESET_POWER_ON:
		return ath9k_hw_set_reset_power_on(ah);
	case ATH9K_RESET_WARM:
	case ATH9K_RESET_COLD:
		return ath9k_hw_set_reset(ah, type);
	default:
		return false;
	}
1100 1101
}

1102
static bool ath9k_hw_chip_reset(struct ath_hw *ah,
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1103
				struct ath9k_channel *chan)
1104
{
1105
	if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1106 1107 1108
		if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
			return false;
	} else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
S
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1109
		return false;
1110

1111
	if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
S
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1112
		return false;
1113

1114
	ah->chip_fullsleep = false;
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1115 1116
	ath9k_hw_init_pll(ah, chan);
	ath9k_hw_set_rfmode(ah, chan);
1117

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1118
	return true;
1119 1120
}

1121
static bool ath9k_hw_channel_change(struct ath_hw *ah,
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1122
				    struct ath9k_channel *chan)
1123
{
1124
	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1125
	struct ath_common *common = ath9k_hw_common(ah);
1126
	struct ieee80211_channel *channel = chan->chan;
1127
	u32 qnum;
1128
	int r;
1129 1130 1131

	for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
		if (ath9k_hw_numtxpending(ah, qnum)) {
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1132 1133
			ath_dbg(common, ATH_DBG_QUEUE,
				"Transmit frames pending on queue %d\n", qnum);
1134 1135 1136 1137
			return false;
		}
	}

1138
	if (!ath9k_hw_rfbus_req(ah)) {
1139
		ath_err(common, "Could not kill baseband RX\n");
1140 1141 1142
		return false;
	}

1143
	ath9k_hw_set_channel_regs(ah, chan);
1144

1145
	r = ath9k_hw_rf_set_freq(ah, chan);
1146
	if (r) {
1147
		ath_err(common, "Failed to set channel\n");
1148
		return false;
1149
	}
1150
	ath9k_hw_set_clockrate(ah);
1151

1152
	ah->eep_ops->set_txpower(ah, chan,
1153
			     ath9k_regd_get_ctl(regulatory, chan),
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1154 1155 1156
			     channel->max_antenna_gain * 2,
			     channel->max_power * 2,
			     min((u32) MAX_RATE_POWER,
1157
			     (u32) regulatory->power_limit), false);
1158

1159
	ath9k_hw_rfbus_done(ah);
1160

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1161 1162 1163
	if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
		ath9k_hw_set_delta_slope(ah, chan);

1164
	ath9k_hw_spur_mitigate_freq(ah, chan);
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1165 1166 1167 1168

	return true;
}

1169
bool ath9k_hw_check_alive(struct ath_hw *ah)
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1170
{
1171 1172 1173
	int count = 50;
	u32 reg;

1174
	if (AR_SREV_9285_12_OR_LATER(ah))
1175 1176 1177 1178
		return true;

	do {
		reg = REG_READ(ah, AR_OBS_BUS_1);
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1179

1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191
		if ((reg & 0x7E7FFFEF) == 0x00702400)
			continue;

		switch (reg & 0x7E000B00) {
		case 0x1E000000:
		case 0x52000B00:
		case 0x18000B00:
			continue;
		default:
			return true;
		}
	} while (count-- > 0);
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1192

1193
	return false;
J
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1194
}
1195
EXPORT_SYMBOL(ath9k_hw_check_alive);
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1196

1197
int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1198
		   struct ath9k_hw_cal_data *caldata, bool bChannelChange)
1199
{
1200
	struct ath_common *common = ath9k_hw_common(ah);
1201
	u32 saveLedState;
1202
	struct ath9k_channel *curchan = ah->curchan;
1203 1204
	u32 saveDefAntenna;
	u32 macStaId1;
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1205
	u64 tsf = 0;
1206
	int i, r;
1207

1208 1209
	ah->txchainmask = common->tx_chainmask;
	ah->rxchainmask = common->rx_chainmask;
1210

1211 1212
	if (!ah->chip_fullsleep) {
		ath9k_hw_abortpcurecv(ah);
1213
		if (!ath9k_hw_stopdmarecv(ah)) {
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1214
			ath_dbg(common, ATH_DBG_XMIT,
1215
				"Failed to stop receive dma\n");
1216 1217
			bChannelChange = false;
		}
1218 1219
	}

1220
	if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1221
		return -EIO;
1222

1223
	if (curchan && !ah->chip_fullsleep)
1224 1225
		ath9k_hw_getnf(ah, curchan);

1226 1227 1228 1229 1230 1231 1232 1233 1234 1235
	ah->caldata = caldata;
	if (caldata &&
	    (chan->channel != caldata->channel ||
	     (chan->channelFlags & ~CHANNEL_CW_INT) !=
	     (caldata->channelFlags & ~CHANNEL_CW_INT))) {
		/* Operating channel changed, reset channel calibration data */
		memset(caldata, 0, sizeof(*caldata));
		ath9k_init_nfcal_hist_buffer(ah, chan);
	}

1236
	if (bChannelChange &&
1237 1238 1239
	    (ah->chip_fullsleep != true) &&
	    (ah->curchan != NULL) &&
	    (chan->channel != ah->curchan->channel) &&
1240
	    ((chan->channelFlags & CHANNEL_ALL) ==
1241
	     (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1242
	    (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) {
1243

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1244
		if (ath9k_hw_channel_change(ah, chan)) {
1245
			ath9k_hw_loadnf(ah, ah->curchan);
1246
			ath9k_hw_start_nfcal(ah, true);
1247 1248
			if (AR_SREV_9271(ah))
				ar9002_hw_load_ani_reg(ah, chan);
1249
			return 0;
1250 1251 1252 1253 1254 1255 1256 1257 1258
		}
	}

	saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
	if (saveDefAntenna == 0)
		saveDefAntenna = 1;

	macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;

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1259
	/* For chips on which RTC reset is done, save TSF before it gets cleared */
1260 1261
	if (AR_SREV_9100(ah) ||
	    (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
S
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1262 1263
		tsf = ath9k_hw_gettsf64(ah);

1264 1265 1266 1267 1268 1269
	saveLedState = REG_READ(ah, AR_CFG_LED) &
		(AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
		 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);

	ath9k_hw_mark_phy_inactive(ah);

1270
	/* Only required on the first reset */
1271 1272 1273 1274 1275 1276 1277
	if (AR_SREV_9271(ah) && ah->htc_reset_init) {
		REG_WRITE(ah,
			  AR9271_RESET_POWER_DOWN_CONTROL,
			  AR9271_RADIO_RF_RST);
		udelay(50);
	}

1278
	if (!ath9k_hw_chip_reset(ah, chan)) {
1279
		ath_err(common, "Chip reset failed\n");
1280
		return -EINVAL;
1281 1282
	}

1283
	/* Only required on the first reset */
1284 1285 1286 1287 1288 1289 1290 1291
	if (AR_SREV_9271(ah) && ah->htc_reset_init) {
		ah->htc_reset_init = false;
		REG_WRITE(ah,
			  AR9271_RESET_POWER_DOWN_CONTROL,
			  AR9271_GATE_MAC_CTL);
		udelay(50);
	}

S
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1292
	/* Restore TSF */
1293
	if (tsf)
S
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1294 1295
		ath9k_hw_settsf64(ah, tsf);

1296
	if (AR_SREV_9280_20_OR_LATER(ah))
1297
		REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1298

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1299 1300 1301
	if (!AR_SREV_9300_20_OR_LATER(ah))
		ar9002_hw_enable_async_fifo(ah);

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1302
	r = ath9k_hw_process_ini(ah, chan);
1303 1304
	if (r)
		return r;
1305

1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316
	/*
	 * Some AR91xx SoC devices frequently fail to accept TSF writes
	 * right after the chip reset. When that happens, write a new
	 * value after the initvals have been applied, with an offset
	 * based on measured time difference
	 */
	if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
		tsf += 1500;
		ath9k_hw_settsf64(ah, tsf);
	}

1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333
	/* Setup MFP options for CCMP */
	if (AR_SREV_9280_20_OR_LATER(ah)) {
		/* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
		 * frames when constructing CCMP AAD. */
		REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
			      0xc7ff);
		ah->sw_mgmt_crypto = false;
	} else if (AR_SREV_9160_10_OR_LATER(ah)) {
		/* Disable hardware crypto for management frames */
		REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
			    AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
		REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
			    AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
		ah->sw_mgmt_crypto = true;
	} else
		ah->sw_mgmt_crypto = true;

1334 1335 1336
	if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
		ath9k_hw_set_delta_slope(ah, chan);

1337
	ath9k_hw_spur_mitigate_freq(ah, chan);
1338
	ah->eep_ops->set_board_values(ah, chan);
1339

1340 1341
	ath9k_hw_set_operating_mode(ah, ah->opmode);

S
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1342 1343
	ENABLE_REGWRITE_BUFFER(ah);

1344 1345
	REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
	REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1346 1347
		  | macStaId1
		  | AR_STA_ID1_RTS_USE_DEF
1348
		  | (ah->config.
1349
		     ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1350
		  | ah->sta_id1_defaults);
1351
	ath_hw_setbssidmask(common);
1352
	REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1353
	ath9k_hw_write_associd(ah);
1354 1355 1356
	REG_WRITE(ah, AR_ISR, ~0);
	REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);

S
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1357 1358
	REGWRITE_BUFFER_FLUSH(ah);

1359
	r = ath9k_hw_rf_set_freq(ah, chan);
1360 1361
	if (r)
		return r;
1362

1363 1364
	ath9k_hw_set_clockrate(ah);

S
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1365 1366
	ENABLE_REGWRITE_BUFFER(ah);

1367 1368 1369
	for (i = 0; i < AR_NUM_DCU; i++)
		REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);

S
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1370 1371
	REGWRITE_BUFFER_FLUSH(ah);

1372 1373
	ah->intr_txqs = 0;
	for (i = 0; i < ah->caps.total_queues; i++)
1374 1375
		ath9k_hw_resettxqueue(ah, i);

1376
	ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1377
	ath9k_hw_ani_cache_ini_regs(ah);
1378 1379
	ath9k_hw_init_qos(ah);

1380
	if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1381
		ath9k_enable_rfkill(ah);
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1382

1383
	ath9k_hw_init_global_settings(ah);
1384

1385
	if (!AR_SREV_9300_20_OR_LATER(ah)) {
S
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1386
		ar9002_hw_update_async_fifo(ah);
1387
		ar9002_hw_enable_wep_aggregation(ah);
1388 1389
	}

1390 1391 1392 1393 1394 1395 1396
	REG_WRITE(ah, AR_STA_ID1,
		  REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);

	ath9k_hw_set_dma(ah);

	REG_WRITE(ah, AR_OBS, 8);

S
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1397
	if (ah->config.rx_intr_mitigation) {
1398 1399 1400 1401
		REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
		REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
	}

1402 1403 1404 1405 1406
	if (ah->config.tx_intr_mitigation) {
		REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
		REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
	}

1407 1408
	ath9k_hw_init_bb(ah, chan);

1409
	if (!ath9k_hw_init_cal(ah, chan))
1410
		return -EIO;
1411

S
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1412
	ENABLE_REGWRITE_BUFFER(ah);
1413

1414
	ath9k_hw_restore_chainmask(ah);
1415 1416
	REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);

S
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1417 1418
	REGWRITE_BUFFER_FLUSH(ah);

1419 1420 1421
	/*
	 * For big endian systems turn on swapping for descriptors
	 */
1422 1423 1424 1425
	if (AR_SREV_9100(ah)) {
		u32 mask;
		mask = REG_READ(ah, AR_CFG);
		if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
J
Joe Perches 已提交
1426
			ath_dbg(common, ATH_DBG_RESET,
S
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1427
				"CFG Byte Swap Set 0x%x\n", mask);
1428 1429 1430 1431
		} else {
			mask =
				INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
			REG_WRITE(ah, AR_CFG, mask);
J
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1432
			ath_dbg(common, ATH_DBG_RESET,
S
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1433
				"Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1434 1435
		}
	} else {
1436 1437 1438 1439 1440 1441 1442
		if (common->bus_ops->ath_bus_type == ATH_USB) {
			/* Configure AR9271 target WLAN */
			if (AR_SREV_9271(ah))
				REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
			else
				REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
		}
1443
#ifdef __BIG_ENDIAN
1444 1445
                else
			REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1446 1447 1448
#endif
	}

1449
	if (ah->btcoex_hw.enabled)
1450 1451
		ath9k_hw_btcoex_enable(ah);

1452
	if (AR_SREV_9300_20_OR_LATER(ah))
1453
		ar9003_hw_bb_watchdog_config(ah);
1454

1455
	return 0;
1456
}
1457
EXPORT_SYMBOL(ath9k_hw_reset);
1458

S
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1459 1460 1461 1462
/******************************/
/* Power Management (Chipset) */
/******************************/

1463 1464 1465 1466
/*
 * Notify Power Mgt is disabled in self-generated frames.
 * If requested, force chip to sleep.
 */
1467
static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1468
{
S
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1469 1470
	REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
	if (setChip) {
1471 1472 1473 1474
		/*
		 * Clear the RTC force wake bit to allow the
		 * mac to go to sleep.
		 */
S
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1475 1476
		REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
			    AR_RTC_FORCE_WAKE_EN);
1477
		if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
S
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1478
			REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1479

1480
		/* Shutdown chip. Active low */
1481
		if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
S
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1482 1483
			REG_CLR_BIT(ah, (AR_RTC_RESET),
				    AR_RTC_RESET_EN);
S
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1484
	}
1485 1486 1487 1488 1489

	/* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
	if (AR_SREV_9300_20_OR_LATER(ah))
		REG_WRITE(ah, AR_WA,
			  ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1490 1491
}

1492 1493 1494 1495 1496
/*
 * Notify Power Management is enabled in self-generating
 * frames. If request, set power mode of chip to
 * auto/normal.  Duration in units of 128us (1/8 TU).
 */
1497
static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1498
{
S
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1499 1500
	REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
	if (setChip) {
1501
		struct ath9k_hw_capabilities *pCap = &ah->caps;
1502

S
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1503
		if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1504
			/* Set WakeOnInterrupt bit; clear ForceWake bit */
S
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1505 1506 1507
			REG_WRITE(ah, AR_RTC_FORCE_WAKE,
				  AR_RTC_FORCE_WAKE_ON_INT);
		} else {
1508 1509 1510 1511
			/*
			 * Clear the RTC force wake bit to allow the
			 * mac to go to sleep.
			 */
S
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1512 1513
			REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
				    AR_RTC_FORCE_WAKE_EN);
1514 1515
		}
	}
1516 1517 1518 1519

	/* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
	if (AR_SREV_9300_20_OR_LATER(ah))
		REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1520 1521
}

1522
static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1523
{
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1524 1525
	u32 val;
	int i;
1526

1527 1528 1529 1530 1531 1532
	/* Set Bits 14 and 17 of AR_WA before powering on the chip. */
	if (AR_SREV_9300_20_OR_LATER(ah)) {
		REG_WRITE(ah, AR_WA, ah->WARegVal);
		udelay(10);
	}

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1533 1534 1535 1536 1537 1538 1539
	if (setChip) {
		if ((REG_READ(ah, AR_RTC_STATUS) &
		     AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
			if (ath9k_hw_set_reset_reg(ah,
					   ATH9K_RESET_POWER_ON) != true) {
				return false;
			}
1540 1541
			if (!AR_SREV_9300_20_OR_LATER(ah))
				ath9k_hw_init_pll(ah, NULL);
S
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1542 1543 1544 1545
		}
		if (AR_SREV_9100(ah))
			REG_SET_BIT(ah, AR_RTC_RESET,
				    AR_RTC_RESET_EN);
1546

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1547 1548 1549
		REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
			    AR_RTC_FORCE_WAKE_EN);
		udelay(50);
1550

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1551 1552 1553 1554 1555 1556 1557
		for (i = POWER_UP_TIME / 50; i > 0; i--) {
			val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
			if (val == AR_RTC_STATUS_ON)
				break;
			udelay(50);
			REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
				    AR_RTC_FORCE_WAKE_EN);
1558
		}
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1559
		if (i == 0) {
1560 1561 1562
			ath_err(ath9k_hw_common(ah),
				"Failed to wakeup in %uus\n",
				POWER_UP_TIME / 20);
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1563
			return false;
1564 1565 1566
		}
	}

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1567
	REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1568

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1569
	return true;
1570 1571
}

1572
bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1573
{
1574
	struct ath_common *common = ath9k_hw_common(ah);
1575
	int status = true, setChip = true;
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1576 1577 1578 1579 1580 1581 1582
	static const char *modes[] = {
		"AWAKE",
		"FULL-SLEEP",
		"NETWORK SLEEP",
		"UNDEFINED"
	};

1583 1584 1585
	if (ah->power_mode == mode)
		return status;

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1586 1587
	ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n",
		modes[ah->power_mode], modes[mode]);
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1588 1589 1590 1591 1592 1593 1594

	switch (mode) {
	case ATH9K_PM_AWAKE:
		status = ath9k_hw_set_power_awake(ah, setChip);
		break;
	case ATH9K_PM_FULL_SLEEP:
		ath9k_set_power_sleep(ah, setChip);
1595
		ah->chip_fullsleep = true;
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1596 1597 1598 1599
		break;
	case ATH9K_PM_NETWORK_SLEEP:
		ath9k_set_power_network_sleep(ah, setChip);
		break;
1600
	default:
1601
		ath_err(common, "Unknown power mode %u\n", mode);
1602 1603
		return false;
	}
1604
	ah->power_mode = mode;
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1605 1606

	return status;
1607
}
1608
EXPORT_SYMBOL(ath9k_hw_setpower);
1609

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1610 1611 1612 1613
/*******************/
/* Beacon Handling */
/*******************/

1614
void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1615 1616 1617
{
	int flags = 0;

1618
	ah->beacon_interval = beacon_period;
1619

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1620 1621
	ENABLE_REGWRITE_BUFFER(ah);

1622
	switch (ah->opmode) {
1623
	case NL80211_IFTYPE_STATION:
1624 1625 1626 1627 1628
		REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
		REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
		REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
		flags |= AR_TBTT_TIMER_EN;
		break;
1629
	case NL80211_IFTYPE_ADHOC:
1630
	case NL80211_IFTYPE_MESH_POINT:
1631 1632 1633 1634
		REG_SET_BIT(ah, AR_TXCFG,
			    AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
		REG_WRITE(ah, AR_NEXT_NDP_TIMER,
			  TU_TO_USEC(next_beacon +
1635 1636
				     (ah->atim_window ? ah->
				      atim_window : 1)));
1637
		flags |= AR_NDP_TIMER_EN;
1638
	case NL80211_IFTYPE_AP:
1639 1640 1641
		REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
		REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
			  TU_TO_USEC(next_beacon -
1642
				     ah->config.
1643
				     dma_beacon_response_time));
1644 1645
		REG_WRITE(ah, AR_NEXT_SWBA,
			  TU_TO_USEC(next_beacon -
1646
				     ah->config.
1647
				     sw_beacon_response_time));
1648 1649 1650
		flags |=
			AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
		break;
1651
	default:
1652 1653 1654 1655 1656 1657 1658 1659
		if (ah->is_monitoring) {
			REG_WRITE(ah, AR_NEXT_TBTT_TIMER,
					TU_TO_USEC(next_beacon));
			REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
			REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
			flags |= AR_TBTT_TIMER_EN;
			break;
		}
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1660 1661 1662
		ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON,
			"%s: unsupported opmode: %d\n",
			__func__, ah->opmode);
1663 1664
		return;
		break;
1665 1666 1667 1668 1669 1670 1671
	}

	REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
	REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
	REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
	REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));

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1672 1673
	REGWRITE_BUFFER_FLUSH(ah);

1674 1675 1676 1677 1678 1679 1680
	beacon_period &= ~ATH9K_BEACON_ENA;
	if (beacon_period & ATH9K_BEACON_RESET_TSF) {
		ath9k_hw_reset_tsf(ah);
	}

	REG_SET_BIT(ah, AR_TIMER_MODE, flags);
}
1681
EXPORT_SYMBOL(ath9k_hw_beaconinit);
1682

1683
void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
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1684
				    const struct ath9k_beacon_state *bs)
1685 1686
{
	u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1687
	struct ath9k_hw_capabilities *pCap = &ah->caps;
1688
	struct ath_common *common = ath9k_hw_common(ah);
1689

S
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1690 1691
	ENABLE_REGWRITE_BUFFER(ah);

1692 1693 1694 1695 1696 1697 1698
	REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));

	REG_WRITE(ah, AR_BEACON_PERIOD,
		  TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
	REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
		  TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));

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1699 1700
	REGWRITE_BUFFER_FLUSH(ah);

1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717
	REG_RMW_FIELD(ah, AR_RSSI_THR,
		      AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);

	beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;

	if (bs->bs_sleepduration > beaconintval)
		beaconintval = bs->bs_sleepduration;

	dtimperiod = bs->bs_dtimperiod;
	if (bs->bs_sleepduration > dtimperiod)
		dtimperiod = bs->bs_sleepduration;

	if (beaconintval == dtimperiod)
		nextTbtt = bs->bs_nextdtim;
	else
		nextTbtt = bs->bs_nexttbtt;

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1718 1719 1720 1721
	ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
	ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
	ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
	ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1722

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1723 1724
	ENABLE_REGWRITE_BUFFER(ah);

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1725 1726 1727
	REG_WRITE(ah, AR_NEXT_DTIM,
		  TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
	REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1728

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1729 1730 1731
	REG_WRITE(ah, AR_SLEEP1,
		  SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
		  | AR_SLEEP1_ASSUME_DTIM);
1732

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1733 1734 1735 1736
	if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
		beacontimeout = (BEACON_TIMEOUT_VAL << 3);
	else
		beacontimeout = MIN_BEACON_TIMEOUT_VAL;
1737

S
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1738 1739
	REG_WRITE(ah, AR_SLEEP2,
		  SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
1740

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1741 1742
	REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
	REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
1743

S
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1744 1745
	REGWRITE_BUFFER_FLUSH(ah);

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1746 1747 1748
	REG_SET_BIT(ah, AR_TIMER_MODE,
		    AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
		    AR_DTIM_TIMER_EN);
1749

1750 1751
	/* TSF Out of Range Threshold */
	REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
1752
}
1753
EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
1754

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1755 1756 1757 1758
/*******************/
/* HW Capabilities */
/*******************/

1759
int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1760
{
1761
	struct ath9k_hw_capabilities *pCap = &ah->caps;
1762
	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1763
	struct ath_common *common = ath9k_hw_common(ah);
1764
	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
1765

S
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1766
	u16 capField = 0, eeval;
1767
	u8 ant_div_ctl1;
1768

S
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1769
	eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
1770
	regulatory->current_rd = eeval;
1771

S
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1772
	eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
1773
	if (AR_SREV_9285_12_OR_LATER(ah))
1774
		eeval |= AR9285_RDEXT_DEFAULT;
1775
	regulatory->current_rd_ext = eeval;
1776

S
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1777
	capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
S
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1778

1779
	if (ah->opmode != NL80211_IFTYPE_AP &&
1780
	    ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
1781 1782 1783 1784 1785
		if (regulatory->current_rd == 0x64 ||
		    regulatory->current_rd == 0x65)
			regulatory->current_rd += 5;
		else if (regulatory->current_rd == 0x41)
			regulatory->current_rd = 0x43;
J
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1786 1787
		ath_dbg(common, ATH_DBG_REGULATORY,
			"regdomain mapped to 0x%x\n", regulatory->current_rd);
S
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1788
	}
1789

S
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1790
	eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
1791
	if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
1792 1793
		ath_err(common,
			"no band has been marked as supported in EEPROM\n");
1794 1795 1796
		return -EINVAL;
	}

1797 1798
	if (eeval & AR5416_OPFLAGS_11A)
		pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
1799

1800 1801
	if (eeval & AR5416_OPFLAGS_11G)
		pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
S
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1802

S
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1803
	pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
1804 1805 1806 1807
	/*
	 * For AR9271 we will temporarilly uses the rx chainmax as read from
	 * the EEPROM.
	 */
1808
	if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
1809 1810 1811
	    !(eeval & AR5416_OPFLAGS_11A) &&
	    !(AR_SREV_9271(ah)))
		/* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
1812 1813
		pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
	else
1814
		/* Use rx_chainmask from EEPROM. */
1815
		pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
1816

1817
	ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
1818

1819 1820 1821 1822
	/* enable key search for every frame in an aggregate */
	if (AR_SREV_9300_20_OR_LATER(ah))
		ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;

S
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1823 1824
	pCap->low_2ghz_chan = 2312;
	pCap->high_2ghz_chan = 2732;
1825

S
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1826 1827
	pCap->low_5ghz_chan = 4920;
	pCap->high_5ghz_chan = 6100;
1828

1829 1830
	common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;

1831
	if (ah->config.ht_enable)
S
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1832 1833 1834
		pCap->hw_caps |= ATH9K_HW_CAP_HT;
	else
		pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
1835

S
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1836 1837 1838 1839 1840
	if (capField & AR_EEPROM_EEPCAP_MAXQCU)
		pCap->total_queues =
			MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
	else
		pCap->total_queues = ATH9K_NUM_TX_QUEUES;
1841

S
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1842 1843 1844 1845 1846
	if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
		pCap->keycache_size =
			1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
	else
		pCap->keycache_size = AR_KEYTABLE_SIZE;
1847

1848 1849 1850 1851
	if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
		pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
	else
		pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
1852

1853 1854
	if (AR_SREV_9271(ah))
		pCap->num_gpio_pins = AR9271_NUM_GPIO;
S
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1855 1856
	else if (AR_DEVID_7010(ah))
		pCap->num_gpio_pins = AR7010_NUM_GPIO;
1857
	else if (AR_SREV_9285_12_OR_LATER(ah))
1858
		pCap->num_gpio_pins = AR9285_NUM_GPIO;
1859
	else if (AR_SREV_9280_20_OR_LATER(ah))
S
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1860 1861 1862
		pCap->num_gpio_pins = AR928X_NUM_GPIO;
	else
		pCap->num_gpio_pins = AR_NUM_GPIO;
1863

S
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1864 1865 1866 1867 1868
	if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
		pCap->hw_caps |= ATH9K_HW_CAP_CST;
		pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
	} else {
		pCap->rts_aggr_limit = (8 * 1024);
1869 1870
	}

S
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1871 1872
	pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;

1873
#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1874 1875 1876 1877 1878 1879
	ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
	if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
		ah->rfkill_gpio =
			MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
		ah->rfkill_polarity =
			MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
S
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1880 1881

		pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
1882
	}
S
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1883
#endif
1884
	if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
1885 1886 1887
		pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
	else
		pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
1888

1889
	if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
S
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1890 1891 1892
		pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
	else
		pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
1893

1894
	if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
S
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1895 1896 1897 1898 1899
		pCap->reg_cap =
			AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
			AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
			AR_EEPROM_EEREGCAP_EN_KK_U2 |
			AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
1900
	} else {
S
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1901 1902 1903
		pCap->reg_cap =
			AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
			AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
1904 1905
	}

1906 1907 1908 1909
	/* Advertise midband for AR5416 with FCC midband set in eeprom */
	if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
	    AR_SREV_5416(ah))
		pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
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1910 1911

	pCap->num_antcfg_5ghz =
S
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1912
		ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
S
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1913
	pCap->num_antcfg_2ghz =
S
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1914
		ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
1915

1916
	if (AR_SREV_9280_20_OR_LATER(ah) && common->btcoex_enabled) {
1917 1918
		btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
		btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
1919

1920
		if (AR_SREV_9285(ah)) {
1921 1922
			btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
			btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
1923
		} else {
1924
			btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
1925
		}
1926
	} else {
1927
		btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
1928
	}
1929

1930
	if (AR_SREV_9300_20_OR_LATER(ah)) {
1931 1932 1933 1934
		pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
		if (!AR_SREV_9485(ah))
			pCap->hw_caps |= ATH9K_HW_CAP_LDPC;

1935 1936 1937
		pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
		pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
		pCap->rx_status_len = sizeof(struct ar9003_rxs);
1938
		pCap->tx_desc_len = sizeof(struct ar9003_txc);
1939
		pCap->txs_len = sizeof(struct ar9003_txs);
1940 1941
		if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
			pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
1942 1943
	} else {
		pCap->tx_desc_len = sizeof(struct ath_desc);
1944 1945 1946 1947 1948
		if (AR_SREV_9280_20(ah) &&
		    ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
		      AR5416_EEP_MINOR_VER_16) ||
		     ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
			pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
1949
	}
1950

1951 1952 1953
	if (AR_SREV_9300_20_OR_LATER(ah))
		pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;

1954 1955 1956
	if (AR_SREV_9300_20_OR_LATER(ah))
		ah->ent_mode = REG_READ(ah, AR_ENT_OTP);

1957
	if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
1958 1959
		pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;

1960 1961 1962 1963 1964 1965 1966
	if (AR_SREV_9285(ah))
		if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
			ant_div_ctl1 =
				ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
			if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
				pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
		}
1967 1968 1969 1970 1971 1972
	if (AR_SREV_9300_20_OR_LATER(ah)) {
		if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
			pCap->hw_caps |= ATH9K_HW_CAP_APM;
	}


1973

1974 1975 1976 1977 1978
	if (AR_SREV_9485_10(ah)) {
		pCap->pcie_lcr_extsync_en = true;
		pCap->pcie_lcr_offset = 0x80;
	}

1979
	return 0;
1980 1981
}

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1982 1983 1984
/****************************/
/* GPIO / RFKILL / Antennae */
/****************************/
1985

1986
static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
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1987 1988 1989 1990
					 u32 gpio, u32 type)
{
	int addr;
	u32 gpio_shift, tmp;
1991

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1992 1993 1994 1995 1996 1997
	if (gpio > 11)
		addr = AR_GPIO_OUTPUT_MUX3;
	else if (gpio > 5)
		addr = AR_GPIO_OUTPUT_MUX2;
	else
		addr = AR_GPIO_OUTPUT_MUX1;
1998

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1999
	gpio_shift = (gpio % 6) * 5;
2000

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2001 2002 2003 2004
	if (AR_SREV_9280_20_OR_LATER(ah)
	    || (addr != AR_GPIO_OUTPUT_MUX1)) {
		REG_RMW(ah, addr, (type << gpio_shift),
			(0x1f << gpio_shift));
2005
	} else {
S
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2006 2007 2008 2009 2010
		tmp = REG_READ(ah, addr);
		tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
		tmp &= ~(0x1f << gpio_shift);
		tmp |= (type << gpio_shift);
		REG_WRITE(ah, addr, tmp);
2011 2012 2013
	}
}

2014
void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2015
{
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2016
	u32 gpio_shift;
2017

2018
	BUG_ON(gpio >= ah->caps.num_gpio_pins);
2019

S
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2020 2021 2022 2023 2024 2025 2026
	if (AR_DEVID_7010(ah)) {
		gpio_shift = gpio;
		REG_RMW(ah, AR7010_GPIO_OE,
			(AR7010_GPIO_OE_AS_INPUT << gpio_shift),
			(AR7010_GPIO_OE_MASK << gpio_shift));
		return;
	}
2027

S
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2028
	gpio_shift = gpio << 1;
S
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2029 2030 2031 2032
	REG_RMW(ah,
		AR_GPIO_OE_OUT,
		(AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
		(AR_GPIO_OE_OUT_DRV << gpio_shift));
2033
}
2034
EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2035

2036
u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2037
{
2038 2039 2040
#define MS_REG_READ(x, y) \
	(MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))

2041
	if (gpio >= ah->caps.num_gpio_pins)
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2042
		return 0xffffffff;
2043

S
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2044 2045 2046 2047 2048
	if (AR_DEVID_7010(ah)) {
		u32 val;
		val = REG_READ(ah, AR7010_GPIO_IN);
		return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
	} else if (AR_SREV_9300_20_OR_LATER(ah))
2049 2050
		return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
			AR_GPIO_BIT(gpio)) != 0;
2051
	else if (AR_SREV_9271(ah))
2052
		return MS_REG_READ(AR9271, gpio) != 0;
2053
	else if (AR_SREV_9287_11_OR_LATER(ah))
2054
		return MS_REG_READ(AR9287, gpio) != 0;
2055
	else if (AR_SREV_9285_12_OR_LATER(ah))
2056
		return MS_REG_READ(AR9285, gpio) != 0;
2057
	else if (AR_SREV_9280_20_OR_LATER(ah))
2058 2059 2060
		return MS_REG_READ(AR928X, gpio) != 0;
	else
		return MS_REG_READ(AR, gpio) != 0;
2061
}
2062
EXPORT_SYMBOL(ath9k_hw_gpio_get);
2063

2064
void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
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2065
			 u32 ah_signal_type)
2066
{
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2067
	u32 gpio_shift;
2068

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2069 2070 2071 2072 2073 2074 2075
	if (AR_DEVID_7010(ah)) {
		gpio_shift = gpio;
		REG_RMW(ah, AR7010_GPIO_OE,
			(AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
			(AR7010_GPIO_OE_MASK << gpio_shift));
		return;
	}
2076

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2077
	ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
S
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2078 2079 2080 2081 2082
	gpio_shift = 2 * gpio;
	REG_RMW(ah,
		AR_GPIO_OE_OUT,
		(AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
		(AR_GPIO_OE_OUT_DRV << gpio_shift));
2083
}
2084
EXPORT_SYMBOL(ath9k_hw_cfg_output);
2085

2086
void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2087
{
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2088 2089 2090 2091 2092 2093 2094
	if (AR_DEVID_7010(ah)) {
		val = val ? 0 : 1;
		REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
			AR_GPIO_BIT(gpio));
		return;
	}

2095 2096 2097
	if (AR_SREV_9271(ah))
		val = ~val;

S
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2098 2099
	REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
		AR_GPIO_BIT(gpio));
2100
}
2101
EXPORT_SYMBOL(ath9k_hw_set_gpio);
2102

2103
u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2104
{
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2105
	return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2106
}
2107
EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2108

2109
void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2110
{
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2111
	REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2112
}
2113
EXPORT_SYMBOL(ath9k_hw_setantenna);
2114

S
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2115 2116 2117 2118
/*********************/
/* General Operation */
/*********************/

2119
u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2120
{
S
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2121 2122
	u32 bits = REG_READ(ah, AR_RX_FILTER);
	u32 phybits = REG_READ(ah, AR_PHY_ERR);
2123

S
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2124 2125 2126 2127
	if (phybits & AR_PHY_ERR_RADAR)
		bits |= ATH9K_RX_FILTER_PHYRADAR;
	if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
		bits |= ATH9K_RX_FILTER_PHYERR;
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2128

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2129
	return bits;
2130
}
2131
EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2132

2133
void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2134
{
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2135
	u32 phybits;
2136

S
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2137 2138
	ENABLE_REGWRITE_BUFFER(ah);

S
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2139 2140
	REG_WRITE(ah, AR_RX_FILTER, bits);

S
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2141 2142 2143 2144 2145 2146
	phybits = 0;
	if (bits & ATH9K_RX_FILTER_PHYRADAR)
		phybits |= AR_PHY_ERR_RADAR;
	if (bits & ATH9K_RX_FILTER_PHYERR)
		phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
	REG_WRITE(ah, AR_PHY_ERR, phybits);
2147

S
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2148 2149 2150 2151 2152 2153
	if (phybits)
		REG_WRITE(ah, AR_RXCFG,
			  REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
	else
		REG_WRITE(ah, AR_RXCFG,
			  REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
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2154 2155

	REGWRITE_BUFFER_FLUSH(ah);
S
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2156
}
2157
EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2158

2159
bool ath9k_hw_phy_disable(struct ath_hw *ah)
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2160
{
2161 2162 2163 2164 2165
	if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
		return false;

	ath9k_hw_init_pll(ah, NULL);
	return true;
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2166
}
2167
EXPORT_SYMBOL(ath9k_hw_phy_disable);
2168

2169
bool ath9k_hw_disable(struct ath_hw *ah)
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2170
{
2171
	if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
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2172
		return false;
2173

2174 2175 2176 2177 2178
	if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
		return false;

	ath9k_hw_init_pll(ah, NULL);
	return true;
2179
}
2180
EXPORT_SYMBOL(ath9k_hw_disable);
2181

2182
void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2183
{
2184
	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2185
	struct ath9k_channel *chan = ah->curchan;
2186
	struct ieee80211_channel *channel = chan->chan;
2187

2188
	regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
2189

2190
	ah->eep_ops->set_txpower(ah, chan,
2191
				 ath9k_regd_get_ctl(regulatory, chan),
2192 2193 2194
				 channel->max_antenna_gain * 2,
				 channel->max_power * 2,
				 min((u32) MAX_RATE_POWER,
2195
				 (u32) regulatory->power_limit), test);
2196
}
2197
EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2198

2199
void ath9k_hw_setopmode(struct ath_hw *ah)
2200
{
2201
	ath9k_hw_set_operating_mode(ah, ah->opmode);
2202
}
2203
EXPORT_SYMBOL(ath9k_hw_setopmode);
2204

2205
void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2206
{
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2207 2208
	REG_WRITE(ah, AR_MCAST_FIL0, filter0);
	REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2209
}
2210
EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2211

2212
void ath9k_hw_write_associd(struct ath_hw *ah)
2213
{
2214 2215 2216 2217 2218
	struct ath_common *common = ath9k_hw_common(ah);

	REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
	REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
		  ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2219
}
2220
EXPORT_SYMBOL(ath9k_hw_write_associd);
2221

2222 2223
#define ATH9K_MAX_TSF_READ 10

2224
u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2225
{
2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236
	u32 tsf_lower, tsf_upper1, tsf_upper2;
	int i;

	tsf_upper1 = REG_READ(ah, AR_TSF_U32);
	for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
		tsf_lower = REG_READ(ah, AR_TSF_L32);
		tsf_upper2 = REG_READ(ah, AR_TSF_U32);
		if (tsf_upper2 == tsf_upper1)
			break;
		tsf_upper1 = tsf_upper2;
	}
2237

2238
	WARN_ON( i == ATH9K_MAX_TSF_READ );
2239

2240
	return (((u64)tsf_upper1 << 32) | tsf_lower);
S
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2241
}
2242
EXPORT_SYMBOL(ath9k_hw_gettsf64);
2243

2244
void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2245 2246
{
	REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
A
Alina Friedrichsen 已提交
2247
	REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2248
}
2249
EXPORT_SYMBOL(ath9k_hw_settsf64);
2250

2251
void ath9k_hw_reset_tsf(struct ath_hw *ah)
S
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2252
{
2253 2254
	if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
			   AH_TSF_WRITE_TIMEOUT))
J
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2255 2256
		ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
			"AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2257

S
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2258 2259
	REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
}
2260
EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2261

S
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2262
void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
S
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2263 2264
{
	if (setting)
2265
		ah->misc_mode |= AR_PCU_TX_ADD_TSF;
S
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2266
	else
2267
		ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
S
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2268
}
2269
EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2270

L
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2271
void ath9k_hw_set11nmac2040(struct ath_hw *ah)
S
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2272
{
L
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2273
	struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
S
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2274 2275
	u32 macmode;

L
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2276
	if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
S
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2277 2278 2279
		macmode = AR_2040_JOINED_RX_CLEAR;
	else
		macmode = 0;
2280

S
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2281
	REG_WRITE(ah, AR_2040_MODE, macmode);
2282
}
2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328

/* HW Generic timers configuration */

static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
{
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
	{AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
				AR_NDP2_TIMER_MODE, 0x0002},
	{AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
				AR_NDP2_TIMER_MODE, 0x0004},
	{AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
				AR_NDP2_TIMER_MODE, 0x0008},
	{AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
				AR_NDP2_TIMER_MODE, 0x0010},
	{AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
				AR_NDP2_TIMER_MODE, 0x0020},
	{AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
				AR_NDP2_TIMER_MODE, 0x0040},
	{AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
				AR_NDP2_TIMER_MODE, 0x0080}
};

/* HW generic timer primitives */

/* compute and clear index of rightmost 1 */
static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
{
	u32 b;

	b = *mask;
	b &= (0-b);
	*mask &= ~b;
	b *= debruijn32;
	b >>= 27;

	return timer_table->gen_timer_index[b];
}

2329
static u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345
{
	return REG_READ(ah, AR_TSF_L32);
}

struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
					  void (*trigger)(void *),
					  void (*overflow)(void *),
					  void *arg,
					  u8 timer_index)
{
	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
	struct ath_gen_timer *timer;

	timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);

	if (timer == NULL) {
2346 2347 2348
		ath_err(ath9k_hw_common(ah),
			"Failed to allocate memory for hw timer[%d]\n",
			timer_index);
2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360
		return NULL;
	}

	/* allocate a hardware generic timer slot */
	timer_table->timers[timer_index] = timer;
	timer->index = timer_index;
	timer->trigger = trigger;
	timer->overflow = overflow;
	timer->arg = arg;

	return timer;
}
2361
EXPORT_SYMBOL(ath_gen_timer_alloc);
2362

2363 2364 2365 2366
void ath9k_hw_gen_timer_start(struct ath_hw *ah,
			      struct ath_gen_timer *timer,
			      u32 timer_next,
			      u32 timer_period)
2367 2368 2369 2370 2371 2372 2373 2374 2375 2376
{
	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
	u32 tsf;

	BUG_ON(!timer_period);

	set_bit(timer->index, &timer_table->timer_mask.timer_bits);

	tsf = ath9k_hw_gettsf32(ah);

J
Joe Perches 已提交
2377 2378 2379
	ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
		"current tsf %x period %x timer_next %x\n",
		tsf, timer_period, timer_next);
2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402

	/*
	 * Pull timer_next forward if the current TSF already passed it
	 * because of software latency
	 */
	if (timer_next < tsf)
		timer_next = tsf + timer_period;

	/*
	 * Program generic timer registers
	 */
	REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
		 timer_next);
	REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
		  timer_period);
	REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
		    gen_tmr_configuration[timer->index].mode_mask);

	/* Enable both trigger and thresh interrupt masks */
	REG_SET_BIT(ah, AR_IMR_S5,
		(SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
		SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
}
2403
EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2404

2405
void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424
{
	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;

	if ((timer->index < AR_FIRST_NDP_TIMER) ||
		(timer->index >= ATH_MAX_GEN_TIMER)) {
		return;
	}

	/* Clear generic timer enable bits. */
	REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
			gen_tmr_configuration[timer->index].mode_mask);

	/* Disable both trigger and thresh interrupt masks */
	REG_CLR_BIT(ah, AR_IMR_S5,
		(SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
		SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));

	clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
}
2425
EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
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void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
{
	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;

	/* free the hardware generic timer slot */
	timer_table->timers[timer->index] = NULL;
	kfree(timer);
}
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EXPORT_SYMBOL(ath_gen_timer_free);
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/*
 * Generic Timer Interrupts handling
 */
void ath_gen_timer_isr(struct ath_hw *ah)
{
	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
	struct ath_gen_timer *timer;
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	struct ath_common *common = ath9k_hw_common(ah);
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	u32 trigger_mask, thresh_mask, index;

	/* get hardware generic timer interrupt status */
	trigger_mask = ah->intr_gen_timer_trigger;
	thresh_mask = ah->intr_gen_timer_thresh;
	trigger_mask &= timer_table->timer_mask.val;
	thresh_mask &= timer_table->timer_mask.val;

	trigger_mask &= ~thresh_mask;

	while (thresh_mask) {
		index = rightmost_index(timer_table, &thresh_mask);
		timer = timer_table->timers[index];
		BUG_ON(!timer);
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		ath_dbg(common, ATH_DBG_HWTIMER,
			"TSF overflow for Gen timer %d\n", index);
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		timer->overflow(timer->arg);
	}

	while (trigger_mask) {
		index = rightmost_index(timer_table, &trigger_mask);
		timer = timer_table->timers[index];
		BUG_ON(!timer);
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		ath_dbg(common, ATH_DBG_HWTIMER,
			"Gen timer[%d] trigger\n", index);
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		timer->trigger(timer->arg);
	}
}
2473
EXPORT_SYMBOL(ath_gen_timer_isr);
2474

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/********/
/* HTC  */
/********/

void ath9k_hw_htc_resetinit(struct ath_hw *ah)
{
	ah->htc_reset_init = true;
}
EXPORT_SYMBOL(ath9k_hw_htc_resetinit);

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static struct {
	u32 version;
	const char * name;
} ath_mac_bb_names[] = {
	/* Devices with external radios */
	{ AR_SREV_VERSION_5416_PCI,	"5416" },
	{ AR_SREV_VERSION_5416_PCIE,	"5418" },
	{ AR_SREV_VERSION_9100,		"9100" },
	{ AR_SREV_VERSION_9160,		"9160" },
	/* Single-chip solutions */
	{ AR_SREV_VERSION_9280,		"9280" },
	{ AR_SREV_VERSION_9285,		"9285" },
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	{ AR_SREV_VERSION_9287,         "9287" },
	{ AR_SREV_VERSION_9271,         "9271" },
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	{ AR_SREV_VERSION_9300,         "9300" },
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};

/* For devices with external radios */
static struct {
	u16 version;
	const char * name;
} ath_rf_names[] = {
	{ 0,				"5133" },
	{ AR_RAD5133_SREV_MAJOR,	"5133" },
	{ AR_RAD5122_SREV_MAJOR,	"5122" },
	{ AR_RAD2133_SREV_MAJOR,	"2133" },
	{ AR_RAD2122_SREV_MAJOR,	"2122" }
};

/*
 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
 */
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static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
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{
	int i;

	for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
		if (ath_mac_bb_names[i].version == mac_bb_version) {
			return ath_mac_bb_names[i].name;
		}
	}

	return "????";
}

/*
 * Return the RF name. "????" is returned if the RF is unknown.
 * Used for devices with external radios.
 */
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static const char *ath9k_hw_rf_name(u16 rf_version)
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{
	int i;

	for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
		if (ath_rf_names[i].version == rf_version) {
			return ath_rf_names[i].name;
		}
	}

	return "????";
}
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void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
{
	int used;

	/* chipsets >= AR9280 are single-chip */
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	if (AR_SREV_9280_20_OR_LATER(ah)) {
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		used = snprintf(hw_name, len,
			       "Atheros AR%s Rev:%x",
			       ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
			       ah->hw_version.macRev);
	}
	else {
		used = snprintf(hw_name, len,
			       "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
			       ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
			       ah->hw_version.macRev,
			       ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
						AR_RADIO_SREV_MAJOR)),
			       ah->hw_version.phyRev);
	}

	hw_name[used] = '\0';
}
EXPORT_SYMBOL(ath9k_hw_name);