dc.h 41.4 KB
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/*
 * Copyright 2012-14 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#ifndef DC_INTERFACE_H_
#define DC_INTERFACE_H_

#include "dc_types.h"
#include "grph_object_defs.h"
#include "logger_types.h"
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#if defined(CONFIG_DRM_AMD_DC_HDCP)
#include "hdcp_types.h"
#endif
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#include "gpio_types.h"
#include "link_service_types.h"
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#include "grph_object_ctrl_defs.h"
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#include <inc/hw/opp.h>
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#include "inc/hw_sequencer.h"
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#include "inc/compressor.h"
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#include "inc/hw/dmcu.h"
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#include "dml/display_mode_lib.h"

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/* forward declaration */
struct aux_payload;
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struct set_config_cmd_payload;
struct dmub_notification;
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#define DC_VER "3.2.198"
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#define MAX_SURFACES 3
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#define MAX_PLANES 6
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#define MAX_STREAMS 6
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#define MAX_SINKS_PER_LINK 4
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#define MIN_VIEWPORT_SIZE 12
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#define MAX_NUM_EDP 2
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/*******************************************************************************
 * Display Core Interfaces
 ******************************************************************************/
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struct dc_versions {
	const char *dc_ver;
	struct dmcu_version dmcu_version;
};

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enum dp_protocol_version {
	DP_VERSION_1_4,
};

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enum dc_plane_type {
	DC_PLANE_TYPE_INVALID,
	DC_PLANE_TYPE_DCE_RGB,
	DC_PLANE_TYPE_DCE_UNDERLAY,
	DC_PLANE_TYPE_DCN_UNIVERSAL,
};

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// Sizes defined as multiples of 64KB
enum det_size {
	DET_SIZE_DEFAULT = 0,
	DET_SIZE_192KB = 3,
	DET_SIZE_256KB = 4,
	DET_SIZE_320KB = 5,
	DET_SIZE_384KB = 6
};


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struct dc_plane_cap {
	enum dc_plane_type type;
	uint32_t blends_with_above : 1;
	uint32_t blends_with_below : 1;
	uint32_t per_pixel_alpha : 1;
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	struct {
		uint32_t argb8888 : 1;
		uint32_t nv12 : 1;
		uint32_t fp16 : 1;
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		uint32_t p010 : 1;
		uint32_t ayuv : 1;
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	} pixel_format_support;
	// max upscaling factor x1000
	// upscaling factors are always >= 1
	// for example, 1080p -> 8K is 4.0, or 4000 raw value
	struct {
		uint32_t argb8888;
		uint32_t nv12;
		uint32_t fp16;
	} max_upscale_factor;
	// max downscale factor x1000
	// downscale factors are always <= 1
	// for example, 8K -> 1080p is 0.25, or 250 raw value
	struct {
		uint32_t argb8888;
		uint32_t nv12;
		uint32_t fp16;
	} max_downscale_factor;
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	// minimal width/height
	uint32_t min_width;
	uint32_t min_height;
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};

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// Color management caps (DPP and MPC)
struct rom_curve_caps {
	uint16_t srgb : 1;
	uint16_t bt2020 : 1;
	uint16_t gamma2_2 : 1;
	uint16_t pq : 1;
	uint16_t hlg : 1;
};

struct dpp_color_caps {
	uint16_t dcn_arch : 1; // all DCE generations treated the same
	// input lut is different than most LUTs, just plain 256-entry lookup
	uint16_t input_lut_shared : 1; // shared with DGAM
	uint16_t icsc : 1;
	uint16_t dgam_ram : 1;
	uint16_t post_csc : 1; // before gamut remap
	uint16_t gamma_corr : 1;

	// hdr_mult and gamut remap always available in DPP (in that order)
	// 3d lut implies shaper LUT,
	// it may be shared with MPC - check MPC:shared_3d_lut flag
	uint16_t hw_3d_lut : 1;
	uint16_t ogam_ram : 1; // blnd gam
	uint16_t ocsc : 1;
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	uint16_t dgam_rom_for_yuv : 1;
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	struct rom_curve_caps dgam_rom_caps;
	struct rom_curve_caps ogam_rom_caps;
};

struct mpc_color_caps {
	uint16_t gamut_remap : 1;
	uint16_t ogam_ram : 1;
	uint16_t ocsc : 1;
	uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT
	uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance

	struct rom_curve_caps ogam_rom_caps;
};

struct dc_color_caps {
	struct dpp_color_caps dpp;
	struct mpc_color_caps mpc;
};

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struct dc_dmub_caps {
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	bool psr;
	bool mclk_sw;
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};

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struct dc_caps {
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	uint32_t max_streams;
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	uint32_t max_links;
	uint32_t max_audios;
	uint32_t max_slave_planes;
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	uint32_t max_slave_yuv_planes;
	uint32_t max_slave_rgb_planes;
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	uint32_t max_planes;
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	uint32_t max_downscale_ratio;
	uint32_t i2c_speed_in_khz;
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	uint32_t i2c_speed_in_khz_hdcp;
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	uint32_t dmdata_alloc_size;
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	unsigned int max_cursor_size;
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	unsigned int max_video_width;
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	unsigned int min_horizontal_blanking_period;
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	int linear_pitch_alignment;
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	bool dcc_const_color;
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	bool dynamic_audio;
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	bool is_apu;
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	bool dual_link_dvi;
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	bool post_blend_color_processing;
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	bool force_dp_tps4_for_cp2520;
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	bool disable_dp_clk_share;
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	bool psp_setup_panel_mode;
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	bool extended_aux_timeout_support;
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	bool dmcub_support;
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	bool zstate_support;
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	uint32_t num_of_internal_disp;
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	enum dp_protocol_version max_dp_protocol_version;
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	unsigned int mall_size_per_mem_channel;
	unsigned int mall_size_total;
	unsigned int cursor_cache_size;
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	struct dc_plane_cap planes[MAX_PLANES];
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	struct dc_color_caps color;
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	struct dc_dmub_caps dmub_caps;
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	bool dp_hpo;
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	bool dp_hdmi21_pcon_support;
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	bool edp_dsc_support;
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	bool vbios_lttpr_aware;
	bool vbios_lttpr_enable;
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	uint32_t max_otg_num;
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	uint32_t max_cab_allocation_bytes;
	uint32_t cache_line_size;
	uint32_t cache_num_ways;
	uint16_t subvp_fw_processing_delay_us;
	uint16_t subvp_prefetch_end_to_mall_start_us;
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	uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height
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	uint16_t subvp_pstate_allow_width_us;
	uint16_t subvp_vertical_int_margin_us;
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	bool seamless_odm;
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};

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struct dc_bug_wa {
	bool no_connect_phy_config;
	bool dedcn20_305_wa;
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	bool skip_clock_update;
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	bool lt_early_cr_pattern;
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};

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struct dc_dcc_surface_param {
	struct dc_size surface_size;
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	enum surface_pixel_format format;
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	enum swizzle_mode_values swizzle_mode;
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	enum dc_scan_direction scan;
};

struct dc_dcc_setting {
	unsigned int max_compressed_blk_size;
	unsigned int max_uncompressed_blk_size;
	bool independent_64b_blks;
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	//These bitfields to be used starting with DCN
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	struct {
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		uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case)
		uint32_t dcc_128_128_uncontrained : 1;  //available in ASICs before DCN
		uint32_t dcc_256_128_128 : 1;		//available starting with DCN
		uint32_t dcc_256_256_unconstrained : 1;  //available in ASICs before DCN (the best compression case)
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	} dcc_controls;
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};

struct dc_surface_dcc_cap {
	union {
		struct {
			struct dc_dcc_setting rgb;
		} grph;

		struct {
			struct dc_dcc_setting luma;
			struct dc_dcc_setting chroma;
		} video;
	};
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	bool capable;
	bool const_color_support;
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};

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struct dc_static_screen_params {
	struct {
		bool force_trigger;
		bool cursor_update;
		bool surface_update;
		bool overlay_update;
	} triggers;
	unsigned int num_frames;
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};

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/* Surface update type is used by dc_update_surfaces_and_stream
 * The update type is determined at the very beginning of the function based
 * on parameters passed in and decides how much programming (or updating) is
 * going to be done during the call.
 *
 * UPDATE_TYPE_FAST is used for really fast updates that do not require much
 * logical calculations or hardware register programming. This update MUST be
 * ISR safe on windows. Currently fast update will only be used to flip surface
 * address.
 *
 * UPDATE_TYPE_MED is used for slower updates which require significant hw
 * re-programming however do not affect bandwidth consumption or clock
 * requirements. At present, this is the level at which front end updates
 * that do not require us to run bw_calcs happen. These are in/out transfer func
 * updates, viewport offset changes, recout size changes and pixel depth changes.
 * This update can be done at ISR, but we want to minimize how often this happens.
 *
 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or
 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
 * a full update. This cannot be done at ISR level and should be a rare event.
 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
 * underscan we don't expect to see this call at all.
 */

enum surface_update_type {
	UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
	UPDATE_TYPE_MED,  /* ISR safe, most of programming needed, no bw/clk change*/
	UPDATE_TYPE_FULL, /* may need to shuffle resources */
};

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/* Forward declaration*/
struct dc;
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struct dc_plane_state;
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struct dc_state;
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struct dc_cap_funcs {
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	bool (*get_dcc_compression_cap)(const struct dc *dc,
			const struct dc_dcc_surface_param *input,
			struct dc_surface_dcc_cap *output);
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};

struct link_training_settings;

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union allow_lttpr_non_transparent_mode {
	struct {
		bool DP1_4A : 1;
		bool DP2_0 : 1;
	} bits;
	unsigned char raw;
};
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/* Structure to hold configuration flags set by dm at dc creation. */
struct dc_config {
	bool gpu_vm_support;
	bool disable_disp_pll_sharing;
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	bool fbc_support;
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	bool disable_fractional_pwm;
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	bool allow_seamless_boot_optimization;
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	bool seamless_boot_edp_requested;
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	bool edp_not_connected;
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	bool edp_no_power_sequencing;
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	bool force_enum_edp;
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	bool forced_clocks;
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	union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode;
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	bool multi_mon_pp_mclk_switch;
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	bool disable_dmcu;
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	bool enable_4to1MPC;
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	bool enable_windowed_mpo_odm;
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	uint32_t allow_edp_hotplug_detection;
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	bool clamp_min_dcfclk;
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	uint64_t vblank_alignment_dto_params;
	uint8_t  vblank_alignment_max_frame_time_diff;
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	bool is_asymmetric_memory;
	bool is_single_rank_dimm;
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	bool use_pipe_ctx_sync_logic;
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	bool ignore_dpref_ss;
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	bool enable_mipi_converter_optimization;
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};

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enum visual_confirm {
	VISUAL_CONFIRM_DISABLE = 0,
	VISUAL_CONFIRM_SURFACE = 1,
	VISUAL_CONFIRM_HDR = 2,
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	VISUAL_CONFIRM_MPCTREE = 4,
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	VISUAL_CONFIRM_PSR = 5,
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	VISUAL_CONFIRM_SWAPCHAIN = 6,
	VISUAL_CONFIRM_FAMS = 7,
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	VISUAL_CONFIRM_SWIZZLE = 9,
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};

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enum dc_psr_power_opts {
	psr_power_opt_invalid = 0x0,
	psr_power_opt_smu_opt_static_screen = 0x1,
	psr_power_opt_z10_static_screen = 0x10,
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	psr_power_opt_ds_disable_allow = 0x100,
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};

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enum dml_hostvm_override_opts {
	DML_HOSTVM_NO_OVERRIDE = 0x0,
	DML_HOSTVM_OVERRIDE_FALSE = 0x1,
	DML_HOSTVM_OVERRIDE_TRUE = 0x2,
};

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enum dcc_option {
	DCC_ENABLE = 0,
	DCC_DISABLE = 1,
	DCC_HALF_REQ_DISALBE = 2,
};

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enum pipe_split_policy {
	MPC_SPLIT_DYNAMIC = 0,
	MPC_SPLIT_AVOID = 1,
	MPC_SPLIT_AVOID_MULT_DISP = 2,
};

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enum wm_report_mode {
	WM_REPORT_DEFAULT = 0,
	WM_REPORT_OVERRIDE = 1,
};
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enum dtm_pstate{
	dtm_level_p0 = 0,/*highest voltage*/
	dtm_level_p1,
	dtm_level_p2,
	dtm_level_p3,
	dtm_level_p4,/*when active_display_count = 0*/
};
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enum dcn_pwr_state {
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	DCN_PWR_STATE_UNKNOWN = -1,
	DCN_PWR_STATE_MISSION_MODE = 0,
	DCN_PWR_STATE_LOW_POWER = 3,
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};

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enum dcn_zstate_support_state {
	DCN_ZSTATE_SUPPORT_UNKNOWN,
	DCN_ZSTATE_SUPPORT_ALLOW,
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	DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY,
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	DCN_ZSTATE_SUPPORT_DISALLOW,
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};
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/*
 * For any clocks that may differ per pipe
 * only the max is stored in this structure
 */
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struct dc_clocks {
	int dispclk_khz;
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	int actual_dispclk_khz;
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	int dppclk_khz;
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	int actual_dppclk_khz;
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	int disp_dpp_voltage_level_khz;
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	int dcfclk_khz;
	int socclk_khz;
	int dcfclk_deep_sleep_khz;
	int fclk_khz;
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	int phyclk_khz;
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	int dramclk_khz;
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	bool p_state_change_support;
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	enum dcn_zstate_support_state zstate_support;
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	bool dtbclk_en;
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	int ref_dtbclk_khz;
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	bool fclk_p_state_change_support;
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	enum dcn_pwr_state pwr_state;
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	/*
	 * Elements below are not compared for the purposes of
	 * optimization required
	 */
	bool prev_p_state_change_support;
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	bool fclk_prev_p_state_change_support;
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	int num_ways;
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	bool fw_based_mclk_switching;
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	bool fw_based_mclk_switching_shut_down;
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	int prev_num_ways;
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	enum dtm_pstate dtm_level;
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	int max_supported_dppclk_khz;
	int max_supported_dispclk_khz;
	int bw_dppclk_khz; /*a copy of dppclk_khz*/
	int bw_dispclk_khz;
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};

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struct dc_bw_validation_profile {
	bool enable;

	unsigned long long total_ticks;
	unsigned long long voltage_level_ticks;
	unsigned long long watermark_ticks;
	unsigned long long rq_dlg_ticks;

	unsigned long long total_count;
	unsigned long long skip_fast_count;
	unsigned long long skip_pass_count;
	unsigned long long skip_fail_count;
};

#define BW_VAL_TRACE_SETUP() \
		unsigned long long end_tick = 0; \
		unsigned long long voltage_level_tick = 0; \
		unsigned long long watermark_tick = 0; \
		unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
				dm_get_timestamp(dc->ctx) : 0

#define BW_VAL_TRACE_COUNT() \
		if (dc->debug.bw_val_profile.enable) \
			dc->debug.bw_val_profile.total_count++

#define BW_VAL_TRACE_SKIP(status) \
		if (dc->debug.bw_val_profile.enable) { \
			if (!voltage_level_tick) \
				voltage_level_tick = dm_get_timestamp(dc->ctx); \
			dc->debug.bw_val_profile.skip_ ## status ## _count++; \
		}

#define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \
		if (dc->debug.bw_val_profile.enable) \
			voltage_level_tick = dm_get_timestamp(dc->ctx)

#define BW_VAL_TRACE_END_WATERMARKS() \
		if (dc->debug.bw_val_profile.enable) \
			watermark_tick = dm_get_timestamp(dc->ctx)

#define BW_VAL_TRACE_FINISH() \
		if (dc->debug.bw_val_profile.enable) { \
			end_tick = dm_get_timestamp(dc->ctx); \
			dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \
			dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \
			if (watermark_tick) { \
				dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \
				dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \
			} \
		}
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union mem_low_power_enable_options {
	struct {
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		bool vga: 1;
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		bool i2c: 1;
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		bool dmcu: 1;
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		bool dscl: 1;
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		bool cm: 1;
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		bool mpc: 1;
		bool optc: 1;
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		bool vpg: 1;
		bool afmt: 1;
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	} bits;
	uint32_t u32All;
};

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union root_clock_optimization_options {
	struct {
		bool dpp: 1;
		bool dsc: 1;
		bool hdmistream: 1;
		bool hdmichar: 1;
		bool dpstream: 1;
		bool symclk32_se: 1;
		bool symclk32_le: 1;
		bool symclk_fe: 1;
		bool physymclk: 1;
		bool dpiasymclk: 1;
		uint32_t reserved: 22;
	} bits;
	uint32_t u32All;
};

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union dpia_debug_options {
	struct {
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		uint32_t disable_dpia:1; /* bit 0 */
		uint32_t force_non_lttpr:1; /* bit 1 */
		uint32_t extend_aux_rd_interval:1; /* bit 2 */
		uint32_t disable_mst_dsc_work_around:1; /* bit 3 */
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		uint32_t enable_force_tbt3_work_around:1; /* bit 4 */
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		uint32_t reserved:27;
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	} bits;
	uint32_t raw;
};

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/* AUX wake work around options
 * 0: enable/disable work around
 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS
 * 15-2: reserved
 * 31-16: timeout in ms
 */
union aux_wake_wa_options {
	struct {
		uint32_t enable_wa : 1;
		uint32_t use_default_timeout : 1;
		uint32_t rsvd: 14;
		uint32_t timeout_ms : 16;
	} bits;
	uint32_t raw;
};

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struct dc_debug_data {
	uint32_t ltFailCount;
	uint32_t i2cErrorCount;
	uint32_t auxErrorCount;
};

struct dc_phy_addr_space_config {
	struct {
		uint64_t start_addr;
		uint64_t end_addr;
		uint64_t fb_top;
		uint64_t fb_offset;
		uint64_t fb_base;
		uint64_t agp_top;
		uint64_t agp_bot;
		uint64_t agp_base;
	} system_aperture;

	struct {
		uint64_t page_table_start_addr;
		uint64_t page_table_end_addr;
		uint64_t page_table_base_addr;
		bool base_addr_is_mc_addr;
	} gart_config;

	bool valid;
	bool is_hvm_enabled;
	uint64_t page_table_default_page_addr;
};

struct dc_virtual_addr_space_config {
	uint64_t	page_table_base_addr;
	uint64_t	page_table_start_addr;
	uint64_t	page_table_end_addr;
	uint32_t	page_table_block_size_in_bytes;
	uint8_t		page_table_depth; // 1 = 1 level, 2 = 2 level, etc.  0 = invalid
};

struct dc_bounding_box_overrides {
	int sr_exit_time_ns;
	int sr_enter_plus_exit_time_ns;
	int urgent_latency_ns;
	int percent_of_ideal_drambw;
	int dram_clock_change_latency_ns;
	int dummy_clock_change_latency_ns;
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	int fclk_clock_change_latency_ns;
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	/* This forces a hard min on the DCFCLK we use
	 * for DML.  Unlike the debug option for forcing
	 * DCFCLK, this override affects watermark calculations
	 */
	int min_dcfclk_mhz;
};

struct dc_state;
struct resource_pool;
struct dce_hwseq;

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struct dc_debug_options {
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	bool native422_support;
	bool disable_dsc;
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	enum visual_confirm visual_confirm;
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	int visual_confirm_rect_height;

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	bool sanity_checks;
632 633
	bool max_disp_clk;
	bool surface_trace;
634
	bool timing_trace;
635
	bool clock_trace;
636
	bool validation_trace;
637
	bool bandwidth_calcs_trace;
638
	int max_downscale_src_width;
639 640

	/* stutter efficiency related */
641
	bool disable_stutter;
642
	bool use_max_lb;
643
	enum dcc_option disable_dcc;
644 645
	enum pipe_split_policy pipe_split_policy;
	bool force_single_disp_pipe_split;
646
	bool voltage_align_fclk;
647
	bool disable_min_fclk;
648

649
	bool disable_dfs_bypass;
650 651
	bool disable_dpp_power_gate;
	bool disable_hubp_power_gate;
652
	bool disable_dsc_power_gate;
653
	int dsc_min_slice_height_override;
654
	int dsc_bpp_increment_div;
655
	bool disable_pplib_wm_range;
656
	enum wm_report_mode pplib_wm_report_mode;
657
	unsigned int min_disp_clk_khz;
658
	unsigned int min_dpp_clk_khz;
659
	unsigned int min_dram_clk_khz;
660 661
	int sr_exit_time_dpm0_ns;
	int sr_enter_plus_exit_time_dpm0_ns;
662 663 664
	int sr_exit_time_ns;
	int sr_enter_plus_exit_time_ns;
	int urgent_latency_ns;
665
	uint32_t underflow_assert_delay_us;
666 667
	int percent_of_ideal_drambw;
	int dram_clock_change_latency_ns;
668
	bool optimized_watermark;
669
	int always_scale;
670
	bool disable_pplib_clock_request;
671
	bool disable_clock_gate;
672
	bool disable_mem_low_power;
673
	bool pstate_enabled;
674
	bool disable_dmcu;
675
	bool disable_psr;
676
	bool force_abm_enable;
677
	bool disable_stereo_support;
678
	bool vsr_support;
679
	bool performance_trace;
680
	bool az_endpoint_mute_only;
681
	bool always_use_regamma;
682
	bool recovery_enabled;
683
	bool avoid_vbios_exec_table;
684
	bool scl_reset_length10;
685
	bool hdmi20_disable;
686
	bool skip_detection_link_training;
R
Raymond Yang 已提交
687
	uint32_t edid_read_retry_times;
688
	unsigned int force_odm_combine; //bit vector based on otg inst
689
	unsigned int seamless_boot_odm_combine;
690
	unsigned int force_odm_combine_4to1; //bit vector based on otg inst
691
	bool disable_z9_mpc;
692
	unsigned int force_fclk_khz;
693
	bool enable_tri_buf;
694 695
	bool dmub_offload_enabled;
	bool dmcub_emulation;
696
	bool disable_idle_power_optimizations;
697
	unsigned int mall_size_override;
698 699
	unsigned int mall_additional_timer_percent;
	bool mall_error_as_fatal;
700
	bool dmub_command_table; /* for testing only */
701
	struct dc_bw_validation_profile bw_val_profile;
702
	bool disable_fec;
703
	bool disable_48mhz_pwrdwn;
704 705 706 707
	/* This forces a hard min on the DCFCLK requested to SMU/PP
	 * watermarks are not affected.
	 */
	unsigned int force_min_dcfclk_mhz;
708
	int dwb_fi_phase;
709
	bool disable_timing_sync;
710
	bool cm_in_bypass;
711
	int force_clock_mode;/*every mode change.*/
712

713
	bool disable_dram_clock_change_vactive_support;
714
	bool validate_dml_output;
715
	bool enable_dmcub_surface_flip;
716
	bool usbc_combo_phy_reset_wa;
717 718
	bool disable_dsc_edp;
	unsigned int  force_dsc_edp_policy;
719
	bool enable_dram_clock_change_one_display_vactive;
720 721
	/* TODO - remove once tested */
	bool legacy_dp2_lt;
722
	bool set_mst_en_for_sst;
723
	bool disable_uhbr;
724
	bool force_dp2_lt_fallback_method;
725
	bool ignore_cable_id;
726
	union mem_low_power_enable_options enable_mem_low_power;
727
	union root_clock_optimization_options root_clock_optimization;
728
	bool hpo_optimization;
729
	bool force_vblank_alignment;
730 731 732

	/* Enable dmub aux for legacy ddc */
	bool enable_dmub_aux_for_legacy_ddc;
733
	bool disable_fams;
734
	bool optimize_edp_link_rate; /* eDP ILR */
735 736
	/* FEC/PSR1 sequence enable delay in 100us */
	uint8_t fec_enable_delay_in100us;
737
	bool enable_driver_sequence_debug;
738 739
	enum det_size crb_alloc_policy;
	int crb_alloc_policy_min_disp_count;
740
	bool disable_z10;
741
	bool enable_z9_disable_interface;
742
	bool enable_sw_cntl_psr;
743
	union dpia_debug_options dpia_debug;
744
	bool disable_fixed_vs_aux_timeout_wa;
745 746 747
	bool force_disable_subvp;
	bool force_subvp_mclk_switch;
	bool force_usr_allow;
748 749
	/* uses value at boot and disables switch */
	bool disable_dtb_ref_clk_switch;
750
	uint32_t fixed_vs_aux_delay_config_wa;
751
	bool extended_blank_optimization;
752
	union aux_wake_wa_options aux_wake_wa;
753
	uint32_t mst_start_top_delay;
754
	uint8_t psr_power_use_phy_fsm;
755
	enum dml_hostvm_override_opts dml_hostvm_override;
756
	bool dml_disallow_alternate_prefetch_modes;
757
	bool use_legacy_soc_bb_mechanism;
758
	bool exit_idle_opt_for_cursor_updates;
759 760
	bool enable_single_display_2to1_odm_policy;
	bool enable_dp_dig_pixel_rate_div_policy;
761
};
762

763
struct gpu_info_soc_bounding_box_v1_0;
764
struct dc {
765
	struct dc_debug_options debug;
766
	struct dc_versions versions;
767 768 769
	struct dc_caps caps;
	struct dc_cap_funcs cap_funcs;
	struct dc_config config;
770
	struct dc_bounding_box_overrides bb_overrides;
771
	struct dc_bug_wa work_arounds;
772
	struct dc_context *ctx;
773
	struct dc_phy_addr_space_config vm_pa_config;
774 775 776 777

	uint8_t link_count;
	struct dc_link *links[MAX_PIPES * 2];

778
	struct dc_state *current_state;
779 780
	struct resource_pool *res_pool;

781 782
	struct clk_mgr *clk_mgr;

783 784 785 786 787 788 789 790 791 792 793 794 795 796
	/* Display Engine Clock levels */
	struct dm_pp_clock_levels sclk_lvls;

	/* Inputs into BW and WM calculations. */
	struct bw_calcs_dceip *bw_dceip;
	struct bw_calcs_vbios *bw_vbios;
	struct dcn_soc_bounding_box *dcn_soc;
	struct dcn_ip_params *dcn_ip;
	struct display_mode_lib dml;

	/* HW functions */
	struct hw_sequencer_funcs hwss;
	struct dce_hwseq *hwseq;

797
	/* Require to optimize clocks and bandwidth for added/removed planes */
798
	bool optimized_required;
799
	bool wm_optimized_required;
800
	bool idle_optimizations_allowed;
801
	bool enable_c20_dtm_b0;
802

803 804
	/* Require to maintain clocks and bandwidth for UEFI enabled HW */

805 806
	/* FBC compressor */
	struct compressor *fbc_compressor;
807 808

	struct dc_debug_data debug_data;
809
	struct dpcd_vendor_signature vendor_signature;
810 811

	const char *build_id;
812
	struct vm_helper *vm_helper;
813 814

	uint32_t *dcn_reg_offsets;
815
	uint32_t *nbio_reg_offsets;
816 817
};

818 819 820 821 822 823 824 825 826 827 828
enum frame_buffer_mode {
	FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
	FRAME_BUFFER_MODE_ZFB_ONLY,
	FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
} ;

struct dchub_init_data {
	int64_t zfb_phys_addr_base;
	int64_t zfb_mc_base_addr;
	uint64_t zfb_size_in_byte;
	enum frame_buffer_mode fb_mode;
829 830
	bool dchub_initialzied;
	bool dchub_info_valid;
831 832
};

833 834 835 836
struct dc_init_data {
	struct hw_asic_id asic_id;
	void *driver; /* ctx */
	struct cgs_device *cgs_device;
837
	struct dc_bounding_box_overrides bb_overrides;
838 839 840 841 842 843 844 845 846

	int num_virtual_links;
	/*
	 * If 'vbios_override' not NULL, it will be called instead
	 * of the real VBIOS. Intended use is Diagnostics on FPGA.
	 */
	struct dc_bios *vbios_override;
	enum dce_environment dce_environment;

847 848
	struct dmub_offload_funcs *dmub_if;
	struct dc_reg_helper_state *dmub_offload;
849

850
	struct dc_config flags;
851 852
	uint64_t log_mask;

853
	struct dpcd_vendor_signature vendor_signature;
854
	bool force_smu_not_present;
855 856 857 858 859 860 861 862
	/*
	 * IP offset for run time initializaion of register addresses
	 *
	 * DCN3.5+ will fail dc_create() if these fields are null for them. They are
	 * applicable starting with DCN32/321 and are not used for ASICs upstreamed
	 * before them.
	 */
	uint32_t *dcn_reg_offsets;
863
	uint32_t *nbio_reg_offsets;
864 865
};

866
struct dc_callback_init {
867 868 869
#ifdef CONFIG_DRM_AMD_DC_HDCP
	struct cp_psp cp_psp;
#else
870
	uint8_t reserved;
871
#endif
872
};
873

874
struct dc *dc_create(const struct dc_init_data *init_params);
875 876
void dc_hardware_init(struct dc *dc);

877 878 879 880
int dc_get_vmid_use_vector(struct dc *dc);
void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);
/* Returns the number of vmids supported */
int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);
881 882
void dc_init_callbacks(struct dc *dc,
		const struct dc_callback_init *init_params);
883
void dc_deinit_callbacks(struct dc *dc);
884 885 886 887 888 889 890
void dc_destroy(struct dc **dc);

/*******************************************************************************
 * Surface Interfaces
 ******************************************************************************/

enum {
891
	TRANSFER_FUNC_POINTS = 1025
892 893
};

894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910
struct dc_hdr_static_metadata {
	/* display chromaticities and white point in units of 0.00001 */
	unsigned int chromaticity_green_x;
	unsigned int chromaticity_green_y;
	unsigned int chromaticity_blue_x;
	unsigned int chromaticity_blue_y;
	unsigned int chromaticity_red_x;
	unsigned int chromaticity_red_y;
	unsigned int chromaticity_white_point_x;
	unsigned int chromaticity_white_point_y;

	uint32_t min_luminance;
	uint32_t max_luminance;
	uint32_t maximum_content_light_level;
	uint32_t maximum_frame_average_light_level;
};

911 912 913
enum dc_transfer_func_type {
	TF_TYPE_PREDEFINED,
	TF_TYPE_DISTRIBUTED_POINTS,
914
	TF_TYPE_BYPASS,
915
	TF_TYPE_HWPWL
916 917 918
};

struct dc_transfer_func_distributed_points {
919 920 921 922
	struct fixed31_32 red[TRANSFER_FUNC_POINTS];
	struct fixed31_32 green[TRANSFER_FUNC_POINTS];
	struct fixed31_32 blue[TRANSFER_FUNC_POINTS];

923
	uint16_t end_exponent;
924 925 926
	uint16_t x_point_at_y1_red;
	uint16_t x_point_at_y1_green;
	uint16_t x_point_at_y1_blue;
927 928 929 930 931
};

enum dc_transfer_func_predefined {
	TRANSFER_FUNCTION_SRGB,
	TRANSFER_FUNCTION_BT709,
932
	TRANSFER_FUNCTION_PQ,
933
	TRANSFER_FUNCTION_LINEAR,
934
	TRANSFER_FUNCTION_UNITY,
V
Vitaly Prosyak 已提交
935
	TRANSFER_FUNCTION_HLG,
936
	TRANSFER_FUNCTION_HLG12,
937 938 939
	TRANSFER_FUNCTION_GAMMA22,
	TRANSFER_FUNCTION_GAMMA24,
	TRANSFER_FUNCTION_GAMMA26
940 941
};

942

943
struct dc_transfer_func {
944
	struct kref refcount;
945 946
	enum dc_transfer_func_type type;
	enum dc_transfer_func_predefined tf;
947 948
	/* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/
	uint32_t sdr_ref_white_level;
949 950 951 952
	union {
		struct pwl_params pwl;
		struct dc_transfer_func_distributed_points tf_pts;
	};
953 954
};

955

956 957 958 959 960 961 962 963 964 965 966 967 968
union dc_3dlut_state {
	struct {
		uint32_t initialized:1;		/*if 3dlut is went through color module for initialization */
		uint32_t rmu_idx_valid:1;	/*if mux settings are valid*/
		uint32_t rmu_mux_num:3;		/*index of mux to use*/
		uint32_t mpc_rmu0_mux:4;	/*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/
		uint32_t mpc_rmu1_mux:4;
		uint32_t mpc_rmu2_mux:4;
		uint32_t reserved:15;
	} bits;
	uint32_t raw;
};

969 970 971 972

struct dc_3dlut {
	struct kref refcount;
	struct tetrahedral_params lut_3d;
973
	struct fixed31_32 hdr_multiplier;
974
	union dc_3dlut_state state;
975
};
976 977 978 979 980
/*
 * This structure is filled in by dc_surface_get_status and contains
 * the last requested address and the currently active address so the called
 * can determine if there are any outstanding flips
 */
981
struct dc_plane_status {
982 983 984 985 986 987
	struct dc_plane_address requested_address;
	struct dc_plane_address current_address;
	bool is_flip_pending;
	bool is_right_eye;
};

988 989 990
union surface_update_flags {

	struct {
991
		uint32_t addr_update:1;
992
		/* Medium updates */
993
		uint32_t dcc_change:1;
994 995 996
		uint32_t color_space_change:1;
		uint32_t horizontal_mirror_change:1;
		uint32_t per_pixel_alpha_change:1;
997
		uint32_t global_alpha_change:1;
998
		uint32_t hdr_mult:1;
999 1000 1001 1002
		uint32_t rotation_change:1;
		uint32_t swizzle_change:1;
		uint32_t scaling_change:1;
		uint32_t position_change:1;
1003
		uint32_t in_transfer_func_change:1;
1004
		uint32_t input_csc_change:1;
1005
		uint32_t coeff_reduction_change:1;
1006
		uint32_t output_tf_change:1;
1007
		uint32_t pixel_format_change:1;
1008
		uint32_t plane_size_change:1;
1009
		uint32_t gamut_remap_change:1;
1010 1011 1012 1013

		/* Full updates */
		uint32_t new_plane:1;
		uint32_t bpp_change:1;
1014
		uint32_t gamma_change:1;
1015 1016 1017
		uint32_t bandwidth_change:1;
		uint32_t clock_change:1;
		uint32_t stereo_format_change:1;
1018
		uint32_t lut_3d:1;
1019
		uint32_t full_update:1;
1020 1021 1022 1023 1024
	} bits;

	uint32_t raw;
};

1025
struct dc_plane_state {
1026
	struct dc_plane_address address;
1027
	struct dc_plane_flip_time time;
1028
	bool triplebuffer_flips;
1029 1030 1031 1032 1033
	struct scaling_taps scaling_quality;
	struct rect src_rect;
	struct rect dst_rect;
	struct rect clip_rect;

1034
	struct plane_size plane_size;
1035
	union dc_tiling_info tiling_info;
1036

1037
	struct dc_plane_dcc_param dcc;
1038

1039
	struct dc_gamma *gamma_correction;
1040
	struct dc_transfer_func *in_transfer_func;
1041
	struct dc_bias_and_scale *bias_and_scale;
1042
	struct dc_csc_transform input_csc_color_matrix;
1043
	struct fixed31_32 coeff_reduction_factor;
1044
	struct fixed31_32 hdr_mult;
1045
	struct colorspace_transform gamut_remap_matrix;
1046

1047 1048
	// TODO: No longer used, remove
	struct dc_hdr_static_metadata hdr_static_ctx;
1049

1050
	enum dc_color_space color_space;
1051

1052 1053 1054 1055
	struct dc_3dlut *lut3d_func;
	struct dc_transfer_func *in_shaper_func;
	struct dc_transfer_func *blend_tf;

1056
	struct dc_transfer_func *gamcor_tf;
1057 1058 1059 1060
	enum surface_pixel_format format;
	enum dc_rotation_angle rotation;
	enum plane_stereo_format stereo_format;

1061
	bool is_tiling_rotated;
1062
	bool per_pixel_alpha;
1063
	bool pre_multiplied_alpha;
1064 1065
	bool global_alpha;
	int  global_alpha_value;
1066 1067 1068
	bool visible;
	bool flip_immediate;
	bool horizontal_mirror;
1069
	int layer_index;
1070

1071
	union surface_update_flags update_flags;
1072
	bool flip_int_enabled;
1073 1074
	bool skip_manual_trigger;

1075
	/* private to DC core */
1076
	struct dc_plane_status status;
1077 1078
	struct dc_context *ctx;

1079 1080 1081
	/* HACK: Workaround for forcing full reprogramming under some conditions */
	bool force_full_update;

1082 1083
	bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead

1084 1085
	/* private to dc_surface.c */
	enum dc_irq_source irq_source;
1086
	struct kref refcount;
1087 1088 1089
};

struct dc_plane_info {
1090
	struct plane_size plane_size;
1091
	union dc_tiling_info tiling_info;
1092
	struct dc_plane_dcc_param dcc;
1093 1094 1095
	enum surface_pixel_format format;
	enum dc_rotation_angle rotation;
	enum plane_stereo_format stereo_format;
1096
	enum dc_color_space color_space;
1097
	bool horizontal_mirror;
1098
	bool visible;
1099
	bool per_pixel_alpha;
1100
	bool pre_multiplied_alpha;
1101 1102
	bool global_alpha;
	int  global_alpha_value;
1103
	bool input_csc_enabled;
1104
	int layer_index;
1105 1106 1107
};

struct dc_scaling_info {
1108 1109 1110 1111
	struct rect src_rect;
	struct rect dst_rect;
	struct rect clip_rect;
	struct scaling_taps scaling_quality;
1112 1113 1114
};

struct dc_surface_update {
1115
	struct dc_plane_state *surface;
1116 1117

	/* isr safe update parameters.  null means no updates */
1118 1119 1120
	const struct dc_flip_addrs *flip_addr;
	const struct dc_plane_info *plane_info;
	const struct dc_scaling_info *scaling_info;
1121
	struct fixed31_32 hdr_mult;
1122 1123 1124
	/* following updates require alloc/sleep/spin that is not isr safe,
	 * null means no updates
	 */
1125 1126
	const struct dc_gamma *gamma;
	const struct dc_transfer_func *in_transfer_func;
1127

1128 1129
	const struct dc_csc_transform *input_csc_color_matrix;
	const struct fixed31_32 *coeff_reduction_factor;
1130 1131
	const struct dc_transfer_func *func_shaper;
	const struct dc_3dlut *lut3d_func;
1132
	const struct dc_transfer_func *blend_tf;
1133
	const struct colorspace_transform *gamut_remap_matrix;
1134 1135 1136 1137 1138
};

/*
 * Create a new surface with default parameters;
 */
1139
struct dc_plane_state *dc_create_plane_state(struct dc *dc);
1140 1141
const struct dc_plane_status *dc_plane_get_status(
		const struct dc_plane_state *plane_state);
1142

1143 1144
void dc_plane_state_retain(struct dc_plane_state *plane_state);
void dc_plane_state_release(struct dc_plane_state *plane_state);
1145

1146 1147
void dc_gamma_retain(struct dc_gamma *dc_gamma);
void dc_gamma_release(struct dc_gamma **dc_gamma);
1148 1149
struct dc_gamma *dc_create_gamma(void);

1150 1151
void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
1152
struct dc_transfer_func *dc_create_transfer_func(void);
1153

1154 1155 1156
struct dc_3dlut *dc_create_3dlut_func(void);
void dc_3dlut_func_release(struct dc_3dlut *lut);
void dc_3dlut_func_retain(struct dc_3dlut *lut);
1157

1158
void dc_post_update_surfaces_to_stream(
1159 1160
		struct dc *dc);

1161
#include "dc_stream.h"
1162

1163
/*
1164
 * Structure to store surface/stream associations for validation
1165 1166
 */
struct dc_validation_set {
1167
	struct dc_stream_state *stream;
1168 1169
	struct dc_plane_state *plane_states[MAX_SURFACES];
	uint8_t plane_count;
1170 1171
};

1172
bool dc_validate_boot_timing(const struct dc *dc,
1173 1174 1175
				const struct dc_sink *sink,
				struct dc_crtc_timing *crtc_timing);

1176
enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
1177

1178 1179
void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info);

1180 1181 1182
bool dc_set_generic_gpio_for_stereo(bool enable,
		struct gpio_service *gpio_service);

1183 1184 1185 1186
/*
 * fast_validate: we return after determining if we can support the new state,
 * but before we populate the programming info
 */
1187
enum dc_status dc_validate_global_state(
1188
		struct dc *dc,
1189 1190
		struct dc_state *new_ctx,
		bool fast_validate);
1191

1192 1193 1194 1195 1196

void dc_resource_state_construct(
		const struct dc *dc,
		struct dc_state *dst_ctx);

1197 1198 1199 1200 1201 1202
bool dc_acquire_release_mpc_3dlut(
		struct dc *dc, bool acquire,
		struct dc_stream_state *stream,
		struct dc_3dlut **lut,
		struct dc_transfer_func **shaper);

1203
void dc_resource_state_copy_construct(
1204 1205
		const struct dc_state *src_ctx,
		struct dc_state *dst_ctx);
1206

1207
void dc_resource_state_copy_construct_current(
1208
		const struct dc *dc,
1209
		struct dc_state *dst_ctx);
1210

1211
void dc_resource_state_destruct(struct dc_state *context);
1212

1213 1214
bool dc_resource_is_dsc_encoding_supported(const struct dc *dc);

1215 1216 1217 1218 1219 1220 1221 1222 1223
/*
 * TODO update to make it about validation sets
 * Set up streams and links associated to drive sinks
 * The streams parameter is an absolute set of all active streams.
 *
 * After this call:
 *   Phy, Encoder, Timing Generator are programmed and enabled.
 *   New streams are enabled with blank stream; no memory read.
 */
1224
bool dc_commit_state(struct dc *dc, struct dc_state *context);
1225

1226 1227
struct dc_state *dc_create_state(struct dc *dc);
struct dc_state *dc_copy_state(struct dc_state *src_ctx);
1228 1229
void dc_retain_state(struct dc_state *context);
void dc_release_state(struct dc_state *context);
1230

1231 1232 1233 1234
/*******************************************************************************
 * Link Interfaces
 ******************************************************************************/

1235 1236 1237 1238
struct dpcd_caps {
	union dpcd_rev dpcd_rev;
	union max_lane_count max_ln_count;
	union max_down_spread max_down_spread;
1239
	union dprx_feature dprx_feature;
1240

1241 1242 1243
	/* valid only for eDP v1.4 or higher*/
	uint8_t edp_supported_link_rates_count;
	enum dc_link_rate edp_supported_link_rates[8];
1244 1245 1246

	/* dongle type (DP converter, CV smart dongle) */
	enum display_dongle_type dongle_type;
1247
	bool is_dongle_type_one;
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	/* branch device or sink device */
	bool is_branch_dev;
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	/* Dongle's downstream count. */
	union sink_count sink_count;
1252
	bool is_mst_capable;
1253 1254 1255 1256 1257
	/* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
	indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
	struct dc_dongle_caps dongle_caps;

	uint32_t sink_dev_id;
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	int8_t sink_dev_id_str[6];
	int8_t sink_hw_revision;
	int8_t sink_fw_revision[2];

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	uint32_t branch_dev_id;
	int8_t branch_dev_name[6];
	int8_t branch_hw_revision;
1265
	int8_t branch_fw_revision[2];
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	bool allow_invalid_MSA_timing_param;
	bool panel_mode_edp;
1269
	bool dpcd_display_control_capable;
1270
	bool ext_receiver_cap_field_present;
1271
	bool set_power_state_capable_edp;
1272
	bool dynamic_backlight_capable_edp;
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	union dpcd_fec_capability fec_cap;
	struct dpcd_dsc_capabilities dsc_caps;
1275
	struct dc_lttpr_caps lttpr_caps;
1276
	struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info;
1277

1278 1279 1280 1281
	union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates;
	union dp_main_line_channel_coding_cap channel_coding_cap;
	union dp_sink_video_fallback_formats fallback_formats;
	union dp_fec_capability1 fec_cap1;
1282
	union dp_cable_id cable_id;
1283 1284 1285
	uint8_t edp_rev;
	union edp_alpm_caps alpm_caps;
	struct edp_psr_info psr_info;
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};

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union dpcd_sink_ext_caps {
	struct {
		/* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode
		 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode.
		 */
		uint8_t sdr_aux_backlight_control : 1;
		uint8_t hdr_aux_backlight_control : 1;
		uint8_t reserved_1 : 2;
		uint8_t oled : 1;
		uint8_t reserved : 3;
	} bits;
	uint8_t raw;
};

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#if defined(CONFIG_DRM_AMD_DC_HDCP)
union hdcp_rx_caps {
	struct {
		uint8_t version;
		uint8_t reserved;
		struct {
			uint8_t repeater	: 1;
			uint8_t hdcp_capable	: 1;
			uint8_t reserved	: 6;
		} byte0;
	} fields;
	uint8_t raw[3];
};

union hdcp_bcaps {
	struct {
		uint8_t HDCP_CAPABLE:1;
		uint8_t REPEATER:1;
		uint8_t RESERVED:6;
	} bits;
	uint8_t raw;
};

struct hdcp_caps {
	union hdcp_rx_caps rx_caps;
	union hdcp_bcaps bcaps;
};
#endif

1331
#include "dc_link.h"
1332

1333 1334
uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);

1335 1336 1337 1338
/*******************************************************************************
 * Sink Interfaces - A sink corresponds to a display output device
 ******************************************************************************/

1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349
struct dc_container_id {
	// 128bit GUID in binary form
	unsigned char  guid[16];
	// 8 byte port ID -> ELD.PortID
	unsigned int   portId[2];
	// 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
	unsigned short manufacturerName;
	// 2 byte product code -> ELD.ProductCode
	unsigned short productCode;
};

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1351 1352 1353 1354
struct dc_sink_dsc_caps {
	// 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology),
	// 'false' if they are sink's DSC caps
	bool is_virtual_dpcd_dsc;
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#if defined(CONFIG_DRM_AMD_DC_DCN)
	// 'true' if MST topology supports DSC passthrough for sink
	// 'false' if MST topology does not support DSC passthrough
	bool is_dsc_passthrough_supported;
#endif
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	struct dsc_dec_dpcd_caps dsc_dec_caps;
};
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1363 1364 1365 1366 1367
struct dc_sink_fec_caps {
	bool is_rx_fec_supported;
	bool is_topology_fec_supported;
};

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/*
 * The sink structure contains EDID and other display device properties
 */
struct dc_sink {
	enum signal_type sink_signal;
	struct dc_edid dc_edid; /* raw edid */
	struct dc_edid_caps edid_caps; /* parse display caps */
1375
	struct dc_container_id *dc_container_id;
1376
	uint32_t dongle_max_pix_clk;
1377
	void *priv;
1378
	struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
1379
	bool converter_disable_audio;
1380

1381 1382
	struct dc_sink_dsc_caps dsc_caps;
	struct dc_sink_fec_caps fec_caps;
1383

1384 1385
	bool is_vsc_sdp_colorimetry_supported;

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	/* private to DC core */
	struct dc_link *link;
	struct dc_context *ctx;

1390 1391
	uint32_t sink_id;

1392
	/* private to dc_sink.c */
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	// refcount must be the last member in dc_sink, since we want the
	// sink structure to be logically cloneable up to (but not including)
	// refcount
D
Dave Airlie 已提交
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	struct kref refcount;
1397 1398
};

1399 1400
void dc_sink_retain(struct dc_sink *sink);
void dc_sink_release(struct dc_sink *sink);
1401 1402 1403

struct dc_sink_init_data {
	enum signal_type sink_signal;
1404
	struct dc_link *link;
1405 1406 1407 1408
	uint32_t dongle_max_pix_clk;
	bool converter_disable_audio;
};

1409 1410
bool dc_extended_blank_supported(struct dc *dc);

1411 1412 1413 1414 1415 1416 1417 1418
struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);

/* Newer interfaces  */
struct dc_cursor {
	struct dc_plane_address address;
	struct dc_cursor_attributes attributes;
};

1419

1420 1421 1422 1423 1424 1425 1426
/*******************************************************************************
 * Interrupt interfaces
 ******************************************************************************/
enum dc_irq_source dc_interrupt_to_irq_source(
		struct dc *dc,
		uint32_t src_id,
		uint32_t ext_id);
1427
bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
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void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
enum dc_irq_source dc_get_hpd_irq_source_at_index(
		struct dc *dc, uint32_t link_index);

1432 1433
void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable);

1434 1435 1436 1437 1438 1439
/*******************************************************************************
 * Power Interfaces
 ******************************************************************************/

void dc_set_power_state(
		struct dc *dc,
1440
		enum dc_acpi_cm_power_state power_state);
1441
void dc_resume(struct dc *dc);
1442

1443 1444
void dc_power_down_on_boot(struct dc *dc);

1445 1446 1447 1448 1449 1450 1451 1452 1453
#if defined(CONFIG_DRM_AMD_DC_HDCP)
/*
 * HDCP Interfaces
 */
enum hdcp_message_status dc_process_hdcp_msg(
		enum signal_type signal,
		struct dc_link *link,
		struct hdcp_protection_message *message_info);
#endif
1454
bool dc_is_dmcu_initialized(struct dc *dc);
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1456 1457
enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
1458

1459 1460
bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,
				struct dc_cursor_attributes *cursor_attr);
1461

1462 1463
void dc_allow_idle_optimizations(struct dc *dc, bool allow);

1464
/* set min and max memory clock to lowest and highest DPM level, respectively */
1465 1466
void dc_unlock_memory_clock_frequency(struct dc *dc);

1467
/* set min memory clock to the min required for current mode, max to maxDPM */
1468 1469
void dc_lock_memory_clock_frequency(struct dc *dc);

1470 1471 1472
/* set soft max for memclk, to be used for AC/DC switching clock limitations */
void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable);

1473 1474 1475
/* cleanup on driver unload */
void dc_hardware_release(struct dc *dc);

1476 1477 1478
/* disables fw based mclk switch */
void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc);

1479
bool dc_set_psr_allow_active(struct dc *dc, bool enable);
1480
void dc_z10_restore(const struct dc *dc);
1481
void dc_z10_save_init(struct dc *dc);
1482

1483
bool dc_is_dmub_outbox_supported(struct dc *dc);
1484 1485
bool dc_enable_dmub_notifications(struct dc *dc);

1486 1487
void dc_enable_dmub_outbox(struct dc *dc);

1488 1489 1490 1491
bool dc_process_dmub_aux_transfer_async(struct dc *dc,
				uint32_t link_index,
				struct aux_payload *payload);

1492 1493 1494
/* Get dc link index from dpia port index */
uint8_t get_link_index_from_dpia_port_index(const struct dc *dc,
				uint8_t dpia_port_index);
1495 1496 1497 1498 1499

bool dc_process_dmub_set_config_async(struct dc *dc,
				uint32_t link_index,
				struct set_config_cmd_payload *payload,
				struct dmub_notification *notify);
1500 1501 1502 1503 1504 1505

enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,
				uint32_t link_index,
				uint8_t mst_alloc_slots,
				uint8_t *mst_slots_in_use);

1506 1507 1508 1509
/*******************************************************************************
 * DSC Interfaces
 ******************************************************************************/
#include "dc_dsc.h"
1510 1511 1512 1513 1514 1515

/*******************************************************************************
 * Disable acc mode Interfaces
 ******************************************************************************/
void dc_disable_accelerated_mode(struct dc *dc);

1516
#endif /* DC_INTERFACE_H_ */