intel_dp.c 174.5 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Keith Packard <keithp@keithp.com>
 *
 */

#include <linux/i2c.h>
29
#include <linux/slab.h>
30
#include <linux/export.h>
31 32
#include <linux/notifier.h>
#include <linux/reboot.h>
33
#include <drm/drmP.h>
34
#include <drm/drm_atomic_helper.h>
35 36 37
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_edid.h>
38
#include "intel_drv.h"
39
#include <drm/i915_drm.h>
40 41 42 43
#include "i915_drv.h"

#define DP_LINK_CHECK_TIMEOUT	(10 * 1000)

44 45 46 47 48 49
/* Compliance test status bits  */
#define INTEL_DP_RESOLUTION_SHIFT_MASK	0
#define INTEL_DP_RESOLUTION_PREFERRED	(1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
#define INTEL_DP_RESOLUTION_STANDARD	(2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
#define INTEL_DP_RESOLUTION_FAILSAFE	(3 << INTEL_DP_RESOLUTION_SHIFT_MASK)

50
struct dp_link_dpll {
51
	int clock;
52 53 54 55
	struct dpll dpll;
};

static const struct dp_link_dpll gen4_dpll[] = {
56
	{ 162000,
57
		{ .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
58
	{ 270000,
59 60 61 62
		{ .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
};

static const struct dp_link_dpll pch_dpll[] = {
63
	{ 162000,
64
		{ .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
65
	{ 270000,
66 67 68
		{ .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
};

69
static const struct dp_link_dpll vlv_dpll[] = {
70
	{ 162000,
C
Chon Ming Lee 已提交
71
		{ .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
72
	{ 270000,
73 74 75
		{ .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
};

76 77 78 79 80 81 82 83 84 85
/*
 * CHV supports eDP 1.4 that have  more link rates.
 * Below only provides the fixed rate but exclude variable rate.
 */
static const struct dp_link_dpll chv_dpll[] = {
	/*
	 * CHV requires to program fractional division for m2.
	 * m2 is stored in fixed point format using formula below
	 * (m2_int << 22) | m2_fraction
	 */
86
	{ 162000,	/* m2_int = 32, m2_fraction = 1677722 */
87
		{ .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
88
	{ 270000,	/* m2_int = 27, m2_fraction = 0 */
89
		{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
90
	{ 540000,	/* m2_int = 27, m2_fraction = 0 */
91 92
		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
};
93

94 95
static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
				  324000, 432000, 540000 };
96
static const int skl_rates[] = { 162000, 216000, 270000,
97
				  324000, 432000, 540000 };
98 99 100
static const int chv_rates[] = { 162000, 202500, 210000, 216000,
				 243000, 270000, 324000, 405000,
				 420000, 432000, 540000 };
101
static const int default_rates[] = { 162000, 270000, 540000 };
102

103 104 105 106 107 108 109 110 111
/**
 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 * @intel_dp: DP struct
 *
 * If a CPU or PCH DP output is attached to an eDP panel, this function
 * will return true, and false otherwise.
 */
static bool is_edp(struct intel_dp *intel_dp)
{
112 113 114
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
115 116
}

117
static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
118
{
119 120 121
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	return intel_dig_port->base.base.dev;
122 123
}

124 125
static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
{
126
	return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
127 128
}

C
Chris Wilson 已提交
129
static void intel_dp_link_down(struct intel_dp *intel_dp);
130
static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
131
static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
132
static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
133 134
static void vlv_steal_power_sequencer(struct drm_device *dev,
				      enum pipe pipe);
135

136 137 138 139 140
static unsigned int intel_dp_unused_lane_mask(int lane_count)
{
	return ~((1 << lane_count) - 1) & 0xf;
}

141 142
static int
intel_dp_max_link_bw(struct intel_dp  *intel_dp)
143
{
144
	int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
145 146 147 148

	switch (max_link_bw) {
	case DP_LINK_BW_1_62:
	case DP_LINK_BW_2_7:
149
	case DP_LINK_BW_5_4:
150
		break;
151
	default:
152 153
		WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
		     max_link_bw);
154 155 156 157 158 159
		max_link_bw = DP_LINK_BW_1_62;
		break;
	}
	return max_link_bw;
}

160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175
static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	u8 source_max, sink_max;

	source_max = 4;
	if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
	    (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
		source_max = 2;

	sink_max = drm_dp_max_lane_count(intel_dp->dpcd);

	return min(source_max, sink_max);
}

176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192
/*
 * The units on the numbers in the next two are... bizarre.  Examples will
 * make it clearer; this one parallels an example in the eDP spec.
 *
 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 *
 *     270000 * 1 * 8 / 10 == 216000
 *
 * The actual data capacity of that configuration is 2.16Gbit/s, so the
 * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 * 119000.  At 18bpp that's 2142000 kilobits per second.
 *
 * Thus the strange-looking division by 10 in intel_dp_link_required, to
 * get the result in decakilobits instead of kilobits.
 */

193
static int
194
intel_dp_link_required(int pixel_clock, int bpp)
195
{
196
	return (pixel_clock * bpp + 9) / 10;
197 198
}

199 200 201 202 203 204
static int
intel_dp_max_data_rate(int max_link_clock, int max_lanes)
{
	return (max_link_clock * max_lanes * 8) / 10;
}

205
static enum drm_mode_status
206 207 208
intel_dp_mode_valid(struct drm_connector *connector,
		    struct drm_display_mode *mode)
{
209
	struct intel_dp *intel_dp = intel_attached_dp(connector);
210 211
	struct intel_connector *intel_connector = to_intel_connector(connector);
	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
212 213
	int target_clock = mode->clock;
	int max_rate, mode_rate, max_lanes, max_link_clock;
214

215 216
	if (is_edp(intel_dp) && fixed_mode) {
		if (mode->hdisplay > fixed_mode->hdisplay)
217 218
			return MODE_PANEL;

219
		if (mode->vdisplay > fixed_mode->vdisplay)
220
			return MODE_PANEL;
221 222

		target_clock = fixed_mode->clock;
223 224
	}

225
	max_link_clock = intel_dp_max_link_rate(intel_dp);
226
	max_lanes = intel_dp_max_lane_count(intel_dp);
227 228 229 230 231

	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
	mode_rate = intel_dp_link_required(target_clock, 18);

	if (mode_rate > max_rate)
232
		return MODE_CLOCK_HIGH;
233 234 235 236

	if (mode->clock < 10000)
		return MODE_CLOCK_LOW;

237 238 239
	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
		return MODE_H_ILLEGAL;

240 241 242
	return MODE_OK;
}

243
uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
244 245 246 247 248 249 250 251 252 253 254
{
	int	i;
	uint32_t v = 0;

	if (src_bytes > 4)
		src_bytes = 4;
	for (i = 0; i < src_bytes; i++)
		v |= ((uint32_t) src[i]) << ((3-i) * 8);
	return v;
}

255
static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
256 257 258 259 260 261 262 263
{
	int i;
	if (dst_bytes > 4)
		dst_bytes = 4;
	for (i = 0; i < dst_bytes; i++)
		dst[i] = src >> ((3-i) * 8);
}

264 265 266 267 268 269 270
/* hrawclock is 1/4 the FSB frequency */
static int
intel_hrawclk(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t clkcfg;

271 272 273 274
	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
	if (IS_VALLEYVIEW(dev))
		return 200;

275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297
	clkcfg = I915_READ(CLKCFG);
	switch (clkcfg & CLKCFG_FSB_MASK) {
	case CLKCFG_FSB_400:
		return 100;
	case CLKCFG_FSB_533:
		return 133;
	case CLKCFG_FSB_667:
		return 166;
	case CLKCFG_FSB_800:
		return 200;
	case CLKCFG_FSB_1067:
		return 266;
	case CLKCFG_FSB_1333:
		return 333;
	/* these two are just a guess; one of them might be right */
	case CLKCFG_FSB_1600:
	case CLKCFG_FSB_1600_ALT:
		return 400;
	default:
		return 133;
	}
}

298 299
static void
intel_dp_init_panel_power_sequencer(struct drm_device *dev,
300
				    struct intel_dp *intel_dp);
301 302
static void
intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
303
					      struct intel_dp *intel_dp);
304

305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336
static void pps_lock(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *encoder = &intel_dig_port->base;
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum intel_display_power_domain power_domain;

	/*
	 * See vlv_power_sequencer_reset() why we need
	 * a power domain reference here.
	 */
	power_domain = intel_display_port_power_domain(encoder);
	intel_display_power_get(dev_priv, power_domain);

	mutex_lock(&dev_priv->pps_mutex);
}

static void pps_unlock(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *encoder = &intel_dig_port->base;
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum intel_display_power_domain power_domain;

	mutex_unlock(&dev_priv->pps_mutex);

	power_domain = intel_display_port_power_domain(encoder);
	intel_display_power_put(dev_priv, power_domain);
}

337 338 339 340 341 342 343
static void
vlv_power_sequencer_kick(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum pipe pipe = intel_dp->pps_pipe;
344 345 346
	bool pll_enabled, release_cl_override = false;
	enum dpio_phy phy = DPIO_PHY(pipe);
	enum dpio_channel ch = vlv_pipe_to_channel(pipe);
347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369
	uint32_t DP;

	if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
		 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
		 pipe_name(pipe), port_name(intel_dig_port->port)))
		return;

	DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
		      pipe_name(pipe), port_name(intel_dig_port->port));

	/* Preserve the BIOS-computed detected bit. This is
	 * supposed to be read-only.
	 */
	DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
	DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
	DP |= DP_PORT_WIDTH(1);
	DP |= DP_LINK_TRAIN_PAT_1;

	if (IS_CHERRYVIEW(dev))
		DP |= DP_PIPE_SELECT_CHV(pipe);
	else if (pipe == PIPE_B)
		DP |= DP_PIPEB_SELECT;

370 371 372 373 374 375
	pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;

	/*
	 * The DPLL for the pipe must be enabled for this to work.
	 * So enable temporarily it if it's not already enabled.
	 */
376 377 378 379
	if (!pll_enabled) {
		release_cl_override = IS_CHERRYVIEW(dev) &&
			!chv_phy_powergate_ch(dev_priv, phy, ch, true);

380 381
		vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
				 &chv_dpll[0].dpll : &vlv_dpll[0].dpll);
382
	}
383

384 385 386 387 388 389 390 391 392 393 394 395 396 397
	/*
	 * Similar magic as in intel_dp_enable_port().
	 * We _must_ do this port enable + disable trick
	 * to make this power seqeuencer lock onto the port.
	 * Otherwise even VDD force bit won't work.
	 */
	I915_WRITE(intel_dp->output_reg, DP);
	POSTING_READ(intel_dp->output_reg);

	I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
	POSTING_READ(intel_dp->output_reg);

	I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
	POSTING_READ(intel_dp->output_reg);
398

399
	if (!pll_enabled) {
400
		vlv_force_pll_off(dev, pipe);
401 402 403 404

		if (release_cl_override)
			chv_phy_powergate_ch(dev_priv, phy, ch, false);
	}
405 406
}

407 408 409 410 411 412
static enum pipe
vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
413 414
	struct intel_encoder *encoder;
	unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
415
	enum pipe pipe;
416

V
Ville Syrjälä 已提交
417
	lockdep_assert_held(&dev_priv->pps_mutex);
418

419 420 421
	/* We should never land here with regular DP ports */
	WARN_ON(!is_edp(intel_dp));

422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446
	if (intel_dp->pps_pipe != INVALID_PIPE)
		return intel_dp->pps_pipe;

	/*
	 * We don't have power sequencer currently.
	 * Pick one that's not used by other ports.
	 */
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		struct intel_dp *tmp;

		if (encoder->type != INTEL_OUTPUT_EDP)
			continue;

		tmp = enc_to_intel_dp(&encoder->base);

		if (tmp->pps_pipe != INVALID_PIPE)
			pipes &= ~(1 << tmp->pps_pipe);
	}

	/*
	 * Didn't find one. This should not happen since there
	 * are two power sequencers and up to two eDP ports.
	 */
	if (WARN_ON(pipes == 0))
447 448 449
		pipe = PIPE_A;
	else
		pipe = ffs(pipes) - 1;
450

451 452
	vlv_steal_power_sequencer(dev, pipe);
	intel_dp->pps_pipe = pipe;
453 454 455 456 457 458

	DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
		      pipe_name(intel_dp->pps_pipe),
		      port_name(intel_dig_port->port));

	/* init power sequencer on this pipe and port */
459 460
	intel_dp_init_panel_power_sequencer(dev, intel_dp);
	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
461

462 463 464 465 466
	/*
	 * Even vdd force doesn't work until we've made
	 * the power sequencer lock in on the port.
	 */
	vlv_power_sequencer_kick(intel_dp);
467 468 469 470

	return intel_dp->pps_pipe;
}

471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490
typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
			       enum pipe pipe);

static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
			       enum pipe pipe)
{
	return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
}

static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
				enum pipe pipe)
{
	return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
}

static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
			 enum pipe pipe)
{
	return true;
}
491

492
static enum pipe
493 494 495
vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
		     enum port port,
		     vlv_pipe_check pipe_check)
496 497
{
	enum pipe pipe;
498 499 500 501

	for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
		u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
			PANEL_PORT_SELECT_MASK;
502 503 504 505

		if (port_sel != PANEL_PORT_SELECT_VLV(port))
			continue;

506 507 508
		if (!pipe_check(dev_priv, pipe))
			continue;

509
		return pipe;
510 511
	}

512 513 514 515 516 517 518 519 520 521 522 523 524 525
	return INVALID_PIPE;
}

static void
vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = intel_dig_port->port;

	lockdep_assert_held(&dev_priv->pps_mutex);

	/* try to find a pipe with this port selected */
526 527 528 529 530 531 532 533 534 535 536
	/* first pick one where the panel is on */
	intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
						  vlv_pipe_has_pp_on);
	/* didn't find one? pick one where vdd is on */
	if (intel_dp->pps_pipe == INVALID_PIPE)
		intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
							  vlv_pipe_has_vdd_on);
	/* didn't find one? pick one with just the correct port */
	if (intel_dp->pps_pipe == INVALID_PIPE)
		intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
							  vlv_pipe_any);
537 538 539 540 541 542

	/* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
	if (intel_dp->pps_pipe == INVALID_PIPE) {
		DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
			      port_name(port));
		return;
543 544
	}

545 546 547
	DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
		      port_name(port), pipe_name(intel_dp->pps_pipe));

548 549
	intel_dp_init_panel_power_sequencer(dev, intel_dp);
	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
550 551
}

552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578
void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
{
	struct drm_device *dev = dev_priv->dev;
	struct intel_encoder *encoder;

	if (WARN_ON(!IS_VALLEYVIEW(dev)))
		return;

	/*
	 * We can't grab pps_mutex here due to deadlock with power_domain
	 * mutex when power_domain functions are called while holding pps_mutex.
	 * That also means that in order to use pps_pipe the code needs to
	 * hold both a power domain reference and pps_mutex, and the power domain
	 * reference get/put must be done while _not_ holding pps_mutex.
	 * pps_{lock,unlock}() do these steps in the correct order, so one
	 * should use them always.
	 */

	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		struct intel_dp *intel_dp;

		if (encoder->type != INTEL_OUTPUT_EDP)
			continue;

		intel_dp = enc_to_intel_dp(&encoder->base);
		intel_dp->pps_pipe = INVALID_PIPE;
	}
579 580 581 582 583 584
}

static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);

585 586 587
	if (IS_BROXTON(dev))
		return BXT_PP_CONTROL(0);
	else if (HAS_PCH_SPLIT(dev))
588 589 590 591 592 593 594 595 596
		return PCH_PP_CONTROL;
	else
		return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
}

static u32 _pp_stat_reg(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);

597 598 599
	if (IS_BROXTON(dev))
		return BXT_PP_STATUS(0);
	else if (HAS_PCH_SPLIT(dev))
600 601 602 603 604
		return PCH_PP_STATUS;
	else
		return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
}

605 606 607 608 609 610 611 612 613 614 615 616 617 618 619
/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
   This function only applicable when panel PM state is not to be tracked */
static int edp_notify_handler(struct notifier_block *this, unsigned long code,
			      void *unused)
{
	struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
						 edp_notifier);
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp_div;
	u32 pp_ctrl_reg, pp_div_reg;

	if (!is_edp(intel_dp) || code != SYS_RESTART)
		return 0;

620
	pps_lock(intel_dp);
V
Ville Syrjälä 已提交
621

622
	if (IS_VALLEYVIEW(dev)) {
V
Ville Syrjälä 已提交
623 624
		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);

625 626 627 628 629 630 631 632 633 634 635
		pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
		pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
		pp_div = I915_READ(pp_div_reg);
		pp_div &= PP_REFERENCE_DIVIDER_MASK;

		/* 0x1F write to PP_DIV_REG sets max cycle delay */
		I915_WRITE(pp_div_reg, pp_div | 0x1F);
		I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
		msleep(intel_dp->panel_power_cycle_delay);
	}

636
	pps_unlock(intel_dp);
V
Ville Syrjälä 已提交
637

638 639 640
	return 0;
}

641
static bool edp_have_panel_power(struct intel_dp *intel_dp)
642
{
643
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
644 645
	struct drm_i915_private *dev_priv = dev->dev_private;

V
Ville Syrjälä 已提交
646 647
	lockdep_assert_held(&dev_priv->pps_mutex);

648 649 650 651
	if (IS_VALLEYVIEW(dev) &&
	    intel_dp->pps_pipe == INVALID_PIPE)
		return false;

652
	return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
653 654
}

655
static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
656
{
657
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
658 659
	struct drm_i915_private *dev_priv = dev->dev_private;

V
Ville Syrjälä 已提交
660 661
	lockdep_assert_held(&dev_priv->pps_mutex);

662 663 664 665
	if (IS_VALLEYVIEW(dev) &&
	    intel_dp->pps_pipe == INVALID_PIPE)
		return false;

666
	return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
667 668
}

669 670 671
static void
intel_dp_check_edp(struct intel_dp *intel_dp)
{
672
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
673
	struct drm_i915_private *dev_priv = dev->dev_private;
674

675 676
	if (!is_edp(intel_dp))
		return;
677

678
	if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
679 680
		WARN(1, "eDP powered off while attempting aux channel communication.\n");
		DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
681 682
			      I915_READ(_pp_stat_reg(intel_dp)),
			      I915_READ(_pp_ctrl_reg(intel_dp)));
683 684 685
	}
}

686 687 688 689 690 691
static uint32_t
intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
692
	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
693 694 695
	uint32_t status;
	bool done;

696
#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
697
	if (has_aux_irq)
698
		done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
699
					  msecs_to_jiffies_timeout(10));
700 701 702 703 704 705 706 707 708 709
	else
		done = wait_for_atomic(C, 10) == 0;
	if (!done)
		DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
			  has_aux_irq);
#undef C

	return status;
}

710
static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
711
{
712 713
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
714

715 716 717
	/*
	 * The clock divider is based off the hrawclk, and would like to run at
	 * 2MHz.  So, take the hrawclk value and divide by 2 and use that
718
	 */
719 720 721 722 723 724 725
	return index ? 0 : intel_hrawclk(dev) / 2;
}

static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
726
	struct drm_i915_private *dev_priv = dev->dev_private;
727 728 729 730 731

	if (index)
		return 0;

	if (intel_dig_port->port == PORT_A) {
732 733
		return DIV_ROUND_UP(dev_priv->cdclk_freq, 2000);

734 735 736 737 738 739 740 741 742 743 744 745 746 747
	} else {
		return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
	}
}

static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (intel_dig_port->port == PORT_A) {
		if (index)
			return 0;
748
		return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
749 750
	} else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
		/* Workaround for non-ULT HSW */
751 752 753 754 755
		switch (index) {
		case 0: return 63;
		case 1: return 72;
		default: return 0;
		}
756
	} else  {
757
		return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
758
	}
759 760
}

761 762 763 764 765
static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
	return index ? 0 : 100;
}

766 767 768 769 770 771 772 773 774 775
static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
	/*
	 * SKL doesn't need us to program the AUX clock divider (Hardware will
	 * derive the clock from CDCLK automatically). We still implement the
	 * get_aux_clock_divider vfunc to plug-in into the existing code.
	 */
	return index ? 0 : 1;
}

776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795
static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
				      bool has_aux_irq,
				      int send_bytes,
				      uint32_t aux_clock_divider)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	uint32_t precharge, timeout;

	if (IS_GEN6(dev))
		precharge = 3;
	else
		precharge = 5;

	if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
		timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
	else
		timeout = DP_AUX_CH_CTL_TIME_OUT_400us;

	return DP_AUX_CH_CTL_SEND_BUSY |
796
	       DP_AUX_CH_CTL_DONE |
797
	       (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
798
	       DP_AUX_CH_CTL_TIME_OUT_ERROR |
799
	       timeout |
800
	       DP_AUX_CH_CTL_RECEIVE_ERROR |
801 802
	       (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
	       (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
803
	       (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
804 805
}

806 807 808 809 810 811 812 813 814 815 816 817 818 819 820
static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
				      bool has_aux_irq,
				      int send_bytes,
				      uint32_t unused)
{
	return DP_AUX_CH_CTL_SEND_BUSY |
	       DP_AUX_CH_CTL_DONE |
	       (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
	       DP_AUX_CH_CTL_TIME_OUT_ERROR |
	       DP_AUX_CH_CTL_TIME_OUT_1600us |
	       DP_AUX_CH_CTL_RECEIVE_ERROR |
	       (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
	       DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
}

821 822
static int
intel_dp_aux_ch(struct intel_dp *intel_dp,
823
		const uint8_t *send, int send_bytes,
824 825 826 827 828 829 830
		uint8_t *recv, int recv_size)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
	uint32_t ch_data = ch_ctl + 4;
831
	uint32_t aux_clock_divider;
832 833
	int i, ret, recv_bytes;
	uint32_t status;
834
	int try, clock = 0;
835
	bool has_aux_irq = HAS_AUX_IRQ(dev);
836 837
	bool vdd;

838
	pps_lock(intel_dp);
V
Ville Syrjälä 已提交
839

840 841 842 843 844 845
	/*
	 * We will be called with VDD already enabled for dpcd/edid/oui reads.
	 * In such cases we want to leave VDD enabled and it's up to upper layers
	 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
	 * ourselves.
	 */
846
	vdd = edp_panel_vdd_on(intel_dp);
847 848 849 850 851 852 853 854

	/* dp aux is extremely sensitive to irq latency, hence request the
	 * lowest possible wakeup latency and so prevent the cpu from going into
	 * deep sleep states.
	 */
	pm_qos_update_request(&dev_priv->pm_qos, 0);

	intel_dp_check_edp(intel_dp);
855

856 857
	intel_aux_display_runtime_get(dev_priv);

858 859
	/* Try to wait for any previous AUX channel activity */
	for (try = 0; try < 3; try++) {
860
		status = I915_READ_NOTRACE(ch_ctl);
861 862 863 864 865 866
		if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
			break;
		msleep(1);
	}

	if (try == 3) {
867 868 869 870 871 872 873 874 875
		static u32 last_status = -1;
		const u32 status = I915_READ(ch_ctl);

		if (status != last_status) {
			WARN(1, "dp_aux_ch not started status 0x%08x\n",
			     status);
			last_status = status;
		}

876 877
		ret = -EBUSY;
		goto out;
878 879
	}

880 881 882 883 884 885
	/* Only 5 data registers! */
	if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
		ret = -E2BIG;
		goto out;
	}

886
	while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
887 888 889 890
		u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
							  has_aux_irq,
							  send_bytes,
							  aux_clock_divider);
891

892 893 894 895 896
		/* Must try at least 3 times according to DP spec */
		for (try = 0; try < 5; try++) {
			/* Load the send data into the aux channel data registers */
			for (i = 0; i < send_bytes; i += 4)
				I915_WRITE(ch_data + i,
897 898
					   intel_dp_pack_aux(send + i,
							     send_bytes - i));
899 900

			/* Send the command and wait for it to complete */
901
			I915_WRITE(ch_ctl, send_ctl);
902 903 904 905 906 907 908 909 910 911

			status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);

			/* Clear done status and any errors */
			I915_WRITE(ch_ctl,
				   status |
				   DP_AUX_CH_CTL_DONE |
				   DP_AUX_CH_CTL_TIME_OUT_ERROR |
				   DP_AUX_CH_CTL_RECEIVE_ERROR);

912
			if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
913
				continue;
914 915 916 917 918 919 920 921

			/* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
			 *   400us delay required for errors and timeouts
			 *   Timeout errors from the HW already meet this
			 *   requirement so skip to next iteration
			 */
			if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
				usleep_range(400, 500);
922
				continue;
923
			}
924
			if (status & DP_AUX_CH_CTL_DONE)
925
				goto done;
926
		}
927 928 929
	}

	if ((status & DP_AUX_CH_CTL_DONE) == 0) {
930
		DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
931 932
		ret = -EBUSY;
		goto out;
933 934
	}

935
done:
936 937 938
	/* Check for timeout or receive error.
	 * Timeouts occur when the sink is not connected
	 */
939
	if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
940
		DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
941 942
		ret = -EIO;
		goto out;
943
	}
944 945 946

	/* Timeouts occur when the device isn't connected, so they're
	 * "normal" -- don't fill the kernel log with these */
947
	if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
948
		DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
949 950
		ret = -ETIMEDOUT;
		goto out;
951 952 953 954 955 956 957
	}

	/* Unload any bytes sent back from the other side */
	recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
		      DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
	if (recv_bytes > recv_size)
		recv_bytes = recv_size;
958

959
	for (i = 0; i < recv_bytes; i += 4)
960 961
		intel_dp_unpack_aux(I915_READ(ch_data + i),
				    recv + i, recv_bytes - i);
962

963 964 965
	ret = recv_bytes;
out:
	pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
966
	intel_aux_display_runtime_put(dev_priv);
967

968 969 970
	if (vdd)
		edp_panel_vdd_off(intel_dp, false);

971
	pps_unlock(intel_dp);
V
Ville Syrjälä 已提交
972

973
	return ret;
974 975
}

976 977
#define BARE_ADDRESS_SIZE	3
#define HEADER_SIZE		(BARE_ADDRESS_SIZE + 1)
978 979
static ssize_t
intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
980
{
981 982 983
	struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
	uint8_t txbuf[20], rxbuf[20];
	size_t txsize, rxsize;
984 985
	int ret;

986 987 988
	txbuf[0] = (msg->request << 4) |
		((msg->address >> 16) & 0xf);
	txbuf[1] = (msg->address >> 8) & 0xff;
989 990
	txbuf[2] = msg->address & 0xff;
	txbuf[3] = msg->size - 1;
991

992 993 994
	switch (msg->request & ~DP_AUX_I2C_MOT) {
	case DP_AUX_NATIVE_WRITE:
	case DP_AUX_I2C_WRITE:
995
		txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
996
		rxsize = 2; /* 0 or 1 data bytes */
997

998 999
		if (WARN_ON(txsize > 20))
			return -E2BIG;
1000

1001
		memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1002

1003 1004 1005
		ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
		if (ret > 0) {
			msg->reply = rxbuf[0] >> 4;
1006

1007 1008 1009 1010 1011 1012 1013
			if (ret > 1) {
				/* Number of bytes written in a short write. */
				ret = clamp_t(int, rxbuf[1], 0, msg->size);
			} else {
				/* Return payload size. */
				ret = msg->size;
			}
1014 1015
		}
		break;
1016

1017 1018
	case DP_AUX_NATIVE_READ:
	case DP_AUX_I2C_READ:
1019
		txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1020
		rxsize = msg->size + 1;
1021

1022 1023
		if (WARN_ON(rxsize > 20))
			return -E2BIG;
1024

1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035
		ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
		if (ret > 0) {
			msg->reply = rxbuf[0] >> 4;
			/*
			 * Assume happy day, and copy the data. The caller is
			 * expected to check msg->reply before touching it.
			 *
			 * Return payload size.
			 */
			ret--;
			memcpy(msg->buffer, rxbuf + 1, ret);
1036
		}
1037 1038 1039 1040 1041
		break;

	default:
		ret = -EINVAL;
		break;
1042
	}
1043

1044
	return ret;
1045 1046
}

1047 1048 1049 1050
static void
intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1051
	struct drm_i915_private *dev_priv = dev->dev_private;
1052 1053
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	enum port port = intel_dig_port->port;
1054
	struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port];
1055
	const char *name = NULL;
1056
	uint32_t porte_aux_ctl_reg = DPA_AUX_CH_CTL;
1057 1058
	int ret;

1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078
	/* On SKL we don't have Aux for port E so we rely on VBT to set
	 * a proper alternate aux channel.
	 */
	if (IS_SKYLAKE(dev) && port == PORT_E) {
		switch (info->alternate_aux_channel) {
		case DP_AUX_B:
			porte_aux_ctl_reg = DPB_AUX_CH_CTL;
			break;
		case DP_AUX_C:
			porte_aux_ctl_reg = DPC_AUX_CH_CTL;
			break;
		case DP_AUX_D:
			porte_aux_ctl_reg = DPD_AUX_CH_CTL;
			break;
		case DP_AUX_A:
		default:
			porte_aux_ctl_reg = DPA_AUX_CH_CTL;
		}
	}

1079 1080 1081
	switch (port) {
	case PORT_A:
		intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
1082
		name = "DPDDC-A";
1083
		break;
1084 1085
	case PORT_B:
		intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
1086
		name = "DPDDC-B";
1087
		break;
1088 1089
	case PORT_C:
		intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
1090
		name = "DPDDC-C";
1091
		break;
1092 1093
	case PORT_D:
		intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
1094
		name = "DPDDC-D";
1095
		break;
1096 1097 1098 1099
	case PORT_E:
		intel_dp->aux_ch_ctl_reg = porte_aux_ctl_reg;
		name = "DPDDC-E";
		break;
1100 1101
	default:
		BUG();
1102 1103
	}

1104 1105 1106 1107 1108 1109 1110 1111 1112
	/*
	 * The AUX_CTL register is usually DP_CTL + 0x10.
	 *
	 * On Haswell and Broadwell though:
	 *   - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
	 *   - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
	 *
	 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
	 */
1113
	if (!IS_HASWELL(dev) && !IS_BROADWELL(dev) && port != PORT_E)
1114
		intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
1115

1116
	intel_dp->aux.name = name;
1117 1118
	intel_dp->aux.dev = dev->dev;
	intel_dp->aux.transfer = intel_dp_aux_transfer;
1119

1120 1121
	DRM_DEBUG_KMS("registering %s bus for %s\n", name,
		      connector->base.kdev->kobj.name);
1122

1123
	ret = drm_dp_aux_register(&intel_dp->aux);
1124
	if (ret < 0) {
1125
		DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1126 1127
			  name, ret);
		return;
1128
	}
1129

1130 1131 1132 1133 1134
	ret = sysfs_create_link(&connector->base.kdev->kobj,
				&intel_dp->aux.ddc.dev.kobj,
				intel_dp->aux.ddc.dev.kobj.name);
	if (ret < 0) {
		DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
1135
		drm_dp_aux_unregister(&intel_dp->aux);
1136
	}
1137 1138
}

1139 1140 1141 1142 1143
static void
intel_dp_connector_unregister(struct intel_connector *intel_connector)
{
	struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);

1144 1145 1146
	if (!intel_connector->mst_port)
		sysfs_remove_link(&intel_connector->base.kdev->kobj,
				  intel_dp->aux.ddc.dev.kobj.name);
1147 1148 1149
	intel_connector_unregister(intel_connector);
}

1150
static void
1151
skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
1152 1153 1154
{
	u32 ctrl1;

1155 1156 1157
	memset(&pipe_config->dpll_hw_state, 0,
	       sizeof(pipe_config->dpll_hw_state));

1158 1159 1160 1161 1162
	pipe_config->ddi_pll_sel = SKL_DPLL0;
	pipe_config->dpll_hw_state.cfgcr1 = 0;
	pipe_config->dpll_hw_state.cfgcr2 = 0;

	ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
1163
	switch (pipe_config->port_clock / 2) {
1164
	case 81000:
1165
		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
1166 1167
					      SKL_DPLL0);
		break;
1168
	case 135000:
1169
		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350,
1170 1171
					      SKL_DPLL0);
		break;
1172
	case 270000:
1173
		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700,
1174 1175
					      SKL_DPLL0);
		break;
1176
	case 162000:
1177
		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620,
1178 1179 1180 1181 1182 1183
					      SKL_DPLL0);
		break;
	/* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
	results in CDCLK change. Need to handle the change of CDCLK by
	disabling pipes and re-enabling them */
	case 108000:
1184
		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
1185 1186 1187
					      SKL_DPLL0);
		break;
	case 216000:
1188
		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
1189 1190 1191
					      SKL_DPLL0);
		break;

1192 1193 1194 1195
	}
	pipe_config->dpll_hw_state.ctrl1 = ctrl1;
}

1196
static void
1197
hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config)
1198
{
1199 1200 1201
	memset(&pipe_config->dpll_hw_state, 0,
	       sizeof(pipe_config->dpll_hw_state));

1202 1203
	switch (pipe_config->port_clock / 2) {
	case 81000:
1204 1205
		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
		break;
1206
	case 135000:
1207 1208
		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
		break;
1209
	case 270000:
1210 1211 1212 1213 1214
		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
		break;
	}
}

1215
static int
1216
intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
1217
{
1218 1219 1220
	if (intel_dp->num_sink_rates) {
		*sink_rates = intel_dp->sink_rates;
		return intel_dp->num_sink_rates;
1221
	}
1222 1223 1224 1225

	*sink_rates = default_rates;

	return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
1226 1227
}

1228
static int
1229
intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
1230
{
1231 1232 1233 1234
	if (IS_BROXTON(dev)) {
		*source_rates = bxt_rates;
		return ARRAY_SIZE(bxt_rates);
	} else if (IS_SKYLAKE(dev)) {
1235 1236
		*source_rates = skl_rates;
		return ARRAY_SIZE(skl_rates);
1237 1238 1239
	} else if (IS_CHERRYVIEW(dev)) {
		*source_rates = chv_rates;
		return ARRAY_SIZE(chv_rates);
1240
	}
1241 1242 1243

	*source_rates = default_rates;

1244 1245 1246 1247 1248 1249 1250 1251
	if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
		/* WaDisableHBR2:skl */
		return (DP_LINK_BW_2_7 >> 3) + 1;
	else if (INTEL_INFO(dev)->gen >= 8 ||
	    (IS_HASWELL(dev) && !IS_HSW_ULX(dev)))
		return (DP_LINK_BW_5_4 >> 3) + 1;
	else
		return (DP_LINK_BW_2_7 >> 3) + 1;
1252 1253
}

1254 1255
static void
intel_dp_set_clock(struct intel_encoder *encoder,
1256
		   struct intel_crtc_state *pipe_config)
1257 1258
{
	struct drm_device *dev = encoder->base.dev;
1259 1260
	const struct dp_link_dpll *divisor = NULL;
	int i, count = 0;
1261 1262

	if (IS_G4X(dev)) {
1263 1264
		divisor = gen4_dpll;
		count = ARRAY_SIZE(gen4_dpll);
1265
	} else if (HAS_PCH_SPLIT(dev)) {
1266 1267
		divisor = pch_dpll;
		count = ARRAY_SIZE(pch_dpll);
1268 1269 1270
	} else if (IS_CHERRYVIEW(dev)) {
		divisor = chv_dpll;
		count = ARRAY_SIZE(chv_dpll);
1271
	} else if (IS_VALLEYVIEW(dev)) {
1272 1273
		divisor = vlv_dpll;
		count = ARRAY_SIZE(vlv_dpll);
1274
	}
1275 1276 1277

	if (divisor && count) {
		for (i = 0; i < count; i++) {
1278
			if (pipe_config->port_clock == divisor[i].clock) {
1279 1280 1281 1282 1283
				pipe_config->dpll = divisor[i].dpll;
				pipe_config->clock_set = true;
				break;
			}
		}
1284 1285 1286
	}
}

1287 1288
static int intersect_rates(const int *source_rates, int source_len,
			   const int *sink_rates, int sink_len,
1289
			   int *common_rates)
1290 1291 1292 1293 1294
{
	int i = 0, j = 0, k = 0;

	while (i < source_len && j < sink_len) {
		if (source_rates[i] == sink_rates[j]) {
1295 1296
			if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
				return k;
1297
			common_rates[k] = source_rates[i];
1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309
			++k;
			++i;
			++j;
		} else if (source_rates[i] < sink_rates[j]) {
			++i;
		} else {
			++j;
		}
	}
	return k;
}

1310 1311
static int intel_dp_common_rates(struct intel_dp *intel_dp,
				 int *common_rates)
1312 1313 1314 1315 1316 1317 1318 1319 1320 1321
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	const int *source_rates, *sink_rates;
	int source_len, sink_len;

	sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
	source_len = intel_dp_source_rates(dev, &source_rates);

	return intersect_rates(source_rates, source_len,
			       sink_rates, sink_len,
1322
			       common_rates);
1323 1324
}

1325 1326 1327 1328 1329 1330 1331 1332
static void snprintf_int_array(char *str, size_t len,
			       const int *array, int nelem)
{
	int i;

	str[0] = '\0';

	for (i = 0; i < nelem; i++) {
1333
		int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344
		if (r >= len)
			return;
		str += r;
		len -= r;
	}
}

static void intel_dp_print_rates(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	const int *source_rates, *sink_rates;
1345 1346
	int source_len, sink_len, common_len;
	int common_rates[DP_MAX_SUPPORTED_RATES];
1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359
	char str[128]; /* FIXME: too big for stack? */

	if ((drm_debug & DRM_UT_KMS) == 0)
		return;

	source_len = intel_dp_source_rates(dev, &source_rates);
	snprintf_int_array(str, sizeof(str), source_rates, source_len);
	DRM_DEBUG_KMS("source rates: %s\n", str);

	sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
	snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
	DRM_DEBUG_KMS("sink rates: %s\n", str);

1360 1361 1362
	common_len = intel_dp_common_rates(intel_dp, common_rates);
	snprintf_int_array(str, sizeof(str), common_rates, common_len);
	DRM_DEBUG_KMS("common rates: %s\n", str);
1363 1364
}

1365
static int rate_to_index(int find, const int *rates)
1366 1367 1368 1369 1370 1371 1372 1373 1374 1375
{
	int i = 0;

	for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
		if (find == rates[i])
			break;

	return i;
}

1376 1377 1378 1379 1380 1381
int
intel_dp_max_link_rate(struct intel_dp *intel_dp)
{
	int rates[DP_MAX_SUPPORTED_RATES] = {};
	int len;

1382
	len = intel_dp_common_rates(intel_dp, rates);
1383 1384 1385 1386 1387 1388
	if (WARN_ON(len <= 0))
		return 162000;

	return rates[rate_to_index(0, rates) - 1];
}

1389 1390
int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
{
1391
	return rate_to_index(rate, intel_dp->sink_rates);
1392 1393
}

1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406
static void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
				  uint8_t *link_bw, uint8_t *rate_select)
{
	if (intel_dp->num_sink_rates) {
		*link_bw = 0;
		*rate_select =
			intel_dp_rate_select(intel_dp, port_clock);
	} else {
		*link_bw = drm_dp_link_rate_to_bw_code(port_clock);
		*rate_select = 0;
	}
}

P
Paulo Zanoni 已提交
1407
bool
1408
intel_dp_compute_config(struct intel_encoder *encoder,
1409
			struct intel_crtc_state *pipe_config)
1410
{
1411
	struct drm_device *dev = encoder->base.dev;
1412
	struct drm_i915_private *dev_priv = dev->dev_private;
1413
	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1414
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1415
	enum port port = dp_to_dig_port(intel_dp)->port;
1416
	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1417
	struct intel_connector *intel_connector = intel_dp->attached_connector;
1418
	int lane_count, clock;
1419
	int min_lane_count = 1;
1420
	int max_lane_count = intel_dp_max_lane_count(intel_dp);
1421
	/* Conveniently, the link BW constants become indices with a shift...*/
1422
	int min_clock = 0;
1423
	int max_clock;
1424
	int bpp, mode_rate;
1425
	int link_avail, link_clock;
1426 1427
	int common_rates[DP_MAX_SUPPORTED_RATES] = {};
	int common_len;
1428
	uint8_t link_bw, rate_select;
1429

1430
	common_len = intel_dp_common_rates(intel_dp, common_rates);
1431 1432

	/* No common link rates between source and sink */
1433
	WARN_ON(common_len <= 0);
1434

1435
	max_clock = common_len - 1;
1436

1437
	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
1438 1439
		pipe_config->has_pch_encoder = true;

1440
	pipe_config->has_dp_encoder = true;
1441
	pipe_config->has_drrs = false;
1442
	pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
1443

1444 1445 1446
	if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
		intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
				       adjusted_mode);
1447 1448 1449

		if (INTEL_INFO(dev)->gen >= 9) {
			int ret;
1450
			ret = skl_update_scaler_crtc(pipe_config);
1451 1452 1453 1454
			if (ret)
				return ret;
		}

1455 1456 1457 1458
		if (!HAS_PCH_SPLIT(dev))
			intel_gmch_panel_fitting(intel_crtc, pipe_config,
						 intel_connector->panel.fitting_mode);
		else
1459 1460
			intel_pch_panel_fitting(intel_crtc, pipe_config,
						intel_connector->panel.fitting_mode);
1461 1462
	}

1463
	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1464 1465
		return false;

1466
	DRM_DEBUG_KMS("DP link computation with max lane count %i "
1467
		      "max bw %d pixel clock %iKHz\n",
1468
		      max_lane_count, common_rates[max_clock],
1469
		      adjusted_mode->crtc_clock);
1470

1471 1472
	/* Walk through all bpp values. Luckily they're all nicely spaced with 2
	 * bpc in between. */
1473
	bpp = pipe_config->pipe_bpp;
1474
	if (is_edp(intel_dp)) {
1475 1476 1477 1478

		/* Get bpp from vbt only for panels that dont have bpp in edid */
		if (intel_connector->base.display_info.bpc == 0 &&
			(dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp)) {
1479 1480 1481 1482 1483
			DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
				      dev_priv->vbt.edp_bpp);
			bpp = dev_priv->vbt.edp_bpp;
		}

1484 1485 1486 1487 1488 1489 1490 1491 1492
		/*
		 * Use the maximum clock and number of lanes the eDP panel
		 * advertizes being capable of. The panels are generally
		 * designed to support only a single clock and lane
		 * configuration, and typically these values correspond to the
		 * native resolution of the panel.
		 */
		min_lane_count = max_lane_count;
		min_clock = max_clock;
1493
	}
1494

1495
	for (; bpp >= 6*3; bpp -= 2*3) {
1496 1497
		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
						   bpp);
1498

1499
		for (clock = min_clock; clock <= max_clock; clock++) {
1500 1501 1502 1503
			for (lane_count = min_lane_count;
				lane_count <= max_lane_count;
				lane_count <<= 1) {

1504
				link_clock = common_rates[clock];
1505 1506 1507 1508 1509 1510 1511 1512 1513
				link_avail = intel_dp_max_data_rate(link_clock,
								    lane_count);

				if (mode_rate <= link_avail) {
					goto found;
				}
			}
		}
	}
1514

1515
	return false;
1516

1517
found:
1518 1519 1520 1521 1522 1523
	if (intel_dp->color_range_auto) {
		/*
		 * See:
		 * CEA-861-E - 5.1 Default Encoding Parameters
		 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
		 */
1524 1525 1526 1527 1528
		pipe_config->limited_color_range =
			bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
	} else {
		pipe_config->limited_color_range =
			intel_dp->limited_color_range;
1529 1530
	}

1531
	pipe_config->lane_count = lane_count;
1532

1533
	pipe_config->pipe_bpp = bpp;
1534
	pipe_config->port_clock = common_rates[clock];
1535

1536 1537 1538 1539 1540
	intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
			      &link_bw, &rate_select);

	DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
		      link_bw, rate_select, pipe_config->lane_count,
1541
		      pipe_config->port_clock, bpp);
1542 1543
	DRM_DEBUG_KMS("DP link bw required %i available %i\n",
		      mode_rate, link_avail);
1544

1545
	intel_link_compute_m_n(bpp, lane_count,
1546 1547
			       adjusted_mode->crtc_clock,
			       pipe_config->port_clock,
1548
			       &pipe_config->dp_m_n);
1549

1550
	if (intel_connector->panel.downclock_mode != NULL &&
1551
		dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1552
			pipe_config->has_drrs = true;
1553 1554 1555 1556 1557 1558
			intel_link_compute_m_n(bpp, lane_count,
				intel_connector->panel.downclock_mode->clock,
				pipe_config->port_clock,
				&pipe_config->dp_m2_n2);
	}

1559
	if (IS_SKYLAKE(dev) && is_edp(intel_dp))
1560
		skl_edp_set_pll_config(pipe_config);
1561 1562
	else if (IS_BROXTON(dev))
		/* handled in ddi */;
1563
	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1564
		hsw_dp_set_ddi_pll_sel(pipe_config);
1565
	else
1566
		intel_dp_set_clock(encoder, pipe_config);
1567

1568
	return true;
1569 1570
}

1571
static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
1572
{
1573 1574 1575
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
	struct drm_device *dev = crtc->base.dev;
1576 1577 1578
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

1579 1580
	DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
		      crtc->config->port_clock);
1581 1582 1583
	dpa_ctl = I915_READ(DP_A);
	dpa_ctl &= ~DP_PLL_FREQ_MASK;

1584
	if (crtc->config->port_clock == 162000) {
1585 1586 1587 1588
		/* For a long time we've carried around a ILK-DevA w/a for the
		 * 160MHz clock. If we're really unlucky, it's still required.
		 */
		DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1589
		dpa_ctl |= DP_PLL_FREQ_160MHZ;
1590
		intel_dp->DP |= DP_PLL_FREQ_160MHZ;
1591 1592
	} else {
		dpa_ctl |= DP_PLL_FREQ_270MHZ;
1593
		intel_dp->DP |= DP_PLL_FREQ_270MHZ;
1594
	}
1595

1596 1597 1598 1599 1600 1601
	I915_WRITE(DP_A, dpa_ctl);

	POSTING_READ(DP_A);
	udelay(500);
}

1602 1603 1604 1605 1606 1607 1608
void intel_dp_set_link_params(struct intel_dp *intel_dp,
			      const struct intel_crtc_state *pipe_config)
{
	intel_dp->link_rate = pipe_config->port_clock;
	intel_dp->lane_count = pipe_config->lane_count;
}

1609
static void intel_dp_prepare(struct intel_encoder *encoder)
1610
{
1611
	struct drm_device *dev = encoder->base.dev;
1612
	struct drm_i915_private *dev_priv = dev->dev_private;
1613
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1614
	enum port port = dp_to_dig_port(intel_dp)->port;
1615
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1616
	struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
1617

1618 1619
	intel_dp_set_link_params(intel_dp, crtc->config);

1620
	/*
K
Keith Packard 已提交
1621
	 * There are four kinds of DP registers:
1622 1623
	 *
	 * 	IBX PCH
K
Keith Packard 已提交
1624 1625
	 * 	SNB CPU
	 *	IVB CPU
1626 1627 1628 1629 1630 1631 1632 1633 1634 1635
	 * 	CPT PCH
	 *
	 * IBX PCH and CPU are the same for almost everything,
	 * except that the CPU DP PLL is configured in this
	 * register
	 *
	 * CPT PCH is quite different, having many bits moved
	 * to the TRANS_DP_CTL register instead. That
	 * configuration happens (oddly) in ironlake_pch_enable
	 */
1636

1637 1638 1639 1640
	/* Preserve the BIOS-computed detected bit. This is
	 * supposed to be read-only.
	 */
	intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1641

1642 1643
	/* Handle DP bits in common between all three register formats */
	intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1644
	intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count);
1645

1646
	if (crtc->config->has_audio)
C
Chris Wilson 已提交
1647
		intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1648

1649
	/* Split out the IBX/CPU vs CPT settings */
1650

1651
	if (IS_GEN7(dev) && port == PORT_A) {
K
Keith Packard 已提交
1652 1653 1654 1655 1656 1657
		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
			intel_dp->DP |= DP_SYNC_HS_HIGH;
		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
			intel_dp->DP |= DP_SYNC_VS_HIGH;
		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;

1658
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
K
Keith Packard 已提交
1659 1660
			intel_dp->DP |= DP_ENHANCED_FRAMING;

1661
		intel_dp->DP |= crtc->pipe << 29;
1662
	} else if (HAS_PCH_CPT(dev) && port != PORT_A) {
1663 1664
		u32 trans_dp;

1665
		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1666 1667 1668 1669 1670 1671 1672

		trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
			trans_dp |= TRANS_DP_ENH_FRAMING;
		else
			trans_dp &= ~TRANS_DP_ENH_FRAMING;
		I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1673
	} else {
1674 1675 1676
		if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
		    crtc->config->limited_color_range)
			intel_dp->DP |= DP_COLOR_RANGE_16_235;
1677 1678 1679 1680 1681 1682 1683

		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
			intel_dp->DP |= DP_SYNC_HS_HIGH;
		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
			intel_dp->DP |= DP_SYNC_VS_HIGH;
		intel_dp->DP |= DP_LINK_TRAIN_OFF;

1684
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1685 1686
			intel_dp->DP |= DP_ENHANCED_FRAMING;

1687
		if (IS_CHERRYVIEW(dev))
1688
			intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1689 1690
		else if (crtc->pipe == PIPE_B)
			intel_dp->DP |= DP_PIPEB_SELECT;
1691
	}
1692 1693
}

1694 1695
#define IDLE_ON_MASK		(PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
#define IDLE_ON_VALUE   	(PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1696

1697 1698
#define IDLE_OFF_MASK		(PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
#define IDLE_OFF_VALUE		(0     | PP_SEQUENCE_NONE | 0                     | 0)
1699

1700 1701
#define IDLE_CYCLE_MASK		(PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
#define IDLE_CYCLE_VALUE	(0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1702

1703
static void wait_panel_status(struct intel_dp *intel_dp,
1704 1705
				       u32 mask,
				       u32 value)
1706
{
1707
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1708
	struct drm_i915_private *dev_priv = dev->dev_private;
1709 1710
	u32 pp_stat_reg, pp_ctrl_reg;

V
Ville Syrjälä 已提交
1711 1712
	lockdep_assert_held(&dev_priv->pps_mutex);

1713 1714
	pp_stat_reg = _pp_stat_reg(intel_dp);
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1715

1716
	DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1717 1718 1719
			mask, value,
			I915_READ(pp_stat_reg),
			I915_READ(pp_ctrl_reg));
1720

1721
	if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1722
		DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1723 1724
				I915_READ(pp_stat_reg),
				I915_READ(pp_ctrl_reg));
1725
	}
1726 1727

	DRM_DEBUG_KMS("Wait complete\n");
1728
}
1729

1730
static void wait_panel_on(struct intel_dp *intel_dp)
1731 1732
{
	DRM_DEBUG_KMS("Wait for panel power on\n");
1733
	wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1734 1735
}

1736
static void wait_panel_off(struct intel_dp *intel_dp)
1737 1738
{
	DRM_DEBUG_KMS("Wait for panel power off time\n");
1739
	wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1740 1741
}

1742
static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1743 1744
{
	DRM_DEBUG_KMS("Wait for panel power cycle\n");
1745 1746 1747 1748 1749 1750

	/* When we disable the VDD override bit last we have to do the manual
	 * wait. */
	wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
				       intel_dp->panel_power_cycle_delay);

1751
	wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1752 1753
}

1754
static void wait_backlight_on(struct intel_dp *intel_dp)
1755 1756 1757 1758 1759
{
	wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
				       intel_dp->backlight_on_delay);
}

1760
static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1761 1762 1763 1764
{
	wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
				       intel_dp->backlight_off_delay);
}
1765

1766 1767 1768 1769
/* Read the current pp_control value, unlocking the register if it
 * is locked
 */

1770
static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1771
{
1772 1773 1774
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 control;
1775

V
Ville Syrjälä 已提交
1776 1777
	lockdep_assert_held(&dev_priv->pps_mutex);

1778
	control = I915_READ(_pp_ctrl_reg(intel_dp));
1779 1780 1781 1782
	if (!IS_BROXTON(dev)) {
		control &= ~PANEL_UNLOCK_MASK;
		control |= PANEL_UNLOCK_REGS;
	}
1783
	return control;
1784 1785
}

1786 1787 1788 1789 1790
/*
 * Must be paired with edp_panel_vdd_off().
 * Must hold pps_mutex around the whole on/off sequence.
 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
 */
1791
static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1792
{
1793
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1794 1795
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
1796
	struct drm_i915_private *dev_priv = dev->dev_private;
1797
	enum intel_display_power_domain power_domain;
1798
	u32 pp;
1799
	u32 pp_stat_reg, pp_ctrl_reg;
1800
	bool need_to_disable = !intel_dp->want_panel_vdd;
1801

V
Ville Syrjälä 已提交
1802 1803
	lockdep_assert_held(&dev_priv->pps_mutex);

1804
	if (!is_edp(intel_dp))
1805
		return false;
1806

1807
	cancel_delayed_work(&intel_dp->panel_vdd_work);
1808
	intel_dp->want_panel_vdd = true;
1809

1810
	if (edp_have_panel_vdd(intel_dp))
1811
		return need_to_disable;
1812

1813 1814
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_get(dev_priv, power_domain);
1815

V
Ville Syrjälä 已提交
1816 1817
	DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
		      port_name(intel_dig_port->port));
1818

1819 1820
	if (!edp_have_panel_power(intel_dp))
		wait_panel_power_cycle(intel_dp);
1821

1822
	pp = ironlake_get_pp_control(intel_dp);
1823
	pp |= EDP_FORCE_VDD;
1824

1825 1826
	pp_stat_reg = _pp_stat_reg(intel_dp);
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1827 1828 1829 1830 1831

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
	DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
			I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1832 1833 1834
	/*
	 * If the panel wasn't on, delay before accessing aux channel
	 */
1835
	if (!edp_have_panel_power(intel_dp)) {
V
Ville Syrjälä 已提交
1836 1837
		DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
			      port_name(intel_dig_port->port));
1838 1839
		msleep(intel_dp->panel_power_up_delay);
	}
1840 1841 1842 1843

	return need_to_disable;
}

1844 1845 1846 1847 1848 1849 1850
/*
 * Must be paired with intel_edp_panel_vdd_off() or
 * intel_edp_panel_off().
 * Nested calls to these functions are not allowed since
 * we drop the lock. Caller must use some higher level
 * locking to prevent nested calls from other threads.
 */
1851
void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1852
{
1853
	bool vdd;
1854

1855 1856 1857
	if (!is_edp(intel_dp))
		return;

1858
	pps_lock(intel_dp);
1859
	vdd = edp_panel_vdd_on(intel_dp);
1860
	pps_unlock(intel_dp);
1861

R
Rob Clark 已提交
1862
	I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
V
Ville Syrjälä 已提交
1863
	     port_name(dp_to_dig_port(intel_dp)->port));
1864 1865
}

1866
static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1867
{
1868
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1869
	struct drm_i915_private *dev_priv = dev->dev_private;
1870 1871 1872 1873
	struct intel_digital_port *intel_dig_port =
		dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	enum intel_display_power_domain power_domain;
1874
	u32 pp;
1875
	u32 pp_stat_reg, pp_ctrl_reg;
1876

V
Ville Syrjälä 已提交
1877
	lockdep_assert_held(&dev_priv->pps_mutex);
1878

1879
	WARN_ON(intel_dp->want_panel_vdd);
1880

1881
	if (!edp_have_panel_vdd(intel_dp))
1882
		return;
1883

V
Ville Syrjälä 已提交
1884 1885
	DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
		      port_name(intel_dig_port->port));
1886

1887 1888
	pp = ironlake_get_pp_control(intel_dp);
	pp &= ~EDP_FORCE_VDD;
1889

1890 1891
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
	pp_stat_reg = _pp_stat_reg(intel_dp);
1892

1893 1894
	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
P
Paulo Zanoni 已提交
1895

1896 1897 1898
	/* Make sure sequencer is idle before allowing subsequent activity */
	DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
	I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1899

1900 1901
	if ((pp & POWER_TARGET_ON) == 0)
		intel_dp->last_power_cycle = jiffies;
1902

1903 1904
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_put(dev_priv, power_domain);
1905
}
1906

1907
static void edp_panel_vdd_work(struct work_struct *__work)
1908 1909 1910 1911
{
	struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
						 struct intel_dp, panel_vdd_work);

1912
	pps_lock(intel_dp);
1913 1914
	if (!intel_dp->want_panel_vdd)
		edp_panel_vdd_off_sync(intel_dp);
1915
	pps_unlock(intel_dp);
1916 1917
}

1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930
static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
{
	unsigned long delay;

	/*
	 * Queue the timer to fire a long time from now (relative to the power
	 * down delay) to keep the panel power up across a sequence of
	 * operations.
	 */
	delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
	schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
}

1931 1932 1933 1934 1935
/*
 * Must be paired with edp_panel_vdd_on().
 * Must hold pps_mutex around the whole on/off sequence.
 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
 */
1936
static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1937
{
V
Ville Syrjälä 已提交
1938 1939 1940 1941 1942
	struct drm_i915_private *dev_priv =
		intel_dp_to_dev(intel_dp)->dev_private;

	lockdep_assert_held(&dev_priv->pps_mutex);

1943 1944
	if (!is_edp(intel_dp))
		return;
1945

R
Rob Clark 已提交
1946
	I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
V
Ville Syrjälä 已提交
1947
	     port_name(dp_to_dig_port(intel_dp)->port));
1948

1949 1950
	intel_dp->want_panel_vdd = false;

1951
	if (sync)
1952
		edp_panel_vdd_off_sync(intel_dp);
1953 1954
	else
		edp_panel_vdd_schedule_off(intel_dp);
1955 1956
}

1957
static void edp_panel_on(struct intel_dp *intel_dp)
1958
{
1959
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1960
	struct drm_i915_private *dev_priv = dev->dev_private;
1961
	u32 pp;
1962
	u32 pp_ctrl_reg;
1963

1964 1965
	lockdep_assert_held(&dev_priv->pps_mutex);

1966
	if (!is_edp(intel_dp))
1967
		return;
1968

V
Ville Syrjälä 已提交
1969 1970
	DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
		      port_name(dp_to_dig_port(intel_dp)->port));
V
Ville Syrjälä 已提交
1971

1972 1973 1974
	if (WARN(edp_have_panel_power(intel_dp),
		 "eDP port %c panel power already on\n",
		 port_name(dp_to_dig_port(intel_dp)->port)))
1975
		return;
1976

1977
	wait_panel_power_cycle(intel_dp);
1978

1979
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1980
	pp = ironlake_get_pp_control(intel_dp);
1981 1982 1983
	if (IS_GEN5(dev)) {
		/* ILK workaround: disable reset around power sequence */
		pp &= ~PANEL_POWER_RESET;
1984 1985
		I915_WRITE(pp_ctrl_reg, pp);
		POSTING_READ(pp_ctrl_reg);
1986
	}
1987

1988
	pp |= POWER_TARGET_ON;
1989 1990 1991
	if (!IS_GEN5(dev))
		pp |= PANEL_POWER_RESET;

1992 1993
	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1994

1995
	wait_panel_on(intel_dp);
1996
	intel_dp->last_power_on = jiffies;
1997

1998 1999
	if (IS_GEN5(dev)) {
		pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2000 2001
		I915_WRITE(pp_ctrl_reg, pp);
		POSTING_READ(pp_ctrl_reg);
2002
	}
2003
}
V
Ville Syrjälä 已提交
2004

2005 2006 2007 2008 2009 2010 2011
void intel_edp_panel_on(struct intel_dp *intel_dp)
{
	if (!is_edp(intel_dp))
		return;

	pps_lock(intel_dp);
	edp_panel_on(intel_dp);
2012
	pps_unlock(intel_dp);
2013 2014
}

2015 2016

static void edp_panel_off(struct intel_dp *intel_dp)
2017
{
2018 2019
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
2020
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2021
	struct drm_i915_private *dev_priv = dev->dev_private;
2022
	enum intel_display_power_domain power_domain;
2023
	u32 pp;
2024
	u32 pp_ctrl_reg;
2025

2026 2027
	lockdep_assert_held(&dev_priv->pps_mutex);

2028 2029
	if (!is_edp(intel_dp))
		return;
2030

V
Ville Syrjälä 已提交
2031 2032
	DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
		      port_name(dp_to_dig_port(intel_dp)->port));
2033

V
Ville Syrjälä 已提交
2034 2035
	WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
	     port_name(dp_to_dig_port(intel_dp)->port));
2036

2037
	pp = ironlake_get_pp_control(intel_dp);
2038 2039
	/* We need to switch off panel power _and_ force vdd, for otherwise some
	 * panels get very unhappy and cease to work. */
2040 2041
	pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
		EDP_BLC_ENABLE);
2042

2043
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2044

2045 2046
	intel_dp->want_panel_vdd = false;

2047 2048
	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
2049

2050
	intel_dp->last_power_cycle = jiffies;
2051
	wait_panel_off(intel_dp);
2052 2053

	/* We got a reference when we enabled the VDD. */
2054 2055
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_put(dev_priv, power_domain);
2056
}
V
Ville Syrjälä 已提交
2057

2058 2059 2060 2061
void intel_edp_panel_off(struct intel_dp *intel_dp)
{
	if (!is_edp(intel_dp))
		return;
V
Ville Syrjälä 已提交
2062

2063 2064
	pps_lock(intel_dp);
	edp_panel_off(intel_dp);
2065
	pps_unlock(intel_dp);
2066 2067
}

2068 2069
/* Enable backlight in the panel power control. */
static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2070
{
2071 2072
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
2073 2074
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
2075
	u32 pp_ctrl_reg;
2076

2077 2078 2079 2080 2081 2082
	/*
	 * If we enable the backlight right away following a panel power
	 * on, we may see slight flicker as the panel syncs with the eDP
	 * link.  So delay a bit to make sure the image is solid before
	 * allowing it to appear.
	 */
2083
	wait_backlight_on(intel_dp);
V
Ville Syrjälä 已提交
2084

2085
	pps_lock(intel_dp);
V
Ville Syrjälä 已提交
2086

2087
	pp = ironlake_get_pp_control(intel_dp);
2088
	pp |= EDP_BLC_ENABLE;
2089

2090
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2091 2092 2093

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
V
Ville Syrjälä 已提交
2094

2095
	pps_unlock(intel_dp);
2096 2097
}

2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111
/* Enable backlight PWM and backlight PP control. */
void intel_edp_backlight_on(struct intel_dp *intel_dp)
{
	if (!is_edp(intel_dp))
		return;

	DRM_DEBUG_KMS("\n");

	intel_panel_enable_backlight(intel_dp->attached_connector);
	_intel_edp_backlight_on(intel_dp);
}

/* Disable backlight in the panel power control. */
static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2112
{
2113
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2114 2115
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
2116
	u32 pp_ctrl_reg;
2117

2118 2119 2120
	if (!is_edp(intel_dp))
		return;

2121
	pps_lock(intel_dp);
V
Ville Syrjälä 已提交
2122

2123
	pp = ironlake_get_pp_control(intel_dp);
2124
	pp &= ~EDP_BLC_ENABLE;
2125

2126
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2127 2128 2129

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
2130

2131
	pps_unlock(intel_dp);
V
Ville Syrjälä 已提交
2132 2133

	intel_dp->last_backlight_off = jiffies;
2134
	edp_wait_backlight_off(intel_dp);
2135
}
2136

2137 2138 2139 2140 2141 2142 2143
/* Disable backlight PP control and backlight PWM. */
void intel_edp_backlight_off(struct intel_dp *intel_dp)
{
	if (!is_edp(intel_dp))
		return;

	DRM_DEBUG_KMS("\n");
2144

2145
	_intel_edp_backlight_off(intel_dp);
2146
	intel_panel_disable_backlight(intel_dp->attached_connector);
2147
}
2148

2149 2150 2151 2152 2153 2154 2155 2156
/*
 * Hook for controlling the panel power control backlight through the bl_power
 * sysfs attribute. Take care to handle multiple calls.
 */
static void intel_edp_backlight_power(struct intel_connector *connector,
				      bool enable)
{
	struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
V
Ville Syrjälä 已提交
2157 2158
	bool is_enabled;

2159
	pps_lock(intel_dp);
V
Ville Syrjälä 已提交
2160
	is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2161
	pps_unlock(intel_dp);
2162 2163 2164 2165

	if (is_enabled == enable)
		return;

2166 2167
	DRM_DEBUG_KMS("panel power control backlight %s\n",
		      enable ? "enable" : "disable");
2168 2169 2170 2171 2172 2173 2174

	if (enable)
		_intel_edp_backlight_on(intel_dp);
	else
		_intel_edp_backlight_off(intel_dp);
}

2175
static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
2176
{
2177 2178 2179
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
	struct drm_device *dev = crtc->dev;
2180 2181 2182
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

2183 2184 2185
	assert_pipe_disabled(dev_priv,
			     to_intel_crtc(crtc)->pipe);

2186 2187
	DRM_DEBUG_KMS("\n");
	dpa_ctl = I915_READ(DP_A);
2188 2189 2190 2191 2192 2193 2194 2195 2196
	WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
	WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");

	/* We don't adjust intel_dp->DP while tearing down the link, to
	 * facilitate link retraining (e.g. after hotplug). Hence clear all
	 * enable bits here to ensure that we don't enable too much. */
	intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
	intel_dp->DP |= DP_PLL_ENABLE;
	I915_WRITE(DP_A, intel_dp->DP);
2197 2198
	POSTING_READ(DP_A);
	udelay(200);
2199 2200
}

2201
static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2202
{
2203 2204 2205
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
	struct drm_device *dev = crtc->dev;
2206 2207 2208
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

2209 2210 2211
	assert_pipe_disabled(dev_priv,
			     to_intel_crtc(crtc)->pipe);

2212
	dpa_ctl = I915_READ(DP_A);
2213 2214 2215 2216 2217 2218 2219
	WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
	     "dp pll off, should be on\n");
	WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");

	/* We can't rely on the value tracked for the DP register in
	 * intel_dp->DP because link_down must not change that (otherwise link
	 * re-training will fail. */
2220
	dpa_ctl &= ~DP_PLL_ENABLE;
2221
	I915_WRITE(DP_A, dpa_ctl);
2222
	POSTING_READ(DP_A);
2223 2224 2225
	udelay(200);
}

2226
/* If the sink supports it, try to set the power state appropriately */
2227
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2228 2229 2230 2231 2232 2233 2234 2235
{
	int ret, i;

	/* Should have a valid DPCD by this point */
	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
		return;

	if (mode != DRM_MODE_DPMS_ON) {
2236 2237
		ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
					 DP_SET_POWER_D3);
2238 2239 2240 2241 2242 2243
	} else {
		/*
		 * When turning on, we need to retry for 1ms to give the sink
		 * time to wake up.
		 */
		for (i = 0; i < 3; i++) {
2244 2245
			ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
						 DP_SET_POWER_D0);
2246 2247 2248 2249 2250
			if (ret == 1)
				break;
			msleep(1);
		}
	}
2251 2252 2253 2254

	if (ret != 1)
		DRM_DEBUG_KMS("failed to %s sink power state\n",
			      mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2255 2256
}

2257 2258
static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
				  enum pipe *pipe)
2259
{
2260
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2261
	enum port port = dp_to_dig_port(intel_dp)->port;
2262 2263
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2264 2265 2266 2267
	enum intel_display_power_domain power_domain;
	u32 tmp;

	power_domain = intel_display_port_power_domain(encoder);
2268
	if (!intel_display_power_is_enabled(dev_priv, power_domain))
2269 2270 2271
		return false;

	tmp = I915_READ(intel_dp->output_reg);
2272 2273 2274 2275

	if (!(tmp & DP_PORT_EN))
		return false;

2276
	if (IS_GEN7(dev) && port == PORT_A) {
2277
		*pipe = PORT_TO_PIPE_CPT(tmp);
2278
	} else if (HAS_PCH_CPT(dev) && port != PORT_A) {
2279
		enum pipe p;
2280

2281 2282 2283 2284
		for_each_pipe(dev_priv, p) {
			u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
			if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
				*pipe = p;
2285 2286 2287 2288
				return true;
			}
		}

2289 2290
		DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
			      intel_dp->output_reg);
2291 2292 2293 2294
	} else if (IS_CHERRYVIEW(dev)) {
		*pipe = DP_PORT_TO_PIPE_CHV(tmp);
	} else {
		*pipe = PORT_TO_PIPE(tmp);
2295
	}
2296

2297 2298
	return true;
}
2299

2300
static void intel_dp_get_config(struct intel_encoder *encoder,
2301
				struct intel_crtc_state *pipe_config)
2302 2303 2304
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	u32 tmp, flags = 0;
2305 2306 2307 2308
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = dp_to_dig_port(intel_dp)->port;
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2309
	int dotclock;
2310

2311
	tmp = I915_READ(intel_dp->output_reg);
2312 2313

	pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2314

2315
	if (HAS_PCH_CPT(dev) && port != PORT_A) {
2316 2317 2318
		u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));

		if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2319 2320 2321
			flags |= DRM_MODE_FLAG_PHSYNC;
		else
			flags |= DRM_MODE_FLAG_NHSYNC;
2322

2323
		if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2324 2325 2326 2327
			flags |= DRM_MODE_FLAG_PVSYNC;
		else
			flags |= DRM_MODE_FLAG_NVSYNC;
	} else {
2328
		if (tmp & DP_SYNC_HS_HIGH)
2329 2330 2331
			flags |= DRM_MODE_FLAG_PHSYNC;
		else
			flags |= DRM_MODE_FLAG_NHSYNC;
2332

2333
		if (tmp & DP_SYNC_VS_HIGH)
2334 2335 2336 2337
			flags |= DRM_MODE_FLAG_PVSYNC;
		else
			flags |= DRM_MODE_FLAG_NVSYNC;
	}
2338

2339
	pipe_config->base.adjusted_mode.flags |= flags;
2340

2341 2342 2343 2344
	if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
	    tmp & DP_COLOR_RANGE_16_235)
		pipe_config->limited_color_range = true;

2345 2346
	pipe_config->has_dp_encoder = true;

2347 2348 2349
	pipe_config->lane_count =
		((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;

2350 2351
	intel_dp_get_m_n(crtc, pipe_config);

2352
	if (port == PORT_A) {
2353 2354 2355 2356 2357
		if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
			pipe_config->port_clock = 162000;
		else
			pipe_config->port_clock = 270000;
	}
2358 2359 2360 2361 2362 2363 2364

	dotclock = intel_dotclock_calculate(pipe_config->port_clock,
					    &pipe_config->dp_m_n);

	if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
		ironlake_check_encoder_dotclock(pipe_config, dotclock);

2365
	pipe_config->base.adjusted_mode.crtc_clock = dotclock;
2366

2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385
	if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
	    pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
		/*
		 * This is a big fat ugly hack.
		 *
		 * Some machines in UEFI boot mode provide us a VBT that has 18
		 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
		 * unknown we fail to light up. Yet the same BIOS boots up with
		 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
		 * max, not what it tells us to use.
		 *
		 * Note: This will still be broken if the eDP panel is not lit
		 * up by the BIOS, and thus we can't get the mode at module
		 * load.
		 */
		DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
			      pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
		dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
	}
2386 2387
}

2388
static void intel_disable_dp(struct intel_encoder *encoder)
2389
{
2390
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2391
	struct drm_device *dev = encoder->base.dev;
2392 2393
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);

2394
	if (crtc->config->has_audio)
2395
		intel_audio_codec_disable(encoder);
2396

2397 2398 2399
	if (HAS_PSR(dev) && !HAS_DDI(dev))
		intel_psr_disable(intel_dp);

2400 2401
	/* Make sure the panel is off before trying to change the mode. But also
	 * ensure that we have vdd while we switch off the panel. */
2402
	intel_edp_panel_vdd_on(intel_dp);
2403
	intel_edp_backlight_off(intel_dp);
2404
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2405
	intel_edp_panel_off(intel_dp);
2406

2407 2408
	/* disable the port before the pipe on g4x */
	if (INTEL_INFO(dev)->gen < 5)
2409
		intel_dp_link_down(intel_dp);
2410 2411
}

2412
static void ilk_post_disable_dp(struct intel_encoder *encoder)
2413
{
2414
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2415
	enum port port = dp_to_dig_port(intel_dp)->port;
2416

2417
	intel_dp_link_down(intel_dp);
2418 2419
	if (port == PORT_A)
		ironlake_edp_pll_off(intel_dp);
2420 2421 2422 2423 2424 2425 2426
}

static void vlv_post_disable_dp(struct intel_encoder *encoder)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

	intel_dp_link_down(intel_dp);
2427 2428
}

2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442
static void chv_post_disable_dp(struct intel_encoder *encoder)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
	enum dpio_channel ch = vlv_dport_to_channel(dport);
	enum pipe pipe = intel_crtc->pipe;
	u32 val;

	intel_dp_link_down(intel_dp);

V
Ville Syrjälä 已提交
2443
	mutex_lock(&dev_priv->sb_lock);
2444 2445

	/* Propagate soft reset to data lane reset */
2446
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2447
	val |= CHV_PCS_REQ_SOFTRESET_EN;
2448
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2449

2450 2451 2452 2453 2454
	if (intel_crtc->config->lane_count > 2) {
		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
		val |= CHV_PCS_REQ_SOFTRESET_EN;
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
	}
2455 2456 2457 2458 2459

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);

2460 2461 2462 2463 2464
	if (intel_crtc->config->lane_count > 2) {
		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
		val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
	}
2465

V
Ville Syrjälä 已提交
2466
	mutex_unlock(&dev_priv->sb_lock);
2467 2468
}

2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504
static void
_intel_dp_set_link_train(struct intel_dp *intel_dp,
			 uint32_t *DP,
			 uint8_t dp_train_pat)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = intel_dig_port->port;

	if (HAS_DDI(dev)) {
		uint32_t temp = I915_READ(DP_TP_CTL(port));

		if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
			temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
		else
			temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;

		temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
			temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;

			break;
		case DP_TRAINING_PATTERN_1:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
			break;
		case DP_TRAINING_PATTERN_2:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
			break;
		case DP_TRAINING_PATTERN_3:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
			break;
		}
		I915_WRITE(DP_TP_CTL(port), temp);

2505 2506
	} else if ((IS_GEN7(dev) && port == PORT_A) ||
		   (HAS_PCH_CPT(dev) && port != PORT_A)) {
2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563
		*DP &= ~DP_LINK_TRAIN_MASK_CPT;

		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
			*DP |= DP_LINK_TRAIN_OFF_CPT;
			break;
		case DP_TRAINING_PATTERN_1:
			*DP |= DP_LINK_TRAIN_PAT_1_CPT;
			break;
		case DP_TRAINING_PATTERN_2:
			*DP |= DP_LINK_TRAIN_PAT_2_CPT;
			break;
		case DP_TRAINING_PATTERN_3:
			DRM_ERROR("DP training pattern 3 not supported\n");
			*DP |= DP_LINK_TRAIN_PAT_2_CPT;
			break;
		}

	} else {
		if (IS_CHERRYVIEW(dev))
			*DP &= ~DP_LINK_TRAIN_MASK_CHV;
		else
			*DP &= ~DP_LINK_TRAIN_MASK;

		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
			*DP |= DP_LINK_TRAIN_OFF;
			break;
		case DP_TRAINING_PATTERN_1:
			*DP |= DP_LINK_TRAIN_PAT_1;
			break;
		case DP_TRAINING_PATTERN_2:
			*DP |= DP_LINK_TRAIN_PAT_2;
			break;
		case DP_TRAINING_PATTERN_3:
			if (IS_CHERRYVIEW(dev)) {
				*DP |= DP_LINK_TRAIN_PAT_3_CHV;
			} else {
				DRM_ERROR("DP training pattern 3 not supported\n");
				*DP |= DP_LINK_TRAIN_PAT_2;
			}
			break;
		}
	}
}

static void intel_dp_enable_port(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;

	/* enable with pattern 1 (as per spec) */
	_intel_dp_set_link_train(intel_dp, &intel_dp->DP,
				 DP_TRAINING_PATTERN_1);

	I915_WRITE(intel_dp->output_reg, intel_dp->DP);
	POSTING_READ(intel_dp->output_reg);
2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574

	/*
	 * Magic for VLV/CHV. We _must_ first set up the register
	 * without actually enabling the port, and then do another
	 * write to enable the port. Otherwise link training will
	 * fail when the power sequencer is freshly used for this port.
	 */
	intel_dp->DP |= DP_PORT_EN;

	I915_WRITE(intel_dp->output_reg, intel_dp->DP);
	POSTING_READ(intel_dp->output_reg);
2575 2576
}

2577
static void intel_enable_dp(struct intel_encoder *encoder)
2578
{
2579 2580 2581
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2582
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2583
	uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2584

2585 2586
	if (WARN_ON(dp_reg & DP_PORT_EN))
		return;
2587

2588 2589 2590 2591 2592
	pps_lock(intel_dp);

	if (IS_VALLEYVIEW(dev))
		vlv_init_panel_power_sequencer(intel_dp);

2593
	intel_dp_enable_port(intel_dp);
2594 2595 2596 2597 2598 2599 2600

	edp_panel_vdd_on(intel_dp);
	edp_panel_on(intel_dp);
	edp_panel_vdd_off(intel_dp, true);

	pps_unlock(intel_dp);

2601 2602 2603 2604 2605 2606
	if (IS_VALLEYVIEW(dev)) {
		unsigned int lane_mask = 0x0;

		if (IS_CHERRYVIEW(dev))
			lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count);

2607 2608
		vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
				    lane_mask);
2609
	}
2610

2611
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2612 2613
	intel_dp_start_link_train(intel_dp);
	intel_dp_complete_link_train(intel_dp);
2614
	intel_dp_stop_link_train(intel_dp);
2615

2616
	if (crtc->config->has_audio) {
2617 2618 2619 2620
		DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
				 pipe_name(crtc->pipe));
		intel_audio_codec_enable(encoder);
	}
2621
}
2622

2623 2624
static void g4x_enable_dp(struct intel_encoder *encoder)
{
2625 2626
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

2627
	intel_enable_dp(encoder);
2628
	intel_edp_backlight_on(intel_dp);
2629
}
2630

2631 2632
static void vlv_enable_dp(struct intel_encoder *encoder)
{
2633 2634
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

2635
	intel_edp_backlight_on(intel_dp);
2636
	intel_psr_enable(intel_dp);
2637 2638
}

2639
static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2640 2641 2642 2643
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);

2644 2645
	intel_dp_prepare(encoder);

2646 2647 2648
	/* Only ilk+ has port A */
	if (dport->port == PORT_A) {
		ironlake_set_pll_cpu_edp(intel_dp);
2649
		ironlake_edp_pll_on(intel_dp);
2650
	}
2651 2652
}

2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678
static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
	enum pipe pipe = intel_dp->pps_pipe;
	int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);

	edp_panel_vdd_off_sync(intel_dp);

	/*
	 * VLV seems to get confused when multiple power seqeuencers
	 * have the same port selected (even if only one has power/vdd
	 * enabled). The failure manifests as vlv_wait_port_ready() failing
	 * CHV on the other hand doesn't seem to mind having the same port
	 * selected in multiple power seqeuencers, but let's clear the
	 * port select always when logically disconnecting a power sequencer
	 * from a port.
	 */
	DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
		      pipe_name(pipe), port_name(intel_dig_port->port));
	I915_WRITE(pp_on_reg, 0);
	POSTING_READ(pp_on_reg);

	intel_dp->pps_pipe = INVALID_PIPE;
}

2679 2680 2681 2682 2683 2684 2685 2686
static void vlv_steal_power_sequencer(struct drm_device *dev,
				      enum pipe pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_encoder *encoder;

	lockdep_assert_held(&dev_priv->pps_mutex);

2687 2688 2689
	if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
		return;

2690 2691 2692
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		struct intel_dp *intel_dp;
2693
		enum port port;
2694 2695 2696 2697 2698

		if (encoder->type != INTEL_OUTPUT_EDP)
			continue;

		intel_dp = enc_to_intel_dp(&encoder->base);
2699
		port = dp_to_dig_port(intel_dp)->port;
2700 2701 2702 2703 2704

		if (intel_dp->pps_pipe != pipe)
			continue;

		DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2705
			      pipe_name(pipe), port_name(port));
2706

2707
		WARN(encoder->base.crtc,
2708 2709
		     "stealing pipe %c power sequencer from active eDP port %c\n",
		     pipe_name(pipe), port_name(port));
2710 2711

		/* make sure vdd is off before we steal it */
2712
		vlv_detach_power_sequencer(intel_dp);
2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725
	}
}

static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *encoder = &intel_dig_port->base;
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);

	lockdep_assert_held(&dev_priv->pps_mutex);

2726 2727 2728
	if (!is_edp(intel_dp))
		return;

2729 2730 2731 2732 2733 2734 2735 2736 2737
	if (intel_dp->pps_pipe == crtc->pipe)
		return;

	/*
	 * If another power sequencer was being used on this
	 * port previously make sure to turn off vdd there while
	 * we still have control of it.
	 */
	if (intel_dp->pps_pipe != INVALID_PIPE)
2738
		vlv_detach_power_sequencer(intel_dp);
2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752

	/*
	 * We may be stealing the power
	 * sequencer from another port.
	 */
	vlv_steal_power_sequencer(dev, crtc->pipe);

	/* now it's all ours */
	intel_dp->pps_pipe = crtc->pipe;

	DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
		      pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));

	/* init power sequencer on this pipe and port */
2753 2754
	intel_dp_init_panel_power_sequencer(dev, intel_dp);
	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
2755 2756
}

2757
static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2758
{
2759
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2760
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2761
	struct drm_device *dev = encoder->base.dev;
2762
	struct drm_i915_private *dev_priv = dev->dev_private;
2763
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2764
	enum dpio_channel port = vlv_dport_to_channel(dport);
2765 2766
	int pipe = intel_crtc->pipe;
	u32 val;
2767

V
Ville Syrjälä 已提交
2768
	mutex_lock(&dev_priv->sb_lock);
2769

2770
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2771 2772 2773 2774 2775 2776
	val = 0;
	if (pipe)
		val |= (1<<21);
	else
		val &= ~(1<<21);
	val |= 0x001000c4;
2777 2778 2779
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2780

V
Ville Syrjälä 已提交
2781
	mutex_unlock(&dev_priv->sb_lock);
2782 2783

	intel_enable_dp(encoder);
2784 2785
}

2786
static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2787 2788 2789 2790
{
	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2791 2792
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
2793
	enum dpio_channel port = vlv_dport_to_channel(dport);
2794
	int pipe = intel_crtc->pipe;
2795

2796 2797
	intel_dp_prepare(encoder);

2798
	/* Program Tx lane resets to default */
V
Ville Syrjälä 已提交
2799
	mutex_lock(&dev_priv->sb_lock);
2800
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2801 2802
			 DPIO_PCS_TX_LANE2_RESET |
			 DPIO_PCS_TX_LANE1_RESET);
2803
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2804 2805 2806 2807 2808 2809
			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
			 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
			 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
				 DPIO_PCS_CLK_SOFT_RESET);

	/* Fix up inter-pair skew failure */
2810 2811 2812
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
V
Ville Syrjälä 已提交
2813
	mutex_unlock(&dev_priv->sb_lock);
2814 2815
}

2816 2817 2818 2819 2820 2821 2822 2823 2824 2825
static void chv_pre_enable_dp(struct intel_encoder *encoder)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
	enum dpio_channel ch = vlv_dport_to_channel(dport);
	int pipe = intel_crtc->pipe;
2826
	int data, i, stagger;
2827
	u32 val;
2828

V
Ville Syrjälä 已提交
2829
	mutex_lock(&dev_priv->sb_lock);
2830

2831 2832 2833 2834 2835
	/* allow hardware to manage TX FIFO reset source */
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);

2836 2837 2838 2839 2840
	if (intel_crtc->config->lane_count > 2) {
		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
		val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
	}
2841

2842
	/* Deassert soft data lane reset*/
2843
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2844
	val |= CHV_PCS_REQ_SOFTRESET_EN;
2845 2846
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);

2847 2848 2849 2850 2851
	if (intel_crtc->config->lane_count > 2) {
		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
		val |= CHV_PCS_REQ_SOFTRESET_EN;
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
	}
2852 2853 2854 2855

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2856

2857 2858 2859 2860 2861
	if (intel_crtc->config->lane_count > 2) {
		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
		val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
	}
2862 2863

	/* Program Tx lane latency optimal setting*/
2864
	for (i = 0; i < intel_crtc->config->lane_count; i++) {
2865
		/* Set the upar bit */
2866 2867 2868 2869
		if (intel_crtc->config->lane_count == 1)
			data = 0x0;
		else
			data = (i == 1) ? 0x0 : 0x1;
2870 2871 2872 2873 2874
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
				data << DPIO_UPAR_SHIFT);
	}

	/* Data lane stagger programming */
2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889
	if (intel_crtc->config->port_clock > 270000)
		stagger = 0x18;
	else if (intel_crtc->config->port_clock > 135000)
		stagger = 0xd;
	else if (intel_crtc->config->port_clock > 67500)
		stagger = 0x7;
	else if (intel_crtc->config->port_clock > 33750)
		stagger = 0x4;
	else
		stagger = 0x2;

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
	val |= DPIO_TX2_STAGGER_MASK(0x1f);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);

2890 2891 2892 2893 2894
	if (intel_crtc->config->lane_count > 2) {
		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
		val |= DPIO_TX2_STAGGER_MASK(0x1f);
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
	}
2895 2896 2897 2898 2899 2900 2901 2902

	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
		       DPIO_LANESTAGGER_STRAP(stagger) |
		       DPIO_LANESTAGGER_STRAP_OVRD |
		       DPIO_TX1_STAGGER_MASK(0x1f) |
		       DPIO_TX1_STAGGER_MULT(6) |
		       DPIO_TX2_STAGGER_MULT(0));

2903 2904 2905 2906 2907 2908 2909 2910
	if (intel_crtc->config->lane_count > 2) {
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
			       DPIO_LANESTAGGER_STRAP(stagger) |
			       DPIO_LANESTAGGER_STRAP_OVRD |
			       DPIO_TX1_STAGGER_MASK(0x1f) |
			       DPIO_TX1_STAGGER_MULT(7) |
			       DPIO_TX2_STAGGER_MULT(5));
	}
2911

V
Ville Syrjälä 已提交
2912
	mutex_unlock(&dev_priv->sb_lock);
2913 2914

	intel_enable_dp(encoder);
2915 2916 2917 2918 2919 2920

	/* Second common lane will stay alive on its own now */
	if (dport->release_cl2_override) {
		chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
		dport->release_cl2_override = false;
	}
2921 2922
}

2923 2924 2925 2926 2927 2928 2929 2930 2931
static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
{
	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
	enum dpio_channel ch = vlv_dport_to_channel(dport);
	enum pipe pipe = intel_crtc->pipe;
2932 2933
	unsigned int lane_mask =
		intel_dp_unused_lane_mask(intel_crtc->config->lane_count);
2934 2935
	u32 val;

2936 2937
	intel_dp_prepare(encoder);

2938 2939 2940 2941 2942 2943 2944 2945
	/*
	 * Must trick the second common lane into life.
	 * Otherwise we can't even access the PLL.
	 */
	if (ch == DPIO_CH0 && pipe == PIPE_B)
		dport->release_cl2_override =
			!chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);

2946 2947
	chv_phy_powergate_lanes(encoder, true, lane_mask);

V
Ville Syrjälä 已提交
2948
	mutex_lock(&dev_priv->sb_lock);
2949

2950 2951 2952 2953 2954 2955 2956 2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968
	/* program left/right clock distribution */
	if (pipe != PIPE_B) {
		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
		if (ch == DPIO_CH0)
			val |= CHV_BUFLEFTENA1_FORCE;
		if (ch == DPIO_CH1)
			val |= CHV_BUFRIGHTENA1_FORCE;
		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
	} else {
		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
		if (ch == DPIO_CH0)
			val |= CHV_BUFLEFTENA2_FORCE;
		if (ch == DPIO_CH1)
			val |= CHV_BUFRIGHTENA2_FORCE;
		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
	}

2969 2970 2971 2972 2973 2974 2975 2976 2977
	/* program clock channel usage */
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
	if (pipe != PIPE_B)
		val &= ~CHV_PCS_USEDCLKCHANNEL;
	else
		val |= CHV_PCS_USEDCLKCHANNEL;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);

2978 2979 2980 2981 2982 2983 2984 2985 2986
	if (intel_crtc->config->lane_count > 2) {
		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
		val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
		if (pipe != PIPE_B)
			val &= ~CHV_PCS_USEDCLKCHANNEL;
		else
			val |= CHV_PCS_USEDCLKCHANNEL;
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
	}
2987 2988 2989 2990 2991 2992 2993 2994 2995 2996 2997 2998 2999

	/*
	 * This a a bit weird since generally CL
	 * matches the pipe, but here we need to
	 * pick the CL based on the port.
	 */
	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
	if (pipe != PIPE_B)
		val &= ~CHV_CMN_USEDCLKCHANNEL;
	else
		val |= CHV_CMN_USEDCLKCHANNEL;
	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);

V
Ville Syrjälä 已提交
3000
	mutex_unlock(&dev_priv->sb_lock);
3001 3002
}

3003 3004 3005 3006 3007 3008 3009 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022
static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
	u32 val;

	mutex_lock(&dev_priv->sb_lock);

	/* disable left/right clock distribution */
	if (pipe != PIPE_B) {
		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
	} else {
		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
	}

	mutex_unlock(&dev_priv->sb_lock);
3023

3024 3025 3026 3027 3028 3029 3030 3031 3032
	/*
	 * Leave the power down bit cleared for at least one
	 * lane so that chv_powergate_phy_ch() will power
	 * on something when the channel is otherwise unused.
	 * When the port is off and the override is removed
	 * the lanes power down anyway, so otherwise it doesn't
	 * really matter what the state of power down bits is
	 * after this.
	 */
3033
	chv_phy_powergate_lanes(encoder, false, 0x0);
3034 3035
}

3036
/*
3037 3038
 * Native read with retry for link status and receiver capability reads for
 * cases where the sink may still be asleep.
3039 3040 3041
 *
 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
 * supposed to retry 3 times per the spec.
3042
 */
3043 3044 3045
static ssize_t
intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
			void *buffer, size_t size)
3046
{
3047 3048
	ssize_t ret;
	int i;
3049

3050 3051 3052 3053 3054 3055 3056
	/*
	 * Sometime we just get the same incorrect byte repeated
	 * over the entire buffer. Doing just one throw away read
	 * initially seems to "solve" it.
	 */
	drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);

3057
	for (i = 0; i < 3; i++) {
3058 3059 3060
		ret = drm_dp_dpcd_read(aux, offset, buffer, size);
		if (ret == size)
			return ret;
3061 3062
		msleep(1);
	}
3063

3064
	return ret;
3065 3066 3067 3068 3069 3070 3071
}

/*
 * Fetch AUX CH registers 0x202 - 0x207 which contain
 * link status information
 */
static bool
3072
intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3073
{
3074 3075 3076 3077
	return intel_dp_dpcd_read_wake(&intel_dp->aux,
				       DP_LANE0_1_STATUS,
				       link_status,
				       DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3078 3079
}

3080
/* These are source-specific values. */
3081
static uint8_t
K
Keith Packard 已提交
3082
intel_dp_voltage_max(struct intel_dp *intel_dp)
3083
{
3084
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
3085
	struct drm_i915_private *dev_priv = dev->dev_private;
3086
	enum port port = dp_to_dig_port(intel_dp)->port;
K
Keith Packard 已提交
3087

3088 3089 3090
	if (IS_BROXTON(dev))
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
	else if (INTEL_INFO(dev)->gen >= 9) {
3091
		if (dev_priv->edp_low_vswing && port == PORT_A)
3092
			return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3093
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3094
	} else if (IS_VALLEYVIEW(dev))
3095
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3096
	else if (IS_GEN7(dev) && port == PORT_A)
3097
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3098
	else if (HAS_PCH_CPT(dev) && port != PORT_A)
3099
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
K
Keith Packard 已提交
3100
	else
3101
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
K
Keith Packard 已提交
3102 3103 3104 3105 3106
}

static uint8_t
intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
{
3107
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
3108
	enum port port = dp_to_dig_port(intel_dp)->port;
K
Keith Packard 已提交
3109

3110 3111 3112 3113 3114 3115 3116 3117
	if (INTEL_INFO(dev)->gen >= 9) {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
			return DP_TRAIN_PRE_EMPH_LEVEL_3;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
			return DP_TRAIN_PRE_EMPH_LEVEL_1;
3118 3119
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
3120 3121 3122 3123
		default:
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
		}
	} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3124
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3125 3126 3127 3128 3129 3130 3131
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
			return DP_TRAIN_PRE_EMPH_LEVEL_3;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
			return DP_TRAIN_PRE_EMPH_LEVEL_1;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3132
		default:
3133
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
3134
		}
3135 3136
	} else if (IS_VALLEYVIEW(dev)) {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3137 3138 3139 3140 3141 3142 3143
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
			return DP_TRAIN_PRE_EMPH_LEVEL_3;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
			return DP_TRAIN_PRE_EMPH_LEVEL_1;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3144
		default:
3145
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
3146
		}
3147
	} else if (IS_GEN7(dev) && port == PORT_A) {
K
Keith Packard 已提交
3148
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3149 3150 3151 3152 3153
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
			return DP_TRAIN_PRE_EMPH_LEVEL_1;
K
Keith Packard 已提交
3154
		default:
3155
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
K
Keith Packard 已提交
3156 3157 3158
		}
	} else {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3159 3160 3161 3162 3163 3164 3165
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
			return DP_TRAIN_PRE_EMPH_LEVEL_1;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
K
Keith Packard 已提交
3166
		default:
3167
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
K
Keith Packard 已提交
3168
		}
3169 3170 3171
	}
}

3172
static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3173 3174 3175 3176
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3177 3178
	struct intel_crtc *intel_crtc =
		to_intel_crtc(dport->base.base.crtc);
3179 3180 3181
	unsigned long demph_reg_value, preemph_reg_value,
		uniqtranscale_reg_value;
	uint8_t train_set = intel_dp->train_set[0];
3182
	enum dpio_channel port = vlv_dport_to_channel(dport);
3183
	int pipe = intel_crtc->pipe;
3184 3185

	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3186
	case DP_TRAIN_PRE_EMPH_LEVEL_0:
3187 3188
		preemph_reg_value = 0x0004000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3189
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3190 3191 3192
			demph_reg_value = 0x2B405555;
			uniqtranscale_reg_value = 0x552AB83A;
			break;
3193
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3194 3195 3196
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x5548B83A;
			break;
3197
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3198 3199 3200
			demph_reg_value = 0x2B245555;
			uniqtranscale_reg_value = 0x5560B83A;
			break;
3201
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3202 3203 3204 3205 3206 3207 3208
			demph_reg_value = 0x2B405555;
			uniqtranscale_reg_value = 0x5598DA3A;
			break;
		default:
			return 0;
		}
		break;
3209
	case DP_TRAIN_PRE_EMPH_LEVEL_1:
3210 3211
		preemph_reg_value = 0x0002000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3212
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3213 3214 3215
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x5552B83A;
			break;
3216
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3217 3218 3219
			demph_reg_value = 0x2B404848;
			uniqtranscale_reg_value = 0x5580B83A;
			break;
3220
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3221 3222 3223 3224 3225 3226 3227
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
3228
	case DP_TRAIN_PRE_EMPH_LEVEL_2:
3229 3230
		preemph_reg_value = 0x0000000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3231
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3232 3233 3234
			demph_reg_value = 0x2B305555;
			uniqtranscale_reg_value = 0x5570B83A;
			break;
3235
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3236 3237 3238 3239 3240 3241 3242
			demph_reg_value = 0x2B2B4040;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
3243
	case DP_TRAIN_PRE_EMPH_LEVEL_3:
3244 3245
		preemph_reg_value = 0x0006000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3246
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3247 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257
			demph_reg_value = 0x1B405555;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
	default:
		return 0;
	}

V
Ville Syrjälä 已提交
3258
	mutex_lock(&dev_priv->sb_lock);
3259 3260 3261
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
3262
			 uniqtranscale_reg_value);
3263 3264 3265 3266
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
V
Ville Syrjälä 已提交
3267
	mutex_unlock(&dev_priv->sb_lock);
3268 3269 3270 3271

	return 0;
}

3272 3273 3274 3275 3276 3277
static bool chv_need_uniq_trans_scale(uint8_t train_set)
{
	return (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) == DP_TRAIN_PRE_EMPH_LEVEL_0 &&
		(train_set & DP_TRAIN_VOLTAGE_SWING_MASK) == DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
}

3278
static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3279 3280 3281 3282 3283
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
	struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
3284
	u32 deemph_reg_value, margin_reg_value, val;
3285 3286
	uint8_t train_set = intel_dp->train_set[0];
	enum dpio_channel ch = vlv_dport_to_channel(dport);
3287 3288
	enum pipe pipe = intel_crtc->pipe;
	int i;
3289 3290

	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3291
	case DP_TRAIN_PRE_EMPH_LEVEL_0:
3292
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3293
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3294 3295 3296
			deemph_reg_value = 128;
			margin_reg_value = 52;
			break;
3297
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3298 3299 3300
			deemph_reg_value = 128;
			margin_reg_value = 77;
			break;
3301
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3302 3303 3304
			deemph_reg_value = 128;
			margin_reg_value = 102;
			break;
3305
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3306 3307 3308 3309 3310 3311 3312 3313
			deemph_reg_value = 128;
			margin_reg_value = 154;
			/* FIXME extra to set for 1200 */
			break;
		default:
			return 0;
		}
		break;
3314
	case DP_TRAIN_PRE_EMPH_LEVEL_1:
3315
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3316
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3317 3318 3319
			deemph_reg_value = 85;
			margin_reg_value = 78;
			break;
3320
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3321 3322 3323
			deemph_reg_value = 85;
			margin_reg_value = 116;
			break;
3324
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3325 3326 3327 3328 3329 3330 3331
			deemph_reg_value = 85;
			margin_reg_value = 154;
			break;
		default:
			return 0;
		}
		break;
3332
	case DP_TRAIN_PRE_EMPH_LEVEL_2:
3333
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3334
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3335 3336 3337
			deemph_reg_value = 64;
			margin_reg_value = 104;
			break;
3338
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3339 3340 3341 3342 3343 3344 3345
			deemph_reg_value = 64;
			margin_reg_value = 154;
			break;
		default:
			return 0;
		}
		break;
3346
	case DP_TRAIN_PRE_EMPH_LEVEL_3:
3347
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3348
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3349 3350 3351 3352 3353 3354 3355 3356 3357 3358 3359
			deemph_reg_value = 43;
			margin_reg_value = 154;
			break;
		default:
			return 0;
		}
		break;
	default:
		return 0;
	}

V
Ville Syrjälä 已提交
3360
	mutex_lock(&dev_priv->sb_lock);
3361 3362

	/* Clear calc init */
3363 3364
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3365 3366
	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3367 3368
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);

3369 3370 3371 3372 3373 3374 3375
	if (intel_crtc->config->lane_count > 2) {
		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
		val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
		val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
		val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
	}
3376

3377 3378 3379 3380 3381
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);

3382 3383 3384 3385 3386 3387
	if (intel_crtc->config->lane_count > 2) {
		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
		val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
		val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
	}
3388

3389
	/* Program swing deemph */
3390
	for (i = 0; i < intel_crtc->config->lane_count; i++) {
3391 3392 3393 3394 3395
		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
		val &= ~DPIO_SWING_DEEMPH9P5_MASK;
		val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
	}
3396 3397

	/* Program swing margin */
3398
	for (i = 0; i < intel_crtc->config->lane_count; i++) {
3399
		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3400

3401 3402
		val &= ~DPIO_SWING_MARGIN000_MASK;
		val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
3403 3404 3405 3406 3407 3408 3409 3410 3411

		/*
		 * Supposedly this value shouldn't matter when unique transition
		 * scale is disabled, but in fact it does matter. Let's just
		 * always program the same value and hope it's OK.
		 */
		val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
		val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;

3412 3413
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
	}
3414

3415 3416 3417 3418 3419 3420
	/*
	 * The document said it needs to set bit 27 for ch0 and bit 26
	 * for ch1. Might be a typo in the doc.
	 * For now, for this unique transition scale selection, set bit
	 * 27 for ch0 and ch1.
	 */
3421
	for (i = 0; i < intel_crtc->config->lane_count; i++) {
3422
		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3423
		if (chv_need_uniq_trans_scale(train_set))
3424
			val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3425 3426 3427
		else
			val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3428 3429 3430
	}

	/* Start swing calculation */
3431 3432 3433 3434
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);

3435 3436 3437 3438 3439
	if (intel_crtc->config->lane_count > 2) {
		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
		val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
	}
3440 3441 3442 3443 3444 3445

	/* LRC Bypass */
	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
	val |= DPIO_LRC_BYPASS;
	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);

V
Ville Syrjälä 已提交
3446
	mutex_unlock(&dev_priv->sb_lock);
3447 3448 3449 3450

	return 0;
}

3451
static void
J
Jani Nikula 已提交
3452 3453
intel_get_adjust_train(struct intel_dp *intel_dp,
		       const uint8_t link_status[DP_LINK_STATUS_SIZE])
3454 3455 3456 3457
{
	uint8_t v = 0;
	uint8_t p = 0;
	int lane;
K
Keith Packard 已提交
3458 3459
	uint8_t voltage_max;
	uint8_t preemph_max;
3460

3461
	for (lane = 0; lane < intel_dp->lane_count; lane++) {
3462 3463
		uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
		uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
3464 3465 3466 3467 3468 3469 3470

		if (this_v > v)
			v = this_v;
		if (this_p > p)
			p = this_p;
	}

K
Keith Packard 已提交
3471
	voltage_max = intel_dp_voltage_max(intel_dp);
3472 3473
	if (v >= voltage_max)
		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
3474

K
Keith Packard 已提交
3475 3476 3477
	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
	if (p >= preemph_max)
		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
3478 3479

	for (lane = 0; lane < 4; lane++)
3480
		intel_dp->train_set[lane] = v | p;
3481 3482 3483
}

static uint32_t
3484
gen4_signal_levels(uint8_t train_set)
3485
{
3486
	uint32_t	signal_levels = 0;
3487

3488
	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3489
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3490 3491 3492
	default:
		signal_levels |= DP_VOLTAGE_0_4;
		break;
3493
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3494 3495
		signal_levels |= DP_VOLTAGE_0_6;
		break;
3496
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3497 3498
		signal_levels |= DP_VOLTAGE_0_8;
		break;
3499
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3500 3501 3502
		signal_levels |= DP_VOLTAGE_1_2;
		break;
	}
3503
	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3504
	case DP_TRAIN_PRE_EMPH_LEVEL_0:
3505 3506 3507
	default:
		signal_levels |= DP_PRE_EMPHASIS_0;
		break;
3508
	case DP_TRAIN_PRE_EMPH_LEVEL_1:
3509 3510
		signal_levels |= DP_PRE_EMPHASIS_3_5;
		break;
3511
	case DP_TRAIN_PRE_EMPH_LEVEL_2:
3512 3513
		signal_levels |= DP_PRE_EMPHASIS_6;
		break;
3514
	case DP_TRAIN_PRE_EMPH_LEVEL_3:
3515 3516 3517 3518 3519 3520
		signal_levels |= DP_PRE_EMPHASIS_9_5;
		break;
	}
	return signal_levels;
}

3521 3522
/* Gen6's DP voltage swing and pre-emphasis control */
static uint32_t
3523
gen6_edp_signal_levels(uint8_t train_set)
3524
{
3525 3526 3527
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
3528 3529
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3530
		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3531
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3532
		return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3533 3534
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3535
		return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3536 3537
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3538
		return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3539 3540
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3541
		return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3542
	default:
3543 3544 3545
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3546 3547 3548
	}
}

K
Keith Packard 已提交
3549 3550
/* Gen7's DP voltage swing and pre-emphasis control */
static uint32_t
3551
gen7_edp_signal_levels(uint8_t train_set)
K
Keith Packard 已提交
3552 3553 3554 3555
{
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
3556
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
K
Keith Packard 已提交
3557
		return EDP_LINK_TRAIN_400MV_0DB_IVB;
3558
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
K
Keith Packard 已提交
3559
		return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3560
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
K
Keith Packard 已提交
3561 3562
		return EDP_LINK_TRAIN_400MV_6DB_IVB;

3563
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
K
Keith Packard 已提交
3564
		return EDP_LINK_TRAIN_600MV_0DB_IVB;
3565
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
K
Keith Packard 已提交
3566 3567
		return EDP_LINK_TRAIN_600MV_3_5DB_IVB;

3568
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
K
Keith Packard 已提交
3569
		return EDP_LINK_TRAIN_800MV_0DB_IVB;
3570
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
K
Keith Packard 已提交
3571 3572 3573 3574 3575 3576 3577 3578 3579
		return EDP_LINK_TRAIN_800MV_3_5DB_IVB;

	default:
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return EDP_LINK_TRAIN_500MV_0DB_IVB;
	}
}

3580 3581 3582 3583 3584
/* Properly updates "DP" with the correct signal levels. */
static void
intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3585
	enum port port = intel_dig_port->port;
3586
	struct drm_device *dev = intel_dig_port->base.base.dev;
3587
	uint32_t signal_levels, mask = 0;
3588 3589
	uint8_t train_set = intel_dp->train_set[0];

3590 3591 3592 3593 3594 3595 3596
	if (HAS_DDI(dev)) {
		signal_levels = ddi_signal_levels(intel_dp);

		if (IS_BROXTON(dev))
			signal_levels = 0;
		else
			mask = DDI_BUF_EMP_MASK;
3597
	} else if (IS_CHERRYVIEW(dev)) {
3598
		signal_levels = chv_signal_levels(intel_dp);
3599
	} else if (IS_VALLEYVIEW(dev)) {
3600
		signal_levels = vlv_signal_levels(intel_dp);
3601
	} else if (IS_GEN7(dev) && port == PORT_A) {
3602
		signal_levels = gen7_edp_signal_levels(train_set);
3603
		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3604
	} else if (IS_GEN6(dev) && port == PORT_A) {
3605
		signal_levels = gen6_edp_signal_levels(train_set);
3606 3607
		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
	} else {
3608
		signal_levels = gen4_signal_levels(train_set);
3609 3610 3611
		mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
	}

3612 3613 3614 3615 3616 3617 3618 3619
	if (mask)
		DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);

	DRM_DEBUG_KMS("Using vswing level %d\n",
		train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
	DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
		(train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
			DP_TRAIN_PRE_EMPHASIS_SHIFT);
3620 3621 3622 3623

	*DP = (*DP & ~mask) | signal_levels;
}

3624
static bool
C
Chris Wilson 已提交
3625
intel_dp_set_link_train(struct intel_dp *intel_dp,
3626
			uint32_t *DP,
3627
			uint8_t dp_train_pat)
3628
{
3629
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3630 3631
	struct drm_i915_private *dev_priv =
		to_i915(intel_dig_port->base.base.dev);
3632 3633
	uint8_t buf[sizeof(intel_dp->train_set) + 1];
	int ret, len;
3634

3635
	_intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3636

3637
	I915_WRITE(intel_dp->output_reg, *DP);
C
Chris Wilson 已提交
3638
	POSTING_READ(intel_dp->output_reg);
3639

3640 3641
	buf[0] = dp_train_pat;
	if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
3642
	    DP_TRAINING_PATTERN_DISABLE) {
3643 3644 3645 3646
		/* don't write DP_TRAINING_LANEx_SET on disable */
		len = 1;
	} else {
		/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3647 3648
		memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
		len = intel_dp->lane_count + 1;
3649
	}
3650

3651 3652
	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
				buf, len);
3653 3654

	return ret == len;
3655 3656
}

3657 3658 3659 3660
static bool
intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
			uint8_t dp_train_pat)
{
3661 3662
	if (!intel_dp->train_set_valid)
		memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
3663 3664 3665 3666 3667 3668
	intel_dp_set_signal_levels(intel_dp, DP);
	return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
}

static bool
intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
J
Jani Nikula 已提交
3669
			   const uint8_t link_status[DP_LINK_STATUS_SIZE])
3670 3671
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3672 3673
	struct drm_i915_private *dev_priv =
		to_i915(intel_dig_port->base.base.dev);
3674 3675 3676 3677 3678 3679 3680 3681
	int ret;

	intel_get_adjust_train(intel_dp, link_status);
	intel_dp_set_signal_levels(intel_dp, DP);

	I915_WRITE(intel_dp->output_reg, *DP);
	POSTING_READ(intel_dp->output_reg);

3682
	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3683
				intel_dp->train_set, intel_dp->lane_count);
3684

3685
	return ret == intel_dp->lane_count;
3686 3687
}

3688 3689 3690 3691 3692 3693 3694 3695 3696 3697 3698 3699 3700 3701 3702 3703 3704 3705 3706 3707 3708 3709 3710 3711 3712 3713 3714 3715 3716 3717 3718
static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = intel_dig_port->port;
	uint32_t val;

	if (!HAS_DDI(dev))
		return;

	val = I915_READ(DP_TP_CTL(port));
	val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
	val |= DP_TP_CTL_LINK_TRAIN_IDLE;
	I915_WRITE(DP_TP_CTL(port), val);

	/*
	 * On PORT_A we can have only eDP in SST mode. There the only reason
	 * we need to set idle transmission mode is to work around a HW issue
	 * where we enable the pipe while not in idle link-training mode.
	 * In this case there is requirement to wait for a minimum number of
	 * idle patterns to be sent.
	 */
	if (port == PORT_A)
		return;

	if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
		     1))
		DRM_ERROR("Timed out waiting for DP idle patterns\n");
}

3719
/* Enable corresponding port and start training pattern 1 */
3720
void
3721
intel_dp_start_link_train(struct intel_dp *intel_dp)
3722
{
3723
	struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
3724
	struct drm_device *dev = encoder->dev;
3725 3726
	int i;
	uint8_t voltage;
3727
	int voltage_tries, loop_tries;
C
Chris Wilson 已提交
3728
	uint32_t DP = intel_dp->DP;
3729
	uint8_t link_config[2];
3730
	uint8_t link_bw, rate_select;
3731

P
Paulo Zanoni 已提交
3732
	if (HAS_DDI(dev))
3733 3734
		intel_ddi_prepare_link_retrain(encoder);

3735
	intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
3736 3737
			      &link_bw, &rate_select);

3738
	/* Write the link configuration data */
3739
	link_config[0] = link_bw;
3740
	link_config[1] = intel_dp->lane_count;
3741 3742
	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
3743
	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
3744
	if (intel_dp->num_sink_rates)
3745
		drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
3746
				  &rate_select, 1);
3747 3748 3749

	link_config[0] = 0;
	link_config[1] = DP_SET_ANSI_8B10B;
3750
	drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
3751 3752

	DP |= DP_PORT_EN;
K
Keith Packard 已提交
3753

3754 3755 3756 3757 3758 3759 3760 3761
	/* clock recovery */
	if (!intel_dp_reset_link_train(intel_dp, &DP,
				       DP_TRAINING_PATTERN_1 |
				       DP_LINK_SCRAMBLING_DISABLE)) {
		DRM_ERROR("failed to enable link training\n");
		return;
	}

3762
	voltage = 0xff;
3763 3764
	voltage_tries = 0;
	loop_tries = 0;
3765
	for (;;) {
3766
		uint8_t link_status[DP_LINK_STATUS_SIZE];
3767

3768
		drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
3769 3770
		if (!intel_dp_get_link_status(intel_dp, link_status)) {
			DRM_ERROR("failed to get link status\n");
3771
			break;
3772
		}
3773

3774
		if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3775
			DRM_DEBUG_KMS("clock recovery OK\n");
3776 3777 3778
			break;
		}

3779 3780 3781 3782 3783 3784 3785 3786 3787 3788 3789 3790 3791 3792 3793 3794 3795
		/*
		 * if we used previously trained voltage and pre-emphasis values
		 * and we don't get clock recovery, reset link training values
		 */
		if (intel_dp->train_set_valid) {
			DRM_DEBUG_KMS("clock recovery not ok, reset");
			/* clear the flag as we are not reusing train set */
			intel_dp->train_set_valid = false;
			if (!intel_dp_reset_link_train(intel_dp, &DP,
						       DP_TRAINING_PATTERN_1 |
						       DP_LINK_SCRAMBLING_DISABLE)) {
				DRM_ERROR("failed to enable link training\n");
				return;
			}
			continue;
		}

3796
		/* Check to see if we've tried the max voltage */
3797
		for (i = 0; i < intel_dp->lane_count; i++)
3798
			if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
3799
				break;
3800
		if (i == intel_dp->lane_count) {
3801 3802
			++loop_tries;
			if (loop_tries == 5) {
3803
				DRM_ERROR("too many full retries, give up\n");
3804 3805
				break;
			}
3806 3807 3808
			intel_dp_reset_link_train(intel_dp, &DP,
						  DP_TRAINING_PATTERN_1 |
						  DP_LINK_SCRAMBLING_DISABLE);
3809 3810 3811
			voltage_tries = 0;
			continue;
		}
3812

3813
		/* Check to see if we've tried the same voltage 5 times */
3814
		if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
3815
			++voltage_tries;
3816
			if (voltage_tries == 5) {
3817
				DRM_ERROR("too many voltage retries, give up\n");
3818 3819 3820 3821 3822
				break;
			}
		} else
			voltage_tries = 0;
		voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
3823

3824 3825 3826 3827 3828
		/* Update training set as requested by target */
		if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
			DRM_ERROR("failed to update link training\n");
			break;
		}
3829 3830
	}

3831 3832 3833
	intel_dp->DP = DP;
}

3834
void
3835 3836 3837
intel_dp_complete_link_train(struct intel_dp *intel_dp)
{
	bool channel_eq = false;
3838
	int tries, cr_tries;
3839
	uint32_t DP = intel_dp->DP;
3840 3841
	uint32_t training_pattern = DP_TRAINING_PATTERN_2;

3842
	/* Training Pattern 3 for HBR2 or 1.2 devices that support it*/
3843
	if (intel_dp->link_rate == 540000 || intel_dp->use_tps3)
3844
		training_pattern = DP_TRAINING_PATTERN_3;
3845

3846
	/* channel equalization */
3847
	if (!intel_dp_set_link_train(intel_dp, &DP,
3848
				     training_pattern |
3849 3850 3851 3852 3853
				     DP_LINK_SCRAMBLING_DISABLE)) {
		DRM_ERROR("failed to start channel equalization\n");
		return;
	}

3854
	tries = 0;
3855
	cr_tries = 0;
3856 3857
	channel_eq = false;
	for (;;) {
3858
		uint8_t link_status[DP_LINK_STATUS_SIZE];
3859

3860 3861 3862 3863 3864
		if (cr_tries > 5) {
			DRM_ERROR("failed to train DP, aborting\n");
			break;
		}

3865
		drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
3866 3867
		if (!intel_dp_get_link_status(intel_dp, link_status)) {
			DRM_ERROR("failed to get link status\n");
3868
			break;
3869
		}
3870

3871
		/* Make sure clock is still ok */
3872
		if (!drm_dp_clock_recovery_ok(link_status,
3873
					      intel_dp->lane_count)) {
3874
			intel_dp->train_set_valid = false;
3875
			intel_dp_start_link_train(intel_dp);
3876
			intel_dp_set_link_train(intel_dp, &DP,
3877
						training_pattern |
3878
						DP_LINK_SCRAMBLING_DISABLE);
3879 3880 3881 3882
			cr_tries++;
			continue;
		}

3883
		if (drm_dp_channel_eq_ok(link_status,
3884
					 intel_dp->lane_count)) {
3885 3886 3887
			channel_eq = true;
			break;
		}
3888

3889 3890
		/* Try 5 times, then try clock recovery if that fails */
		if (tries > 5) {
3891
			intel_dp->train_set_valid = false;
3892
			intel_dp_start_link_train(intel_dp);
3893
			intel_dp_set_link_train(intel_dp, &DP,
3894
						training_pattern |
3895
						DP_LINK_SCRAMBLING_DISABLE);
3896 3897 3898 3899
			tries = 0;
			cr_tries++;
			continue;
		}
3900

3901 3902 3903 3904 3905
		/* Update training set as requested by target */
		if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
			DRM_ERROR("failed to update link training\n");
			break;
		}
3906
		++tries;
3907
	}
3908

3909 3910 3911 3912
	intel_dp_set_idle_link_train(intel_dp);

	intel_dp->DP = DP;

3913
	if (channel_eq) {
3914
		intel_dp->train_set_valid = true;
M
Masanari Iida 已提交
3915
		DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3916
	}
3917 3918 3919 3920
}

void intel_dp_stop_link_train(struct intel_dp *intel_dp)
{
3921
	intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3922
				DP_TRAINING_PATTERN_DISABLE);
3923 3924 3925
}

static void
C
Chris Wilson 已提交
3926
intel_dp_link_down(struct intel_dp *intel_dp)
3927
{
3928
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3929
	struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3930
	enum port port = intel_dig_port->port;
3931
	struct drm_device *dev = intel_dig_port->base.base.dev;
3932
	struct drm_i915_private *dev_priv = dev->dev_private;
C
Chris Wilson 已提交
3933
	uint32_t DP = intel_dp->DP;
3934

3935
	if (WARN_ON(HAS_DDI(dev)))
3936 3937
		return;

3938
	if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3939 3940
		return;

3941
	DRM_DEBUG_KMS("\n");
3942

3943 3944
	if ((IS_GEN7(dev) && port == PORT_A) ||
	    (HAS_PCH_CPT(dev) && port != PORT_A)) {
3945
		DP &= ~DP_LINK_TRAIN_MASK_CPT;
3946
		DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3947
	} else {
3948 3949 3950 3951
		if (IS_CHERRYVIEW(dev))
			DP &= ~DP_LINK_TRAIN_MASK_CHV;
		else
			DP &= ~DP_LINK_TRAIN_MASK;
3952
		DP |= DP_LINK_TRAIN_PAT_IDLE;
3953
	}
3954
	I915_WRITE(intel_dp->output_reg, DP);
3955
	POSTING_READ(intel_dp->output_reg);
3956

3957 3958 3959 3960 3961 3962 3963 3964 3965 3966 3967 3968 3969 3970 3971 3972 3973
	DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
	I915_WRITE(intel_dp->output_reg, DP);
	POSTING_READ(intel_dp->output_reg);

	/*
	 * HW workaround for IBX, we need to move the port
	 * to transcoder A after disabling it to allow the
	 * matching HDMI port to be enabled on transcoder A.
	 */
	if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
		/* always enable with pattern 1 (as per spec) */
		DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
		DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
		I915_WRITE(intel_dp->output_reg, DP);
		POSTING_READ(intel_dp->output_reg);

		DP &= ~DP_PORT_EN;
3974
		I915_WRITE(intel_dp->output_reg, DP);
3975
		POSTING_READ(intel_dp->output_reg);
3976 3977
	}

3978
	msleep(intel_dp->panel_power_down_delay);
3979 3980
}

3981 3982
static bool
intel_dp_get_dpcd(struct intel_dp *intel_dp)
3983
{
R
Rodrigo Vivi 已提交
3984 3985 3986
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
3987
	uint8_t rev;
R
Rodrigo Vivi 已提交
3988

3989 3990
	if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
				    sizeof(intel_dp->dpcd)) < 0)
3991
		return false; /* aux transfer failed */
3992

3993
	DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3994

3995 3996 3997
	if (intel_dp->dpcd[DP_DPCD_REV] == 0)
		return false; /* DPCD not present */

3998 3999
	/* Check if the panel supports PSR */
	memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
4000
	if (is_edp(intel_dp)) {
4001 4002 4003
		intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
					intel_dp->psr_dpcd,
					sizeof(intel_dp->psr_dpcd));
R
Rodrigo Vivi 已提交
4004 4005
		if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
			dev_priv->psr.sink_support = true;
4006
			DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
R
Rodrigo Vivi 已提交
4007
		}
4008 4009 4010 4011 4012 4013 4014 4015 4016 4017 4018 4019 4020 4021 4022

		if (INTEL_INFO(dev)->gen >= 9 &&
			(intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
			uint8_t frame_sync_cap;

			dev_priv->psr.sink_support = true;
			intel_dp_dpcd_read_wake(&intel_dp->aux,
					DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
					&frame_sync_cap, 1);
			dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
			/* PSR2 needs frame sync as well */
			dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
			DRM_DEBUG_KMS("PSR2 %s on sink",
				dev_priv->psr.psr2_support ? "supported" : "not supported");
		}
4023 4024
	}

4025
	/* Training Pattern 3 support, both source and sink */
4026
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
4027 4028
	    intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
	    (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {
4029
		intel_dp->use_tps3 = true;
4030
		DRM_DEBUG_KMS("Displayport TPS3 supported\n");
4031 4032 4033
	} else
		intel_dp->use_tps3 = false;

4034 4035 4036 4037 4038
	/* Intermediate frequency support */
	if (is_edp(intel_dp) &&
	    (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] &	DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
	    (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
	    (rev >= 0x03)) { /* eDp v1.4 or higher */
4039
		__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
4040 4041
		int i;

4042 4043
		intel_dp_dpcd_read_wake(&intel_dp->aux,
				DP_SUPPORTED_LINK_RATES,
4044 4045
				sink_rates,
				sizeof(sink_rates));
4046

4047 4048
		for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
			int val = le16_to_cpu(sink_rates[i]);
4049 4050 4051 4052

			if (val == 0)
				break;

4053 4054
			/* Value read is in kHz while drm clock is saved in deca-kHz */
			intel_dp->sink_rates[i] = (val * 200) / 10;
4055
		}
4056
		intel_dp->num_sink_rates = i;
4057
	}
4058 4059 4060

	intel_dp_print_rates(intel_dp);

4061 4062 4063 4064 4065 4066 4067
	if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
	      DP_DWN_STRM_PORT_PRESENT))
		return true; /* native DP sink */

	if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
		return true; /* no per-port downstream info */

4068 4069 4070
	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
				    intel_dp->downstream_ports,
				    DP_MAX_DOWNSTREAM_PORTS) < 0)
4071 4072 4073
		return false; /* downstream port status fetch failed */

	return true;
4074 4075
}

4076 4077 4078 4079 4080 4081 4082 4083
static void
intel_dp_probe_oui(struct intel_dp *intel_dp)
{
	u8 buf[3];

	if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
		return;

4084
	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
4085 4086 4087
		DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
			      buf[0], buf[1], buf[2]);

4088
	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
4089 4090 4091 4092
		DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
			      buf[0], buf[1], buf[2]);
}

4093 4094 4095 4096 4097 4098 4099 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 4110 4111 4112 4113 4114 4115 4116 4117
static bool
intel_dp_probe_mst(struct intel_dp *intel_dp)
{
	u8 buf[1];

	if (!intel_dp->can_mst)
		return false;

	if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
		return false;

	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
		if (buf[0] & DP_MST_CAP) {
			DRM_DEBUG_KMS("Sink is MST capable\n");
			intel_dp->is_mst = true;
		} else {
			DRM_DEBUG_KMS("Sink is not MST capable\n");
			intel_dp->is_mst = false;
		}
	}

	drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
	return intel_dp->is_mst;
}

4118
static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
4119
{
4120 4121
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
R
Rodrigo Vivi 已提交
4122
	u8 buf;
4123
	int ret = 0;
4124

4125 4126
	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
		DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
4127 4128
		ret = -EIO;
		goto out;
4129 4130
	}

4131
	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
4132
			       buf & ~DP_TEST_SINK_START) < 0) {
4133
		DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
4134 4135 4136
		ret = -EIO;
		goto out;
	}
4137

4138
	intel_dp->sink_crc.started = false;
4139
 out:
4140
	hsw_enable_ips(intel_crtc);
4141
	return ret;
4142 4143 4144 4145 4146 4147 4148
}

static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
	u8 buf;
4149 4150
	int ret;

4151
	if (intel_dp->sink_crc.started) {
4152 4153 4154 4155
		ret = intel_dp_sink_crc_stop(intel_dp);
		if (ret)
			return ret;
	}
4156 4157 4158 4159 4160 4161 4162

	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
		return -EIO;

	if (!(buf & DP_TEST_CRC_SUPPORTED))
		return -ENOTTY;

4163 4164
	intel_dp->sink_crc.last_count = buf & DP_TEST_COUNT_MASK;

4165 4166 4167 4168
	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
		return -EIO;

	hsw_disable_ips(intel_crtc);
4169

4170
	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
4171 4172 4173
			       buf | DP_TEST_SINK_START) < 0) {
		hsw_enable_ips(intel_crtc);
		return -EIO;
4174 4175
	}

4176
	intel_dp->sink_crc.started = true;
4177 4178 4179 4180 4181 4182 4183 4184 4185
	return 0;
}

int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
	struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
	u8 buf;
4186
	int count, ret;
4187
	int attempts = 6;
4188
	bool old_equal_new;
4189 4190 4191 4192 4193

	ret = intel_dp_sink_crc_start(intel_dp);
	if (ret)
		return ret;

R
Rodrigo Vivi 已提交
4194
	do {
4195 4196
		intel_wait_for_vblank(dev, intel_crtc->pipe);

4197
		if (drm_dp_dpcd_readb(&intel_dp->aux,
4198 4199
				      DP_TEST_SINK_MISC, &buf) < 0) {
			ret = -EIO;
4200
			goto stop;
4201
		}
4202
		count = buf & DP_TEST_COUNT_MASK;
4203

4204 4205 4206 4207 4208 4209 4210 4211 4212 4213 4214
		/*
		 * Count might be reset during the loop. In this case
		 * last known count needs to be reset as well.
		 */
		if (count == 0)
			intel_dp->sink_crc.last_count = 0;

		if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
			ret = -EIO;
			goto stop;
		}
4215 4216 4217 4218 4219 4220

		old_equal_new = (count == intel_dp->sink_crc.last_count &&
				 !memcmp(intel_dp->sink_crc.last_crc, crc,
					 6 * sizeof(u8)));

	} while (--attempts && (count == 0 || old_equal_new));
4221 4222 4223

	intel_dp->sink_crc.last_count = buf & DP_TEST_COUNT_MASK;
	memcpy(intel_dp->sink_crc.last_crc, crc, 6 * sizeof(u8));
R
Rodrigo Vivi 已提交
4224 4225

	if (attempts == 0) {
4226 4227 4228 4229 4230 4231 4232
		if (old_equal_new) {
			DRM_DEBUG_KMS("Unreliable Sink CRC counter: Current returned CRC is identical to the previous one\n");
		} else {
			DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
			ret = -ETIMEDOUT;
			goto stop;
		}
R
Rodrigo Vivi 已提交
4233
	}
4234

4235
stop:
4236
	intel_dp_sink_crc_stop(intel_dp);
4237
	return ret;
4238 4239
}

4240 4241 4242
static bool
intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
{
4243 4244 4245
	return intel_dp_dpcd_read_wake(&intel_dp->aux,
				       DP_DEVICE_SERVICE_IRQ_VECTOR,
				       sink_irq_vector, 1) == 1;
4246 4247
}

4248 4249 4250 4251 4252 4253 4254 4255 4256 4257 4258 4259 4260 4261
static bool
intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
{
	int ret;

	ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
					     DP_SINK_COUNT_ESI,
					     sink_irq_vector, 14);
	if (ret != 14)
		return false;

	return true;
}

4262 4263 4264 4265 4266 4267 4268 4269 4270 4271 4272 4273 4274
static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
{
	uint8_t test_result = DP_TEST_ACK;
	return test_result;
}

static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
{
	uint8_t test_result = DP_TEST_NAK;
	return test_result;
}

static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4275
{
4276
	uint8_t test_result = DP_TEST_NAK;
4277 4278 4279 4280
	struct intel_connector *intel_connector = intel_dp->attached_connector;
	struct drm_connector *connector = &intel_connector->base;

	if (intel_connector->detect_edid == NULL ||
4281
	    connector->edid_corrupt ||
4282 4283 4284 4285 4286 4287 4288 4289 4290 4291 4292 4293 4294 4295 4296
	    intel_dp->aux.i2c_defer_count > 6) {
		/* Check EDID read for NACKs, DEFERs and corruption
		 * (DP CTS 1.2 Core r1.1)
		 *    4.2.2.4 : Failed EDID read, I2C_NAK
		 *    4.2.2.5 : Failed EDID read, I2C_DEFER
		 *    4.2.2.6 : EDID corruption detected
		 * Use failsafe mode for all cases
		 */
		if (intel_dp->aux.i2c_nack_count > 0 ||
			intel_dp->aux.i2c_defer_count > 0)
			DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
				      intel_dp->aux.i2c_nack_count,
				      intel_dp->aux.i2c_defer_count);
		intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
	} else {
4297 4298 4299 4300 4301 4302 4303
		struct edid *block = intel_connector->detect_edid;

		/* We have to write the checksum
		 * of the last block read
		 */
		block += intel_connector->detect_edid->extensions;

4304 4305
		if (!drm_dp_dpcd_write(&intel_dp->aux,
					DP_TEST_EDID_CHECKSUM,
4306
					&block->checksum,
D
Dan Carpenter 已提交
4307
					1))
4308 4309 4310 4311 4312 4313 4314 4315 4316
			DRM_DEBUG_KMS("Failed to write EDID checksum\n");

		test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
		intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
	}

	/* Set test active flag here so userspace doesn't interrupt things */
	intel_dp->compliance_test_active = 1;

4317 4318 4319 4320
	return test_result;
}

static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4321
{
4322 4323 4324 4325 4326 4327 4328 4329 4330 4331
	uint8_t test_result = DP_TEST_NAK;
	return test_result;
}

static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
{
	uint8_t response = DP_TEST_NAK;
	uint8_t rxdata = 0;
	int status = 0;

4332
	intel_dp->compliance_test_active = 0;
4333
	intel_dp->compliance_test_type = 0;
4334 4335
	intel_dp->compliance_test_data = 0;

4336 4337 4338 4339 4340 4341 4342 4343 4344 4345 4346 4347 4348 4349 4350 4351 4352 4353 4354 4355 4356 4357 4358 4359 4360 4361 4362 4363 4364 4365 4366 4367 4368 4369 4370 4371 4372 4373 4374 4375 4376
	intel_dp->aux.i2c_nack_count = 0;
	intel_dp->aux.i2c_defer_count = 0;

	status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
	if (status <= 0) {
		DRM_DEBUG_KMS("Could not read test request from sink\n");
		goto update_status;
	}

	switch (rxdata) {
	case DP_TEST_LINK_TRAINING:
		DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
		intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
		response = intel_dp_autotest_link_training(intel_dp);
		break;
	case DP_TEST_LINK_VIDEO_PATTERN:
		DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
		intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
		response = intel_dp_autotest_video_pattern(intel_dp);
		break;
	case DP_TEST_LINK_EDID_READ:
		DRM_DEBUG_KMS("EDID test requested\n");
		intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
		response = intel_dp_autotest_edid(intel_dp);
		break;
	case DP_TEST_LINK_PHY_TEST_PATTERN:
		DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
		intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
		response = intel_dp_autotest_phy_pattern(intel_dp);
		break;
	default:
		DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
		break;
	}

update_status:
	status = drm_dp_dpcd_write(&intel_dp->aux,
				   DP_TEST_RESPONSE,
				   &response, 1);
	if (status <= 0)
		DRM_DEBUG_KMS("Could not write test response to sink\n");
4377 4378
}

4379 4380 4381 4382 4383 4384 4385 4386 4387 4388 4389 4390 4391 4392 4393
static int
intel_dp_check_mst_status(struct intel_dp *intel_dp)
{
	bool bret;

	if (intel_dp->is_mst) {
		u8 esi[16] = { 0 };
		int ret = 0;
		int retry;
		bool handled;
		bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
go_again:
		if (bret == true) {

			/* check link status - esi[10] = 0x200c */
4394
			if (intel_dp->active_mst_links &&
4395
			    !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4396 4397 4398 4399 4400 4401
				DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
				intel_dp_start_link_train(intel_dp);
				intel_dp_complete_link_train(intel_dp);
				intel_dp_stop_link_train(intel_dp);
			}

4402
			DRM_DEBUG_KMS("got esi %3ph\n", esi);
4403 4404 4405 4406 4407 4408 4409 4410 4411 4412 4413 4414 4415 4416 4417
			ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);

			if (handled) {
				for (retry = 0; retry < 3; retry++) {
					int wret;
					wret = drm_dp_dpcd_write(&intel_dp->aux,
								 DP_SINK_COUNT_ESI+1,
								 &esi[1], 3);
					if (wret == 3) {
						break;
					}
				}

				bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
				if (bret == true) {
4418
					DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4419 4420 4421 4422 4423 4424 4425 4426 4427 4428 4429 4430 4431 4432 4433 4434 4435 4436
					goto go_again;
				}
			} else
				ret = 0;

			return ret;
		} else {
			struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
			DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
			intel_dp->is_mst = false;
			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
			/* send a hotplug event */
			drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
		}
	}
	return -EINVAL;
}

4437 4438 4439 4440 4441 4442 4443 4444
/*
 * According to DP spec
 * 5.1.2:
 *  1. Read DPCD
 *  2. Configure link according to Receiver Capabilities
 *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
 *  4. Check link status on receipt of hot-plug interrupt
 */
4445
static void
C
Chris Wilson 已提交
4446
intel_dp_check_link_status(struct intel_dp *intel_dp)
4447
{
4448
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
4449
	struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4450
	u8 sink_irq_vector;
4451
	u8 link_status[DP_LINK_STATUS_SIZE];
4452

4453 4454
	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));

4455
	if (!intel_encoder->base.crtc)
4456 4457
		return;

4458 4459 4460
	if (!to_intel_crtc(intel_encoder->base.crtc)->active)
		return;

4461
	/* Try to read receiver status if the link appears to be up */
4462
	if (!intel_dp_get_link_status(intel_dp, link_status)) {
4463 4464 4465
		return;
	}

4466
	/* Now read the DPCD to see if it's actually running */
4467
	if (!intel_dp_get_dpcd(intel_dp)) {
4468 4469 4470
		return;
	}

4471 4472 4473 4474
	/* Try to read the source of the interrupt */
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
		/* Clear interrupt source */
4475 4476 4477
		drm_dp_dpcd_writeb(&intel_dp->aux,
				   DP_DEVICE_SERVICE_IRQ_VECTOR,
				   sink_irq_vector);
4478 4479

		if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4480
			DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
4481 4482 4483 4484
		if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
			DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
	}

4485
	if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
4486
		DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4487
			      intel_encoder->base.name);
4488 4489
		intel_dp_start_link_train(intel_dp);
		intel_dp_complete_link_train(intel_dp);
4490
		intel_dp_stop_link_train(intel_dp);
4491
	}
4492 4493
}

4494
/* XXX this is probably wrong for multiple downstream ports */
4495
static enum drm_connector_status
4496
intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4497
{
4498 4499 4500 4501 4502 4503 4504 4505
	uint8_t *dpcd = intel_dp->dpcd;
	uint8_t type;

	if (!intel_dp_get_dpcd(intel_dp))
		return connector_status_disconnected;

	/* if there's no downstream port, we're done */
	if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
4506
		return connector_status_connected;
4507 4508

	/* If we're HPD-aware, SINK_COUNT changes dynamically */
4509 4510
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4511
		uint8_t reg;
4512 4513 4514

		if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
					    &reg, 1) < 0)
4515
			return connector_status_unknown;
4516

4517 4518
		return DP_GET_SINK_COUNT(reg) ? connector_status_connected
					      : connector_status_disconnected;
4519 4520 4521
	}

	/* If no HPD, poke DDC gently */
4522
	if (drm_probe_ddc(&intel_dp->aux.ddc))
4523
		return connector_status_connected;
4524 4525

	/* Well we tried, say unknown for unreliable port types */
4526 4527 4528 4529 4530 4531 4532 4533 4534 4535 4536 4537
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
		type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
		if (type == DP_DS_PORT_TYPE_VGA ||
		    type == DP_DS_PORT_TYPE_NON_EDID)
			return connector_status_unknown;
	} else {
		type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
			DP_DWN_STRM_PORT_TYPE_MASK;
		if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
		    type == DP_DWN_STRM_PORT_TYPE_OTHER)
			return connector_status_unknown;
	}
4538 4539 4540

	/* Anything else is out of spec, warn and ignore */
	DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4541
	return connector_status_disconnected;
4542 4543
}

4544 4545 4546 4547 4548 4549 4550 4551 4552 4553 4554 4555 4556
static enum drm_connector_status
edp_detect(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	enum drm_connector_status status;

	status = intel_panel_detect(dev);
	if (status == connector_status_unknown)
		status = connector_status_connected;

	return status;
}

4557 4558
static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
				       struct intel_digital_port *port)
4559
{
4560
	u32 bit;
4561

4562 4563 4564 4565 4566 4567 4568 4569 4570 4571 4572 4573 4574 4575 4576 4577 4578 4579 4580 4581 4582 4583 4584 4585 4586 4587 4588 4589 4590 4591 4592 4593 4594 4595 4596 4597 4598 4599 4600 4601
	switch (port->port) {
	case PORT_A:
		return true;
	case PORT_B:
		bit = SDE_PORTB_HOTPLUG;
		break;
	case PORT_C:
		bit = SDE_PORTC_HOTPLUG;
		break;
	case PORT_D:
		bit = SDE_PORTD_HOTPLUG;
		break;
	default:
		MISSING_CASE(port->port);
		return false;
	}

	return I915_READ(SDEISR) & bit;
}

static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
				       struct intel_digital_port *port)
{
	u32 bit;

	switch (port->port) {
	case PORT_A:
		return true;
	case PORT_B:
		bit = SDE_PORTB_HOTPLUG_CPT;
		break;
	case PORT_C:
		bit = SDE_PORTC_HOTPLUG_CPT;
		break;
	case PORT_D:
		bit = SDE_PORTD_HOTPLUG_CPT;
		break;
	default:
		MISSING_CASE(port->port);
		return false;
4602
	}
4603

4604
	return I915_READ(SDEISR) & bit;
4605 4606
}

4607
static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
4608
				       struct intel_digital_port *port)
4609
{
4610
	u32 bit;
4611

4612 4613 4614 4615 4616 4617 4618 4619 4620 4621 4622 4623 4624 4625 4626 4627 4628 4629 4630 4631 4632 4633 4634 4635 4636 4637 4638 4639 4640 4641 4642 4643 4644 4645 4646 4647
	switch (port->port) {
	case PORT_B:
		bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
		break;
	case PORT_C:
		bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
		break;
	case PORT_D:
		bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
		break;
	default:
		MISSING_CASE(port->port);
		return false;
	}

	return I915_READ(PORT_HOTPLUG_STAT) & bit;
}

static bool vlv_digital_port_connected(struct drm_i915_private *dev_priv,
				       struct intel_digital_port *port)
{
	u32 bit;

	switch (port->port) {
	case PORT_B:
		bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
		break;
	case PORT_C:
		bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
		break;
	case PORT_D:
		bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
		break;
	default:
		MISSING_CASE(port->port);
		return false;
4648 4649
	}

4650
	return I915_READ(PORT_HOTPLUG_STAT) & bit;
4651 4652
}

4653 4654 4655 4656 4657 4658 4659 4660 4661 4662 4663 4664 4665 4666 4667 4668 4669 4670 4671 4672 4673 4674 4675
static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
				       struct intel_digital_port *port)
{
	u32 bit;

	switch (port->port) {
	case PORT_A:
		bit = BXT_DE_PORT_HP_DDIA;
		break;
	case PORT_B:
		bit = BXT_DE_PORT_HP_DDIB;
		break;
	case PORT_C:
		bit = BXT_DE_PORT_HP_DDIC;
		break;
	default:
		MISSING_CASE(port->port);
		return false;
	}

	return I915_READ(GEN8_DE_PORT_ISR) & bit;
}

4676 4677 4678 4679 4680 4681 4682 4683 4684 4685
/*
 * intel_digital_port_connected - is the specified port connected?
 * @dev_priv: i915 private structure
 * @port: the port to test
 *
 * Return %true if @port is connected, %false otherwise.
 */
static bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
					 struct intel_digital_port *port)
{
4686
	if (HAS_PCH_IBX(dev_priv))
4687
		return ibx_digital_port_connected(dev_priv, port);
4688 4689
	if (HAS_PCH_SPLIT(dev_priv))
		return cpt_digital_port_connected(dev_priv, port);
4690 4691
	else if (IS_BROXTON(dev_priv))
		return bxt_digital_port_connected(dev_priv, port);
4692 4693
	else if (IS_VALLEYVIEW(dev_priv))
		return vlv_digital_port_connected(dev_priv, port);
4694 4695 4696 4697
	else
		return g4x_digital_port_connected(dev_priv, port);
}

4698 4699 4700 4701 4702 4703 4704
static enum drm_connector_status
ironlake_dp_detect(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

4705
	if (!intel_digital_port_connected(dev_priv, intel_dig_port))
4706 4707 4708 4709 4710
		return connector_status_disconnected;

	return intel_dp_detect_dpcd(intel_dp);
}

4711 4712 4713 4714 4715 4716 4717 4718 4719 4720 4721 4722 4723 4724 4725 4726
static enum drm_connector_status
g4x_dp_detect(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	/* Can't disconnect eDP, but you can close the lid... */
	if (is_edp(intel_dp)) {
		enum drm_connector_status status;

		status = intel_panel_detect(dev);
		if (status == connector_status_unknown)
			status = connector_status_connected;
		return status;
	}

4727
	if (!intel_digital_port_connected(dev->dev_private, intel_dig_port))
4728 4729
		return connector_status_disconnected;

4730
	return intel_dp_detect_dpcd(intel_dp);
Z
Zhenyu Wang 已提交
4731 4732
}

4733
static struct edid *
4734
intel_dp_get_edid(struct intel_dp *intel_dp)
4735
{
4736
	struct intel_connector *intel_connector = intel_dp->attached_connector;
4737

4738 4739 4740 4741
	/* use cached edid if we have one */
	if (intel_connector->edid) {
		/* invalid edid */
		if (IS_ERR(intel_connector->edid))
4742 4743
			return NULL;

J
Jani Nikula 已提交
4744
		return drm_edid_duplicate(intel_connector->edid);
4745 4746 4747 4748
	} else
		return drm_get_edid(&intel_connector->base,
				    &intel_dp->aux.ddc);
}
4749

4750 4751 4752 4753 4754
static void
intel_dp_set_edid(struct intel_dp *intel_dp)
{
	struct intel_connector *intel_connector = intel_dp->attached_connector;
	struct edid *edid;
4755

4756 4757 4758 4759 4760 4761 4762
	edid = intel_dp_get_edid(intel_dp);
	intel_connector->detect_edid = edid;

	if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
		intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
	else
		intel_dp->has_audio = drm_detect_monitor_audio(edid);
4763 4764
}

4765 4766
static void
intel_dp_unset_edid(struct intel_dp *intel_dp)
4767
{
4768
	struct intel_connector *intel_connector = intel_dp->attached_connector;
4769

4770 4771
	kfree(intel_connector->detect_edid);
	intel_connector->detect_edid = NULL;
4772

4773 4774
	intel_dp->has_audio = false;
}
4775

4776 4777 4778 4779 4780 4781 4782 4783 4784 4785 4786
static enum intel_display_power_domain
intel_dp_power_get(struct intel_dp *dp)
{
	struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
	enum intel_display_power_domain power_domain;

	power_domain = intel_display_port_power_domain(encoder);
	intel_display_power_get(to_i915(encoder->base.dev), power_domain);

	return power_domain;
}
4787

4788 4789 4790 4791 4792 4793
static void
intel_dp_power_put(struct intel_dp *dp,
		   enum intel_display_power_domain power_domain)
{
	struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
	intel_display_power_put(to_i915(encoder->base.dev), power_domain);
4794 4795
}

Z
Zhenyu Wang 已提交
4796 4797 4798 4799
static enum drm_connector_status
intel_dp_detect(struct drm_connector *connector, bool force)
{
	struct intel_dp *intel_dp = intel_attached_dp(connector);
4800 4801
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
4802
	struct drm_device *dev = connector->dev;
Z
Zhenyu Wang 已提交
4803
	enum drm_connector_status status;
4804
	enum intel_display_power_domain power_domain;
4805
	bool ret;
4806
	u8 sink_irq_vector;
Z
Zhenyu Wang 已提交
4807

4808
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4809
		      connector->base.id, connector->name);
4810
	intel_dp_unset_edid(intel_dp);
4811

4812 4813 4814 4815
	if (intel_dp->is_mst) {
		/* MST devices are disconnected from a monitor POV */
		if (intel_encoder->type != INTEL_OUTPUT_EDP)
			intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4816
		return connector_status_disconnected;
4817 4818
	}

4819
	power_domain = intel_dp_power_get(intel_dp);
Z
Zhenyu Wang 已提交
4820

4821 4822 4823 4824
	/* Can't disconnect eDP, but you can close the lid... */
	if (is_edp(intel_dp))
		status = edp_detect(intel_dp);
	else if (HAS_PCH_SPLIT(dev))
Z
Zhenyu Wang 已提交
4825 4826 4827 4828
		status = ironlake_dp_detect(intel_dp);
	else
		status = g4x_dp_detect(intel_dp);
	if (status != connector_status_connected)
4829
		goto out;
Z
Zhenyu Wang 已提交
4830

4831 4832
	intel_dp_probe_oui(intel_dp);

4833 4834 4835 4836 4837 4838 4839 4840 4841 4842
	ret = intel_dp_probe_mst(intel_dp);
	if (ret) {
		/* if we are in MST mode then this connector
		   won't appear connected or have anything with EDID on it */
		if (intel_encoder->type != INTEL_OUTPUT_EDP)
			intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
		status = connector_status_disconnected;
		goto out;
	}

4843
	intel_dp_set_edid(intel_dp);
Z
Zhenyu Wang 已提交
4844

4845 4846
	if (intel_encoder->type != INTEL_OUTPUT_EDP)
		intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4847 4848
	status = connector_status_connected;

4849 4850 4851 4852 4853 4854 4855 4856 4857 4858 4859 4860 4861 4862
	/* Try to read the source of the interrupt */
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
		/* Clear interrupt source */
		drm_dp_dpcd_writeb(&intel_dp->aux,
				   DP_DEVICE_SERVICE_IRQ_VECTOR,
				   sink_irq_vector);

		if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
			intel_dp_handle_test_request(intel_dp);
		if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
			DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
	}

4863
out:
4864
	intel_dp_power_put(intel_dp, power_domain);
4865
	return status;
4866 4867
}

4868 4869
static void
intel_dp_force(struct drm_connector *connector)
4870
{
4871
	struct intel_dp *intel_dp = intel_attached_dp(connector);
4872
	struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4873
	enum intel_display_power_domain power_domain;
4874

4875 4876 4877
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
		      connector->base.id, connector->name);
	intel_dp_unset_edid(intel_dp);
4878

4879 4880
	if (connector->status != connector_status_connected)
		return;
4881

4882 4883 4884 4885 4886 4887 4888 4889 4890 4891 4892 4893 4894 4895 4896 4897 4898 4899 4900 4901 4902
	power_domain = intel_dp_power_get(intel_dp);

	intel_dp_set_edid(intel_dp);

	intel_dp_power_put(intel_dp, power_domain);

	if (intel_encoder->type != INTEL_OUTPUT_EDP)
		intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
}

static int intel_dp_get_modes(struct drm_connector *connector)
{
	struct intel_connector *intel_connector = to_intel_connector(connector);
	struct edid *edid;

	edid = intel_connector->detect_edid;
	if (edid) {
		int ret = intel_connector_update_modes(connector, edid);
		if (ret)
			return ret;
	}
4903

4904
	/* if eDP has no EDID, fall back to fixed mode */
4905 4906
	if (is_edp(intel_attached_dp(connector)) &&
	    intel_connector->panel.fixed_mode) {
4907
		struct drm_display_mode *mode;
4908 4909

		mode = drm_mode_duplicate(connector->dev,
4910
					  intel_connector->panel.fixed_mode);
4911
		if (mode) {
4912 4913 4914 4915
			drm_mode_probed_add(connector, mode);
			return 1;
		}
	}
4916

4917
	return 0;
4918 4919
}

4920 4921 4922 4923
static bool
intel_dp_detect_audio(struct drm_connector *connector)
{
	bool has_audio = false;
4924
	struct edid *edid;
4925

4926 4927
	edid = to_intel_connector(connector)->detect_edid;
	if (edid)
4928
		has_audio = drm_detect_monitor_audio(edid);
4929

4930 4931 4932
	return has_audio;
}

4933 4934 4935 4936 4937
static int
intel_dp_set_property(struct drm_connector *connector,
		      struct drm_property *property,
		      uint64_t val)
{
4938
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
4939
	struct intel_connector *intel_connector = to_intel_connector(connector);
4940 4941
	struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4942 4943
	int ret;

4944
	ret = drm_object_property_set_value(&connector->base, property, val);
4945 4946 4947
	if (ret)
		return ret;

4948
	if (property == dev_priv->force_audio_property) {
4949 4950 4951 4952
		int i = val;
		bool has_audio;

		if (i == intel_dp->force_audio)
4953 4954
			return 0;

4955
		intel_dp->force_audio = i;
4956

4957
		if (i == HDMI_AUDIO_AUTO)
4958 4959
			has_audio = intel_dp_detect_audio(connector);
		else
4960
			has_audio = (i == HDMI_AUDIO_ON);
4961 4962

		if (has_audio == intel_dp->has_audio)
4963 4964
			return 0;

4965
		intel_dp->has_audio = has_audio;
4966 4967 4968
		goto done;
	}

4969
	if (property == dev_priv->broadcast_rgb_property) {
4970
		bool old_auto = intel_dp->color_range_auto;
4971
		bool old_range = intel_dp->limited_color_range;
4972

4973 4974 4975 4976 4977 4978
		switch (val) {
		case INTEL_BROADCAST_RGB_AUTO:
			intel_dp->color_range_auto = true;
			break;
		case INTEL_BROADCAST_RGB_FULL:
			intel_dp->color_range_auto = false;
4979
			intel_dp->limited_color_range = false;
4980 4981 4982
			break;
		case INTEL_BROADCAST_RGB_LIMITED:
			intel_dp->color_range_auto = false;
4983
			intel_dp->limited_color_range = true;
4984 4985 4986 4987
			break;
		default:
			return -EINVAL;
		}
4988 4989

		if (old_auto == intel_dp->color_range_auto &&
4990
		    old_range == intel_dp->limited_color_range)
4991 4992
			return 0;

4993 4994 4995
		goto done;
	}

4996 4997 4998 4999 5000 5001 5002 5003 5004 5005 5006 5007 5008 5009 5010 5011
	if (is_edp(intel_dp) &&
	    property == connector->dev->mode_config.scaling_mode_property) {
		if (val == DRM_MODE_SCALE_NONE) {
			DRM_DEBUG_KMS("no scaling not supported\n");
			return -EINVAL;
		}

		if (intel_connector->panel.fitting_mode == val) {
			/* the eDP scaling property is not changed */
			return 0;
		}
		intel_connector->panel.fitting_mode = val;

		goto done;
	}

5012 5013 5014
	return -EINVAL;

done:
5015 5016
	if (intel_encoder->base.crtc)
		intel_crtc_restore_mode(intel_encoder->base.crtc);
5017 5018 5019 5020

	return 0;
}

5021
static void
5022
intel_dp_connector_destroy(struct drm_connector *connector)
5023
{
5024
	struct intel_connector *intel_connector = to_intel_connector(connector);
5025

5026
	kfree(intel_connector->detect_edid);
5027

5028 5029 5030
	if (!IS_ERR_OR_NULL(intel_connector->edid))
		kfree(intel_connector->edid);

5031 5032 5033
	/* Can't call is_edp() since the encoder may have been destroyed
	 * already. */
	if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5034
		intel_panel_fini(&intel_connector->panel);
5035

5036
	drm_connector_cleanup(connector);
5037
	kfree(connector);
5038 5039
}

P
Paulo Zanoni 已提交
5040
void intel_dp_encoder_destroy(struct drm_encoder *encoder)
5041
{
5042 5043
	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
	struct intel_dp *intel_dp = &intel_dig_port->dp;
5044

5045
	drm_dp_aux_unregister(&intel_dp->aux);
5046
	intel_dp_mst_encoder_cleanup(intel_dig_port);
5047 5048
	if (is_edp(intel_dp)) {
		cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5049 5050 5051 5052
		/*
		 * vdd might still be enabled do to the delayed vdd off.
		 * Make sure vdd is actually turned off here.
		 */
5053
		pps_lock(intel_dp);
5054
		edp_panel_vdd_off_sync(intel_dp);
5055 5056
		pps_unlock(intel_dp);

5057 5058 5059 5060
		if (intel_dp->edp_notifier.notifier_call) {
			unregister_reboot_notifier(&intel_dp->edp_notifier);
			intel_dp->edp_notifier.notifier_call = NULL;
		}
5061
	}
5062
	drm_encoder_cleanup(encoder);
5063
	kfree(intel_dig_port);
5064 5065
}

5066 5067 5068 5069 5070 5071 5072
static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);

	if (!is_edp(intel_dp))
		return;

5073 5074 5075 5076
	/*
	 * vdd might still be enabled do to the delayed vdd off.
	 * Make sure vdd is actually turned off here.
	 */
5077
	cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5078
	pps_lock(intel_dp);
5079
	edp_panel_vdd_off_sync(intel_dp);
5080
	pps_unlock(intel_dp);
5081 5082
}

5083 5084 5085 5086 5087 5088 5089 5090 5091 5092 5093 5094 5095 5096 5097 5098 5099 5100 5101 5102 5103 5104 5105 5106 5107
static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum intel_display_power_domain power_domain;

	lockdep_assert_held(&dev_priv->pps_mutex);

	if (!edp_have_panel_vdd(intel_dp))
		return;

	/*
	 * The VDD bit needs a power domain reference, so if the bit is
	 * already enabled when we boot or resume, grab this reference and
	 * schedule a vdd off, so we don't hold on to the reference
	 * indefinitely.
	 */
	DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
	power_domain = intel_display_port_power_domain(&intel_dig_port->base);
	intel_display_power_get(dev_priv, power_domain);

	edp_panel_vdd_schedule_off(intel_dp);
}

5108 5109
static void intel_dp_encoder_reset(struct drm_encoder *encoder)
{
5110 5111 5112 5113 5114 5115 5116 5117 5118 5119 5120 5121 5122 5123 5124 5125 5126 5127 5128
	struct intel_dp *intel_dp;

	if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
		return;

	intel_dp = enc_to_intel_dp(encoder);

	pps_lock(intel_dp);

	/*
	 * Read out the current power sequencer assignment,
	 * in case the BIOS did something with it.
	 */
	if (IS_VALLEYVIEW(encoder->dev))
		vlv_initial_power_sequencer_setup(intel_dp);

	intel_edp_panel_vdd_sanitize(intel_dp);

	pps_unlock(intel_dp);
5129 5130
}

5131
static const struct drm_connector_funcs intel_dp_connector_funcs = {
5132
	.dpms = drm_atomic_helper_connector_dpms,
5133
	.detect = intel_dp_detect,
5134
	.force = intel_dp_force,
5135
	.fill_modes = drm_helper_probe_single_connector_modes,
5136
	.set_property = intel_dp_set_property,
5137
	.atomic_get_property = intel_connector_atomic_get_property,
5138
	.destroy = intel_dp_connector_destroy,
5139
	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5140
	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
5141 5142 5143 5144 5145
};

static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
	.get_modes = intel_dp_get_modes,
	.mode_valid = intel_dp_mode_valid,
5146
	.best_encoder = intel_best_encoder,
5147 5148 5149
};

static const struct drm_encoder_funcs intel_dp_enc_funcs = {
5150
	.reset = intel_dp_encoder_reset,
5151
	.destroy = intel_dp_encoder_destroy,
5152 5153
};

5154
enum irqreturn
5155 5156 5157
intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
{
	struct intel_dp *intel_dp = &intel_dig_port->dp;
5158
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
5159 5160
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
5161
	enum intel_display_power_domain power_domain;
5162
	enum irqreturn ret = IRQ_NONE;
5163

5164 5165
	if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
		intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
5166

5167 5168 5169 5170 5171 5172 5173 5174 5175
	if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
		/*
		 * vdd off can generate a long pulse on eDP which
		 * would require vdd on to handle it, and thus we
		 * would end up in an endless cycle of
		 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
		 */
		DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
			      port_name(intel_dig_port->port));
5176
		return IRQ_HANDLED;
5177 5178
	}

5179 5180
	DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
		      port_name(intel_dig_port->port),
5181
		      long_hpd ? "long" : "short");
5182

5183 5184 5185
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_get(dev_priv, power_domain);

5186
	if (long_hpd) {
5187 5188
		/* indicate that we need to restart link training */
		intel_dp->train_set_valid = false;
5189

5190 5191
		if (!intel_digital_port_connected(dev_priv, intel_dig_port))
			goto mst_fail;
5192 5193 5194 5195 5196 5197 5198 5199 5200 5201 5202 5203

		if (!intel_dp_get_dpcd(intel_dp)) {
			goto mst_fail;
		}

		intel_dp_probe_oui(intel_dp);

		if (!intel_dp_probe_mst(intel_dp))
			goto mst_fail;

	} else {
		if (intel_dp->is_mst) {
5204
			if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
5205 5206 5207 5208 5209 5210 5211 5212
				goto mst_fail;
		}

		if (!intel_dp->is_mst) {
			/*
			 * we'll check the link status via the normal hot plug path later -
			 * but for short hpds we should check it now
			 */
5213
			drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
5214
			intel_dp_check_link_status(intel_dp);
5215
			drm_modeset_unlock(&dev->mode_config.connection_mutex);
5216 5217
		}
	}
5218 5219 5220

	ret = IRQ_HANDLED;

5221
	goto put_power;
5222 5223 5224 5225 5226 5227 5228
mst_fail:
	/* if we were in MST mode, and device is not there get out of MST mode */
	if (intel_dp->is_mst) {
		DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
		intel_dp->is_mst = false;
		drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
	}
5229 5230 5231 5232
put_power:
	intel_display_power_put(dev_priv, power_domain);

	return ret;
5233 5234
}

5235 5236
/* Return which DP Port should be selected for Transcoder DP control */
int
5237
intel_trans_dp_port_sel(struct drm_crtc *crtc)
5238 5239
{
	struct drm_device *dev = crtc->dev;
5240 5241
	struct intel_encoder *intel_encoder;
	struct intel_dp *intel_dp;
5242

5243 5244
	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		intel_dp = enc_to_intel_dp(&intel_encoder->base);
5245

5246 5247
		if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
		    intel_encoder->type == INTEL_OUTPUT_EDP)
C
Chris Wilson 已提交
5248
			return intel_dp->output_reg;
5249
	}
C
Chris Wilson 已提交
5250

5251 5252 5253
	return -1;
}

5254
/* check the VBT to see whether the eDP is on DP-D port */
5255
bool intel_dp_is_edp(struct drm_device *dev, enum port port)
5256 5257
{
	struct drm_i915_private *dev_priv = dev->dev_private;
5258
	union child_device_config *p_child;
5259
	int i;
5260 5261 5262 5263 5264
	static const short port_mapping[] = {
		[PORT_B] = PORT_IDPB,
		[PORT_C] = PORT_IDPC,
		[PORT_D] = PORT_IDPD,
	};
5265

5266 5267 5268
	if (port == PORT_A)
		return true;

5269
	if (!dev_priv->vbt.child_dev_num)
5270 5271
		return false;

5272 5273
	for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
		p_child = dev_priv->vbt.child_dev + i;
5274

5275
		if (p_child->common.dvo_port == port_mapping[port] &&
5276 5277
		    (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
		    (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
5278 5279 5280 5281 5282
			return true;
	}
	return false;
}

5283
void
5284 5285
intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
{
5286 5287
	struct intel_connector *intel_connector = to_intel_connector(connector);

5288
	intel_attach_force_audio_property(connector);
5289
	intel_attach_broadcast_rgb_property(connector);
5290
	intel_dp->color_range_auto = true;
5291 5292 5293

	if (is_edp(intel_dp)) {
		drm_mode_create_scaling_mode_property(connector->dev);
5294 5295
		drm_object_attach_property(
			&connector->base,
5296
			connector->dev->mode_config.scaling_mode_property,
5297 5298
			DRM_MODE_SCALE_ASPECT);
		intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
5299
	}
5300 5301
}

5302 5303 5304 5305 5306 5307 5308
static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
{
	intel_dp->last_power_cycle = jiffies;
	intel_dp->last_power_on = jiffies;
	intel_dp->last_backlight_off = jiffies;
}

5309 5310
static void
intel_dp_init_panel_power_sequencer(struct drm_device *dev,
5311
				    struct intel_dp *intel_dp)
5312 5313
{
	struct drm_i915_private *dev_priv = dev->dev_private;
5314 5315
	struct edp_power_seq cur, vbt, spec,
		*final = &intel_dp->pps_delays;
5316 5317
	u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
	int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg = 0;
5318

V
Ville Syrjälä 已提交
5319 5320
	lockdep_assert_held(&dev_priv->pps_mutex);

5321 5322 5323 5324
	/* already initialized? */
	if (final->t11_t12 != 0)
		return;

5325 5326 5327 5328 5329 5330 5331 5332 5333 5334
	if (IS_BROXTON(dev)) {
		/*
		 * TODO: BXT has 2 sets of PPS registers.
		 * Correct Register for Broxton need to be identified
		 * using VBT. hardcoding for now
		 */
		pp_ctrl_reg = BXT_PP_CONTROL(0);
		pp_on_reg = BXT_PP_ON_DELAYS(0);
		pp_off_reg = BXT_PP_OFF_DELAYS(0);
	} else if (HAS_PCH_SPLIT(dev)) {
5335
		pp_ctrl_reg = PCH_PP_CONTROL;
5336 5337 5338 5339
		pp_on_reg = PCH_PP_ON_DELAYS;
		pp_off_reg = PCH_PP_OFF_DELAYS;
		pp_div_reg = PCH_PP_DIVISOR;
	} else {
5340 5341 5342 5343 5344 5345
		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);

		pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
		pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
		pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
		pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
5346
	}
5347 5348 5349

	/* Workaround: Need to write PP_CONTROL with the unlock key as
	 * the very first thing. */
5350
	pp_ctl = ironlake_get_pp_control(intel_dp);
5351

5352 5353
	pp_on = I915_READ(pp_on_reg);
	pp_off = I915_READ(pp_off_reg);
5354 5355 5356 5357
	if (!IS_BROXTON(dev)) {
		I915_WRITE(pp_ctrl_reg, pp_ctl);
		pp_div = I915_READ(pp_div_reg);
	}
5358 5359 5360 5361 5362 5363 5364 5365 5366 5367 5368 5369 5370 5371

	/* Pull timing values out of registers */
	cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
		PANEL_POWER_UP_DELAY_SHIFT;

	cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
		PANEL_LIGHT_ON_DELAY_SHIFT;

	cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
		PANEL_LIGHT_OFF_DELAY_SHIFT;

	cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
		PANEL_POWER_DOWN_DELAY_SHIFT;

5372 5373 5374 5375 5376 5377 5378 5379 5380
	if (IS_BROXTON(dev)) {
		u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
			BXT_POWER_CYCLE_DELAY_SHIFT;
		if (tmp > 0)
			cur.t11_t12 = (tmp - 1) * 1000;
		else
			cur.t11_t12 = 0;
	} else {
		cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5381
		       PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5382
	}
5383 5384 5385 5386

	DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		      cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);

5387
	vbt = dev_priv->vbt.edp_pps;
5388 5389 5390 5391 5392 5393 5394 5395 5396 5397 5398 5399 5400 5401 5402 5403 5404 5405

	/* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
	 * our hw here, which are all in 100usec. */
	spec.t1_t3 = 210 * 10;
	spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
	spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
	spec.t10 = 500 * 10;
	/* This one is special and actually in units of 100ms, but zero
	 * based in the hw (so we need to add 100 ms). But the sw vbt
	 * table multiplies it with 1000 to make it in units of 100usec,
	 * too. */
	spec.t11_t12 = (510 + 100) * 10;

	DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		      vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);

	/* Use the max of the register settings and vbt. If both are
	 * unset, fall back to the spec limits. */
5406
#define assign_final(field)	final->field = (max(cur.field, vbt.field) == 0 ? \
5407 5408 5409 5410 5411 5412 5413 5414 5415
				       spec.field : \
				       max(cur.field, vbt.field))
	assign_final(t1_t3);
	assign_final(t8);
	assign_final(t9);
	assign_final(t10);
	assign_final(t11_t12);
#undef assign_final

5416
#define get_delay(field)	(DIV_ROUND_UP(final->field, 10))
5417 5418 5419 5420 5421 5422 5423
	intel_dp->panel_power_up_delay = get_delay(t1_t3);
	intel_dp->backlight_on_delay = get_delay(t8);
	intel_dp->backlight_off_delay = get_delay(t9);
	intel_dp->panel_power_down_delay = get_delay(t10);
	intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
#undef get_delay

5424 5425 5426 5427 5428 5429 5430 5431 5432 5433
	DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
		      intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
		      intel_dp->panel_power_cycle_delay);

	DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
		      intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
}

static void
intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
5434
					      struct intel_dp *intel_dp)
5435 5436
{
	struct drm_i915_private *dev_priv = dev->dev_private;
5437 5438
	u32 pp_on, pp_off, pp_div, port_sel = 0;
	int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
5439
	int pp_on_reg, pp_off_reg, pp_div_reg = 0, pp_ctrl_reg;
5440
	enum port port = dp_to_dig_port(intel_dp)->port;
5441
	const struct edp_power_seq *seq = &intel_dp->pps_delays;
5442

V
Ville Syrjälä 已提交
5443
	lockdep_assert_held(&dev_priv->pps_mutex);
5444

5445 5446 5447 5448 5449 5450 5451 5452 5453 5454 5455
	if (IS_BROXTON(dev)) {
		/*
		 * TODO: BXT has 2 sets of PPS registers.
		 * Correct Register for Broxton need to be identified
		 * using VBT. hardcoding for now
		 */
		pp_ctrl_reg = BXT_PP_CONTROL(0);
		pp_on_reg = BXT_PP_ON_DELAYS(0);
		pp_off_reg = BXT_PP_OFF_DELAYS(0);

	} else if (HAS_PCH_SPLIT(dev)) {
5456 5457 5458 5459
		pp_on_reg = PCH_PP_ON_DELAYS;
		pp_off_reg = PCH_PP_OFF_DELAYS;
		pp_div_reg = PCH_PP_DIVISOR;
	} else {
5460 5461 5462 5463 5464
		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);

		pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
		pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
		pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
5465 5466
	}

5467 5468 5469 5470 5471 5472 5473 5474
	/*
	 * And finally store the new values in the power sequencer. The
	 * backlight delays are set to 1 because we do manual waits on them. For
	 * T8, even BSpec recommends doing it. For T9, if we don't do this,
	 * we'll end up waiting for the backlight off delay twice: once when we
	 * do the manual sleep, and once when we disable the panel and wait for
	 * the PP_STATUS bit to become zero.
	 */
5475
	pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5476 5477
		(1 << PANEL_LIGHT_ON_DELAY_SHIFT);
	pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5478
		 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5479 5480
	/* Compute the divisor for the pp clock, simply match the Bspec
	 * formula. */
5481 5482 5483 5484 5485 5486 5487 5488 5489 5490
	if (IS_BROXTON(dev)) {
		pp_div = I915_READ(pp_ctrl_reg);
		pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
		pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
				<< BXT_POWER_CYCLE_DELAY_SHIFT);
	} else {
		pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
		pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
				<< PANEL_POWER_CYCLE_DELAY_SHIFT);
	}
5491 5492 5493

	/* Haswell doesn't have any port selection bits for the panel
	 * power sequencer any more. */
5494
	if (IS_VALLEYVIEW(dev)) {
5495
		port_sel = PANEL_PORT_SELECT_VLV(port);
5496
	} else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5497
		if (port == PORT_A)
5498
			port_sel = PANEL_PORT_SELECT_DPA;
5499
		else
5500
			port_sel = PANEL_PORT_SELECT_DPD;
5501 5502
	}

5503 5504 5505 5506
	pp_on |= port_sel;

	I915_WRITE(pp_on_reg, pp_on);
	I915_WRITE(pp_off_reg, pp_off);
5507 5508 5509 5510
	if (IS_BROXTON(dev))
		I915_WRITE(pp_ctrl_reg, pp_div);
	else
		I915_WRITE(pp_div_reg, pp_div);
5511 5512

	DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5513 5514
		      I915_READ(pp_on_reg),
		      I915_READ(pp_off_reg),
5515 5516
		      IS_BROXTON(dev) ?
		      (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) :
5517
		      I915_READ(pp_div_reg));
5518 5519
}

5520 5521 5522 5523 5524 5525 5526 5527 5528 5529 5530 5531
/**
 * intel_dp_set_drrs_state - program registers for RR switch to take effect
 * @dev: DRM device
 * @refresh_rate: RR to be programmed
 *
 * This function gets called when refresh rate (RR) has to be changed from
 * one frequency to another. Switches can be between high and low RR
 * supported by the panel or to any other RR based on media playback (in
 * this case, RR value needs to be passed from user space).
 *
 * The caller of this function needs to take a lock on dev_priv->drrs.
 */
5532
static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
5533 5534 5535
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_encoder *encoder;
5536 5537
	struct intel_digital_port *dig_port = NULL;
	struct intel_dp *intel_dp = dev_priv->drrs.dp;
5538
	struct intel_crtc_state *config = NULL;
5539 5540
	struct intel_crtc *intel_crtc = NULL;
	u32 reg, val;
5541
	enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5542 5543 5544 5545 5546 5547

	if (refresh_rate <= 0) {
		DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
		return;
	}

5548 5549
	if (intel_dp == NULL) {
		DRM_DEBUG_KMS("DRRS not supported.\n");
5550 5551 5552
		return;
	}

5553
	/*
5554 5555
	 * FIXME: This needs proper synchronization with psr state for some
	 * platforms that cannot have PSR and DRRS enabled at the same time.
5556
	 */
5557

5558 5559
	dig_port = dp_to_dig_port(intel_dp);
	encoder = &dig_port->base;
5560
	intel_crtc = to_intel_crtc(encoder->base.crtc);
5561 5562 5563 5564 5565 5566

	if (!intel_crtc) {
		DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
		return;
	}

5567
	config = intel_crtc->config;
5568

5569
	if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5570 5571 5572 5573
		DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
		return;
	}

5574 5575
	if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
			refresh_rate)
5576 5577
		index = DRRS_LOW_RR;

5578
	if (index == dev_priv->drrs.refresh_rate_type) {
5579 5580 5581 5582 5583 5584 5585 5586 5587 5588
		DRM_DEBUG_KMS(
			"DRRS requested for previously set RR...ignoring\n");
		return;
	}

	if (!intel_crtc->active) {
		DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
		return;
	}

D
Durgadoss R 已提交
5589
	if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
5590 5591 5592 5593 5594 5595 5596 5597 5598 5599 5600 5601
		switch (index) {
		case DRRS_HIGH_RR:
			intel_dp_set_m_n(intel_crtc, M1_N1);
			break;
		case DRRS_LOW_RR:
			intel_dp_set_m_n(intel_crtc, M2_N2);
			break;
		case DRRS_MAX_RR:
		default:
			DRM_ERROR("Unsupported refreshrate type\n");
		}
	} else if (INTEL_INFO(dev)->gen > 6) {
5602
		reg = PIPECONF(intel_crtc->config->cpu_transcoder);
5603
		val = I915_READ(reg);
5604

5605
		if (index > DRRS_HIGH_RR) {
5606 5607 5608 5609
			if (IS_VALLEYVIEW(dev))
				val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
			else
				val |= PIPECONF_EDP_RR_MODE_SWITCH;
5610
		} else {
5611 5612 5613 5614
			if (IS_VALLEYVIEW(dev))
				val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
			else
				val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5615 5616 5617 5618
		}
		I915_WRITE(reg, val);
	}

5619 5620 5621 5622 5623
	dev_priv->drrs.refresh_rate_type = index;

	DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
}

5624 5625 5626 5627 5628 5629
/**
 * intel_edp_drrs_enable - init drrs struct if supported
 * @intel_dp: DP struct
 *
 * Initializes frontbuffer_bits and drrs.dp
 */
V
Vandana Kannan 已提交
5630 5631 5632 5633 5634 5635 5636 5637 5638 5639 5640 5641 5642 5643 5644 5645 5646 5647 5648 5649 5650 5651 5652 5653 5654 5655 5656
void intel_edp_drrs_enable(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = dig_port->base.base.crtc;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	if (!intel_crtc->config->has_drrs) {
		DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
		return;
	}

	mutex_lock(&dev_priv->drrs.mutex);
	if (WARN_ON(dev_priv->drrs.dp)) {
		DRM_ERROR("DRRS already enabled\n");
		goto unlock;
	}

	dev_priv->drrs.busy_frontbuffer_bits = 0;

	dev_priv->drrs.dp = intel_dp;

unlock:
	mutex_unlock(&dev_priv->drrs.mutex);
}

5657 5658 5659 5660 5661
/**
 * intel_edp_drrs_disable - Disable DRRS
 * @intel_dp: DP struct
 *
 */
V
Vandana Kannan 已提交
5662 5663 5664 5665 5666 5667 5668 5669 5670 5671 5672 5673 5674 5675 5676 5677 5678 5679 5680 5681 5682 5683 5684 5685 5686 5687 5688 5689
void intel_edp_drrs_disable(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = dig_port->base.base.crtc;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	if (!intel_crtc->config->has_drrs)
		return;

	mutex_lock(&dev_priv->drrs.mutex);
	if (!dev_priv->drrs.dp) {
		mutex_unlock(&dev_priv->drrs.mutex);
		return;
	}

	if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
		intel_dp_set_drrs_state(dev_priv->dev,
			intel_dp->attached_connector->panel.
			fixed_mode->vrefresh);

	dev_priv->drrs.dp = NULL;
	mutex_unlock(&dev_priv->drrs.mutex);

	cancel_delayed_work_sync(&dev_priv->drrs.work);
}

5690 5691 5692 5693 5694 5695 5696 5697 5698 5699 5700 5701 5702
static void intel_edp_drrs_downclock_work(struct work_struct *work)
{
	struct drm_i915_private *dev_priv =
		container_of(work, typeof(*dev_priv), drrs.work.work);
	struct intel_dp *intel_dp;

	mutex_lock(&dev_priv->drrs.mutex);

	intel_dp = dev_priv->drrs.dp;

	if (!intel_dp)
		goto unlock;

5703
	/*
5704 5705
	 * The delayed work can race with an invalidate hence we need to
	 * recheck.
5706 5707
	 */

5708 5709
	if (dev_priv->drrs.busy_frontbuffer_bits)
		goto unlock;
5710

5711 5712 5713 5714
	if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
		intel_dp_set_drrs_state(dev_priv->dev,
			intel_dp->attached_connector->panel.
			downclock_mode->vrefresh);
5715

5716 5717
unlock:
	mutex_unlock(&dev_priv->drrs.mutex);
5718 5719
}

5720
/**
5721
 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5722 5723 5724
 * @dev: DRM device
 * @frontbuffer_bits: frontbuffer plane tracking bits
 *
5725 5726
 * This function gets called everytime rendering on the given planes start.
 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5727 5728 5729
 *
 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
 */
5730 5731 5732 5733 5734 5735 5736
void intel_edp_drrs_invalidate(struct drm_device *dev,
		unsigned frontbuffer_bits)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc;
	enum pipe pipe;

5737
	if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5738 5739
		return;

5740
	cancel_delayed_work(&dev_priv->drrs.work);
5741

5742
	mutex_lock(&dev_priv->drrs.mutex);
5743 5744 5745 5746 5747
	if (!dev_priv->drrs.dp) {
		mutex_unlock(&dev_priv->drrs.mutex);
		return;
	}

5748 5749 5750
	crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
	pipe = to_intel_crtc(crtc)->pipe;

5751 5752 5753
	frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
	dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;

5754
	/* invalidate means busy screen hence upclock */
5755
	if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5756 5757 5758 5759 5760 5761 5762
		intel_dp_set_drrs_state(dev_priv->dev,
				dev_priv->drrs.dp->attached_connector->panel.
				fixed_mode->vrefresh);

	mutex_unlock(&dev_priv->drrs.mutex);
}

5763
/**
5764
 * intel_edp_drrs_flush - Restart Idleness DRRS
5765 5766 5767
 * @dev: DRM device
 * @frontbuffer_bits: frontbuffer plane tracking bits
 *
5768 5769 5770 5771
 * This function gets called every time rendering on the given planes has
 * completed or flip on a crtc is completed. So DRRS should be upclocked
 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
 * if no other planes are dirty.
5772 5773 5774
 *
 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
 */
5775 5776 5777 5778 5779 5780 5781
void intel_edp_drrs_flush(struct drm_device *dev,
		unsigned frontbuffer_bits)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc;
	enum pipe pipe;

5782
	if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5783 5784
		return;

5785
	cancel_delayed_work(&dev_priv->drrs.work);
5786

5787
	mutex_lock(&dev_priv->drrs.mutex);
5788 5789 5790 5791 5792
	if (!dev_priv->drrs.dp) {
		mutex_unlock(&dev_priv->drrs.mutex);
		return;
	}

5793 5794
	crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
	pipe = to_intel_crtc(crtc)->pipe;
5795 5796

	frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5797 5798
	dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;

5799
	/* flush means busy screen hence upclock */
5800
	if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5801 5802 5803 5804 5805 5806 5807 5808 5809
		intel_dp_set_drrs_state(dev_priv->dev,
				dev_priv->drrs.dp->attached_connector->panel.
				fixed_mode->vrefresh);

	/*
	 * flush also means no more activity hence schedule downclock, if all
	 * other fbs are quiescent too
	 */
	if (!dev_priv->drrs.busy_frontbuffer_bits)
5810 5811 5812 5813 5814
		schedule_delayed_work(&dev_priv->drrs.work,
				msecs_to_jiffies(1000));
	mutex_unlock(&dev_priv->drrs.mutex);
}

5815 5816 5817 5818 5819 5820 5821 5822 5823 5824 5825 5826 5827 5828 5829 5830 5831 5832 5833 5834 5835 5836 5837 5838 5839 5840 5841 5842 5843 5844 5845 5846 5847 5848 5849 5850 5851 5852 5853 5854 5855 5856 5857 5858 5859 5860 5861 5862 5863 5864
/**
 * DOC: Display Refresh Rate Switching (DRRS)
 *
 * Display Refresh Rate Switching (DRRS) is a power conservation feature
 * which enables swtching between low and high refresh rates,
 * dynamically, based on the usage scenario. This feature is applicable
 * for internal panels.
 *
 * Indication that the panel supports DRRS is given by the panel EDID, which
 * would list multiple refresh rates for one resolution.
 *
 * DRRS is of 2 types - static and seamless.
 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
 * (may appear as a blink on screen) and is used in dock-undock scenario.
 * Seamless DRRS involves changing RR without any visual effect to the user
 * and can be used during normal system usage. This is done by programming
 * certain registers.
 *
 * Support for static/seamless DRRS may be indicated in the VBT based on
 * inputs from the panel spec.
 *
 * DRRS saves power by switching to low RR based on usage scenarios.
 *
 * eDP DRRS:-
 *        The implementation is based on frontbuffer tracking implementation.
 * When there is a disturbance on the screen triggered by user activity or a
 * periodic system activity, DRRS is disabled (RR is changed to high RR).
 * When there is no movement on screen, after a timeout of 1 second, a switch
 * to low RR is made.
 *        For integration with frontbuffer tracking code,
 * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
 *
 * DRRS can be further extended to support other internal panels and also
 * the scenario of video playback wherein RR is set based on the rate
 * requested by userspace.
 */

/**
 * intel_dp_drrs_init - Init basic DRRS work and mutex.
 * @intel_connector: eDP connector
 * @fixed_mode: preferred mode of panel
 *
 * This function is  called only once at driver load to initialize basic
 * DRRS stuff.
 *
 * Returns:
 * Downclock mode if panel supports it, else return NULL.
 * DRRS support is determined by the presence of downclock mode (apart
 * from VBT setting).
 */
5865
static struct drm_display_mode *
5866 5867
intel_dp_drrs_init(struct intel_connector *intel_connector,
		struct drm_display_mode *fixed_mode)
5868 5869
{
	struct drm_connector *connector = &intel_connector->base;
5870
	struct drm_device *dev = connector->dev;
5871 5872 5873
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_display_mode *downclock_mode = NULL;

5874 5875 5876
	INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
	mutex_init(&dev_priv->drrs.mutex);

5877 5878 5879 5880 5881 5882
	if (INTEL_INFO(dev)->gen <= 6) {
		DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
		return NULL;
	}

	if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5883
		DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5884 5885 5886 5887 5888 5889 5890
		return NULL;
	}

	downclock_mode = intel_find_panel_downclock
					(dev, fixed_mode, connector);

	if (!downclock_mode) {
5891
		DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5892 5893 5894
		return NULL;
	}

5895
	dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5896

5897
	dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5898
	DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5899 5900 5901
	return downclock_mode;
}

5902
static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5903
				     struct intel_connector *intel_connector)
5904 5905 5906
{
	struct drm_connector *connector = &intel_connector->base;
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5907 5908
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct drm_device *dev = intel_encoder->base.dev;
5909 5910
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_display_mode *fixed_mode = NULL;
5911
	struct drm_display_mode *downclock_mode = NULL;
5912 5913 5914
	bool has_dpcd;
	struct drm_display_mode *scan;
	struct edid *edid;
5915
	enum pipe pipe = INVALID_PIPE;
5916 5917 5918 5919

	if (!is_edp(intel_dp))
		return true;

5920 5921 5922
	pps_lock(intel_dp);
	intel_edp_panel_vdd_sanitize(intel_dp);
	pps_unlock(intel_dp);
5923

5924 5925 5926 5927 5928 5929 5930 5931 5932 5933 5934 5935 5936 5937 5938
	/* Cache DPCD and EDID for edp. */
	has_dpcd = intel_dp_get_dpcd(intel_dp);

	if (has_dpcd) {
		if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
			dev_priv->no_aux_handshake =
				intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
				DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
	} else {
		/* if this fails, presume the device is a ghost */
		DRM_INFO("failed to retrieve link info, disabling eDP\n");
		return false;
	}

	/* We now know it's not a ghost, init power sequence regs. */
5939
	pps_lock(intel_dp);
5940
	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5941
	pps_unlock(intel_dp);
5942

5943
	mutex_lock(&dev->mode_config.mutex);
5944
	edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5945 5946 5947 5948 5949 5950 5951 5952 5953 5954 5955 5956 5957 5958 5959 5960 5961 5962
	if (edid) {
		if (drm_add_edid_modes(connector, edid)) {
			drm_mode_connector_update_edid_property(connector,
								edid);
			drm_edid_to_eld(connector, edid);
		} else {
			kfree(edid);
			edid = ERR_PTR(-EINVAL);
		}
	} else {
		edid = ERR_PTR(-ENOENT);
	}
	intel_connector->edid = edid;

	/* prefer fixed mode from EDID if available */
	list_for_each_entry(scan, &connector->probed_modes, head) {
		if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
			fixed_mode = drm_mode_duplicate(dev, scan);
5963 5964
			downclock_mode = intel_dp_drrs_init(
						intel_connector, fixed_mode);
5965 5966 5967 5968 5969 5970 5971 5972 5973 5974 5975
			break;
		}
	}

	/* fallback to VBT if available for eDP */
	if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
		fixed_mode = drm_mode_duplicate(dev,
					dev_priv->vbt.lfp_lvds_vbt_mode);
		if (fixed_mode)
			fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
	}
5976
	mutex_unlock(&dev->mode_config.mutex);
5977

5978 5979 5980
	if (IS_VALLEYVIEW(dev)) {
		intel_dp->edp_notifier.notifier_call = edp_notify_handler;
		register_reboot_notifier(&intel_dp->edp_notifier);
5981 5982 5983 5984 5985 5986 5987 5988 5989 5990 5991 5992 5993 5994 5995 5996 5997 5998 5999

		/*
		 * Figure out the current pipe for the initial backlight setup.
		 * If the current pipe isn't valid, try the PPS pipe, and if that
		 * fails just assume pipe A.
		 */
		if (IS_CHERRYVIEW(dev))
			pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
		else
			pipe = PORT_TO_PIPE(intel_dp->DP);

		if (pipe != PIPE_A && pipe != PIPE_B)
			pipe = intel_dp->pps_pipe;

		if (pipe != PIPE_A && pipe != PIPE_B)
			pipe = PIPE_A;

		DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
			      pipe_name(pipe));
6000 6001
	}

6002
	intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
6003
	intel_connector->panel.backlight_power = intel_edp_backlight_power;
6004
	intel_panel_setup_backlight(connector, pipe);
6005 6006 6007 6008

	return true;
}

6009
bool
6010 6011
intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
			struct intel_connector *intel_connector)
6012
{
6013 6014 6015 6016
	struct drm_connector *connector = &intel_connector->base;
	struct intel_dp *intel_dp = &intel_dig_port->dp;
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct drm_device *dev = intel_encoder->base.dev;
6017
	struct drm_i915_private *dev_priv = dev->dev_private;
6018
	enum port port = intel_dig_port->port;
6019
	int type;
6020

6021 6022
	intel_dp->pps_pipe = INVALID_PIPE;

6023
	/* intel_dp vfuncs */
6024 6025 6026
	if (INTEL_INFO(dev)->gen >= 9)
		intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
	else if (IS_VALLEYVIEW(dev))
6027 6028 6029 6030 6031 6032 6033 6034
		intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
		intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
	else if (HAS_PCH_SPLIT(dev))
		intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
	else
		intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;

6035 6036 6037 6038
	if (INTEL_INFO(dev)->gen >= 9)
		intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
	else
		intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
6039

6040 6041
	/* Preserve the current hw state. */
	intel_dp->DP = I915_READ(intel_dp->output_reg);
6042
	intel_dp->attached_connector = intel_connector;
6043

6044
	if (intel_dp_is_edp(dev, port))
6045
		type = DRM_MODE_CONNECTOR_eDP;
6046 6047
	else
		type = DRM_MODE_CONNECTOR_DisplayPort;
6048

6049 6050 6051 6052 6053 6054 6055 6056
	/*
	 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
	 * for DP the encoder type can be set by the caller to
	 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
	 */
	if (type == DRM_MODE_CONNECTOR_eDP)
		intel_encoder->type = INTEL_OUTPUT_EDP;

6057 6058 6059 6060 6061
	/* eDP only on port B and/or C on vlv/chv */
	if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
		    port != PORT_B && port != PORT_C))
		return false;

6062 6063 6064 6065
	DRM_DEBUG_KMS("Adding %s connector on port %c\n",
			type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
			port_name(port));

6066
	drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
6067 6068 6069 6070 6071
	drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);

	connector->interlace_allowed = true;
	connector->doublescan_allowed = 0;

6072
	INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
6073
			  edp_panel_vdd_work);
6074

6075
	intel_connector_attach_encoder(intel_connector, intel_encoder);
6076
	drm_connector_register(connector);
6077

P
Paulo Zanoni 已提交
6078
	if (HAS_DDI(dev))
6079 6080 6081
		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
	else
		intel_connector->get_hw_state = intel_connector_get_hw_state;
6082
	intel_connector->unregister = intel_dp_connector_unregister;
6083

6084
	/* Set up the hotplug pin. */
6085 6086
	switch (port) {
	case PORT_A:
6087
		intel_encoder->hpd_pin = HPD_PORT_A;
6088 6089
		break;
	case PORT_B:
6090
		intel_encoder->hpd_pin = HPD_PORT_B;
6091 6092
		if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0))
			intel_encoder->hpd_pin = HPD_PORT_A;
6093 6094
		break;
	case PORT_C:
6095
		intel_encoder->hpd_pin = HPD_PORT_C;
6096 6097
		break;
	case PORT_D:
6098
		intel_encoder->hpd_pin = HPD_PORT_D;
6099 6100
		break;
	default:
6101
		BUG();
6102 6103
	}

6104
	if (is_edp(intel_dp)) {
6105
		pps_lock(intel_dp);
6106 6107
		intel_dp_init_panel_power_timestamps(intel_dp);
		if (IS_VALLEYVIEW(dev))
6108
			vlv_initial_power_sequencer_setup(intel_dp);
6109
		else
6110
			intel_dp_init_panel_power_sequencer(dev, intel_dp);
6111
		pps_unlock(intel_dp);
6112
	}
6113

6114
	intel_dp_aux_init(intel_dp, intel_connector);
6115

6116
	/* init MST on ports that can support it */
6117 6118 6119 6120
	if (HAS_DP_MST(dev) &&
	    (port == PORT_B || port == PORT_C || port == PORT_D))
		intel_dp_mst_encoder_init(intel_dig_port,
					  intel_connector->base.base.id);
6121

6122
	if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6123
		drm_dp_aux_unregister(&intel_dp->aux);
6124 6125
		if (is_edp(intel_dp)) {
			cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
6126 6127 6128 6129
			/*
			 * vdd might still be enabled do to the delayed vdd off.
			 * Make sure vdd is actually turned off here.
			 */
6130
			pps_lock(intel_dp);
6131
			edp_panel_vdd_off_sync(intel_dp);
6132
			pps_unlock(intel_dp);
6133
		}
6134
		drm_connector_unregister(connector);
6135
		drm_connector_cleanup(connector);
6136
		return false;
6137
	}
6138

6139 6140
	intel_dp_add_properties(intel_dp, connector);

6141 6142 6143 6144 6145 6146 6147 6148
	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
	 * 0xd.  Failure to do so will result in spurious interrupts being
	 * generated on the port when a cable is not attached.
	 */
	if (IS_G4X(dev) && !IS_GM45(dev)) {
		u32 temp = I915_READ(PEG_BAND_GAP_DATA);
		I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
	}
6149

6150 6151
	i915_debugfs_connector_add(connector);

6152
	return true;
6153
}
6154 6155 6156 6157

void
intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
{
6158
	struct drm_i915_private *dev_priv = dev->dev_private;
6159 6160 6161 6162 6163
	struct intel_digital_port *intel_dig_port;
	struct intel_encoder *intel_encoder;
	struct drm_encoder *encoder;
	struct intel_connector *intel_connector;

6164
	intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
6165 6166 6167
	if (!intel_dig_port)
		return;

6168
	intel_connector = intel_connector_alloc();
6169 6170 6171 6172 6173 6174 6175 6176 6177 6178 6179
	if (!intel_connector) {
		kfree(intel_dig_port);
		return;
	}

	intel_encoder = &intel_dig_port->base;
	encoder = &intel_encoder->base;

	drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
			 DRM_MODE_ENCODER_TMDS);

6180
	intel_encoder->compute_config = intel_dp_compute_config;
P
Paulo Zanoni 已提交
6181 6182
	intel_encoder->disable = intel_disable_dp;
	intel_encoder->get_hw_state = intel_dp_get_hw_state;
6183
	intel_encoder->get_config = intel_dp_get_config;
6184
	intel_encoder->suspend = intel_dp_encoder_suspend;
6185
	if (IS_CHERRYVIEW(dev)) {
6186
		intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
6187 6188
		intel_encoder->pre_enable = chv_pre_enable_dp;
		intel_encoder->enable = vlv_enable_dp;
6189
		intel_encoder->post_disable = chv_post_disable_dp;
6190
		intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
6191
	} else if (IS_VALLEYVIEW(dev)) {
6192
		intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
6193 6194
		intel_encoder->pre_enable = vlv_pre_enable_dp;
		intel_encoder->enable = vlv_enable_dp;
6195
		intel_encoder->post_disable = vlv_post_disable_dp;
6196
	} else {
6197 6198
		intel_encoder->pre_enable = g4x_pre_enable_dp;
		intel_encoder->enable = g4x_enable_dp;
6199 6200
		if (INTEL_INFO(dev)->gen >= 5)
			intel_encoder->post_disable = ilk_post_disable_dp;
6201
	}
6202

6203
	intel_dig_port->port = port;
6204 6205
	intel_dig_port->dp.output_reg = output_reg;

P
Paulo Zanoni 已提交
6206
	intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
6207 6208 6209 6210 6211 6212 6213 6214
	if (IS_CHERRYVIEW(dev)) {
		if (port == PORT_D)
			intel_encoder->crtc_mask = 1 << 2;
		else
			intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
	} else {
		intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
	}
6215
	intel_encoder->cloneable = 0;
6216

6217
	intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6218
	dev_priv->hotplug.irq_port[port] = intel_dig_port;
6219

6220 6221 6222
	if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
		drm_encoder_cleanup(encoder);
		kfree(intel_dig_port);
6223
		kfree(intel_connector);
6224
	}
6225
}
6226 6227 6228 6229 6230 6231 6232 6233

void intel_dp_mst_suspend(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;

	/* disable MST */
	for (i = 0; i < I915_MAX_PORTS; i++) {
6234
		struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6235 6236 6237 6238 6239 6240 6241 6242 6243 6244 6245 6246 6247 6248 6249 6250 6251 6252
		if (!intel_dig_port)
			continue;

		if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
			if (!intel_dig_port->dp.can_mst)
				continue;
			if (intel_dig_port->dp.is_mst)
				drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
		}
	}
}

void intel_dp_mst_resume(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;

	for (i = 0; i < I915_MAX_PORTS; i++) {
6253
		struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6254 6255 6256 6257 6258 6259 6260 6261 6262 6263 6264 6265 6266 6267 6268
		if (!intel_dig_port)
			continue;
		if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
			int ret;

			if (!intel_dig_port->dp.can_mst)
				continue;

			ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
			if (ret != 0) {
				intel_dp_check_mst_status(&intel_dig_port->dp);
			}
		}
	}
}