gadget.c 84.8 KB
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// SPDX-License-Identifier: GPL-2.0
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/*
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 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
 *
 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
 *
 * Authors: Felipe Balbi <balbi@ti.com>,
 *	    Sebastian Andrzej Siewior <bigeasy@linutronix.de>
 */

#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/list.h>
#include <linux/dma-mapping.h>

#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>

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#include "debug.h"
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#include "core.h"
#include "gadget.h"
#include "io.h"

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#define DWC3_ALIGN_FRAME(d, n)	(((d)->frame_number + ((d)->interval * (n))) \
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					& ~((d)->interval - 1))

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/**
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 * dwc3_gadget_set_test_mode - enables usb2 test modes
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 * @dwc: pointer to our context structure
 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
 *
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 * Caller should take care of locking. This function will return 0 on
 * success or -EINVAL if wrong Test Selector is passed.
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 */
int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
{
	u32		reg;

	reg = dwc3_readl(dwc->regs, DWC3_DCTL);
	reg &= ~DWC3_DCTL_TSTCTRL_MASK;

	switch (mode) {
	case TEST_J:
	case TEST_K:
	case TEST_SE0_NAK:
	case TEST_PACKET:
	case TEST_FORCE_EN:
		reg |= mode << 1;
		break;
	default:
		return -EINVAL;
	}

	dwc3_writel(dwc->regs, DWC3_DCTL, reg);

	return 0;
}

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/**
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 * dwc3_gadget_get_link_state - gets current state of usb link
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 * @dwc: pointer to our context structure
 *
 * Caller should take care of locking. This function will
 * return the link state on success (>= 0) or -ETIMEDOUT.
 */
int dwc3_gadget_get_link_state(struct dwc3 *dwc)
{
	u32		reg;

	reg = dwc3_readl(dwc->regs, DWC3_DSTS);

	return DWC3_DSTS_USBLNKST(reg);
}

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/**
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 * dwc3_gadget_set_link_state - sets usb link to a particular state
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 * @dwc: pointer to our context structure
 * @state: the state to put link into
 *
 * Caller should take care of locking. This function will
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 * return 0 on success or -ETIMEDOUT.
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 */
int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
{
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	int		retries = 10000;
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	u32		reg;

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	/*
	 * Wait until device controller is ready. Only applies to 1.94a and
	 * later RTL.
	 */
	if (dwc->revision >= DWC3_REVISION_194A) {
		while (--retries) {
			reg = dwc3_readl(dwc->regs, DWC3_DSTS);
			if (reg & DWC3_DSTS_DCNRD)
				udelay(5);
			else
				break;
		}

		if (retries <= 0)
			return -ETIMEDOUT;
	}

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	reg = dwc3_readl(dwc->regs, DWC3_DCTL);
	reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;

	/* set requested state */
	reg |= DWC3_DCTL_ULSTCHNGREQ(state);
	dwc3_writel(dwc->regs, DWC3_DCTL, reg);

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	/*
	 * The following code is racy when called from dwc3_gadget_wakeup,
	 * and is not needed, at least on newer versions
	 */
	if (dwc->revision >= DWC3_REVISION_194A)
		return 0;

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	/* wait for a change in DSTS */
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	retries = 10000;
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	while (--retries) {
		reg = dwc3_readl(dwc->regs, DWC3_DSTS);

		if (DWC3_DSTS_USBLNKST(reg) == state)
			return 0;

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		udelay(5);
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	}

	return -ETIMEDOUT;
}

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/**
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 * dwc3_ep_inc_trb - increment a trb index.
 * @index: Pointer to the TRB index to increment.
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 *
 * The index should never point to the link TRB. After incrementing,
 * if it is point to the link TRB, wrap around to the beginning. The
 * link TRB is always at the last TRB entry.
 */
static void dwc3_ep_inc_trb(u8 *index)
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{
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	(*index)++;
	if (*index == (DWC3_TRB_NUM - 1))
		*index = 0;
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}
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/**
 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
 * @dep: The endpoint whose enqueue pointer we're incrementing
 */
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static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
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{
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	dwc3_ep_inc_trb(&dep->trb_enqueue);
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}
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/**
 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
 * @dep: The endpoint whose enqueue pointer we're incrementing
 */
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static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
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{
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	dwc3_ep_inc_trb(&dep->trb_dequeue);
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}

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static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
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		struct dwc3_request *req, int status)
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{
	struct dwc3			*dwc = dep->dwc;

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	req->started = false;
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	list_del(&req->list);
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	req->remaining = 0;
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	if (req->request.status == -EINPROGRESS)
		req->request.status = status;

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	if (req->trb)
		usb_gadget_unmap_request_by_dev(dwc->sysdev,
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				&req->request, req->direction);
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	req->trb = NULL;
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	trace_dwc3_gadget_giveback(req);
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	if (dep->number > 1)
		pm_runtime_put(dwc->dev);
}

/**
 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
 * @dep: The endpoint to whom the request belongs to
 * @req: The request we're giving back
 * @status: completion code for the request
 *
 * Must be called with controller's lock held and interrupts disabled. This
 * function will unmap @req and call its ->complete() callback to notify upper
 * layers that it has completed.
 */
void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
		int status)
{
	struct dwc3			*dwc = dep->dwc;

	dwc3_gadget_del_and_unmap_request(dep, req, status);

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	spin_unlock(&dwc->lock);
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	usb_gadget_giveback_request(&dep->endpoint, &req->request);
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	spin_lock(&dwc->lock);
}

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/**
 * dwc3_send_gadget_generic_command - issue a generic command for the controller
 * @dwc: pointer to the controller context
 * @cmd: the command to be issued
 * @param: command parameter
 *
 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
 * and wait for its completion.
 */
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int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
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{
	u32		timeout = 500;
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	int		status = 0;
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	int		ret = 0;
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	u32		reg;

	dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
	dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);

	do {
		reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
		if (!(reg & DWC3_DGCMD_CMDACT)) {
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			status = DWC3_DGCMD_STATUS(reg);
			if (status)
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				ret = -EINVAL;
			break;
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		}
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	} while (--timeout);
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	if (!timeout) {
		ret = -ETIMEDOUT;
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		status = -ETIMEDOUT;
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	}

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	trace_dwc3_gadget_generic_cmd(cmd, param, status);

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	return ret;
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}

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static int __dwc3_gadget_wakeup(struct dwc3 *dwc);

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/**
 * dwc3_send_gadget_ep_cmd - issue an endpoint command
 * @dep: the endpoint to which the command is going to be issued
 * @cmd: the command to be issued
 * @params: parameters to the command
 *
 * Caller should handle locking. This function will issue @cmd with given
 * @params to @dep and wait for its completion.
 */
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int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
		struct dwc3_gadget_ep_cmd_params *params)
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{
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	const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
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	struct dwc3		*dwc = dep->dwc;
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	u32			timeout = 1000;
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	u32			saved_config = 0;
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	u32			reg;

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	int			cmd_status = 0;
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	int			ret = -EINVAL;
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	/*
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	 * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
	 * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
	 * endpoint command.
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	 *
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	 * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
	 * settings. Restore them after the command is completed.
	 *
	 * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
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	 */
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	if (dwc->gadget.speed <= USB_SPEED_HIGH) {
		reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
		if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
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			saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
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			reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
		}
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		if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
			saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
			reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
		}

		if (saved_config)
			dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
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	}

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	if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
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		int		needs_wakeup;

		needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
				dwc->link_state == DWC3_LINK_STATE_U2 ||
				dwc->link_state == DWC3_LINK_STATE_U3);

		if (unlikely(needs_wakeup)) {
			ret = __dwc3_gadget_wakeup(dwc);
			dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
					ret);
		}
	}

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	dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
	dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
	dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
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	/*
	 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
	 * not relying on XferNotReady, we can make use of a special "No
	 * Response Update Transfer" command where we should clear both CmdAct
	 * and CmdIOC bits.
	 *
	 * With this, we don't need to wait for command completion and can
	 * straight away issue further commands to the endpoint.
	 *
	 * NOTICE: We're making an assumption that control endpoints will never
	 * make use of Update Transfer command. This is a safe assumption
	 * because we can never have more than one request at a time with
	 * Control Endpoints. If anybody changes that assumption, this chunk
	 * needs to be updated accordingly.
	 */
	if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
			!usb_endpoint_xfer_isoc(desc))
		cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
	else
		cmd |= DWC3_DEPCMD_CMDACT;

	dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
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	do {
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		reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
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		if (!(reg & DWC3_DEPCMD_CMDACT)) {
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			cmd_status = DWC3_DEPCMD_STATUS(reg);
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			switch (cmd_status) {
			case 0:
				ret = 0;
				break;
			case DEPEVT_TRANSFER_NO_RESOURCE:
				ret = -EINVAL;
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				break;
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			case DEPEVT_TRANSFER_BUS_EXPIRY:
				/*
				 * SW issues START TRANSFER command to
				 * isochronous ep with future frame interval. If
				 * future interval time has already passed when
				 * core receives the command, it will respond
				 * with an error status of 'Bus Expiry'.
				 *
				 * Instead of always returning -EINVAL, let's
				 * give a hint to the gadget driver that this is
				 * the case by returning -EAGAIN.
				 */
				ret = -EAGAIN;
				break;
			default:
				dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
			}

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			break;
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		}
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	} while (--timeout);
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	if (timeout == 0) {
		ret = -ETIMEDOUT;
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		cmd_status = -ETIMEDOUT;
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	}
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	trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);

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	if (ret == 0) {
		switch (DWC3_DEPCMD_CMD(cmd)) {
		case DWC3_DEPCMD_STARTTRANSFER:
			dep->flags |= DWC3_EP_TRANSFER_STARTED;
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			dwc3_gadget_ep_get_transfer_index(dep);
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			break;
		case DWC3_DEPCMD_ENDTRANSFER:
			dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
			break;
		default:
			/* nothing */
			break;
		}
	}

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	if (saved_config) {
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		reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
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		reg |= saved_config;
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		dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
	}

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	return ret;
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}

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static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
{
	struct dwc3 *dwc = dep->dwc;
	struct dwc3_gadget_ep_cmd_params params;
	u32 cmd = DWC3_DEPCMD_CLEARSTALL;

	/*
	 * As of core revision 2.60a the recommended programming model
	 * is to set the ClearPendIN bit when issuing a Clear Stall EP
	 * command for IN endpoints. This is to prevent an issue where
	 * some (non-compliant) hosts may not send ACK TPs for pending
	 * IN transfers due to a mishandled error condition. Synopsys
	 * STAR 9000614252.
	 */
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	if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
	    (dwc->gadget.speed >= USB_SPEED_SUPER))
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		cmd |= DWC3_DEPCMD_CLEARPENDIN;

	memset(&params, 0, sizeof(params));

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	return dwc3_send_gadget_ep_cmd(dep, cmd, &params);
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}

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static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
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		struct dwc3_trb *trb)
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{
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	u32		offset = (char *) trb - (char *) dep->trb_pool;
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	return dep->trb_pool_dma + offset;
}

static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
{
	struct dwc3		*dwc = dep->dwc;

	if (dep->trb_pool)
		return 0;

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	dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
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			sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
			&dep->trb_pool_dma, GFP_KERNEL);
	if (!dep->trb_pool) {
		dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
				dep->name);
		return -ENOMEM;
	}

	return 0;
}

static void dwc3_free_trb_pool(struct dwc3_ep *dep)
{
	struct dwc3		*dwc = dep->dwc;

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	dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
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			dep->trb_pool, dep->trb_pool_dma);

	dep->trb_pool = NULL;
	dep->trb_pool_dma = 0;
}

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static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep)
{
	struct dwc3_gadget_ep_cmd_params params;

	memset(&params, 0x00, sizeof(params));

	params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);

	return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
			&params);
}
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/**
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 * dwc3_gadget_start_config - configure ep resources
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 * @dep: endpoint that is being enabled
 *
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 * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
 * completion, it will set Transfer Resource for all available endpoints.
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 *
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 * The assignment of transfer resources cannot perfectly follow the data book
 * due to the fact that the controller driver does not have all knowledge of the
 * configuration in advance. It is given this information piecemeal by the
 * composite gadget framework after every SET_CONFIGURATION and
 * SET_INTERFACE. Trying to follow the databook programming model in this
 * scenario can cause errors. For two reasons:
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 *
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 * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
 * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
 * incorrect in the scenario of multiple interfaces.
 *
 * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
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 * endpoint on alt setting (8.1.6).
 *
 * The following simplified method is used instead:
 *
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 * All hardware endpoints can be assigned a transfer resource and this setting
 * will stay persistent until either a core reset or hibernation. So whenever we
 * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
 * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
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 * guaranteed that there are as many transfer resources as endpoints.
 *
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 * This function is called for each endpoint when it is being enabled but is
 * triggered only when called for EP0-out, which always happens first, and which
 * should only happen in one of the above conditions.
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 */
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static int dwc3_gadget_start_config(struct dwc3_ep *dep)
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{
	struct dwc3_gadget_ep_cmd_params params;
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	struct dwc3		*dwc;
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	u32			cmd;
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	int			i;
	int			ret;

	if (dep->number)
		return 0;
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	memset(&params, 0x00, sizeof(params));
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	cmd = DWC3_DEPCMD_DEPSTARTCFG;
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	dwc = dep->dwc;
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	ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
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	if (ret)
		return ret;

	for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
		struct dwc3_ep *dep = dwc->eps[i];
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		if (!dep)
			continue;

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		ret = dwc3_gadget_set_xfer_resource(dep);
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		if (ret)
			return ret;
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	}

	return 0;
}

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static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
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{
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	const struct usb_ss_ep_comp_descriptor *comp_desc;
	const struct usb_endpoint_descriptor *desc;
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	struct dwc3_gadget_ep_cmd_params params;
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	struct dwc3 *dwc = dep->dwc;
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	comp_desc = dep->endpoint.comp_desc;
	desc = dep->endpoint.desc;

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	memset(&params, 0x00, sizeof(params));

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	params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
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		| DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));

	/* Burst size is only needed in SuperSpeed mode */
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	if (dwc->gadget.speed >= USB_SPEED_SUPER) {
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		u32 burst = dep->endpoint.maxburst;
		params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
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	}
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	params.param0 |= action;
	if (action == DWC3_DEPCFG_ACTION_RESTORE)
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		params.param2 |= dep->saved_state;

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	if (usb_endpoint_xfer_control(desc))
		params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
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	if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
		params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
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	if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
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		params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
			| DWC3_DEPCFG_STREAM_EVENT_EN;
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		dep->stream_capable = true;
	}

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	if (!usb_endpoint_xfer_control(desc))
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		params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
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	/*
	 * We are doing 1:1 mapping for endpoints, meaning
	 * Physical Endpoints 2 maps to Logical Endpoint 2 and
	 * so on. We consider the direction bit as part of the physical
	 * endpoint number. So USB endpoint 0x81 is 0x03.
	 */
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	params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
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	/*
	 * We must use the lower 16 TX FIFOs even though
	 * HW might have more
	 */
	if (dep->direction)
602
		params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
603 604

	if (desc->bInterval) {
605
		params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
606 607 608
		dep->interval = 1 << (desc->bInterval - 1);
	}

609
	return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, &params);
610 611 612
}

/**
F
Felipe Balbi 已提交
613
 * __dwc3_gadget_ep_enable - initializes a hw endpoint
614
 * @dep: endpoint to be initialized
615
 * @action: one of INIT, MODIFY or RESTORE
616
 *
F
Felipe Balbi 已提交
617 618
 * Caller should take care of locking. Execute all necessary commands to
 * initialize a HW endpoint so it can be used by a gadget driver.
619
 */
620
static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
621
{
622
	const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
623
	struct dwc3		*dwc = dep->dwc;
624

625
	u32			reg;
626
	int			ret;
627 628

	if (!(dep->flags & DWC3_EP_ENABLED)) {
629
		ret = dwc3_gadget_start_config(dep);
630 631 632 633
		if (ret)
			return ret;
	}

634
	ret = dwc3_gadget_set_ep_config(dep, action);
635 636 637 638
	if (ret)
		return ret;

	if (!(dep->flags & DWC3_EP_ENABLED)) {
639 640
		struct dwc3_trb	*trb_st_hw;
		struct dwc3_trb	*trb_link;
641 642 643

		dep->type = usb_endpoint_type(desc);
		dep->flags |= DWC3_EP_ENABLED;
644
		dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
645 646 647 648 649

		reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
		reg |= DWC3_DALEPENA_EP(dep->number);
		dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);

650
		if (usb_endpoint_xfer_control(desc))
651
			goto out;
652

653 654 655 656 657 658
		/* Initialize the TRB ring */
		dep->trb_dequeue = 0;
		dep->trb_enqueue = 0;
		memset(dep->trb_pool, 0,
		       sizeof(struct dwc3_trb) * DWC3_TRB_NUM);

659
		/* Link TRB. The HWO bit is never reset */
660 661
		trb_st_hw = &dep->trb_pool[0];

662 663 664 665 666
		trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
		trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
		trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
		trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
		trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
667 668
	}

669 670 671 672
	/*
	 * Issue StartTransfer here with no-op TRB so we can always rely on No
	 * Response Update Transfer command.
	 */
673
	if ((usb_endpoint_xfer_bulk(desc) && !dep->stream_capable) ||
674
			usb_endpoint_xfer_int(desc)) {
675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693
		struct dwc3_gadget_ep_cmd_params params;
		struct dwc3_trb	*trb;
		dma_addr_t trb_dma;
		u32 cmd;

		memset(&params, 0, sizeof(params));
		trb = &dep->trb_pool[0];
		trb_dma = dwc3_trb_dma_offset(dep, trb);

		params.param0 = upper_32_bits(trb_dma);
		params.param1 = lower_32_bits(trb_dma);

		cmd = DWC3_DEPCMD_STARTTRANSFER;

		ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
		if (ret < 0)
			return ret;
	}

694 695 696
out:
	trace_dwc3_gadget_ep_enable(dep);

697 698 699
	return 0;
}

700
static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force);
701
static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
702 703 704
{
	struct dwc3_request		*req;

705
	dwc3_stop_active_transfer(dep, true);
706

707 708 709
	/* - giveback all requests to gadget driver */
	while (!list_empty(&dep->started_list)) {
		req = next_request(&dep->started_list);
710

711
		dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
712 713
	}

714 715
	while (!list_empty(&dep->pending_list)) {
		req = next_request(&dep->pending_list);
716

717
		dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
718 719 720 721
	}
}

/**
F
Felipe Balbi 已提交
722
 * __dwc3_gadget_ep_disable - disables a hw endpoint
723 724
 * @dep: the endpoint to disable
 *
F
Felipe Balbi 已提交
725 726 727 728
 * This function undoes what __dwc3_gadget_ep_enable did and also removes
 * requests which are currently being processed by the hardware and those which
 * are not yet scheduled.
 *
729
 * Caller should take care of locking.
730 731 732 733 734 735
 */
static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
{
	struct dwc3		*dwc = dep->dwc;
	u32			reg;

736
	trace_dwc3_gadget_ep_disable(dep);
737

738
	dwc3_remove_requests(dwc, dep);
739

740 741
	/* make sure HW endpoint isn't stalled */
	if (dep->flags & DWC3_EP_STALL)
742
		__dwc3_gadget_ep_set_halt(dep, 0, false);
743

744 745 746 747
	reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
	reg &= ~DWC3_DALEPENA_EP(dep->number);
	dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);

748
	dep->stream_capable = false;
749
	dep->type = 0;
750
	dep->flags &= DWC3_EP_END_TRANSFER_PENDING;
751

752 753 754 755 756 757
	/* Clear out the ep descriptors for non-ep0 */
	if (dep->number > 1) {
		dep->endpoint.comp_desc = NULL;
		dep->endpoint.desc = NULL;
	}

758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796
	return 0;
}

/* -------------------------------------------------------------------------- */

static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
		const struct usb_endpoint_descriptor *desc)
{
	return -EINVAL;
}

static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
{
	return -EINVAL;
}

/* -------------------------------------------------------------------------- */

static int dwc3_gadget_ep_enable(struct usb_ep *ep,
		const struct usb_endpoint_descriptor *desc)
{
	struct dwc3_ep			*dep;
	struct dwc3			*dwc;
	unsigned long			flags;
	int				ret;

	if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
		pr_debug("dwc3: invalid parameters\n");
		return -EINVAL;
	}

	if (!desc->wMaxPacketSize) {
		pr_debug("dwc3: missing wMaxPacketSize\n");
		return -EINVAL;
	}

	dep = to_dwc3_ep(ep);
	dwc = dep->dwc;

797 798 799
	if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
					"%s is already enabled\n",
					dep->name))
800 801
		return 0;

802
	spin_lock_irqsave(&dwc->lock, flags);
803
	ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823
	spin_unlock_irqrestore(&dwc->lock, flags);

	return ret;
}

static int dwc3_gadget_ep_disable(struct usb_ep *ep)
{
	struct dwc3_ep			*dep;
	struct dwc3			*dwc;
	unsigned long			flags;
	int				ret;

	if (!ep) {
		pr_debug("dwc3: invalid parameters\n");
		return -EINVAL;
	}

	dep = to_dwc3_ep(ep);
	dwc = dep->dwc;

824 825 826
	if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
					"%s is already disabled\n",
					dep->name))
827 828 829 830 831 832 833 834 835 836
		return 0;

	spin_lock_irqsave(&dwc->lock, flags);
	ret = __dwc3_gadget_ep_disable(dep);
	spin_unlock_irqrestore(&dwc->lock, flags);

	return ret;
}

static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
837
		gfp_t gfp_flags)
838 839 840 841 842
{
	struct dwc3_request		*req;
	struct dwc3_ep			*dep = to_dwc3_ep(ep);

	req = kzalloc(sizeof(*req), gfp_flags);
843
	if (!req)
844 845
		return NULL;

846
	req->direction	= dep->direction;
847 848 849
	req->epnum	= dep->number;
	req->dep	= dep;

850 851
	trace_dwc3_alloc_request(req);

852 853 854 855 856 857 858 859
	return &req->request;
}

static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
		struct usb_request *request)
{
	struct dwc3_request		*req = to_dwc3_request(request);

860
	trace_dwc3_free_request(req);
861 862 863
	kfree(req);
}

864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910
/**
 * dwc3_ep_prev_trb - returns the previous TRB in the ring
 * @dep: The endpoint with the TRB ring
 * @index: The index of the current TRB in the ring
 *
 * Returns the TRB prior to the one pointed to by the index. If the
 * index is 0, we will wrap backwards, skip the link TRB, and return
 * the one just before that.
 */
static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
{
	u8 tmp = index;

	if (!tmp)
		tmp = DWC3_TRB_NUM - 1;

	return &dep->trb_pool[tmp - 1];
}

static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
{
	struct dwc3_trb		*tmp;
	u8			trbs_left;

	/*
	 * If enqueue & dequeue are equal than it is either full or empty.
	 *
	 * One way to know for sure is if the TRB right before us has HWO bit
	 * set or not. If it has, then we're definitely full and can't fit any
	 * more transfers in our ring.
	 */
	if (dep->trb_enqueue == dep->trb_dequeue) {
		tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
		if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
			return 0;

		return DWC3_TRB_NUM - 1;
	}

	trbs_left = dep->trb_dequeue - dep->trb_enqueue;
	trbs_left &= (DWC3_TRB_NUM - 1);

	if (dep->trb_dequeue < dep->trb_enqueue)
		trbs_left--;

	return trbs_left;
}
911

912 913 914
static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
		dma_addr_t dma, unsigned length, unsigned chain, unsigned node,
		unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt)
915
{
916 917 918
	struct dwc3		*dwc = dep->dwc;
	struct usb_gadget	*gadget = &dwc->gadget;
	enum usb_device_speed	speed = gadget->speed;
919

920 921 922
	trb->size = DWC3_TRB_SIZE_LENGTH(length);
	trb->bpl = lower_32_bits(dma);
	trb->bph = upper_32_bits(dma);
923

924
	switch (usb_endpoint_type(dep->endpoint.desc)) {
925
	case USB_ENDPOINT_XFER_CONTROL:
926
		trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
927 928 929
		break;

	case USB_ENDPOINT_XFER_ISOC:
930
		if (!node) {
931
			trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
932

933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954
			/*
			 * USB Specification 2.0 Section 5.9.2 states that: "If
			 * there is only a single transaction in the microframe,
			 * only a DATA0 data packet PID is used.  If there are
			 * two transactions per microframe, DATA1 is used for
			 * the first transaction data packet and DATA0 is used
			 * for the second transaction data packet.  If there are
			 * three transactions per microframe, DATA2 is used for
			 * the first transaction data packet, DATA1 is used for
			 * the second, and DATA0 is used for the third."
			 *
			 * IOW, we should satisfy the following cases:
			 *
			 * 1) length <= maxpacket
			 *	- DATA0
			 *
			 * 2) maxpacket < length <= (2 * maxpacket)
			 *	- DATA1, DATA0
			 *
			 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
			 *	- DATA2, DATA1, DATA0
			 */
955 956
			if (speed == USB_SPEED_HIGH) {
				struct usb_ep *ep = &dep->endpoint;
957
				unsigned int mult = 2;
958 959 960 961 962 963 964 965 966
				unsigned int maxp = usb_endpoint_maxp(ep->desc);

				if (length <= (2 * maxp))
					mult--;

				if (length <= maxp)
					mult--;

				trb->size |= DWC3_TRB_SIZE_PCM1(mult);
967 968
			}
		} else {
969
			trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
970
		}
971 972 973

		/* always enable Interrupt on Missed ISOC */
		trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
974 975 976 977
		break;

	case USB_ENDPOINT_XFER_BULK:
	case USB_ENDPOINT_XFER_INT:
978
		trb->ctrl = DWC3_TRBCTL_NORMAL;
979 980 981 982 983 984
		break;
	default:
		/*
		 * This is only possible with faulty memory because we
		 * checked it already :)
		 */
985 986
		dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
				usb_endpoint_type(dep->endpoint.desc));
987 988
	}

989
	/* always enable Continue on Short Packet */
990
	if (usb_endpoint_dir_out(dep->endpoint.desc)) {
991
		trb->ctrl |= DWC3_TRB_CTRL_CSP;
992

993
		if (short_not_ok)
994 995 996
			trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
	}

997
	if ((!no_interrupt && !chain) ||
998
			(dwc3_calc_trbs_left(dep) == 1))
999
		trb->ctrl |= DWC3_TRB_CTRL_IOC;
1000

1001 1002 1003
	if (chain)
		trb->ctrl |= DWC3_TRB_CTRL_CHN;

1004
	if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
1005
		trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
1006

1007
	trb->ctrl |= DWC3_TRB_CTRL_HWO;
1008

1009 1010
	dwc3_ep_inc_enq(dep);

1011
	trace_dwc3_prepare_trb(dep, trb);
1012 1013
}

1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024
/**
 * dwc3_prepare_one_trb - setup one TRB from one request
 * @dep: endpoint for which this request is prepared
 * @req: dwc3_request pointer
 * @chain: should this TRB be chained to the next?
 * @node: only for isochronous endpoints. First TRB needs different type.
 */
static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
		struct dwc3_request *req, unsigned chain, unsigned node)
{
	struct dwc3_trb		*trb;
1025 1026
	unsigned int		length;
	dma_addr_t		dma;
1027 1028 1029
	unsigned		stream_id = req->request.stream_id;
	unsigned		short_not_ok = req->request.short_not_ok;
	unsigned		no_interrupt = req->request.no_interrupt;
1030 1031 1032 1033 1034 1035 1036 1037

	if (req->request.num_sgs > 0) {
		length = sg_dma_len(req->start_sg);
		dma = sg_dma_address(req->start_sg);
	} else {
		length = req->request.length;
		dma = req->request.dma;
	}
1038 1039 1040 1041 1042 1043 1044 1045 1046

	trb = &dep->trb_pool[dep->trb_enqueue];

	if (!req->trb) {
		dwc3_gadget_move_started_request(req);
		req->trb = trb;
		req->trb_dma = dwc3_trb_dma_offset(dep, trb);
	}

1047 1048
	req->num_trbs++;

1049 1050 1051 1052
	__dwc3_prepare_one_trb(dep, trb, dma, length, chain, node,
			stream_id, short_not_ok, no_interrupt);
}

1053
static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
1054
		struct dwc3_request *req)
1055
{
1056
	struct scatterlist *sg = req->start_sg;
1057 1058 1059
	struct scatterlist *s;
	int		i;

1060 1061 1062 1063
	unsigned int remaining = req->request.num_mapped_sgs
		- req->num_queued_sgs;

	for_each_sg(sg, s, remaining, i) {
1064 1065 1066
		unsigned int length = req->request.length;
		unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
		unsigned int rem = length % maxp;
1067 1068
		unsigned chain = true;

1069
		if (sg_is_last(s))
1070 1071
			chain = false;

1072 1073 1074 1075
		if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) {
			struct dwc3	*dwc = dep->dwc;
			struct dwc3_trb	*trb;

1076
			req->needs_extra_trb = true;
1077 1078 1079 1080 1081 1082

			/* prepare normal TRB */
			dwc3_prepare_one_trb(dep, req, true, i);

			/* Now prepare one extra TRB to align transfer size */
			trb = &dep->trb_pool[dep->trb_enqueue];
1083
			req->num_trbs++;
1084
			__dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr,
1085
					maxp - rem, false, 1,
1086 1087 1088 1089 1090 1091
					req->request.stream_id,
					req->request.short_not_ok,
					req->request.no_interrupt);
		} else {
			dwc3_prepare_one_trb(dep, req, chain, i);
		}
1092

1093 1094 1095 1096 1097 1098 1099 1100 1101 1102
		/*
		 * There can be a situation where all sgs in sglist are not
		 * queued because of insufficient trb number. To handle this
		 * case, update start_sg to next sg to be queued, so that
		 * we have free trbs we can continue queuing from where we
		 * previously stopped
		 */
		if (chain)
			req->start_sg = sg_next(s);

1103 1104
		req->num_queued_sgs++;

1105
		if (!dwc3_calc_trbs_left(dep))
1106 1107 1108 1109 1110
			break;
	}
}

static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
1111
		struct dwc3_request *req)
1112
{
1113 1114 1115 1116 1117 1118 1119 1120
	unsigned int length = req->request.length;
	unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
	unsigned int rem = length % maxp;

	if (rem && usb_endpoint_dir_out(dep->endpoint.desc)) {
		struct dwc3	*dwc = dep->dwc;
		struct dwc3_trb	*trb;

1121
		req->needs_extra_trb = true;
1122 1123 1124 1125 1126 1127

		/* prepare normal TRB */
		dwc3_prepare_one_trb(dep, req, true, 0);

		/* Now prepare one extra TRB to align transfer size */
		trb = &dep->trb_pool[dep->trb_enqueue];
1128
		req->num_trbs++;
1129
		__dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem,
1130
				false, 1, req->request.stream_id,
1131 1132
				req->request.short_not_ok,
				req->request.no_interrupt);
F
Felipe Balbi 已提交
1133
	} else if (req->request.zero && req->request.length &&
1134
		   (IS_ALIGNED(req->request.length, maxp))) {
F
Felipe Balbi 已提交
1135 1136 1137
		struct dwc3	*dwc = dep->dwc;
		struct dwc3_trb	*trb;

1138
		req->needs_extra_trb = true;
F
Felipe Balbi 已提交
1139 1140 1141 1142 1143 1144

		/* prepare normal TRB */
		dwc3_prepare_one_trb(dep, req, true, 0);

		/* Now prepare one extra TRB to handle ZLP */
		trb = &dep->trb_pool[dep->trb_enqueue];
1145
		req->num_trbs++;
F
Felipe Balbi 已提交
1146
		__dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0,
1147
				false, 1, req->request.stream_id,
F
Felipe Balbi 已提交
1148 1149
				req->request.short_not_ok,
				req->request.no_interrupt);
1150 1151 1152
	} else {
		dwc3_prepare_one_trb(dep, req, false, 0);
	}
1153 1154
}

1155 1156 1157 1158
/*
 * dwc3_prepare_trbs - setup TRBs from requests
 * @dep: endpoint for which requests are being prepared
 *
1159 1160 1161
 * The function goes through the requests list and sets up TRBs for the
 * transfers. The function returns once there are no more TRBs available or
 * it runs out of requests.
1162
 */
1163
static void dwc3_prepare_trbs(struct dwc3_ep *dep)
1164
{
1165
	struct dwc3_request	*req, *n;
1166 1167 1168

	BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);

1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186
	/*
	 * We can get in a situation where there's a request in the started list
	 * but there weren't enough TRBs to fully kick it in the first time
	 * around, so it has been waiting for more TRBs to be freed up.
	 *
	 * In that case, we should check if we have a request with pending_sgs
	 * in the started list and prepare TRBs for that request first,
	 * otherwise we will prepare TRBs completely out of order and that will
	 * break things.
	 */
	list_for_each_entry(req, &dep->started_list, list) {
		if (req->num_pending_sgs > 0)
			dwc3_prepare_one_trb_sg(dep, req);

		if (!dwc3_calc_trbs_left(dep))
			return;
	}

1187
	list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1188 1189 1190 1191 1192 1193 1194 1195 1196
		struct dwc3	*dwc = dep->dwc;
		int		ret;

		ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
						    dep->direction);
		if (ret)
			return;

		req->sg			= req->request.sg;
1197
		req->start_sg		= req->sg;
1198
		req->num_queued_sgs	= 0;
1199 1200
		req->num_pending_sgs	= req->request.num_mapped_sgs;

1201
		if (req->num_pending_sgs > 0)
1202
			dwc3_prepare_one_trb_sg(dep, req);
1203
		else
1204
			dwc3_prepare_one_trb_linear(dep, req);
1205

1206
		if (!dwc3_calc_trbs_left(dep))
1207
			return;
1208 1209 1210
	}
}

1211
static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
1212 1213 1214
{
	struct dwc3_gadget_ep_cmd_params params;
	struct dwc3_request		*req;
1215
	int				starting;
1216 1217 1218
	int				ret;
	u32				cmd;

1219 1220 1221
	if (!dwc3_calc_trbs_left(dep))
		return 0;

1222
	starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED);
1223

1224 1225
	dwc3_prepare_trbs(dep);
	req = next_request(&dep->started_list);
1226 1227 1228 1229 1230 1231 1232
	if (!req) {
		dep->flags |= DWC3_EP_PENDING_REQUEST;
		return 0;
	}

	memset(&params, 0, sizeof(params));

1233
	if (starting) {
1234 1235
		params.param0 = upper_32_bits(req->trb_dma);
		params.param1 = lower_32_bits(req->trb_dma);
1236 1237
		cmd = DWC3_DEPCMD_STARTTRANSFER;

1238 1239 1240
		if (dep->stream_capable)
			cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id);

1241 1242
		if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
			cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
1243
	} else {
1244 1245
		cmd = DWC3_DEPCMD_UPDATETRANSFER |
			DWC3_DEPCMD_PARAM(dep->resource_index);
1246
	}
1247

1248
	ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1249 1250 1251 1252
	if (ret < 0) {
		/*
		 * FIXME we need to iterate over the list of requests
		 * here and stop, unmap, free and del each of the linked
1253
		 * requests instead of what we do now.
1254
		 */
1255 1256
		if (req->trb)
			memset(req->trb, 0, sizeof(struct dwc3_trb));
1257
		dwc3_gadget_del_and_unmap_request(dep, req, ret);
1258 1259 1260 1261 1262 1263
		return ret;
	}

	return 0;
}

1264 1265 1266 1267 1268 1269 1270 1271
static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
{
	u32			reg;

	reg = dwc3_readl(dwc->regs, DWC3_DSTS);
	return DWC3_DSTS_SOFFN(reg);
}

1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313
/**
 * dwc3_gadget_start_isoc_quirk - workaround invalid frame number
 * @dep: isoc endpoint
 *
 * This function tests for the correct combination of BIT[15:14] from the 16-bit
 * microframe number reported by the XferNotReady event for the future frame
 * number to start the isoc transfer.
 *
 * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed
 * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the
 * XferNotReady event are invalid. The driver uses this number to schedule the
 * isochronous transfer and passes it to the START TRANSFER command. Because
 * this number is invalid, the command may fail. If BIT[15:14] matches the
 * internal 16-bit microframe, the START TRANSFER command will pass and the
 * transfer will start at the scheduled time, if it is off by 1, the command
 * will still pass, but the transfer will start 2 seconds in the future. For all
 * other conditions, the START TRANSFER command will fail with bus-expiry.
 *
 * In order to workaround this issue, we can test for the correct combination of
 * BIT[15:14] by sending START TRANSFER commands with different values of
 * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart
 * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status.
 * As the result, within the 4 possible combinations for BIT[15:14], there will
 * be 2 successful and 2 failure START COMMAND status. One of the 2 successful
 * command status will result in a 2-second delay start. The smaller BIT[15:14]
 * value is the correct combination.
 *
 * Since there are only 4 outcomes and the results are ordered, we can simply
 * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to
 * deduce the smaller successful combination.
 *
 * Let test0 = test status for combination 'b00 and test1 = test status for 'b01
 * of BIT[15:14]. The correct combination is as follow:
 *
 * if test0 fails and test1 passes, BIT[15:14] is 'b01
 * if test0 fails and test1 fails, BIT[15:14] is 'b10
 * if test0 passes and test1 fails, BIT[15:14] is 'b11
 * if test0 passes and test1 passes, BIT[15:14] is 'b00
 *
 * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
 * endpoints.
 */
1314
static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep)
1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343
{
	int cmd_status = 0;
	bool test0;
	bool test1;

	while (dep->combo_num < 2) {
		struct dwc3_gadget_ep_cmd_params params;
		u32 test_frame_number;
		u32 cmd;

		/*
		 * Check if we can start isoc transfer on the next interval or
		 * 4 uframes in the future with BIT[15:14] as dep->combo_num
		 */
		test_frame_number = dep->frame_number & 0x3fff;
		test_frame_number |= dep->combo_num << 14;
		test_frame_number += max_t(u32, 4, dep->interval);

		params.param0 = upper_32_bits(dep->dwc->bounce_addr);
		params.param1 = lower_32_bits(dep->dwc->bounce_addr);

		cmd = DWC3_DEPCMD_STARTTRANSFER;
		cmd |= DWC3_DEPCMD_PARAM(test_frame_number);
		cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, &params);

		/* Redo if some other failure beside bus-expiry is received */
		if (cmd_status && cmd_status != -EAGAIN) {
			dep->start_cmd_status = 0;
			dep->combo_num = 0;
1344
			return 0;
1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358
		}

		/* Store the first test status */
		if (dep->combo_num == 0)
			dep->start_cmd_status = cmd_status;

		dep->combo_num++;

		/*
		 * End the transfer if the START_TRANSFER command is successful
		 * to wait for the next XferNotReady to test the command again
		 */
		if (cmd_status == 0) {
			dwc3_stop_active_transfer(dep, true);
1359
			return 0;
1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383
		}
	}

	/* test0 and test1 are both completed at this point */
	test0 = (dep->start_cmd_status == 0);
	test1 = (cmd_status == 0);

	if (!test0 && test1)
		dep->combo_num = 1;
	else if (!test0 && !test1)
		dep->combo_num = 2;
	else if (test0 && !test1)
		dep->combo_num = 3;
	else if (test0 && test1)
		dep->combo_num = 0;

	dep->frame_number &= 0x3fff;
	dep->frame_number |= dep->combo_num << 14;
	dep->frame_number += max_t(u32, 4, dep->interval);

	/* Reinitialize test variables */
	dep->start_cmd_status = 0;
	dep->combo_num = 0;

1384
	return __dwc3_gadget_kick_transfer(dep);
1385 1386
}

1387
static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep)
1388
{
1389
	struct dwc3 *dwc = dep->dwc;
1390 1391
	int ret;
	int i;
1392

1393
	if (list_empty(&dep->pending_list)) {
1394
		dep->flags |= DWC3_EP_PENDING_REQUEST;
1395
		return -EAGAIN;
1396 1397
	}

1398 1399 1400 1401 1402 1403
	if (!dwc->dis_start_transfer_quirk && dwc3_is_usb31(dwc) &&
	    (dwc->revision <= DWC3_USB31_REVISION_160A ||
	     (dwc->revision == DWC3_USB31_REVISION_170A &&
	      dwc->version_type >= DWC31_VERSIONTYPE_EA01 &&
	      dwc->version_type <= DWC31_VERSIONTYPE_EA06))) {

1404 1405
		if (dwc->gadget.speed <= USB_SPEED_HIGH && dep->direction)
			return dwc3_gadget_start_isoc_quirk(dep);
1406 1407
	}

1408 1409 1410 1411 1412 1413 1414 1415 1416
	for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) {
		dep->frame_number = DWC3_ALIGN_FRAME(dep, i + 1);

		ret = __dwc3_gadget_kick_transfer(dep);
		if (ret != -EAGAIN)
			break;
	}

	return ret;
1417 1418
}

1419 1420
static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
{
1421 1422
	struct dwc3		*dwc = dep->dwc;

1423
	if (!dep->endpoint.desc) {
1424 1425
		dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
				dep->name);
1426 1427 1428
		return -ESHUTDOWN;
	}

F
Felipe Balbi 已提交
1429 1430
	if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
				&req->request, req->dep->name))
1431 1432
		return -EINVAL;

F
Felipe Balbi 已提交
1433 1434
	pm_runtime_get(dwc->dev);

1435 1436 1437
	req->request.actual	= 0;
	req->request.status	= -EINPROGRESS;

1438 1439
	trace_dwc3_ep_queue(req);

1440
	list_add_tail(&req->list, &dep->pending_list);
1441

1442 1443 1444 1445 1446 1447 1448 1449 1450
	/*
	 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
	 * wait for a XferNotReady event so we will know what's the current
	 * (micro-)frame number.
	 *
	 * Without this trick, we are very, very likely gonna get Bus Expiry
	 * errors which will force us issue EndTransfer command.
	 */
	if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1451 1452 1453 1454
		if (!(dep->flags & DWC3_EP_PENDING_REQUEST) &&
				!(dep->flags & DWC3_EP_TRANSFER_STARTED))
			return 0;

1455
		if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1456
			if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) {
1457
				return __dwc3_gadget_start_isoc(dep);
1458
			}
1459
		}
1460
	}
1461

1462
	return __dwc3_gadget_kick_transfer(dep);
1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475
}

static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
	gfp_t gfp_flags)
{
	struct dwc3_request		*req = to_dwc3_request(request);
	struct dwc3_ep			*dep = to_dwc3_ep(ep);
	struct dwc3			*dwc = dep->dwc;

	unsigned long			flags;

	int				ret;

1476
	spin_lock_irqsave(&dwc->lock, flags);
1477 1478 1479 1480 1481 1482
	ret = __dwc3_gadget_ep_queue(dep, req);
	spin_unlock_irqrestore(&dwc->lock, flags);

	return ret;
}

1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505
static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req)
{
	int i;

	/*
	 * If request was already started, this means we had to
	 * stop the transfer. With that we also need to ignore
	 * all TRBs used by the request, however TRBs can only
	 * be modified after completion of END_TRANSFER
	 * command. So what we do here is that we wait for
	 * END_TRANSFER completion and only after that, we jump
	 * over TRBs by clearing HWO and incrementing dequeue
	 * pointer.
	 */
	for (i = 0; i < req->num_trbs; i++) {
		struct dwc3_trb *trb;

		trb = req->trb + i;
		trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
		dwc3_ep_inc_deq(dep);
	}
}

1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516
static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep)
{
	struct dwc3_request		*req;
	struct dwc3_request		*tmp;

	list_for_each_entry_safe(req, tmp, &dep->cancelled_list, list) {
		dwc3_gadget_ep_skip_trbs(dep, req);
		dwc3_gadget_giveback(dep, req, -ECONNRESET);
	}
}

1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528
static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
		struct usb_request *request)
{
	struct dwc3_request		*req = to_dwc3_request(request);
	struct dwc3_request		*r = NULL;

	struct dwc3_ep			*dep = to_dwc3_ep(ep);
	struct dwc3			*dwc = dep->dwc;

	unsigned long			flags;
	int				ret = 0;

1529 1530
	trace_dwc3_ep_dequeue(req);

1531 1532
	spin_lock_irqsave(&dwc->lock, flags);

1533
	list_for_each_entry(r, &dep->pending_list, list) {
1534 1535 1536 1537 1538
		if (r == req)
			break;
	}

	if (r != req) {
1539
		list_for_each_entry(r, &dep->started_list, list) {
1540 1541 1542 1543 1544
			if (r == req)
				break;
		}
		if (r == req) {
			/* wait until it is processed */
1545
			dwc3_stop_active_transfer(dep, true);
1546 1547

			if (!r->trb)
1548
				goto out0;
1549

1550 1551
			dwc3_gadget_move_cancelled_request(req);
			goto out0;
1552
		}
F
Felipe Balbi 已提交
1553
		dev_err(dwc->dev, "request %pK was not queued to %s\n",
1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566
				request, ep->name);
		ret = -EINVAL;
		goto out0;
	}

	dwc3_gadget_giveback(dep, req, -ECONNRESET);

out0:
	spin_unlock_irqrestore(&dwc->lock, flags);

	return ret;
}

1567
int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1568 1569 1570 1571 1572
{
	struct dwc3_gadget_ep_cmd_params	params;
	struct dwc3				*dwc = dep->dwc;
	int					ret;

1573 1574 1575 1576 1577
	if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
		dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
		return -EINVAL;
	}

1578 1579 1580
	memset(&params, 0x00, sizeof(params));

	if (value) {
1581 1582 1583 1584 1585
		struct dwc3_trb *trb;

		unsigned transfer_in_flight;
		unsigned started;

1586 1587 1588
		if (dep->flags & DWC3_EP_STALL)
			return 0;

1589 1590 1591 1592 1593 1594 1595 1596 1597 1598
		if (dep->number > 1)
			trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
		else
			trb = &dwc->ep0_trb[dep->trb_enqueue];

		transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
		started = !list_empty(&dep->started_list);

		if (!protocol && ((dep->direction && transfer_in_flight) ||
				(!dep->direction && started))) {
1599 1600 1601
			return -EAGAIN;
		}

1602 1603
		ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
				&params);
1604
		if (ret)
1605
			dev_err(dwc->dev, "failed to set STALL on %s\n",
1606 1607 1608 1609
					dep->name);
		else
			dep->flags |= DWC3_EP_STALL;
	} else {
1610 1611
		if (!(dep->flags & DWC3_EP_STALL))
			return 0;
1612

1613
		ret = dwc3_send_clear_stall_ep_cmd(dep);
1614
		if (ret)
1615
			dev_err(dwc->dev, "failed to clear STALL on %s\n",
1616 1617
					dep->name);
		else
1618
			dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1619
	}
1620

1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633
	return ret;
}

static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
{
	struct dwc3_ep			*dep = to_dwc3_ep(ep);
	struct dwc3			*dwc = dep->dwc;

	unsigned long			flags;

	int				ret;

	spin_lock_irqsave(&dwc->lock, flags);
1634
	ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1635 1636 1637 1638 1639 1640 1641 1642
	spin_unlock_irqrestore(&dwc->lock, flags);

	return ret;
}

static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
{
	struct dwc3_ep			*dep = to_dwc3_ep(ep);
1643 1644
	struct dwc3			*dwc = dep->dwc;
	unsigned long			flags;
1645
	int				ret;
1646

1647
	spin_lock_irqsave(&dwc->lock, flags);
1648 1649
	dep->flags |= DWC3_EP_WEDGE;

1650
	if (dep->number == 0 || dep->number == 1)
1651
		ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1652
	else
1653
		ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1654 1655 1656
	spin_unlock_irqrestore(&dwc->lock, flags);

	return ret;
1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673
}

/* -------------------------------------------------------------------------- */

static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
	.bLength	= USB_DT_ENDPOINT_SIZE,
	.bDescriptorType = USB_DT_ENDPOINT,
	.bmAttributes	= USB_ENDPOINT_XFER_CONTROL,
};

static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
	.enable		= dwc3_gadget_ep0_enable,
	.disable	= dwc3_gadget_ep0_disable,
	.alloc_request	= dwc3_gadget_ep_alloc_request,
	.free_request	= dwc3_gadget_ep_free_request,
	.queue		= dwc3_gadget_ep0_queue,
	.dequeue	= dwc3_gadget_ep_dequeue,
1674
	.set_halt	= dwc3_gadget_ep0_set_halt,
1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694
	.set_wedge	= dwc3_gadget_ep_set_wedge,
};

static const struct usb_ep_ops dwc3_gadget_ep_ops = {
	.enable		= dwc3_gadget_ep_enable,
	.disable	= dwc3_gadget_ep_disable,
	.alloc_request	= dwc3_gadget_ep_alloc_request,
	.free_request	= dwc3_gadget_ep_free_request,
	.queue		= dwc3_gadget_ep_queue,
	.dequeue	= dwc3_gadget_ep_dequeue,
	.set_halt	= dwc3_gadget_ep_set_halt,
	.set_wedge	= dwc3_gadget_ep_set_wedge,
};

/* -------------------------------------------------------------------------- */

static int dwc3_gadget_get_frame(struct usb_gadget *g)
{
	struct dwc3		*dwc = gadget_to_dwc(g);

1695
	return __dwc3_gadget_get_frame(dwc);
1696 1697
}

1698
static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1699
{
1700
	int			retries;
1701

1702
	int			ret;
1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716
	u32			reg;

	u8			link_state;
	u8			speed;

	/*
	 * According to the Databook Remote wakeup request should
	 * be issued only when the device is in early suspend state.
	 *
	 * We can check that via USB Link State bits in DSTS register.
	 */
	reg = dwc3_readl(dwc->regs, DWC3_DSTS);

	speed = reg & DWC3_DSTS_CONNECTSPD;
1717
	if ((speed == DWC3_DSTS_SUPERSPEED) ||
1718
	    (speed == DWC3_DSTS_SUPERSPEED_PLUS))
1719
		return 0;
1720 1721 1722 1723 1724 1725 1726 1727

	link_state = DWC3_DSTS_USBLNKST(reg);

	switch (link_state) {
	case DWC3_LINK_STATE_RX_DET:	/* in HS, means Early Suspend */
	case DWC3_LINK_STATE_U3:	/* in HS, means SUSPEND */
		break;
	default:
1728
		return -EINVAL;
1729 1730
	}

1731 1732 1733
	ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
	if (ret < 0) {
		dev_err(dwc->dev, "failed to put link in Recovery\n");
1734
		return ret;
1735
	}
1736

1737 1738 1739
	/* Recent versions do this automatically */
	if (dwc->revision < DWC3_REVISION_194A) {
		/* write zeroes to Link Change Request */
1740
		reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1741 1742 1743
		reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
		dwc3_writel(dwc->regs, DWC3_DCTL, reg);
	}
1744

1745
	/* poll until Link State changes to ON */
1746
	retries = 20000;
1747

1748
	while (retries--) {
1749 1750 1751 1752 1753 1754 1755 1756 1757
		reg = dwc3_readl(dwc->regs, DWC3_DSTS);

		/* in HS, means ON */
		if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
			break;
	}

	if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
		dev_err(dwc->dev, "failed to send remote wakeup\n");
1758
		return -EINVAL;
1759 1760
	}

1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771
	return 0;
}

static int dwc3_gadget_wakeup(struct usb_gadget *g)
{
	struct dwc3		*dwc = gadget_to_dwc(g);
	unsigned long		flags;
	int			ret;

	spin_lock_irqsave(&dwc->lock, flags);
	ret = __dwc3_gadget_wakeup(dwc);
1772 1773 1774 1775 1776 1777 1778 1779 1780
	spin_unlock_irqrestore(&dwc->lock, flags);

	return ret;
}

static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
		int is_selfpowered)
{
	struct dwc3		*dwc = gadget_to_dwc(g);
1781
	unsigned long		flags;
1782

1783
	spin_lock_irqsave(&dwc->lock, flags);
1784
	g->is_selfpowered = !!is_selfpowered;
1785
	spin_unlock_irqrestore(&dwc->lock, flags);
1786 1787 1788 1789

	return 0;
}

1790
static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1791 1792
{
	u32			reg;
1793
	u32			timeout = 500;
1794

F
Felipe Balbi 已提交
1795 1796 1797
	if (pm_runtime_suspended(dwc->dev))
		return 0;

1798
	reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1799
	if (is_on) {
1800 1801 1802 1803 1804 1805 1806 1807
		if (dwc->revision <= DWC3_REVISION_187A) {
			reg &= ~DWC3_DCTL_TRGTULST_MASK;
			reg |= DWC3_DCTL_TRGTULST_RX_DET;
		}

		if (dwc->revision >= DWC3_REVISION_194A)
			reg &= ~DWC3_DCTL_KEEP_CONNECT;
		reg |= DWC3_DCTL_RUN_STOP;
1808 1809 1810 1811

		if (dwc->has_hibernation)
			reg |= DWC3_DCTL_KEEP_CONNECT;

1812
		dwc->pullups_connected = true;
1813
	} else {
1814
		reg &= ~DWC3_DCTL_RUN_STOP;
1815 1816 1817 1818

		if (dwc->has_hibernation && !suspend)
			reg &= ~DWC3_DCTL_KEEP_CONNECT;

1819
		dwc->pullups_connected = false;
1820
	}
1821 1822 1823 1824 1825

	dwc3_writel(dwc->regs, DWC3_DCTL, reg);

	do {
		reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1826 1827
		reg &= DWC3_DSTS_DEVCTRLHLT;
	} while (--timeout && !(!is_on ^ !reg));
1828 1829 1830

	if (!timeout)
		return -ETIMEDOUT;
1831

1832
	return 0;
1833 1834 1835 1836 1837 1838
}

static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
{
	struct dwc3		*dwc = gadget_to_dwc(g);
	unsigned long		flags;
1839
	int			ret;
1840 1841 1842

	is_on = !!is_on;

1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857
	/*
	 * Per databook, when we want to stop the gadget, if a control transfer
	 * is still in process, complete it and get the core into setup phase.
	 */
	if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
		reinit_completion(&dwc->ep0_in_setup);

		ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
				msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
		if (ret == 0) {
			dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
			return -ETIMEDOUT;
		}
	}

1858
	spin_lock_irqsave(&dwc->lock, flags);
1859
	ret = dwc3_gadget_run_stop(dwc, is_on, false);
1860 1861
	spin_unlock_irqrestore(&dwc->lock, flags);

1862
	return ret;
1863 1864
}

1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878
static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
{
	u32			reg;

	/* Enable all but Start and End of Frame IRQs */
	reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
			DWC3_DEVTEN_EVNTOVERFLOWEN |
			DWC3_DEVTEN_CMDCMPLTEN |
			DWC3_DEVTEN_ERRTICERREN |
			DWC3_DEVTEN_WKUPEVTEN |
			DWC3_DEVTEN_CONNECTDONEEN |
			DWC3_DEVTEN_USBRSTEN |
			DWC3_DEVTEN_DISCONNEVTEN);

1879 1880 1881
	if (dwc->revision < DWC3_REVISION_250A)
		reg |= DWC3_DEVTEN_ULSTCNGEN;

1882 1883 1884 1885 1886 1887 1888 1889 1890 1891
	dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
}

static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
{
	/* mask all interrupts */
	dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
}

static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1892
static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1893

1894
/**
F
Felipe Balbi 已提交
1895 1896
 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
 * @dwc: pointer to our context structure
1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934
 *
 * The following looks like complex but it's actually very simple. In order to
 * calculate the number of packets we can burst at once on OUT transfers, we're
 * gonna use RxFIFO size.
 *
 * To calculate RxFIFO size we need two numbers:
 * MDWIDTH = size, in bits, of the internal memory bus
 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
 *
 * Given these two numbers, the formula is simple:
 *
 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
 *
 * 24 bytes is for 3x SETUP packets
 * 16 bytes is a clock domain crossing tolerance
 *
 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
 */
static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
{
	u32 ram2_depth;
	u32 mdwidth;
	u32 nump;
	u32 reg;

	ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
	mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);

	nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
	nump = min_t(u32, nump, 16);

	/* update NumP */
	reg = dwc3_readl(dwc->regs, DWC3_DCFG);
	reg &= ~DWC3_DCFG_NUMP_MASK;
	reg |= nump << DWC3_DCFG_NUMP_SHIFT;
	dwc3_writel(dwc->regs, DWC3_DCFG, reg);
}

1935
static int __dwc3_gadget_start(struct dwc3 *dwc)
1936 1937 1938 1939 1940
{
	struct dwc3_ep		*dep;
	int			ret = 0;
	u32			reg;

1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951
	/*
	 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
	 * the core supports IMOD, disable it.
	 */
	if (dwc->imod_interval) {
		dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
		dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
	} else if (dwc3_has_imod(dwc)) {
		dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
	}

1952 1953 1954 1955 1956 1957 1958 1959
	/*
	 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
	 * field instead of letting dwc3 itself calculate that automatically.
	 *
	 * This way, we maximize the chances that we'll be able to get several
	 * bursts of data without going through any sort of endpoint throttling.
	 */
	reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1960 1961 1962 1963 1964
	if (dwc3_is_usb31(dwc))
		reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
	else
		reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;

1965 1966
	dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);

1967 1968
	dwc3_gadget_setup_nump(dwc);

1969 1970 1971 1972
	/* Start with SuperSpeed Default */
	dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);

	dep = dwc->eps[0];
1973
	ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1974 1975
	if (ret) {
		dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1976
		goto err0;
1977 1978 1979
	}

	dep = dwc->eps[1];
1980
	ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1981 1982
	if (ret) {
		dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1983
		goto err1;
1984 1985 1986
	}

	/* begin to receive SETUP packets */
1987
	dwc->ep0state = EP0_SETUP_PHASE;
1988 1989
	dwc3_ep0_out_start(dwc);

1990 1991
	dwc3_gadget_enable_irq(dwc);

1992 1993
	return 0;

1994
err1:
1995
	__dwc3_gadget_ep_disable(dwc->eps[0]);
1996 1997

err0:
1998 1999 2000
	return ret;
}

2001 2002
static int dwc3_gadget_start(struct usb_gadget *g,
		struct usb_gadget_driver *driver)
2003 2004 2005
{
	struct dwc3		*dwc = gadget_to_dwc(g);
	unsigned long		flags;
2006
	int			ret = 0;
2007
	int			irq;
2008

2009
	irq = dwc->irq_gadget;
2010 2011 2012 2013 2014 2015 2016 2017
	ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
			IRQF_SHARED, "dwc3", dwc->ev_buf);
	if (ret) {
		dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
				irq, ret);
		goto err0;
	}

2018
	spin_lock_irqsave(&dwc->lock, flags);
2019 2020 2021 2022 2023 2024 2025 2026 2027 2028
	if (dwc->gadget_driver) {
		dev_err(dwc->dev, "%s is already bound to %s\n",
				dwc->gadget.name,
				dwc->gadget_driver->driver.name);
		ret = -EBUSY;
		goto err1;
	}

	dwc->gadget_driver	= driver;

F
Felipe Balbi 已提交
2029 2030 2031
	if (pm_runtime_active(dwc->dev))
		__dwc3_gadget_start(dwc);

2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042
	spin_unlock_irqrestore(&dwc->lock, flags);

	return 0;

err1:
	spin_unlock_irqrestore(&dwc->lock, flags);
	free_irq(irq, dwc);

err0:
	return ret;
}
2043

2044 2045
static void __dwc3_gadget_stop(struct dwc3 *dwc)
{
2046
	dwc3_gadget_disable_irq(dwc);
2047 2048
	__dwc3_gadget_ep_disable(dwc->eps[0]);
	__dwc3_gadget_ep_disable(dwc->eps[1]);
2049
}
2050

2051 2052 2053 2054
static int dwc3_gadget_stop(struct usb_gadget *g)
{
	struct dwc3		*dwc = gadget_to_dwc(g);
	unsigned long		flags;
2055

2056
	spin_lock_irqsave(&dwc->lock, flags);
2057 2058 2059 2060

	if (pm_runtime_suspended(dwc->dev))
		goto out;

2061
	__dwc3_gadget_stop(dwc);
2062 2063

out:
2064
	dwc->gadget_driver	= NULL;
2065 2066
	spin_unlock_irqrestore(&dwc->lock, flags);

2067
	free_irq(dwc->irq_gadget, dwc->ev_buf);
2068

2069 2070
	return 0;
}
2071

2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095
static void dwc3_gadget_set_speed(struct usb_gadget *g,
				  enum usb_device_speed speed)
{
	struct dwc3		*dwc = gadget_to_dwc(g);
	unsigned long		flags;
	u32			reg;

	spin_lock_irqsave(&dwc->lock, flags);
	reg = dwc3_readl(dwc->regs, DWC3_DCFG);
	reg &= ~(DWC3_DCFG_SPEED_MASK);

	/*
	 * WORKAROUND: DWC3 revision < 2.20a have an issue
	 * which would cause metastability state on Run/Stop
	 * bit if we try to force the IP to USB2-only mode.
	 *
	 * Because of that, we cannot configure the IP to any
	 * speed other than the SuperSpeed
	 *
	 * Refers to:
	 *
	 * STAR#9000525659: Clock Domain Crossing on DCTL in
	 * USB 2.0 Mode
	 */
2096 2097
	if (dwc->revision < DWC3_REVISION_220A &&
	    !dwc->dis_metastability_quirk) {
2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113
		reg |= DWC3_DCFG_SUPERSPEED;
	} else {
		switch (speed) {
		case USB_SPEED_LOW:
			reg |= DWC3_DCFG_LOWSPEED;
			break;
		case USB_SPEED_FULL:
			reg |= DWC3_DCFG_FULLSPEED;
			break;
		case USB_SPEED_HIGH:
			reg |= DWC3_DCFG_HIGHSPEED;
			break;
		case USB_SPEED_SUPER:
			reg |= DWC3_DCFG_SUPERSPEED;
			break;
		case USB_SPEED_SUPER_PLUS:
2114 2115 2116 2117
			if (dwc3_is_usb31(dwc))
				reg |= DWC3_DCFG_SUPERSPEED_PLUS;
			else
				reg |= DWC3_DCFG_SUPERSPEED;
2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132
			break;
		default:
			dev_err(dwc->dev, "invalid speed (%d)\n", speed);

			if (dwc->revision & DWC3_REVISION_IS_DWC31)
				reg |= DWC3_DCFG_SUPERSPEED_PLUS;
			else
				reg |= DWC3_DCFG_SUPERSPEED;
		}
	}
	dwc3_writel(dwc->regs, DWC3_DCFG, reg);

	spin_unlock_irqrestore(&dwc->lock, flags);
}

2133 2134 2135 2136 2137 2138 2139
static const struct usb_gadget_ops dwc3_gadget_ops = {
	.get_frame		= dwc3_gadget_get_frame,
	.wakeup			= dwc3_gadget_wakeup,
	.set_selfpowered	= dwc3_gadget_set_selfpowered,
	.pullup			= dwc3_gadget_pullup,
	.udc_start		= dwc3_gadget_start,
	.udc_stop		= dwc3_gadget_stop,
2140
	.udc_set_speed		= dwc3_gadget_set_speed,
2141 2142 2143 2144
};

/* -------------------------------------------------------------------------- */

2145
static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep)
2146
{
2147
	struct dwc3 *dwc = dep->dwc;
2148

2149 2150 2151 2152 2153
	usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
	dep->endpoint.maxburst = 1;
	dep->endpoint.ops = &dwc3_gadget_ep0_ops;
	if (!dep->direction)
		dwc->gadget.ep0 = &dep->endpoint;
2154

2155
	dep->endpoint.caps.type_control = true;
2156

2157 2158
	return 0;
}
2159

2160 2161 2162 2163 2164 2165
static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep)
{
	struct dwc3 *dwc = dep->dwc;
	int mdwidth;
	int kbytes;
	int size;
2166

2167 2168 2169
	mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
	/* MDWIDTH is represented in bits, we need it in bytes */
	mdwidth /= 8;
2170

2171 2172 2173 2174 2175
	size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1));
	if (dwc3_is_usb31(dwc))
		size = DWC31_GTXFIFOSIZ_TXFDEF(size);
	else
		size = DWC3_GTXFIFOSIZ_TXFDEF(size);
2176

2177 2178
	/* FIFO Depth is in MDWDITH bytes. Multiply */
	size *= mdwidth;
2179

2180 2181 2182
	kbytes = size / 1024;
	if (kbytes == 0)
		kbytes = 1;
2183

2184 2185 2186 2187 2188 2189 2190
	/*
	 * FIFO sizes account an extra MDWIDTH * (kbytes + 1) bytes for
	 * internal overhead. We don't really know how these are used,
	 * but documentation say it exists.
	 */
	size -= mdwidth * (kbytes + 1);
	size /= kbytes;
2191

2192
	usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2193

2194 2195 2196 2197 2198 2199 2200
	dep->endpoint.max_streams = 15;
	dep->endpoint.ops = &dwc3_gadget_ep_ops;
	list_add_tail(&dep->endpoint.ep_list,
			&dwc->gadget.ep_list);
	dep->endpoint.caps.type_iso = true;
	dep->endpoint.caps.type_bulk = true;
	dep->endpoint.caps.type_int = true;
2201

2202 2203
	return dwc3_alloc_trb_pool(dep);
}
2204

2205 2206 2207
static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep)
{
	struct dwc3 *dwc = dep->dwc;
2208

2209 2210 2211 2212 2213 2214 2215 2216
	usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
	dep->endpoint.max_streams = 15;
	dep->endpoint.ops = &dwc3_gadget_ep_ops;
	list_add_tail(&dep->endpoint.ep_list,
			&dwc->gadget.ep_list);
	dep->endpoint.caps.type_iso = true;
	dep->endpoint.caps.type_bulk = true;
	dep->endpoint.caps.type_int = true;
2217

2218 2219
	return dwc3_alloc_trb_pool(dep);
}
2220

2221 2222 2223 2224 2225 2226
static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum)
{
	struct dwc3_ep			*dep;
	bool				direction = epnum & 1;
	int				ret;
	u8				num = epnum >> 1;
2227

2228 2229 2230 2231 2232 2233 2234 2235 2236
	dep = kzalloc(sizeof(*dep), GFP_KERNEL);
	if (!dep)
		return -ENOMEM;

	dep->dwc = dwc;
	dep->number = epnum;
	dep->direction = direction;
	dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
	dwc->eps[epnum] = dep;
2237 2238
	dep->combo_num = 0;
	dep->start_cmd_status = 0;
2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260

	snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
			direction ? "in" : "out");

	dep->endpoint.name = dep->name;

	if (!(dep->number > 1)) {
		dep->endpoint.desc = &dwc3_gadget_ep0_desc;
		dep->endpoint.comp_desc = NULL;
	}

	spin_lock_init(&dep->lock);

	if (num == 0)
		ret = dwc3_gadget_init_control_endpoint(dep);
	else if (direction)
		ret = dwc3_gadget_init_in_endpoint(dep);
	else
		ret = dwc3_gadget_init_out_endpoint(dep);

	if (ret)
		return ret;
2261

2262 2263
	dep->endpoint.caps.dir_in = direction;
	dep->endpoint.caps.dir_out = !direction;
2264

2265 2266
	INIT_LIST_HEAD(&dep->pending_list);
	INIT_LIST_HEAD(&dep->started_list);
2267
	INIT_LIST_HEAD(&dep->cancelled_list);
2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283

	return 0;
}

static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
{
	u8				epnum;

	INIT_LIST_HEAD(&dwc->gadget.ep_list);

	for (epnum = 0; epnum < total; epnum++) {
		int			ret;

		ret = dwc3_gadget_init_endpoint(dwc, epnum);
		if (ret)
			return ret;
2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295
	}

	return 0;
}

static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
{
	struct dwc3_ep			*dep;
	u8				epnum;

	for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
		dep = dwc->eps[epnum];
2296 2297
		if (!dep)
			continue;
2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308
		/*
		 * Physical endpoints 0 and 1 are special; they form the
		 * bi-directional USB endpoint 0.
		 *
		 * For those two physical endpoints, we don't allocate a TRB
		 * pool nor do we add them the endpoints list. Due to that, we
		 * shouldn't do these two operations otherwise we would end up
		 * with all sorts of bugs when removing dwc3.ko.
		 */
		if (epnum != 0 && epnum != 1) {
			dwc3_free_trb_pool(dep);
2309
			list_del(&dep->endpoint.ep_list);
2310
		}
2311 2312 2313 2314 2315 2316

		kfree(dep);
	}
}

/* -------------------------------------------------------------------------- */
2317

2318 2319 2320
static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep,
		struct dwc3_request *req, struct dwc3_trb *trb,
		const struct dwc3_event_depevt *event, int status, int chain)
2321 2322 2323
{
	unsigned int		count;

2324
	dwc3_ep_inc_deq(dep);
2325

2326
	trace_dwc3_complete_trb(dep, trb);
2327
	req->num_trbs--;
2328

2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341
	/*
	 * If we're in the middle of series of chained TRBs and we
	 * receive a short transfer along the way, DWC3 will skip
	 * through all TRBs including the last TRB in the chain (the
	 * where CHN bit is zero. DWC3 will also avoid clearing HWO
	 * bit and SW has to do it manually.
	 *
	 * We're going to do that here to avoid problems of HW trying
	 * to use bogus TRBs for transfers.
	 */
	if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
		trb->ctrl &= ~DWC3_TRB_CTRL_HWO;

2342 2343 2344 2345 2346
	/*
	 * If we're dealing with unaligned size OUT transfer, we will be left
	 * with one TRB pending in the ring. We need to manually clear HWO bit
	 * from that TRB.
	 */
2347 2348

	if (req->needs_extra_trb && !(trb->ctrl & DWC3_TRB_CTRL_CHN)) {
2349 2350 2351 2352
		trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
		return 1;
	}

2353
	count = trb->size & DWC3_TRB_SIZE_MASK;
2354
	req->remaining += count;
2355

2356 2357 2358
	if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
		return 1;

2359
	if (event->status & DEPEVT_STATUS_SHORT && !chain)
2360
		return 1;
2361

2362
	if (event->status & DEPEVT_STATUS_IOC)
2363
		return 1;
2364

2365 2366 2367
	return 0;
}

2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406
static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep,
		struct dwc3_request *req, const struct dwc3_event_depevt *event,
		int status)
{
	struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
	struct scatterlist *sg = req->sg;
	struct scatterlist *s;
	unsigned int pending = req->num_pending_sgs;
	unsigned int i;
	int ret = 0;

	for_each_sg(sg, s, pending, i) {
		trb = &dep->trb_pool[dep->trb_dequeue];

		if (trb->ctrl & DWC3_TRB_CTRL_HWO)
			break;

		req->sg = sg_next(s);
		req->num_pending_sgs--;

		ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req,
				trb, event, status, true);
		if (ret)
			break;
	}

	return ret;
}

static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep,
		struct dwc3_request *req, const struct dwc3_event_depevt *event,
		int status)
{
	struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];

	return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb,
			event, status, false);
}

2407 2408 2409 2410 2411
static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req)
{
	return req->request.actual == req->request.length;
}

2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424
static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep,
		const struct dwc3_event_depevt *event,
		struct dwc3_request *req, int status)
{
	int ret;

	if (req->num_pending_sgs)
		ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event,
				status);
	else
		ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
				status);

2425
	if (req->needs_extra_trb) {
2426 2427
		ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
				status);
2428
		req->needs_extra_trb = false;
2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444
	}

	req->request.actual = req->request.length - req->remaining;

	if (!dwc3_gadget_ep_request_completed(req) &&
			req->num_pending_sgs) {
		__dwc3_gadget_kick_transfer(dep);
		goto out;
	}

	dwc3_gadget_giveback(dep, req, status);

out:
	return ret;
}

2445
static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep,
2446
		const struct dwc3_event_depevt *event, int status)
2447
{
2448 2449
	struct dwc3_request	*req;
	struct dwc3_request	*tmp;
2450

2451
	list_for_each_entry_safe(req, tmp, &dep->started_list, list) {
2452
		int ret;
2453

2454 2455
		ret = dwc3_gadget_ep_cleanup_completed_request(dep, event,
				req, status);
2456
		if (ret)
2457
			break;
2458
	}
2459 2460
}

2461 2462 2463
static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep,
		const struct dwc3_event_depevt *event)
{
2464
	dep->frame_number = event->parameters;
2465 2466
}

2467 2468
static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep,
		const struct dwc3_event_depevt *event)
2469
{
2470
	struct dwc3		*dwc = dep->dwc;
2471
	unsigned		status = 0;
2472
	bool			stop = false;
2473

2474 2475
	dwc3_gadget_endpoint_frame_from_event(dep, event);

2476 2477 2478
	if (event->status & DEPEVT_STATUS_BUSERR)
		status = -ECONNRESET;

2479 2480
	if (event->status & DEPEVT_STATUS_MISSED_ISOC) {
		status = -EXDEV;
2481 2482 2483

		if (list_empty(&dep->started_list))
			stop = true;
2484 2485
	}

2486
	dwc3_gadget_ep_cleanup_completed_requests(dep, event, status);
2487

2488 2489 2490 2491 2492
	if (stop) {
		dwc3_stop_active_transfer(dep, true);
		dep->flags = DWC3_EP_ENABLED;
	}

2493 2494 2495 2496 2497 2498 2499 2500 2501
	/*
	 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
	 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
	 */
	if (dwc->revision < DWC3_REVISION_183A) {
		u32		reg;
		int		i;

		for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2502
			dep = dwc->eps[i];
2503 2504 2505 2506

			if (!(dep->flags & DWC3_EP_ENABLED))
				continue;

2507
			if (!list_empty(&dep->started_list))
2508 2509 2510 2511 2512 2513 2514 2515 2516
				return;
		}

		reg = dwc3_readl(dwc->regs, DWC3_DCTL);
		reg |= dwc->u1u2;
		dwc3_writel(dwc->regs, DWC3_DCTL, reg);

		dwc->u1u2 = 0;
	}
2517 2518
}

2519 2520
static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep,
		const struct dwc3_event_depevt *event)
2521
{
2522
	dwc3_gadget_endpoint_frame_from_event(dep, event);
2523
	(void) __dwc3_gadget_start_isoc(dep);
2524 2525
}

2526 2527 2528 2529 2530
static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
		const struct dwc3_event_depevt *event)
{
	struct dwc3_ep		*dep;
	u8			epnum = event->endpoint_number;
2531
	u8			cmd;
2532 2533 2534

	dep = dwc->eps[epnum];

2535 2536 2537 2538 2539 2540 2541 2542
	if (!(dep->flags & DWC3_EP_ENABLED)) {
		if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
			return;

		/* Handle only EPCMDCMPLT when EP disabled */
		if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
			return;
	}
2543

2544 2545 2546 2547 2548 2549 2550
	if (epnum == 0 || epnum == 1) {
		dwc3_ep0_interrupt(dwc, event);
		return;
	}

	switch (event->endpoint_event) {
	case DWC3_DEPEVT_XFERINPROGRESS:
2551
		dwc3_gadget_endpoint_transfer_in_progress(dep, event);
2552 2553
		break;
	case DWC3_DEPEVT_XFERNOTREADY:
2554
		dwc3_gadget_endpoint_transfer_not_ready(dep, event);
2555
		break;
2556
	case DWC3_DEPEVT_EPCMDCMPLT:
2557 2558 2559 2560
		cmd = DEPEVT_PARAMETER_CMD(event->parameters);

		if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
			dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
2561
			dwc3_gadget_ep_cleanup_cancelled_requests(dep);
2562 2563
		}
		break;
2564
	case DWC3_DEPEVT_STREAMEVT:
2565
	case DWC3_DEPEVT_XFERCOMPLETE:
2566
	case DWC3_DEPEVT_RXTXFIFOEVT:
2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579
		break;
	}
}

static void dwc3_disconnect_gadget(struct dwc3 *dwc)
{
	if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
		spin_unlock(&dwc->lock);
		dwc->gadget_driver->disconnect(&dwc->gadget);
		spin_lock(&dwc->lock);
	}
}

2580 2581
static void dwc3_suspend_gadget(struct dwc3 *dwc)
{
2582
	if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2583 2584 2585 2586 2587 2588 2589 2590
		spin_unlock(&dwc->lock);
		dwc->gadget_driver->suspend(&dwc->gadget);
		spin_lock(&dwc->lock);
	}
}

static void dwc3_resume_gadget(struct dwc3 *dwc)
{
2591
	if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2592 2593
		spin_unlock(&dwc->lock);
		dwc->gadget_driver->resume(&dwc->gadget);
2594
		spin_lock(&dwc->lock);
2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605
	}
}

static void dwc3_reset_gadget(struct dwc3 *dwc)
{
	if (!dwc->gadget_driver)
		return;

	if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
		spin_unlock(&dwc->lock);
		usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2606 2607 2608 2609
		spin_lock(&dwc->lock);
	}
}

2610
static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force)
2611
{
2612
	struct dwc3 *dwc = dep->dwc;
2613 2614 2615 2616
	struct dwc3_gadget_ep_cmd_params params;
	u32 cmd;
	int ret;

2617 2618
	if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
	    !dep->resource_index)
2619 2620
		return;

2621 2622 2623 2624 2625 2626 2627 2628 2629
	/*
	 * NOTICE: We are violating what the Databook says about the
	 * EndTransfer command. Ideally we would _always_ wait for the
	 * EndTransfer Command Completion IRQ, but that's causing too
	 * much trouble synchronizing between us and gadget driver.
	 *
	 * We have discussed this with the IP Provider and it was
	 * suggested to giveback all requests here, but give HW some
	 * extra time to synchronize with the interconnect. We're using
2630
	 * an arbitrary 100us delay for that.
2631 2632 2633 2634 2635 2636 2637
	 *
	 * Note also that a similar handling was tested by Synopsys
	 * (thanks a lot Paul) and nothing bad has come out of it.
	 * In short, what we're doing is:
	 *
	 * - Issue EndTransfer WITH CMDIOC bit set
	 * - Wait 100us
2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649
	 *
	 * As of IP version 3.10a of the DWC_usb3 IP, the controller
	 * supports a mode to work around the above limitation. The
	 * software can poll the CMDACT bit in the DEPCMD register
	 * after issuing a EndTransfer command. This mode is enabled
	 * by writing GUCTL2[14]. This polling is already done in the
	 * dwc3_send_gadget_ep_cmd() function so if the mode is
	 * enabled, the EndTransfer command will have completed upon
	 * returning from this function and we don't need to delay for
	 * 100us.
	 *
	 * This mode is NOT available on the DWC_usb31 IP.
2650 2651
	 */

2652
	cmd = DWC3_DEPCMD_ENDTRANSFER;
2653 2654
	cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
	cmd |= DWC3_DEPCMD_CMDIOC;
2655
	cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2656
	memset(&params, 0, sizeof(params));
2657
	ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
2658
	WARN_ON_ONCE(ret);
2659
	dep->resource_index = 0;
2660

2661 2662
	if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) {
		dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
2663
		udelay(100);
2664
	}
2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675
}

static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
{
	u32 epnum;

	for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
		struct dwc3_ep *dep;
		int ret;

		dep = dwc->eps[epnum];
2676 2677
		if (!dep)
			continue;
2678 2679 2680 2681 2682 2683

		if (!(dep->flags & DWC3_EP_STALL))
			continue;

		dep->flags &= ~DWC3_EP_STALL;

2684
		ret = dwc3_send_clear_stall_ep_cmd(dep);
2685 2686 2687 2688 2689 2690
		WARN_ON_ONCE(ret);
	}
}

static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
{
2691 2692
	int			reg;

2693 2694 2695 2696 2697 2698 2699 2700 2701 2702
	reg = dwc3_readl(dwc->regs, DWC3_DCTL);
	reg &= ~DWC3_DCTL_INITU1ENA;
	dwc3_writel(dwc->regs, DWC3_DCTL, reg);

	reg &= ~DWC3_DCTL_INITU2ENA;
	dwc3_writel(dwc->regs, DWC3_DCTL, reg);

	dwc3_disconnect_gadget(dwc);

	dwc->gadget.speed = USB_SPEED_UNKNOWN;
2703
	dwc->setup_packet_pending = false;
2704
	usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
F
Felipe Balbi 已提交
2705 2706

	dwc->connected = false;
2707 2708 2709 2710 2711 2712
}

static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
{
	u32			reg;

F
Felipe Balbi 已提交
2713 2714
	dwc->connected = true;

2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731
	/*
	 * WORKAROUND: DWC3 revisions <1.88a have an issue which
	 * would cause a missing Disconnect Event if there's a
	 * pending Setup Packet in the FIFO.
	 *
	 * There's no suggested workaround on the official Bug
	 * report, which states that "unless the driver/application
	 * is doing any special handling of a disconnect event,
	 * there is no functional issue".
	 *
	 * Unfortunately, it turns out that we _do_ some special
	 * handling of a disconnect event, namely complete all
	 * pending transfers, notify gadget driver of the
	 * disconnection, and so on.
	 *
	 * Our suggested workaround is to follow the Disconnect
	 * Event steps here, instead, based on a setup_packet_pending
2732 2733
	 * flag. Such flag gets set whenever we have a SETUP_PENDING
	 * status for EP0 TRBs and gets cleared on XferComplete for the
2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745
	 * same endpoint.
	 *
	 * Refers to:
	 *
	 * STAR#9000466709: RTL: Device : Disconnect event not
	 * generated if setup packet pending in FIFO
	 */
	if (dwc->revision < DWC3_REVISION_188A) {
		if (dwc->setup_packet_pending)
			dwc3_gadget_disconnect_interrupt(dwc);
	}

2746
	dwc3_reset_gadget(dwc);
2747 2748 2749 2750

	reg = dwc3_readl(dwc->regs, DWC3_DCTL);
	reg &= ~DWC3_DCTL_TSTCTRL_MASK;
	dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2751
	dwc->test_mode = false;
2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767 2768 2769 2770
	dwc3_clear_stall_all_ep(dwc);

	/* Reset device address to zero */
	reg = dwc3_readl(dwc->regs, DWC3_DCFG);
	reg &= ~(DWC3_DCFG_DEVADDR_MASK);
	dwc3_writel(dwc->regs, DWC3_DCFG, reg);
}

static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
{
	struct dwc3_ep		*dep;
	int			ret;
	u32			reg;
	u8			speed;

	reg = dwc3_readl(dwc->regs, DWC3_DSTS);
	speed = reg & DWC3_DSTS_CONNECTSPD;
	dwc->speed = speed;

2771 2772 2773 2774 2775 2776 2777 2778
	/*
	 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
	 * each time on Connect Done.
	 *
	 * Currently we always use the reset value. If any platform
	 * wants to set this to a different value, we need to add a
	 * setting and update GCTL.RAMCLKSEL here.
	 */
2779 2780

	switch (speed) {
2781
	case DWC3_DSTS_SUPERSPEED_PLUS:
J
John Youn 已提交
2782 2783 2784 2785
		dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
		dwc->gadget.ep0->maxpacket = 512;
		dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
		break;
2786
	case DWC3_DSTS_SUPERSPEED:
2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 2802
		/*
		 * WORKAROUND: DWC3 revisions <1.90a have an issue which
		 * would cause a missing USB3 Reset event.
		 *
		 * In such situations, we should force a USB3 Reset
		 * event by calling our dwc3_gadget_reset_interrupt()
		 * routine.
		 *
		 * Refers to:
		 *
		 * STAR#9000483510: RTL: SS : USB3 reset event may
		 * not be generated always when the link enters poll
		 */
		if (dwc->revision < DWC3_REVISION_190A)
			dwc3_gadget_reset_interrupt(dwc);

2803 2804 2805 2806
		dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
		dwc->gadget.ep0->maxpacket = 512;
		dwc->gadget.speed = USB_SPEED_SUPER;
		break;
2807
	case DWC3_DSTS_HIGHSPEED:
2808 2809 2810 2811
		dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
		dwc->gadget.ep0->maxpacket = 64;
		dwc->gadget.speed = USB_SPEED_HIGH;
		break;
2812
	case DWC3_DSTS_FULLSPEED:
2813 2814 2815 2816
		dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
		dwc->gadget.ep0->maxpacket = 64;
		dwc->gadget.speed = USB_SPEED_FULL;
		break;
2817
	case DWC3_DSTS_LOWSPEED:
2818 2819 2820 2821 2822 2823
		dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
		dwc->gadget.ep0->maxpacket = 8;
		dwc->gadget.speed = USB_SPEED_LOW;
		break;
	}

2824 2825
	dwc->eps[1]->endpoint.maxpacket = dwc->gadget.ep0->maxpacket;

2826 2827
	/* Enable USB2 LPM Capability */

2828
	if ((dwc->revision > DWC3_REVISION_194A) &&
2829 2830
	    (speed != DWC3_DSTS_SUPERSPEED) &&
	    (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2831 2832 2833 2834 2835 2836 2837
		reg = dwc3_readl(dwc->regs, DWC3_DCFG);
		reg |= DWC3_DCFG_LPM_CAP;
		dwc3_writel(dwc->regs, DWC3_DCFG, reg);

		reg = dwc3_readl(dwc->regs, DWC3_DCTL);
		reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);

2838
		reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2839

H
Huang Rui 已提交
2840 2841 2842 2843 2844 2845 2846 2847
		/*
		 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
		 * DCFG.LPMCap is set, core responses with an ACK and the
		 * BESL value in the LPM token is less than or equal to LPM
		 * NYET threshold.
		 */
		WARN_ONCE(dwc->revision < DWC3_REVISION_240A
				&& dwc->has_lpm_erratum,
2848
				"LPM Erratum not available on dwc3 revisions < 2.40a\n");
H
Huang Rui 已提交
2849 2850 2851 2852

		if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
			reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);

2853 2854 2855 2856
		dwc3_writel(dwc->regs, DWC3_DCTL, reg);
	} else {
		reg = dwc3_readl(dwc->regs, DWC3_DCTL);
		reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2857 2858 2859
		dwc3_writel(dwc->regs, DWC3_DCTL, reg);
	}

2860
	dep = dwc->eps[0];
2861
	ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
2862 2863 2864 2865 2866 2867
	if (ret) {
		dev_err(dwc->dev, "failed to enable %s\n", dep->name);
		return;
	}

	dep = dwc->eps[1];
2868
	ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
2869 2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889
	if (ret) {
		dev_err(dwc->dev, "failed to enable %s\n", dep->name);
		return;
	}

	/*
	 * Configure PHY via GUSB3PIPECTLn if required.
	 *
	 * Update GTXFIFOSIZn
	 *
	 * In both cases reset values should be sufficient.
	 */
}

static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
{
	/*
	 * TODO take core out of low power mode when that's
	 * implemented.
	 */

2890 2891 2892 2893 2894
	if (dwc->gadget_driver && dwc->gadget_driver->resume) {
		spin_unlock(&dwc->lock);
		dwc->gadget_driver->resume(&dwc->gadget);
		spin_lock(&dwc->lock);
	}
2895 2896 2897 2898 2899
}

static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
		unsigned int evtinfo)
{
2900
	enum dwc3_link_state	next = evtinfo & DWC3_LINK_STATE_MASK;
2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927
	unsigned int		pwropt;

	/*
	 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
	 * Hibernation mode enabled which would show up when device detects
	 * host-initiated U3 exit.
	 *
	 * In that case, device will generate a Link State Change Interrupt
	 * from U3 to RESUME which is only necessary if Hibernation is
	 * configured in.
	 *
	 * There are no functional changes due to such spurious event and we
	 * just need to ignore it.
	 *
	 * Refers to:
	 *
	 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
	 * operational mode
	 */
	pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
	if ((dwc->revision < DWC3_REVISION_250A) &&
			(pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
		if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
				(next == DWC3_LINK_STATE_RESUME)) {
			return;
		}
	}
2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 2956 2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974

	/*
	 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
	 * on the link partner, the USB session might do multiple entry/exit
	 * of low power states before a transfer takes place.
	 *
	 * Due to this problem, we might experience lower throughput. The
	 * suggested workaround is to disable DCTL[12:9] bits if we're
	 * transitioning from U1/U2 to U0 and enable those bits again
	 * after a transfer completes and there are no pending transfers
	 * on any of the enabled endpoints.
	 *
	 * This is the first half of that workaround.
	 *
	 * Refers to:
	 *
	 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
	 * core send LGO_Ux entering U0
	 */
	if (dwc->revision < DWC3_REVISION_183A) {
		if (next == DWC3_LINK_STATE_U0) {
			u32	u1u2;
			u32	reg;

			switch (dwc->link_state) {
			case DWC3_LINK_STATE_U1:
			case DWC3_LINK_STATE_U2:
				reg = dwc3_readl(dwc->regs, DWC3_DCTL);
				u1u2 = reg & (DWC3_DCTL_INITU2ENA
						| DWC3_DCTL_ACCEPTU2ENA
						| DWC3_DCTL_INITU1ENA
						| DWC3_DCTL_ACCEPTU1ENA);

				if (!dwc->u1u2)
					dwc->u1u2 = reg & u1u2;

				reg &= ~u1u2;

				dwc3_writel(dwc->regs, DWC3_DCTL, reg);
				break;
			default:
				/* do nothing */
				break;
			}
		}
	}

2975 2976 2977 2978 2979 2980 2981 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991
	switch (next) {
	case DWC3_LINK_STATE_U1:
		if (dwc->speed == USB_SPEED_SUPER)
			dwc3_suspend_gadget(dwc);
		break;
	case DWC3_LINK_STATE_U2:
	case DWC3_LINK_STATE_U3:
		dwc3_suspend_gadget(dwc);
		break;
	case DWC3_LINK_STATE_RESUME:
		dwc3_resume_gadget(dwc);
		break;
	default:
		/* do nothing */
		break;
	}

2992
	dwc->link_state = next;
2993 2994
}

2995 2996 2997 2998 2999 3000 3001 3002 3003 3004 3005
static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
					  unsigned int evtinfo)
{
	enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;

	if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
		dwc3_suspend_gadget(dwc);

	dwc->link_state = next;
}

3006 3007 3008 3009 3010
static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
		unsigned int evtinfo)
{
	unsigned int is_ss = evtinfo & BIT(4);

F
Felipe Balbi 已提交
3011
	/*
3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 3027 3028 3029
	 * WORKAROUND: DWC3 revison 2.20a with hibernation support
	 * have a known issue which can cause USB CV TD.9.23 to fail
	 * randomly.
	 *
	 * Because of this issue, core could generate bogus hibernation
	 * events which SW needs to ignore.
	 *
	 * Refers to:
	 *
	 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
	 * Device Fallback from SuperSpeed
	 */
	if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
		return;

	/* enter hibernation here */
}

3030 3031 3032 3033 3034 3035 3036 3037 3038 3039 3040 3041 3042 3043 3044 3045
static void dwc3_gadget_interrupt(struct dwc3 *dwc,
		const struct dwc3_event_devt *event)
{
	switch (event->type) {
	case DWC3_DEVICE_EVENT_DISCONNECT:
		dwc3_gadget_disconnect_interrupt(dwc);
		break;
	case DWC3_DEVICE_EVENT_RESET:
		dwc3_gadget_reset_interrupt(dwc);
		break;
	case DWC3_DEVICE_EVENT_CONNECT_DONE:
		dwc3_gadget_conndone_interrupt(dwc);
		break;
	case DWC3_DEVICE_EVENT_WAKEUP:
		dwc3_gadget_wakeup_interrupt(dwc);
		break;
3046 3047 3048 3049 3050 3051 3052
	case DWC3_DEVICE_EVENT_HIBER_REQ:
		if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
					"unexpected hibernation event\n"))
			break;

		dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
		break;
3053 3054 3055 3056
	case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
		dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
		break;
	case DWC3_DEVICE_EVENT_EOPF:
3057
		/* It changed to be suspend event for version 2.30a and above */
3058
		if (dwc->revision >= DWC3_REVISION_230A) {
3059 3060 3061 3062 3063 3064 3065 3066
			/*
			 * Ignore suspend event until the gadget enters into
			 * USB_STATE_CONFIGURED state.
			 */
			if (dwc->gadget.state >= USB_STATE_CONFIGURED)
				dwc3_gadget_suspend_interrupt(dwc,
						event->event_info);
		}
3067 3068 3069 3070 3071 3072 3073
		break;
	case DWC3_DEVICE_EVENT_SOF:
	case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
	case DWC3_DEVICE_EVENT_CMD_CMPL:
	case DWC3_DEVICE_EVENT_OVERFLOW:
		break;
	default:
3074
		dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
3075 3076 3077 3078 3079 3080
	}
}

static void dwc3_process_event_entry(struct dwc3 *dwc,
		const union dwc3_event *event)
{
3081
	trace_dwc3_event(event->raw, dwc);
3082

3083 3084 3085
	if (!event->type.is_devspec)
		dwc3_endpoint_interrupt(dwc, &event->depevt);
	else if (event->type.type == DWC3_EVENT_TYPE_DEV)
3086
		dwc3_gadget_interrupt(dwc, &event->devt);
3087
	else
3088 3089 3090
		dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
}

3091
static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
3092
{
3093
	struct dwc3 *dwc = evt->dwc;
3094
	irqreturn_t ret = IRQ_NONE;
3095
	int left;
3096
	u32 reg;
3097

3098
	left = evt->count;
3099

3100 3101
	if (!(evt->flags & DWC3_EVENT_PENDING))
		return IRQ_NONE;
3102

3103 3104
	while (left > 0) {
		union dwc3_event event;
3105

3106
		event.raw = *(u32 *) (evt->cache + evt->lpos);
3107

3108
		dwc3_process_event_entry(dwc, &event);
3109

3110 3111 3112 3113 3114 3115 3116 3117 3118
		/*
		 * FIXME we wrap around correctly to the next entry as
		 * almost all entries are 4 bytes in size. There is one
		 * entry which has 12 bytes which is a regular entry
		 * followed by 8 bytes data. ATM I don't know how
		 * things are organized if we get next to the a
		 * boundary so I worry about that once we try to handle
		 * that.
		 */
3119
		evt->lpos = (evt->lpos + 4) % evt->length;
3120 3121
		left -= 4;
	}
3122

3123 3124 3125
	evt->count = 0;
	evt->flags &= ~DWC3_EVENT_PENDING;
	ret = IRQ_HANDLED;
3126

3127
	/* Unmask interrupt */
3128
	reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3129
	reg &= ~DWC3_GEVNTSIZ_INTMASK;
3130
	dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3131

3132 3133 3134 3135 3136
	if (dwc->imod_interval) {
		dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
		dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
	}

3137 3138
	return ret;
}
3139

3140
static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
3141
{
3142 3143
	struct dwc3_event_buffer *evt = _evt;
	struct dwc3 *dwc = evt->dwc;
3144
	unsigned long flags;
3145 3146
	irqreturn_t ret = IRQ_NONE;

3147
	spin_lock_irqsave(&dwc->lock, flags);
3148
	ret = dwc3_process_event_buf(evt);
3149
	spin_unlock_irqrestore(&dwc->lock, flags);
3150 3151 3152 3153

	return ret;
}

3154
static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
3155
{
3156
	struct dwc3 *dwc = evt->dwc;
3157
	u32 amount;
3158
	u32 count;
3159
	u32 reg;
3160

F
Felipe Balbi 已提交
3161 3162 3163 3164 3165 3166 3167
	if (pm_runtime_suspended(dwc->dev)) {
		pm_runtime_get(dwc->dev);
		disable_irq_nosync(dwc->irq_gadget);
		dwc->pending_events = true;
		return IRQ_HANDLED;
	}

3168 3169 3170 3171 3172 3173 3174 3175 3176
	/*
	 * With PCIe legacy interrupt, test shows that top-half irq handler can
	 * be called again after HW interrupt deassertion. Check if bottom-half
	 * irq event handler completes before caching new event to prevent
	 * losing events.
	 */
	if (evt->flags & DWC3_EVENT_PENDING)
		return IRQ_HANDLED;

3177
	count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
3178 3179 3180 3181
	count &= DWC3_GEVNTCOUNT_MASK;
	if (!count)
		return IRQ_NONE;

3182 3183
	evt->count = count;
	evt->flags |= DWC3_EVENT_PENDING;
3184

3185
	/* Mask interrupt */
3186
	reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3187
	reg |= DWC3_GEVNTSIZ_INTMASK;
3188
	dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3189

3190 3191 3192 3193 3194 3195
	amount = min(count, evt->length - evt->lpos);
	memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);

	if (amount < count)
		memcpy(evt->cache, evt->buf, count - amount);

3196 3197
	dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);

3198
	return IRQ_WAKE_THREAD;
3199 3200
}

3201
static irqreturn_t dwc3_interrupt(int irq, void *_evt)
3202
{
3203
	struct dwc3_event_buffer	*evt = _evt;
3204

3205
	return dwc3_check_event_buf(evt);
3206 3207
}

3208 3209 3210 3211 3212 3213 3214 3215 3216 3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238 3239 3240
static int dwc3_gadget_get_irq(struct dwc3 *dwc)
{
	struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
	int irq;

	irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
	if (irq > 0)
		goto out;

	if (irq == -EPROBE_DEFER)
		goto out;

	irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3");
	if (irq > 0)
		goto out;

	if (irq == -EPROBE_DEFER)
		goto out;

	irq = platform_get_irq(dwc3_pdev, 0);
	if (irq > 0)
		goto out;

	if (irq != -EPROBE_DEFER)
		dev_err(dwc->dev, "missing peripheral IRQ\n");

	if (!irq)
		irq = -EINVAL;

out:
	return irq;
}

3241
/**
F
Felipe Balbi 已提交
3242
 * dwc3_gadget_init - initializes gadget related registers
3243
 * @dwc: pointer to our controller context structure
3244 3245 3246
 *
 * Returns 0 on success otherwise negative errno.
 */
B
Bill Pemberton 已提交
3247
int dwc3_gadget_init(struct dwc3 *dwc)
3248
{
3249 3250
	int ret;
	int irq;
3251

3252 3253 3254 3255
	irq = dwc3_gadget_get_irq(dwc);
	if (irq < 0) {
		ret = irq;
		goto err0;
3256 3257 3258
	}

	dwc->irq_gadget = irq;
3259

3260 3261 3262
	dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
					  sizeof(*dwc->ep0_trb) * 2,
					  &dwc->ep0_trb_addr, GFP_KERNEL);
3263 3264 3265
	if (!dwc->ep0_trb) {
		dev_err(dwc->dev, "failed to allocate ep0 trb\n");
		ret = -ENOMEM;
3266
		goto err0;
3267 3268
	}

3269
	dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
3270 3271
	if (!dwc->setup_buf) {
		ret = -ENOMEM;
3272
		goto err1;
3273 3274
	}

3275 3276 3277 3278
	dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
			&dwc->bounce_addr, GFP_KERNEL);
	if (!dwc->bounce) {
		ret = -ENOMEM;
F
Felipe Balbi 已提交
3279
		goto err2;
3280 3281
	}

3282 3283
	init_completion(&dwc->ep0_in_setup);

3284 3285
	dwc->gadget.ops			= &dwc3_gadget_ops;
	dwc->gadget.speed		= USB_SPEED_UNKNOWN;
3286
	dwc->gadget.sg_supported	= true;
3287
	dwc->gadget.name		= "dwc3-gadget";
3288
	dwc->gadget.is_otg		= dwc->dr_mode == USB_DR_MODE_OTG;
3289

3290 3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305
	/*
	 * FIXME We might be setting max_speed to <SUPER, however versions
	 * <2.20a of dwc3 have an issue with metastability (documented
	 * elsewhere in this driver) which tells us we can't set max speed to
	 * anything lower than SUPER.
	 *
	 * Because gadget.max_speed is only used by composite.c and function
	 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
	 * to happen so we avoid sending SuperSpeed Capability descriptor
	 * together with our BOS descriptor as that could confuse host into
	 * thinking we can handle super speed.
	 *
	 * Note that, in fact, we won't even support GetBOS requests when speed
	 * is less than super speed because we don't have means, yet, to tell
	 * composite.c that we are USB 2.0 + LPM ECN.
	 */
3306 3307
	if (dwc->revision < DWC3_REVISION_220A &&
	    !dwc->dis_metastability_quirk)
3308
		dev_info(dwc->dev, "changing max_speed on rev %08x\n",
3309 3310 3311 3312
				dwc->revision);

	dwc->gadget.max_speed		= dwc->maximum_speed;

3313 3314 3315 3316 3317
	/*
	 * REVISIT: Here we should clear all pending IRQs to be
	 * sure we're starting from a well known location.
	 */

3318
	ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
3319
	if (ret)
F
Felipe Balbi 已提交
3320
		goto err3;
3321 3322 3323 3324

	ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
	if (ret) {
		dev_err(dwc->dev, "failed to register udc\n");
F
Felipe Balbi 已提交
3325
		goto err4;
3326 3327 3328 3329
	}

	return 0;

3330
err4:
F
Felipe Balbi 已提交
3331
	dwc3_gadget_free_endpoints(dwc);
3332

3333
err3:
F
Felipe Balbi 已提交
3334 3335
	dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
			dwc->bounce_addr);
3336

3337
err2:
3338
	kfree(dwc->setup_buf);
3339

3340
err1:
3341
	dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3342 3343 3344 3345 3346 3347
			dwc->ep0_trb, dwc->ep0_trb_addr);

err0:
	return ret;
}

3348 3349
/* -------------------------------------------------------------------------- */

3350 3351 3352 3353
void dwc3_gadget_exit(struct dwc3 *dwc)
{
	usb_del_gadget_udc(&dwc->gadget);
	dwc3_gadget_free_endpoints(dwc);
3354
	dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
F
Felipe Balbi 已提交
3355
			  dwc->bounce_addr);
3356
	kfree(dwc->setup_buf);
3357
	dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
F
Felipe Balbi 已提交
3358
			  dwc->ep0_trb, dwc->ep0_trb_addr);
3359
}
3360

3361
int dwc3_gadget_suspend(struct dwc3 *dwc)
3362
{
3363 3364 3365
	if (!dwc->gadget_driver)
		return 0;

3366
	dwc3_gadget_run_stop(dwc, false, false);
3367 3368
	dwc3_disconnect_gadget(dwc);
	__dwc3_gadget_stop(dwc);
3369 3370 3371 3372 3373 3374 3375 3376

	return 0;
}

int dwc3_gadget_resume(struct dwc3 *dwc)
{
	int			ret;

3377 3378 3379
	if (!dwc->gadget_driver)
		return 0;

3380 3381
	ret = __dwc3_gadget_start(dwc);
	if (ret < 0)
3382 3383
		goto err0;

3384 3385
	ret = dwc3_gadget_run_stop(dwc, true, false);
	if (ret < 0)
3386 3387 3388 3389 3390
		goto err1;

	return 0;

err1:
3391
	__dwc3_gadget_stop(dwc);
3392 3393 3394 3395

err0:
	return ret;
}
F
Felipe Balbi 已提交
3396 3397 3398 3399 3400 3401 3402 3403 3404

void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
{
	if (dwc->pending_events) {
		dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
		dwc->pending_events = false;
		enable_irq(dwc->irq_gadget);
	}
}