amdgpu_vm.c 76.1 KB
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/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
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#include <linux/dma-fence-array.h>
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#include <linux/interval_tree_generic.h>
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#include <linux/idr.h>
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#include <drm/drmP.h>
#include <drm/amdgpu_drm.h>
#include "amdgpu.h"
#include "amdgpu_trace.h"
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#include "amdgpu_amdkfd.h"
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#include "amdgpu_gmc.h"
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/**
 * DOC: GPUVM
 *
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 * GPUVM is similar to the legacy gart on older asics, however
 * rather than there being a single global gart table
 * for the entire GPU, there are multiple VM page tables active
 * at any given time.  The VM page tables can contain a mix
 * vram pages and system memory pages and system memory pages
 * can be mapped as snooped (cached system pages) or unsnooped
 * (uncached system pages).
 * Each VM has an ID associated with it and there is a page table
 * associated with each VMID.  When execting a command buffer,
 * the kernel tells the the ring what VMID to use for that command
 * buffer.  VMIDs are allocated dynamically as commands are submitted.
 * The userspace drivers maintain their own address space and the kernel
 * sets up their pages tables accordingly when they submit their
 * command buffers and a VMID is assigned.
 * Cayman/Trinity support up to 8 active VMs at any given time;
 * SI supports 16.
 */

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#define START(node) ((node)->start)
#define LAST(node) ((node)->last)

INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
		     START, LAST, static, amdgpu_vm_it)

#undef START
#undef LAST

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/**
 * struct amdgpu_pte_update_params - Local structure
 *
 * Encapsulate some VM table update parameters to reduce
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 * the number of function parameters
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 *
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 */
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struct amdgpu_pte_update_params {
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	/**
	 * @adev: amdgpu device we do this update for
	 */
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	struct amdgpu_device *adev;
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	/**
	 * @vm: optional amdgpu_vm we do this update for
	 */
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	struct amdgpu_vm *vm;
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	/**
	 * @src: address where to copy page table entries from
	 */
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	uint64_t src;
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	/**
	 * @ib: indirect buffer to fill with commands
	 */
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	struct amdgpu_ib *ib;
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	/**
	 * @func: Function which actually does the update
	 */
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	void (*func)(struct amdgpu_pte_update_params *params,
		     struct amdgpu_bo *bo, uint64_t pe,
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		     uint64_t addr, unsigned count, uint32_t incr,
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		     uint64_t flags);
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	/**
	 * @pages_addr:
	 *
	 * DMA addresses to use for mapping, used during VM update by CPU
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	 */
	dma_addr_t *pages_addr;
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	/**
	 * @kptr:
	 *
	 * Kernel pointer of PD/PT BO that needs to be updated,
	 * used during VM update by CPU
	 */
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	void *kptr;
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};

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/**
 * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback
 */
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struct amdgpu_prt_cb {
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	/**
	 * @adev: amdgpu device
	 */
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	struct amdgpu_device *adev;
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	/**
	 * @cb: callback
	 */
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	struct dma_fence_cb cb;
};

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/**
 * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm
 *
 * @base: base structure for tracking BO usage in a VM
 * @vm: vm to which bo is to be added
 * @bo: amdgpu buffer object
 *
 * Initialize a bo_va_base structure and add it to the appropriate lists
 *
 */
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static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
				   struct amdgpu_vm *vm,
				   struct amdgpu_bo *bo)
{
	base->vm = vm;
	base->bo = bo;
	INIT_LIST_HEAD(&base->bo_list);
	INIT_LIST_HEAD(&base->vm_status);

	if (!bo)
		return;
	list_add_tail(&base->bo_list, &bo->va);

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	if (bo->tbo.type == ttm_bo_type_kernel)
		list_move(&base->vm_status, &vm->relocated);

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	if (bo->tbo.resv != vm->root.base.bo->tbo.resv)
		return;

	if (bo->preferred_domains &
	    amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type))
		return;

	/*
	 * we checked all the prerequisites, but it looks like this per vm bo
	 * is currently evicted. add the bo to the evicted list to make sure it
	 * is validated on next vm use to avoid fault.
	 * */
	list_move_tail(&base->vm_status, &vm->evicted);
}

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/**
 * amdgpu_vm_level_shift - return the addr shift for each level
 *
 * @adev: amdgpu_device pointer
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 * @level: VMPT level
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 *
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 * Returns:
 * The number of bits the pfn needs to be right shifted for a level.
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 */
static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev,
				      unsigned level)
{
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	unsigned shift = 0xff;

	switch (level) {
	case AMDGPU_VM_PDB2:
	case AMDGPU_VM_PDB1:
	case AMDGPU_VM_PDB0:
		shift = 9 * (AMDGPU_VM_PDB0 - level) +
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			adev->vm_manager.block_size;
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		break;
	case AMDGPU_VM_PTB:
		shift = 0;
		break;
	default:
		dev_err(adev->dev, "the level%d isn't supported.\n", level);
	}

	return shift;
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}

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/**
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 * amdgpu_vm_num_entries - return the number of entries in a PD/PT
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 *
 * @adev: amdgpu_device pointer
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 * @level: VMPT level
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 *
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 * Returns:
 * The number of entries in a page directory or page table.
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 */
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static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
				      unsigned level)
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{
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	unsigned shift = amdgpu_vm_level_shift(adev,
					       adev->vm_manager.root_level);
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	if (level == adev->vm_manager.root_level)
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		/* For the root directory */
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		return round_up(adev->vm_manager.max_pfn, 1 << shift) >> shift;
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	else if (level != AMDGPU_VM_PTB)
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		/* Everything in between */
		return 512;
	else
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		/* For the page tables on the leaves */
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		return AMDGPU_VM_PTE_COUNT(adev);
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}

/**
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 * amdgpu_vm_bo_size - returns the size of the BOs in bytes
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 *
 * @adev: amdgpu_device pointer
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 * @level: VMPT level
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 *
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 * Returns:
 * The size of the BO for a page directory or page table in bytes.
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 */
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static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level)
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{
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	return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8);
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}

/**
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 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
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 *
 * @vm: vm providing the BOs
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 * @validated: head of validation list
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 * @entry: entry to add
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 *
 * Add the page directory to the list of BOs to
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 * validate for command submission.
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 */
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void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
			 struct list_head *validated,
			 struct amdgpu_bo_list_entry *entry)
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{
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	entry->robj = vm->root.base.bo;
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	entry->priority = 0;
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	entry->tv.bo = &entry->robj->tbo;
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	entry->tv.shared = true;
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	entry->user_pages = NULL;
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	list_add(&entry->tv.head, validated);
}
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/**
 * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU
 *
 * @adev: amdgpu device pointer
 * @vm: vm providing the BOs
 *
 * Move all BOs to the end of LRU and remember their positions to put them
 * together.
 */
void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
				struct amdgpu_vm *vm)
{
	struct ttm_bo_global *glob = adev->mman.bdev.glob;
	struct amdgpu_vm_bo_base *bo_base;

	if (vm->bulk_moveable) {
		spin_lock(&glob->lru_lock);
		ttm_bo_bulk_move_lru_tail(&vm->lru_bulk_move);
		spin_unlock(&glob->lru_lock);
		return;
	}

	memset(&vm->lru_bulk_move, 0, sizeof(vm->lru_bulk_move));

	spin_lock(&glob->lru_lock);
	list_for_each_entry(bo_base, &vm->idle, vm_status) {
		struct amdgpu_bo *bo = bo_base->bo;

		if (!bo->parent)
			continue;

		ttm_bo_move_to_lru_tail(&bo->tbo, &vm->lru_bulk_move);
		if (bo->shadow)
			ttm_bo_move_to_lru_tail(&bo->shadow->tbo,
						&vm->lru_bulk_move);
	}
	spin_unlock(&glob->lru_lock);

	vm->bulk_moveable = true;
}

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/**
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 * amdgpu_vm_validate_pt_bos - validate the page table BOs
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 *
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 * @adev: amdgpu device pointer
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 * @vm: vm providing the BOs
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 * @validate: callback to do the validation
 * @param: parameter for the validation callback
 *
 * Validate the page table BOs on command submission if neccessary.
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 *
 * Returns:
 * Validation result.
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 */
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int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
			      int (*validate)(void *p, struct amdgpu_bo *bo),
			      void *param)
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{
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	struct amdgpu_vm_bo_base *bo_base, *tmp;
	int r = 0;
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	vm->bulk_moveable &= list_empty(&vm->evicted);

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	list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) {
		struct amdgpu_bo *bo = bo_base->bo;
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		r = validate(param, bo);
		if (r)
			break;
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		if (bo->tbo.type != ttm_bo_type_kernel) {
			spin_lock(&vm->moved_lock);
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			list_move(&bo_base->vm_status, &vm->moved);
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			spin_unlock(&vm->moved_lock);
		} else {
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			list_move(&bo_base->vm_status, &vm->relocated);
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		}
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	}

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	return r;
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}

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/**
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 * amdgpu_vm_ready - check VM is ready for updates
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 *
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 * @vm: VM to check
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 *
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 * Check if all VM PDs/PTs are ready for updates
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 *
 * Returns:
 * True if eviction list is empty.
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 */
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bool amdgpu_vm_ready(struct amdgpu_vm *vm)
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{
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	return list_empty(&vm->evicted);
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}

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/**
 * amdgpu_vm_clear_bo - initially clear the PDs/PTs
 *
 * @adev: amdgpu_device pointer
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 * @vm: VM to clear BO from
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 * @bo: BO to clear
 * @level: level this BO is at
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 * @pte_support_ats: indicate ATS support from PTE
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 *
 * Root PD needs to be reserved when calling this.
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 *
 * Returns:
 * 0 on success, errno otherwise.
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 */
static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
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			      struct amdgpu_vm *vm, struct amdgpu_bo *bo,
			      unsigned level, bool pte_support_ats)
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{
	struct ttm_operation_ctx ctx = { true, false };
	struct dma_fence *fence = NULL;
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	unsigned entries, ats_entries;
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	struct amdgpu_ring *ring;
	struct amdgpu_job *job;
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	uint64_t addr;
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	int r;

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	entries = amdgpu_bo_size(bo) / 8;

	if (pte_support_ats) {
		if (level == adev->vm_manager.root_level) {
			ats_entries = amdgpu_vm_level_shift(adev, level);
			ats_entries += AMDGPU_GPU_PAGE_SHIFT;
			ats_entries = AMDGPU_VA_HOLE_START >> ats_entries;
			ats_entries = min(ats_entries, entries);
			entries -= ats_entries;
		} else {
			ats_entries = entries;
			entries = 0;
		}
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	} else {
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		ats_entries = 0;
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	}

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	ring = container_of(vm->entity.rq->sched, struct amdgpu_ring, sched);
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	r = reservation_object_reserve_shared(bo->tbo.resv);
	if (r)
		return r;

	r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
	if (r)
		goto error;

	r = amdgpu_job_alloc_with_ib(adev, 64, &job);
	if (r)
		goto error;

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	addr = amdgpu_bo_gpu_offset(bo);
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	if (ats_entries) {
		uint64_t ats_value;

		ats_value = AMDGPU_PTE_DEFAULT_ATC;
		if (level != AMDGPU_VM_PTB)
			ats_value |= AMDGPU_PDE_PTE;

		amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0,
				      ats_entries, 0, ats_value);
		addr += ats_entries * 8;
	}

	if (entries)
		amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0,
				      entries, 0, 0);

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	amdgpu_ring_pad_ib(ring, &job->ibs[0]);

	WARN_ON(job->ibs[0].length_dw > 64);
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	r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.resv,
			     AMDGPU_FENCE_OWNER_UNDEFINED, false);
	if (r)
		goto error_free;

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	r = amdgpu_job_submit(job, &vm->entity, AMDGPU_FENCE_OWNER_UNDEFINED,
			      &fence);
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	if (r)
		goto error_free;

	amdgpu_bo_fence(bo, fence, true);
	dma_fence_put(fence);
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	if (bo->shadow)
		return amdgpu_vm_clear_bo(adev, vm, bo->shadow,
					  level, pte_support_ats);

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	return 0;

error_free:
	amdgpu_job_free(job);

error:
	return r;
}

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/**
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 * amdgpu_vm_alloc_levels - allocate the PD/PT levels
 *
 * @adev: amdgpu_device pointer
 * @vm: requested vm
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 * @parent: parent PT
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 * @saddr: start of the address range
 * @eaddr: end of the address range
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 * @level: VMPT level
 * @ats: indicate ATS support from PTE
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 *
 * Make sure the page directories and page tables are allocated
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 *
 * Returns:
 * 0 on success, errno otherwise.
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 */
static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
				  struct amdgpu_vm *vm,
				  struct amdgpu_vm_pt *parent,
				  uint64_t saddr, uint64_t eaddr,
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				  unsigned level, bool ats)
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{
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	unsigned shift = amdgpu_vm_level_shift(adev, level);
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	unsigned pt_idx, from, to;
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	u64 flags;
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	int r;
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	if (!parent->entries) {
		unsigned num_entries = amdgpu_vm_num_entries(adev, level);

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		parent->entries = kvmalloc_array(num_entries,
						   sizeof(struct amdgpu_vm_pt),
						   GFP_KERNEL | __GFP_ZERO);
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		if (!parent->entries)
			return -ENOMEM;
		memset(parent->entries, 0 , sizeof(struct amdgpu_vm_pt));
	}

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	from = saddr >> shift;
	to = eaddr >> shift;
	if (from >= amdgpu_vm_num_entries(adev, level) ||
	    to >= amdgpu_vm_num_entries(adev, level))
		return -EINVAL;
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	++level;
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	saddr = saddr & ((1 << shift) - 1);
	eaddr = eaddr & ((1 << shift) - 1);
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	flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
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	if (vm->root.base.bo->shadow)
		flags |= AMDGPU_GEM_CREATE_SHADOW;
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	if (vm->use_cpu_for_update)
		flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
	else
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		flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
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	/* walk over the address space and allocate the page tables */
	for (pt_idx = from; pt_idx <= to; ++pt_idx) {
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		struct reservation_object *resv = vm->root.base.bo->tbo.resv;
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		struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
		struct amdgpu_bo *pt;

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		if (!entry->base.bo) {
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			struct amdgpu_bo_param bp;

			memset(&bp, 0, sizeof(bp));
			bp.size = amdgpu_vm_bo_size(adev, level);
			bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
			bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
			bp.flags = flags;
			bp.type = ttm_bo_type_kernel;
			bp.resv = resv;
			r = amdgpu_bo_create(adev, &bp, &pt);
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			if (r)
				return r;

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			r = amdgpu_vm_clear_bo(adev, vm, pt, level, ats);
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			if (r) {
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				amdgpu_bo_unref(&pt->shadow);
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				amdgpu_bo_unref(&pt);
				return r;
			}

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			if (vm->use_cpu_for_update) {
				r = amdgpu_bo_kmap(pt, NULL);
				if (r) {
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					amdgpu_bo_unref(&pt->shadow);
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					amdgpu_bo_unref(&pt);
					return r;
				}
			}

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			/* Keep a reference to the root directory to avoid
			* freeing them up in the wrong order.
			*/
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			pt->parent = amdgpu_bo_ref(parent->base.bo);
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			amdgpu_vm_bo_base_init(&entry->base, vm, pt);
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		}

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		if (level < AMDGPU_VM_PTB) {
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			uint64_t sub_saddr = (pt_idx == from) ? saddr : 0;
			uint64_t sub_eaddr = (pt_idx == to) ? eaddr :
				((1 << shift) - 1);
			r = amdgpu_vm_alloc_levels(adev, vm, entry, sub_saddr,
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						   sub_eaddr, level, ats);
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			if (r)
				return r;
		}
	}

	return 0;
}

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/**
 * amdgpu_vm_alloc_pts - Allocate page tables.
 *
 * @adev: amdgpu_device pointer
 * @vm: VM to allocate page tables for
 * @saddr: Start address which needs to be allocated
 * @size: Size from start address we need.
 *
 * Make sure the page tables are allocated.
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 *
 * Returns:
 * 0 on success, errno otherwise.
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 */
int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
			struct amdgpu_vm *vm,
			uint64_t saddr, uint64_t size)
{
	uint64_t eaddr;
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	bool ats = false;
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	/* validate the parameters */
	if (saddr & AMDGPU_GPU_PAGE_MASK || size & AMDGPU_GPU_PAGE_MASK)
		return -EINVAL;

	eaddr = saddr + size - 1;
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	if (vm->pte_support_ats)
		ats = saddr < AMDGPU_VA_HOLE_START;
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	saddr /= AMDGPU_GPU_PAGE_SIZE;
	eaddr /= AMDGPU_GPU_PAGE_SIZE;

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	if (eaddr >= adev->vm_manager.max_pfn) {
		dev_err(adev->dev, "va above limit (0x%08llX >= 0x%08llX)\n",
			eaddr, adev->vm_manager.max_pfn);
		return -EINVAL;
	}

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	return amdgpu_vm_alloc_levels(adev, vm, &vm->root, saddr, eaddr,
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				      adev->vm_manager.root_level, ats);
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}

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/**
 * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
 *
 * @adev: amdgpu_device pointer
 */
void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
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{
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	const struct amdgpu_ip_block *ip_block;
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	bool has_compute_vm_bug;
	struct amdgpu_ring *ring;
	int i;
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	has_compute_vm_bug = false;
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	ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
641 642 643 644 645 646 647 648 649
	if (ip_block) {
		/* Compute has a VM bug for GFX version < 7.
		   Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
		if (ip_block->version->major <= 7)
			has_compute_vm_bug = true;
		else if (ip_block->version->major == 8)
			if (adev->gfx.mec_fw_version < 673)
				has_compute_vm_bug = true;
	}
650

651 652 653 654 655
	for (i = 0; i < adev->num_rings; i++) {
		ring = adev->rings[i];
		if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
			/* only compute rings */
			ring->has_compute_vm_bug = has_compute_vm_bug;
656
		else
657
			ring->has_compute_vm_bug = false;
658 659 660
	}
}

661 662 663 664 665 666 667 668 669
/**
 * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job.
 *
 * @ring: ring on which the job will be submitted
 * @job: job to submit
 *
 * Returns:
 * True if sync is needed.
 */
670 671
bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
				  struct amdgpu_job *job)
A
Alex Xie 已提交
672
{
673 674
	struct amdgpu_device *adev = ring->adev;
	unsigned vmhub = ring->funcs->vmhub;
675 676
	struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
	struct amdgpu_vmid *id;
677
	bool gds_switch_needed;
678
	bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug;
679

680
	if (job->vmid == 0)
681
		return false;
682
	id = &id_mgr->ids[job->vmid];
683 684 685 686 687 688 689
	gds_switch_needed = ring->funcs->emit_gds_switch && (
		id->gds_base != job->gds_base ||
		id->gds_size != job->gds_size ||
		id->gws_base != job->gws_base ||
		id->gws_size != job->gws_size ||
		id->oa_base != job->oa_base ||
		id->oa_size != job->oa_size);
A
Alex Xie 已提交
690

691
	if (amdgpu_vmid_had_gpu_reset(adev, id))
692
		return true;
A
Alex Xie 已提交
693

694
	return vm_flush_needed || gds_switch_needed;
695 696
}

A
Alex Deucher 已提交
697 698 699 700
/**
 * amdgpu_vm_flush - hardware flush the vm
 *
 * @ring: ring to use for flush
701
 * @job:  related job
702
 * @need_pipe_sync: is pipe sync needed
A
Alex Deucher 已提交
703
 *
704
 * Emit a VM flush when it is necessary.
705 706 707
 *
 * Returns:
 * 0 on success, errno otherwise.
A
Alex Deucher 已提交
708
 */
M
Monk Liu 已提交
709
int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync)
A
Alex Deucher 已提交
710
{
711
	struct amdgpu_device *adev = ring->adev;
712
	unsigned vmhub = ring->funcs->vmhub;
713
	struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
714
	struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
715
	bool gds_switch_needed = ring->funcs->emit_gds_switch && (
716 717 718 719 720 721
		id->gds_base != job->gds_base ||
		id->gds_size != job->gds_size ||
		id->gws_base != job->gws_base ||
		id->gws_size != job->gws_size ||
		id->oa_base != job->oa_base ||
		id->oa_size != job->oa_size);
722
	bool vm_flush_needed = job->vm_needs_flush;
723 724 725 726
	bool pasid_mapping_needed = id->pasid != job->pasid ||
		!id->pasid_mapping ||
		!dma_fence_is_signaled(id->pasid_mapping);
	struct dma_fence *fence = NULL;
727
	unsigned patch_offset = 0;
728
	int r;
729

730
	if (amdgpu_vmid_had_gpu_reset(adev, id)) {
731 732
		gds_switch_needed = true;
		vm_flush_needed = true;
733
		pasid_mapping_needed = true;
734
	}
735

736 737 738 739 740
	gds_switch_needed &= !!ring->funcs->emit_gds_switch;
	vm_flush_needed &= !!ring->funcs->emit_vm_flush;
	pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping &&
		ring->funcs->emit_wreg;

M
Monk Liu 已提交
741
	if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync)
742
		return 0;
743

744 745
	if (ring->funcs->init_cond_exec)
		patch_offset = amdgpu_ring_init_cond_exec(ring);
746

M
Monk Liu 已提交
747 748 749
	if (need_pipe_sync)
		amdgpu_ring_emit_pipeline_sync(ring);

750
	if (vm_flush_needed) {
751
		trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
752
		amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
753 754 755 756
	}

	if (pasid_mapping_needed)
		amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
757

758
	if (vm_flush_needed || pasid_mapping_needed) {
759
		r = amdgpu_fence_emit(ring, &fence, 0);
760 761
		if (r)
			return r;
762
	}
763

764
	if (vm_flush_needed) {
765
		mutex_lock(&id_mgr->lock);
766
		dma_fence_put(id->last_flush);
767 768 769
		id->last_flush = dma_fence_get(fence);
		id->current_gpu_reset_count =
			atomic_read(&adev->gpu_reset_counter);
770
		mutex_unlock(&id_mgr->lock);
771
	}
772

773 774 775 776 777 778 779
	if (pasid_mapping_needed) {
		id->pasid = job->pasid;
		dma_fence_put(id->pasid_mapping);
		id->pasid_mapping = dma_fence_get(fence);
	}
	dma_fence_put(fence);

780
	if (ring->funcs->emit_gds_switch && gds_switch_needed) {
781 782 783 784 785 786
		id->gds_base = job->gds_base;
		id->gds_size = job->gds_size;
		id->gws_base = job->gws_base;
		id->gws_size = job->gws_size;
		id->oa_base = job->oa_base;
		id->oa_size = job->oa_size;
787
		amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
788 789 790 791 792 793 794 795 796 797 798 799
					    job->gds_size, job->gws_base,
					    job->gws_size, job->oa_base,
					    job->oa_size);
	}

	if (ring->funcs->patch_cond_exec)
		amdgpu_ring_patch_cond_exec(ring, patch_offset);

	/* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
	if (ring->funcs->emit_switch_buffer) {
		amdgpu_ring_emit_switch_buffer(ring);
		amdgpu_ring_emit_switch_buffer(ring);
800
	}
801
	return 0;
802 803
}

A
Alex Deucher 已提交
804 805 806 807 808 809
/**
 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
 *
 * @vm: requested vm
 * @bo: requested buffer object
 *
810
 * Find @bo inside the requested vm.
A
Alex Deucher 已提交
811 812 813 814
 * Search inside the @bos vm list for the requested vm
 * Returns the found bo_va or NULL if none is found
 *
 * Object has to be reserved!
815 816 817
 *
 * Returns:
 * Found bo_va or NULL.
A
Alex Deucher 已提交
818 819 820 821 822 823
 */
struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
				       struct amdgpu_bo *bo)
{
	struct amdgpu_bo_va *bo_va;

824 825
	list_for_each_entry(bo_va, &bo->va, base.bo_list) {
		if (bo_va->base.vm == vm) {
A
Alex Deucher 已提交
826 827 828 829 830 831 832
			return bo_va;
		}
	}
	return NULL;
}

/**
833
 * amdgpu_vm_do_set_ptes - helper to call the right asic function
A
Alex Deucher 已提交
834
 *
835
 * @params: see amdgpu_pte_update_params definition
836
 * @bo: PD/PT to update
A
Alex Deucher 已提交
837 838 839 840 841 842 843 844 845
 * @pe: addr of the page entry
 * @addr: dst addr to write into pe
 * @count: number of page entries to update
 * @incr: increase next addr by incr bytes
 * @flags: hw access flags
 *
 * Traces the parameters and calls the right asic functions
 * to setup the page table using the DMA.
 */
846
static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params,
847
				  struct amdgpu_bo *bo,
848 849
				  uint64_t pe, uint64_t addr,
				  unsigned count, uint32_t incr,
850
				  uint64_t flags)
A
Alex Deucher 已提交
851
{
852
	pe += amdgpu_bo_gpu_offset(bo);
853
	trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);
A
Alex Deucher 已提交
854

855
	if (count < 3) {
856 857
		amdgpu_vm_write_pte(params->adev, params->ib, pe,
				    addr | flags, count, incr);
A
Alex Deucher 已提交
858 859

	} else {
860
		amdgpu_vm_set_pte_pde(params->adev, params->ib, pe, addr,
A
Alex Deucher 已提交
861 862 863 864
				      count, incr, flags);
	}
}

865 866 867 868
/**
 * amdgpu_vm_do_copy_ptes - copy the PTEs from the GART
 *
 * @params: see amdgpu_pte_update_params definition
869
 * @bo: PD/PT to update
870 871 872 873 874 875 876 877 878
 * @pe: addr of the page entry
 * @addr: dst addr to write into pe
 * @count: number of page entries to update
 * @incr: increase next addr by incr bytes
 * @flags: hw access flags
 *
 * Traces the parameters and calls the DMA function to copy the PTEs.
 */
static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params,
879
				   struct amdgpu_bo *bo,
880 881
				   uint64_t pe, uint64_t addr,
				   unsigned count, uint32_t incr,
882
				   uint64_t flags)
883
{
884
	uint64_t src = (params->src + (addr >> 12) * 8);
885

886
	pe += amdgpu_bo_gpu_offset(bo);
887 888 889
	trace_amdgpu_vm_copy_ptes(pe, src, count);

	amdgpu_vm_copy_pte(params->adev, params->ib, pe, src, count);
890 891
}

A
Alex Deucher 已提交
892
/**
893
 * amdgpu_vm_map_gart - Resolve gart mapping of addr
A
Alex Deucher 已提交
894
 *
895
 * @pages_addr: optional DMA address to use for lookup
A
Alex Deucher 已提交
896 897 898
 * @addr: the unmapped addr
 *
 * Look up the physical address of the page that the pte resolves
899 900 901 902
 * to.
 *
 * Returns:
 * The pointer for the page table entry.
A
Alex Deucher 已提交
903
 */
904
static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
A
Alex Deucher 已提交
905 906 907
{
	uint64_t result;

908 909
	/* page table offset */
	result = pages_addr[addr >> PAGE_SHIFT];
910

911 912
	/* in case cpu page size != gpu page size*/
	result |= addr & (~PAGE_MASK);
A
Alex Deucher 已提交
913

914
	result &= 0xFFFFFFFFFFFFF000ULL;
A
Alex Deucher 已提交
915 916 917 918

	return result;
}

919 920 921 922
/**
 * amdgpu_vm_cpu_set_ptes - helper to update page tables via CPU
 *
 * @params: see amdgpu_pte_update_params definition
923
 * @bo: PD/PT to update
924 925 926 927 928 929 930 931 932
 * @pe: kmap addr of the page entry
 * @addr: dst addr to write into pe
 * @count: number of page entries to update
 * @incr: increase next addr by incr bytes
 * @flags: hw access flags
 *
 * Write count number of PT/PD entries directly.
 */
static void amdgpu_vm_cpu_set_ptes(struct amdgpu_pte_update_params *params,
933
				   struct amdgpu_bo *bo,
934 935 936 937 938
				   uint64_t pe, uint64_t addr,
				   unsigned count, uint32_t incr,
				   uint64_t flags)
{
	unsigned int i;
939
	uint64_t value;
940

941 942
	pe += (unsigned long)amdgpu_bo_kptr(bo);

943 944
	trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);

945
	for (i = 0; i < count; i++) {
946 947 948
		value = params->pages_addr ?
			amdgpu_vm_map_gart(params->pages_addr, addr) :
			addr;
949 950
		amdgpu_gmc_set_pte_pde(params->adev, (void *)(uintptr_t)pe,
				       i, value, flags);
951 952 953 954
		addr += incr;
	}
}

955 956 957 958 959 960 961 962 963 964 965

/**
 * amdgpu_vm_wait_pd - Wait for PT BOs to be free.
 *
 * @adev: amdgpu_device pointer
 * @vm: related vm
 * @owner: fence owner
 *
 * Returns:
 * 0 on success, errno otherwise.
 */
966 967
static int amdgpu_vm_wait_pd(struct amdgpu_device *adev, struct amdgpu_vm *vm,
			     void *owner)
968 969 970 971 972
{
	struct amdgpu_sync sync;
	int r;

	amdgpu_sync_create(&sync);
973
	amdgpu_sync_resv(adev, &sync, vm->root.base.bo->tbo.resv, owner, false);
974 975 976 977 978 979
	r = amdgpu_sync_wait(&sync, true);
	amdgpu_sync_free(&sync);

	return r;
}

980
/*
981
 * amdgpu_vm_update_pde - update a single level in the hierarchy
982
 *
983
 * @param: parameters for the update
984
 * @vm: requested vm
985
 * @parent: parent directory
986
 * @entry: entry to update
987
 *
988
 * Makes sure the requested entry in parent is up to date.
989
 */
990 991 992 993
static void amdgpu_vm_update_pde(struct amdgpu_pte_update_params *params,
				 struct amdgpu_vm *vm,
				 struct amdgpu_vm_pt *parent,
				 struct amdgpu_vm_pt *entry)
A
Alex Deucher 已提交
994
{
995
	struct amdgpu_bo *bo = parent->base.bo, *pbo;
996 997
	uint64_t pde, pt, flags;
	unsigned level;
C
Chunming Zhou 已提交
998

999 1000 1001
	/* Don't update huge pages here */
	if (entry->huge)
		return;
A
Alex Deucher 已提交
1002

1003
	for (level = 0, pbo = bo->parent; pbo; ++level)
1004 1005
		pbo = pbo->parent;

1006
	level += params->adev->vm_manager.root_level;
1007
	pt = amdgpu_bo_gpu_offset(entry->base.bo);
1008
	flags = AMDGPU_PTE_VALID;
1009
	amdgpu_gmc_get_vm_pde(params->adev, level, &pt, &flags);
1010 1011 1012 1013
	pde = (entry - parent->entries) * 8;
	if (bo->shadow)
		params->func(params, bo->shadow, pde, pt, 1, 0, flags);
	params->func(params, bo, pde, pt, 1, 0, flags);
A
Alex Deucher 已提交
1014 1015
}

1016 1017 1018
/*
 * amdgpu_vm_invalidate_level - mark all PD levels as invalid
 *
1019 1020
 * @adev: amdgpu_device pointer
 * @vm: related vm
1021
 * @parent: parent PD
1022
 * @level: VMPT level
1023 1024 1025
 *
 * Mark all PD level as invalid after an error.
 */
1026 1027 1028 1029
static void amdgpu_vm_invalidate_level(struct amdgpu_device *adev,
				       struct amdgpu_vm *vm,
				       struct amdgpu_vm_pt *parent,
				       unsigned level)
1030
{
1031
	unsigned pt_idx, num_entries;
1032 1033 1034 1035 1036

	/*
	 * Recurse into the subdirectories. This recursion is harmless because
	 * we only have a maximum of 5 layers.
	 */
1037 1038
	num_entries = amdgpu_vm_num_entries(adev, level);
	for (pt_idx = 0; pt_idx < num_entries; ++pt_idx) {
1039 1040
		struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];

1041
		if (!entry->base.bo)
1042 1043
			continue;

1044 1045
		if (!entry->base.moved)
			list_move(&entry->base.vm_status, &vm->relocated);
1046
		amdgpu_vm_invalidate_level(adev, vm, entry, level + 1);
1047 1048 1049
	}
}

1050 1051 1052 1053 1054 1055 1056
/*
 * amdgpu_vm_update_directories - make sure that all directories are valid
 *
 * @adev: amdgpu_device pointer
 * @vm: requested vm
 *
 * Makes sure all directories are up to date.
1057 1058 1059
 *
 * Returns:
 * 0 for success, error for failure.
1060 1061 1062 1063
 */
int amdgpu_vm_update_directories(struct amdgpu_device *adev,
				 struct amdgpu_vm *vm)
{
1064 1065 1066
	struct amdgpu_pte_update_params params;
	struct amdgpu_job *job;
	unsigned ndw = 0;
1067
	int r = 0;
1068

1069 1070 1071 1072 1073 1074 1075 1076
	if (list_empty(&vm->relocated))
		return 0;

restart:
	memset(&params, 0, sizeof(params));
	params.adev = adev;

	if (vm->use_cpu_for_update) {
1077 1078 1079 1080 1081 1082 1083 1084
		struct amdgpu_vm_bo_base *bo_base;

		list_for_each_entry(bo_base, &vm->relocated, vm_status) {
			r = amdgpu_bo_kmap(bo_base->bo, NULL);
			if (unlikely(r))
				return r;
		}

1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099
		r = amdgpu_vm_wait_pd(adev, vm, AMDGPU_FENCE_OWNER_VM);
		if (unlikely(r))
			return r;

		params.func = amdgpu_vm_cpu_set_ptes;
	} else {
		ndw = 512 * 8;
		r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
		if (r)
			return r;

		params.ib = &job->ibs[0];
		params.func = amdgpu_vm_do_set_ptes;
	}

1100
	while (!list_empty(&vm->relocated)) {
1101 1102
		struct amdgpu_vm_bo_base *bo_base, *parent;
		struct amdgpu_vm_pt *pt, *entry;
1103 1104 1105 1106 1107
		struct amdgpu_bo *bo;

		bo_base = list_first_entry(&vm->relocated,
					   struct amdgpu_vm_bo_base,
					   vm_status);
1108
		bo_base->moved = false;
1109
		list_move(&bo_base->vm_status, &vm->idle);
1110 1111

		bo = bo_base->bo->parent;
1112
		if (!bo)
1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124
			continue;

		parent = list_first_entry(&bo->va, struct amdgpu_vm_bo_base,
					  bo_list);
		pt = container_of(parent, struct amdgpu_vm_pt, base);
		entry = container_of(bo_base, struct amdgpu_vm_pt, base);

		amdgpu_vm_update_pde(&params, vm, pt, entry);

		if (!vm->use_cpu_for_update &&
		    (ndw - params.ib->length_dw) < 32)
			break;
1125
	}
1126

1127 1128 1129
	if (vm->use_cpu_for_update) {
		/* Flush HDP */
		mb();
1130
		amdgpu_asic_flush_hdp(adev, NULL);
1131 1132 1133 1134 1135 1136 1137
	} else if (params.ib->length_dw == 0) {
		amdgpu_job_free(job);
	} else {
		struct amdgpu_bo *root = vm->root.base.bo;
		struct amdgpu_ring *ring;
		struct dma_fence *fence;

1138
		ring = container_of(vm->entity.rq->sched, struct amdgpu_ring,
1139 1140 1141 1142 1143 1144
				    sched);

		amdgpu_ring_pad_ib(ring, params.ib);
		amdgpu_sync_resv(adev, &job->sync, root->tbo.resv,
				 AMDGPU_FENCE_OWNER_VM, false);
		WARN_ON(params.ib->length_dw > ndw);
1145 1146
		r = amdgpu_job_submit(job, &vm->entity, AMDGPU_FENCE_OWNER_VM,
				      &fence);
1147 1148 1149 1150 1151 1152
		if (r)
			goto error;

		amdgpu_bo_fence(root, fence, true);
		dma_fence_put(vm->last_update);
		vm->last_update = fence;
1153 1154
	}

1155 1156 1157 1158 1159 1160
	if (!list_empty(&vm->relocated))
		goto restart;

	return 0;

error:
1161 1162
	amdgpu_vm_invalidate_level(adev, vm, &vm->root,
				   adev->vm_manager.root_level);
1163
	amdgpu_job_free(job);
1164
	return r;
1165 1166
}

1167
/**
1168
 * amdgpu_vm_find_entry - find the entry for an address
1169 1170 1171
 *
 * @p: see amdgpu_pte_update_params definition
 * @addr: virtual address in question
1172 1173
 * @entry: resulting entry or NULL
 * @parent: parent entry
1174
 *
1175
 * Find the vm_pt entry and it's parent for the given address.
1176
 */
1177 1178 1179
void amdgpu_vm_get_entry(struct amdgpu_pte_update_params *p, uint64_t addr,
			 struct amdgpu_vm_pt **entry,
			 struct amdgpu_vm_pt **parent)
1180
{
1181
	unsigned level = p->adev->vm_manager.root_level;
1182

1183 1184 1185
	*parent = NULL;
	*entry = &p->vm->root;
	while ((*entry)->entries) {
1186
		unsigned shift = amdgpu_vm_level_shift(p->adev, level++);
1187

1188
		*parent = *entry;
1189 1190
		*entry = &(*entry)->entries[addr >> shift];
		addr &= (1ULL << shift) - 1;
1191 1192
	}

1193
	if (level != AMDGPU_VM_PTB)
1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208
		*entry = NULL;
}

/**
 * amdgpu_vm_handle_huge_pages - handle updating the PD with huge pages
 *
 * @p: see amdgpu_pte_update_params definition
 * @entry: vm_pt entry to check
 * @parent: parent entry
 * @nptes: number of PTEs updated with this operation
 * @dst: destination address where the PTEs should point to
 * @flags: access flags fro the PTEs
 *
 * Check if we can update the PD with a huge page.
 */
1209 1210 1211 1212 1213
static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p,
					struct amdgpu_vm_pt *entry,
					struct amdgpu_vm_pt *parent,
					unsigned nptes, uint64_t dst,
					uint64_t flags)
1214
{
1215
	uint64_t pde;
1216 1217

	/* In the case of a mixed PT the PDE must point to it*/
1218 1219
	if (p->adev->asic_type >= CHIP_VEGA10 && !p->src &&
	    nptes == AMDGPU_VM_PTE_COUNT(p->adev)) {
1220
		/* Set the huge page flag to stop scanning at this PDE */
1221 1222 1223
		flags |= AMDGPU_PDE_PTE;
	}

1224 1225 1226 1227 1228 1229
	if (!(flags & AMDGPU_PDE_PTE)) {
		if (entry->huge) {
			/* Add the entry to the relocated list to update it. */
			entry->huge = false;
			list_move(&entry->base.vm_status, &p->vm->relocated);
		}
1230
		return;
1231
	}
1232

1233
	entry->huge = true;
1234
	amdgpu_gmc_get_vm_pde(p->adev, AMDGPU_VM_PDB0, &dst, &flags);
1235

1236 1237 1238 1239
	pde = (entry - parent->entries) * 8;
	if (parent->base.bo->shadow)
		p->func(p, parent->base.bo->shadow, pde, dst, 1, 0, flags);
	p->func(p, parent->base.bo, pde, dst, 1, 0, flags);
1240 1241
}

A
Alex Deucher 已提交
1242 1243 1244
/**
 * amdgpu_vm_update_ptes - make sure that page tables are valid
 *
1245
 * @params: see amdgpu_pte_update_params definition
A
Alex Deucher 已提交
1246 1247
 * @start: start of GPU address range
 * @end: end of GPU address range
1248
 * @dst: destination address to map to, the next dst inside the function
A
Alex Deucher 已提交
1249 1250
 * @flags: mapping flags
 *
1251
 * Update the page tables in the range @start - @end.
1252 1253 1254
 *
 * Returns:
 * 0 for success, -EINVAL for failure.
A
Alex Deucher 已提交
1255
 */
1256
static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
1257
				  uint64_t start, uint64_t end,
1258
				  uint64_t dst, uint64_t flags)
A
Alex Deucher 已提交
1259
{
1260 1261
	struct amdgpu_device *adev = params->adev;
	const uint64_t mask = AMDGPU_VM_PTE_COUNT(adev) - 1;
1262

1263
	uint64_t addr, pe_start;
1264
	struct amdgpu_bo *pt;
1265
	unsigned nptes;
A
Alex Deucher 已提交
1266 1267

	/* walk over the address space and update the page tables */
1268 1269 1270 1271 1272 1273 1274
	for (addr = start; addr < end; addr += nptes,
	     dst += nptes * AMDGPU_GPU_PAGE_SIZE) {
		struct amdgpu_vm_pt *entry, *parent;

		amdgpu_vm_get_entry(params, addr, &entry, &parent);
		if (!entry)
			return -ENOENT;
1275

A
Alex Deucher 已提交
1276 1277 1278
		if ((addr & ~mask) == (end & ~mask))
			nptes = end - addr;
		else
1279
			nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask);
A
Alex Deucher 已提交
1280

1281 1282
		amdgpu_vm_handle_huge_pages(params, entry, parent,
					    nptes, dst, flags);
1283
		/* We don't need to update PTEs for huge pages */
1284
		if (entry->huge)
1285 1286
			continue;

1287
		pt = entry->base.bo;
1288 1289 1290 1291 1292
		pe_start = (addr & mask) * 8;
		if (pt->shadow)
			params->func(params, pt->shadow, pe_start, dst, nptes,
				     AMDGPU_GPU_PAGE_SIZE, flags);
		params->func(params, pt, pe_start, dst, nptes,
1293
			     AMDGPU_GPU_PAGE_SIZE, flags);
A
Alex Deucher 已提交
1294 1295
	}

1296
	return 0;
1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307
}

/*
 * amdgpu_vm_frag_ptes - add fragment information to PTEs
 *
 * @params: see amdgpu_pte_update_params definition
 * @vm: requested vm
 * @start: first PTE to handle
 * @end: last PTE to handle
 * @dst: addr those PTEs should point to
 * @flags: hw mapping flags
1308 1309 1310
 *
 * Returns:
 * 0 for success, -EINVAL for failure.
1311
 */
1312
static int amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params	*params,
1313
				uint64_t start, uint64_t end,
1314
				uint64_t dst, uint64_t flags)
1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333
{
	/**
	 * The MC L1 TLB supports variable sized pages, based on a fragment
	 * field in the PTE. When this field is set to a non-zero value, page
	 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
	 * flags are considered valid for all PTEs within the fragment range
	 * and corresponding mappings are assumed to be physically contiguous.
	 *
	 * The L1 TLB can store a single PTE for the whole fragment,
	 * significantly increasing the space available for translation
	 * caching. This leads to large improvements in throughput when the
	 * TLB is under pressure.
	 *
	 * The L2 TLB distributes small and large fragments into two
	 * asymmetric partitions. The large fragment cache is significantly
	 * larger. Thus, we try to use large fragments wherever possible.
	 * Userspace can support this by aligning virtual base address and
	 * allocation size to the fragment size.
	 */
1334 1335
	unsigned max_frag = params->adev->vm_manager.fragment_size;
	int r;
1336 1337

	/* system pages are non continuously */
1338
	if (params->src || !(flags & AMDGPU_PTE_VALID))
1339
		return amdgpu_vm_update_ptes(params, start, end, dst, flags);
1340

1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357
	while (start != end) {
		uint64_t frag_flags, frag_end;
		unsigned frag;

		/* This intentionally wraps around if no bit is set */
		frag = min((unsigned)ffs(start) - 1,
			   (unsigned)fls64(end - start) - 1);
		if (frag >= max_frag) {
			frag_flags = AMDGPU_PTE_FRAG(max_frag);
			frag_end = end & ~((1ULL << max_frag) - 1);
		} else {
			frag_flags = AMDGPU_PTE_FRAG(frag);
			frag_end = start + (1 << frag);
		}

		r = amdgpu_vm_update_ptes(params, start, frag_end, dst,
					  flags | frag_flags);
1358 1359
		if (r)
			return r;
1360

1361 1362
		dst += (frag_end - start) * AMDGPU_GPU_PAGE_SIZE;
		start = frag_end;
1363
	}
1364 1365

	return 0;
A
Alex Deucher 已提交
1366 1367 1368 1369 1370 1371
}

/**
 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
 *
 * @adev: amdgpu_device pointer
1372
 * @exclusive: fence we need to sync to
1373
 * @pages_addr: DMA addresses to use for mapping
A
Alex Deucher 已提交
1374
 * @vm: requested vm
1375 1376 1377
 * @start: start of mapped range
 * @last: last mapped entry
 * @flags: flags for the entries
A
Alex Deucher 已提交
1378 1379 1380
 * @addr: addr to set the area to
 * @fence: optional resulting fence
 *
1381
 * Fill in the page table entries between @start and @last.
1382 1383 1384
 *
 * Returns:
 * 0 for success, -EINVAL for failure.
A
Alex Deucher 已提交
1385 1386
 */
static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
1387
				       struct dma_fence *exclusive,
1388
				       dma_addr_t *pages_addr,
A
Alex Deucher 已提交
1389
				       struct amdgpu_vm *vm,
1390
				       uint64_t start, uint64_t last,
1391
				       uint64_t flags, uint64_t addr,
1392
				       struct dma_fence **fence)
A
Alex Deucher 已提交
1393
{
1394
	struct amdgpu_ring *ring;
1395
	void *owner = AMDGPU_FENCE_OWNER_VM;
A
Alex Deucher 已提交
1396
	unsigned nptes, ncmds, ndw;
1397
	struct amdgpu_job *job;
1398
	struct amdgpu_pte_update_params params;
1399
	struct dma_fence *f = NULL;
A
Alex Deucher 已提交
1400 1401
	int r;

1402 1403
	memset(&params, 0, sizeof(params));
	params.adev = adev;
1404
	params.vm = vm;
1405

1406 1407 1408 1409
	/* sync to everything on unmapping */
	if (!(flags & AMDGPU_PTE_VALID))
		owner = AMDGPU_FENCE_OWNER_UNDEFINED;

1410 1411 1412 1413 1414 1415 1416 1417
	if (vm->use_cpu_for_update) {
		/* params.src is used as flag to indicate system Memory */
		if (pages_addr)
			params.src = ~0;

		/* Wait for PT BOs to be free. PTs share the same resv. object
		 * as the root PD BO
		 */
1418
		r = amdgpu_vm_wait_pd(adev, vm, owner);
1419 1420 1421 1422 1423 1424 1425 1426 1427
		if (unlikely(r))
			return r;

		params.func = amdgpu_vm_cpu_set_ptes;
		params.pages_addr = pages_addr;
		return amdgpu_vm_frag_ptes(&params, start, last + 1,
					   addr, flags);
	}

1428
	ring = container_of(vm->entity.rq->sched, struct amdgpu_ring, sched);
1429

1430
	nptes = last - start + 1;
A
Alex Deucher 已提交
1431 1432

	/*
1433
	 * reserve space for two commands every (1 << BLOCK_SIZE)
A
Alex Deucher 已提交
1434
	 *  entries or 2k dwords (whatever is smaller)
1435 1436
         *
         * The second command is for the shadow pagetables.
A
Alex Deucher 已提交
1437
	 */
1438 1439 1440 1441
	if (vm->root.base.bo->shadow)
		ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1) * 2;
	else
		ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1);
A
Alex Deucher 已提交
1442 1443 1444 1445

	/* padding, etc. */
	ndw = 64;

1446
	if (pages_addr) {
1447
		/* copy commands needed */
1448
		ndw += ncmds * adev->vm_manager.vm_pte_funcs->copy_pte_num_dw;
A
Alex Deucher 已提交
1449

1450
		/* and also PTEs */
A
Alex Deucher 已提交
1451 1452
		ndw += nptes * 2;

1453 1454
		params.func = amdgpu_vm_do_copy_ptes;

A
Alex Deucher 已提交
1455 1456
	} else {
		/* set page commands needed */
1457
		ndw += ncmds * 10;
A
Alex Deucher 已提交
1458

1459
		/* extra commands for begin/end fragments */
1460 1461 1462 1463
		if (vm->root.base.bo->shadow)
		        ndw += 2 * 10 * adev->vm_manager.fragment_size * 2;
		else
		        ndw += 2 * 10 * adev->vm_manager.fragment_size;
1464 1465

		params.func = amdgpu_vm_do_set_ptes;
A
Alex Deucher 已提交
1466 1467
	}

1468 1469
	r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
	if (r)
A
Alex Deucher 已提交
1470
		return r;
1471

1472
	params.ib = &job->ibs[0];
C
Chunming Zhou 已提交
1473

1474
	if (pages_addr) {
1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487
		uint64_t *pte;
		unsigned i;

		/* Put the PTEs at the end of the IB. */
		i = ndw - nptes * 2;
		pte= (uint64_t *)&(job->ibs->ptr[i]);
		params.src = job->ibs->gpu_addr + i * 4;

		for (i = 0; i < nptes; ++i) {
			pte[i] = amdgpu_vm_map_gart(pages_addr, addr + i *
						    AMDGPU_GPU_PAGE_SIZE);
			pte[i] |= flags;
		}
1488
		addr = 0;
1489 1490
	}

1491
	r = amdgpu_sync_fence(adev, &job->sync, exclusive, false);
1492 1493 1494
	if (r)
		goto error_free;

1495
	r = amdgpu_sync_resv(adev, &job->sync, vm->root.base.bo->tbo.resv,
1496
			     owner, false);
1497 1498
	if (r)
		goto error_free;
A
Alex Deucher 已提交
1499

1500
	r = reservation_object_reserve_shared(vm->root.base.bo->tbo.resv);
1501 1502 1503
	if (r)
		goto error_free;

1504 1505 1506
	r = amdgpu_vm_frag_ptes(&params, start, last + 1, addr, flags);
	if (r)
		goto error_free;
A
Alex Deucher 已提交
1507

1508 1509
	amdgpu_ring_pad_ib(ring, params.ib);
	WARN_ON(params.ib->length_dw > ndw);
1510
	r = amdgpu_job_submit(job, &vm->entity, AMDGPU_FENCE_OWNER_VM, &f);
1511 1512
	if (r)
		goto error_free;
A
Alex Deucher 已提交
1513

1514
	amdgpu_bo_fence(vm->root.base.bo, f, true);
1515 1516
	dma_fence_put(*fence);
	*fence = f;
A
Alex Deucher 已提交
1517
	return 0;
C
Chunming Zhou 已提交
1518 1519

error_free:
1520
	amdgpu_job_free(job);
1521
	return r;
A
Alex Deucher 已提交
1522 1523
}

1524 1525 1526 1527
/**
 * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks
 *
 * @adev: amdgpu_device pointer
1528
 * @exclusive: fence we need to sync to
1529
 * @pages_addr: DMA addresses to use for mapping
1530 1531
 * @vm: requested vm
 * @mapping: mapped range and flags to use for the update
1532
 * @flags: HW flags for the mapping
1533
 * @nodes: array of drm_mm_nodes with the MC addresses
1534 1535 1536 1537
 * @fence: optional resulting fence
 *
 * Split the mapping into smaller chunks so that each update fits
 * into a SDMA IB.
1538 1539 1540
 *
 * Returns:
 * 0 for success, -EINVAL for failure.
1541 1542
 */
static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
1543
				      struct dma_fence *exclusive,
1544
				      dma_addr_t *pages_addr,
1545 1546
				      struct amdgpu_vm *vm,
				      struct amdgpu_bo_va_mapping *mapping,
1547
				      uint64_t flags,
1548
				      struct drm_mm_node *nodes,
1549
				      struct dma_fence **fence)
1550
{
1551
	unsigned min_linear_pages = 1 << adev->vm_manager.fragment_size;
1552
	uint64_t pfn, start = mapping->start;
1553 1554 1555 1556 1557 1558 1559 1560 1561 1562
	int r;

	/* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
	 * but in case of something, we filter the flags in first place
	 */
	if (!(mapping->flags & AMDGPU_PTE_READABLE))
		flags &= ~AMDGPU_PTE_READABLE;
	if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
		flags &= ~AMDGPU_PTE_WRITEABLE;

1563 1564 1565
	flags &= ~AMDGPU_PTE_EXECUTABLE;
	flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;

1566 1567 1568
	flags &= ~AMDGPU_PTE_MTYPE_MASK;
	flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK);

1569 1570 1571 1572 1573 1574
	if ((mapping->flags & AMDGPU_PTE_PRT) &&
	    (adev->asic_type >= CHIP_VEGA10)) {
		flags |= AMDGPU_PTE_PRT;
		flags &= ~AMDGPU_PTE_VALID;
	}

1575 1576
	trace_amdgpu_vm_bo_update(mapping);

1577 1578 1579 1580 1581 1582
	pfn = mapping->offset >> PAGE_SHIFT;
	if (nodes) {
		while (pfn >= nodes->size) {
			pfn -= nodes->size;
			++nodes;
		}
1583
	}
1584

1585
	do {
1586
		dma_addr_t *dma_addr = NULL;
1587 1588
		uint64_t max_entries;
		uint64_t addr, last;
1589

1590 1591 1592
		if (nodes) {
			addr = nodes->start << PAGE_SHIFT;
			max_entries = (nodes->size - pfn) *
1593
				AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1594 1595 1596 1597
		} else {
			addr = 0;
			max_entries = S64_MAX;
		}
1598

1599
		if (pages_addr) {
1600 1601
			uint64_t count;

1602
			max_entries = min(max_entries, 16ull * 1024ull);
1603
			for (count = 1;
1604
			     count < max_entries / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1605
			     ++count) {
1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617
				uint64_t idx = pfn + count;

				if (pages_addr[idx] !=
				    (pages_addr[idx - 1] + PAGE_SIZE))
					break;
			}

			if (count < min_linear_pages) {
				addr = pfn << PAGE_SHIFT;
				dma_addr = pages_addr;
			} else {
				addr = pages_addr[pfn];
1618
				max_entries = count * AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1619 1620
			}

1621 1622
		} else if (flags & AMDGPU_PTE_VALID) {
			addr += adev->vm_manager.vram_base_offset;
1623
			addr += pfn << PAGE_SHIFT;
1624 1625
		}

1626
		last = min((uint64_t)mapping->last, start + max_entries - 1);
1627
		r = amdgpu_vm_bo_update_mapping(adev, exclusive, dma_addr, vm,
1628 1629 1630 1631 1632
						start, last, flags, addr,
						fence);
		if (r)
			return r;

1633
		pfn += (last - start + 1) / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1634 1635 1636 1637
		if (nodes && nodes->size == pfn) {
			pfn = 0;
			++nodes;
		}
1638
		start = last + 1;
1639

1640
	} while (unlikely(start != mapping->last + 1));
1641 1642 1643 1644

	return 0;
}

A
Alex Deucher 已提交
1645 1646 1647 1648 1649
/**
 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
 *
 * @adev: amdgpu_device pointer
 * @bo_va: requested BO and VM object
1650
 * @clear: if true clear the entries
A
Alex Deucher 已提交
1651 1652
 *
 * Fill in the page table entries for @bo_va.
1653 1654 1655
 *
 * Returns:
 * 0 for success, -EINVAL for failure.
A
Alex Deucher 已提交
1656 1657 1658
 */
int amdgpu_vm_bo_update(struct amdgpu_device *adev,
			struct amdgpu_bo_va *bo_va,
1659
			bool clear)
A
Alex Deucher 已提交
1660
{
1661 1662
	struct amdgpu_bo *bo = bo_va->base.bo;
	struct amdgpu_vm *vm = bo_va->base.vm;
A
Alex Deucher 已提交
1663
	struct amdgpu_bo_va_mapping *mapping;
1664
	dma_addr_t *pages_addr = NULL;
1665
	struct ttm_mem_reg *mem;
1666
	struct drm_mm_node *nodes;
1667
	struct dma_fence *exclusive, **last_update;
1668
	uint64_t flags;
A
Alex Deucher 已提交
1669 1670
	int r;

1671
	if (clear || !bo) {
1672
		mem = NULL;
1673
		nodes = NULL;
1674 1675
		exclusive = NULL;
	} else {
1676 1677
		struct ttm_dma_tt *ttm;

1678
		mem = &bo->tbo.mem;
1679 1680
		nodes = mem->mm_node;
		if (mem->mem_type == TTM_PL_TT) {
1681
			ttm = container_of(bo->tbo.ttm, struct ttm_dma_tt, ttm);
1682
			pages_addr = ttm->dma_address;
1683
		}
1684
		exclusive = reservation_object_get_excl(bo->tbo.resv);
A
Alex Deucher 已提交
1685 1686
	}

1687
	if (bo)
1688
		flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
1689
	else
1690
		flags = 0x0;
A
Alex Deucher 已提交
1691

1692 1693 1694 1695 1696
	if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv))
		last_update = &vm->last_update;
	else
		last_update = &bo_va->last_pt_update;

1697 1698
	if (!clear && bo_va->base.moved) {
		bo_va->base.moved = false;
1699
		list_splice_init(&bo_va->valids, &bo_va->invalids);
1700

1701 1702
	} else if (bo_va->cleared != clear) {
		list_splice_init(&bo_va->valids, &bo_va->invalids);
1703
	}
1704 1705

	list_for_each_entry(mapping, &bo_va->invalids, list) {
1706
		r = amdgpu_vm_bo_split_mapping(adev, exclusive, pages_addr, vm,
1707
					       mapping, flags, nodes,
1708
					       last_update);
A
Alex Deucher 已提交
1709 1710 1711 1712
		if (r)
			return r;
	}

1713 1714 1715
	if (vm->use_cpu_for_update) {
		/* Flush HDP */
		mb();
1716
		amdgpu_asic_flush_hdp(adev, NULL);
1717 1718
	}

1719
	spin_lock(&vm->moved_lock);
1720
	list_del_init(&bo_va->base.vm_status);
1721
	spin_unlock(&vm->moved_lock);
1722

1723 1724 1725 1726
	/* If the BO is not in its preferred location add it back to
	 * the evicted list so that it gets validated again on the
	 * next command submission.
	 */
1727 1728 1729 1730 1731 1732 1733 1734
	if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv) {
		uint32_t mem_type = bo->tbo.mem.mem_type;

		if (!(bo->preferred_domains & amdgpu_mem_type_to_domain(mem_type)))
			list_add_tail(&bo_va->base.vm_status, &vm->evicted);
		else
			list_add(&bo_va->base.vm_status, &vm->idle);
	}
A
Alex Deucher 已提交
1735

1736 1737 1738 1739 1740 1741
	list_splice_init(&bo_va->invalids, &bo_va->valids);
	bo_va->cleared = clear;

	if (trace_amdgpu_vm_bo_mapping_enabled()) {
		list_for_each_entry(mapping, &bo_va->valids, list)
			trace_amdgpu_vm_bo_mapping(mapping);
1742 1743
	}

A
Alex Deucher 已提交
1744 1745 1746
	return 0;
}

1747 1748
/**
 * amdgpu_vm_update_prt_state - update the global PRT state
1749 1750
 *
 * @adev: amdgpu_device pointer
1751 1752 1753 1754 1755 1756 1757
 */
static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
{
	unsigned long flags;
	bool enable;

	spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
1758
	enable = !!atomic_read(&adev->vm_manager.num_prt_users);
1759
	adev->gmc.gmc_funcs->set_prt(adev, enable);
1760 1761 1762
	spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
}

1763
/**
1764
 * amdgpu_vm_prt_get - add a PRT user
1765 1766
 *
 * @adev: amdgpu_device pointer
1767 1768 1769
 */
static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
{
1770
	if (!adev->gmc.gmc_funcs->set_prt)
1771 1772
		return;

1773 1774 1775 1776
	if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
		amdgpu_vm_update_prt_state(adev);
}

1777 1778
/**
 * amdgpu_vm_prt_put - drop a PRT user
1779 1780
 *
 * @adev: amdgpu_device pointer
1781 1782 1783
 */
static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
{
1784
	if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
1785 1786 1787
		amdgpu_vm_update_prt_state(adev);
}

1788
/**
1789
 * amdgpu_vm_prt_cb - callback for updating the PRT status
1790 1791
 *
 * @fence: fence for the callback
1792
 * @_cb: the callback function
1793 1794 1795 1796 1797
 */
static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
{
	struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);

1798
	amdgpu_vm_prt_put(cb->adev);
1799 1800 1801
	kfree(cb);
}

1802 1803
/**
 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
1804 1805 1806
 *
 * @adev: amdgpu_device pointer
 * @fence: fence for the callback
1807 1808 1809 1810
 */
static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
				 struct dma_fence *fence)
{
1811
	struct amdgpu_prt_cb *cb;
1812

1813
	if (!adev->gmc.gmc_funcs->set_prt)
1814 1815 1816
		return;

	cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
1817 1818 1819 1820 1821
	if (!cb) {
		/* Last resort when we are OOM */
		if (fence)
			dma_fence_wait(fence, false);

1822
		amdgpu_vm_prt_put(adev);
1823 1824 1825 1826 1827 1828 1829 1830
	} else {
		cb->adev = adev;
		if (!fence || dma_fence_add_callback(fence, &cb->cb,
						     amdgpu_vm_prt_cb))
			amdgpu_vm_prt_cb(fence, &cb->cb);
	}
}

1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845
/**
 * amdgpu_vm_free_mapping - free a mapping
 *
 * @adev: amdgpu_device pointer
 * @vm: requested vm
 * @mapping: mapping to be freed
 * @fence: fence of the unmap operation
 *
 * Free a mapping and make sure we decrease the PRT usage count if applicable.
 */
static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
				   struct amdgpu_vm *vm,
				   struct amdgpu_bo_va_mapping *mapping,
				   struct dma_fence *fence)
{
1846 1847 1848 1849
	if (mapping->flags & AMDGPU_PTE_PRT)
		amdgpu_vm_add_prt_cb(adev, fence);
	kfree(mapping);
}
1850

1851 1852 1853 1854 1855 1856 1857 1858 1859 1860
/**
 * amdgpu_vm_prt_fini - finish all prt mappings
 *
 * @adev: amdgpu_device pointer
 * @vm: requested vm
 *
 * Register a cleanup callback to disable PRT support after VM dies.
 */
static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
{
1861
	struct reservation_object *resv = vm->root.base.bo->tbo.resv;
1862 1863 1864
	struct dma_fence *excl, **shared;
	unsigned i, shared_count;
	int r;
1865

1866 1867 1868 1869 1870 1871 1872 1873 1874
	r = reservation_object_get_fences_rcu(resv, &excl,
					      &shared_count, &shared);
	if (r) {
		/* Not enough memory to grab the fence list, as last resort
		 * block for all the fences to complete.
		 */
		reservation_object_wait_timeout_rcu(resv, true, false,
						    MAX_SCHEDULE_TIMEOUT);
		return;
1875
	}
1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886

	/* Add a callback for each fence in the reservation object */
	amdgpu_vm_prt_get(adev);
	amdgpu_vm_add_prt_cb(adev, excl);

	for (i = 0; i < shared_count; ++i) {
		amdgpu_vm_prt_get(adev);
		amdgpu_vm_add_prt_cb(adev, shared[i]);
	}

	kfree(shared);
1887 1888
}

A
Alex Deucher 已提交
1889 1890 1891 1892 1893
/**
 * amdgpu_vm_clear_freed - clear freed BOs in the PT
 *
 * @adev: amdgpu_device pointer
 * @vm: requested vm
1894 1895
 * @fence: optional resulting fence (unchanged if no work needed to be done
 * or if an error occurred)
A
Alex Deucher 已提交
1896 1897 1898
 *
 * Make sure all freed BOs are cleared in the PT.
 * PTs have to be reserved and mutex must be locked!
1899 1900 1901 1902
 *
 * Returns:
 * 0 for success.
 *
A
Alex Deucher 已提交
1903 1904
 */
int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
1905 1906
			  struct amdgpu_vm *vm,
			  struct dma_fence **fence)
A
Alex Deucher 已提交
1907 1908
{
	struct amdgpu_bo_va_mapping *mapping;
1909
	uint64_t init_pte_value = 0;
1910
	struct dma_fence *f = NULL;
A
Alex Deucher 已提交
1911 1912 1913 1914 1915 1916
	int r;

	while (!list_empty(&vm->freed)) {
		mapping = list_first_entry(&vm->freed,
			struct amdgpu_bo_va_mapping, list);
		list_del(&mapping->list);
1917

1918
		if (vm->pte_support_ats && mapping->start < AMDGPU_VA_HOLE_START)
1919
			init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
Y
Yong Zhao 已提交
1920

1921
		r = amdgpu_vm_bo_update_mapping(adev, NULL, NULL, vm,
1922
						mapping->start, mapping->last,
Y
Yong Zhao 已提交
1923
						init_pte_value, 0, &f);
1924
		amdgpu_vm_free_mapping(adev, vm, mapping, f);
1925
		if (r) {
1926
			dma_fence_put(f);
A
Alex Deucher 已提交
1927
			return r;
1928
		}
1929
	}
A
Alex Deucher 已提交
1930

1931 1932 1933 1934 1935
	if (fence && f) {
		dma_fence_put(*fence);
		*fence = f;
	} else {
		dma_fence_put(f);
A
Alex Deucher 已提交
1936
	}
1937

A
Alex Deucher 已提交
1938 1939 1940 1941 1942
	return 0;

}

/**
1943
 * amdgpu_vm_handle_moved - handle moved BOs in the PT
A
Alex Deucher 已提交
1944 1945 1946 1947
 *
 * @adev: amdgpu_device pointer
 * @vm: requested vm
 *
1948
 * Make sure all BOs which are moved are updated in the PTs.
1949 1950 1951
 *
 * Returns:
 * 0 for success.
A
Alex Deucher 已提交
1952
 *
1953
 * PTs have to be reserved!
A
Alex Deucher 已提交
1954
 */
1955
int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
1956
			   struct amdgpu_vm *vm)
A
Alex Deucher 已提交
1957
{
1958 1959
	struct amdgpu_bo_va *bo_va, *tmp;
	struct list_head moved;
1960
	bool clear;
1961
	int r;
A
Alex Deucher 已提交
1962

1963
	INIT_LIST_HEAD(&moved);
1964
	spin_lock(&vm->moved_lock);
1965 1966
	list_splice_init(&vm->moved, &moved);
	spin_unlock(&vm->moved_lock);
1967

1968 1969
	list_for_each_entry_safe(bo_va, tmp, &moved, base.vm_status) {
		struct reservation_object *resv = bo_va->base.bo->tbo.resv;
1970

1971
		/* Per VM BOs never need to bo cleared in the page tables */
1972 1973 1974
		if (resv == vm->root.base.bo->tbo.resv)
			clear = false;
		/* Try to reserve the BO to avoid clearing its ptes */
1975
		else if (!amdgpu_vm_debug && reservation_object_trylock(resv))
1976 1977 1978 1979
			clear = false;
		/* Somebody else is using the BO right now */
		else
			clear = true;
1980 1981

		r = amdgpu_vm_bo_update(adev, bo_va, clear);
1982 1983 1984 1985
		if (r) {
			spin_lock(&vm->moved_lock);
			list_splice(&moved, &vm->moved);
			spin_unlock(&vm->moved_lock);
A
Alex Deucher 已提交
1986
			return r;
1987
		}
A
Alex Deucher 已提交
1988

1989 1990 1991
		if (!clear && resv != vm->root.base.bo->tbo.resv)
			reservation_object_unlock(resv);

A
Alex Deucher 已提交
1992 1993
	}

1994
	return 0;
A
Alex Deucher 已提交
1995 1996 1997 1998 1999 2000 2001 2002 2003
}

/**
 * amdgpu_vm_bo_add - add a bo to a specific vm
 *
 * @adev: amdgpu_device pointer
 * @vm: requested vm
 * @bo: amdgpu buffer object
 *
2004
 * Add @bo into the requested vm.
A
Alex Deucher 已提交
2005
 * Add @bo to the list of bos associated with the vm
2006 2007 2008
 *
 * Returns:
 * Newly added bo_va or NULL for failure
A
Alex Deucher 已提交
2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021
 *
 * Object has to be reserved!
 */
struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
				      struct amdgpu_vm *vm,
				      struct amdgpu_bo *bo)
{
	struct amdgpu_bo_va *bo_va;

	bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
	if (bo_va == NULL) {
		return NULL;
	}
2022
	amdgpu_vm_bo_base_init(&bo_va->base, vm, bo);
2023

A
Alex Deucher 已提交
2024
	bo_va->ref_count = 1;
2025 2026
	INIT_LIST_HEAD(&bo_va->valids);
	INIT_LIST_HEAD(&bo_va->invalids);
2027

A
Alex Deucher 已提交
2028 2029 2030
	return bo_va;
}

2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047

/**
 * amdgpu_vm_bo_insert_mapping - insert a new mapping
 *
 * @adev: amdgpu_device pointer
 * @bo_va: bo_va to store the address
 * @mapping: the mapping to insert
 *
 * Insert a new mapping into all structures.
 */
static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
				    struct amdgpu_bo_va *bo_va,
				    struct amdgpu_bo_va_mapping *mapping)
{
	struct amdgpu_vm *vm = bo_va->base.vm;
	struct amdgpu_bo *bo = bo_va->base.bo;

2048
	mapping->bo_va = bo_va;
2049 2050 2051 2052 2053 2054
	list_add(&mapping->list, &bo_va->invalids);
	amdgpu_vm_it_insert(mapping, &vm->va);

	if (mapping->flags & AMDGPU_PTE_PRT)
		amdgpu_vm_prt_get(adev);

2055 2056
	if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv &&
	    !bo_va->base.moved) {
2057
		spin_lock(&vm->moved_lock);
2058
		list_move(&bo_va->base.vm_status, &vm->moved);
2059
		spin_unlock(&vm->moved_lock);
2060 2061 2062 2063
	}
	trace_amdgpu_vm_bo_map(bo_va, mapping);
}

A
Alex Deucher 已提交
2064 2065 2066 2067 2068 2069 2070
/**
 * amdgpu_vm_bo_map - map bo inside a vm
 *
 * @adev: amdgpu_device pointer
 * @bo_va: bo_va to store the address
 * @saddr: where to map the BO
 * @offset: requested offset in the BO
2071
 * @size: BO size in bytes
A
Alex Deucher 已提交
2072 2073 2074
 * @flags: attributes of pages (read/write/valid/etc.)
 *
 * Add a mapping of the BO at the specefied addr into the VM.
2075 2076 2077
 *
 * Returns:
 * 0 for success, error for failure.
A
Alex Deucher 已提交
2078
 *
2079
 * Object has to be reserved and unreserved outside!
A
Alex Deucher 已提交
2080 2081 2082 2083
 */
int amdgpu_vm_bo_map(struct amdgpu_device *adev,
		     struct amdgpu_bo_va *bo_va,
		     uint64_t saddr, uint64_t offset,
2084
		     uint64_t size, uint64_t flags)
A
Alex Deucher 已提交
2085
{
2086
	struct amdgpu_bo_va_mapping *mapping, *tmp;
2087 2088
	struct amdgpu_bo *bo = bo_va->base.bo;
	struct amdgpu_vm *vm = bo_va->base.vm;
A
Alex Deucher 已提交
2089 2090
	uint64_t eaddr;

2091 2092
	/* validate the parameters */
	if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
2093
	    size == 0 || size & AMDGPU_GPU_PAGE_MASK)
2094 2095
		return -EINVAL;

A
Alex Deucher 已提交
2096
	/* make sure object fit at this offset */
2097
	eaddr = saddr + size - 1;
2098
	if (saddr >= eaddr ||
2099
	    (bo && offset + size > amdgpu_bo_size(bo)))
A
Alex Deucher 已提交
2100 2101 2102 2103 2104
		return -EINVAL;

	saddr /= AMDGPU_GPU_PAGE_SIZE;
	eaddr /= AMDGPU_GPU_PAGE_SIZE;

2105 2106
	tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
	if (tmp) {
A
Alex Deucher 已提交
2107 2108
		/* bo and tmp overlap, invalid addr */
		dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
2109
			"0x%010Lx-0x%010Lx\n", bo, saddr, eaddr,
2110
			tmp->start, tmp->last + 1);
2111
		return -EINVAL;
A
Alex Deucher 已提交
2112 2113 2114
	}

	mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2115 2116
	if (!mapping)
		return -ENOMEM;
A
Alex Deucher 已提交
2117

2118 2119
	mapping->start = saddr;
	mapping->last = eaddr;
A
Alex Deucher 已提交
2120 2121 2122
	mapping->offset = offset;
	mapping->flags = flags;

2123
	amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134

	return 0;
}

/**
 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
 *
 * @adev: amdgpu_device pointer
 * @bo_va: bo_va to store the address
 * @saddr: where to map the BO
 * @offset: requested offset in the BO
2135
 * @size: BO size in bytes
2136 2137 2138 2139
 * @flags: attributes of pages (read/write/valid/etc.)
 *
 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
 * mappings as we do so.
2140 2141 2142
 *
 * Returns:
 * 0 for success, error for failure.
2143 2144 2145 2146 2147 2148 2149 2150 2151
 *
 * Object has to be reserved and unreserved outside!
 */
int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
			     struct amdgpu_bo_va *bo_va,
			     uint64_t saddr, uint64_t offset,
			     uint64_t size, uint64_t flags)
{
	struct amdgpu_bo_va_mapping *mapping;
2152
	struct amdgpu_bo *bo = bo_va->base.bo;
2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163
	uint64_t eaddr;
	int r;

	/* validate the parameters */
	if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
	    size == 0 || size & AMDGPU_GPU_PAGE_MASK)
		return -EINVAL;

	/* make sure object fit at this offset */
	eaddr = saddr + size - 1;
	if (saddr >= eaddr ||
2164
	    (bo && offset + size > amdgpu_bo_size(bo)))
2165 2166 2167 2168 2169 2170 2171
		return -EINVAL;

	/* Allocate all the needed memory */
	mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
	if (!mapping)
		return -ENOMEM;

2172
	r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size);
2173 2174 2175 2176 2177 2178 2179 2180
	if (r) {
		kfree(mapping);
		return r;
	}

	saddr /= AMDGPU_GPU_PAGE_SIZE;
	eaddr /= AMDGPU_GPU_PAGE_SIZE;

2181 2182
	mapping->start = saddr;
	mapping->last = eaddr;
2183 2184 2185
	mapping->offset = offset;
	mapping->flags = flags;

2186
	amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2187

A
Alex Deucher 已提交
2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198
	return 0;
}

/**
 * amdgpu_vm_bo_unmap - remove bo mapping from vm
 *
 * @adev: amdgpu_device pointer
 * @bo_va: bo_va to remove the address from
 * @saddr: where to the BO is mapped
 *
 * Remove a mapping of the BO at the specefied addr from the VM.
2199 2200 2201
 *
 * Returns:
 * 0 for success, error for failure.
A
Alex Deucher 已提交
2202
 *
2203
 * Object has to be reserved and unreserved outside!
A
Alex Deucher 已提交
2204 2205 2206 2207 2208 2209
 */
int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
		       struct amdgpu_bo_va *bo_va,
		       uint64_t saddr)
{
	struct amdgpu_bo_va_mapping *mapping;
2210
	struct amdgpu_vm *vm = bo_va->base.vm;
2211
	bool valid = true;
A
Alex Deucher 已提交
2212

2213
	saddr /= AMDGPU_GPU_PAGE_SIZE;
2214

2215
	list_for_each_entry(mapping, &bo_va->valids, list) {
2216
		if (mapping->start == saddr)
A
Alex Deucher 已提交
2217 2218 2219
			break;
	}

2220 2221 2222 2223
	if (&mapping->list == &bo_va->valids) {
		valid = false;

		list_for_each_entry(mapping, &bo_va->invalids, list) {
2224
			if (mapping->start == saddr)
2225 2226 2227
				break;
		}

2228
		if (&mapping->list == &bo_va->invalids)
2229
			return -ENOENT;
A
Alex Deucher 已提交
2230
	}
2231

A
Alex Deucher 已提交
2232
	list_del(&mapping->list);
2233
	amdgpu_vm_it_remove(mapping, &vm->va);
2234
	mapping->bo_va = NULL;
2235
	trace_amdgpu_vm_bo_unmap(bo_va, mapping);
A
Alex Deucher 已提交
2236

2237
	if (valid)
A
Alex Deucher 已提交
2238
		list_add(&mapping->list, &vm->freed);
2239
	else
2240 2241
		amdgpu_vm_free_mapping(adev, vm, mapping,
				       bo_va->last_pt_update);
A
Alex Deucher 已提交
2242 2243 2244 2245

	return 0;
}

2246 2247 2248 2249 2250 2251 2252 2253 2254
/**
 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
 *
 * @adev: amdgpu_device pointer
 * @vm: VM structure to use
 * @saddr: start of the range
 * @size: size of the range
 *
 * Remove all mappings in a range, split them as appropriate.
2255 2256 2257
 *
 * Returns:
 * 0 for success, error for failure.
2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274
 */
int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
				struct amdgpu_vm *vm,
				uint64_t saddr, uint64_t size)
{
	struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
	LIST_HEAD(removed);
	uint64_t eaddr;

	eaddr = saddr + size - 1;
	saddr /= AMDGPU_GPU_PAGE_SIZE;
	eaddr /= AMDGPU_GPU_PAGE_SIZE;

	/* Allocate all the needed memory */
	before = kzalloc(sizeof(*before), GFP_KERNEL);
	if (!before)
		return -ENOMEM;
2275
	INIT_LIST_HEAD(&before->list);
2276 2277 2278 2279 2280 2281

	after = kzalloc(sizeof(*after), GFP_KERNEL);
	if (!after) {
		kfree(before);
		return -ENOMEM;
	}
2282
	INIT_LIST_HEAD(&after->list);
2283 2284

	/* Now gather all removed mappings */
2285 2286
	tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
	while (tmp) {
2287
		/* Remember mapping split at the start */
2288 2289 2290
		if (tmp->start < saddr) {
			before->start = tmp->start;
			before->last = saddr - 1;
2291 2292
			before->offset = tmp->offset;
			before->flags = tmp->flags;
2293 2294
			before->bo_va = tmp->bo_va;
			list_add(&before->list, &tmp->bo_va->invalids);
2295 2296 2297
		}

		/* Remember mapping split at the end */
2298 2299 2300
		if (tmp->last > eaddr) {
			after->start = eaddr + 1;
			after->last = tmp->last;
2301
			after->offset = tmp->offset;
2302
			after->offset += after->start - tmp->start;
2303
			after->flags = tmp->flags;
2304 2305
			after->bo_va = tmp->bo_va;
			list_add(&after->list, &tmp->bo_va->invalids);
2306 2307 2308 2309
		}

		list_del(&tmp->list);
		list_add(&tmp->list, &removed);
2310 2311

		tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
2312 2313 2314 2315
	}

	/* And free them up */
	list_for_each_entry_safe(tmp, next, &removed, list) {
2316
		amdgpu_vm_it_remove(tmp, &vm->va);
2317 2318
		list_del(&tmp->list);

2319 2320 2321 2322
		if (tmp->start < saddr)
		    tmp->start = saddr;
		if (tmp->last > eaddr)
		    tmp->last = eaddr;
2323

2324
		tmp->bo_va = NULL;
2325 2326 2327 2328
		list_add(&tmp->list, &vm->freed);
		trace_amdgpu_vm_bo_unmap(NULL, tmp);
	}

2329 2330
	/* Insert partial mapping before the range */
	if (!list_empty(&before->list)) {
2331
		amdgpu_vm_it_insert(before, &vm->va);
2332 2333 2334 2335 2336 2337 2338
		if (before->flags & AMDGPU_PTE_PRT)
			amdgpu_vm_prt_get(adev);
	} else {
		kfree(before);
	}

	/* Insert partial mapping after the range */
2339
	if (!list_empty(&after->list)) {
2340
		amdgpu_vm_it_insert(after, &vm->va);
2341 2342 2343 2344 2345 2346 2347 2348 2349
		if (after->flags & AMDGPU_PTE_PRT)
			amdgpu_vm_prt_get(adev);
	} else {
		kfree(after);
	}

	return 0;
}

2350 2351 2352 2353
/**
 * amdgpu_vm_bo_lookup_mapping - find mapping by address
 *
 * @vm: the requested VM
2354
 * @addr: the address
2355 2356
 *
 * Find a mapping by it's address.
2357 2358 2359 2360
 *
 * Returns:
 * The amdgpu_bo_va_mapping matching for addr or NULL
 *
2361 2362 2363 2364 2365 2366 2367
 */
struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
							 uint64_t addr)
{
	return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
}

2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396
/**
 * amdgpu_vm_bo_trace_cs - trace all reserved mappings
 *
 * @vm: the requested vm
 * @ticket: CS ticket
 *
 * Trace all mappings of BOs reserved during a command submission.
 */
void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket)
{
	struct amdgpu_bo_va_mapping *mapping;

	if (!trace_amdgpu_vm_bo_cs_enabled())
		return;

	for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping;
	     mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) {
		if (mapping->bo_va && mapping->bo_va->base.bo) {
			struct amdgpu_bo *bo;

			bo = mapping->bo_va->base.bo;
			if (READ_ONCE(bo->tbo.resv->lock.ctx) != ticket)
				continue;
		}

		trace_amdgpu_vm_bo_cs(mapping);
	}
}

A
Alex Deucher 已提交
2397 2398 2399 2400 2401 2402
/**
 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
 *
 * @adev: amdgpu_device pointer
 * @bo_va: requested bo_va
 *
2403
 * Remove @bo_va->bo from the requested vm.
A
Alex Deucher 已提交
2404 2405 2406 2407 2408 2409 2410
 *
 * Object have to be reserved!
 */
void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
		      struct amdgpu_bo_va *bo_va)
{
	struct amdgpu_bo_va_mapping *mapping, *next;
2411
	struct amdgpu_vm *vm = bo_va->base.vm;
A
Alex Deucher 已提交
2412

2413
	list_del(&bo_va->base.bo_list);
A
Alex Deucher 已提交
2414

2415
	spin_lock(&vm->moved_lock);
2416
	list_del(&bo_va->base.vm_status);
2417
	spin_unlock(&vm->moved_lock);
A
Alex Deucher 已提交
2418

2419
	list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
A
Alex Deucher 已提交
2420
		list_del(&mapping->list);
2421
		amdgpu_vm_it_remove(mapping, &vm->va);
2422
		mapping->bo_va = NULL;
2423
		trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2424 2425 2426 2427
		list_add(&mapping->list, &vm->freed);
	}
	list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
		list_del(&mapping->list);
2428
		amdgpu_vm_it_remove(mapping, &vm->va);
2429 2430
		amdgpu_vm_free_mapping(adev, vm, mapping,
				       bo_va->last_pt_update);
A
Alex Deucher 已提交
2431
	}
2432

2433
	dma_fence_put(bo_va->last_pt_update);
A
Alex Deucher 已提交
2434 2435 2436 2437 2438 2439 2440 2441
	kfree(bo_va);
}

/**
 * amdgpu_vm_bo_invalidate - mark the bo as invalid
 *
 * @adev: amdgpu_device pointer
 * @bo: amdgpu buffer object
2442
 * @evicted: is the BO evicted
A
Alex Deucher 已提交
2443
 *
2444
 * Mark @bo as invalid.
A
Alex Deucher 已提交
2445 2446
 */
void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2447
			     struct amdgpu_bo *bo, bool evicted)
A
Alex Deucher 已提交
2448
{
2449 2450
	struct amdgpu_vm_bo_base *bo_base;

2451 2452 2453 2454
	/* shadow bo doesn't have bo base, its validation needs its parent */
	if (bo->parent && bo->parent->shadow == bo)
		bo = bo->parent;

2455
	list_for_each_entry(bo_base, &bo->va, bo_list) {
2456
		struct amdgpu_vm *vm = bo_base->vm;
2457
		bool was_moved = bo_base->moved;
2458

2459
		bo_base->moved = true;
2460
		if (evicted && bo->tbo.resv == vm->root.base.bo->tbo.resv) {
2461 2462 2463 2464 2465
			if (bo->tbo.type == ttm_bo_type_kernel)
				list_move(&bo_base->vm_status, &vm->evicted);
			else
				list_move_tail(&bo_base->vm_status,
					       &vm->evicted);
2466 2467 2468
			continue;
		}

2469
		if (was_moved)
2470 2471
			continue;

2472 2473 2474 2475 2476 2477 2478
		if (bo->tbo.type == ttm_bo_type_kernel) {
			list_move(&bo_base->vm_status, &vm->relocated);
		} else {
			spin_lock(&bo_base->vm->moved_lock);
			list_move(&bo_base->vm_status, &vm->moved);
			spin_unlock(&bo_base->vm->moved_lock);
		}
A
Alex Deucher 已提交
2479 2480 2481
	}
}

2482 2483 2484 2485 2486 2487 2488 2489
/**
 * amdgpu_vm_get_block_size - calculate VM page table size as power of two
 *
 * @vm_size: VM size
 *
 * Returns:
 * VM page table as power of two
 */
2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502
static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
{
	/* Total bits covered by PD + PTs */
	unsigned bits = ilog2(vm_size) + 18;

	/* Make sure the PD is 4K in size up to 8GB address space.
	   Above that split equal between PD and PTs */
	if (vm_size <= 8)
		return (bits - 9);
	else
		return ((bits + 3) / 2);
}

2503 2504
/**
 * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
2505 2506
 *
 * @adev: amdgpu_device pointer
2507
 * @min_vm_size: the minimum vm size in GB if it's set auto
2508 2509 2510 2511
 * @fragment_size_default: Default PTE fragment size
 * @max_level: max VMPT level
 * @max_bits: max address space size in bits
 *
2512
 */
2513
void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
2514 2515
			   uint32_t fragment_size_default, unsigned max_level,
			   unsigned max_bits)
2516
{
2517 2518
	unsigned int max_size = 1 << (max_bits - 30);
	unsigned int vm_size;
2519 2520 2521
	uint64_t tmp;

	/* adjust vm size first */
2522
	if (amdgpu_vm_size != -1) {
2523
		vm_size = amdgpu_vm_size;
2524 2525 2526 2527 2528
		if (vm_size > max_size) {
			dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",
				 amdgpu_vm_size, max_size);
			vm_size = max_size;
		}
2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552
	} else {
		struct sysinfo si;
		unsigned int phys_ram_gb;

		/* Optimal VM size depends on the amount of physical
		 * RAM available. Underlying requirements and
		 * assumptions:
		 *
		 *  - Need to map system memory and VRAM from all GPUs
		 *     - VRAM from other GPUs not known here
		 *     - Assume VRAM <= system memory
		 *  - On GFX8 and older, VM space can be segmented for
		 *    different MTYPEs
		 *  - Need to allow room for fragmentation, guard pages etc.
		 *
		 * This adds up to a rough guess of system memory x3.
		 * Round up to power of two to maximize the available
		 * VM size with the given page table size.
		 */
		si_meminfo(&si);
		phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit +
			       (1 << 30) - 1) >> 30;
		vm_size = roundup_pow_of_two(
			min(max(phys_ram_gb * 3, min_vm_size), max_size));
2553
	}
2554 2555

	adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
2556 2557

	tmp = roundup_pow_of_two(adev->vm_manager.max_pfn);
2558 2559
	if (amdgpu_vm_block_size != -1)
		tmp >>= amdgpu_vm_block_size - 9;
2560 2561
	tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
	adev->vm_manager.num_level = min(max_level, (unsigned)tmp);
2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574
	switch (adev->vm_manager.num_level) {
	case 3:
		adev->vm_manager.root_level = AMDGPU_VM_PDB2;
		break;
	case 2:
		adev->vm_manager.root_level = AMDGPU_VM_PDB1;
		break;
	case 1:
		adev->vm_manager.root_level = AMDGPU_VM_PDB0;
		break;
	default:
		dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n");
	}
2575
	/* block size depends on vm size and hw setup*/
2576
	if (amdgpu_vm_block_size != -1)
2577
		adev->vm_manager.block_size =
2578 2579 2580 2581 2582
			min((unsigned)amdgpu_vm_block_size, max_bits
			    - AMDGPU_GPU_PAGE_SHIFT
			    - 9 * adev->vm_manager.num_level);
	else if (adev->vm_manager.num_level > 1)
		adev->vm_manager.block_size = 9;
2583
	else
2584
		adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp);
2585

2586 2587 2588 2589
	if (amdgpu_vm_fragment_size == -1)
		adev->vm_manager.fragment_size = fragment_size_default;
	else
		adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
2590

2591 2592 2593
	DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",
		 vm_size, adev->vm_manager.num_level + 1,
		 adev->vm_manager.block_size,
2594
		 adev->vm_manager.fragment_size);
2595 2596
}

A
Alex Deucher 已提交
2597 2598 2599 2600 2601
/**
 * amdgpu_vm_init - initialize a vm instance
 *
 * @adev: amdgpu_device pointer
 * @vm: requested vm
2602
 * @vm_context: Indicates if it GFX or Compute context
2603
 * @pasid: Process address space identifier
A
Alex Deucher 已提交
2604
 *
2605
 * Init @vm fields.
2606 2607 2608
 *
 * Returns:
 * 0 for success, error for failure.
A
Alex Deucher 已提交
2609
 */
2610
int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
2611
		   int vm_context, unsigned int pasid)
A
Alex Deucher 已提交
2612
{
2613
	struct amdgpu_bo_param bp;
2614
	struct amdgpu_bo *root;
2615
	unsigned long size;
2616
	uint64_t flags;
2617
	int r, i;
A
Alex Deucher 已提交
2618

2619
	vm->va = RB_ROOT_CACHED;
2620 2621
	for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
		vm->reserved_vmid[i] = NULL;
2622
	INIT_LIST_HEAD(&vm->evicted);
2623
	INIT_LIST_HEAD(&vm->relocated);
2624
	spin_lock_init(&vm->moved_lock);
2625
	INIT_LIST_HEAD(&vm->moved);
2626
	INIT_LIST_HEAD(&vm->idle);
A
Alex Deucher 已提交
2627
	INIT_LIST_HEAD(&vm->freed);
2628

2629
	/* create scheduler entity for page table updates */
2630 2631
	r = drm_sched_entity_init(&vm->entity, adev->vm_manager.vm_pte_rqs,
				  adev->vm_manager.vm_pte_num_rqs, NULL);
2632
	if (r)
2633
		return r;
2634

Y
Yong Zhao 已提交
2635
	vm->pte_support_ats = false;
2636
	vm->bulk_moveable = true;
Y
Yong Zhao 已提交
2637 2638

	if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) {
2639 2640
		vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
						AMDGPU_VM_USE_CPU_FOR_COMPUTE);
Y
Yong Zhao 已提交
2641

2642
		if (adev->asic_type == CHIP_RAVEN)
Y
Yong Zhao 已提交
2643
			vm->pte_support_ats = true;
2644
	} else {
2645 2646
		vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
						AMDGPU_VM_USE_CPU_FOR_GFX);
2647
	}
2648 2649
	DRM_DEBUG_DRIVER("VM update mode is %s\n",
			 vm->use_cpu_for_update ? "CPU" : "SDMA");
2650
	WARN_ONCE((vm->use_cpu_for_update & !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2651
		  "CPU update of VM recommended only for large BAR system\n");
2652
	vm->last_update = NULL;
2653

2654
	flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
2655 2656
	if (vm->use_cpu_for_update)
		flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
2657
	else if (vm_context != AMDGPU_VM_CONTEXT_COMPUTE)
2658
		flags |= AMDGPU_GEM_CREATE_SHADOW;
2659

2660
	size = amdgpu_vm_bo_size(adev, adev->vm_manager.root_level);
2661 2662
	memset(&bp, 0, sizeof(bp));
	bp.size = size;
2663
	bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
2664 2665 2666 2667
	bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
	bp.flags = flags;
	bp.type = ttm_bo_type_kernel;
	bp.resv = NULL;
2668
	r = amdgpu_bo_create(adev, &bp, &root);
A
Alex Deucher 已提交
2669
	if (r)
2670 2671
		goto error_free_sched_entity;

2672
	r = amdgpu_bo_reserve(root, true);
2673 2674 2675
	if (r)
		goto error_free_root;

2676
	r = amdgpu_vm_clear_bo(adev, vm, root,
2677 2678
			       adev->vm_manager.root_level,
			       vm->pte_support_ats);
2679 2680 2681
	if (r)
		goto error_unreserve;

2682
	amdgpu_vm_bo_base_init(&vm->root.base, vm, root);
2683
	amdgpu_bo_unreserve(vm->root.base.bo);
A
Alex Deucher 已提交
2684

2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695
	if (pasid) {
		unsigned long flags;

		spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
		r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
			      GFP_ATOMIC);
		spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
		if (r < 0)
			goto error_free_root;

		vm->pasid = pasid;
2696 2697
	}

2698
	INIT_KFIFO(vm->faults);
2699
	vm->fault_credit = 16;
A
Alex Deucher 已提交
2700 2701

	return 0;
2702

2703 2704 2705
error_unreserve:
	amdgpu_bo_unreserve(vm->root.base.bo);

2706
error_free_root:
2707 2708 2709
	amdgpu_bo_unref(&vm->root.base.bo->shadow);
	amdgpu_bo_unref(&vm->root.base.bo);
	vm->root.base.bo = NULL;
2710 2711

error_free_sched_entity:
2712
	drm_sched_entity_destroy(&vm->entity);
2713 2714

	return r;
A
Alex Deucher 已提交
2715 2716
}

2717 2718 2719
/**
 * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM
 *
2720 2721 2722
 * @adev: amdgpu_device pointer
 * @vm: requested vm
 *
2723 2724 2725 2726 2727 2728 2729 2730 2731
 * This only works on GFX VMs that don't have any BOs added and no
 * page tables allocated yet.
 *
 * Changes the following VM parameters:
 * - use_cpu_for_update
 * - pte_supports_ats
 * - pasid (old PASID is released, because compute manages its own PASIDs)
 *
 * Reinitializes the page directory to reflect the changed ATS
2732
 * setting.
2733
 *
2734 2735
 * Returns:
 * 0 for success, -errno for errors.
2736 2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767 2768
 */
int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
{
	bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
	int r;

	r = amdgpu_bo_reserve(vm->root.base.bo, true);
	if (r)
		return r;

	/* Sanity checks */
	if (!RB_EMPTY_ROOT(&vm->va.rb_root) || vm->root.entries) {
		r = -EINVAL;
		goto error;
	}

	/* Check if PD needs to be reinitialized and do it before
	 * changing any other state, in case it fails.
	 */
	if (pte_support_ats != vm->pte_support_ats) {
		r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo,
			       adev->vm_manager.root_level,
			       pte_support_ats);
		if (r)
			goto error;
	}

	/* Update VM state */
	vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
				    AMDGPU_VM_USE_CPU_FOR_COMPUTE);
	vm->pte_support_ats = pte_support_ats;
	DRM_DEBUG_DRIVER("VM update mode is %s\n",
			 vm->use_cpu_for_update ? "CPU" : "SDMA");
2769
	WARN_ONCE((vm->use_cpu_for_update & !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2770 2771 2772 2773 2774 2775 2776 2777 2778 2779 2780 2781
		  "CPU update of VM recommended only for large BAR system\n");

	if (vm->pasid) {
		unsigned long flags;

		spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
		idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
		spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);

		vm->pasid = 0;
	}

2782 2783 2784
	/* Free the shadow bo for compute VM */
	amdgpu_bo_unref(&vm->root.base.bo->shadow);

2785 2786 2787 2788 2789
error:
	amdgpu_bo_unreserve(vm->root.base.bo);
	return r;
}

2790 2791 2792
/**
 * amdgpu_vm_free_levels - free PD/PT levels
 *
2793 2794 2795
 * @adev: amdgpu device structure
 * @parent: PD/PT starting level to free
 * @level: level of parent structure
2796 2797 2798
 *
 * Free the page directory or page table level and all sub levels.
 */
2799 2800 2801
static void amdgpu_vm_free_levels(struct amdgpu_device *adev,
				  struct amdgpu_vm_pt *parent,
				  unsigned level)
2802
{
2803
	unsigned i, num_entries = amdgpu_vm_num_entries(adev, level);
2804

2805 2806 2807 2808 2809
	if (parent->base.bo) {
		list_del(&parent->base.bo_list);
		list_del(&parent->base.vm_status);
		amdgpu_bo_unref(&parent->base.bo->shadow);
		amdgpu_bo_unref(&parent->base.bo);
2810 2811
	}

2812 2813 2814 2815
	if (parent->entries)
		for (i = 0; i < num_entries; i++)
			amdgpu_vm_free_levels(adev, &parent->entries[i],
					      level + 1);
2816

2817
	kvfree(parent->entries);
2818 2819
}

A
Alex Deucher 已提交
2820 2821 2822 2823 2824 2825
/**
 * amdgpu_vm_fini - tear down a vm instance
 *
 * @adev: amdgpu_device pointer
 * @vm: requested vm
 *
2826
 * Tear down @vm.
A
Alex Deucher 已提交
2827 2828 2829 2830 2831
 * Unbind the VM and remove all bos from the vm bo list
 */
void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
{
	struct amdgpu_bo_va_mapping *mapping, *tmp;
2832
	bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt;
2833
	struct amdgpu_bo *root;
2834
	u64 fault;
2835
	int i, r;
A
Alex Deucher 已提交
2836

2837 2838
	amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);

2839 2840 2841 2842
	/* Clear pending page faults from IH when the VM is destroyed */
	while (kfifo_get(&vm->faults, &fault))
		amdgpu_ih_clear_fault(adev, fault);

2843 2844 2845 2846 2847 2848 2849 2850
	if (vm->pasid) {
		unsigned long flags;

		spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
		idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
		spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
	}

2851
	drm_sched_entity_destroy(&vm->entity);
2852

2853
	if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
A
Alex Deucher 已提交
2854 2855
		dev_err(adev->dev, "still active bo inside vm\n");
	}
2856 2857
	rbtree_postorder_for_each_entry_safe(mapping, tmp,
					     &vm->va.rb_root, rb) {
A
Alex Deucher 已提交
2858
		list_del(&mapping->list);
2859
		amdgpu_vm_it_remove(mapping, &vm->va);
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Alex Deucher 已提交
2860 2861 2862
		kfree(mapping);
	}
	list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
2863
		if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
2864
			amdgpu_vm_prt_fini(adev, vm);
2865
			prt_fini_needed = false;
2866
		}
2867

A
Alex Deucher 已提交
2868
		list_del(&mapping->list);
2869
		amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
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Alex Deucher 已提交
2870 2871
	}

2872 2873 2874 2875 2876
	root = amdgpu_bo_ref(vm->root.base.bo);
	r = amdgpu_bo_reserve(root, true);
	if (r) {
		dev_err(adev->dev, "Leaking page tables because BO reservation failed\n");
	} else {
2877 2878
		amdgpu_vm_free_levels(adev, &vm->root,
				      adev->vm_manager.root_level);
2879 2880 2881
		amdgpu_bo_unreserve(root);
	}
	amdgpu_bo_unref(&root);
2882
	dma_fence_put(vm->last_update);
2883
	for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2884
		amdgpu_vmid_free_reserved(adev, vm, i);
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Alex Deucher 已提交
2885
}
2886

2887 2888 2889 2890 2891 2892
/**
 * amdgpu_vm_pasid_fault_credit - Check fault credit for given PASID
 *
 * @adev: amdgpu_device pointer
 * @pasid: PASID do identify the VM
 *
2893 2894 2895 2896
 * This function is expected to be called in interrupt context.
 *
 * Returns:
 * True if there was fault credit, false otherwise
2897 2898 2899 2900 2901 2902 2903 2904
 */
bool amdgpu_vm_pasid_fault_credit(struct amdgpu_device *adev,
				  unsigned int pasid)
{
	struct amdgpu_vm *vm;

	spin_lock(&adev->vm_manager.pasid_lock);
	vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
2905
	if (!vm) {
2906
		/* VM not found, can't track fault credit */
2907
		spin_unlock(&adev->vm_manager.pasid_lock);
2908
		return true;
2909
	}
2910 2911

	/* No lock needed. only accessed by IRQ handler */
2912
	if (!vm->fault_credit) {
2913
		/* Too many faults in this VM */
2914
		spin_unlock(&adev->vm_manager.pasid_lock);
2915
		return false;
2916
	}
2917 2918

	vm->fault_credit--;
2919
	spin_unlock(&adev->vm_manager.pasid_lock);
2920 2921 2922
	return true;
}

2923 2924 2925 2926 2927 2928 2929 2930 2931
/**
 * amdgpu_vm_manager_init - init the VM manager
 *
 * @adev: amdgpu_device pointer
 *
 * Initialize the VM manager structures
 */
void amdgpu_vm_manager_init(struct amdgpu_device *adev)
{
2932
	unsigned i;
2933

2934
	amdgpu_vmid_mgr_init(adev);
2935

2936 2937
	adev->vm_manager.fence_context =
		dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2938 2939 2940
	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
		adev->vm_manager.seqno[i] = 0;

2941
	spin_lock_init(&adev->vm_manager.prt_lock);
2942
	atomic_set(&adev->vm_manager.num_prt_users, 0);
2943 2944 2945 2946 2947 2948

	/* If not overridden by the user, by default, only in large BAR systems
	 * Compute VM tables will be updated by CPU
	 */
#ifdef CONFIG_X86_64
	if (amdgpu_vm_update_mode == -1) {
2949
		if (amdgpu_gmc_vram_full_visible(&adev->gmc))
2950 2951 2952 2953 2954 2955 2956 2957 2958 2959
			adev->vm_manager.vm_update_mode =
				AMDGPU_VM_USE_CPU_FOR_COMPUTE;
		else
			adev->vm_manager.vm_update_mode = 0;
	} else
		adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode;
#else
	adev->vm_manager.vm_update_mode = 0;
#endif

2960 2961
	idr_init(&adev->vm_manager.pasid_idr);
	spin_lock_init(&adev->vm_manager.pasid_lock);
2962 2963
}

2964 2965 2966 2967 2968 2969 2970 2971 2972
/**
 * amdgpu_vm_manager_fini - cleanup VM manager
 *
 * @adev: amdgpu_device pointer
 *
 * Cleanup the VM manager and free resources.
 */
void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
{
2973 2974 2975
	WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr));
	idr_destroy(&adev->vm_manager.pasid_idr);

2976
	amdgpu_vmid_mgr_fini(adev);
2977
}
C
Chunming Zhou 已提交
2978

2979 2980 2981 2982 2983 2984 2985 2986 2987 2988
/**
 * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs.
 *
 * @dev: drm device pointer
 * @data: drm_amdgpu_vm
 * @filp: drm file pointer
 *
 * Returns:
 * 0 for success, -errno for errors.
 */
C
Chunming Zhou 已提交
2989 2990 2991
int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
{
	union drm_amdgpu_vm *args = data;
2992 2993 2994
	struct amdgpu_device *adev = dev->dev_private;
	struct amdgpu_fpriv *fpriv = filp->driver_priv;
	int r;
C
Chunming Zhou 已提交
2995 2996 2997

	switch (args->in.op) {
	case AMDGPU_VM_OP_RESERVE_VMID:
2998
		/* current, we only have requirement to reserve vmid from gfxhub */
2999
		r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB);
3000 3001 3002
		if (r)
			return r;
		break;
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Chunming Zhou 已提交
3003
	case AMDGPU_VM_OP_UNRESERVE_VMID:
3004
		amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB);
C
Chunming Zhou 已提交
3005 3006 3007 3008 3009 3010 3011
		break;
	default:
		return -EINVAL;
	}

	return 0;
}
3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 3027 3028 3029 3030 3031 3032 3033 3034 3035 3036 3037 3038 3039 3040 3041 3042 3043 3044 3045 3046 3047 3048 3049 3050

/**
 * amdgpu_vm_get_task_info - Extracts task info for a PASID.
 *
 * @dev: drm device pointer
 * @pasid: PASID identifier for VM
 * @task_info: task_info to fill.
 */
void amdgpu_vm_get_task_info(struct amdgpu_device *adev, unsigned int pasid,
			 struct amdgpu_task_info *task_info)
{
	struct amdgpu_vm *vm;

	spin_lock(&adev->vm_manager.pasid_lock);

	vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
	if (vm)
		*task_info = vm->task_info;

	spin_unlock(&adev->vm_manager.pasid_lock);
}

/**
 * amdgpu_vm_set_task_info - Sets VMs task info.
 *
 * @vm: vm for which to set the info
 */
void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)
{
	if (!vm->task_info.pid) {
		vm->task_info.pid = current->pid;
		get_task_comm(vm->task_info.task_name, current);

		if (current->group_leader->mm == current->mm) {
			vm->task_info.tgid = current->group_leader->pid;
			get_task_comm(vm->task_info.process_name, current->group_leader);
		}
	}
}