amdgpu_vm.c 74.3 KB
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/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
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#include <linux/dma-fence-array.h>
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#include <linux/interval_tree_generic.h>
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#include <linux/idr.h>
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#include <drm/drmP.h>
#include <drm/amdgpu_drm.h>
#include "amdgpu.h"
#include "amdgpu_trace.h"
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#include "amdgpu_amdkfd.h"
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#include "amdgpu_gmc.h"
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/**
 * DOC: GPUVM
 *
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 * GPUVM is similar to the legacy gart on older asics, however
 * rather than there being a single global gart table
 * for the entire GPU, there are multiple VM page tables active
 * at any given time.  The VM page tables can contain a mix
 * vram pages and system memory pages and system memory pages
 * can be mapped as snooped (cached system pages) or unsnooped
 * (uncached system pages).
 * Each VM has an ID associated with it and there is a page table
 * associated with each VMID.  When execting a command buffer,
 * the kernel tells the the ring what VMID to use for that command
 * buffer.  VMIDs are allocated dynamically as commands are submitted.
 * The userspace drivers maintain their own address space and the kernel
 * sets up their pages tables accordingly when they submit their
 * command buffers and a VMID is assigned.
 * Cayman/Trinity support up to 8 active VMs at any given time;
 * SI supports 16.
 */

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#define START(node) ((node)->start)
#define LAST(node) ((node)->last)

INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
		     START, LAST, static, amdgpu_vm_it)

#undef START
#undef LAST

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/**
 * struct amdgpu_pte_update_params - Local structure
 *
 * Encapsulate some VM table update parameters to reduce
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 * the number of function parameters
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 *
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 */
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struct amdgpu_pte_update_params {
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	/**
	 * @adev: amdgpu device we do this update for
	 */
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	struct amdgpu_device *adev;
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	/**
	 * @vm: optional amdgpu_vm we do this update for
	 */
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	struct amdgpu_vm *vm;
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	/**
	 * @src: address where to copy page table entries from
	 */
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	uint64_t src;
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	/**
	 * @ib: indirect buffer to fill with commands
	 */
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	struct amdgpu_ib *ib;
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	/**
	 * @func: Function which actually does the update
	 */
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	void (*func)(struct amdgpu_pte_update_params *params,
		     struct amdgpu_bo *bo, uint64_t pe,
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		     uint64_t addr, unsigned count, uint32_t incr,
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		     uint64_t flags);
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	/**
	 * @pages_addr:
	 *
	 * DMA addresses to use for mapping, used during VM update by CPU
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	 */
	dma_addr_t *pages_addr;
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	/**
	 * @kptr:
	 *
	 * Kernel pointer of PD/PT BO that needs to be updated,
	 * used during VM update by CPU
	 */
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	void *kptr;
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};

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/**
 * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback
 */
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struct amdgpu_prt_cb {
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	/**
	 * @adev: amdgpu device
	 */
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	struct amdgpu_device *adev;
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	/**
	 * @cb: callback
	 */
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	struct dma_fence_cb cb;
};

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/**
 * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm
 *
 * @base: base structure for tracking BO usage in a VM
 * @vm: vm to which bo is to be added
 * @bo: amdgpu buffer object
 *
 * Initialize a bo_va_base structure and add it to the appropriate lists
 *
 */
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static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
				   struct amdgpu_vm *vm,
				   struct amdgpu_bo *bo)
{
	base->vm = vm;
	base->bo = bo;
	INIT_LIST_HEAD(&base->bo_list);
	INIT_LIST_HEAD(&base->vm_status);

	if (!bo)
		return;
	list_add_tail(&base->bo_list, &bo->va);

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	if (bo->tbo.type == ttm_bo_type_kernel)
		list_move(&base->vm_status, &vm->relocated);

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	if (bo->tbo.resv != vm->root.base.bo->tbo.resv)
		return;

	if (bo->preferred_domains &
	    amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type))
		return;

	/*
	 * we checked all the prerequisites, but it looks like this per vm bo
	 * is currently evicted. add the bo to the evicted list to make sure it
	 * is validated on next vm use to avoid fault.
	 * */
	list_move_tail(&base->vm_status, &vm->evicted);
}

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/**
 * amdgpu_vm_level_shift - return the addr shift for each level
 *
 * @adev: amdgpu_device pointer
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 * @level: VMPT level
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 *
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 * Returns:
 * The number of bits the pfn needs to be right shifted for a level.
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 */
static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev,
				      unsigned level)
{
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	unsigned shift = 0xff;

	switch (level) {
	case AMDGPU_VM_PDB2:
	case AMDGPU_VM_PDB1:
	case AMDGPU_VM_PDB0:
		shift = 9 * (AMDGPU_VM_PDB0 - level) +
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			adev->vm_manager.block_size;
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		break;
	case AMDGPU_VM_PTB:
		shift = 0;
		break;
	default:
		dev_err(adev->dev, "the level%d isn't supported.\n", level);
	}

	return shift;
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}

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/**
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 * amdgpu_vm_num_entries - return the number of entries in a PD/PT
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 *
 * @adev: amdgpu_device pointer
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 * @level: VMPT level
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 *
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 * Returns:
 * The number of entries in a page directory or page table.
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 */
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static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
				      unsigned level)
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{
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	unsigned shift = amdgpu_vm_level_shift(adev,
					       adev->vm_manager.root_level);
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	if (level == adev->vm_manager.root_level)
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		/* For the root directory */
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		return round_up(adev->vm_manager.max_pfn, 1 << shift) >> shift;
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	else if (level != AMDGPU_VM_PTB)
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		/* Everything in between */
		return 512;
	else
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		/* For the page tables on the leaves */
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		return AMDGPU_VM_PTE_COUNT(adev);
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}

/**
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 * amdgpu_vm_bo_size - returns the size of the BOs in bytes
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 *
 * @adev: amdgpu_device pointer
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 * @level: VMPT level
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 *
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 * Returns:
 * The size of the BO for a page directory or page table in bytes.
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 */
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static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level)
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{
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	return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8);
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}

/**
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 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
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 *
 * @vm: vm providing the BOs
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 * @validated: head of validation list
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 * @entry: entry to add
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 *
 * Add the page directory to the list of BOs to
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 * validate for command submission.
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 */
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void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
			 struct list_head *validated,
			 struct amdgpu_bo_list_entry *entry)
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{
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	entry->robj = vm->root.base.bo;
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	entry->priority = 0;
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	entry->tv.bo = &entry->robj->tbo;
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	entry->tv.shared = true;
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	entry->user_pages = NULL;
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	list_add(&entry->tv.head, validated);
}
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/**
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 * amdgpu_vm_validate_pt_bos - validate the page table BOs
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 *
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 * @adev: amdgpu device pointer
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 * @vm: vm providing the BOs
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 * @validate: callback to do the validation
 * @param: parameter for the validation callback
 *
 * Validate the page table BOs on command submission if neccessary.
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 *
 * Returns:
 * Validation result.
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 */
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int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
			      int (*validate)(void *p, struct amdgpu_bo *bo),
			      void *param)
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{
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	struct ttm_bo_global *glob = adev->mman.bdev.glob;
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	struct amdgpu_vm_bo_base *bo_base, *tmp;
	int r = 0;
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	list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) {
		struct amdgpu_bo *bo = bo_base->bo;
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		if (bo->parent) {
			r = validate(param, bo);
			if (r)
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				break;
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			spin_lock(&glob->lru_lock);
			ttm_bo_move_to_lru_tail(&bo->tbo);
			if (bo->shadow)
				ttm_bo_move_to_lru_tail(&bo->shadow->tbo);
			spin_unlock(&glob->lru_lock);
		}
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		if (bo->tbo.type != ttm_bo_type_kernel) {
			spin_lock(&vm->moved_lock);
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			list_move(&bo_base->vm_status, &vm->moved);
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			spin_unlock(&vm->moved_lock);
		} else {
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			list_move(&bo_base->vm_status, &vm->relocated);
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		}
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	}

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	spin_lock(&glob->lru_lock);
	list_for_each_entry(bo_base, &vm->idle, vm_status) {
		struct amdgpu_bo *bo = bo_base->bo;

		if (!bo->parent)
			continue;

		ttm_bo_move_to_lru_tail(&bo->tbo);
		if (bo->shadow)
			ttm_bo_move_to_lru_tail(&bo->shadow->tbo);
	}
	spin_unlock(&glob->lru_lock);

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	return r;
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}

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/**
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 * amdgpu_vm_ready - check VM is ready for updates
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 *
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 * @vm: VM to check
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 *
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 * Check if all VM PDs/PTs are ready for updates
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 *
 * Returns:
 * True if eviction list is empty.
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 */
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bool amdgpu_vm_ready(struct amdgpu_vm *vm)
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{
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	return list_empty(&vm->evicted);
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}

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/**
 * amdgpu_vm_clear_bo - initially clear the PDs/PTs
 *
 * @adev: amdgpu_device pointer
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 * @vm: VM to clear BO from
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 * @bo: BO to clear
 * @level: level this BO is at
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 * @pte_support_ats: indicate ATS support from PTE
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 *
 * Root PD needs to be reserved when calling this.
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 *
 * Returns:
 * 0 on success, errno otherwise.
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 */
static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
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			      struct amdgpu_vm *vm, struct amdgpu_bo *bo,
			      unsigned level, bool pte_support_ats)
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{
	struct ttm_operation_ctx ctx = { true, false };
	struct dma_fence *fence = NULL;
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	unsigned entries, ats_entries;
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	struct amdgpu_ring *ring;
	struct amdgpu_job *job;
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	uint64_t addr;
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	int r;

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	addr = amdgpu_bo_gpu_offset(bo);
	entries = amdgpu_bo_size(bo) / 8;

	if (pte_support_ats) {
		if (level == adev->vm_manager.root_level) {
			ats_entries = amdgpu_vm_level_shift(adev, level);
			ats_entries += AMDGPU_GPU_PAGE_SHIFT;
			ats_entries = AMDGPU_VA_HOLE_START >> ats_entries;
			ats_entries = min(ats_entries, entries);
			entries -= ats_entries;
		} else {
			ats_entries = entries;
			entries = 0;
		}
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	} else {
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		ats_entries = 0;
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	}

	ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);

	r = reservation_object_reserve_shared(bo->tbo.resv);
	if (r)
		return r;

	r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
	if (r)
		goto error;

	r = amdgpu_job_alloc_with_ib(adev, 64, &job);
	if (r)
		goto error;

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	if (ats_entries) {
		uint64_t ats_value;

		ats_value = AMDGPU_PTE_DEFAULT_ATC;
		if (level != AMDGPU_VM_PTB)
			ats_value |= AMDGPU_PDE_PTE;

		amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0,
				      ats_entries, 0, ats_value);
		addr += ats_entries * 8;
	}

	if (entries)
		amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0,
				      entries, 0, 0);

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	amdgpu_ring_pad_ib(ring, &job->ibs[0]);

	WARN_ON(job->ibs[0].length_dw > 64);
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	r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.resv,
			     AMDGPU_FENCE_OWNER_UNDEFINED, false);
	if (r)
		goto error_free;

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	r = amdgpu_job_submit(job, &vm->entity, AMDGPU_FENCE_OWNER_UNDEFINED,
			      &fence);
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	if (r)
		goto error_free;

	amdgpu_bo_fence(bo, fence, true);
	dma_fence_put(fence);
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	if (bo->shadow)
		return amdgpu_vm_clear_bo(adev, vm, bo->shadow,
					  level, pte_support_ats);

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	return 0;

error_free:
	amdgpu_job_free(job);

error:
	return r;
}

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/**
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 * amdgpu_vm_alloc_levels - allocate the PD/PT levels
 *
 * @adev: amdgpu_device pointer
 * @vm: requested vm
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 * @parent: parent PT
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 * @saddr: start of the address range
 * @eaddr: end of the address range
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 * @level: VMPT level
 * @ats: indicate ATS support from PTE
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 *
 * Make sure the page directories and page tables are allocated
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 *
 * Returns:
 * 0 on success, errno otherwise.
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 */
static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
				  struct amdgpu_vm *vm,
				  struct amdgpu_vm_pt *parent,
				  uint64_t saddr, uint64_t eaddr,
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				  unsigned level, bool ats)
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{
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	unsigned shift = amdgpu_vm_level_shift(adev, level);
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	unsigned pt_idx, from, to;
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	u64 flags;
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	int r;
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	if (!parent->entries) {
		unsigned num_entries = amdgpu_vm_num_entries(adev, level);

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		parent->entries = kvmalloc_array(num_entries,
						   sizeof(struct amdgpu_vm_pt),
						   GFP_KERNEL | __GFP_ZERO);
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		if (!parent->entries)
			return -ENOMEM;
		memset(parent->entries, 0 , sizeof(struct amdgpu_vm_pt));
	}

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	from = saddr >> shift;
	to = eaddr >> shift;
	if (from >= amdgpu_vm_num_entries(adev, level) ||
	    to >= amdgpu_vm_num_entries(adev, level))
		return -EINVAL;
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	++level;
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	saddr = saddr & ((1 << shift) - 1);
	eaddr = eaddr & ((1 << shift) - 1);
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	flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
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	if (vm->use_cpu_for_update)
		flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
	else
		flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
				AMDGPU_GEM_CREATE_SHADOW);

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	/* walk over the address space and allocate the page tables */
	for (pt_idx = from; pt_idx <= to; ++pt_idx) {
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		struct reservation_object *resv = vm->root.base.bo->tbo.resv;
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		struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
		struct amdgpu_bo *pt;

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		if (!entry->base.bo) {
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			struct amdgpu_bo_param bp;

			memset(&bp, 0, sizeof(bp));
			bp.size = amdgpu_vm_bo_size(adev, level);
			bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
			bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
			bp.flags = flags;
			bp.type = ttm_bo_type_kernel;
			bp.resv = resv;
			r = amdgpu_bo_create(adev, &bp, &pt);
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			if (r)
				return r;

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			r = amdgpu_vm_clear_bo(adev, vm, pt, level, ats);
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			if (r) {
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				amdgpu_bo_unref(&pt->shadow);
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				amdgpu_bo_unref(&pt);
				return r;
			}

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			if (vm->use_cpu_for_update) {
				r = amdgpu_bo_kmap(pt, NULL);
				if (r) {
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					amdgpu_bo_unref(&pt->shadow);
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					amdgpu_bo_unref(&pt);
					return r;
				}
			}

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			/* Keep a reference to the root directory to avoid
			* freeing them up in the wrong order.
			*/
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			pt->parent = amdgpu_bo_ref(parent->base.bo);
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			amdgpu_vm_bo_base_init(&entry->base, vm, pt);
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		}

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		if (level < AMDGPU_VM_PTB) {
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			uint64_t sub_saddr = (pt_idx == from) ? saddr : 0;
			uint64_t sub_eaddr = (pt_idx == to) ? eaddr :
				((1 << shift) - 1);
			r = amdgpu_vm_alloc_levels(adev, vm, entry, sub_saddr,
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						   sub_eaddr, level, ats);
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			if (r)
				return r;
		}
	}

	return 0;
}

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/**
 * amdgpu_vm_alloc_pts - Allocate page tables.
 *
 * @adev: amdgpu_device pointer
 * @vm: VM to allocate page tables for
 * @saddr: Start address which needs to be allocated
 * @size: Size from start address we need.
 *
 * Make sure the page tables are allocated.
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 *
 * Returns:
 * 0 on success, errno otherwise.
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 */
int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
			struct amdgpu_vm *vm,
			uint64_t saddr, uint64_t size)
{
	uint64_t eaddr;
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	bool ats = false;
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	/* validate the parameters */
	if (saddr & AMDGPU_GPU_PAGE_MASK || size & AMDGPU_GPU_PAGE_MASK)
		return -EINVAL;

	eaddr = saddr + size - 1;
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	if (vm->pte_support_ats)
		ats = saddr < AMDGPU_VA_HOLE_START;
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	saddr /= AMDGPU_GPU_PAGE_SIZE;
	eaddr /= AMDGPU_GPU_PAGE_SIZE;

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	if (eaddr >= adev->vm_manager.max_pfn) {
		dev_err(adev->dev, "va above limit (0x%08llX >= 0x%08llX)\n",
			eaddr, adev->vm_manager.max_pfn);
		return -EINVAL;
	}

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	return amdgpu_vm_alloc_levels(adev, vm, &vm->root, saddr, eaddr,
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				      adev->vm_manager.root_level, ats);
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}

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/**
 * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
 *
 * @adev: amdgpu_device pointer
 */
void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
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{
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	const struct amdgpu_ip_block *ip_block;
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	bool has_compute_vm_bug;
	struct amdgpu_ring *ring;
	int i;
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	has_compute_vm_bug = false;
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	ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
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	if (ip_block) {
		/* Compute has a VM bug for GFX version < 7.
		   Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
		if (ip_block->version->major <= 7)
			has_compute_vm_bug = true;
		else if (ip_block->version->major == 8)
			if (adev->gfx.mec_fw_version < 673)
				has_compute_vm_bug = true;
	}
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	for (i = 0; i < adev->num_rings; i++) {
		ring = adev->rings[i];
		if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
			/* only compute rings */
			ring->has_compute_vm_bug = has_compute_vm_bug;
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		else
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			ring->has_compute_vm_bug = false;
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	}
}

639 640 641 642 643 644 645 646 647
/**
 * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job.
 *
 * @ring: ring on which the job will be submitted
 * @job: job to submit
 *
 * Returns:
 * True if sync is needed.
 */
648 649
bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
				  struct amdgpu_job *job)
A
Alex Xie 已提交
650
{
651 652
	struct amdgpu_device *adev = ring->adev;
	unsigned vmhub = ring->funcs->vmhub;
653 654
	struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
	struct amdgpu_vmid *id;
655
	bool gds_switch_needed;
656
	bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug;
657

658
	if (job->vmid == 0)
659
		return false;
660
	id = &id_mgr->ids[job->vmid];
661 662 663 664 665 666 667
	gds_switch_needed = ring->funcs->emit_gds_switch && (
		id->gds_base != job->gds_base ||
		id->gds_size != job->gds_size ||
		id->gws_base != job->gws_base ||
		id->gws_size != job->gws_size ||
		id->oa_base != job->oa_base ||
		id->oa_size != job->oa_size);
A
Alex Xie 已提交
668

669
	if (amdgpu_vmid_had_gpu_reset(adev, id))
670
		return true;
A
Alex Xie 已提交
671

672
	return vm_flush_needed || gds_switch_needed;
673 674
}

A
Alex Deucher 已提交
675 676 677 678
/**
 * amdgpu_vm_flush - hardware flush the vm
 *
 * @ring: ring to use for flush
679
 * @job:  related job
680
 * @need_pipe_sync: is pipe sync needed
A
Alex Deucher 已提交
681
 *
682
 * Emit a VM flush when it is necessary.
683 684 685
 *
 * Returns:
 * 0 on success, errno otherwise.
A
Alex Deucher 已提交
686
 */
M
Monk Liu 已提交
687
int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync)
A
Alex Deucher 已提交
688
{
689
	struct amdgpu_device *adev = ring->adev;
690
	unsigned vmhub = ring->funcs->vmhub;
691
	struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
692
	struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
693
	bool gds_switch_needed = ring->funcs->emit_gds_switch && (
694 695 696 697 698 699
		id->gds_base != job->gds_base ||
		id->gds_size != job->gds_size ||
		id->gws_base != job->gws_base ||
		id->gws_size != job->gws_size ||
		id->oa_base != job->oa_base ||
		id->oa_size != job->oa_size);
700
	bool vm_flush_needed = job->vm_needs_flush;
701 702 703 704
	bool pasid_mapping_needed = id->pasid != job->pasid ||
		!id->pasid_mapping ||
		!dma_fence_is_signaled(id->pasid_mapping);
	struct dma_fence *fence = NULL;
705
	unsigned patch_offset = 0;
706
	int r;
707

708
	if (amdgpu_vmid_had_gpu_reset(adev, id)) {
709 710
		gds_switch_needed = true;
		vm_flush_needed = true;
711
		pasid_mapping_needed = true;
712
	}
713

714 715 716 717 718
	gds_switch_needed &= !!ring->funcs->emit_gds_switch;
	vm_flush_needed &= !!ring->funcs->emit_vm_flush;
	pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping &&
		ring->funcs->emit_wreg;

M
Monk Liu 已提交
719
	if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync)
720
		return 0;
721

722 723
	if (ring->funcs->init_cond_exec)
		patch_offset = amdgpu_ring_init_cond_exec(ring);
724

M
Monk Liu 已提交
725 726 727
	if (need_pipe_sync)
		amdgpu_ring_emit_pipeline_sync(ring);

728
	if (vm_flush_needed) {
729
		trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
730
		amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
731 732 733 734
	}

	if (pasid_mapping_needed)
		amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
735

736
	if (vm_flush_needed || pasid_mapping_needed) {
737
		r = amdgpu_fence_emit(ring, &fence, 0);
738 739
		if (r)
			return r;
740
	}
741

742
	if (vm_flush_needed) {
743
		mutex_lock(&id_mgr->lock);
744
		dma_fence_put(id->last_flush);
745 746 747
		id->last_flush = dma_fence_get(fence);
		id->current_gpu_reset_count =
			atomic_read(&adev->gpu_reset_counter);
748
		mutex_unlock(&id_mgr->lock);
749
	}
750

751 752 753 754 755 756 757
	if (pasid_mapping_needed) {
		id->pasid = job->pasid;
		dma_fence_put(id->pasid_mapping);
		id->pasid_mapping = dma_fence_get(fence);
	}
	dma_fence_put(fence);

758
	if (ring->funcs->emit_gds_switch && gds_switch_needed) {
759 760 761 762 763 764
		id->gds_base = job->gds_base;
		id->gds_size = job->gds_size;
		id->gws_base = job->gws_base;
		id->gws_size = job->gws_size;
		id->oa_base = job->oa_base;
		id->oa_size = job->oa_size;
765
		amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
766 767 768 769 770 771 772 773 774 775 776 777
					    job->gds_size, job->gws_base,
					    job->gws_size, job->oa_base,
					    job->oa_size);
	}

	if (ring->funcs->patch_cond_exec)
		amdgpu_ring_patch_cond_exec(ring, patch_offset);

	/* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
	if (ring->funcs->emit_switch_buffer) {
		amdgpu_ring_emit_switch_buffer(ring);
		amdgpu_ring_emit_switch_buffer(ring);
778
	}
779
	return 0;
780 781
}

A
Alex Deucher 已提交
782 783 784 785 786 787
/**
 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
 *
 * @vm: requested vm
 * @bo: requested buffer object
 *
788
 * Find @bo inside the requested vm.
A
Alex Deucher 已提交
789 790 791 792
 * Search inside the @bos vm list for the requested vm
 * Returns the found bo_va or NULL if none is found
 *
 * Object has to be reserved!
793 794 795
 *
 * Returns:
 * Found bo_va or NULL.
A
Alex Deucher 已提交
796 797 798 799 800 801
 */
struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
				       struct amdgpu_bo *bo)
{
	struct amdgpu_bo_va *bo_va;

802 803
	list_for_each_entry(bo_va, &bo->va, base.bo_list) {
		if (bo_va->base.vm == vm) {
A
Alex Deucher 已提交
804 805 806 807 808 809 810
			return bo_va;
		}
	}
	return NULL;
}

/**
811
 * amdgpu_vm_do_set_ptes - helper to call the right asic function
A
Alex Deucher 已提交
812
 *
813
 * @params: see amdgpu_pte_update_params definition
814
 * @bo: PD/PT to update
A
Alex Deucher 已提交
815 816 817 818 819 820 821 822 823
 * @pe: addr of the page entry
 * @addr: dst addr to write into pe
 * @count: number of page entries to update
 * @incr: increase next addr by incr bytes
 * @flags: hw access flags
 *
 * Traces the parameters and calls the right asic functions
 * to setup the page table using the DMA.
 */
824
static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params,
825
				  struct amdgpu_bo *bo,
826 827
				  uint64_t pe, uint64_t addr,
				  unsigned count, uint32_t incr,
828
				  uint64_t flags)
A
Alex Deucher 已提交
829
{
830
	pe += amdgpu_bo_gpu_offset(bo);
831
	trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);
A
Alex Deucher 已提交
832

833
	if (count < 3) {
834 835
		amdgpu_vm_write_pte(params->adev, params->ib, pe,
				    addr | flags, count, incr);
A
Alex Deucher 已提交
836 837

	} else {
838
		amdgpu_vm_set_pte_pde(params->adev, params->ib, pe, addr,
A
Alex Deucher 已提交
839 840 841 842
				      count, incr, flags);
	}
}

843 844 845 846
/**
 * amdgpu_vm_do_copy_ptes - copy the PTEs from the GART
 *
 * @params: see amdgpu_pte_update_params definition
847
 * @bo: PD/PT to update
848 849 850 851 852 853 854 855 856
 * @pe: addr of the page entry
 * @addr: dst addr to write into pe
 * @count: number of page entries to update
 * @incr: increase next addr by incr bytes
 * @flags: hw access flags
 *
 * Traces the parameters and calls the DMA function to copy the PTEs.
 */
static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params,
857
				   struct amdgpu_bo *bo,
858 859
				   uint64_t pe, uint64_t addr,
				   unsigned count, uint32_t incr,
860
				   uint64_t flags)
861
{
862
	uint64_t src = (params->src + (addr >> 12) * 8);
863

864
	pe += amdgpu_bo_gpu_offset(bo);
865 866 867
	trace_amdgpu_vm_copy_ptes(pe, src, count);

	amdgpu_vm_copy_pte(params->adev, params->ib, pe, src, count);
868 869
}

A
Alex Deucher 已提交
870
/**
871
 * amdgpu_vm_map_gart - Resolve gart mapping of addr
A
Alex Deucher 已提交
872
 *
873
 * @pages_addr: optional DMA address to use for lookup
A
Alex Deucher 已提交
874 875 876
 * @addr: the unmapped addr
 *
 * Look up the physical address of the page that the pte resolves
877 878 879 880
 * to.
 *
 * Returns:
 * The pointer for the page table entry.
A
Alex Deucher 已提交
881
 */
882
static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
A
Alex Deucher 已提交
883 884 885
{
	uint64_t result;

886 887
	/* page table offset */
	result = pages_addr[addr >> PAGE_SHIFT];
888

889 890
	/* in case cpu page size != gpu page size*/
	result |= addr & (~PAGE_MASK);
A
Alex Deucher 已提交
891

892
	result &= 0xFFFFFFFFFFFFF000ULL;
A
Alex Deucher 已提交
893 894 895 896

	return result;
}

897 898 899 900
/**
 * amdgpu_vm_cpu_set_ptes - helper to update page tables via CPU
 *
 * @params: see amdgpu_pte_update_params definition
901
 * @bo: PD/PT to update
902 903 904 905 906 907 908 909 910
 * @pe: kmap addr of the page entry
 * @addr: dst addr to write into pe
 * @count: number of page entries to update
 * @incr: increase next addr by incr bytes
 * @flags: hw access flags
 *
 * Write count number of PT/PD entries directly.
 */
static void amdgpu_vm_cpu_set_ptes(struct amdgpu_pte_update_params *params,
911
				   struct amdgpu_bo *bo,
912 913 914 915 916
				   uint64_t pe, uint64_t addr,
				   unsigned count, uint32_t incr,
				   uint64_t flags)
{
	unsigned int i;
917
	uint64_t value;
918

919 920
	pe += (unsigned long)amdgpu_bo_kptr(bo);

921 922
	trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);

923
	for (i = 0; i < count; i++) {
924 925 926
		value = params->pages_addr ?
			amdgpu_vm_map_gart(params->pages_addr, addr) :
			addr;
927 928
		amdgpu_gmc_set_pte_pde(params->adev, (void *)(uintptr_t)pe,
				       i, value, flags);
929 930 931 932
		addr += incr;
	}
}

933 934 935 936 937 938 939 940 941 942 943

/**
 * amdgpu_vm_wait_pd - Wait for PT BOs to be free.
 *
 * @adev: amdgpu_device pointer
 * @vm: related vm
 * @owner: fence owner
 *
 * Returns:
 * 0 on success, errno otherwise.
 */
944 945
static int amdgpu_vm_wait_pd(struct amdgpu_device *adev, struct amdgpu_vm *vm,
			     void *owner)
946 947 948 949 950
{
	struct amdgpu_sync sync;
	int r;

	amdgpu_sync_create(&sync);
951
	amdgpu_sync_resv(adev, &sync, vm->root.base.bo->tbo.resv, owner, false);
952 953 954 955 956 957
	r = amdgpu_sync_wait(&sync, true);
	amdgpu_sync_free(&sync);

	return r;
}

958
/*
959
 * amdgpu_vm_update_pde - update a single level in the hierarchy
960
 *
961
 * @param: parameters for the update
962
 * @vm: requested vm
963
 * @parent: parent directory
964
 * @entry: entry to update
965
 *
966
 * Makes sure the requested entry in parent is up to date.
967
 */
968 969 970 971
static void amdgpu_vm_update_pde(struct amdgpu_pte_update_params *params,
				 struct amdgpu_vm *vm,
				 struct amdgpu_vm_pt *parent,
				 struct amdgpu_vm_pt *entry)
A
Alex Deucher 已提交
972
{
973
	struct amdgpu_bo *bo = parent->base.bo, *pbo;
974 975
	uint64_t pde, pt, flags;
	unsigned level;
C
Chunming Zhou 已提交
976

977 978 979
	/* Don't update huge pages here */
	if (entry->huge)
		return;
A
Alex Deucher 已提交
980

981
	for (level = 0, pbo = bo->parent; pbo; ++level)
982 983
		pbo = pbo->parent;

984
	level += params->adev->vm_manager.root_level;
985
	pt = amdgpu_bo_gpu_offset(entry->base.bo);
986
	flags = AMDGPU_PTE_VALID;
987
	amdgpu_gmc_get_vm_pde(params->adev, level, &pt, &flags);
988 989 990 991
	pde = (entry - parent->entries) * 8;
	if (bo->shadow)
		params->func(params, bo->shadow, pde, pt, 1, 0, flags);
	params->func(params, bo, pde, pt, 1, 0, flags);
A
Alex Deucher 已提交
992 993
}

994 995 996
/*
 * amdgpu_vm_invalidate_level - mark all PD levels as invalid
 *
997 998
 * @adev: amdgpu_device pointer
 * @vm: related vm
999
 * @parent: parent PD
1000
 * @level: VMPT level
1001 1002 1003
 *
 * Mark all PD level as invalid after an error.
 */
1004 1005 1006 1007
static void amdgpu_vm_invalidate_level(struct amdgpu_device *adev,
				       struct amdgpu_vm *vm,
				       struct amdgpu_vm_pt *parent,
				       unsigned level)
1008
{
1009
	unsigned pt_idx, num_entries;
1010 1011 1012 1013 1014

	/*
	 * Recurse into the subdirectories. This recursion is harmless because
	 * we only have a maximum of 5 layers.
	 */
1015 1016
	num_entries = amdgpu_vm_num_entries(adev, level);
	for (pt_idx = 0; pt_idx < num_entries; ++pt_idx) {
1017 1018
		struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];

1019
		if (!entry->base.bo)
1020 1021
			continue;

1022 1023
		if (!entry->base.moved)
			list_move(&entry->base.vm_status, &vm->relocated);
1024
		amdgpu_vm_invalidate_level(adev, vm, entry, level + 1);
1025 1026 1027
	}
}

1028 1029 1030 1031 1032 1033 1034
/*
 * amdgpu_vm_update_directories - make sure that all directories are valid
 *
 * @adev: amdgpu_device pointer
 * @vm: requested vm
 *
 * Makes sure all directories are up to date.
1035 1036 1037
 *
 * Returns:
 * 0 for success, error for failure.
1038 1039 1040 1041
 */
int amdgpu_vm_update_directories(struct amdgpu_device *adev,
				 struct amdgpu_vm *vm)
{
1042 1043 1044
	struct amdgpu_pte_update_params params;
	struct amdgpu_job *job;
	unsigned ndw = 0;
1045
	int r = 0;
1046

1047 1048 1049 1050 1051 1052 1053 1054
	if (list_empty(&vm->relocated))
		return 0;

restart:
	memset(&params, 0, sizeof(params));
	params.adev = adev;

	if (vm->use_cpu_for_update) {
1055 1056 1057 1058 1059 1060 1061 1062
		struct amdgpu_vm_bo_base *bo_base;

		list_for_each_entry(bo_base, &vm->relocated, vm_status) {
			r = amdgpu_bo_kmap(bo_base->bo, NULL);
			if (unlikely(r))
				return r;
		}

1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077
		r = amdgpu_vm_wait_pd(adev, vm, AMDGPU_FENCE_OWNER_VM);
		if (unlikely(r))
			return r;

		params.func = amdgpu_vm_cpu_set_ptes;
	} else {
		ndw = 512 * 8;
		r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
		if (r)
			return r;

		params.ib = &job->ibs[0];
		params.func = amdgpu_vm_do_set_ptes;
	}

1078
	while (!list_empty(&vm->relocated)) {
1079 1080
		struct amdgpu_vm_bo_base *bo_base, *parent;
		struct amdgpu_vm_pt *pt, *entry;
1081 1082 1083 1084 1085
		struct amdgpu_bo *bo;

		bo_base = list_first_entry(&vm->relocated,
					   struct amdgpu_vm_bo_base,
					   vm_status);
1086
		bo_base->moved = false;
1087
		list_del_init(&bo_base->vm_status);
1088 1089

		bo = bo_base->bo->parent;
1090
		if (!bo)
1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102
			continue;

		parent = list_first_entry(&bo->va, struct amdgpu_vm_bo_base,
					  bo_list);
		pt = container_of(parent, struct amdgpu_vm_pt, base);
		entry = container_of(bo_base, struct amdgpu_vm_pt, base);

		amdgpu_vm_update_pde(&params, vm, pt, entry);

		if (!vm->use_cpu_for_update &&
		    (ndw - params.ib->length_dw) < 32)
			break;
1103
	}
1104

1105 1106 1107
	if (vm->use_cpu_for_update) {
		/* Flush HDP */
		mb();
1108
		amdgpu_asic_flush_hdp(adev, NULL);
1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122
	} else if (params.ib->length_dw == 0) {
		amdgpu_job_free(job);
	} else {
		struct amdgpu_bo *root = vm->root.base.bo;
		struct amdgpu_ring *ring;
		struct dma_fence *fence;

		ring = container_of(vm->entity.sched, struct amdgpu_ring,
				    sched);

		amdgpu_ring_pad_ib(ring, params.ib);
		amdgpu_sync_resv(adev, &job->sync, root->tbo.resv,
				 AMDGPU_FENCE_OWNER_VM, false);
		WARN_ON(params.ib->length_dw > ndw);
1123 1124
		r = amdgpu_job_submit(job, &vm->entity, AMDGPU_FENCE_OWNER_VM,
				      &fence);
1125 1126 1127 1128 1129 1130
		if (r)
			goto error;

		amdgpu_bo_fence(root, fence, true);
		dma_fence_put(vm->last_update);
		vm->last_update = fence;
1131 1132
	}

1133 1134 1135 1136 1137 1138
	if (!list_empty(&vm->relocated))
		goto restart;

	return 0;

error:
1139 1140
	amdgpu_vm_invalidate_level(adev, vm, &vm->root,
				   adev->vm_manager.root_level);
1141
	amdgpu_job_free(job);
1142
	return r;
1143 1144
}

1145
/**
1146
 * amdgpu_vm_find_entry - find the entry for an address
1147 1148 1149
 *
 * @p: see amdgpu_pte_update_params definition
 * @addr: virtual address in question
1150 1151
 * @entry: resulting entry or NULL
 * @parent: parent entry
1152
 *
1153
 * Find the vm_pt entry and it's parent for the given address.
1154
 */
1155 1156 1157
void amdgpu_vm_get_entry(struct amdgpu_pte_update_params *p, uint64_t addr,
			 struct amdgpu_vm_pt **entry,
			 struct amdgpu_vm_pt **parent)
1158
{
1159
	unsigned level = p->adev->vm_manager.root_level;
1160

1161 1162 1163
	*parent = NULL;
	*entry = &p->vm->root;
	while ((*entry)->entries) {
1164
		unsigned shift = amdgpu_vm_level_shift(p->adev, level++);
1165

1166
		*parent = *entry;
1167 1168
		*entry = &(*entry)->entries[addr >> shift];
		addr &= (1ULL << shift) - 1;
1169 1170
	}

1171
	if (level != AMDGPU_VM_PTB)
1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186
		*entry = NULL;
}

/**
 * amdgpu_vm_handle_huge_pages - handle updating the PD with huge pages
 *
 * @p: see amdgpu_pte_update_params definition
 * @entry: vm_pt entry to check
 * @parent: parent entry
 * @nptes: number of PTEs updated with this operation
 * @dst: destination address where the PTEs should point to
 * @flags: access flags fro the PTEs
 *
 * Check if we can update the PD with a huge page.
 */
1187 1188 1189 1190 1191
static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p,
					struct amdgpu_vm_pt *entry,
					struct amdgpu_vm_pt *parent,
					unsigned nptes, uint64_t dst,
					uint64_t flags)
1192
{
1193
	uint64_t pde;
1194 1195

	/* In the case of a mixed PT the PDE must point to it*/
1196 1197
	if (p->adev->asic_type >= CHIP_VEGA10 && !p->src &&
	    nptes == AMDGPU_VM_PTE_COUNT(p->adev)) {
1198
		/* Set the huge page flag to stop scanning at this PDE */
1199 1200 1201
		flags |= AMDGPU_PDE_PTE;
	}

1202 1203 1204 1205 1206 1207
	if (!(flags & AMDGPU_PDE_PTE)) {
		if (entry->huge) {
			/* Add the entry to the relocated list to update it. */
			entry->huge = false;
			list_move(&entry->base.vm_status, &p->vm->relocated);
		}
1208
		return;
1209
	}
1210

1211
	entry->huge = true;
1212
	amdgpu_gmc_get_vm_pde(p->adev, AMDGPU_VM_PDB0, &dst, &flags);
1213

1214 1215 1216 1217
	pde = (entry - parent->entries) * 8;
	if (parent->base.bo->shadow)
		p->func(p, parent->base.bo->shadow, pde, dst, 1, 0, flags);
	p->func(p, parent->base.bo, pde, dst, 1, 0, flags);
1218 1219
}

A
Alex Deucher 已提交
1220 1221 1222
/**
 * amdgpu_vm_update_ptes - make sure that page tables are valid
 *
1223
 * @params: see amdgpu_pte_update_params definition
A
Alex Deucher 已提交
1224 1225
 * @start: start of GPU address range
 * @end: end of GPU address range
1226
 * @dst: destination address to map to, the next dst inside the function
A
Alex Deucher 已提交
1227 1228
 * @flags: mapping flags
 *
1229
 * Update the page tables in the range @start - @end.
1230 1231 1232
 *
 * Returns:
 * 0 for success, -EINVAL for failure.
A
Alex Deucher 已提交
1233
 */
1234
static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
1235
				  uint64_t start, uint64_t end,
1236
				  uint64_t dst, uint64_t flags)
A
Alex Deucher 已提交
1237
{
1238 1239
	struct amdgpu_device *adev = params->adev;
	const uint64_t mask = AMDGPU_VM_PTE_COUNT(adev) - 1;
1240

1241
	uint64_t addr, pe_start;
1242
	struct amdgpu_bo *pt;
1243
	unsigned nptes;
A
Alex Deucher 已提交
1244 1245

	/* walk over the address space and update the page tables */
1246 1247 1248 1249 1250 1251 1252
	for (addr = start; addr < end; addr += nptes,
	     dst += nptes * AMDGPU_GPU_PAGE_SIZE) {
		struct amdgpu_vm_pt *entry, *parent;

		amdgpu_vm_get_entry(params, addr, &entry, &parent);
		if (!entry)
			return -ENOENT;
1253

A
Alex Deucher 已提交
1254 1255 1256
		if ((addr & ~mask) == (end & ~mask))
			nptes = end - addr;
		else
1257
			nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask);
A
Alex Deucher 已提交
1258

1259 1260
		amdgpu_vm_handle_huge_pages(params, entry, parent,
					    nptes, dst, flags);
1261
		/* We don't need to update PTEs for huge pages */
1262
		if (entry->huge)
1263 1264
			continue;

1265
		pt = entry->base.bo;
1266 1267 1268 1269 1270
		pe_start = (addr & mask) * 8;
		if (pt->shadow)
			params->func(params, pt->shadow, pe_start, dst, nptes,
				     AMDGPU_GPU_PAGE_SIZE, flags);
		params->func(params, pt, pe_start, dst, nptes,
1271
			     AMDGPU_GPU_PAGE_SIZE, flags);
A
Alex Deucher 已提交
1272 1273
	}

1274
	return 0;
1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285
}

/*
 * amdgpu_vm_frag_ptes - add fragment information to PTEs
 *
 * @params: see amdgpu_pte_update_params definition
 * @vm: requested vm
 * @start: first PTE to handle
 * @end: last PTE to handle
 * @dst: addr those PTEs should point to
 * @flags: hw mapping flags
1286 1287 1288
 *
 * Returns:
 * 0 for success, -EINVAL for failure.
1289
 */
1290
static int amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params	*params,
1291
				uint64_t start, uint64_t end,
1292
				uint64_t dst, uint64_t flags)
1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311
{
	/**
	 * The MC L1 TLB supports variable sized pages, based on a fragment
	 * field in the PTE. When this field is set to a non-zero value, page
	 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
	 * flags are considered valid for all PTEs within the fragment range
	 * and corresponding mappings are assumed to be physically contiguous.
	 *
	 * The L1 TLB can store a single PTE for the whole fragment,
	 * significantly increasing the space available for translation
	 * caching. This leads to large improvements in throughput when the
	 * TLB is under pressure.
	 *
	 * The L2 TLB distributes small and large fragments into two
	 * asymmetric partitions. The large fragment cache is significantly
	 * larger. Thus, we try to use large fragments wherever possible.
	 * Userspace can support this by aligning virtual base address and
	 * allocation size to the fragment size.
	 */
1312 1313
	unsigned max_frag = params->adev->vm_manager.fragment_size;
	int r;
1314 1315

	/* system pages are non continuously */
1316
	if (params->src || !(flags & AMDGPU_PTE_VALID))
1317
		return amdgpu_vm_update_ptes(params, start, end, dst, flags);
1318

1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335
	while (start != end) {
		uint64_t frag_flags, frag_end;
		unsigned frag;

		/* This intentionally wraps around if no bit is set */
		frag = min((unsigned)ffs(start) - 1,
			   (unsigned)fls64(end - start) - 1);
		if (frag >= max_frag) {
			frag_flags = AMDGPU_PTE_FRAG(max_frag);
			frag_end = end & ~((1ULL << max_frag) - 1);
		} else {
			frag_flags = AMDGPU_PTE_FRAG(frag);
			frag_end = start + (1 << frag);
		}

		r = amdgpu_vm_update_ptes(params, start, frag_end, dst,
					  flags | frag_flags);
1336 1337
		if (r)
			return r;
1338

1339 1340
		dst += (frag_end - start) * AMDGPU_GPU_PAGE_SIZE;
		start = frag_end;
1341
	}
1342 1343

	return 0;
A
Alex Deucher 已提交
1344 1345 1346 1347 1348 1349
}

/**
 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
 *
 * @adev: amdgpu_device pointer
1350
 * @exclusive: fence we need to sync to
1351
 * @pages_addr: DMA addresses to use for mapping
A
Alex Deucher 已提交
1352
 * @vm: requested vm
1353 1354 1355
 * @start: start of mapped range
 * @last: last mapped entry
 * @flags: flags for the entries
A
Alex Deucher 已提交
1356 1357 1358
 * @addr: addr to set the area to
 * @fence: optional resulting fence
 *
1359
 * Fill in the page table entries between @start and @last.
1360 1361 1362
 *
 * Returns:
 * 0 for success, -EINVAL for failure.
A
Alex Deucher 已提交
1363 1364
 */
static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
1365
				       struct dma_fence *exclusive,
1366
				       dma_addr_t *pages_addr,
A
Alex Deucher 已提交
1367
				       struct amdgpu_vm *vm,
1368
				       uint64_t start, uint64_t last,
1369
				       uint64_t flags, uint64_t addr,
1370
				       struct dma_fence **fence)
A
Alex Deucher 已提交
1371
{
1372
	struct amdgpu_ring *ring;
1373
	void *owner = AMDGPU_FENCE_OWNER_VM;
A
Alex Deucher 已提交
1374
	unsigned nptes, ncmds, ndw;
1375
	struct amdgpu_job *job;
1376
	struct amdgpu_pte_update_params params;
1377
	struct dma_fence *f = NULL;
A
Alex Deucher 已提交
1378 1379
	int r;

1380 1381
	memset(&params, 0, sizeof(params));
	params.adev = adev;
1382
	params.vm = vm;
1383

1384 1385 1386 1387
	/* sync to everything on unmapping */
	if (!(flags & AMDGPU_PTE_VALID))
		owner = AMDGPU_FENCE_OWNER_UNDEFINED;

1388 1389 1390 1391 1392 1393 1394 1395
	if (vm->use_cpu_for_update) {
		/* params.src is used as flag to indicate system Memory */
		if (pages_addr)
			params.src = ~0;

		/* Wait for PT BOs to be free. PTs share the same resv. object
		 * as the root PD BO
		 */
1396
		r = amdgpu_vm_wait_pd(adev, vm, owner);
1397 1398 1399 1400 1401 1402 1403 1404 1405
		if (unlikely(r))
			return r;

		params.func = amdgpu_vm_cpu_set_ptes;
		params.pages_addr = pages_addr;
		return amdgpu_vm_frag_ptes(&params, start, last + 1,
					   addr, flags);
	}

1406
	ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
1407

1408
	nptes = last - start + 1;
A
Alex Deucher 已提交
1409 1410

	/*
1411
	 * reserve space for two commands every (1 << BLOCK_SIZE)
A
Alex Deucher 已提交
1412
	 *  entries or 2k dwords (whatever is smaller)
1413 1414
         *
         * The second command is for the shadow pagetables.
A
Alex Deucher 已提交
1415
	 */
1416 1417 1418 1419
	if (vm->root.base.bo->shadow)
		ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1) * 2;
	else
		ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1);
A
Alex Deucher 已提交
1420 1421 1422 1423

	/* padding, etc. */
	ndw = 64;

1424
	if (pages_addr) {
1425
		/* copy commands needed */
1426
		ndw += ncmds * adev->vm_manager.vm_pte_funcs->copy_pte_num_dw;
A
Alex Deucher 已提交
1427

1428
		/* and also PTEs */
A
Alex Deucher 已提交
1429 1430
		ndw += nptes * 2;

1431 1432
		params.func = amdgpu_vm_do_copy_ptes;

A
Alex Deucher 已提交
1433 1434
	} else {
		/* set page commands needed */
1435
		ndw += ncmds * 10;
A
Alex Deucher 已提交
1436

1437
		/* extra commands for begin/end fragments */
1438 1439 1440 1441
		if (vm->root.base.bo->shadow)
		        ndw += 2 * 10 * adev->vm_manager.fragment_size * 2;
		else
		        ndw += 2 * 10 * adev->vm_manager.fragment_size;
1442 1443

		params.func = amdgpu_vm_do_set_ptes;
A
Alex Deucher 已提交
1444 1445
	}

1446 1447
	r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
	if (r)
A
Alex Deucher 已提交
1448
		return r;
1449

1450
	params.ib = &job->ibs[0];
C
Chunming Zhou 已提交
1451

1452
	if (pages_addr) {
1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465
		uint64_t *pte;
		unsigned i;

		/* Put the PTEs at the end of the IB. */
		i = ndw - nptes * 2;
		pte= (uint64_t *)&(job->ibs->ptr[i]);
		params.src = job->ibs->gpu_addr + i * 4;

		for (i = 0; i < nptes; ++i) {
			pte[i] = amdgpu_vm_map_gart(pages_addr, addr + i *
						    AMDGPU_GPU_PAGE_SIZE);
			pte[i] |= flags;
		}
1466
		addr = 0;
1467 1468
	}

1469
	r = amdgpu_sync_fence(adev, &job->sync, exclusive, false);
1470 1471 1472
	if (r)
		goto error_free;

1473
	r = amdgpu_sync_resv(adev, &job->sync, vm->root.base.bo->tbo.resv,
1474
			     owner, false);
1475 1476
	if (r)
		goto error_free;
A
Alex Deucher 已提交
1477

1478
	r = reservation_object_reserve_shared(vm->root.base.bo->tbo.resv);
1479 1480 1481
	if (r)
		goto error_free;

1482 1483 1484
	r = amdgpu_vm_frag_ptes(&params, start, last + 1, addr, flags);
	if (r)
		goto error_free;
A
Alex Deucher 已提交
1485

1486 1487
	amdgpu_ring_pad_ib(ring, params.ib);
	WARN_ON(params.ib->length_dw > ndw);
1488
	r = amdgpu_job_submit(job, &vm->entity, AMDGPU_FENCE_OWNER_VM, &f);
1489 1490
	if (r)
		goto error_free;
A
Alex Deucher 已提交
1491

1492
	amdgpu_bo_fence(vm->root.base.bo, f, true);
1493 1494
	dma_fence_put(*fence);
	*fence = f;
A
Alex Deucher 已提交
1495
	return 0;
C
Chunming Zhou 已提交
1496 1497

error_free:
1498
	amdgpu_job_free(job);
1499
	return r;
A
Alex Deucher 已提交
1500 1501
}

1502 1503 1504 1505
/**
 * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks
 *
 * @adev: amdgpu_device pointer
1506
 * @exclusive: fence we need to sync to
1507
 * @pages_addr: DMA addresses to use for mapping
1508 1509
 * @vm: requested vm
 * @mapping: mapped range and flags to use for the update
1510
 * @flags: HW flags for the mapping
1511
 * @nodes: array of drm_mm_nodes with the MC addresses
1512 1513 1514 1515
 * @fence: optional resulting fence
 *
 * Split the mapping into smaller chunks so that each update fits
 * into a SDMA IB.
1516 1517 1518
 *
 * Returns:
 * 0 for success, -EINVAL for failure.
1519 1520
 */
static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
1521
				      struct dma_fence *exclusive,
1522
				      dma_addr_t *pages_addr,
1523 1524
				      struct amdgpu_vm *vm,
				      struct amdgpu_bo_va_mapping *mapping,
1525
				      uint64_t flags,
1526
				      struct drm_mm_node *nodes,
1527
				      struct dma_fence **fence)
1528
{
1529
	unsigned min_linear_pages = 1 << adev->vm_manager.fragment_size;
1530
	uint64_t pfn, start = mapping->start;
1531 1532 1533 1534 1535 1536 1537 1538 1539 1540
	int r;

	/* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
	 * but in case of something, we filter the flags in first place
	 */
	if (!(mapping->flags & AMDGPU_PTE_READABLE))
		flags &= ~AMDGPU_PTE_READABLE;
	if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
		flags &= ~AMDGPU_PTE_WRITEABLE;

1541 1542 1543
	flags &= ~AMDGPU_PTE_EXECUTABLE;
	flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;

1544 1545 1546
	flags &= ~AMDGPU_PTE_MTYPE_MASK;
	flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK);

1547 1548 1549 1550 1551 1552
	if ((mapping->flags & AMDGPU_PTE_PRT) &&
	    (adev->asic_type >= CHIP_VEGA10)) {
		flags |= AMDGPU_PTE_PRT;
		flags &= ~AMDGPU_PTE_VALID;
	}

1553 1554
	trace_amdgpu_vm_bo_update(mapping);

1555 1556 1557 1558 1559 1560
	pfn = mapping->offset >> PAGE_SHIFT;
	if (nodes) {
		while (pfn >= nodes->size) {
			pfn -= nodes->size;
			++nodes;
		}
1561
	}
1562

1563
	do {
1564
		dma_addr_t *dma_addr = NULL;
1565 1566
		uint64_t max_entries;
		uint64_t addr, last;
1567

1568 1569 1570
		if (nodes) {
			addr = nodes->start << PAGE_SHIFT;
			max_entries = (nodes->size - pfn) *
1571
				AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1572 1573 1574 1575
		} else {
			addr = 0;
			max_entries = S64_MAX;
		}
1576

1577
		if (pages_addr) {
1578 1579
			uint64_t count;

1580
			max_entries = min(max_entries, 16ull * 1024ull);
1581
			for (count = 1;
1582
			     count < max_entries / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1583
			     ++count) {
1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595
				uint64_t idx = pfn + count;

				if (pages_addr[idx] !=
				    (pages_addr[idx - 1] + PAGE_SIZE))
					break;
			}

			if (count < min_linear_pages) {
				addr = pfn << PAGE_SHIFT;
				dma_addr = pages_addr;
			} else {
				addr = pages_addr[pfn];
1596
				max_entries = count * AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1597 1598
			}

1599 1600
		} else if (flags & AMDGPU_PTE_VALID) {
			addr += adev->vm_manager.vram_base_offset;
1601
			addr += pfn << PAGE_SHIFT;
1602 1603
		}

1604
		last = min((uint64_t)mapping->last, start + max_entries - 1);
1605
		r = amdgpu_vm_bo_update_mapping(adev, exclusive, dma_addr, vm,
1606 1607 1608 1609 1610
						start, last, flags, addr,
						fence);
		if (r)
			return r;

1611
		pfn += (last - start + 1) / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1612 1613 1614 1615
		if (nodes && nodes->size == pfn) {
			pfn = 0;
			++nodes;
		}
1616
		start = last + 1;
1617

1618
	} while (unlikely(start != mapping->last + 1));
1619 1620 1621 1622

	return 0;
}

A
Alex Deucher 已提交
1623 1624 1625 1626 1627
/**
 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
 *
 * @adev: amdgpu_device pointer
 * @bo_va: requested BO and VM object
1628
 * @clear: if true clear the entries
A
Alex Deucher 已提交
1629 1630
 *
 * Fill in the page table entries for @bo_va.
1631 1632 1633
 *
 * Returns:
 * 0 for success, -EINVAL for failure.
A
Alex Deucher 已提交
1634 1635 1636
 */
int amdgpu_vm_bo_update(struct amdgpu_device *adev,
			struct amdgpu_bo_va *bo_va,
1637
			bool clear)
A
Alex Deucher 已提交
1638
{
1639 1640
	struct amdgpu_bo *bo = bo_va->base.bo;
	struct amdgpu_vm *vm = bo_va->base.vm;
A
Alex Deucher 已提交
1641
	struct amdgpu_bo_va_mapping *mapping;
1642
	dma_addr_t *pages_addr = NULL;
1643
	struct ttm_mem_reg *mem;
1644
	struct drm_mm_node *nodes;
1645
	struct dma_fence *exclusive, **last_update;
1646
	uint64_t flags;
A
Alex Deucher 已提交
1647 1648
	int r;

1649
	if (clear || !bo) {
1650
		mem = NULL;
1651
		nodes = NULL;
1652 1653
		exclusive = NULL;
	} else {
1654 1655
		struct ttm_dma_tt *ttm;

1656
		mem = &bo->tbo.mem;
1657 1658
		nodes = mem->mm_node;
		if (mem->mem_type == TTM_PL_TT) {
1659
			ttm = container_of(bo->tbo.ttm, struct ttm_dma_tt, ttm);
1660
			pages_addr = ttm->dma_address;
1661
		}
1662
		exclusive = reservation_object_get_excl(bo->tbo.resv);
A
Alex Deucher 已提交
1663 1664
	}

1665
	if (bo)
1666
		flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
1667
	else
1668
		flags = 0x0;
A
Alex Deucher 已提交
1669

1670 1671 1672 1673 1674
	if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv))
		last_update = &vm->last_update;
	else
		last_update = &bo_va->last_pt_update;

1675 1676
	if (!clear && bo_va->base.moved) {
		bo_va->base.moved = false;
1677
		list_splice_init(&bo_va->valids, &bo_va->invalids);
1678

1679 1680
	} else if (bo_va->cleared != clear) {
		list_splice_init(&bo_va->valids, &bo_va->invalids);
1681
	}
1682 1683

	list_for_each_entry(mapping, &bo_va->invalids, list) {
1684
		r = amdgpu_vm_bo_split_mapping(adev, exclusive, pages_addr, vm,
1685
					       mapping, flags, nodes,
1686
					       last_update);
A
Alex Deucher 已提交
1687 1688 1689 1690
		if (r)
			return r;
	}

1691 1692 1693
	if (vm->use_cpu_for_update) {
		/* Flush HDP */
		mb();
1694
		amdgpu_asic_flush_hdp(adev, NULL);
1695 1696
	}

1697
	spin_lock(&vm->moved_lock);
1698
	list_del_init(&bo_va->base.vm_status);
1699
	spin_unlock(&vm->moved_lock);
1700

1701 1702 1703 1704
	/* If the BO is not in its preferred location add it back to
	 * the evicted list so that it gets validated again on the
	 * next command submission.
	 */
1705 1706 1707 1708 1709 1710 1711 1712
	if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv) {
		uint32_t mem_type = bo->tbo.mem.mem_type;

		if (!(bo->preferred_domains & amdgpu_mem_type_to_domain(mem_type)))
			list_add_tail(&bo_va->base.vm_status, &vm->evicted);
		else
			list_add(&bo_va->base.vm_status, &vm->idle);
	}
A
Alex Deucher 已提交
1713

1714 1715 1716 1717 1718 1719
	list_splice_init(&bo_va->invalids, &bo_va->valids);
	bo_va->cleared = clear;

	if (trace_amdgpu_vm_bo_mapping_enabled()) {
		list_for_each_entry(mapping, &bo_va->valids, list)
			trace_amdgpu_vm_bo_mapping(mapping);
1720 1721
	}

A
Alex Deucher 已提交
1722 1723 1724
	return 0;
}

1725 1726
/**
 * amdgpu_vm_update_prt_state - update the global PRT state
1727 1728
 *
 * @adev: amdgpu_device pointer
1729 1730 1731 1732 1733 1734 1735
 */
static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
{
	unsigned long flags;
	bool enable;

	spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
1736
	enable = !!atomic_read(&adev->vm_manager.num_prt_users);
1737
	adev->gmc.gmc_funcs->set_prt(adev, enable);
1738 1739 1740
	spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
}

1741
/**
1742
 * amdgpu_vm_prt_get - add a PRT user
1743 1744
 *
 * @adev: amdgpu_device pointer
1745 1746 1747
 */
static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
{
1748
	if (!adev->gmc.gmc_funcs->set_prt)
1749 1750
		return;

1751 1752 1753 1754
	if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
		amdgpu_vm_update_prt_state(adev);
}

1755 1756
/**
 * amdgpu_vm_prt_put - drop a PRT user
1757 1758
 *
 * @adev: amdgpu_device pointer
1759 1760 1761
 */
static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
{
1762
	if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
1763 1764 1765
		amdgpu_vm_update_prt_state(adev);
}

1766
/**
1767
 * amdgpu_vm_prt_cb - callback for updating the PRT status
1768 1769
 *
 * @fence: fence for the callback
1770
 * @_cb: the callback function
1771 1772 1773 1774 1775
 */
static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
{
	struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);

1776
	amdgpu_vm_prt_put(cb->adev);
1777 1778 1779
	kfree(cb);
}

1780 1781
/**
 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
1782 1783 1784
 *
 * @adev: amdgpu_device pointer
 * @fence: fence for the callback
1785 1786 1787 1788
 */
static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
				 struct dma_fence *fence)
{
1789
	struct amdgpu_prt_cb *cb;
1790

1791
	if (!adev->gmc.gmc_funcs->set_prt)
1792 1793 1794
		return;

	cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
1795 1796 1797 1798 1799
	if (!cb) {
		/* Last resort when we are OOM */
		if (fence)
			dma_fence_wait(fence, false);

1800
		amdgpu_vm_prt_put(adev);
1801 1802 1803 1804 1805 1806 1807 1808
	} else {
		cb->adev = adev;
		if (!fence || dma_fence_add_callback(fence, &cb->cb,
						     amdgpu_vm_prt_cb))
			amdgpu_vm_prt_cb(fence, &cb->cb);
	}
}

1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823
/**
 * amdgpu_vm_free_mapping - free a mapping
 *
 * @adev: amdgpu_device pointer
 * @vm: requested vm
 * @mapping: mapping to be freed
 * @fence: fence of the unmap operation
 *
 * Free a mapping and make sure we decrease the PRT usage count if applicable.
 */
static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
				   struct amdgpu_vm *vm,
				   struct amdgpu_bo_va_mapping *mapping,
				   struct dma_fence *fence)
{
1824 1825 1826 1827
	if (mapping->flags & AMDGPU_PTE_PRT)
		amdgpu_vm_add_prt_cb(adev, fence);
	kfree(mapping);
}
1828

1829 1830 1831 1832 1833 1834 1835 1836 1837 1838
/**
 * amdgpu_vm_prt_fini - finish all prt mappings
 *
 * @adev: amdgpu_device pointer
 * @vm: requested vm
 *
 * Register a cleanup callback to disable PRT support after VM dies.
 */
static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
{
1839
	struct reservation_object *resv = vm->root.base.bo->tbo.resv;
1840 1841 1842
	struct dma_fence *excl, **shared;
	unsigned i, shared_count;
	int r;
1843

1844 1845 1846 1847 1848 1849 1850 1851 1852
	r = reservation_object_get_fences_rcu(resv, &excl,
					      &shared_count, &shared);
	if (r) {
		/* Not enough memory to grab the fence list, as last resort
		 * block for all the fences to complete.
		 */
		reservation_object_wait_timeout_rcu(resv, true, false,
						    MAX_SCHEDULE_TIMEOUT);
		return;
1853
	}
1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864

	/* Add a callback for each fence in the reservation object */
	amdgpu_vm_prt_get(adev);
	amdgpu_vm_add_prt_cb(adev, excl);

	for (i = 0; i < shared_count; ++i) {
		amdgpu_vm_prt_get(adev);
		amdgpu_vm_add_prt_cb(adev, shared[i]);
	}

	kfree(shared);
1865 1866
}

A
Alex Deucher 已提交
1867 1868 1869 1870 1871
/**
 * amdgpu_vm_clear_freed - clear freed BOs in the PT
 *
 * @adev: amdgpu_device pointer
 * @vm: requested vm
1872 1873
 * @fence: optional resulting fence (unchanged if no work needed to be done
 * or if an error occurred)
A
Alex Deucher 已提交
1874 1875 1876
 *
 * Make sure all freed BOs are cleared in the PT.
 * PTs have to be reserved and mutex must be locked!
1877 1878 1879 1880
 *
 * Returns:
 * 0 for success.
 *
A
Alex Deucher 已提交
1881 1882
 */
int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
1883 1884
			  struct amdgpu_vm *vm,
			  struct dma_fence **fence)
A
Alex Deucher 已提交
1885 1886
{
	struct amdgpu_bo_va_mapping *mapping;
1887
	uint64_t init_pte_value = 0;
1888
	struct dma_fence *f = NULL;
A
Alex Deucher 已提交
1889 1890 1891 1892 1893 1894
	int r;

	while (!list_empty(&vm->freed)) {
		mapping = list_first_entry(&vm->freed,
			struct amdgpu_bo_va_mapping, list);
		list_del(&mapping->list);
1895

1896
		if (vm->pte_support_ats && mapping->start < AMDGPU_VA_HOLE_START)
1897
			init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
Y
Yong Zhao 已提交
1898

1899
		r = amdgpu_vm_bo_update_mapping(adev, NULL, NULL, vm,
1900
						mapping->start, mapping->last,
Y
Yong Zhao 已提交
1901
						init_pte_value, 0, &f);
1902
		amdgpu_vm_free_mapping(adev, vm, mapping, f);
1903
		if (r) {
1904
			dma_fence_put(f);
A
Alex Deucher 已提交
1905
			return r;
1906
		}
1907
	}
A
Alex Deucher 已提交
1908

1909 1910 1911 1912 1913
	if (fence && f) {
		dma_fence_put(*fence);
		*fence = f;
	} else {
		dma_fence_put(f);
A
Alex Deucher 已提交
1914
	}
1915

A
Alex Deucher 已提交
1916 1917 1918 1919 1920
	return 0;

}

/**
1921
 * amdgpu_vm_handle_moved - handle moved BOs in the PT
A
Alex Deucher 已提交
1922 1923 1924 1925
 *
 * @adev: amdgpu_device pointer
 * @vm: requested vm
 *
1926
 * Make sure all BOs which are moved are updated in the PTs.
1927 1928 1929
 *
 * Returns:
 * 0 for success.
A
Alex Deucher 已提交
1930
 *
1931
 * PTs have to be reserved!
A
Alex Deucher 已提交
1932
 */
1933
int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
1934
			   struct amdgpu_vm *vm)
A
Alex Deucher 已提交
1935
{
1936 1937
	struct amdgpu_bo_va *bo_va, *tmp;
	struct list_head moved;
1938
	bool clear;
1939
	int r;
A
Alex Deucher 已提交
1940

1941
	INIT_LIST_HEAD(&moved);
1942
	spin_lock(&vm->moved_lock);
1943 1944
	list_splice_init(&vm->moved, &moved);
	spin_unlock(&vm->moved_lock);
1945

1946 1947
	list_for_each_entry_safe(bo_va, tmp, &moved, base.vm_status) {
		struct reservation_object *resv = bo_va->base.bo->tbo.resv;
1948

1949
		/* Per VM BOs never need to bo cleared in the page tables */
1950 1951 1952
		if (resv == vm->root.base.bo->tbo.resv)
			clear = false;
		/* Try to reserve the BO to avoid clearing its ptes */
1953
		else if (!amdgpu_vm_debug && reservation_object_trylock(resv))
1954 1955 1956 1957
			clear = false;
		/* Somebody else is using the BO right now */
		else
			clear = true;
1958 1959

		r = amdgpu_vm_bo_update(adev, bo_va, clear);
1960 1961 1962 1963
		if (r) {
			spin_lock(&vm->moved_lock);
			list_splice(&moved, &vm->moved);
			spin_unlock(&vm->moved_lock);
A
Alex Deucher 已提交
1964
			return r;
1965
		}
A
Alex Deucher 已提交
1966

1967 1968 1969
		if (!clear && resv != vm->root.base.bo->tbo.resv)
			reservation_object_unlock(resv);

A
Alex Deucher 已提交
1970 1971
	}

1972
	return 0;
A
Alex Deucher 已提交
1973 1974 1975 1976 1977 1978 1979 1980 1981
}

/**
 * amdgpu_vm_bo_add - add a bo to a specific vm
 *
 * @adev: amdgpu_device pointer
 * @vm: requested vm
 * @bo: amdgpu buffer object
 *
1982
 * Add @bo into the requested vm.
A
Alex Deucher 已提交
1983
 * Add @bo to the list of bos associated with the vm
1984 1985 1986
 *
 * Returns:
 * Newly added bo_va or NULL for failure
A
Alex Deucher 已提交
1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999
 *
 * Object has to be reserved!
 */
struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
				      struct amdgpu_vm *vm,
				      struct amdgpu_bo *bo)
{
	struct amdgpu_bo_va *bo_va;

	bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
	if (bo_va == NULL) {
		return NULL;
	}
2000
	amdgpu_vm_bo_base_init(&bo_va->base, vm, bo);
2001

A
Alex Deucher 已提交
2002
	bo_va->ref_count = 1;
2003 2004
	INIT_LIST_HEAD(&bo_va->valids);
	INIT_LIST_HEAD(&bo_va->invalids);
2005

A
Alex Deucher 已提交
2006 2007 2008
	return bo_va;
}

2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025

/**
 * amdgpu_vm_bo_insert_mapping - insert a new mapping
 *
 * @adev: amdgpu_device pointer
 * @bo_va: bo_va to store the address
 * @mapping: the mapping to insert
 *
 * Insert a new mapping into all structures.
 */
static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
				    struct amdgpu_bo_va *bo_va,
				    struct amdgpu_bo_va_mapping *mapping)
{
	struct amdgpu_vm *vm = bo_va->base.vm;
	struct amdgpu_bo *bo = bo_va->base.bo;

2026
	mapping->bo_va = bo_va;
2027 2028 2029 2030 2031 2032
	list_add(&mapping->list, &bo_va->invalids);
	amdgpu_vm_it_insert(mapping, &vm->va);

	if (mapping->flags & AMDGPU_PTE_PRT)
		amdgpu_vm_prt_get(adev);

2033 2034
	if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv &&
	    !bo_va->base.moved) {
2035
		spin_lock(&vm->moved_lock);
2036
		list_move(&bo_va->base.vm_status, &vm->moved);
2037
		spin_unlock(&vm->moved_lock);
2038 2039 2040 2041
	}
	trace_amdgpu_vm_bo_map(bo_va, mapping);
}

A
Alex Deucher 已提交
2042 2043 2044 2045 2046 2047 2048
/**
 * amdgpu_vm_bo_map - map bo inside a vm
 *
 * @adev: amdgpu_device pointer
 * @bo_va: bo_va to store the address
 * @saddr: where to map the BO
 * @offset: requested offset in the BO
2049
 * @size: BO size in bytes
A
Alex Deucher 已提交
2050 2051 2052
 * @flags: attributes of pages (read/write/valid/etc.)
 *
 * Add a mapping of the BO at the specefied addr into the VM.
2053 2054 2055
 *
 * Returns:
 * 0 for success, error for failure.
A
Alex Deucher 已提交
2056
 *
2057
 * Object has to be reserved and unreserved outside!
A
Alex Deucher 已提交
2058 2059 2060 2061
 */
int amdgpu_vm_bo_map(struct amdgpu_device *adev,
		     struct amdgpu_bo_va *bo_va,
		     uint64_t saddr, uint64_t offset,
2062
		     uint64_t size, uint64_t flags)
A
Alex Deucher 已提交
2063
{
2064
	struct amdgpu_bo_va_mapping *mapping, *tmp;
2065 2066
	struct amdgpu_bo *bo = bo_va->base.bo;
	struct amdgpu_vm *vm = bo_va->base.vm;
A
Alex Deucher 已提交
2067 2068
	uint64_t eaddr;

2069 2070
	/* validate the parameters */
	if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
2071
	    size == 0 || size & AMDGPU_GPU_PAGE_MASK)
2072 2073
		return -EINVAL;

A
Alex Deucher 已提交
2074
	/* make sure object fit at this offset */
2075
	eaddr = saddr + size - 1;
2076
	if (saddr >= eaddr ||
2077
	    (bo && offset + size > amdgpu_bo_size(bo)))
A
Alex Deucher 已提交
2078 2079 2080 2081 2082
		return -EINVAL;

	saddr /= AMDGPU_GPU_PAGE_SIZE;
	eaddr /= AMDGPU_GPU_PAGE_SIZE;

2083 2084
	tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
	if (tmp) {
A
Alex Deucher 已提交
2085 2086
		/* bo and tmp overlap, invalid addr */
		dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
2087
			"0x%010Lx-0x%010Lx\n", bo, saddr, eaddr,
2088
			tmp->start, tmp->last + 1);
2089
		return -EINVAL;
A
Alex Deucher 已提交
2090 2091 2092
	}

	mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2093 2094
	if (!mapping)
		return -ENOMEM;
A
Alex Deucher 已提交
2095

2096 2097
	mapping->start = saddr;
	mapping->last = eaddr;
A
Alex Deucher 已提交
2098 2099 2100
	mapping->offset = offset;
	mapping->flags = flags;

2101
	amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112

	return 0;
}

/**
 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
 *
 * @adev: amdgpu_device pointer
 * @bo_va: bo_va to store the address
 * @saddr: where to map the BO
 * @offset: requested offset in the BO
2113
 * @size: BO size in bytes
2114 2115 2116 2117
 * @flags: attributes of pages (read/write/valid/etc.)
 *
 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
 * mappings as we do so.
2118 2119 2120
 *
 * Returns:
 * 0 for success, error for failure.
2121 2122 2123 2124 2125 2126 2127 2128 2129
 *
 * Object has to be reserved and unreserved outside!
 */
int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
			     struct amdgpu_bo_va *bo_va,
			     uint64_t saddr, uint64_t offset,
			     uint64_t size, uint64_t flags)
{
	struct amdgpu_bo_va_mapping *mapping;
2130
	struct amdgpu_bo *bo = bo_va->base.bo;
2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141
	uint64_t eaddr;
	int r;

	/* validate the parameters */
	if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
	    size == 0 || size & AMDGPU_GPU_PAGE_MASK)
		return -EINVAL;

	/* make sure object fit at this offset */
	eaddr = saddr + size - 1;
	if (saddr >= eaddr ||
2142
	    (bo && offset + size > amdgpu_bo_size(bo)))
2143 2144 2145 2146 2147 2148 2149
		return -EINVAL;

	/* Allocate all the needed memory */
	mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
	if (!mapping)
		return -ENOMEM;

2150
	r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size);
2151 2152 2153 2154 2155 2156 2157 2158
	if (r) {
		kfree(mapping);
		return r;
	}

	saddr /= AMDGPU_GPU_PAGE_SIZE;
	eaddr /= AMDGPU_GPU_PAGE_SIZE;

2159 2160
	mapping->start = saddr;
	mapping->last = eaddr;
2161 2162 2163
	mapping->offset = offset;
	mapping->flags = flags;

2164
	amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2165

A
Alex Deucher 已提交
2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176
	return 0;
}

/**
 * amdgpu_vm_bo_unmap - remove bo mapping from vm
 *
 * @adev: amdgpu_device pointer
 * @bo_va: bo_va to remove the address from
 * @saddr: where to the BO is mapped
 *
 * Remove a mapping of the BO at the specefied addr from the VM.
2177 2178 2179
 *
 * Returns:
 * 0 for success, error for failure.
A
Alex Deucher 已提交
2180
 *
2181
 * Object has to be reserved and unreserved outside!
A
Alex Deucher 已提交
2182 2183 2184 2185 2186 2187
 */
int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
		       struct amdgpu_bo_va *bo_va,
		       uint64_t saddr)
{
	struct amdgpu_bo_va_mapping *mapping;
2188
	struct amdgpu_vm *vm = bo_va->base.vm;
2189
	bool valid = true;
A
Alex Deucher 已提交
2190

2191
	saddr /= AMDGPU_GPU_PAGE_SIZE;
2192

2193
	list_for_each_entry(mapping, &bo_va->valids, list) {
2194
		if (mapping->start == saddr)
A
Alex Deucher 已提交
2195 2196 2197
			break;
	}

2198 2199 2200 2201
	if (&mapping->list == &bo_va->valids) {
		valid = false;

		list_for_each_entry(mapping, &bo_va->invalids, list) {
2202
			if (mapping->start == saddr)
2203 2204 2205
				break;
		}

2206
		if (&mapping->list == &bo_va->invalids)
2207
			return -ENOENT;
A
Alex Deucher 已提交
2208
	}
2209

A
Alex Deucher 已提交
2210
	list_del(&mapping->list);
2211
	amdgpu_vm_it_remove(mapping, &vm->va);
2212
	mapping->bo_va = NULL;
2213
	trace_amdgpu_vm_bo_unmap(bo_va, mapping);
A
Alex Deucher 已提交
2214

2215
	if (valid)
A
Alex Deucher 已提交
2216
		list_add(&mapping->list, &vm->freed);
2217
	else
2218 2219
		amdgpu_vm_free_mapping(adev, vm, mapping,
				       bo_va->last_pt_update);
A
Alex Deucher 已提交
2220 2221 2222 2223

	return 0;
}

2224 2225 2226 2227 2228 2229 2230 2231 2232
/**
 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
 *
 * @adev: amdgpu_device pointer
 * @vm: VM structure to use
 * @saddr: start of the range
 * @size: size of the range
 *
 * Remove all mappings in a range, split them as appropriate.
2233 2234 2235
 *
 * Returns:
 * 0 for success, error for failure.
2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252
 */
int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
				struct amdgpu_vm *vm,
				uint64_t saddr, uint64_t size)
{
	struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
	LIST_HEAD(removed);
	uint64_t eaddr;

	eaddr = saddr + size - 1;
	saddr /= AMDGPU_GPU_PAGE_SIZE;
	eaddr /= AMDGPU_GPU_PAGE_SIZE;

	/* Allocate all the needed memory */
	before = kzalloc(sizeof(*before), GFP_KERNEL);
	if (!before)
		return -ENOMEM;
2253
	INIT_LIST_HEAD(&before->list);
2254 2255 2256 2257 2258 2259

	after = kzalloc(sizeof(*after), GFP_KERNEL);
	if (!after) {
		kfree(before);
		return -ENOMEM;
	}
2260
	INIT_LIST_HEAD(&after->list);
2261 2262

	/* Now gather all removed mappings */
2263 2264
	tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
	while (tmp) {
2265
		/* Remember mapping split at the start */
2266 2267 2268
		if (tmp->start < saddr) {
			before->start = tmp->start;
			before->last = saddr - 1;
2269 2270
			before->offset = tmp->offset;
			before->flags = tmp->flags;
2271 2272
			before->bo_va = tmp->bo_va;
			list_add(&before->list, &tmp->bo_va->invalids);
2273 2274 2275
		}

		/* Remember mapping split at the end */
2276 2277 2278
		if (tmp->last > eaddr) {
			after->start = eaddr + 1;
			after->last = tmp->last;
2279
			after->offset = tmp->offset;
2280
			after->offset += after->start - tmp->start;
2281
			after->flags = tmp->flags;
2282 2283
			after->bo_va = tmp->bo_va;
			list_add(&after->list, &tmp->bo_va->invalids);
2284 2285 2286 2287
		}

		list_del(&tmp->list);
		list_add(&tmp->list, &removed);
2288 2289

		tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
2290 2291 2292 2293
	}

	/* And free them up */
	list_for_each_entry_safe(tmp, next, &removed, list) {
2294
		amdgpu_vm_it_remove(tmp, &vm->va);
2295 2296
		list_del(&tmp->list);

2297 2298 2299 2300
		if (tmp->start < saddr)
		    tmp->start = saddr;
		if (tmp->last > eaddr)
		    tmp->last = eaddr;
2301

2302
		tmp->bo_va = NULL;
2303 2304 2305 2306
		list_add(&tmp->list, &vm->freed);
		trace_amdgpu_vm_bo_unmap(NULL, tmp);
	}

2307 2308
	/* Insert partial mapping before the range */
	if (!list_empty(&before->list)) {
2309
		amdgpu_vm_it_insert(before, &vm->va);
2310 2311 2312 2313 2314 2315 2316
		if (before->flags & AMDGPU_PTE_PRT)
			amdgpu_vm_prt_get(adev);
	} else {
		kfree(before);
	}

	/* Insert partial mapping after the range */
2317
	if (!list_empty(&after->list)) {
2318
		amdgpu_vm_it_insert(after, &vm->va);
2319 2320 2321 2322 2323 2324 2325 2326 2327
		if (after->flags & AMDGPU_PTE_PRT)
			amdgpu_vm_prt_get(adev);
	} else {
		kfree(after);
	}

	return 0;
}

2328 2329 2330 2331
/**
 * amdgpu_vm_bo_lookup_mapping - find mapping by address
 *
 * @vm: the requested VM
2332
 * @addr: the address
2333 2334
 *
 * Find a mapping by it's address.
2335 2336 2337 2338
 *
 * Returns:
 * The amdgpu_bo_va_mapping matching for addr or NULL
 *
2339 2340 2341 2342 2343 2344 2345
 */
struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
							 uint64_t addr)
{
	return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
}

A
Alex Deucher 已提交
2346 2347 2348 2349 2350 2351
/**
 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
 *
 * @adev: amdgpu_device pointer
 * @bo_va: requested bo_va
 *
2352
 * Remove @bo_va->bo from the requested vm.
A
Alex Deucher 已提交
2353 2354 2355 2356 2357 2358 2359
 *
 * Object have to be reserved!
 */
void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
		      struct amdgpu_bo_va *bo_va)
{
	struct amdgpu_bo_va_mapping *mapping, *next;
2360
	struct amdgpu_vm *vm = bo_va->base.vm;
A
Alex Deucher 已提交
2361

2362
	list_del(&bo_va->base.bo_list);
A
Alex Deucher 已提交
2363

2364
	spin_lock(&vm->moved_lock);
2365
	list_del(&bo_va->base.vm_status);
2366
	spin_unlock(&vm->moved_lock);
A
Alex Deucher 已提交
2367

2368
	list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
A
Alex Deucher 已提交
2369
		list_del(&mapping->list);
2370
		amdgpu_vm_it_remove(mapping, &vm->va);
2371
		mapping->bo_va = NULL;
2372
		trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2373 2374 2375 2376
		list_add(&mapping->list, &vm->freed);
	}
	list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
		list_del(&mapping->list);
2377
		amdgpu_vm_it_remove(mapping, &vm->va);
2378 2379
		amdgpu_vm_free_mapping(adev, vm, mapping,
				       bo_va->last_pt_update);
A
Alex Deucher 已提交
2380
	}
2381

2382
	dma_fence_put(bo_va->last_pt_update);
A
Alex Deucher 已提交
2383 2384 2385 2386 2387 2388 2389 2390
	kfree(bo_va);
}

/**
 * amdgpu_vm_bo_invalidate - mark the bo as invalid
 *
 * @adev: amdgpu_device pointer
 * @bo: amdgpu buffer object
2391
 * @evicted: is the BO evicted
A
Alex Deucher 已提交
2392
 *
2393
 * Mark @bo as invalid.
A
Alex Deucher 已提交
2394 2395
 */
void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2396
			     struct amdgpu_bo *bo, bool evicted)
A
Alex Deucher 已提交
2397
{
2398 2399
	struct amdgpu_vm_bo_base *bo_base;

2400 2401 2402 2403
	/* shadow bo doesn't have bo base, its validation needs its parent */
	if (bo->parent && bo->parent->shadow == bo)
		bo = bo->parent;

2404
	list_for_each_entry(bo_base, &bo->va, bo_list) {
2405
		struct amdgpu_vm *vm = bo_base->vm;
2406
		bool was_moved = bo_base->moved;
2407

2408
		bo_base->moved = true;
2409
		if (evicted && bo->tbo.resv == vm->root.base.bo->tbo.resv) {
2410 2411 2412 2413 2414
			if (bo->tbo.type == ttm_bo_type_kernel)
				list_move(&bo_base->vm_status, &vm->evicted);
			else
				list_move_tail(&bo_base->vm_status,
					       &vm->evicted);
2415 2416 2417
			continue;
		}

2418
		if (was_moved)
2419 2420
			continue;

2421 2422 2423 2424 2425 2426 2427
		if (bo->tbo.type == ttm_bo_type_kernel) {
			list_move(&bo_base->vm_status, &vm->relocated);
		} else {
			spin_lock(&bo_base->vm->moved_lock);
			list_move(&bo_base->vm_status, &vm->moved);
			spin_unlock(&bo_base->vm->moved_lock);
		}
A
Alex Deucher 已提交
2428 2429 2430
	}
}

2431 2432 2433 2434 2435 2436 2437 2438
/**
 * amdgpu_vm_get_block_size - calculate VM page table size as power of two
 *
 * @vm_size: VM size
 *
 * Returns:
 * VM page table as power of two
 */
2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451
static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
{
	/* Total bits covered by PD + PTs */
	unsigned bits = ilog2(vm_size) + 18;

	/* Make sure the PD is 4K in size up to 8GB address space.
	   Above that split equal between PD and PTs */
	if (vm_size <= 8)
		return (bits - 9);
	else
		return ((bits + 3) / 2);
}

2452 2453
/**
 * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
2454 2455 2456
 *
 * @adev: amdgpu_device pointer
 * @vm_size: the default vm size if it's set auto
2457 2458 2459 2460
 * @fragment_size_default: Default PTE fragment size
 * @max_level: max VMPT level
 * @max_bits: max address space size in bits
 *
2461
 */
2462
void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
2463 2464
			   uint32_t fragment_size_default, unsigned max_level,
			   unsigned max_bits)
2465
{
2466 2467 2468
	uint64_t tmp;

	/* adjust vm size first */
2469 2470 2471
	if (amdgpu_vm_size != -1) {
		unsigned max_size = 1 << (max_bits - 30);

2472
		vm_size = amdgpu_vm_size;
2473 2474 2475 2476 2477 2478
		if (vm_size > max_size) {
			dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",
				 amdgpu_vm_size, max_size);
			vm_size = max_size;
		}
	}
2479 2480

	adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
2481 2482

	tmp = roundup_pow_of_two(adev->vm_manager.max_pfn);
2483 2484
	if (amdgpu_vm_block_size != -1)
		tmp >>= amdgpu_vm_block_size - 9;
2485 2486
	tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
	adev->vm_manager.num_level = min(max_level, (unsigned)tmp);
2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499
	switch (adev->vm_manager.num_level) {
	case 3:
		adev->vm_manager.root_level = AMDGPU_VM_PDB2;
		break;
	case 2:
		adev->vm_manager.root_level = AMDGPU_VM_PDB1;
		break;
	case 1:
		adev->vm_manager.root_level = AMDGPU_VM_PDB0;
		break;
	default:
		dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n");
	}
2500
	/* block size depends on vm size and hw setup*/
2501
	if (amdgpu_vm_block_size != -1)
2502
		adev->vm_manager.block_size =
2503 2504 2505 2506 2507
			min((unsigned)amdgpu_vm_block_size, max_bits
			    - AMDGPU_GPU_PAGE_SHIFT
			    - 9 * adev->vm_manager.num_level);
	else if (adev->vm_manager.num_level > 1)
		adev->vm_manager.block_size = 9;
2508
	else
2509
		adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp);
2510

2511 2512 2513 2514
	if (amdgpu_vm_fragment_size == -1)
		adev->vm_manager.fragment_size = fragment_size_default;
	else
		adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
2515

2516 2517 2518
	DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",
		 vm_size, adev->vm_manager.num_level + 1,
		 adev->vm_manager.block_size,
2519
		 adev->vm_manager.fragment_size);
2520 2521
}

A
Alex Deucher 已提交
2522 2523 2524 2525 2526
/**
 * amdgpu_vm_init - initialize a vm instance
 *
 * @adev: amdgpu_device pointer
 * @vm: requested vm
2527
 * @vm_context: Indicates if it GFX or Compute context
2528
 * @pasid: Process address space identifier
A
Alex Deucher 已提交
2529
 *
2530
 * Init @vm fields.
2531 2532 2533
 *
 * Returns:
 * 0 for success, error for failure.
A
Alex Deucher 已提交
2534
 */
2535
int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
2536
		   int vm_context, unsigned int pasid)
A
Alex Deucher 已提交
2537
{
2538
	struct amdgpu_bo_param bp;
2539
	struct amdgpu_bo *root;
A
Alex Deucher 已提交
2540
	const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
2541
		AMDGPU_VM_PTE_COUNT(adev) * 8);
2542 2543
	unsigned ring_instance;
	struct amdgpu_ring *ring;
2544
	struct drm_sched_rq *rq;
2545
	unsigned long size;
2546
	uint64_t flags;
2547
	int r, i;
A
Alex Deucher 已提交
2548

2549
	vm->va = RB_ROOT_CACHED;
2550 2551
	for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
		vm->reserved_vmid[i] = NULL;
2552
	INIT_LIST_HEAD(&vm->evicted);
2553
	INIT_LIST_HEAD(&vm->relocated);
2554
	spin_lock_init(&vm->moved_lock);
2555
	INIT_LIST_HEAD(&vm->moved);
2556
	INIT_LIST_HEAD(&vm->idle);
A
Alex Deucher 已提交
2557
	INIT_LIST_HEAD(&vm->freed);
2558

2559
	/* create scheduler entity for page table updates */
2560 2561 2562 2563

	ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring);
	ring_instance %= adev->vm_manager.vm_pte_num_rings;
	ring = adev->vm_manager.vm_pte_rings[ring_instance];
2564
	rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
2565
	r = drm_sched_entity_init(&vm->entity, &rq, 1, NULL);
2566
	if (r)
2567
		return r;
2568

Y
Yong Zhao 已提交
2569 2570 2571
	vm->pte_support_ats = false;

	if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) {
2572 2573
		vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
						AMDGPU_VM_USE_CPU_FOR_COMPUTE);
Y
Yong Zhao 已提交
2574

2575
		if (adev->asic_type == CHIP_RAVEN)
Y
Yong Zhao 已提交
2576
			vm->pte_support_ats = true;
2577
	} else {
2578 2579
		vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
						AMDGPU_VM_USE_CPU_FOR_GFX);
2580
	}
2581 2582
	DRM_DEBUG_DRIVER("VM update mode is %s\n",
			 vm->use_cpu_for_update ? "CPU" : "SDMA");
2583
	WARN_ONCE((vm->use_cpu_for_update & !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2584
		  "CPU update of VM recommended only for large BAR system\n");
2585
	vm->last_update = NULL;
2586

2587
	flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
2588 2589 2590
	if (vm->use_cpu_for_update)
		flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
	else
2591
		flags |= AMDGPU_GEM_CREATE_SHADOW;
2592

2593
	size = amdgpu_vm_bo_size(adev, adev->vm_manager.root_level);
2594 2595 2596 2597 2598 2599 2600
	memset(&bp, 0, sizeof(bp));
	bp.size = size;
	bp.byte_align = align;
	bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
	bp.flags = flags;
	bp.type = ttm_bo_type_kernel;
	bp.resv = NULL;
2601
	r = amdgpu_bo_create(adev, &bp, &root);
A
Alex Deucher 已提交
2602
	if (r)
2603 2604
		goto error_free_sched_entity;

2605
	r = amdgpu_bo_reserve(root, true);
2606 2607 2608
	if (r)
		goto error_free_root;

2609
	r = amdgpu_vm_clear_bo(adev, vm, root,
2610 2611
			       adev->vm_manager.root_level,
			       vm->pte_support_ats);
2612 2613 2614
	if (r)
		goto error_unreserve;

2615
	amdgpu_vm_bo_base_init(&vm->root.base, vm, root);
2616
	amdgpu_bo_unreserve(vm->root.base.bo);
A
Alex Deucher 已提交
2617

2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628
	if (pasid) {
		unsigned long flags;

		spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
		r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
			      GFP_ATOMIC);
		spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
		if (r < 0)
			goto error_free_root;

		vm->pasid = pasid;
2629 2630
	}

2631
	INIT_KFIFO(vm->faults);
2632
	vm->fault_credit = 16;
A
Alex Deucher 已提交
2633 2634

	return 0;
2635

2636 2637 2638
error_unreserve:
	amdgpu_bo_unreserve(vm->root.base.bo);

2639
error_free_root:
2640 2641 2642
	amdgpu_bo_unref(&vm->root.base.bo->shadow);
	amdgpu_bo_unref(&vm->root.base.bo);
	vm->root.base.bo = NULL;
2643 2644

error_free_sched_entity:
2645
	drm_sched_entity_destroy(&vm->entity);
2646 2647

	return r;
A
Alex Deucher 已提交
2648 2649
}

2650 2651 2652
/**
 * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM
 *
2653 2654 2655
 * @adev: amdgpu_device pointer
 * @vm: requested vm
 *
2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667
 * This only works on GFX VMs that don't have any BOs added and no
 * page tables allocated yet.
 *
 * Changes the following VM parameters:
 * - use_cpu_for_update
 * - pte_supports_ats
 * - pasid (old PASID is released, because compute manages its own PASIDs)
 *
 * Reinitializes the page directory to reflect the changed ATS
 * setting. May leave behind an unused shadow BO for the page
 * directory when switching from SDMA updates to CPU updates.
 *
2668 2669
 * Returns:
 * 0 for success, -errno for errors.
2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702
 */
int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
{
	bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
	int r;

	r = amdgpu_bo_reserve(vm->root.base.bo, true);
	if (r)
		return r;

	/* Sanity checks */
	if (!RB_EMPTY_ROOT(&vm->va.rb_root) || vm->root.entries) {
		r = -EINVAL;
		goto error;
	}

	/* Check if PD needs to be reinitialized and do it before
	 * changing any other state, in case it fails.
	 */
	if (pte_support_ats != vm->pte_support_ats) {
		r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo,
			       adev->vm_manager.root_level,
			       pte_support_ats);
		if (r)
			goto error;
	}

	/* Update VM state */
	vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
				    AMDGPU_VM_USE_CPU_FOR_COMPUTE);
	vm->pte_support_ats = pte_support_ats;
	DRM_DEBUG_DRIVER("VM update mode is %s\n",
			 vm->use_cpu_for_update ? "CPU" : "SDMA");
2703
	WARN_ONCE((vm->use_cpu_for_update & !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2704 2705 2706 2707 2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720
		  "CPU update of VM recommended only for large BAR system\n");

	if (vm->pasid) {
		unsigned long flags;

		spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
		idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
		spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);

		vm->pasid = 0;
	}

error:
	amdgpu_bo_unreserve(vm->root.base.bo);
	return r;
}

2721 2722 2723
/**
 * amdgpu_vm_free_levels - free PD/PT levels
 *
2724 2725 2726
 * @adev: amdgpu device structure
 * @parent: PD/PT starting level to free
 * @level: level of parent structure
2727 2728 2729
 *
 * Free the page directory or page table level and all sub levels.
 */
2730 2731 2732
static void amdgpu_vm_free_levels(struct amdgpu_device *adev,
				  struct amdgpu_vm_pt *parent,
				  unsigned level)
2733
{
2734
	unsigned i, num_entries = amdgpu_vm_num_entries(adev, level);
2735

2736 2737 2738 2739 2740
	if (parent->base.bo) {
		list_del(&parent->base.bo_list);
		list_del(&parent->base.vm_status);
		amdgpu_bo_unref(&parent->base.bo->shadow);
		amdgpu_bo_unref(&parent->base.bo);
2741 2742
	}

2743 2744 2745 2746
	if (parent->entries)
		for (i = 0; i < num_entries; i++)
			amdgpu_vm_free_levels(adev, &parent->entries[i],
					      level + 1);
2747

2748
	kvfree(parent->entries);
2749 2750
}

A
Alex Deucher 已提交
2751 2752 2753 2754 2755 2756
/**
 * amdgpu_vm_fini - tear down a vm instance
 *
 * @adev: amdgpu_device pointer
 * @vm: requested vm
 *
2757
 * Tear down @vm.
A
Alex Deucher 已提交
2758 2759 2760 2761 2762
 * Unbind the VM and remove all bos from the vm bo list
 */
void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
{
	struct amdgpu_bo_va_mapping *mapping, *tmp;
2763
	bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt;
2764
	struct amdgpu_bo *root;
2765
	u64 fault;
2766
	int i, r;
A
Alex Deucher 已提交
2767

2768 2769
	amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);

2770 2771 2772 2773
	/* Clear pending page faults from IH when the VM is destroyed */
	while (kfifo_get(&vm->faults, &fault))
		amdgpu_ih_clear_fault(adev, fault);

2774 2775 2776 2777 2778 2779 2780 2781
	if (vm->pasid) {
		unsigned long flags;

		spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
		idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
		spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
	}

2782
	drm_sched_entity_destroy(&vm->entity);
2783

2784
	if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
A
Alex Deucher 已提交
2785 2786
		dev_err(adev->dev, "still active bo inside vm\n");
	}
2787 2788
	rbtree_postorder_for_each_entry_safe(mapping, tmp,
					     &vm->va.rb_root, rb) {
A
Alex Deucher 已提交
2789
		list_del(&mapping->list);
2790
		amdgpu_vm_it_remove(mapping, &vm->va);
A
Alex Deucher 已提交
2791 2792 2793
		kfree(mapping);
	}
	list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
2794
		if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
2795
			amdgpu_vm_prt_fini(adev, vm);
2796
			prt_fini_needed = false;
2797
		}
2798

A
Alex Deucher 已提交
2799
		list_del(&mapping->list);
2800
		amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
A
Alex Deucher 已提交
2801 2802
	}

2803 2804 2805 2806 2807
	root = amdgpu_bo_ref(vm->root.base.bo);
	r = amdgpu_bo_reserve(root, true);
	if (r) {
		dev_err(adev->dev, "Leaking page tables because BO reservation failed\n");
	} else {
2808 2809
		amdgpu_vm_free_levels(adev, &vm->root,
				      adev->vm_manager.root_level);
2810 2811 2812
		amdgpu_bo_unreserve(root);
	}
	amdgpu_bo_unref(&root);
2813
	dma_fence_put(vm->last_update);
2814
	for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2815
		amdgpu_vmid_free_reserved(adev, vm, i);
A
Alex Deucher 已提交
2816
}
2817

2818 2819 2820 2821 2822 2823
/**
 * amdgpu_vm_pasid_fault_credit - Check fault credit for given PASID
 *
 * @adev: amdgpu_device pointer
 * @pasid: PASID do identify the VM
 *
2824 2825 2826 2827
 * This function is expected to be called in interrupt context.
 *
 * Returns:
 * True if there was fault credit, false otherwise
2828 2829 2830 2831 2832 2833 2834 2835
 */
bool amdgpu_vm_pasid_fault_credit(struct amdgpu_device *adev,
				  unsigned int pasid)
{
	struct amdgpu_vm *vm;

	spin_lock(&adev->vm_manager.pasid_lock);
	vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
2836
	if (!vm) {
2837
		/* VM not found, can't track fault credit */
2838
		spin_unlock(&adev->vm_manager.pasid_lock);
2839
		return true;
2840
	}
2841 2842

	/* No lock needed. only accessed by IRQ handler */
2843
	if (!vm->fault_credit) {
2844
		/* Too many faults in this VM */
2845
		spin_unlock(&adev->vm_manager.pasid_lock);
2846
		return false;
2847
	}
2848 2849

	vm->fault_credit--;
2850
	spin_unlock(&adev->vm_manager.pasid_lock);
2851 2852 2853
	return true;
}

2854 2855 2856 2857 2858 2859 2860 2861 2862
/**
 * amdgpu_vm_manager_init - init the VM manager
 *
 * @adev: amdgpu_device pointer
 *
 * Initialize the VM manager structures
 */
void amdgpu_vm_manager_init(struct amdgpu_device *adev)
{
2863
	unsigned i;
2864

2865
	amdgpu_vmid_mgr_init(adev);
2866

2867 2868
	adev->vm_manager.fence_context =
		dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2869 2870 2871
	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
		adev->vm_manager.seqno[i] = 0;

2872
	atomic_set(&adev->vm_manager.vm_pte_next_ring, 0);
2873
	spin_lock_init(&adev->vm_manager.prt_lock);
2874
	atomic_set(&adev->vm_manager.num_prt_users, 0);
2875 2876 2877 2878 2879 2880

	/* If not overridden by the user, by default, only in large BAR systems
	 * Compute VM tables will be updated by CPU
	 */
#ifdef CONFIG_X86_64
	if (amdgpu_vm_update_mode == -1) {
2881
		if (amdgpu_gmc_vram_full_visible(&adev->gmc))
2882 2883 2884 2885 2886 2887 2888 2889 2890 2891
			adev->vm_manager.vm_update_mode =
				AMDGPU_VM_USE_CPU_FOR_COMPUTE;
		else
			adev->vm_manager.vm_update_mode = 0;
	} else
		adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode;
#else
	adev->vm_manager.vm_update_mode = 0;
#endif

2892 2893
	idr_init(&adev->vm_manager.pasid_idr);
	spin_lock_init(&adev->vm_manager.pasid_lock);
2894 2895
}

2896 2897 2898 2899 2900 2901 2902 2903 2904
/**
 * amdgpu_vm_manager_fini - cleanup VM manager
 *
 * @adev: amdgpu_device pointer
 *
 * Cleanup the VM manager and free resources.
 */
void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
{
2905 2906 2907
	WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr));
	idr_destroy(&adev->vm_manager.pasid_idr);

2908
	amdgpu_vmid_mgr_fini(adev);
2909
}
C
Chunming Zhou 已提交
2910

2911 2912 2913 2914 2915 2916 2917 2918 2919 2920
/**
 * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs.
 *
 * @dev: drm device pointer
 * @data: drm_amdgpu_vm
 * @filp: drm file pointer
 *
 * Returns:
 * 0 for success, -errno for errors.
 */
C
Chunming Zhou 已提交
2921 2922 2923
int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
{
	union drm_amdgpu_vm *args = data;
2924 2925 2926
	struct amdgpu_device *adev = dev->dev_private;
	struct amdgpu_fpriv *fpriv = filp->driver_priv;
	int r;
C
Chunming Zhou 已提交
2927 2928 2929

	switch (args->in.op) {
	case AMDGPU_VM_OP_RESERVE_VMID:
2930
		/* current, we only have requirement to reserve vmid from gfxhub */
2931
		r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB);
2932 2933 2934
		if (r)
			return r;
		break;
C
Chunming Zhou 已提交
2935
	case AMDGPU_VM_OP_UNRESERVE_VMID:
2936
		amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB);
C
Chunming Zhou 已提交
2937 2938 2939 2940 2941 2942 2943
		break;
	default:
		return -EINVAL;
	}

	return 0;
}
2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 2956 2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982

/**
 * amdgpu_vm_get_task_info - Extracts task info for a PASID.
 *
 * @dev: drm device pointer
 * @pasid: PASID identifier for VM
 * @task_info: task_info to fill.
 */
void amdgpu_vm_get_task_info(struct amdgpu_device *adev, unsigned int pasid,
			 struct amdgpu_task_info *task_info)
{
	struct amdgpu_vm *vm;

	spin_lock(&adev->vm_manager.pasid_lock);

	vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
	if (vm)
		*task_info = vm->task_info;

	spin_unlock(&adev->vm_manager.pasid_lock);
}

/**
 * amdgpu_vm_set_task_info - Sets VMs task info.
 *
 * @vm: vm for which to set the info
 */
void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)
{
	if (!vm->task_info.pid) {
		vm->task_info.pid = current->pid;
		get_task_comm(vm->task_info.task_name, current);

		if (current->group_leader->mm == current->mm) {
			vm->task_info.tgid = current->group_leader->pid;
			get_task_comm(vm->task_info.process_name, current->group_leader);
		}
	}
}