i915_irq.c 129.6 KB
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/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
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 */
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/*
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

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#include <linux/sysrq.h>
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#include <linux/slab.h>
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#include <linux/circ_buf.h>
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#include <drm/drmP.h>
#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#include "i915_trace.h"
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#include "intel_drv.h"
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/**
 * DOC: interrupt handling
 *
 * These functions provide the basic support for enabling and disabling the
 * interrupt handling support. There's a lot more functionality in i915_irq.c
 * and related files, but that will be described in separate chapters.
 */

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static const u32 hpd_ilk[HPD_NUM_PINS] = {
	[HPD_PORT_A] = DE_DP_A_HOTPLUG,
};

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static const u32 hpd_ivb[HPD_NUM_PINS] = {
	[HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
};

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static const u32 hpd_bdw[HPD_NUM_PINS] = {
	[HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
};

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static const u32 hpd_ibx[HPD_NUM_PINS] = {
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	[HPD_CRT] = SDE_CRT_HOTPLUG,
	[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
	[HPD_PORT_B] = SDE_PORTB_HOTPLUG,
	[HPD_PORT_C] = SDE_PORTC_HOTPLUG,
	[HPD_PORT_D] = SDE_PORTD_HOTPLUG
};

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static const u32 hpd_cpt[HPD_NUM_PINS] = {
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	[HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
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	[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
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	[HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
	[HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
	[HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
};

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static const u32 hpd_spt[HPD_NUM_PINS] = {
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	[HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
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	[HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
	[HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
	[HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
	[HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
};

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static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
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	[HPD_CRT] = CRT_HOTPLUG_INT_EN,
	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
	[HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
	[HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
	[HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
};

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static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
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	[HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
	[HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
	[HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
	[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
};

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static const u32 hpd_status_i915[HPD_NUM_PINS] = {
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	[HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
	[HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
	[HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
	[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
};

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/* BXT hpd list */
static const u32 hpd_bxt[HPD_NUM_PINS] = {
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	[HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
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	[HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
	[HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
};

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/* IIR can theoretically queue up two events. Be paranoid. */
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#define GEN8_IRQ_RESET_NDX(type, which) do { \
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	I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
	POSTING_READ(GEN8_##type##_IMR(which)); \
	I915_WRITE(GEN8_##type##_IER(which), 0); \
	I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
	POSTING_READ(GEN8_##type##_IIR(which)); \
	I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
	POSTING_READ(GEN8_##type##_IIR(which)); \
} while (0)

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#define GEN5_IRQ_RESET(type) do { \
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	I915_WRITE(type##IMR, 0xffffffff); \
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	POSTING_READ(type##IMR); \
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	I915_WRITE(type##IER, 0); \
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	I915_WRITE(type##IIR, 0xffffffff); \
	POSTING_READ(type##IIR); \
	I915_WRITE(type##IIR, 0xffffffff); \
	POSTING_READ(type##IIR); \
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} while (0)

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/*
 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
 */
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static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv,
				    i915_reg_t reg)
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{
	u32 val = I915_READ(reg);

	if (val == 0)
		return;

	WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
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	     i915_mmio_reg_offset(reg), val);
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	I915_WRITE(reg, 0xffffffff);
	POSTING_READ(reg);
	I915_WRITE(reg, 0xffffffff);
	POSTING_READ(reg);
}
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#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
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	gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
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	I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
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	I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
	POSTING_READ(GEN8_##type##_IMR(which)); \
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} while (0)

#define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
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	gen5_assert_iir_is_zero(dev_priv, type##IIR); \
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	I915_WRITE(type##IER, (ier_val)); \
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	I915_WRITE(type##IMR, (imr_val)); \
	POSTING_READ(type##IMR); \
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} while (0)

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static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);

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/* For display hotplug interrupt */
static inline void
i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
				     uint32_t mask,
				     uint32_t bits)
{
	uint32_t val;

	assert_spin_locked(&dev_priv->irq_lock);
	WARN_ON(bits & ~mask);

	val = I915_READ(PORT_HOTPLUG_EN);
	val &= ~mask;
	val |= bits;
	I915_WRITE(PORT_HOTPLUG_EN, val);
}

/**
 * i915_hotplug_interrupt_update - update hotplug interrupt enable
 * @dev_priv: driver private
 * @mask: bits to update
 * @bits: bits to enable
 * NOTE: the HPD enable bits are modified both inside and outside
 * of an interrupt context. To avoid that read-modify-write cycles
 * interfer, these bits are protected by a spinlock. Since this
 * function is usually not called from a context where the lock is
 * held already, this function acquires the lock itself. A non-locking
 * version is also available.
 */
void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
				   uint32_t mask,
				   uint32_t bits)
{
	spin_lock_irq(&dev_priv->irq_lock);
	i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
	spin_unlock_irq(&dev_priv->irq_lock);
}

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/**
 * ilk_update_display_irq - update DEIMR
 * @dev_priv: driver private
 * @interrupt_mask: mask of interrupt bits to update
 * @enabled_irq_mask: mask of interrupt bits to enable
 */
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void ilk_update_display_irq(struct drm_i915_private *dev_priv,
			    uint32_t interrupt_mask,
			    uint32_t enabled_irq_mask)
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{
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	uint32_t new_val;

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	assert_spin_locked(&dev_priv->irq_lock);

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	WARN_ON(enabled_irq_mask & ~interrupt_mask);

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	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
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		return;

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	new_val = dev_priv->irq_mask;
	new_val &= ~interrupt_mask;
	new_val |= (~enabled_irq_mask & interrupt_mask);

	if (new_val != dev_priv->irq_mask) {
		dev_priv->irq_mask = new_val;
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		I915_WRITE(DEIMR, dev_priv->irq_mask);
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		POSTING_READ(DEIMR);
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	}
}

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/**
 * ilk_update_gt_irq - update GTIMR
 * @dev_priv: driver private
 * @interrupt_mask: mask of interrupt bits to update
 * @enabled_irq_mask: mask of interrupt bits to enable
 */
static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
			      uint32_t interrupt_mask,
			      uint32_t enabled_irq_mask)
{
	assert_spin_locked(&dev_priv->irq_lock);

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	WARN_ON(enabled_irq_mask & ~interrupt_mask);

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	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
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		return;

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	dev_priv->gt_irq_mask &= ~interrupt_mask;
	dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
}

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void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
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{
	ilk_update_gt_irq(dev_priv, mask, mask);
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	POSTING_READ_FW(GTIMR);
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}

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void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
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{
	ilk_update_gt_irq(dev_priv, mask, 0);
}

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static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
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{
	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
}

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static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
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{
	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
}

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static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
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{
	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
}

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/**
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 * snb_update_pm_irq - update GEN6_PMIMR
 * @dev_priv: driver private
 * @interrupt_mask: mask of interrupt bits to update
 * @enabled_irq_mask: mask of interrupt bits to enable
 */
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static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
			      uint32_t interrupt_mask,
			      uint32_t enabled_irq_mask)
{
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	uint32_t new_val;
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	WARN_ON(enabled_irq_mask & ~interrupt_mask);

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	assert_spin_locked(&dev_priv->irq_lock);

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	new_val = dev_priv->pm_irq_mask;
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	new_val &= ~interrupt_mask;
	new_val |= (~enabled_irq_mask & interrupt_mask);

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	if (new_val != dev_priv->pm_irq_mask) {
		dev_priv->pm_irq_mask = new_val;
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		I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
		POSTING_READ(gen6_pm_imr(dev_priv));
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	}
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}

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void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
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{
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	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
		return;

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	snb_update_pm_irq(dev_priv, mask, mask);
}

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static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
				  uint32_t mask)
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{
	snb_update_pm_irq(dev_priv, mask, 0);
}

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void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
{
	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
		return;

	__gen6_disable_pm_irq(dev_priv, mask);
}

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void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
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{
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	i915_reg_t reg = gen6_pm_iir(dev_priv);
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	spin_lock_irq(&dev_priv->irq_lock);
	I915_WRITE(reg, dev_priv->pm_rps_events);
	I915_WRITE(reg, dev_priv->pm_rps_events);
	POSTING_READ(reg);
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	dev_priv->rps.pm_iir = 0;
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	spin_unlock_irq(&dev_priv->irq_lock);
}

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void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
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{
	spin_lock_irq(&dev_priv->irq_lock);
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	WARN_ON_ONCE(dev_priv->rps.pm_iir);
	WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
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	dev_priv->rps.interrupts_enabled = true;
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	I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
				dev_priv->pm_rps_events);
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	gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
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	spin_unlock_irq(&dev_priv->irq_lock);
}

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u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
{
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	return (mask & ~dev_priv->rps.pm_intr_keep);
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}

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void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
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{
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	spin_lock_irq(&dev_priv->irq_lock);
	dev_priv->rps.interrupts_enabled = false;
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	I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0));
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	__gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
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	I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
				~dev_priv->pm_rps_events);
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	spin_unlock_irq(&dev_priv->irq_lock);
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	synchronize_irq(dev_priv->drm.irq);
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	/* Now that we will not be generating any more work, flush any
	 * outsanding tasks. As we are called on the RPS idle path,
	 * we will reset the GPU to minimum frequencies, so the current
	 * state of the worker can be discarded.
	 */
	cancel_work_sync(&dev_priv->rps.work);
	gen6_reset_rps_interrupts(dev_priv);
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}

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/**
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 * bdw_update_port_irq - update DE port interrupt
 * @dev_priv: driver private
 * @interrupt_mask: mask of interrupt bits to update
 * @enabled_irq_mask: mask of interrupt bits to enable
 */
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static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
				uint32_t interrupt_mask,
				uint32_t enabled_irq_mask)
{
	uint32_t new_val;
	uint32_t old_val;

	assert_spin_locked(&dev_priv->irq_lock);

	WARN_ON(enabled_irq_mask & ~interrupt_mask);

	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
		return;

	old_val = I915_READ(GEN8_DE_PORT_IMR);

	new_val = old_val;
	new_val &= ~interrupt_mask;
	new_val |= (~enabled_irq_mask & interrupt_mask);

	if (new_val != old_val) {
		I915_WRITE(GEN8_DE_PORT_IMR, new_val);
		POSTING_READ(GEN8_DE_PORT_IMR);
	}
}

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/**
 * bdw_update_pipe_irq - update DE pipe interrupt
 * @dev_priv: driver private
 * @pipe: pipe whose interrupt to update
 * @interrupt_mask: mask of interrupt bits to update
 * @enabled_irq_mask: mask of interrupt bits to enable
 */
void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
			 enum pipe pipe,
			 uint32_t interrupt_mask,
			 uint32_t enabled_irq_mask)
{
	uint32_t new_val;

	assert_spin_locked(&dev_priv->irq_lock);

	WARN_ON(enabled_irq_mask & ~interrupt_mask);

	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
		return;

	new_val = dev_priv->de_irq_mask[pipe];
	new_val &= ~interrupt_mask;
	new_val |= (~enabled_irq_mask & interrupt_mask);

	if (new_val != dev_priv->de_irq_mask[pipe]) {
		dev_priv->de_irq_mask[pipe] = new_val;
		I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
		POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
	}
}

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/**
 * ibx_display_interrupt_update - update SDEIMR
 * @dev_priv: driver private
 * @interrupt_mask: mask of interrupt bits to update
 * @enabled_irq_mask: mask of interrupt bits to enable
 */
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void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
				  uint32_t interrupt_mask,
				  uint32_t enabled_irq_mask)
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{
	uint32_t sdeimr = I915_READ(SDEIMR);
	sdeimr &= ~interrupt_mask;
	sdeimr |= (~enabled_irq_mask & interrupt_mask);

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	WARN_ON(enabled_irq_mask & ~interrupt_mask);

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	assert_spin_locked(&dev_priv->irq_lock);

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	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
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		return;

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	I915_WRITE(SDEIMR, sdeimr);
	POSTING_READ(SDEIMR);
}
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static void
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__i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		       u32 enable_mask, u32 status_mask)
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{
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	i915_reg_t reg = PIPESTAT(pipe);
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	u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
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	assert_spin_locked(&dev_priv->irq_lock);
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	WARN_ON(!intel_irqs_enabled(dev_priv));
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	if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
		      status_mask & ~PIPESTAT_INT_STATUS_MASK,
		      "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
		      pipe_name(pipe), enable_mask, status_mask))
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		return;

	if ((pipestat & enable_mask) == enable_mask)
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		return;

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	dev_priv->pipestat_irq_mask[pipe] |= status_mask;

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	/* Enable the interrupt, clear any pending status */
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	pipestat |= enable_mask | status_mask;
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	I915_WRITE(reg, pipestat);
	POSTING_READ(reg);
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}

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static void
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__i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		        u32 enable_mask, u32 status_mask)
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{
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	i915_reg_t reg = PIPESTAT(pipe);
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	u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
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	assert_spin_locked(&dev_priv->irq_lock);
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	WARN_ON(!intel_irqs_enabled(dev_priv));
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	if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
		      status_mask & ~PIPESTAT_INT_STATUS_MASK,
		      "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
		      pipe_name(pipe), enable_mask, status_mask))
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		return;

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	if ((pipestat & enable_mask) == 0)
		return;

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	dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;

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	pipestat &= ~enable_mask;
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	I915_WRITE(reg, pipestat);
	POSTING_READ(reg);
532 533
}

534 535 536 537 538
static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
{
	u32 enable_mask = status_mask << 16;

	/*
539 540
	 * On pipe A we don't support the PSR interrupt yet,
	 * on pipe B and C the same bit MBZ.
541 542 543
	 */
	if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
		return 0;
544 545 546 547 548 549
	/*
	 * On pipe B and C we don't support the PSR interrupt yet, on pipe
	 * A the same bit is for perf counters which we don't use either.
	 */
	if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
		return 0;
550 551 552 553 554 555 556 557 558 559 560 561

	enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
			 SPRITE0_FLIP_DONE_INT_EN_VLV |
			 SPRITE1_FLIP_DONE_INT_EN_VLV);
	if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
		enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
	if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
		enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;

	return enable_mask;
}

562 563 564 565 566 567
void
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		     u32 status_mask)
{
	u32 enable_mask;

568
	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
569
		enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
570 571 572
							   status_mask);
	else
		enable_mask = status_mask << 16;
573 574 575 576 577 578 579 580 581
	__i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
}

void
i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		      u32 status_mask)
{
	u32 enable_mask;

582
	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
583
		enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
584 585 586
							   status_mask);
	else
		enable_mask = status_mask << 16;
587 588 589
	__i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
}

590
/**
591
 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
592
 * @dev_priv: i915 device private
593
 */
594
static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
595
{
596
	if (!dev_priv->opregion.asle || !IS_MOBILE(dev_priv))
597 598
		return;

599
	spin_lock_irq(&dev_priv->irq_lock);
600

601
	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
602
	if (INTEL_GEN(dev_priv) >= 4)
603
		i915_enable_pipestat(dev_priv, PIPE_A,
604
				     PIPE_LEGACY_BLC_EVENT_STATUS);
605

606
	spin_unlock_irq(&dev_priv->irq_lock);
607 608
}

609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658
/*
 * This timing diagram depicts the video signal in and
 * around the vertical blanking period.
 *
 * Assumptions about the fictitious mode used in this example:
 *  vblank_start >= 3
 *  vsync_start = vblank_start + 1
 *  vsync_end = vblank_start + 2
 *  vtotal = vblank_start + 3
 *
 *           start of vblank:
 *           latch double buffered registers
 *           increment frame counter (ctg+)
 *           generate start of vblank interrupt (gen4+)
 *           |
 *           |          frame start:
 *           |          generate frame start interrupt (aka. vblank interrupt) (gmch)
 *           |          may be shifted forward 1-3 extra lines via PIPECONF
 *           |          |
 *           |          |  start of vsync:
 *           |          |  generate vsync interrupt
 *           |          |  |
 * ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx
 *       .   \hs/   .      \hs/          \hs/          \hs/   .      \hs/
 * ----va---> <-----------------vb--------------------> <--------va-------------
 *       |          |       <----vs----->                     |
 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
 *       |          |                                         |
 *       last visible pixel                                   first visible pixel
 *                  |                                         increment frame counter (gen3/4)
 *                  pixel counter = vblank_start * htotal     pixel counter = 0 (gen3/4)
 *
 * x  = horizontal active
 * _  = horizontal blanking
 * hs = horizontal sync
 * va = vertical active
 * vb = vertical blanking
 * vs = vertical sync
 * vbs = vblank_start (number)
 *
 * Summary:
 * - most events happen at the start of horizontal sync
 * - frame start happens at the start of horizontal blank, 1-4 lines
 *   (depending on PIPECONF settings) after the start of vblank
 * - gen3/4 pixel and frame counter are synchronized with the start
 *   of horizontal active on the first line of vertical active
 */

659 660 661
/* Called from drm generic code, passed a 'crtc', which
 * we use as a pipe index
 */
662
static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
663
{
664
	struct drm_i915_private *dev_priv = to_i915(dev);
665
	i915_reg_t high_frame, low_frame;
666
	u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
667 668
	struct intel_crtc *intel_crtc =
		to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
669
	const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
670

671 672 673 674 675
	htotal = mode->crtc_htotal;
	hsync_start = mode->crtc_hsync_start;
	vbl_start = mode->crtc_vblank_start;
	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
		vbl_start = DIV_ROUND_UP(vbl_start, 2);
676

677 678 679 680 681 682
	/* Convert to pixel count */
	vbl_start *= htotal;

	/* Start of vblank event occurs at start of hsync */
	vbl_start -= htotal - hsync_start;

683 684
	high_frame = PIPEFRAME(pipe);
	low_frame = PIPEFRAMEPIXEL(pipe);
685

686 687 688 689 690 691
	/*
	 * High & low register fields aren't synchronized, so make sure
	 * we get a low value that's stable across two reads of the high
	 * register.
	 */
	do {
692
		high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
693
		low   = I915_READ(low_frame);
694
		high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
695 696
	} while (high1 != high2);

697
	high1 >>= PIPE_FRAME_HIGH_SHIFT;
698
	pixel = low & PIPE_PIXEL_MASK;
699
	low >>= PIPE_FRAME_LOW_SHIFT;
700 701 702 703 704 705

	/*
	 * The frame counter increments at beginning of active.
	 * Cook up a vblank counter by also checking the pixel
	 * counter against vblank start.
	 */
706
	return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
707 708
}

709
static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
710
{
711
	struct drm_i915_private *dev_priv = to_i915(dev);
712

713
	return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
714 715
}

716
/* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
717 718 719
static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
{
	struct drm_device *dev = crtc->base.dev;
720
	struct drm_i915_private *dev_priv = to_i915(dev);
721
	const struct drm_display_mode *mode = &crtc->base.hwmode;
722
	enum pipe pipe = crtc->pipe;
723
	int position, vtotal;
724

725
	vtotal = mode->crtc_vtotal;
726 727 728
	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
		vtotal /= 2;

729
	if (IS_GEN2(dev_priv))
730
		position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
731
	else
732
		position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
733

734 735 736 737 738 739 740 741 742 743 744 745
	/*
	 * On HSW, the DSL reg (0x70000) appears to return 0 if we
	 * read it just before the start of vblank.  So try it again
	 * so we don't accidentally end up spanning a vblank frame
	 * increment, causing the pipe_update_end() code to squak at us.
	 *
	 * The nature of this problem means we can't simply check the ISR
	 * bit and return the vblank start value; nor can we use the scanline
	 * debug register in the transcoder as it appears to have the same
	 * problem.  We may need to extend this to include other platforms,
	 * but so far testing only shows the problem on HSW.
	 */
746
	if (HAS_DDI(dev_priv) && !position) {
747 748 749 750 751 752 753 754 755 756 757 758 759
		int i, temp;

		for (i = 0; i < 100; i++) {
			udelay(1);
			temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) &
				DSL_LINEMASK_GEN3;
			if (temp != position) {
				position = temp;
				break;
			}
		}
	}

760
	/*
761 762
	 * See update_scanline_offset() for the details on the
	 * scanline_offset adjustment.
763
	 */
764
	return (position + crtc->scanline_offset) % vtotal;
765 766
}

767
static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
768
				    unsigned int flags, int *vpos, int *hpos,
769 770
				    ktime_t *stime, ktime_t *etime,
				    const struct drm_display_mode *mode)
771
{
772
	struct drm_i915_private *dev_priv = to_i915(dev);
773 774
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
775
	int position;
776
	int vbl_start, vbl_end, hsync_start, htotal, vtotal;
777 778
	bool in_vbl = true;
	int ret = 0;
779
	unsigned long irqflags;
780

781
	if (WARN_ON(!mode->crtc_clock)) {
782
		DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
783
				 "pipe %c\n", pipe_name(pipe));
784 785 786
		return 0;
	}

787
	htotal = mode->crtc_htotal;
788
	hsync_start = mode->crtc_hsync_start;
789 790 791
	vtotal = mode->crtc_vtotal;
	vbl_start = mode->crtc_vblank_start;
	vbl_end = mode->crtc_vblank_end;
792

793 794 795 796 797 798
	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
		vbl_start = DIV_ROUND_UP(vbl_start, 2);
		vbl_end /= 2;
		vtotal /= 2;
	}

799 800
	ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;

801 802 803 804 805 806
	/*
	 * Lock uncore.lock, as we will do multiple timing critical raw
	 * register reads, potentially with preemption disabled, so the
	 * following code must not block on uncore.lock.
	 */
	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
807

808 809 810 811 812 813
	/* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */

	/* Get optional system timestamp before query. */
	if (stime)
		*stime = ktime_get();

814
	if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
815 816 817
		/* No obvious pixelcount register. Only query vertical
		 * scanout position from Display scan line register.
		 */
818
		position = __intel_get_crtc_scanline(intel_crtc);
819 820 821 822 823
	} else {
		/* Have access to pixelcount since start of frame.
		 * We can split this into vertical and horizontal
		 * scanout position.
		 */
824
		position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
825

826 827 828 829
		/* convert to pixel counts */
		vbl_start *= htotal;
		vbl_end *= htotal;
		vtotal *= htotal;
830

831 832 833 834 835 836 837 838 839 840 841 842
		/*
		 * In interlaced modes, the pixel counter counts all pixels,
		 * so one field will have htotal more pixels. In order to avoid
		 * the reported position from jumping backwards when the pixel
		 * counter is beyond the length of the shorter field, just
		 * clamp the position the length of the shorter field. This
		 * matches how the scanline counter based position works since
		 * the scanline counter doesn't count the two half lines.
		 */
		if (position >= vtotal)
			position = vtotal - 1;

843 844 845 846 847 848 849 850 851 852
		/*
		 * Start of vblank interrupt is triggered at start of hsync,
		 * just prior to the first active line of vblank. However we
		 * consider lines to start at the leading edge of horizontal
		 * active. So, should we get here before we've crossed into
		 * the horizontal active of the first line in vblank, we would
		 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
		 * always add htotal-hsync_start to the current pixel position.
		 */
		position = (position + htotal - hsync_start) % vtotal;
853 854
	}

855 856 857 858 859 860 861 862
	/* Get optional system timestamp after query. */
	if (etime)
		*etime = ktime_get();

	/* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */

	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

863 864 865 866 867 868 869 870 871 872 873 874
	in_vbl = position >= vbl_start && position < vbl_end;

	/*
	 * While in vblank, position will be negative
	 * counting up towards 0 at vbl_end. And outside
	 * vblank, position will be positive counting
	 * up since vbl_end.
	 */
	if (position >= vbl_start)
		position -= vbl_end;
	else
		position += vtotal - vbl_end;
875

876
	if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
877 878 879 880 881 882
		*vpos = position;
		*hpos = 0;
	} else {
		*vpos = position / htotal;
		*hpos = position - (*vpos * htotal);
	}
883 884 885

	/* In vblank? */
	if (in_vbl)
886
		ret |= DRM_SCANOUTPOS_IN_VBLANK;
887 888 889 890

	return ret;
}

891 892
int intel_get_crtc_scanline(struct intel_crtc *crtc)
{
893
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
894 895 896 897 898 899 900 901 902 903
	unsigned long irqflags;
	int position;

	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
	position = __intel_get_crtc_scanline(crtc);
	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

	return position;
}

904
static int i915_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe,
905 906 907 908
			      int *max_error,
			      struct timeval *vblank_time,
			      unsigned flags)
{
909
	struct drm_crtc *crtc;
910

911 912
	if (pipe >= INTEL_INFO(dev)->num_pipes) {
		DRM_ERROR("Invalid crtc %u\n", pipe);
913 914 915 916
		return -EINVAL;
	}

	/* Get drm_crtc to timestamp: */
917 918
	crtc = intel_get_crtc_for_pipe(dev, pipe);
	if (crtc == NULL) {
919
		DRM_ERROR("Invalid crtc %u\n", pipe);
920 921 922
		return -EINVAL;
	}

923
	if (!crtc->hwmode.crtc_clock) {
924
		DRM_DEBUG_KMS("crtc %u is disabled\n", pipe);
925 926
		return -EBUSY;
	}
927 928

	/* Helper routine in DRM core does all the work: */
929 930
	return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
						     vblank_time, flags,
931
						     &crtc->hwmode);
932 933
}

934
static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv)
935
{
936
	u32 busy_up, busy_down, max_avg, min_avg;
937 938
	u8 new_delay;

939
	spin_lock(&mchdev_lock);
940

941 942
	I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));

943
	new_delay = dev_priv->ips.cur_delay;
944

945
	I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
946 947
	busy_up = I915_READ(RCPREVBSYTUPAVG);
	busy_down = I915_READ(RCPREVBSYTDNAVG);
948 949 950 951
	max_avg = I915_READ(RCBMAXAVG);
	min_avg = I915_READ(RCBMINAVG);

	/* Handle RCS change request from hw */
952
	if (busy_up > max_avg) {
953 954 955 956
		if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
			new_delay = dev_priv->ips.cur_delay - 1;
		if (new_delay < dev_priv->ips.max_delay)
			new_delay = dev_priv->ips.max_delay;
957
	} else if (busy_down < min_avg) {
958 959 960 961
		if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
			new_delay = dev_priv->ips.cur_delay + 1;
		if (new_delay > dev_priv->ips.min_delay)
			new_delay = dev_priv->ips.min_delay;
962 963
	}

964
	if (ironlake_set_drps(dev_priv, new_delay))
965
		dev_priv->ips.cur_delay = new_delay;
966

967
	spin_unlock(&mchdev_lock);
968

969 970 971
	return;
}

972
static void notify_ring(struct intel_engine_cs *engine)
973
{
974
	smp_store_mb(engine->breadcrumbs.irq_posted, true);
975
	if (intel_engine_wakeup(engine))
976
		trace_i915_gem_request_notify(engine);
977 978
}

979 980
static void vlv_c0_read(struct drm_i915_private *dev_priv,
			struct intel_rps_ei *ei)
981
{
982 983 984 985
	ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
	ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
	ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
}
986

987 988 989 990 991 992
static bool vlv_c0_above(struct drm_i915_private *dev_priv,
			 const struct intel_rps_ei *old,
			 const struct intel_rps_ei *now,
			 int threshold)
{
	u64 time, c0;
993
	unsigned int mul = 100;
994

995 996
	if (old->cz_clock == 0)
		return false;
997

998 999 1000
	if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
		mul <<= 8;

1001
	time = now->cz_clock - old->cz_clock;
1002
	time *= threshold * dev_priv->czclk_freq;
1003

1004 1005 1006
	/* Workload can be split between render + media, e.g. SwapBuffers
	 * being blitted in X after being rendered in mesa. To account for
	 * this we need to combine both engines into our activity counter.
1007
	 */
1008 1009
	c0 = now->render_c0 - old->render_c0;
	c0 += now->media_c0 - old->media_c0;
1010
	c0 *= mul * VLV_CZ_CLOCK_TO_MILLI_SEC;
1011

1012
	return c0 >= time;
1013 1014
}

1015
void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1016
{
1017 1018 1019
	vlv_c0_read(dev_priv, &dev_priv->rps.down_ei);
	dev_priv->rps.up_ei = dev_priv->rps.down_ei;
}
1020

1021 1022 1023 1024
static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
{
	struct intel_rps_ei now;
	u32 events = 0;
1025

1026
	if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0)
1027
		return 0;
1028

1029 1030 1031
	vlv_c0_read(dev_priv, &now);
	if (now.cz_clock == 0)
		return 0;
1032

1033 1034 1035
	if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
		if (!vlv_c0_above(dev_priv,
				  &dev_priv->rps.down_ei, &now,
1036
				  dev_priv->rps.down_threshold))
1037 1038 1039
			events |= GEN6_PM_RP_DOWN_THRESHOLD;
		dev_priv->rps.down_ei = now;
	}
1040

1041 1042 1043
	if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
		if (vlv_c0_above(dev_priv,
				 &dev_priv->rps.up_ei, &now,
1044
				 dev_priv->rps.up_threshold))
1045 1046
			events |= GEN6_PM_RP_UP_THRESHOLD;
		dev_priv->rps.up_ei = now;
1047 1048
	}

1049
	return events;
1050 1051
}

1052 1053
static bool any_waiters(struct drm_i915_private *dev_priv)
{
1054
	struct intel_engine_cs *engine;
1055

1056
	for_each_engine(engine, dev_priv)
1057
		if (intel_engine_has_waiter(engine))
1058 1059 1060 1061 1062
			return true;

	return false;
}

1063
static void gen6_pm_rps_work(struct work_struct *work)
1064
{
1065 1066
	struct drm_i915_private *dev_priv =
		container_of(work, struct drm_i915_private, rps.work);
1067 1068
	bool client_boost;
	int new_delay, adj, min, max;
P
Paulo Zanoni 已提交
1069
	u32 pm_iir;
1070

1071
	spin_lock_irq(&dev_priv->irq_lock);
I
Imre Deak 已提交
1072 1073 1074 1075 1076
	/* Speed up work cancelation during disabling rps interrupts. */
	if (!dev_priv->rps.interrupts_enabled) {
		spin_unlock_irq(&dev_priv->irq_lock);
		return;
	}
1077

1078 1079
	pm_iir = dev_priv->rps.pm_iir;
	dev_priv->rps.pm_iir = 0;
1080 1081
	/* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
	gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1082 1083
	client_boost = dev_priv->rps.client_boost;
	dev_priv->rps.client_boost = false;
1084
	spin_unlock_irq(&dev_priv->irq_lock);
1085

1086
	/* Make sure we didn't queue anything we're not going to process. */
1087
	WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1088

1089
	if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1090
		return;
1091

1092
	mutex_lock(&dev_priv->rps.hw_lock);
1093

1094 1095
	pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);

1096
	adj = dev_priv->rps.last_adj;
1097
	new_delay = dev_priv->rps.cur_freq;
1098 1099
	min = dev_priv->rps.min_freq_softlimit;
	max = dev_priv->rps.max_freq_softlimit;
1100 1101 1102 1103
	if (client_boost || any_waiters(dev_priv))
		max = dev_priv->rps.max_freq;
	if (client_boost && new_delay < dev_priv->rps.boost_freq) {
		new_delay = dev_priv->rps.boost_freq;
1104 1105
		adj = 0;
	} else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1106 1107
		if (adj > 0)
			adj *= 2;
1108 1109
		else /* CHV needs even encode values */
			adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1110 1111 1112 1113
		/*
		 * For better performance, jump directly
		 * to RPe if we're below it.
		 */
1114
		if (new_delay < dev_priv->rps.efficient_freq - adj) {
1115
			new_delay = dev_priv->rps.efficient_freq;
1116 1117
			adj = 0;
		}
1118
	} else if (client_boost || any_waiters(dev_priv)) {
1119
		adj = 0;
1120
	} else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1121 1122
		if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
			new_delay = dev_priv->rps.efficient_freq;
1123
		else
1124
			new_delay = dev_priv->rps.min_freq_softlimit;
1125 1126 1127 1128
		adj = 0;
	} else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
		if (adj < 0)
			adj *= 2;
1129 1130
		else /* CHV needs even encode values */
			adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1131
	} else { /* unknown event */
1132
		adj = 0;
1133
	}
1134

1135 1136
	dev_priv->rps.last_adj = adj;

1137 1138 1139
	/* sysfs frequency interfaces may have snuck in while servicing the
	 * interrupt
	 */
1140
	new_delay += adj;
1141
	new_delay = clamp_t(int, new_delay, min, max);
1142

1143
	intel_set_rps(dev_priv, new_delay);
1144

1145
	mutex_unlock(&dev_priv->rps.hw_lock);
1146 1147
}

1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159

/**
 * ivybridge_parity_work - Workqueue called when a parity error interrupt
 * occurred.
 * @work: workqueue struct
 *
 * Doesn't actually do anything except notify userspace. As a consequence of
 * this event, userspace should try to remap the bad rows since statistically
 * it is likely the same row is more likely to go bad again.
 */
static void ivybridge_parity_work(struct work_struct *work)
{
1160 1161
	struct drm_i915_private *dev_priv =
		container_of(work, struct drm_i915_private, l3_parity.error_work);
1162
	u32 error_status, row, bank, subbank;
1163
	char *parity_event[6];
1164
	uint32_t misccpctl;
1165
	uint8_t slice = 0;
1166 1167 1168 1169 1170

	/* We must turn off DOP level clock gating to access the L3 registers.
	 * In order to prevent a get/put style interface, acquire struct mutex
	 * any time we access those registers.
	 */
1171
	mutex_lock(&dev_priv->drm.struct_mutex);
1172

1173 1174 1175 1176
	/* If we've screwed up tracking, just let the interrupt fire again */
	if (WARN_ON(!dev_priv->l3_parity.which_slice))
		goto out;

1177 1178 1179 1180
	misccpctl = I915_READ(GEN7_MISCCPCTL);
	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
	POSTING_READ(GEN7_MISCCPCTL);

1181
	while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1182
		i915_reg_t reg;
1183

1184
		slice--;
1185
		if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv)))
1186
			break;
1187

1188
		dev_priv->l3_parity.which_slice &= ~(1<<slice);
1189

1190
		reg = GEN7_L3CDERRST1(slice);
1191

1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206
		error_status = I915_READ(reg);
		row = GEN7_PARITY_ERROR_ROW(error_status);
		bank = GEN7_PARITY_ERROR_BANK(error_status);
		subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);

		I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
		POSTING_READ(reg);

		parity_event[0] = I915_L3_PARITY_UEVENT "=1";
		parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
		parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
		parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
		parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
		parity_event[5] = NULL;

1207
		kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,
1208
				   KOBJ_CHANGE, parity_event);
1209

1210 1211
		DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
			  slice, row, bank, subbank);
1212

1213 1214 1215 1216 1217
		kfree(parity_event[4]);
		kfree(parity_event[3]);
		kfree(parity_event[2]);
		kfree(parity_event[1]);
	}
1218

1219
	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1220

1221 1222
out:
	WARN_ON(dev_priv->l3_parity.which_slice);
1223
	spin_lock_irq(&dev_priv->irq_lock);
1224
	gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1225
	spin_unlock_irq(&dev_priv->irq_lock);
1226

1227
	mutex_unlock(&dev_priv->drm.struct_mutex);
1228 1229
}

1230 1231
static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv,
					       u32 iir)
1232
{
1233
	if (!HAS_L3_DPF(dev_priv))
1234 1235
		return;

1236
	spin_lock(&dev_priv->irq_lock);
1237
	gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1238
	spin_unlock(&dev_priv->irq_lock);
1239

1240
	iir &= GT_PARITY_ERROR(dev_priv);
1241 1242 1243 1244 1245 1246
	if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
		dev_priv->l3_parity.which_slice |= 1 << 1;

	if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
		dev_priv->l3_parity.which_slice |= 1 << 0;

1247
	queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1248 1249
}

1250
static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv,
1251 1252
			       u32 gt_iir)
{
1253
	if (gt_iir & GT_RENDER_USER_INTERRUPT)
1254
		notify_ring(&dev_priv->engine[RCS]);
1255
	if (gt_iir & ILK_BSD_USER_INTERRUPT)
1256
		notify_ring(&dev_priv->engine[VCS]);
1257 1258
}

1259
static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
1260 1261
			       u32 gt_iir)
{
1262
	if (gt_iir & GT_RENDER_USER_INTERRUPT)
1263
		notify_ring(&dev_priv->engine[RCS]);
1264
	if (gt_iir & GT_BSD_USER_INTERRUPT)
1265
		notify_ring(&dev_priv->engine[VCS]);
1266
	if (gt_iir & GT_BLT_USER_INTERRUPT)
1267
		notify_ring(&dev_priv->engine[BCS]);
1268

1269 1270
	if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
		      GT_BSD_CS_ERROR_INTERRUPT |
1271 1272
		      GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
		DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1273

1274 1275
	if (gt_iir & GT_PARITY_ERROR(dev_priv))
		ivybridge_parity_error_irq_handler(dev_priv, gt_iir);
1276 1277
}

1278
static __always_inline void
1279
gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
1280 1281
{
	if (iir & (GT_RENDER_USER_INTERRUPT << test_shift))
1282
		notify_ring(engine);
1283
	if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift))
1284
		tasklet_schedule(&engine->irq_tasklet);
1285 1286
}

1287 1288 1289
static irqreturn_t gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
				   u32 master_ctl,
				   u32 gt_iir[4])
1290 1291 1292 1293
{
	irqreturn_t ret = IRQ_NONE;

	if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1294 1295 1296
		gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0));
		if (gt_iir[0]) {
			I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir[0]);
1297 1298 1299 1300 1301
			ret = IRQ_HANDLED;
		} else
			DRM_ERROR("The master control interrupt lied (GT0)!\n");
	}

1302
	if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1303 1304 1305
		gt_iir[1] = I915_READ_FW(GEN8_GT_IIR(1));
		if (gt_iir[1]) {
			I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir[1]);
1306
			ret = IRQ_HANDLED;
1307
		} else
1308
			DRM_ERROR("The master control interrupt lied (GT1)!\n");
1309 1310
	}

1311
	if (master_ctl & GEN8_GT_VECS_IRQ) {
1312 1313 1314
		gt_iir[3] = I915_READ_FW(GEN8_GT_IIR(3));
		if (gt_iir[3]) {
			I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir[3]);
1315 1316 1317 1318 1319
			ret = IRQ_HANDLED;
		} else
			DRM_ERROR("The master control interrupt lied (GT3)!\n");
	}

1320
	if (master_ctl & GEN8_GT_PM_IRQ) {
1321 1322
		gt_iir[2] = I915_READ_FW(GEN8_GT_IIR(2));
		if (gt_iir[2] & dev_priv->pm_rps_events) {
1323
			I915_WRITE_FW(GEN8_GT_IIR(2),
1324
				      gt_iir[2] & dev_priv->pm_rps_events);
1325
			ret = IRQ_HANDLED;
1326 1327 1328 1329
		} else
			DRM_ERROR("The master control interrupt lied (PM)!\n");
	}

1330 1331 1332
	return ret;
}

1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357
static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
				u32 gt_iir[4])
{
	if (gt_iir[0]) {
		gen8_cs_irq_handler(&dev_priv->engine[RCS],
				    gt_iir[0], GEN8_RCS_IRQ_SHIFT);
		gen8_cs_irq_handler(&dev_priv->engine[BCS],
				    gt_iir[0], GEN8_BCS_IRQ_SHIFT);
	}

	if (gt_iir[1]) {
		gen8_cs_irq_handler(&dev_priv->engine[VCS],
				    gt_iir[1], GEN8_VCS1_IRQ_SHIFT);
		gen8_cs_irq_handler(&dev_priv->engine[VCS2],
				    gt_iir[1], GEN8_VCS2_IRQ_SHIFT);
	}

	if (gt_iir[3])
		gen8_cs_irq_handler(&dev_priv->engine[VECS],
				    gt_iir[3], GEN8_VECS_IRQ_SHIFT);

	if (gt_iir[2] & dev_priv->pm_rps_events)
		gen6_rps_irq_handler(dev_priv, gt_iir[2]);
}

1358 1359 1360 1361
static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
{
	switch (port) {
	case PORT_A:
1362
		return val & PORTA_HOTPLUG_LONG_DETECT;
1363 1364 1365 1366 1367 1368 1369 1370 1371
	case PORT_B:
		return val & PORTB_HOTPLUG_LONG_DETECT;
	case PORT_C:
		return val & PORTC_HOTPLUG_LONG_DETECT;
	default:
		return false;
	}
}

1372 1373 1374 1375 1376 1377 1378 1379 1380 1381
static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
{
	switch (port) {
	case PORT_E:
		return val & PORTE_HOTPLUG_LONG_DETECT;
	default:
		return false;
	}
}

1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397
static bool spt_port_hotplug_long_detect(enum port port, u32 val)
{
	switch (port) {
	case PORT_A:
		return val & PORTA_HOTPLUG_LONG_DETECT;
	case PORT_B:
		return val & PORTB_HOTPLUG_LONG_DETECT;
	case PORT_C:
		return val & PORTC_HOTPLUG_LONG_DETECT;
	case PORT_D:
		return val & PORTD_HOTPLUG_LONG_DETECT;
	default:
		return false;
	}
}

1398 1399 1400 1401 1402 1403 1404 1405 1406 1407
static bool ilk_port_hotplug_long_detect(enum port port, u32 val)
{
	switch (port) {
	case PORT_A:
		return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
	default:
		return false;
	}
}

1408
static bool pch_port_hotplug_long_detect(enum port port, u32 val)
1409 1410 1411
{
	switch (port) {
	case PORT_B:
1412
		return val & PORTB_HOTPLUG_LONG_DETECT;
1413
	case PORT_C:
1414
		return val & PORTC_HOTPLUG_LONG_DETECT;
1415
	case PORT_D:
1416 1417 1418
		return val & PORTD_HOTPLUG_LONG_DETECT;
	default:
		return false;
1419 1420 1421
	}
}

1422
static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
1423 1424 1425
{
	switch (port) {
	case PORT_B:
1426
		return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1427
	case PORT_C:
1428
		return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1429
	case PORT_D:
1430 1431 1432
		return val & PORTD_HOTPLUG_INT_LONG_PULSE;
	default:
		return false;
1433 1434 1435
	}
}

1436 1437 1438 1439 1440 1441 1442
/*
 * Get a bit mask of pins that have triggered, and which ones may be long.
 * This can be called multiple times with the same masks to accumulate
 * hotplug detection results from several registers.
 *
 * Note that the caller is expected to zero out the masks initially.
 */
1443
static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
1444
			     u32 hotplug_trigger, u32 dig_hotplug_reg,
1445 1446
			     const u32 hpd[HPD_NUM_PINS],
			     bool long_pulse_detect(enum port port, u32 val))
1447
{
1448
	enum port port;
1449 1450 1451
	int i;

	for_each_hpd_pin(i) {
1452 1453
		if ((hpd[i] & hotplug_trigger) == 0)
			continue;
1454

1455 1456
		*pin_mask |= BIT(i);

1457 1458 1459
		if (!intel_hpd_pin_to_port(i, &port))
			continue;

1460
		if (long_pulse_detect(port, dig_hotplug_reg))
1461
			*long_mask |= BIT(i);
1462 1463 1464 1465 1466 1467 1468
	}

	DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
			 hotplug_trigger, dig_hotplug_reg, *pin_mask);

}

1469
static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1470
{
1471
	wake_up_all(&dev_priv->gmbus_wait_queue);
1472 1473
}

1474
static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1475
{
1476
	wake_up_all(&dev_priv->gmbus_wait_queue);
1477 1478
}

1479
#if defined(CONFIG_DEBUG_FS)
1480 1481
static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
					 enum pipe pipe,
1482 1483 1484
					 uint32_t crc0, uint32_t crc1,
					 uint32_t crc2, uint32_t crc3,
					 uint32_t crc4)
1485 1486 1487
{
	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
	struct intel_pipe_crc_entry *entry;
1488
	int head, tail;
1489

1490 1491
	spin_lock(&pipe_crc->lock);

1492
	if (!pipe_crc->entries) {
1493
		spin_unlock(&pipe_crc->lock);
1494
		DRM_DEBUG_KMS("spurious interrupt\n");
1495 1496 1497
		return;
	}

1498 1499
	head = pipe_crc->head;
	tail = pipe_crc->tail;
1500 1501

	if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1502
		spin_unlock(&pipe_crc->lock);
1503 1504 1505 1506 1507
		DRM_ERROR("CRC buffer overflowing\n");
		return;
	}

	entry = &pipe_crc->entries[head];
1508

1509
	entry->frame = dev_priv->drm.driver->get_vblank_counter(&dev_priv->drm,
1510
								 pipe);
1511 1512 1513 1514 1515
	entry->crc[0] = crc0;
	entry->crc[1] = crc1;
	entry->crc[2] = crc2;
	entry->crc[3] = crc3;
	entry->crc[4] = crc4;
1516 1517

	head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1518 1519 1520
	pipe_crc->head = head;

	spin_unlock(&pipe_crc->lock);
1521 1522

	wake_up_interruptible(&pipe_crc->wq);
1523
}
1524 1525
#else
static inline void
1526 1527
display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
			     enum pipe pipe,
1528 1529 1530 1531 1532
			     uint32_t crc0, uint32_t crc1,
			     uint32_t crc2, uint32_t crc3,
			     uint32_t crc4) {}
#endif

1533

1534 1535
static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
				     enum pipe pipe)
D
Daniel Vetter 已提交
1536
{
1537
	display_pipe_crc_irq_handler(dev_priv, pipe,
1538 1539
				     I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
				     0, 0, 0, 0);
D
Daniel Vetter 已提交
1540 1541
}

1542 1543
static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
				     enum pipe pipe)
1544
{
1545
	display_pipe_crc_irq_handler(dev_priv, pipe,
1546 1547 1548 1549 1550
				     I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
				     I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
				     I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
				     I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
				     I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1551
}
1552

1553 1554
static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
				      enum pipe pipe)
1555
{
1556 1557
	uint32_t res1, res2;

1558
	if (INTEL_GEN(dev_priv) >= 3)
1559 1560 1561 1562
		res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
	else
		res1 = 0;

1563
	if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1564 1565 1566
		res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
	else
		res2 = 0;
1567

1568
	display_pipe_crc_irq_handler(dev_priv, pipe,
1569 1570 1571 1572
				     I915_READ(PIPE_CRC_RES_RED(pipe)),
				     I915_READ(PIPE_CRC_RES_GREEN(pipe)),
				     I915_READ(PIPE_CRC_RES_BLUE(pipe)),
				     res1, res2);
1573
}
1574

1575 1576 1577 1578
/* The RPS events need forcewake, so we add them to a work queue and mask their
 * IMR bits until the work is done. Other interrupts can be processed without
 * the work queue. */
static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1579
{
1580
	if (pm_iir & dev_priv->pm_rps_events) {
1581
		spin_lock(&dev_priv->irq_lock);
1582
		gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
I
Imre Deak 已提交
1583 1584
		if (dev_priv->rps.interrupts_enabled) {
			dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1585
			schedule_work(&dev_priv->rps.work);
I
Imre Deak 已提交
1586
		}
1587
		spin_unlock(&dev_priv->irq_lock);
1588 1589
	}

1590 1591 1592
	if (INTEL_INFO(dev_priv)->gen >= 8)
		return;

1593
	if (HAS_VEBOX(dev_priv)) {
1594
		if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1595
			notify_ring(&dev_priv->engine[VECS]);
B
Ben Widawsky 已提交
1596

1597 1598
		if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
			DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
B
Ben Widawsky 已提交
1599
	}
1600 1601
}

1602
static bool intel_pipe_handle_vblank(struct drm_i915_private *dev_priv,
1603
				     enum pipe pipe)
1604
{
1605 1606
	bool ret;

1607
	ret = drm_handle_vblank(&dev_priv->drm, pipe);
1608
	if (ret)
1609
		intel_finish_page_flip_mmio(dev_priv, pipe);
1610 1611

	return ret;
1612 1613
}

1614 1615
static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
					u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1616 1617 1618
{
	int pipe;

1619
	spin_lock(&dev_priv->irq_lock);
1620 1621 1622 1623 1624 1625

	if (!dev_priv->display_irqs_enabled) {
		spin_unlock(&dev_priv->irq_lock);
		return;
	}

1626
	for_each_pipe(dev_priv, pipe) {
1627
		i915_reg_t reg;
1628
		u32 mask, iir_bit = 0;
1629

1630 1631 1632 1633 1634 1635 1636
		/*
		 * PIPESTAT bits get signalled even when the interrupt is
		 * disabled with the mask bits, and some of the status bits do
		 * not generate interrupts at all (like the underrun bit). Hence
		 * we need to be careful that we only handle what we want to
		 * handle.
		 */
1637 1638 1639

		/* fifo underruns are filterered in the underrun handler. */
		mask = PIPE_FIFO_UNDERRUN_STATUS;
1640 1641 1642 1643 1644 1645 1646 1647

		switch (pipe) {
		case PIPE_A:
			iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
			break;
		case PIPE_B:
			iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
			break;
1648 1649 1650
		case PIPE_C:
			iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
			break;
1651 1652 1653 1654 1655
		}
		if (iir & iir_bit)
			mask |= dev_priv->pipestat_irq_mask[pipe];

		if (!mask)
1656 1657 1658
			continue;

		reg = PIPESTAT(pipe);
1659 1660
		mask |= PIPESTAT_INT_ENABLE_MASK;
		pipe_stats[pipe] = I915_READ(reg) & mask;
1661 1662 1663 1664

		/*
		 * Clear the PIPE*STAT regs before the IIR
		 */
1665 1666
		if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
					PIPESTAT_INT_STATUS_MASK))
1667 1668
			I915_WRITE(reg, pipe_stats[pipe]);
	}
1669
	spin_unlock(&dev_priv->irq_lock);
1670 1671
}

1672
static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1673 1674 1675
					    u32 pipe_stats[I915_MAX_PIPES])
{
	enum pipe pipe;
1676

1677
	for_each_pipe(dev_priv, pipe) {
1678 1679 1680
		if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
		    intel_pipe_handle_vblank(dev_priv, pipe))
			intel_check_page_flip(dev_priv, pipe);
1681

1682
		if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)
1683
			intel_finish_page_flip_cs(dev_priv, pipe);
1684 1685

		if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1686
			i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1687

1688 1689
		if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1690 1691 1692
	}

	if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1693
		gmbus_irq_handler(dev_priv);
1694 1695
}

1696
static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
1697 1698 1699
{
	u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);

1700 1701
	if (hotplug_status)
		I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1702

1703 1704 1705
	return hotplug_status;
}

1706
static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1707 1708 1709
				 u32 hotplug_status)
{
	u32 pin_mask = 0, long_mask = 0;
1710

1711 1712
	if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
	    IS_CHERRYVIEW(dev_priv)) {
1713
		u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1714

1715 1716 1717 1718 1719
		if (hotplug_trigger) {
			intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
					   hotplug_trigger, hpd_status_g4x,
					   i9xx_port_hotplug_long_detect);

1720
			intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1721
		}
1722 1723

		if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1724
			dp_aux_irq_handler(dev_priv);
1725 1726
	} else {
		u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1727

1728 1729
		if (hotplug_trigger) {
			intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1730
					   hotplug_trigger, hpd_status_i915,
1731
					   i9xx_port_hotplug_long_detect);
1732
			intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1733
		}
1734
	}
1735 1736
}

1737
static irqreturn_t valleyview_irq_handler(int irq, void *arg)
J
Jesse Barnes 已提交
1738
{
1739
	struct drm_device *dev = arg;
1740
	struct drm_i915_private *dev_priv = to_i915(dev);
J
Jesse Barnes 已提交
1741 1742
	irqreturn_t ret = IRQ_NONE;

1743 1744 1745
	if (!intel_irqs_enabled(dev_priv))
		return IRQ_NONE;

1746 1747 1748
	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
	disable_rpm_wakeref_asserts(dev_priv);

1749
	do {
1750
		u32 iir, gt_iir, pm_iir;
1751
		u32 pipe_stats[I915_MAX_PIPES] = {};
1752
		u32 hotplug_status = 0;
1753
		u32 ier = 0;
1754

J
Jesse Barnes 已提交
1755 1756
		gt_iir = I915_READ(GTIIR);
		pm_iir = I915_READ(GEN6_PMIIR);
1757
		iir = I915_READ(VLV_IIR);
J
Jesse Barnes 已提交
1758 1759

		if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1760
			break;
J
Jesse Barnes 已提交
1761 1762 1763

		ret = IRQ_HANDLED;

1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776
		/*
		 * Theory on interrupt generation, based on empirical evidence:
		 *
		 * x = ((VLV_IIR & VLV_IER) ||
		 *      (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
		 *       (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
		 *
		 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
		 * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
		 * guarantee the CPU interrupt will be raised again even if we
		 * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
		 * bits this time around.
		 */
1777
		I915_WRITE(VLV_MASTER_IER, 0);
1778 1779
		ier = I915_READ(VLV_IER);
		I915_WRITE(VLV_IER, 0);
1780 1781 1782 1783 1784 1785

		if (gt_iir)
			I915_WRITE(GTIIR, gt_iir);
		if (pm_iir)
			I915_WRITE(GEN6_PMIIR, pm_iir);

1786
		if (iir & I915_DISPLAY_PORT_INTERRUPT)
1787
			hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1788

1789 1790
		/* Call regardless, as some status bits might not be
		 * signalled in iir */
1791
		valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1792 1793 1794 1795 1796 1797 1798

		/*
		 * VLV_IIR is single buffered, and reflects the level
		 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
		 */
		if (iir)
			I915_WRITE(VLV_IIR, iir);
1799

1800
		I915_WRITE(VLV_IER, ier);
1801 1802
		I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
		POSTING_READ(VLV_MASTER_IER);
1803

1804
		if (gt_iir)
1805
			snb_gt_irq_handler(dev_priv, gt_iir);
1806 1807 1808
		if (pm_iir)
			gen6_rps_irq_handler(dev_priv, pm_iir);

1809
		if (hotplug_status)
1810
			i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1811

1812
		valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1813
	} while (0);
J
Jesse Barnes 已提交
1814

1815 1816
	enable_rpm_wakeref_asserts(dev_priv);

J
Jesse Barnes 已提交
1817 1818 1819
	return ret;
}

1820 1821
static irqreturn_t cherryview_irq_handler(int irq, void *arg)
{
1822
	struct drm_device *dev = arg;
1823
	struct drm_i915_private *dev_priv = to_i915(dev);
1824 1825
	irqreturn_t ret = IRQ_NONE;

1826 1827 1828
	if (!intel_irqs_enabled(dev_priv))
		return IRQ_NONE;

1829 1830 1831
	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
	disable_rpm_wakeref_asserts(dev_priv);

1832
	do {
1833
		u32 master_ctl, iir;
1834
		u32 gt_iir[4] = {};
1835
		u32 pipe_stats[I915_MAX_PIPES] = {};
1836
		u32 hotplug_status = 0;
1837 1838
		u32 ier = 0;

1839 1840
		master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
		iir = I915_READ(VLV_IIR);
1841

1842 1843
		if (master_ctl == 0 && iir == 0)
			break;
1844

1845 1846
		ret = IRQ_HANDLED;

1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859
		/*
		 * Theory on interrupt generation, based on empirical evidence:
		 *
		 * x = ((VLV_IIR & VLV_IER) ||
		 *      ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
		 *       (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
		 *
		 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
		 * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
		 * guarantee the CPU interrupt will be raised again even if we
		 * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
		 * bits this time around.
		 */
1860
		I915_WRITE(GEN8_MASTER_IRQ, 0);
1861 1862
		ier = I915_READ(VLV_IER);
		I915_WRITE(VLV_IER, 0);
1863

1864
		gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
1865

1866
		if (iir & I915_DISPLAY_PORT_INTERRUPT)
1867
			hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1868

1869 1870
		/* Call regardless, as some status bits might not be
		 * signalled in iir */
1871
		valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1872

1873 1874 1875 1876 1877 1878 1879
		/*
		 * VLV_IIR is single buffered, and reflects the level
		 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
		 */
		if (iir)
			I915_WRITE(VLV_IIR, iir);

1880
		I915_WRITE(VLV_IER, ier);
1881
		I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
1882
		POSTING_READ(GEN8_MASTER_IRQ);
1883

1884 1885
		gen8_gt_irq_handler(dev_priv, gt_iir);

1886
		if (hotplug_status)
1887
			i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1888

1889
		valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1890
	} while (0);
1891

1892 1893
	enable_rpm_wakeref_asserts(dev_priv);

1894 1895 1896
	return ret;
}

1897 1898
static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
				u32 hotplug_trigger,
1899 1900 1901 1902
				const u32 hpd[HPD_NUM_PINS])
{
	u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;

1903 1904 1905 1906 1907 1908
	/*
	 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
	 * unless we touch the hotplug register, even if hotplug_trigger is
	 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
	 * errors.
	 */
1909
	dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1910 1911 1912 1913 1914 1915 1916 1917
	if (!hotplug_trigger) {
		u32 mask = PORTA_HOTPLUG_STATUS_MASK |
			PORTD_HOTPLUG_STATUS_MASK |
			PORTC_HOTPLUG_STATUS_MASK |
			PORTB_HOTPLUG_STATUS_MASK;
		dig_hotplug_reg &= ~mask;
	}

1918
	I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1919 1920
	if (!hotplug_trigger)
		return;
1921 1922 1923 1924 1925

	intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
			   dig_hotplug_reg, hpd,
			   pch_port_hotplug_long_detect);

1926
	intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1927 1928
}

1929
static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1930
{
1931
	int pipe;
1932
	u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1933

1934
	ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx);
1935

1936 1937 1938
	if (pch_iir & SDE_AUDIO_POWER_MASK) {
		int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
			       SDE_AUDIO_POWER_SHIFT);
1939
		DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1940 1941
				 port_name(port));
	}
1942

1943
	if (pch_iir & SDE_AUX_MASK)
1944
		dp_aux_irq_handler(dev_priv);
1945

1946
	if (pch_iir & SDE_GMBUS)
1947
		gmbus_irq_handler(dev_priv);
1948 1949 1950 1951 1952 1953 1954 1955 1956 1957

	if (pch_iir & SDE_AUDIO_HDCP_MASK)
		DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");

	if (pch_iir & SDE_AUDIO_TRANS_MASK)
		DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");

	if (pch_iir & SDE_POISON)
		DRM_ERROR("PCH poison interrupt\n");

1958
	if (pch_iir & SDE_FDI_MASK)
1959
		for_each_pipe(dev_priv, pipe)
1960 1961 1962
			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
					 pipe_name(pipe),
					 I915_READ(FDI_RX_IIR(pipe)));
1963 1964 1965 1966 1967 1968 1969 1970

	if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
		DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");

	if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
		DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");

	if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1971
		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
1972 1973

	if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1974
		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
1975 1976
}

1977
static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
1978 1979
{
	u32 err_int = I915_READ(GEN7_ERR_INT);
D
Daniel Vetter 已提交
1980
	enum pipe pipe;
1981

1982 1983 1984
	if (err_int & ERR_INT_POISON)
		DRM_ERROR("Poison interrupt\n");

1985
	for_each_pipe(dev_priv, pipe) {
1986 1987
		if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1988

D
Daniel Vetter 已提交
1989
		if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1990 1991
			if (IS_IVYBRIDGE(dev_priv))
				ivb_pipe_crc_irq_handler(dev_priv, pipe);
D
Daniel Vetter 已提交
1992
			else
1993
				hsw_pipe_crc_irq_handler(dev_priv, pipe);
D
Daniel Vetter 已提交
1994 1995
		}
	}
1996

1997 1998 1999
	I915_WRITE(GEN7_ERR_INT, err_int);
}

2000
static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
2001 2002 2003
{
	u32 serr_int = I915_READ(SERR_INT);

2004 2005 2006
	if (serr_int & SERR_INT_POISON)
		DRM_ERROR("PCH poison interrupt\n");

2007
	if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2008
		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2009 2010

	if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2011
		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2012 2013

	if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2014
		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
2015 2016

	I915_WRITE(SERR_INT, serr_int);
2017 2018
}

2019
static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2020 2021
{
	int pipe;
2022
	u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2023

2024
	ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt);
2025

2026 2027 2028 2029 2030 2031
	if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
		int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
			       SDE_AUDIO_POWER_SHIFT_CPT);
		DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
				 port_name(port));
	}
2032 2033

	if (pch_iir & SDE_AUX_MASK_CPT)
2034
		dp_aux_irq_handler(dev_priv);
2035 2036

	if (pch_iir & SDE_GMBUS_CPT)
2037
		gmbus_irq_handler(dev_priv);
2038 2039 2040 2041 2042 2043 2044 2045

	if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
		DRM_DEBUG_DRIVER("Audio CP request interrupt\n");

	if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
		DRM_DEBUG_DRIVER("Audio CP change interrupt\n");

	if (pch_iir & SDE_FDI_MASK_CPT)
2046
		for_each_pipe(dev_priv, pipe)
2047 2048 2049
			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
					 pipe_name(pipe),
					 I915_READ(FDI_RX_IIR(pipe)));
2050 2051

	if (pch_iir & SDE_ERROR_CPT)
2052
		cpt_serr_int_handler(dev_priv);
2053 2054
}

2055
static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069
{
	u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
		~SDE_PORTE_HOTPLUG_SPT;
	u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
	u32 pin_mask = 0, long_mask = 0;

	if (hotplug_trigger) {
		u32 dig_hotplug_reg;

		dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
		I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);

		intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
				   dig_hotplug_reg, hpd_spt,
2070
				   spt_port_hotplug_long_detect);
2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084
	}

	if (hotplug2_trigger) {
		u32 dig_hotplug_reg;

		dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
		I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);

		intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger,
				   dig_hotplug_reg, hpd_spt,
				   spt_port_hotplug2_long_detect);
	}

	if (pin_mask)
2085
		intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2086 2087

	if (pch_iir & SDE_GMBUS_CPT)
2088
		gmbus_irq_handler(dev_priv);
2089 2090
}

2091 2092
static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
				u32 hotplug_trigger,
2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103
				const u32 hpd[HPD_NUM_PINS])
{
	u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;

	dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
	I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);

	intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
			   dig_hotplug_reg, hpd,
			   ilk_port_hotplug_long_detect);

2104
	intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2105 2106
}

2107 2108
static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
				    u32 de_iir)
2109
{
2110
	enum pipe pipe;
2111 2112
	u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;

2113
	if (hotplug_trigger)
2114
		ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk);
2115 2116

	if (de_iir & DE_AUX_CHANNEL_A)
2117
		dp_aux_irq_handler(dev_priv);
2118 2119

	if (de_iir & DE_GSE)
2120
		intel_opregion_asle_intr(dev_priv);
2121 2122 2123 2124

	if (de_iir & DE_POISON)
		DRM_ERROR("Poison interrupt\n");

2125
	for_each_pipe(dev_priv, pipe) {
2126 2127 2128
		if (de_iir & DE_PIPE_VBLANK(pipe) &&
		    intel_pipe_handle_vblank(dev_priv, pipe))
			intel_check_page_flip(dev_priv, pipe);
2129

2130
		if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2131
			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2132

2133
		if (de_iir & DE_PIPE_CRC_DONE(pipe))
2134
			i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2135

2136
		/* plane/pipes map 1:1 on ilk+ */
2137
		if (de_iir & DE_PLANE_FLIP_DONE(pipe))
2138
			intel_finish_page_flip_cs(dev_priv, pipe);
2139 2140 2141 2142 2143 2144
	}

	/* check event from PCH */
	if (de_iir & DE_PCH_EVENT) {
		u32 pch_iir = I915_READ(SDEIIR);

2145 2146
		if (HAS_PCH_CPT(dev_priv))
			cpt_irq_handler(dev_priv, pch_iir);
2147
		else
2148
			ibx_irq_handler(dev_priv, pch_iir);
2149 2150 2151 2152 2153

		/* should clear PCH hotplug event before clear CPU irq */
		I915_WRITE(SDEIIR, pch_iir);
	}

2154 2155
	if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT)
		ironlake_rps_change_irq_handler(dev_priv);
2156 2157
}

2158 2159
static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
				    u32 de_iir)
2160
{
2161
	enum pipe pipe;
2162 2163
	u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;

2164
	if (hotplug_trigger)
2165
		ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb);
2166 2167

	if (de_iir & DE_ERR_INT_IVB)
2168
		ivb_err_int_handler(dev_priv);
2169 2170

	if (de_iir & DE_AUX_CHANNEL_A_IVB)
2171
		dp_aux_irq_handler(dev_priv);
2172 2173

	if (de_iir & DE_GSE_IVB)
2174
		intel_opregion_asle_intr(dev_priv);
2175

2176
	for_each_pipe(dev_priv, pipe) {
2177 2178 2179
		if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
		    intel_pipe_handle_vblank(dev_priv, pipe))
			intel_check_page_flip(dev_priv, pipe);
2180 2181

		/* plane/pipes map 1:1 on ilk+ */
2182
		if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe))
2183
			intel_finish_page_flip_cs(dev_priv, pipe);
2184 2185 2186
	}

	/* check event from PCH */
2187
	if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2188 2189
		u32 pch_iir = I915_READ(SDEIIR);

2190
		cpt_irq_handler(dev_priv, pch_iir);
2191 2192 2193 2194 2195 2196

		/* clear PCH hotplug event before clear CPU irq */
		I915_WRITE(SDEIIR, pch_iir);
	}
}

2197 2198 2199 2200 2201 2202 2203 2204
/*
 * To handle irqs with the minimum potential races with fresh interrupts, we:
 * 1 - Disable Master Interrupt Control.
 * 2 - Find the source(s) of the interrupt.
 * 3 - Clear the Interrupt Identity bits (IIR).
 * 4 - Process the interrupt(s) that had bits set in the IIRs.
 * 5 - Re-enable Master Interrupt Control.
 */
2205
static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2206
{
2207
	struct drm_device *dev = arg;
2208
	struct drm_i915_private *dev_priv = to_i915(dev);
2209
	u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2210
	irqreturn_t ret = IRQ_NONE;
2211

2212 2213 2214
	if (!intel_irqs_enabled(dev_priv))
		return IRQ_NONE;

2215 2216 2217
	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
	disable_rpm_wakeref_asserts(dev_priv);

2218 2219 2220
	/* disable master interrupt before clearing iir  */
	de_ier = I915_READ(DEIER);
	I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2221
	POSTING_READ(DEIER);
2222

2223 2224 2225 2226 2227
	/* Disable south interrupts. We'll only write to SDEIIR once, so further
	 * interrupts will will be stored on its back queue, and then we'll be
	 * able to process them after we restore SDEIER (as soon as we restore
	 * it, we'll get an interrupt if SDEIIR still has something to process
	 * due to its back queue). */
2228
	if (!HAS_PCH_NOP(dev_priv)) {
2229 2230 2231 2232
		sde_ier = I915_READ(SDEIER);
		I915_WRITE(SDEIER, 0);
		POSTING_READ(SDEIER);
	}
2233

2234 2235
	/* Find, clear, then process each source of interrupt */

2236
	gt_iir = I915_READ(GTIIR);
2237
	if (gt_iir) {
2238 2239
		I915_WRITE(GTIIR, gt_iir);
		ret = IRQ_HANDLED;
2240
		if (INTEL_GEN(dev_priv) >= 6)
2241
			snb_gt_irq_handler(dev_priv, gt_iir);
2242
		else
2243
			ilk_gt_irq_handler(dev_priv, gt_iir);
2244 2245
	}

2246 2247
	de_iir = I915_READ(DEIIR);
	if (de_iir) {
2248 2249
		I915_WRITE(DEIIR, de_iir);
		ret = IRQ_HANDLED;
2250 2251
		if (INTEL_GEN(dev_priv) >= 7)
			ivb_display_irq_handler(dev_priv, de_iir);
2252
		else
2253
			ilk_display_irq_handler(dev_priv, de_iir);
2254 2255
	}

2256
	if (INTEL_GEN(dev_priv) >= 6) {
2257 2258 2259 2260
		u32 pm_iir = I915_READ(GEN6_PMIIR);
		if (pm_iir) {
			I915_WRITE(GEN6_PMIIR, pm_iir);
			ret = IRQ_HANDLED;
2261
			gen6_rps_irq_handler(dev_priv, pm_iir);
2262
		}
2263
	}
2264 2265 2266

	I915_WRITE(DEIER, de_ier);
	POSTING_READ(DEIER);
2267
	if (!HAS_PCH_NOP(dev_priv)) {
2268 2269 2270
		I915_WRITE(SDEIER, sde_ier);
		POSTING_READ(SDEIER);
	}
2271

2272 2273 2274
	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
	enable_rpm_wakeref_asserts(dev_priv);

2275 2276 2277
	return ret;
}

2278 2279
static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
				u32 hotplug_trigger,
2280
				const u32 hpd[HPD_NUM_PINS])
2281
{
2282
	u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2283

2284 2285
	dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
	I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2286

2287
	intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2288
			   dig_hotplug_reg, hpd,
2289
			   bxt_port_hotplug_long_detect);
2290

2291
	intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2292 2293
}

2294 2295
static irqreturn_t
gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2296 2297
{
	irqreturn_t ret = IRQ_NONE;
2298
	u32 iir;
2299
	enum pipe pipe;
J
Jesse Barnes 已提交
2300

2301
	if (master_ctl & GEN8_DE_MISC_IRQ) {
2302 2303 2304
		iir = I915_READ(GEN8_DE_MISC_IIR);
		if (iir) {
			I915_WRITE(GEN8_DE_MISC_IIR, iir);
2305
			ret = IRQ_HANDLED;
2306
			if (iir & GEN8_DE_MISC_GSE)
2307
				intel_opregion_asle_intr(dev_priv);
2308 2309
			else
				DRM_ERROR("Unexpected DE Misc interrupt\n");
2310
		}
2311 2312
		else
			DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2313 2314
	}

2315
	if (master_ctl & GEN8_DE_PORT_IRQ) {
2316 2317 2318
		iir = I915_READ(GEN8_DE_PORT_IIR);
		if (iir) {
			u32 tmp_mask;
2319
			bool found = false;
2320

2321
			I915_WRITE(GEN8_DE_PORT_IIR, iir);
2322
			ret = IRQ_HANDLED;
J
Jesse Barnes 已提交
2323

2324 2325 2326 2327 2328 2329 2330
			tmp_mask = GEN8_AUX_CHANNEL_A;
			if (INTEL_INFO(dev_priv)->gen >= 9)
				tmp_mask |= GEN9_AUX_CHANNEL_B |
					    GEN9_AUX_CHANNEL_C |
					    GEN9_AUX_CHANNEL_D;

			if (iir & tmp_mask) {
2331
				dp_aux_irq_handler(dev_priv);
2332 2333 2334
				found = true;
			}

2335 2336 2337
			if (IS_BROXTON(dev_priv)) {
				tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
				if (tmp_mask) {
2338 2339
					bxt_hpd_irq_handler(dev_priv, tmp_mask,
							    hpd_bxt);
2340 2341 2342 2343 2344
					found = true;
				}
			} else if (IS_BROADWELL(dev_priv)) {
				tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
				if (tmp_mask) {
2345 2346
					ilk_hpd_irq_handler(dev_priv,
							    tmp_mask, hpd_bdw);
2347 2348
					found = true;
				}
2349 2350
			}

2351 2352
			if (IS_BROXTON(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
				gmbus_irq_handler(dev_priv);
S
Shashank Sharma 已提交
2353 2354 2355
				found = true;
			}

2356
			if (!found)
2357
				DRM_ERROR("Unexpected DE Port interrupt\n");
2358
		}
2359 2360
		else
			DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2361 2362
	}

2363
	for_each_pipe(dev_priv, pipe) {
2364
		u32 flip_done, fault_errors;
2365

2366 2367
		if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
			continue;
2368

2369 2370 2371 2372 2373
		iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
		if (!iir) {
			DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
			continue;
		}
2374

2375 2376
		ret = IRQ_HANDLED;
		I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2377

2378 2379 2380
		if (iir & GEN8_PIPE_VBLANK &&
		    intel_pipe_handle_vblank(dev_priv, pipe))
			intel_check_page_flip(dev_priv, pipe);
2381

2382 2383 2384 2385 2386
		flip_done = iir;
		if (INTEL_INFO(dev_priv)->gen >= 9)
			flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE;
		else
			flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE;
2387

2388
		if (flip_done)
2389
			intel_finish_page_flip_cs(dev_priv, pipe);
2390

2391
		if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2392
			hsw_pipe_crc_irq_handler(dev_priv, pipe);
2393

2394 2395
		if (iir & GEN8_PIPE_FIFO_UNDERRUN)
			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2396

2397 2398 2399 2400 2401
		fault_errors = iir;
		if (INTEL_INFO(dev_priv)->gen >= 9)
			fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
		else
			fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2402

2403 2404 2405 2406
		if (fault_errors)
			DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
				  pipe_name(pipe),
				  fault_errors);
2407 2408
	}

2409
	if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2410
	    master_ctl & GEN8_DE_PCH_IRQ) {
2411 2412 2413 2414 2415
		/*
		 * FIXME(BDW): Assume for now that the new interrupt handling
		 * scheme also closed the SDE interrupt handling race we've seen
		 * on older pch-split platforms. But this needs testing.
		 */
2416 2417 2418
		iir = I915_READ(SDEIIR);
		if (iir) {
			I915_WRITE(SDEIIR, iir);
2419
			ret = IRQ_HANDLED;
2420

2421
			if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
2422
				spt_irq_handler(dev_priv, iir);
2423
			else
2424
				cpt_irq_handler(dev_priv, iir);
2425 2426 2427 2428 2429 2430 2431
		} else {
			/*
			 * Like on previous PCH there seems to be something
			 * fishy going on with forwarding PCH interrupts.
			 */
			DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
		}
2432 2433
	}

2434 2435 2436 2437 2438 2439
	return ret;
}

static irqreturn_t gen8_irq_handler(int irq, void *arg)
{
	struct drm_device *dev = arg;
2440
	struct drm_i915_private *dev_priv = to_i915(dev);
2441
	u32 master_ctl;
2442
	u32 gt_iir[4] = {};
2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458
	irqreturn_t ret;

	if (!intel_irqs_enabled(dev_priv))
		return IRQ_NONE;

	master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
	master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
	if (!master_ctl)
		return IRQ_NONE;

	I915_WRITE_FW(GEN8_MASTER_IRQ, 0);

	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
	disable_rpm_wakeref_asserts(dev_priv);

	/* Find, clear, then process each source of interrupt */
2459 2460
	ret = gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
	gen8_gt_irq_handler(dev_priv, gt_iir);
2461 2462
	ret |= gen8_de_irq_handler(dev_priv, master_ctl);

2463 2464
	I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
	POSTING_READ_FW(GEN8_MASTER_IRQ);
2465

2466 2467
	enable_rpm_wakeref_asserts(dev_priv);

2468 2469 2470
	return ret;
}

2471
static void i915_error_wake_up(struct drm_i915_private *dev_priv)
2472 2473 2474 2475 2476 2477 2478 2479 2480
{
	/*
	 * Notify all waiters for GPU completion events that reset state has
	 * been changed, and that they need to restart their wait after
	 * checking for potential errors (and bail out to drop locks if there is
	 * a gpu reset pending so that i915_error_work_func can acquire them).
	 */

	/* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2481
	wake_up_all(&dev_priv->gpu_error.wait_queue);
2482 2483 2484 2485 2486

	/* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
	wake_up_all(&dev_priv->pending_flip_queue);
}

2487
/**
2488
 * i915_reset_and_wakeup - do process context error handling work
2489
 * @dev_priv: i915 device private
2490 2491 2492 2493
 *
 * Fire an error uevent so userspace can see that a hang or error
 * was detected.
 */
2494
static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
2495
{
2496
	struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
2497 2498 2499
	char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
	char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
	char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2500
	int ret;
2501

2502
	kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
2503

2504 2505 2506 2507 2508 2509 2510 2511 2512 2513
	/*
	 * Note that there's only one work item which does gpu resets, so we
	 * need not worry about concurrent gpu resets potentially incrementing
	 * error->reset_counter twice. We only need to take care of another
	 * racing irq/hangcheck declaring the gpu dead for a second time. A
	 * quick check for that is good enough: schedule_work ensures the
	 * correct ordering between hang detection and this work item, and since
	 * the reset in-progress bit is only ever set by code outside of this
	 * work we don't need to worry about any other races.
	 */
2514
	if (i915_reset_in_progress(&dev_priv->gpu_error)) {
2515
		DRM_DEBUG_DRIVER("resetting chip\n");
2516
		kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
2517

2518 2519 2520 2521 2522 2523 2524 2525
		/*
		 * In most cases it's guaranteed that we get here with an RPM
		 * reference held, for example because there is a pending GPU
		 * request that won't finish until the reset is done. This
		 * isn't the case at least when we get here by doing a
		 * simulated reset via debugs, so get an RPM reference.
		 */
		intel_runtime_pm_get(dev_priv);
2526

2527
		intel_prepare_reset(dev_priv);
2528

2529 2530 2531 2532 2533 2534
		/*
		 * All state reset _must_ be completed before we update the
		 * reset counter, for otherwise waiters might miss the reset
		 * pending state and not properly drop locks, resulting in
		 * deadlocks with the reset work.
		 */
2535
		ret = i915_reset(dev_priv);
2536

2537
		intel_finish_reset(dev_priv);
2538

2539 2540
		intel_runtime_pm_put(dev_priv);

2541
		if (ret == 0)
2542
			kobject_uevent_env(kobj,
2543
					   KOBJ_CHANGE, reset_done_event);
2544

2545 2546 2547 2548
		/*
		 * Note: The wake_up also serves as a memory barrier so that
		 * waiters see the update value of the reset counter atomic_t.
		 */
2549
		wake_up_all(&dev_priv->gpu_error.reset_queue);
2550
	}
2551 2552
}

2553
static void i915_report_and_clear_eir(struct drm_i915_private *dev_priv)
2554
{
2555
	uint32_t instdone[I915_NUM_INSTDONE_REG];
2556
	u32 eir = I915_READ(EIR);
2557
	int pipe, i;
2558

2559 2560
	if (!eir)
		return;
2561

2562
	pr_err("render error detected, EIR: 0x%08x\n", eir);
2563

2564
	i915_get_extra_instdone(dev_priv, instdone);
2565

2566
	if (IS_G4X(dev_priv)) {
2567 2568 2569
		if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
			u32 ipeir = I915_READ(IPEIR_I965);

2570 2571
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2572 2573
			for (i = 0; i < ARRAY_SIZE(instdone); i++)
				pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2574 2575
			pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2576
			I915_WRITE(IPEIR_I965, ipeir);
2577
			POSTING_READ(IPEIR_I965);
2578 2579 2580
		}
		if (eir & GM45_ERROR_PAGE_TABLE) {
			u32 pgtbl_err = I915_READ(PGTBL_ER);
2581 2582
			pr_err("page table error\n");
			pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2583
			I915_WRITE(PGTBL_ER, pgtbl_err);
2584
			POSTING_READ(PGTBL_ER);
2585 2586 2587
		}
	}

2588
	if (!IS_GEN2(dev_priv)) {
2589 2590
		if (eir & I915_ERROR_PAGE_TABLE) {
			u32 pgtbl_err = I915_READ(PGTBL_ER);
2591 2592
			pr_err("page table error\n");
			pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2593
			I915_WRITE(PGTBL_ER, pgtbl_err);
2594
			POSTING_READ(PGTBL_ER);
2595 2596 2597 2598
		}
	}

	if (eir & I915_ERROR_MEMORY_REFRESH) {
2599
		pr_err("memory refresh error:\n");
2600
		for_each_pipe(dev_priv, pipe)
2601
			pr_err("pipe %c stat: 0x%08x\n",
2602
			       pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2603 2604 2605
		/* pipestat has already been acked */
	}
	if (eir & I915_ERROR_INSTRUCTION) {
2606 2607
		pr_err("instruction error\n");
		pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
2608 2609
		for (i = 0; i < ARRAY_SIZE(instdone); i++)
			pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2610
		if (INTEL_GEN(dev_priv) < 4) {
2611 2612
			u32 ipeir = I915_READ(IPEIR);

2613 2614 2615
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
2616
			I915_WRITE(IPEIR, ipeir);
2617
			POSTING_READ(IPEIR);
2618 2619 2620
		} else {
			u32 ipeir = I915_READ(IPEIR_I965);

2621 2622 2623 2624
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
			pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2625
			I915_WRITE(IPEIR_I965, ipeir);
2626
			POSTING_READ(IPEIR_I965);
2627 2628 2629 2630
		}
	}

	I915_WRITE(EIR, eir);
2631
	POSTING_READ(EIR);
2632 2633 2634 2635 2636 2637 2638 2639 2640 2641
	eir = I915_READ(EIR);
	if (eir) {
		/*
		 * some errors might have become stuck,
		 * mask them.
		 */
		DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
		I915_WRITE(EMR, I915_READ(EMR) | eir);
		I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
	}
2642 2643 2644
}

/**
2645
 * i915_handle_error - handle a gpu error
2646
 * @dev_priv: i915 device private
2647
 * @engine_mask: mask representing engines that are hung
2648
 * Do some basic checking of register state at error time and
2649 2650 2651 2652
 * dump it to the syslog.  Also call i915_capture_error_state() to make
 * sure we get a record and make it available in debugfs.  Fire a uevent
 * so userspace knows something bad happened (should trigger collection
 * of a ring dump etc.).
2653
 * @fmt: Error message format string
2654
 */
2655 2656
void i915_handle_error(struct drm_i915_private *dev_priv,
		       u32 engine_mask,
2657
		       const char *fmt, ...)
2658
{
2659 2660
	va_list args;
	char error_msg[80];
2661

2662 2663 2664 2665
	va_start(args, fmt);
	vscnprintf(error_msg, sizeof(error_msg), fmt, args);
	va_end(args);

2666 2667
	i915_capture_error_state(dev_priv, engine_mask, error_msg);
	i915_report_and_clear_eir(dev_priv);
2668

2669
	if (engine_mask) {
2670
		atomic_or(I915_RESET_IN_PROGRESS_FLAG,
2671
				&dev_priv->gpu_error.reset_counter);
2672

2673
		/*
2674 2675 2676
		 * Wakeup waiting processes so that the reset function
		 * i915_reset_and_wakeup doesn't deadlock trying to grab
		 * various locks. By bumping the reset counter first, the woken
2677 2678 2679 2680 2681 2682 2683 2684
		 * processes will see a reset in progress and back off,
		 * releasing their locks and then wait for the reset completion.
		 * We must do this for _all_ gpu waiters that might hold locks
		 * that the reset work needs to acquire.
		 *
		 * Note: The wake_up serves as the required memory barrier to
		 * ensure that the waiters see the updated value of the reset
		 * counter atomic_t.
2685
		 */
2686
		i915_error_wake_up(dev_priv);
2687 2688
	}

2689
	i915_reset_and_wakeup(dev_priv);
2690 2691
}

2692 2693 2694
/* Called from drm generic code, passed 'crtc' which
 * we use as a pipe index
 */
2695
static int i915_enable_vblank(struct drm_device *dev, unsigned int pipe)
2696
{
2697
	struct drm_i915_private *dev_priv = to_i915(dev);
2698
	unsigned long irqflags;
2699

2700
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2701
	if (INTEL_INFO(dev)->gen >= 4)
2702
		i915_enable_pipestat(dev_priv, pipe,
2703
				     PIPE_START_VBLANK_INTERRUPT_STATUS);
2704
	else
2705
		i915_enable_pipestat(dev_priv, pipe,
2706
				     PIPE_VBLANK_INTERRUPT_STATUS);
2707
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2708

2709 2710 2711
	return 0;
}

2712
static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
2713
{
2714
	struct drm_i915_private *dev_priv = to_i915(dev);
2715
	unsigned long irqflags;
2716
	uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2717
						     DE_PIPE_VBLANK(pipe);
2718 2719

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2720
	ilk_enable_display_irq(dev_priv, bit);
2721 2722 2723 2724 2725
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

	return 0;
}

2726
static int valleyview_enable_vblank(struct drm_device *dev, unsigned int pipe)
J
Jesse Barnes 已提交
2727
{
2728
	struct drm_i915_private *dev_priv = to_i915(dev);
J
Jesse Barnes 已提交
2729 2730 2731
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2732
	i915_enable_pipestat(dev_priv, pipe,
2733
			     PIPE_START_VBLANK_INTERRUPT_STATUS);
J
Jesse Barnes 已提交
2734 2735 2736 2737 2738
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

	return 0;
}

2739
static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
2740
{
2741
	struct drm_i915_private *dev_priv = to_i915(dev);
2742 2743 2744
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2745
	bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2746
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2747

2748 2749 2750
	return 0;
}

2751 2752 2753
/* Called from drm generic code, passed 'crtc' which
 * we use as a pipe index
 */
2754
static void i915_disable_vblank(struct drm_device *dev, unsigned int pipe)
2755
{
2756
	struct drm_i915_private *dev_priv = to_i915(dev);
2757
	unsigned long irqflags;
2758

2759
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2760
	i915_disable_pipestat(dev_priv, pipe,
2761 2762
			      PIPE_VBLANK_INTERRUPT_STATUS |
			      PIPE_START_VBLANK_INTERRUPT_STATUS);
2763 2764 2765
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

2766
static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
2767
{
2768
	struct drm_i915_private *dev_priv = to_i915(dev);
2769
	unsigned long irqflags;
2770
	uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2771
						     DE_PIPE_VBLANK(pipe);
2772 2773

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2774
	ilk_disable_display_irq(dev_priv, bit);
2775 2776 2777
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

2778
static void valleyview_disable_vblank(struct drm_device *dev, unsigned int pipe)
J
Jesse Barnes 已提交
2779
{
2780
	struct drm_i915_private *dev_priv = to_i915(dev);
J
Jesse Barnes 已提交
2781 2782 2783
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2784
	i915_disable_pipestat(dev_priv, pipe,
2785
			      PIPE_START_VBLANK_INTERRUPT_STATUS);
J
Jesse Barnes 已提交
2786 2787 2788
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

2789
static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
2790
{
2791
	struct drm_i915_private *dev_priv = to_i915(dev);
2792 2793 2794
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2795
	bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2796 2797 2798
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

2799
static bool
2800
ipehr_is_semaphore_wait(struct intel_engine_cs *engine, u32 ipehr)
2801
{
2802
	if (INTEL_GEN(engine->i915) >= 8) {
2803
		return (ipehr >> 23) == 0x1c;
2804 2805 2806 2807 2808 2809 2810
	} else {
		ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
		return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
				 MI_SEMAPHORE_REGISTER);
	}
}

2811
static struct intel_engine_cs *
2812 2813
semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr,
				 u64 offset)
2814
{
2815
	struct drm_i915_private *dev_priv = engine->i915;
2816
	struct intel_engine_cs *signaller;
2817

2818
	if (INTEL_GEN(dev_priv) >= 8) {
2819
		for_each_engine(signaller, dev_priv) {
2820
			if (engine == signaller)
2821 2822
				continue;

2823
			if (offset == signaller->semaphore.signal_ggtt[engine->id])
2824 2825
				return signaller;
		}
2826 2827 2828
	} else {
		u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;

2829
		for_each_engine(signaller, dev_priv) {
2830
			if(engine == signaller)
2831 2832
				continue;

2833
			if (sync_bits == signaller->semaphore.mbox.wait[engine->id])
2834 2835 2836 2837
				return signaller;
		}
	}

2838
	DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2839
		  engine->id, ipehr, offset);
2840 2841 2842 2843

	return NULL;
}

2844
static struct intel_engine_cs *
2845
semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
2846
{
2847
	struct drm_i915_private *dev_priv = engine->i915;
2848
	void __iomem *vaddr;
2849
	u32 cmd, ipehr, head;
2850 2851
	u64 offset = 0;
	int i, backwards;
2852

2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869
	/*
	 * This function does not support execlist mode - any attempt to
	 * proceed further into this function will result in a kernel panic
	 * when dereferencing ring->buffer, which is not set up in execlist
	 * mode.
	 *
	 * The correct way of doing it would be to derive the currently
	 * executing ring buffer from the current context, which is derived
	 * from the currently running request. Unfortunately, to get the
	 * current request we would have to grab the struct_mutex before doing
	 * anything else, which would be ill-advised since some other thread
	 * might have grabbed it already and managed to hang itself, causing
	 * the hang checker to deadlock.
	 *
	 * Therefore, this function does not support execlist mode in its
	 * current form. Just return NULL and move on.
	 */
2870
	if (engine->buffer == NULL)
2871 2872
		return NULL;

2873
	ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
2874
	if (!ipehr_is_semaphore_wait(engine, ipehr))
2875
		return NULL;
2876

2877 2878 2879
	/*
	 * HEAD is likely pointing to the dword after the actual command,
	 * so scan backwards until we find the MBOX. But limit it to just 3
2880 2881
	 * or 4 dwords depending on the semaphore wait command size.
	 * Note that we don't care about ACTHD here since that might
2882 2883
	 * point at at batch, and semaphores are always emitted into the
	 * ringbuffer itself.
2884
	 */
2885
	head = I915_READ_HEAD(engine) & HEAD_ADDR;
2886
	backwards = (INTEL_GEN(dev_priv) >= 8) ? 5 : 4;
2887
	vaddr = (void __iomem *)engine->buffer->vaddr;
2888

2889
	for (i = backwards; i; --i) {
2890 2891 2892 2893 2894
		/*
		 * Be paranoid and presume the hw has gone off into the wild -
		 * our ring is smaller than what the hardware (and hence
		 * HEAD_ADDR) allows. Also handles wrap-around.
		 */
2895
		head &= engine->buffer->size - 1;
2896 2897

		/* This here seems to blow up */
2898
		cmd = ioread32(vaddr + head);
2899 2900 2901
		if (cmd == ipehr)
			break;

2902 2903
		head -= 4;
	}
2904

2905 2906
	if (!i)
		return NULL;
2907

2908
	*seqno = ioread32(vaddr + head + 4) + 1;
2909
	if (INTEL_GEN(dev_priv) >= 8) {
2910
		offset = ioread32(vaddr + head + 12);
2911
		offset <<= 32;
2912
		offset |= ioread32(vaddr + head + 8);
2913
	}
2914
	return semaphore_wait_to_signaller_ring(engine, ipehr, offset);
2915 2916
}

2917
static int semaphore_passed(struct intel_engine_cs *engine)
2918
{
2919
	struct drm_i915_private *dev_priv = engine->i915;
2920
	struct intel_engine_cs *signaller;
2921
	u32 seqno;
2922

2923
	engine->hangcheck.deadlock++;
2924

2925
	signaller = semaphore_waits_for(engine, &seqno);
2926 2927 2928 2929
	if (signaller == NULL)
		return -1;

	/* Prevent pathological recursion due to driver bugs */
2930
	if (signaller->hangcheck.deadlock >= I915_NUM_ENGINES)
2931 2932
		return -1;

2933
	if (i915_seqno_passed(intel_engine_get_seqno(signaller), seqno))
2934 2935
		return 1;

2936 2937 2938
	/* cursory check for an unkickable deadlock */
	if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
	    semaphore_passed(signaller) < 0)
2939 2940 2941
		return -1;

	return 0;
2942 2943 2944 2945
}

static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
{
2946
	struct intel_engine_cs *engine;
2947

2948
	for_each_engine(engine, dev_priv)
2949
		engine->hangcheck.deadlock = 0;
2950 2951
}

2952
static bool subunits_stuck(struct intel_engine_cs *engine)
2953
{
2954 2955 2956 2957
	u32 instdone[I915_NUM_INSTDONE_REG];
	bool stuck;
	int i;

2958
	if (engine->id != RCS)
2959 2960
		return true;

2961
	i915_get_extra_instdone(engine->i915, instdone);
2962

2963 2964 2965 2966 2967 2968 2969
	/* There might be unstable subunit states even when
	 * actual head is not moving. Filter out the unstable ones by
	 * accumulating the undone -> done transitions and only
	 * consider those as progress.
	 */
	stuck = true;
	for (i = 0; i < I915_NUM_INSTDONE_REG; i++) {
2970
		const u32 tmp = instdone[i] | engine->hangcheck.instdone[i];
2971

2972
		if (tmp != engine->hangcheck.instdone[i])
2973 2974
			stuck = false;

2975
		engine->hangcheck.instdone[i] |= tmp;
2976 2977 2978 2979 2980
	}

	return stuck;
}

2981
static enum intel_engine_hangcheck_action
2982
head_stuck(struct intel_engine_cs *engine, u64 acthd)
2983
{
2984
	if (acthd != engine->hangcheck.acthd) {
2985 2986

		/* Clear subunit states on head movement */
2987 2988
		memset(engine->hangcheck.instdone, 0,
		       sizeof(engine->hangcheck.instdone));
2989

2990
		return HANGCHECK_ACTIVE;
2991
	}
2992

2993
	if (!subunits_stuck(engine))
2994 2995 2996 2997 2998
		return HANGCHECK_ACTIVE;

	return HANGCHECK_HUNG;
}

2999 3000
static enum intel_engine_hangcheck_action
engine_stuck(struct intel_engine_cs *engine, u64 acthd)
3001
{
3002
	struct drm_i915_private *dev_priv = engine->i915;
3003
	enum intel_engine_hangcheck_action ha;
3004 3005
	u32 tmp;

3006
	ha = head_stuck(engine, acthd);
3007 3008 3009
	if (ha != HANGCHECK_HUNG)
		return ha;

3010
	if (IS_GEN2(dev_priv))
3011
		return HANGCHECK_HUNG;
3012 3013 3014 3015 3016 3017

	/* Is the chip hanging on a WAIT_FOR_EVENT?
	 * If so we can simply poke the RB_WAIT bit
	 * and break the hang. This should work on
	 * all but the second generation chipsets.
	 */
3018
	tmp = I915_READ_CTL(engine);
3019
	if (tmp & RING_WAIT) {
3020
		i915_handle_error(dev_priv, 0,
3021
				  "Kicking stuck wait on %s",
3022 3023
				  engine->name);
		I915_WRITE_CTL(engine, tmp);
3024
		return HANGCHECK_KICK;
3025 3026
	}

3027
	if (INTEL_GEN(dev_priv) >= 6 && tmp & RING_WAIT_SEMAPHORE) {
3028
		switch (semaphore_passed(engine)) {
3029
		default:
3030
			return HANGCHECK_HUNG;
3031
		case 1:
3032
			i915_handle_error(dev_priv, 0,
3033
					  "Kicking stuck semaphore on %s",
3034 3035
					  engine->name);
			I915_WRITE_CTL(engine, tmp);
3036
			return HANGCHECK_KICK;
3037
		case 0:
3038
			return HANGCHECK_WAIT;
3039
		}
3040
	}
3041

3042
	return HANGCHECK_HUNG;
3043 3044
}

3045
/*
B
Ben Gamari 已提交
3046
 * This is called when the chip hasn't reported back with completed
3047 3048 3049 3050 3051
 * batchbuffers in a long time. We keep track per ring seqno progress and
 * if there are no progress, hangcheck score for that ring is increased.
 * Further, acthd is inspected to see if the ring is stuck. On stuck case
 * we kick the ring. If we see no progress on three subsequent calls
 * we assume chip is wedged and try to fix it by resetting the chip.
B
Ben Gamari 已提交
3052
 */
3053
static void i915_hangcheck_elapsed(struct work_struct *work)
B
Ben Gamari 已提交
3054
{
3055 3056 3057
	struct drm_i915_private *dev_priv =
		container_of(work, typeof(*dev_priv),
			     gpu_error.hangcheck_work.work);
3058
	struct intel_engine_cs *engine;
3059 3060
	unsigned int hung = 0, stuck = 0;
	int busy_count = 0;
3061 3062 3063
#define BUSY 1
#define KICK 5
#define HUNG 20
3064
#define ACTIVE_DECAY 15
3065

3066
	if (!i915.enable_hangcheck)
3067 3068
		return;

3069
	if (!READ_ONCE(dev_priv->gt.awake))
3070
		return;
3071

3072 3073 3074 3075 3076 3077
	/* As enabling the GPU requires fairly extensive mmio access,
	 * periodically arm the mmio checker to see if we are triggering
	 * any invalid access.
	 */
	intel_uncore_arm_unclaimed_mmio_detection(dev_priv);

3078
	for_each_engine(engine, dev_priv) {
3079
		bool busy = intel_engine_has_waiter(engine);
3080 3081
		u64 acthd;
		u32 seqno;
3082
		u32 submit;
3083

3084 3085
		semaphore_clear_deadlocks(dev_priv);

3086 3087 3088 3089 3090 3091 3092 3093 3094 3095
		/* We don't strictly need an irq-barrier here, as we are not
		 * serving an interrupt request, be paranoid in case the
		 * barrier has side-effects (such as preventing a broken
		 * cacheline snoop) and so be sure that we can see the seqno
		 * advance. If the seqno should stick, due to a stale
		 * cacheline, we would erroneously declare the GPU hung.
		 */
		if (engine->irq_seqno_barrier)
			engine->irq_seqno_barrier(engine);

3096
		acthd = intel_engine_get_active_head(engine);
3097
		seqno = intel_engine_get_seqno(engine);
3098
		submit = READ_ONCE(engine->last_submitted_seqno);
3099

3100
		if (engine->hangcheck.seqno == seqno) {
3101
			if (i915_seqno_passed(seqno, submit)) {
3102
				engine->hangcheck.action = HANGCHECK_IDLE;
3103
				if (busy) {
3104
					/* Safeguard against driver failure */
3105
					engine->hangcheck.score += BUSY;
3106
				}
3107
			} else {
3108
				/* We always increment the hangcheck score
3109
				 * if the engine is busy and still processing
3110 3111 3112 3113
				 * the same request, so that no single request
				 * can run indefinitely (such as a chain of
				 * batches). The only time we do not increment
				 * the hangcheck score on this ring, if this
3114 3115
				 * engine is in a legitimate wait for another
				 * engine. In that case the waiting engine is a
3116 3117 3118 3119 3120 3121 3122
				 * victim and we want to be sure we catch the
				 * right culprit. Then every time we do kick
				 * the ring, add a small increment to the
				 * score so that we can catch a batch that is
				 * being repeatedly kicked and so responsible
				 * for stalling the machine.
				 */
3123 3124
				engine->hangcheck.action =
					engine_stuck(engine, acthd);
3125

3126
				switch (engine->hangcheck.action) {
3127
				case HANGCHECK_IDLE:
3128
				case HANGCHECK_WAIT:
3129
					break;
3130
				case HANGCHECK_ACTIVE:
3131
					engine->hangcheck.score += BUSY;
3132
					break;
3133
				case HANGCHECK_KICK:
3134
					engine->hangcheck.score += KICK;
3135
					break;
3136
				case HANGCHECK_HUNG:
3137
					engine->hangcheck.score += HUNG;
3138 3139
					break;
				}
3140
			}
3141 3142 3143 3144 3145 3146

			if (engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
				hung |= intel_engine_flag(engine);
				if (engine->hangcheck.action != HANGCHECK_HUNG)
					stuck |= intel_engine_flag(engine);
			}
3147
		} else {
3148
			engine->hangcheck.action = HANGCHECK_ACTIVE;
3149

3150 3151 3152
			/* Gradually reduce the count so that we catch DoS
			 * attempts across multiple batches.
			 */
3153 3154 3155 3156
			if (engine->hangcheck.score > 0)
				engine->hangcheck.score -= ACTIVE_DECAY;
			if (engine->hangcheck.score < 0)
				engine->hangcheck.score = 0;
3157

3158
			/* Clear head and subunit states on seqno movement */
3159
			acthd = 0;
3160

3161 3162
			memset(engine->hangcheck.instdone, 0,
			       sizeof(engine->hangcheck.instdone));
3163 3164
		}

3165 3166
		engine->hangcheck.seqno = seqno;
		engine->hangcheck.acthd = acthd;
3167
		busy_count += busy;
3168
	}
3169

3170 3171
	if (hung) {
		char msg[80];
3172
		unsigned int tmp;
3173
		int len;
3174

3175 3176 3177 3178 3179 3180 3181
		/* If some rings hung but others were still busy, only
		 * blame the hanging rings in the synopsis.
		 */
		if (stuck != hung)
			hung &= ~stuck;
		len = scnprintf(msg, sizeof(msg),
				"%s on ", stuck == hung ? "No progress" : "Hang");
3182
		for_each_engine_masked(engine, dev_priv, hung, tmp)
3183 3184 3185 3186 3187 3188
			len += scnprintf(msg + len, sizeof(msg) - len,
					 "%s, ", engine->name);
		msg[len-2] = '\0';

		return i915_handle_error(dev_priv, hung, msg);
	}
B
Ben Gamari 已提交
3189

3190
	/* Reset timer in case GPU hangs without another request being added */
3191
	if (busy_count)
3192
		i915_queue_hangcheck(dev_priv);
3193 3194
}

3195
static void ibx_irq_reset(struct drm_device *dev)
P
Paulo Zanoni 已提交
3196
{
3197
	struct drm_i915_private *dev_priv = to_i915(dev);
P
Paulo Zanoni 已提交
3198 3199 3200 3201

	if (HAS_PCH_NOP(dev))
		return;

3202
	GEN5_IRQ_RESET(SDE);
3203 3204 3205

	if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
		I915_WRITE(SERR_INT, 0xffffffff);
P
Paulo Zanoni 已提交
3206
}
3207

P
Paulo Zanoni 已提交
3208 3209 3210 3211 3212 3213 3214 3215 3216 3217
/*
 * SDEIER is also touched by the interrupt handler to work around missed PCH
 * interrupts. Hence we can't update it after the interrupt handler is enabled -
 * instead we unconditionally enable all PCH interrupt sources here, but then
 * only unmask them as needed with SDEIMR.
 *
 * This function needs to be called before interrupts are enabled.
 */
static void ibx_irq_pre_postinstall(struct drm_device *dev)
{
3218
	struct drm_i915_private *dev_priv = to_i915(dev);
P
Paulo Zanoni 已提交
3219 3220 3221 3222 3223

	if (HAS_PCH_NOP(dev))
		return;

	WARN_ON(I915_READ(SDEIER) != 0);
P
Paulo Zanoni 已提交
3224 3225 3226 3227
	I915_WRITE(SDEIER, 0xffffffff);
	POSTING_READ(SDEIER);
}

3228
static void gen5_gt_irq_reset(struct drm_device *dev)
3229
{
3230
	struct drm_i915_private *dev_priv = to_i915(dev);
3231

3232
	GEN5_IRQ_RESET(GT);
P
Paulo Zanoni 已提交
3233
	if (INTEL_INFO(dev)->gen >= 6)
3234
		GEN5_IRQ_RESET(GEN6_PM);
3235 3236
}

3237 3238 3239 3240
static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
{
	enum pipe pipe;

3241 3242 3243 3244 3245
	if (IS_CHERRYVIEW(dev_priv))
		I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
	else
		I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);

3246
	i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
3247 3248
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));

3249 3250 3251 3252 3253 3254
	for_each_pipe(dev_priv, pipe) {
		I915_WRITE(PIPESTAT(pipe),
			   PIPE_FIFO_UNDERRUN_STATUS |
			   PIPESTAT_INT_STATUS_MASK);
		dev_priv->pipestat_irq_mask[pipe] = 0;
	}
3255 3256

	GEN5_IRQ_RESET(VLV_);
3257
	dev_priv->irq_mask = ~0;
3258 3259
}

3260 3261 3262
static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
{
	u32 pipestat_mask;
3263
	u32 enable_mask;
3264 3265 3266 3267 3268 3269 3270 3271 3272
	enum pipe pipe;

	pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
			PIPE_CRC_DONE_INTERRUPT_STATUS;

	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
	for_each_pipe(dev_priv, pipe)
		i915_enable_pipestat(dev_priv, pipe, pipestat_mask);

3273 3274 3275
	enable_mask = I915_DISPLAY_PORT_INTERRUPT |
		I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3276
	if (IS_CHERRYVIEW(dev_priv))
3277
		enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3278 3279 3280

	WARN_ON(dev_priv->irq_mask != ~0);

3281 3282 3283
	dev_priv->irq_mask = ~enable_mask;

	GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);
3284 3285 3286 3287 3288 3289
}

/* drm_dma.h hooks
*/
static void ironlake_irq_reset(struct drm_device *dev)
{
3290
	struct drm_i915_private *dev_priv = to_i915(dev);
3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301 3302

	I915_WRITE(HWSTAM, 0xffffffff);

	GEN5_IRQ_RESET(DE);
	if (IS_GEN7(dev))
		I915_WRITE(GEN7_ERR_INT, 0xffffffff);

	gen5_gt_irq_reset(dev);

	ibx_irq_reset(dev);
}

J
Jesse Barnes 已提交
3303 3304
static void valleyview_irq_preinstall(struct drm_device *dev)
{
3305
	struct drm_i915_private *dev_priv = to_i915(dev);
J
Jesse Barnes 已提交
3306

3307 3308 3309
	I915_WRITE(VLV_MASTER_IER, 0);
	POSTING_READ(VLV_MASTER_IER);

3310
	gen5_gt_irq_reset(dev);
J
Jesse Barnes 已提交
3311

3312
	spin_lock_irq(&dev_priv->irq_lock);
3313 3314
	if (dev_priv->display_irqs_enabled)
		vlv_display_irq_reset(dev_priv);
3315
	spin_unlock_irq(&dev_priv->irq_lock);
J
Jesse Barnes 已提交
3316 3317
}

3318 3319 3320 3321 3322 3323 3324 3325
static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
{
	GEN8_IRQ_RESET_NDX(GT, 0);
	GEN8_IRQ_RESET_NDX(GT, 1);
	GEN8_IRQ_RESET_NDX(GT, 2);
	GEN8_IRQ_RESET_NDX(GT, 3);
}

P
Paulo Zanoni 已提交
3326
static void gen8_irq_reset(struct drm_device *dev)
3327
{
3328
	struct drm_i915_private *dev_priv = to_i915(dev);
3329 3330 3331 3332 3333
	int pipe;

	I915_WRITE(GEN8_MASTER_IRQ, 0);
	POSTING_READ(GEN8_MASTER_IRQ);

3334
	gen8_gt_irq_reset(dev_priv);
3335

3336
	for_each_pipe(dev_priv, pipe)
3337 3338
		if (intel_display_power_is_enabled(dev_priv,
						   POWER_DOMAIN_PIPE(pipe)))
3339
			GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3340

3341 3342 3343
	GEN5_IRQ_RESET(GEN8_DE_PORT_);
	GEN5_IRQ_RESET(GEN8_DE_MISC_);
	GEN5_IRQ_RESET(GEN8_PCU_);
3344

3345 3346
	if (HAS_PCH_SPLIT(dev))
		ibx_irq_reset(dev);
3347
}
3348

3349 3350
void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
				     unsigned int pipe_mask)
3351
{
3352
	uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3353
	enum pipe pipe;
3354

3355
	spin_lock_irq(&dev_priv->irq_lock);
3356 3357 3358 3359
	for_each_pipe_masked(dev_priv, pipe, pipe_mask)
		GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
				  dev_priv->de_irq_mask[pipe],
				  ~dev_priv->de_irq_mask[pipe] | extra_ier);
3360
	spin_unlock_irq(&dev_priv->irq_lock);
3361 3362
}

3363 3364 3365
void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
				     unsigned int pipe_mask)
{
3366 3367
	enum pipe pipe;

3368
	spin_lock_irq(&dev_priv->irq_lock);
3369 3370
	for_each_pipe_masked(dev_priv, pipe, pipe_mask)
		GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3371 3372 3373
	spin_unlock_irq(&dev_priv->irq_lock);

	/* make sure we're done processing display irqs */
3374
	synchronize_irq(dev_priv->drm.irq);
3375 3376
}

3377 3378
static void cherryview_irq_preinstall(struct drm_device *dev)
{
3379
	struct drm_i915_private *dev_priv = to_i915(dev);
3380 3381 3382 3383

	I915_WRITE(GEN8_MASTER_IRQ, 0);
	POSTING_READ(GEN8_MASTER_IRQ);

3384
	gen8_gt_irq_reset(dev_priv);
3385 3386 3387

	GEN5_IRQ_RESET(GEN8_PCU_);

3388
	spin_lock_irq(&dev_priv->irq_lock);
3389 3390
	if (dev_priv->display_irqs_enabled)
		vlv_display_irq_reset(dev_priv);
3391
	spin_unlock_irq(&dev_priv->irq_lock);
3392 3393
}

3394
static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
3395 3396 3397 3398 3399
				  const u32 hpd[HPD_NUM_PINS])
{
	struct intel_encoder *encoder;
	u32 enabled_irqs = 0;

3400
	for_each_intel_encoder(&dev_priv->drm, encoder)
3401 3402 3403 3404 3405 3406
		if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
			enabled_irqs |= hpd[encoder->hpd_pin];

	return enabled_irqs;
}

3407
static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
3408
{
3409
	u32 hotplug_irqs, hotplug, enabled_irqs;
3410

3411
	if (HAS_PCH_IBX(dev_priv)) {
3412
		hotplug_irqs = SDE_HOTPLUG_MASK;
3413
		enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx);
3414
	} else {
3415
		hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3416
		enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt);
3417
	}
3418

3419
	ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3420 3421 3422

	/*
	 * Enable digital hotplug on the PCH, and configure the DP short pulse
3423 3424
	 * duration to 2ms (which is the minimum in the Display Port spec).
	 * The pulse duration bits are reserved on LPT+.
3425
	 */
3426 3427 3428 3429 3430
	hotplug = I915_READ(PCH_PORT_HOTPLUG);
	hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
	hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
	hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
	hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3431 3432 3433 3434
	/*
	 * When CPU and PCH are on the same package, port A
	 * HPD must be enabled in both north and south.
	 */
3435
	if (HAS_PCH_LPT_LP(dev_priv))
3436
		hotplug |= PORTA_HOTPLUG_ENABLE;
3437
	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3438
}
X
Xiong Zhang 已提交
3439

3440
static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3441 3442 3443 3444
{
	u32 hotplug_irqs, hotplug, enabled_irqs;

	hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3445
	enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt);
3446 3447 3448 3449 3450 3451

	ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);

	/* Enable digital hotplug on the PCH */
	hotplug = I915_READ(PCH_PORT_HOTPLUG);
	hotplug |= PORTD_HOTPLUG_ENABLE | PORTC_HOTPLUG_ENABLE |
3452
		PORTB_HOTPLUG_ENABLE | PORTA_HOTPLUG_ENABLE;
3453 3454 3455 3456 3457
	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);

	hotplug = I915_READ(PCH_PORT_HOTPLUG2);
	hotplug |= PORTE_HOTPLUG_ENABLE;
	I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3458 3459
}

3460
static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
3461 3462 3463
{
	u32 hotplug_irqs, hotplug, enabled_irqs;

3464
	if (INTEL_GEN(dev_priv) >= 8) {
3465
		hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3466
		enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw);
3467 3468

		bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3469
	} else if (INTEL_GEN(dev_priv) >= 7) {
3470
		hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3471
		enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb);
3472 3473

		ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3474 3475
	} else {
		hotplug_irqs = DE_DP_A_HOTPLUG;
3476
		enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk);
3477

3478 3479
		ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
	}
3480 3481 3482 3483

	/*
	 * Enable digital hotplug on the CPU, and configure the DP short pulse
	 * duration to 2ms (which is the minimum in the Display Port spec)
3484
	 * The pulse duration bits are reserved on HSW+.
3485 3486 3487 3488 3489 3490
	 */
	hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
	hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
	hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | DIGITAL_PORTA_PULSE_DURATION_2ms;
	I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);

3491
	ibx_hpd_irq_setup(dev_priv);
3492 3493
}

3494
static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3495
{
3496
	u32 hotplug_irqs, hotplug, enabled_irqs;
3497

3498
	enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt);
3499
	hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
3500

3501
	bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3502

3503 3504 3505
	hotplug = I915_READ(PCH_PORT_HOTPLUG);
	hotplug |= PORTC_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |
		PORTA_HOTPLUG_ENABLE;
3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517 3518 3519 3520 3521 3522 3523 3524 3525

	DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n",
		      hotplug, enabled_irqs);
	hotplug &= ~BXT_DDI_HPD_INVERT_MASK;

	/*
	 * For BXT invert bit has to be set based on AOB design
	 * for HPD detection logic, update it based on VBT fields.
	 */

	if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
	    intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
		hotplug |= BXT_DDIA_HPD_INVERT;
	if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
	    intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
		hotplug |= BXT_DDIB_HPD_INVERT;
	if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
	    intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
		hotplug |= BXT_DDIC_HPD_INVERT;

3526
	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3527 3528
}

P
Paulo Zanoni 已提交
3529 3530
static void ibx_irq_postinstall(struct drm_device *dev)
{
3531
	struct drm_i915_private *dev_priv = to_i915(dev);
3532
	u32 mask;
3533

D
Daniel Vetter 已提交
3534 3535 3536
	if (HAS_PCH_NOP(dev))
		return;

3537
	if (HAS_PCH_IBX(dev))
3538
		mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3539
	else
3540
		mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3541

3542
	gen5_assert_iir_is_zero(dev_priv, SDEIIR);
P
Paulo Zanoni 已提交
3543 3544 3545
	I915_WRITE(SDEIMR, ~mask);
}

3546 3547
static void gen5_gt_irq_postinstall(struct drm_device *dev)
{
3548
	struct drm_i915_private *dev_priv = to_i915(dev);
3549 3550 3551 3552 3553
	u32 pm_irqs, gt_irqs;

	pm_irqs = gt_irqs = 0;

	dev_priv->gt_irq_mask = ~0;
3554
	if (HAS_L3_DPF(dev)) {
3555
		/* L3 parity interrupt is always unmasked. */
3556 3557
		dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
		gt_irqs |= GT_PARITY_ERROR(dev);
3558 3559 3560 3561
	}

	gt_irqs |= GT_RENDER_USER_INTERRUPT;
	if (IS_GEN5(dev)) {
3562
		gt_irqs |= ILK_BSD_USER_INTERRUPT;
3563 3564 3565 3566
	} else {
		gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
	}

P
Paulo Zanoni 已提交
3567
	GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3568 3569

	if (INTEL_INFO(dev)->gen >= 6) {
3570 3571 3572 3573
		/*
		 * RPS interrupts will get enabled/disabled on demand when RPS
		 * itself is enabled/disabled.
		 */
3574 3575 3576
		if (HAS_VEBOX(dev))
			pm_irqs |= PM_VEBOX_USER_INTERRUPT;

3577
		dev_priv->pm_irq_mask = 0xffffffff;
P
Paulo Zanoni 已提交
3578
		GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3579 3580 3581
	}
}

3582
static int ironlake_irq_postinstall(struct drm_device *dev)
3583
{
3584
	struct drm_i915_private *dev_priv = to_i915(dev);
3585 3586 3587 3588 3589 3590
	u32 display_mask, extra_mask;

	if (INTEL_INFO(dev)->gen >= 7) {
		display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
				DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
				DE_PLANEB_FLIP_DONE_IVB |
3591
				DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3592
		extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3593 3594
			      DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
			      DE_DP_A_HOTPLUG_IVB);
3595 3596 3597
	} else {
		display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
				DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3598 3599 3600
				DE_AUX_CHANNEL_A |
				DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
				DE_POISON);
3601 3602 3603
		extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
			      DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
			      DE_DP_A_HOTPLUG);
3604
	}
3605

3606
	dev_priv->irq_mask = ~display_mask;
3607

3608 3609
	I915_WRITE(HWSTAM, 0xeffe);

P
Paulo Zanoni 已提交
3610 3611
	ibx_irq_pre_postinstall(dev);

P
Paulo Zanoni 已提交
3612
	GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3613

3614
	gen5_gt_irq_postinstall(dev);
3615

P
Paulo Zanoni 已提交
3616
	ibx_irq_postinstall(dev);
3617

3618
	if (IS_IRONLAKE_M(dev)) {
3619 3620 3621
		/* Enable PCU event interrupts
		 *
		 * spinlocking not required here for correctness since interrupt
3622 3623
		 * setup is guaranteed to run in single-threaded context. But we
		 * need it to make the assert_spin_locked happy. */
3624
		spin_lock_irq(&dev_priv->irq_lock);
3625
		ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
3626
		spin_unlock_irq(&dev_priv->irq_lock);
3627 3628
	}

3629 3630 3631
	return 0;
}

3632 3633 3634 3635 3636 3637 3638 3639 3640
void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
{
	assert_spin_locked(&dev_priv->irq_lock);

	if (dev_priv->display_irqs_enabled)
		return;

	dev_priv->display_irqs_enabled = true;

3641 3642
	if (intel_irqs_enabled(dev_priv)) {
		vlv_display_irq_reset(dev_priv);
3643
		vlv_display_irq_postinstall(dev_priv);
3644
	}
3645 3646 3647 3648 3649 3650 3651 3652 3653 3654 3655
}

void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
{
	assert_spin_locked(&dev_priv->irq_lock);

	if (!dev_priv->display_irqs_enabled)
		return;

	dev_priv->display_irqs_enabled = false;

3656
	if (intel_irqs_enabled(dev_priv))
3657
		vlv_display_irq_reset(dev_priv);
3658 3659
}

3660 3661 3662

static int valleyview_irq_postinstall(struct drm_device *dev)
{
3663
	struct drm_i915_private *dev_priv = to_i915(dev);
3664

3665
	gen5_gt_irq_postinstall(dev);
J
Jesse Barnes 已提交
3666

3667
	spin_lock_irq(&dev_priv->irq_lock);
3668 3669
	if (dev_priv->display_irqs_enabled)
		vlv_display_irq_postinstall(dev_priv);
3670 3671
	spin_unlock_irq(&dev_priv->irq_lock);

J
Jesse Barnes 已提交
3672
	I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3673
	POSTING_READ(VLV_MASTER_IER);
3674 3675 3676 3677

	return 0;
}

3678 3679 3680 3681 3682
static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
{
	/* These are interrupts we'll toggle with the ring mask register */
	uint32_t gt_interrupts[] = {
		GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3683 3684 3685
			GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
			GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
			GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3686
		GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3687 3688 3689
			GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
			GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
			GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3690
		0,
3691 3692
		GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
			GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3693 3694
		};

3695 3696 3697
	if (HAS_L3_DPF(dev_priv))
		gt_interrupts[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;

3698
	dev_priv->pm_irq_mask = 0xffffffff;
3699 3700
	GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
	GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3701 3702 3703 3704 3705
	/*
	 * RPS interrupts will get enabled/disabled on demand when RPS itself
	 * is enabled/disabled.
	 */
	GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
3706
	GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3707 3708 3709 3710
}

static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
{
3711 3712
	uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
	uint32_t de_pipe_enables;
3713 3714
	u32 de_port_masked = GEN8_AUX_CHANNEL_A;
	u32 de_port_enables;
3715
	u32 de_misc_masked = GEN8_DE_MISC_GSE;
3716
	enum pipe pipe;
3717

3718
	if (INTEL_INFO(dev_priv)->gen >= 9) {
3719 3720
		de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
				  GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3721 3722
		de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
				  GEN9_AUX_CHANNEL_D;
S
Shashank Sharma 已提交
3723
		if (IS_BROXTON(dev_priv))
3724 3725
			de_port_masked |= BXT_DE_PORT_GMBUS;
	} else {
3726 3727
		de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
				  GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3728
	}
3729 3730 3731 3732

	de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
					   GEN8_PIPE_FIFO_UNDERRUN;

3733
	de_port_enables = de_port_masked;
3734 3735 3736
	if (IS_BROXTON(dev_priv))
		de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
	else if (IS_BROADWELL(dev_priv))
3737 3738
		de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;

3739 3740 3741
	dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
	dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
	dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3742

3743
	for_each_pipe(dev_priv, pipe)
3744
		if (intel_display_power_is_enabled(dev_priv,
3745 3746 3747 3748
				POWER_DOMAIN_PIPE(pipe)))
			GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
					  dev_priv->de_irq_mask[pipe],
					  de_pipe_enables);
3749

3750
	GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3751
	GEN5_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
3752 3753 3754 3755
}

static int gen8_irq_postinstall(struct drm_device *dev)
{
3756
	struct drm_i915_private *dev_priv = to_i915(dev);
3757

3758 3759
	if (HAS_PCH_SPLIT(dev))
		ibx_irq_pre_postinstall(dev);
P
Paulo Zanoni 已提交
3760

3761 3762 3763
	gen8_gt_irq_postinstall(dev_priv);
	gen8_de_irq_postinstall(dev_priv);

3764 3765
	if (HAS_PCH_SPLIT(dev))
		ibx_irq_postinstall(dev);
3766

3767
	I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3768 3769 3770 3771 3772
	POSTING_READ(GEN8_MASTER_IRQ);

	return 0;
}

3773 3774
static int cherryview_irq_postinstall(struct drm_device *dev)
{
3775
	struct drm_i915_private *dev_priv = to_i915(dev);
3776 3777 3778

	gen8_gt_irq_postinstall(dev_priv);

3779
	spin_lock_irq(&dev_priv->irq_lock);
3780 3781
	if (dev_priv->display_irqs_enabled)
		vlv_display_irq_postinstall(dev_priv);
3782 3783
	spin_unlock_irq(&dev_priv->irq_lock);

3784
	I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3785 3786 3787 3788 3789
	POSTING_READ(GEN8_MASTER_IRQ);

	return 0;
}

3790 3791
static void gen8_irq_uninstall(struct drm_device *dev)
{
3792
	struct drm_i915_private *dev_priv = to_i915(dev);
3793 3794 3795 3796

	if (!dev_priv)
		return;

P
Paulo Zanoni 已提交
3797
	gen8_irq_reset(dev);
3798 3799
}

J
Jesse Barnes 已提交
3800 3801
static void valleyview_irq_uninstall(struct drm_device *dev)
{
3802
	struct drm_i915_private *dev_priv = to_i915(dev);
J
Jesse Barnes 已提交
3803 3804 3805 3806

	if (!dev_priv)
		return;

3807
	I915_WRITE(VLV_MASTER_IER, 0);
3808
	POSTING_READ(VLV_MASTER_IER);
3809

3810 3811
	gen5_gt_irq_reset(dev);

J
Jesse Barnes 已提交
3812
	I915_WRITE(HWSTAM, 0xffffffff);
3813

3814
	spin_lock_irq(&dev_priv->irq_lock);
3815 3816
	if (dev_priv->display_irqs_enabled)
		vlv_display_irq_reset(dev_priv);
3817
	spin_unlock_irq(&dev_priv->irq_lock);
J
Jesse Barnes 已提交
3818 3819
}

3820 3821
static void cherryview_irq_uninstall(struct drm_device *dev)
{
3822
	struct drm_i915_private *dev_priv = to_i915(dev);
3823 3824 3825 3826 3827 3828 3829

	if (!dev_priv)
		return;

	I915_WRITE(GEN8_MASTER_IRQ, 0);
	POSTING_READ(GEN8_MASTER_IRQ);

3830
	gen8_gt_irq_reset(dev_priv);
3831

3832
	GEN5_IRQ_RESET(GEN8_PCU_);
3833

3834
	spin_lock_irq(&dev_priv->irq_lock);
3835 3836
	if (dev_priv->display_irqs_enabled)
		vlv_display_irq_reset(dev_priv);
3837
	spin_unlock_irq(&dev_priv->irq_lock);
3838 3839
}

3840
static void ironlake_irq_uninstall(struct drm_device *dev)
3841
{
3842
	struct drm_i915_private *dev_priv = to_i915(dev);
3843 3844 3845 3846

	if (!dev_priv)
		return;

P
Paulo Zanoni 已提交
3847
	ironlake_irq_reset(dev);
3848 3849
}

3850
static void i8xx_irq_preinstall(struct drm_device * dev)
L
Linus Torvalds 已提交
3851
{
3852
	struct drm_i915_private *dev_priv = to_i915(dev);
3853
	int pipe;
3854

3855
	for_each_pipe(dev_priv, pipe)
3856
		I915_WRITE(PIPESTAT(pipe), 0);
3857 3858 3859
	I915_WRITE16(IMR, 0xffff);
	I915_WRITE16(IER, 0x0);
	POSTING_READ16(IER);
C
Chris Wilson 已提交
3860 3861 3862 3863
}

static int i8xx_irq_postinstall(struct drm_device *dev)
{
3864
	struct drm_i915_private *dev_priv = to_i915(dev);
C
Chris Wilson 已提交
3865 3866 3867 3868 3869 3870 3871 3872 3873

	I915_WRITE16(EMR,
		     ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));

	/* Unmask the interrupts that we always want on. */
	dev_priv->irq_mask =
		~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3874
		  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
C
Chris Wilson 已提交
3875 3876 3877 3878 3879 3880 3881 3882
	I915_WRITE16(IMR, dev_priv->irq_mask);

	I915_WRITE16(IER,
		     I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		     I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		     I915_USER_INTERRUPT);
	POSTING_READ16(IER);

3883 3884
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
3885
	spin_lock_irq(&dev_priv->irq_lock);
3886 3887
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3888
	spin_unlock_irq(&dev_priv->irq_lock);
3889

C
Chris Wilson 已提交
3890 3891 3892
	return 0;
}

3893 3894 3895 3896 3897 3898 3899 3900 3901 3902 3903 3904 3905 3906 3907 3908 3909 3910 3911 3912 3913 3914 3915 3916 3917 3918 3919 3920 3921 3922 3923
/*
 * Returns true when a page flip has completed.
 */
static bool i8xx_handle_vblank(struct drm_i915_private *dev_priv,
			       int plane, int pipe, u32 iir)
{
	u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);

	if (!intel_pipe_handle_vblank(dev_priv, pipe))
		return false;

	if ((iir & flip_pending) == 0)
		goto check_page_flip;

	/* We detect FlipDone by looking for the change in PendingFlip from '1'
	 * to '0' on the following vblank, i.e. IIR has the Pendingflip
	 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
	 * the flip is completed (no longer pending). Since this doesn't raise
	 * an interrupt per se, we watch for the change at vblank.
	 */
	if (I915_READ16(ISR) & flip_pending)
		goto check_page_flip;

	intel_finish_page_flip_cs(dev_priv, pipe);
	return true;

check_page_flip:
	intel_check_page_flip(dev_priv, pipe);
	return false;
}

3924
static irqreturn_t i8xx_irq_handler(int irq, void *arg)
C
Chris Wilson 已提交
3925
{
3926
	struct drm_device *dev = arg;
3927
	struct drm_i915_private *dev_priv = to_i915(dev);
C
Chris Wilson 已提交
3928 3929 3930 3931 3932 3933
	u16 iir, new_iir;
	u32 pipe_stats[2];
	int pipe;
	u16 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3934
	irqreturn_t ret;
C
Chris Wilson 已提交
3935

3936 3937 3938
	if (!intel_irqs_enabled(dev_priv))
		return IRQ_NONE;

3939 3940 3941 3942
	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
	disable_rpm_wakeref_asserts(dev_priv);

	ret = IRQ_NONE;
C
Chris Wilson 已提交
3943 3944
	iir = I915_READ16(IIR);
	if (iir == 0)
3945
		goto out;
C
Chris Wilson 已提交
3946 3947 3948 3949 3950 3951 3952

	while (iir & ~flip_mask) {
		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
3953
		spin_lock(&dev_priv->irq_lock);
C
Chris Wilson 已提交
3954
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3955
			DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
C
Chris Wilson 已提交
3956

3957
		for_each_pipe(dev_priv, pipe) {
3958
			i915_reg_t reg = PIPESTAT(pipe);
C
Chris Wilson 已提交
3959 3960 3961 3962 3963
			pipe_stats[pipe] = I915_READ(reg);

			/*
			 * Clear the PIPE*STAT regs before the IIR
			 */
3964
			if (pipe_stats[pipe] & 0x8000ffff)
C
Chris Wilson 已提交
3965 3966
				I915_WRITE(reg, pipe_stats[pipe]);
		}
3967
		spin_unlock(&dev_priv->irq_lock);
C
Chris Wilson 已提交
3968 3969 3970 3971 3972

		I915_WRITE16(IIR, iir & ~flip_mask);
		new_iir = I915_READ16(IIR); /* Flush posted writes */

		if (iir & I915_USER_INTERRUPT)
3973
			notify_ring(&dev_priv->engine[RCS]);
C
Chris Wilson 已提交
3974

3975
		for_each_pipe(dev_priv, pipe) {
3976 3977 3978 3979 3980 3981 3982
			int plane = pipe;
			if (HAS_FBC(dev_priv))
				plane = !plane;

			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
			    i8xx_handle_vblank(dev_priv, plane, pipe, iir))
				flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
C
Chris Wilson 已提交
3983

3984
			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3985
				i9xx_pipe_crc_irq_handler(dev_priv, pipe);
3986

3987 3988 3989
			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
				intel_cpu_fifo_underrun_irq_handler(dev_priv,
								    pipe);
3990
		}
C
Chris Wilson 已提交
3991 3992 3993

		iir = new_iir;
	}
3994 3995 3996 3997
	ret = IRQ_HANDLED;

out:
	enable_rpm_wakeref_asserts(dev_priv);
C
Chris Wilson 已提交
3998

3999
	return ret;
C
Chris Wilson 已提交
4000 4001 4002 4003
}

static void i8xx_irq_uninstall(struct drm_device * dev)
{
4004
	struct drm_i915_private *dev_priv = to_i915(dev);
C
Chris Wilson 已提交
4005 4006
	int pipe;

4007
	for_each_pipe(dev_priv, pipe) {
C
Chris Wilson 已提交
4008 4009 4010 4011 4012 4013 4014 4015 4016
		/* Clear enable bits; then clear status bits */
		I915_WRITE(PIPESTAT(pipe), 0);
		I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
	}
	I915_WRITE16(IMR, 0xffff);
	I915_WRITE16(IER, 0x0);
	I915_WRITE16(IIR, I915_READ16(IIR));
}

4017 4018
static void i915_irq_preinstall(struct drm_device * dev)
{
4019
	struct drm_i915_private *dev_priv = to_i915(dev);
4020 4021 4022
	int pipe;

	if (I915_HAS_HOTPLUG(dev)) {
4023
		i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4024 4025 4026
		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	}

4027
	I915_WRITE16(HWSTAM, 0xeffe);
4028
	for_each_pipe(dev_priv, pipe)
4029 4030 4031 4032 4033 4034 4035 4036
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);
	POSTING_READ(IER);
}

static int i915_irq_postinstall(struct drm_device *dev)
{
4037
	struct drm_i915_private *dev_priv = to_i915(dev);
4038
	u32 enable_mask;
4039

4040 4041 4042 4043 4044 4045 4046 4047
	I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));

	/* Unmask the interrupts that we always want on. */
	dev_priv->irq_mask =
		~(I915_ASLE_INTERRUPT |
		  I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4048
		  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4049 4050 4051 4052 4053 4054 4055

	enable_mask =
		I915_ASLE_INTERRUPT |
		I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		I915_USER_INTERRUPT;

4056
	if (I915_HAS_HOTPLUG(dev)) {
4057
		i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4058 4059
		POSTING_READ(PORT_HOTPLUG_EN);

4060 4061 4062 4063 4064 4065 4066 4067 4068 4069
		/* Enable in IER... */
		enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
		/* and unmask in IMR */
		dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
	}

	I915_WRITE(IMR, dev_priv->irq_mask);
	I915_WRITE(IER, enable_mask);
	POSTING_READ(IER);

4070
	i915_enable_asle_pipestat(dev_priv);
4071

4072 4073
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
4074
	spin_lock_irq(&dev_priv->irq_lock);
4075 4076
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4077
	spin_unlock_irq(&dev_priv->irq_lock);
4078

4079 4080 4081
	return 0;
}

4082 4083 4084 4085 4086 4087 4088 4089 4090 4091 4092 4093 4094 4095 4096 4097 4098 4099 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 4110 4111 4112
/*
 * Returns true when a page flip has completed.
 */
static bool i915_handle_vblank(struct drm_i915_private *dev_priv,
			       int plane, int pipe, u32 iir)
{
	u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);

	if (!intel_pipe_handle_vblank(dev_priv, pipe))
		return false;

	if ((iir & flip_pending) == 0)
		goto check_page_flip;

	/* We detect FlipDone by looking for the change in PendingFlip from '1'
	 * to '0' on the following vblank, i.e. IIR has the Pendingflip
	 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
	 * the flip is completed (no longer pending). Since this doesn't raise
	 * an interrupt per se, we watch for the change at vblank.
	 */
	if (I915_READ(ISR) & flip_pending)
		goto check_page_flip;

	intel_finish_page_flip_cs(dev_priv, pipe);
	return true;

check_page_flip:
	intel_check_page_flip(dev_priv, pipe);
	return false;
}

4113
static irqreturn_t i915_irq_handler(int irq, void *arg)
4114
{
4115
	struct drm_device *dev = arg;
4116
	struct drm_i915_private *dev_priv = to_i915(dev);
4117
	u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
4118 4119 4120 4121
	u32 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
	int pipe, ret = IRQ_NONE;
4122

4123 4124 4125
	if (!intel_irqs_enabled(dev_priv))
		return IRQ_NONE;

4126 4127 4128
	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
	disable_rpm_wakeref_asserts(dev_priv);

4129
	iir = I915_READ(IIR);
4130 4131
	do {
		bool irq_received = (iir & ~flip_mask) != 0;
4132
		bool blc_event = false;
4133 4134 4135 4136 4137 4138

		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
4139
		spin_lock(&dev_priv->irq_lock);
4140
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4141
			DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4142

4143
		for_each_pipe(dev_priv, pipe) {
4144
			i915_reg_t reg = PIPESTAT(pipe);
4145 4146
			pipe_stats[pipe] = I915_READ(reg);

4147
			/* Clear the PIPE*STAT regs before the IIR */
4148 4149
			if (pipe_stats[pipe] & 0x8000ffff) {
				I915_WRITE(reg, pipe_stats[pipe]);
4150
				irq_received = true;
4151 4152
			}
		}
4153
		spin_unlock(&dev_priv->irq_lock);
4154 4155 4156 4157 4158

		if (!irq_received)
			break;

		/* Consume port.  Then clear IIR or we'll miss events */
4159
		if (I915_HAS_HOTPLUG(dev_priv) &&
4160 4161 4162
		    iir & I915_DISPLAY_PORT_INTERRUPT) {
			u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
			if (hotplug_status)
4163
				i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4164
		}
4165

4166
		I915_WRITE(IIR, iir & ~flip_mask);
4167 4168 4169
		new_iir = I915_READ(IIR); /* Flush posted writes */

		if (iir & I915_USER_INTERRUPT)
4170
			notify_ring(&dev_priv->engine[RCS]);
4171

4172
		for_each_pipe(dev_priv, pipe) {
4173 4174 4175 4176 4177 4178 4179
			int plane = pipe;
			if (HAS_FBC(dev_priv))
				plane = !plane;

			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
			    i915_handle_vblank(dev_priv, plane, pipe, iir))
				flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4180 4181 4182

			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
				blc_event = true;
4183 4184

			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4185
				i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4186

4187 4188 4189
			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
				intel_cpu_fifo_underrun_irq_handler(dev_priv,
								    pipe);
4190 4191 4192
		}

		if (blc_event || (iir & I915_ASLE_INTERRUPT))
4193
			intel_opregion_asle_intr(dev_priv);
4194 4195 4196 4197 4198 4199 4200 4201 4202 4203 4204 4205 4206 4207 4208 4209

		/* With MSI, interrupts are only generated when iir
		 * transitions from zero to nonzero.  If another bit got
		 * set while we were handling the existing iir bits, then
		 * we would never get another interrupt.
		 *
		 * This is fine on non-MSI as well, as if we hit this path
		 * we avoid exiting the interrupt handler only to generate
		 * another one.
		 *
		 * Note that for MSI this could cause a stray interrupt report
		 * if an interrupt landed in the time between writing IIR and
		 * the posting read.  This should be rare enough to never
		 * trigger the 99% of 100,000 interrupts test for disabling
		 * stray interrupts.
		 */
4210
		ret = IRQ_HANDLED;
4211
		iir = new_iir;
4212
	} while (iir & ~flip_mask);
4213

4214 4215
	enable_rpm_wakeref_asserts(dev_priv);

4216 4217 4218 4219 4220
	return ret;
}

static void i915_irq_uninstall(struct drm_device * dev)
{
4221
	struct drm_i915_private *dev_priv = to_i915(dev);
4222 4223 4224
	int pipe;

	if (I915_HAS_HOTPLUG(dev)) {
4225
		i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4226 4227 4228
		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	}

4229
	I915_WRITE16(HWSTAM, 0xffff);
4230
	for_each_pipe(dev_priv, pipe) {
4231
		/* Clear enable bits; then clear status bits */
4232
		I915_WRITE(PIPESTAT(pipe), 0);
4233 4234
		I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
	}
4235 4236 4237 4238 4239 4240 4241 4242
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);

	I915_WRITE(IIR, I915_READ(IIR));
}

static void i965_irq_preinstall(struct drm_device * dev)
{
4243
	struct drm_i915_private *dev_priv = to_i915(dev);
4244 4245
	int pipe;

4246
	i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4247
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4248 4249

	I915_WRITE(HWSTAM, 0xeffe);
4250
	for_each_pipe(dev_priv, pipe)
4251 4252 4253 4254 4255 4256 4257 4258
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);
	POSTING_READ(IER);
}

static int i965_irq_postinstall(struct drm_device *dev)
{
4259
	struct drm_i915_private *dev_priv = to_i915(dev);
4260
	u32 enable_mask;
4261 4262 4263
	u32 error_mask;

	/* Unmask the interrupts that we always want on. */
4264
	dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4265
			       I915_DISPLAY_PORT_INTERRUPT |
4266 4267 4268 4269 4270 4271 4272
			       I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
			       I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
			       I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
			       I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
			       I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);

	enable_mask = ~dev_priv->irq_mask;
4273 4274
	enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
			 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4275 4276
	enable_mask |= I915_USER_INTERRUPT;

4277
	if (IS_G4X(dev_priv))
4278
		enable_mask |= I915_BSD_USER_INTERRUPT;
4279

4280 4281
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
4282
	spin_lock_irq(&dev_priv->irq_lock);
4283 4284 4285
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4286
	spin_unlock_irq(&dev_priv->irq_lock);
4287 4288 4289 4290 4291

	/*
	 * Enable some error detection, note the instruction error mask
	 * bit is reserved, so we leave it masked.
	 */
4292
	if (IS_G4X(dev_priv)) {
4293 4294 4295 4296 4297 4298 4299 4300 4301 4302 4303 4304 4305 4306
		error_mask = ~(GM45_ERROR_PAGE_TABLE |
			       GM45_ERROR_MEM_PRIV |
			       GM45_ERROR_CP_PRIV |
			       I915_ERROR_MEMORY_REFRESH);
	} else {
		error_mask = ~(I915_ERROR_PAGE_TABLE |
			       I915_ERROR_MEMORY_REFRESH);
	}
	I915_WRITE(EMR, error_mask);

	I915_WRITE(IMR, dev_priv->irq_mask);
	I915_WRITE(IER, enable_mask);
	POSTING_READ(IER);

4307
	i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4308 4309
	POSTING_READ(PORT_HOTPLUG_EN);

4310
	i915_enable_asle_pipestat(dev_priv);
4311 4312 4313 4314

	return 0;
}

4315
static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
4316 4317 4318
{
	u32 hotplug_en;

4319 4320
	assert_spin_locked(&dev_priv->irq_lock);

4321 4322
	/* Note HDMI and DP share hotplug bits */
	/* enable bits are the same for all generations */
4323
	hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
4324 4325 4326 4327
	/* Programming the CRT detection parameters tends
	   to generate a spurious hotplug event about three
	   seconds later.  So just do it once.
	*/
4328
	if (IS_G4X(dev_priv))
4329 4330 4331 4332
		hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
	hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;

	/* Ignore TV since it's buggy */
4333
	i915_hotplug_interrupt_update_locked(dev_priv,
4334 4335 4336 4337
					     HOTPLUG_INT_EN_MASK |
					     CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
					     CRT_HOTPLUG_ACTIVATION_PERIOD_64,
					     hotplug_en);
4338 4339
}

4340
static irqreturn_t i965_irq_handler(int irq, void *arg)
4341
{
4342
	struct drm_device *dev = arg;
4343
	struct drm_i915_private *dev_priv = to_i915(dev);
4344 4345 4346
	u32 iir, new_iir;
	u32 pipe_stats[I915_MAX_PIPES];
	int ret = IRQ_NONE, pipe;
4347 4348 4349
	u32 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4350

4351 4352 4353
	if (!intel_irqs_enabled(dev_priv))
		return IRQ_NONE;

4354 4355 4356
	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
	disable_rpm_wakeref_asserts(dev_priv);

4357 4358 4359
	iir = I915_READ(IIR);

	for (;;) {
4360
		bool irq_received = (iir & ~flip_mask) != 0;
4361 4362
		bool blc_event = false;

4363 4364 4365 4366 4367
		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
4368
		spin_lock(&dev_priv->irq_lock);
4369
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4370
			DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4371

4372
		for_each_pipe(dev_priv, pipe) {
4373
			i915_reg_t reg = PIPESTAT(pipe);
4374 4375 4376 4377 4378 4379 4380
			pipe_stats[pipe] = I915_READ(reg);

			/*
			 * Clear the PIPE*STAT regs before the IIR
			 */
			if (pipe_stats[pipe] & 0x8000ffff) {
				I915_WRITE(reg, pipe_stats[pipe]);
4381
				irq_received = true;
4382 4383
			}
		}
4384
		spin_unlock(&dev_priv->irq_lock);
4385 4386 4387 4388 4389 4390 4391

		if (!irq_received)
			break;

		ret = IRQ_HANDLED;

		/* Consume port.  Then clear IIR or we'll miss events */
4392 4393 4394
		if (iir & I915_DISPLAY_PORT_INTERRUPT) {
			u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
			if (hotplug_status)
4395
				i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4396
		}
4397

4398
		I915_WRITE(IIR, iir & ~flip_mask);
4399 4400 4401
		new_iir = I915_READ(IIR); /* Flush posted writes */

		if (iir & I915_USER_INTERRUPT)
4402
			notify_ring(&dev_priv->engine[RCS]);
4403
		if (iir & I915_BSD_USER_INTERRUPT)
4404
			notify_ring(&dev_priv->engine[VCS]);
4405

4406
		for_each_pipe(dev_priv, pipe) {
4407 4408 4409
			if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
			    i915_handle_vblank(dev_priv, pipe, pipe, iir))
				flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4410 4411 4412

			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
				blc_event = true;
4413 4414

			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4415
				i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4416

4417 4418
			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
				intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4419
		}
4420 4421

		if (blc_event || (iir & I915_ASLE_INTERRUPT))
4422
			intel_opregion_asle_intr(dev_priv);
4423

4424
		if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4425
			gmbus_irq_handler(dev_priv);
4426

4427 4428 4429 4430 4431 4432 4433 4434 4435 4436 4437 4438 4439 4440 4441 4442 4443 4444
		/* With MSI, interrupts are only generated when iir
		 * transitions from zero to nonzero.  If another bit got
		 * set while we were handling the existing iir bits, then
		 * we would never get another interrupt.
		 *
		 * This is fine on non-MSI as well, as if we hit this path
		 * we avoid exiting the interrupt handler only to generate
		 * another one.
		 *
		 * Note that for MSI this could cause a stray interrupt report
		 * if an interrupt landed in the time between writing IIR and
		 * the posting read.  This should be rare enough to never
		 * trigger the 99% of 100,000 interrupts test for disabling
		 * stray interrupts.
		 */
		iir = new_iir;
	}

4445 4446
	enable_rpm_wakeref_asserts(dev_priv);

4447 4448 4449 4450 4451
	return ret;
}

static void i965_irq_uninstall(struct drm_device * dev)
{
4452
	struct drm_i915_private *dev_priv = to_i915(dev);
4453 4454 4455 4456 4457
	int pipe;

	if (!dev_priv)
		return;

4458
	i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4459
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4460 4461

	I915_WRITE(HWSTAM, 0xffffffff);
4462
	for_each_pipe(dev_priv, pipe)
4463 4464 4465 4466
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);

4467
	for_each_pipe(dev_priv, pipe)
4468 4469 4470 4471 4472
		I915_WRITE(PIPESTAT(pipe),
			   I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
	I915_WRITE(IIR, I915_READ(IIR));
}

4473 4474 4475 4476 4477 4478 4479
/**
 * intel_irq_init - initializes irq support
 * @dev_priv: i915 device instance
 *
 * This function initializes all the irq support including work items, timers
 * and all the vtables. It does not setup the interrupt itself though.
 */
4480
void intel_irq_init(struct drm_i915_private *dev_priv)
4481
{
4482
	struct drm_device *dev = &dev_priv->drm;
4483

4484 4485
	intel_hpd_init_work(dev_priv);

4486
	INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4487
	INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4488

4489
	/* Let's track the enabled rps events */
4490
	if (IS_VALLEYVIEW(dev_priv))
4491
		/* WaGsvRC0ResidencyMethod:vlv */
4492
		dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
4493 4494
	else
		dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4495

4496 4497 4498 4499 4500 4501 4502 4503 4504 4505 4506 4507 4508 4509
	dev_priv->rps.pm_intr_keep = 0;

	/*
	 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
	 * if GEN6_PM_UP_EI_EXPIRED is masked.
	 *
	 * TODO: verify if this can be reproduced on VLV,CHV.
	 */
	if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
		dev_priv->rps.pm_intr_keep |= GEN6_PM_RP_UP_EI_EXPIRED;

	if (INTEL_INFO(dev_priv)->gen >= 8)
		dev_priv->rps.pm_intr_keep |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;

4510 4511
	INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
			  i915_hangcheck_elapsed);
4512

4513
	if (IS_GEN2(dev_priv)) {
4514
		/* Gen2 doesn't have a hardware frame counter */
4515
		dev->max_vblank_count = 0;
4516
		dev->driver->get_vblank_counter = drm_vblank_no_hw_counter;
4517
	} else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4518
		dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4519
		dev->driver->get_vblank_counter = g4x_get_vblank_counter;
4520 4521 4522
	} else {
		dev->driver->get_vblank_counter = i915_get_vblank_counter;
		dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4523 4524
	}

4525 4526 4527 4528 4529
	/*
	 * Opt out of the vblank disable timer on everything except gen2.
	 * Gen2 doesn't have a hardware frame counter and so depends on
	 * vblank interrupts to produce sane vblank seuquence numbers.
	 */
4530
	if (!IS_GEN2(dev_priv))
4531 4532
		dev->vblank_disable_immediate = true;

4533 4534
	dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
	dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4535

4536
	if (IS_CHERRYVIEW(dev_priv)) {
4537 4538 4539 4540 4541 4542 4543
		dev->driver->irq_handler = cherryview_irq_handler;
		dev->driver->irq_preinstall = cherryview_irq_preinstall;
		dev->driver->irq_postinstall = cherryview_irq_postinstall;
		dev->driver->irq_uninstall = cherryview_irq_uninstall;
		dev->driver->enable_vblank = valleyview_enable_vblank;
		dev->driver->disable_vblank = valleyview_disable_vblank;
		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4544
	} else if (IS_VALLEYVIEW(dev_priv)) {
J
Jesse Barnes 已提交
4545 4546 4547 4548 4549 4550
		dev->driver->irq_handler = valleyview_irq_handler;
		dev->driver->irq_preinstall = valleyview_irq_preinstall;
		dev->driver->irq_postinstall = valleyview_irq_postinstall;
		dev->driver->irq_uninstall = valleyview_irq_uninstall;
		dev->driver->enable_vblank = valleyview_enable_vblank;
		dev->driver->disable_vblank = valleyview_disable_vblank;
4551
		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4552
	} else if (INTEL_INFO(dev_priv)->gen >= 8) {
4553
		dev->driver->irq_handler = gen8_irq_handler;
4554
		dev->driver->irq_preinstall = gen8_irq_reset;
4555 4556 4557 4558
		dev->driver->irq_postinstall = gen8_irq_postinstall;
		dev->driver->irq_uninstall = gen8_irq_uninstall;
		dev->driver->enable_vblank = gen8_enable_vblank;
		dev->driver->disable_vblank = gen8_disable_vblank;
4559
		if (IS_BROXTON(dev))
4560
			dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4561
		else if (HAS_PCH_SPT(dev) || HAS_PCH_KBP(dev))
4562 4563
			dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
		else
4564
			dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4565 4566
	} else if (HAS_PCH_SPLIT(dev)) {
		dev->driver->irq_handler = ironlake_irq_handler;
4567
		dev->driver->irq_preinstall = ironlake_irq_reset;
4568 4569 4570 4571
		dev->driver->irq_postinstall = ironlake_irq_postinstall;
		dev->driver->irq_uninstall = ironlake_irq_uninstall;
		dev->driver->enable_vblank = ironlake_enable_vblank;
		dev->driver->disable_vblank = ironlake_disable_vblank;
4572
		dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4573
	} else {
4574
		if (IS_GEN2(dev_priv)) {
C
Chris Wilson 已提交
4575 4576 4577 4578
			dev->driver->irq_preinstall = i8xx_irq_preinstall;
			dev->driver->irq_postinstall = i8xx_irq_postinstall;
			dev->driver->irq_handler = i8xx_irq_handler;
			dev->driver->irq_uninstall = i8xx_irq_uninstall;
4579
		} else if (IS_GEN3(dev_priv)) {
4580 4581 4582 4583
			dev->driver->irq_preinstall = i915_irq_preinstall;
			dev->driver->irq_postinstall = i915_irq_postinstall;
			dev->driver->irq_uninstall = i915_irq_uninstall;
			dev->driver->irq_handler = i915_irq_handler;
C
Chris Wilson 已提交
4584
		} else {
4585 4586 4587 4588
			dev->driver->irq_preinstall = i965_irq_preinstall;
			dev->driver->irq_postinstall = i965_irq_postinstall;
			dev->driver->irq_uninstall = i965_irq_uninstall;
			dev->driver->irq_handler = i965_irq_handler;
C
Chris Wilson 已提交
4589
		}
4590 4591
		if (I915_HAS_HOTPLUG(dev_priv))
			dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4592 4593 4594 4595
		dev->driver->enable_vblank = i915_enable_vblank;
		dev->driver->disable_vblank = i915_disable_vblank;
	}
}
4596

4597 4598 4599 4600 4601 4602 4603 4604 4605 4606 4607
/**
 * intel_irq_install - enables the hardware interrupt
 * @dev_priv: i915 device instance
 *
 * This function enables the hardware interrupt handling, but leaves the hotplug
 * handling still disabled. It is called after intel_irq_init().
 *
 * In the driver load and resume code we need working interrupts in a few places
 * but don't want to deal with the hassle of concurrent probe and hotplug
 * workers. Hence the split into this two-stage approach.
 */
4608 4609 4610 4611 4612 4613 4614 4615 4616
int intel_irq_install(struct drm_i915_private *dev_priv)
{
	/*
	 * We enable some interrupt sources in our postinstall hooks, so mark
	 * interrupts as enabled _before_ actually enabling them to avoid
	 * special cases in our ordering checks.
	 */
	dev_priv->pm.irqs_enabled = true;

4617
	return drm_irq_install(&dev_priv->drm, dev_priv->drm.pdev->irq);
4618 4619
}

4620 4621 4622 4623 4624 4625 4626
/**
 * intel_irq_uninstall - finilizes all irq handling
 * @dev_priv: i915 device instance
 *
 * This stops interrupt and hotplug handling and unregisters and frees all
 * resources acquired in the init functions.
 */
4627 4628
void intel_irq_uninstall(struct drm_i915_private *dev_priv)
{
4629
	drm_irq_uninstall(&dev_priv->drm);
4630 4631 4632 4633
	intel_hpd_cancel_work(dev_priv);
	dev_priv->pm.irqs_enabled = false;
}

4634 4635 4636 4637 4638 4639 4640
/**
 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
 * @dev_priv: i915 device instance
 *
 * This function is used to disable interrupts at runtime, both in the runtime
 * pm and the system suspend/resume code.
 */
4641
void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4642
{
4643
	dev_priv->drm.driver->irq_uninstall(&dev_priv->drm);
4644
	dev_priv->pm.irqs_enabled = false;
4645
	synchronize_irq(dev_priv->drm.irq);
4646 4647
}

4648 4649 4650 4651 4652 4653 4654
/**
 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
 * @dev_priv: i915 device instance
 *
 * This function is used to enable interrupts at runtime, both in the runtime
 * pm and the system suspend/resume code.
 */
4655
void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4656
{
4657
	dev_priv->pm.irqs_enabled = true;
4658 4659
	dev_priv->drm.driver->irq_preinstall(&dev_priv->drm);
	dev_priv->drm.driver->irq_postinstall(&dev_priv->drm);
4660
}