i915_irq.c 98.4 KB
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/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
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 */
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/*
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

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#include <linux/sysrq.h>
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#include <linux/slab.h>
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#include <linux/circ_buf.h>
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#include <drm/drmP.h>
#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#include "i915_trace.h"
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#include "intel_drv.h"
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static const u32 hpd_ibx[] = {
	[HPD_CRT] = SDE_CRT_HOTPLUG,
	[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
	[HPD_PORT_B] = SDE_PORTB_HOTPLUG,
	[HPD_PORT_C] = SDE_PORTC_HOTPLUG,
	[HPD_PORT_D] = SDE_PORTD_HOTPLUG
};

static const u32 hpd_cpt[] = {
	[HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
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	[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
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	[HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
	[HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
	[HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
};

static const u32 hpd_mask_i915[] = {
	[HPD_CRT] = CRT_HOTPLUG_INT_EN,
	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
	[HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
	[HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
	[HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
};

static const u32 hpd_status_gen4[] = {
	[HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
	[HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
	[HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
	[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
};

static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
	[HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
	[HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
	[HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
	[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
};

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/* For display hotplug interrupt */
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static void
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ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
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{
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	assert_spin_locked(&dev_priv->irq_lock);

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	if (dev_priv->pc8.irqs_disabled) {
		WARN(1, "IRQs disabled\n");
		dev_priv->pc8.regsave.deimr &= ~mask;
		return;
	}

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	if ((dev_priv->irq_mask & mask) != 0) {
		dev_priv->irq_mask &= ~mask;
		I915_WRITE(DEIMR, dev_priv->irq_mask);
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		POSTING_READ(DEIMR);
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	}
}

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static void
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ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
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{
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	assert_spin_locked(&dev_priv->irq_lock);

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	if (dev_priv->pc8.irqs_disabled) {
		WARN(1, "IRQs disabled\n");
		dev_priv->pc8.regsave.deimr |= mask;
		return;
	}

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	if ((dev_priv->irq_mask & mask) != mask) {
		dev_priv->irq_mask |= mask;
		I915_WRITE(DEIMR, dev_priv->irq_mask);
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		POSTING_READ(DEIMR);
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	}
}

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/**
 * ilk_update_gt_irq - update GTIMR
 * @dev_priv: driver private
 * @interrupt_mask: mask of interrupt bits to update
 * @enabled_irq_mask: mask of interrupt bits to enable
 */
static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
			      uint32_t interrupt_mask,
			      uint32_t enabled_irq_mask)
{
	assert_spin_locked(&dev_priv->irq_lock);

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	if (dev_priv->pc8.irqs_disabled) {
		WARN(1, "IRQs disabled\n");
		dev_priv->pc8.regsave.gtimr &= ~interrupt_mask;
		dev_priv->pc8.regsave.gtimr |= (~enabled_irq_mask &
						interrupt_mask);
		return;
	}

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	dev_priv->gt_irq_mask &= ~interrupt_mask;
	dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
	POSTING_READ(GTIMR);
}

void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
{
	ilk_update_gt_irq(dev_priv, mask, mask);
}

void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
{
	ilk_update_gt_irq(dev_priv, mask, 0);
}

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/**
  * snb_update_pm_irq - update GEN6_PMIMR
  * @dev_priv: driver private
  * @interrupt_mask: mask of interrupt bits to update
  * @enabled_irq_mask: mask of interrupt bits to enable
  */
static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
			      uint32_t interrupt_mask,
			      uint32_t enabled_irq_mask)
{
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	uint32_t new_val;
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	assert_spin_locked(&dev_priv->irq_lock);

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	if (dev_priv->pc8.irqs_disabled) {
		WARN(1, "IRQs disabled\n");
		dev_priv->pc8.regsave.gen6_pmimr &= ~interrupt_mask;
		dev_priv->pc8.regsave.gen6_pmimr |= (~enabled_irq_mask &
						     interrupt_mask);
		return;
	}

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	new_val = dev_priv->pm_irq_mask;
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	new_val &= ~interrupt_mask;
	new_val |= (~enabled_irq_mask & interrupt_mask);

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	if (new_val != dev_priv->pm_irq_mask) {
		dev_priv->pm_irq_mask = new_val;
		I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
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		POSTING_READ(GEN6_PMIMR);
	}
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}

void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
{
	snb_update_pm_irq(dev_priv, mask, mask);
}

void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
{
	snb_update_pm_irq(dev_priv, mask, 0);
}

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static bool ivb_can_enable_err_int(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *crtc;
	enum pipe pipe;

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	assert_spin_locked(&dev_priv->irq_lock);

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	for_each_pipe(pipe) {
		crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);

		if (crtc->cpu_fifo_underrun_disabled)
			return false;
	}

	return true;
}

static bool cpt_can_enable_serr_int(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum pipe pipe;
	struct intel_crtc *crtc;

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	assert_spin_locked(&dev_priv->irq_lock);

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	for_each_pipe(pipe) {
		crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);

		if (crtc->pch_fifo_underrun_disabled)
			return false;
	}

	return true;
}

static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
						 enum pipe pipe, bool enable)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
					  DE_PIPEB_FIFO_UNDERRUN;

	if (enable)
		ironlake_enable_display_irq(dev_priv, bit);
	else
		ironlake_disable_display_irq(dev_priv, bit);
}

static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
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						  enum pipe pipe, bool enable)
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{
	struct drm_i915_private *dev_priv = dev->dev_private;
	if (enable) {
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		I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));

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		if (!ivb_can_enable_err_int(dev))
			return;

		ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
	} else {
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		bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);

		/* Change the state _after_ we've read out the current one. */
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		ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
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		if (!was_enabled &&
		    (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
			DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
				      pipe_name(pipe));
		}
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	}
}

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/**
 * ibx_display_interrupt_update - update SDEIMR
 * @dev_priv: driver private
 * @interrupt_mask: mask of interrupt bits to update
 * @enabled_irq_mask: mask of interrupt bits to enable
 */
static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
					 uint32_t interrupt_mask,
					 uint32_t enabled_irq_mask)
{
	uint32_t sdeimr = I915_READ(SDEIMR);
	sdeimr &= ~interrupt_mask;
	sdeimr |= (~enabled_irq_mask & interrupt_mask);

	assert_spin_locked(&dev_priv->irq_lock);

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	if (dev_priv->pc8.irqs_disabled &&
	    (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) {
		WARN(1, "IRQs disabled\n");
		dev_priv->pc8.regsave.sdeimr &= ~interrupt_mask;
		dev_priv->pc8.regsave.sdeimr |= (~enabled_irq_mask &
						 interrupt_mask);
		return;
	}

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	I915_WRITE(SDEIMR, sdeimr);
	POSTING_READ(SDEIMR);
}
#define ibx_enable_display_interrupt(dev_priv, bits) \
	ibx_display_interrupt_update((dev_priv), (bits), (bits))
#define ibx_disable_display_interrupt(dev_priv, bits) \
	ibx_display_interrupt_update((dev_priv), (bits), 0)

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static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
					    enum transcoder pch_transcoder,
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					    bool enable)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
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	uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
		       SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
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	if (enable)
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		ibx_enable_display_interrupt(dev_priv, bit);
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	else
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		ibx_disable_display_interrupt(dev_priv, bit);
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}

static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
					    enum transcoder pch_transcoder,
					    bool enable)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (enable) {
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		I915_WRITE(SERR_INT,
			   SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));

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		if (!cpt_can_enable_serr_int(dev))
			return;

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		ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
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	} else {
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		uint32_t tmp = I915_READ(SERR_INT);
		bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);

		/* Change the state _after_ we've read out the current one. */
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		ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
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		if (!was_enabled &&
		    (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
			DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
				      transcoder_name(pch_transcoder));
		}
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	}
}

/**
 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
 * @dev: drm device
 * @pipe: pipe
 * @enable: true if we want to report FIFO underrun errors, false otherwise
 *
 * This function makes us disable or enable CPU fifo underruns for a specific
 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
 * reporting for one pipe may also disable all the other CPU error interruts for
 * the other pipes, due to the fact that there's just one interrupt mask/enable
 * bit for all the pipes.
 *
 * Returns the previous state of underrun reporting.
 */
bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
					   enum pipe pipe, bool enable)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	unsigned long flags;
	bool ret;

	spin_lock_irqsave(&dev_priv->irq_lock, flags);

	ret = !intel_crtc->cpu_fifo_underrun_disabled;

	if (enable == ret)
		goto done;

	intel_crtc->cpu_fifo_underrun_disabled = !enable;

	if (IS_GEN5(dev) || IS_GEN6(dev))
		ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
	else if (IS_GEN7(dev))
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		ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
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done:
	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
	return ret;
}

/**
 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
 * @dev: drm device
 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
 * @enable: true if we want to report FIFO underrun errors, false otherwise
 *
 * This function makes us disable or enable PCH fifo underruns for a specific
 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
 * underrun reporting for one transcoder may also disable all the other PCH
 * error interruts for the other transcoders, due to the fact that there's just
 * one interrupt mask/enable bit for all the transcoders.
 *
 * Returns the previous state of underrun reporting.
 */
bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
					   enum transcoder pch_transcoder,
					   bool enable)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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	unsigned long flags;
	bool ret;

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	/*
	 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
	 * has only one pch transcoder A that all pipes can use. To avoid racy
	 * pch transcoder -> pipe lookups from interrupt code simply store the
	 * underrun statistics in crtc A. Since we never expose this anywhere
	 * nor use it outside of the fifo underrun code here using the "wrong"
	 * crtc on LPT won't cause issues.
	 */
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	spin_lock_irqsave(&dev_priv->irq_lock, flags);

	ret = !intel_crtc->pch_fifo_underrun_disabled;

	if (enable == ret)
		goto done;

	intel_crtc->pch_fifo_underrun_disabled = !enable;

	if (HAS_PCH_IBX(dev))
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		ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
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	else
		cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);

done:
	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
	return ret;
}


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void
i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
{
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	u32 reg = PIPESTAT(pipe);
	u32 pipestat = I915_READ(reg) & 0x7fff0000;
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	assert_spin_locked(&dev_priv->irq_lock);

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	if ((pipestat & mask) == mask)
		return;

	/* Enable the interrupt, clear any pending status */
	pipestat |= mask | (mask >> 16);
	I915_WRITE(reg, pipestat);
	POSTING_READ(reg);
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}

void
i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
{
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	u32 reg = PIPESTAT(pipe);
	u32 pipestat = I915_READ(reg) & 0x7fff0000;
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	assert_spin_locked(&dev_priv->irq_lock);

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	if ((pipestat & mask) == 0)
		return;

	pipestat &= ~mask;
	I915_WRITE(reg, pipestat);
	POSTING_READ(reg);
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}

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/**
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 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
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 */
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static void i915_enable_asle_pipestat(struct drm_device *dev)
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{
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	drm_i915_private_t *dev_priv = dev->dev_private;
	unsigned long irqflags;

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	if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
		return;

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	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
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	i915_enable_pipestat(dev_priv, 1, PIPE_LEGACY_BLC_EVENT_ENABLE);
	if (INTEL_INFO(dev)->gen >= 4)
		i915_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE);
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	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
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}

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/**
 * i915_pipe_enabled - check if a pipe is enabled
 * @dev: DRM device
 * @pipe: pipe to check
 *
 * Reading certain registers when the pipe is disabled can hang the chip.
 * Use this routine to make sure the PLL is running and the pipe is active
 * before reading such registers if unsure.
 */
static int
i915_pipe_enabled(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
		/* Locking is horribly broken here, but whatever. */
		struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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		return intel_crtc->active;
	} else {
		return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
	}
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}

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static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
{
	/* Gen2 doesn't have a hardware frame counter */
	return 0;
}

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/* Called from drm generic code, passed a 'crtc', which
 * we use as a pipe index
 */
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static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
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{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long high_frame;
	unsigned long low_frame;
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	u32 high1, high2, low, pixel, vbl_start;
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	if (!i915_pipe_enabled(dev, pipe)) {
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		DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
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				"pipe %c\n", pipe_name(pipe));
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		return 0;
	}

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	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
		struct intel_crtc *intel_crtc =
			to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
		const struct drm_display_mode *mode =
			&intel_crtc->config.adjusted_mode;

		vbl_start = mode->crtc_vblank_start * mode->crtc_htotal;
	} else {
		enum transcoder cpu_transcoder =
			intel_pipe_to_cpu_transcoder(dev_priv, pipe);
		u32 htotal;

		htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
		vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;

		vbl_start *= htotal;
	}

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	high_frame = PIPEFRAME(pipe);
	low_frame = PIPEFRAMEPIXEL(pipe);
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	/*
	 * High & low register fields aren't synchronized, so make sure
	 * we get a low value that's stable across two reads of the high
	 * register.
	 */
	do {
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		high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
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		low   = I915_READ(low_frame);
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		high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
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	} while (high1 != high2);

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	high1 >>= PIPE_FRAME_HIGH_SHIFT;
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	pixel = low & PIPE_PIXEL_MASK;
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	low >>= PIPE_FRAME_LOW_SHIFT;
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	/*
	 * The frame counter increments at beginning of active.
	 * Cook up a vblank counter by also checking the pixel
	 * counter against vblank start.
	 */
	return ((high1 << 8) | low) + (pixel >= vbl_start);
586 587
}

588
static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
589 590
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
591
	int reg = PIPE_FRMCOUNT_GM45(pipe);
592 593

	if (!i915_pipe_enabled(dev, pipe)) {
594
		DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
595
				 "pipe %c\n", pipe_name(pipe));
596 597 598 599 600 601
		return 0;
	}

	return I915_READ(reg);
}

602
static bool intel_pipe_in_vblank(struct drm_device *dev, enum pipe pipe)
603 604 605 606 607 608 609 610 611 612
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t status;

	if (IS_VALLEYVIEW(dev)) {
		status = pipe == PIPE_A ?
			I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT :
			I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;

		return I915_READ(VLV_ISR) & status;
613 614 615 616 617 618 619
	} else if (IS_GEN2(dev)) {
		status = pipe == PIPE_A ?
			I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT :
			I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;

		return I915_READ16(ISR) & status;
	} else if (INTEL_INFO(dev)->gen < 5) {
620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648
		status = pipe == PIPE_A ?
			I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT :
			I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;

		return I915_READ(ISR) & status;
	} else if (INTEL_INFO(dev)->gen < 7) {
		status = pipe == PIPE_A ?
			DE_PIPEA_VBLANK :
			DE_PIPEB_VBLANK;

		return I915_READ(DEISR) & status;
	} else {
		switch (pipe) {
		default:
		case PIPE_A:
			status = DE_PIPEA_VBLANK_IVB;
			break;
		case PIPE_B:
			status = DE_PIPEB_VBLANK_IVB;
			break;
		case PIPE_C:
			status = DE_PIPEC_VBLANK_IVB;
			break;
		}

		return I915_READ(DEISR) & status;
	}
}

649
static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
650 651
			     int *vpos, int *hpos)
{
652 653 654 655
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
656
	int position;
657 658 659 660
	int vbl_start, vbl_end, htotal, vtotal;
	bool in_vbl = true;
	int ret = 0;

661
	if (!intel_crtc->active) {
662
		DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
663
				 "pipe %c\n", pipe_name(pipe));
664 665 666
		return 0;
	}

667 668 669 670
	htotal = mode->crtc_htotal;
	vtotal = mode->crtc_vtotal;
	vbl_start = mode->crtc_vblank_start;
	vbl_end = mode->crtc_vblank_end;
671

672 673
	ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;

674
	if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
675 676 677
		/* No obvious pixelcount register. Only query vertical
		 * scanout position from Display scan line register.
		 */
678 679 680 681
		if (IS_GEN2(dev))
			position = I915_READ(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
		else
			position = I915_READ(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
682 683 684 685 686 687 688 689

		/*
		 * The scanline counter increments at the leading edge
		 * of hsync, ie. it completely misses the active portion
		 * of the line. Fix up the counter at both edges of vblank
		 * to get a more accurate picture whether we're in vblank
		 * or not.
		 */
690
		in_vbl = intel_pipe_in_vblank(dev, pipe);
691 692 693
		if ((in_vbl && position == vbl_start - 1) ||
		    (!in_vbl && position == vbl_end - 1))
			position = (position + 1) % vtotal;
694 695 696 697 698 699 700
	} else {
		/* Have access to pixelcount since start of frame.
		 * We can split this into vertical and horizontal
		 * scanout position.
		 */
		position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;

701 702 703 704
		/* convert to pixel counts */
		vbl_start *= htotal;
		vbl_end *= htotal;
		vtotal *= htotal;
705 706
	}

707 708 709 710 711 712 713 714 715 716 717 718
	in_vbl = position >= vbl_start && position < vbl_end;

	/*
	 * While in vblank, position will be negative
	 * counting up towards 0 at vbl_end. And outside
	 * vblank, position will be positive counting
	 * up since vbl_end.
	 */
	if (position >= vbl_start)
		position -= vbl_end;
	else
		position += vtotal - vbl_end;
719

720
	if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
721 722 723 724 725 726
		*vpos = position;
		*hpos = 0;
	} else {
		*vpos = position / htotal;
		*hpos = position - (*vpos * htotal);
	}
727 728 729 730 731 732 733 734

	/* In vblank? */
	if (in_vbl)
		ret |= DRM_SCANOUTPOS_INVBL;

	return ret;
}

735
static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
736 737 738 739
			      int *max_error,
			      struct timeval *vblank_time,
			      unsigned flags)
{
740
	struct drm_crtc *crtc;
741

742
	if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
743
		DRM_ERROR("Invalid crtc %d\n", pipe);
744 745 746 747
		return -EINVAL;
	}

	/* Get drm_crtc to timestamp: */
748 749 750 751 752 753 754 755 756 757
	crtc = intel_get_crtc_for_pipe(dev, pipe);
	if (crtc == NULL) {
		DRM_ERROR("Invalid crtc %d\n", pipe);
		return -EINVAL;
	}

	if (!crtc->enabled) {
		DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
		return -EBUSY;
	}
758 759

	/* Helper routine in DRM core does all the work: */
760 761 762
	return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
						     vblank_time, flags,
						     crtc);
763 764
}

765 766
static bool intel_hpd_irq_event(struct drm_device *dev,
				struct drm_connector *connector)
767 768 769 770 771 772 773
{
	enum drm_connector_status old_status;

	WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
	old_status = connector->status;

	connector->status = connector->funcs->detect(connector, false);
774 775 776 777
	if (old_status == connector->status)
		return false;

	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
778 779
		      connector->base.id,
		      drm_get_connector_name(connector),
780 781 782 783
		      drm_get_connector_status_name(old_status),
		      drm_get_connector_status_name(connector->status));

	return true;
784 785
}

786 787 788
/*
 * Handle hotplug events outside the interrupt handler proper.
 */
789 790
#define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)

791 792 793 794 795
static void i915_hotplug_work_func(struct work_struct *work)
{
	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
						    hotplug_work);
	struct drm_device *dev = dev_priv->dev;
796
	struct drm_mode_config *mode_config = &dev->mode_config;
797 798 799 800 801
	struct intel_connector *intel_connector;
	struct intel_encoder *intel_encoder;
	struct drm_connector *connector;
	unsigned long irqflags;
	bool hpd_disabled = false;
802
	bool changed = false;
803
	u32 hpd_event_bits;
804

805 806 807 808
	/* HPD irq before everything is fully set up. */
	if (!dev_priv->enable_hotplug_processing)
		return;

809
	mutex_lock(&mode_config->mutex);
810 811
	DRM_DEBUG_KMS("running encoder hotplug functions\n");

812
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
813 814 815

	hpd_event_bits = dev_priv->hpd_event_bits;
	dev_priv->hpd_event_bits = 0;
816 817 818 819 820 821 822 823 824 825 826 827 828 829
	list_for_each_entry(connector, &mode_config->connector_list, head) {
		intel_connector = to_intel_connector(connector);
		intel_encoder = intel_connector->encoder;
		if (intel_encoder->hpd_pin > HPD_NONE &&
		    dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
		    connector->polled == DRM_CONNECTOR_POLL_HPD) {
			DRM_INFO("HPD interrupt storm detected on connector %s: "
				 "switching from hotplug detection to polling\n",
				drm_get_connector_name(connector));
			dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
			connector->polled = DRM_CONNECTOR_POLL_CONNECT
				| DRM_CONNECTOR_POLL_DISCONNECT;
			hpd_disabled = true;
		}
830 831 832 833
		if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
			DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
				      drm_get_connector_name(connector), intel_encoder->hpd_pin);
		}
834 835 836 837
	}
	 /* if there were no outputs to poll, poll was disabled,
	  * therefore make sure it's enabled when disabling HPD on
	  * some connectors */
838
	if (hpd_disabled) {
839
		drm_kms_helper_poll_enable(dev);
840 841 842
		mod_timer(&dev_priv->hotplug_reenable_timer,
			  jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
	}
843 844 845

	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

846 847 848 849 850 851 852 853 854 855
	list_for_each_entry(connector, &mode_config->connector_list, head) {
		intel_connector = to_intel_connector(connector);
		intel_encoder = intel_connector->encoder;
		if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
			if (intel_encoder->hot_plug)
				intel_encoder->hot_plug(intel_encoder);
			if (intel_hpd_irq_event(dev, connector))
				changed = true;
		}
	}
856 857
	mutex_unlock(&mode_config->mutex);

858 859
	if (changed)
		drm_kms_helper_hotplug_event(dev);
860 861
}

862
static void ironlake_rps_change_irq_handler(struct drm_device *dev)
863 864
{
	drm_i915_private_t *dev_priv = dev->dev_private;
865
	u32 busy_up, busy_down, max_avg, min_avg;
866 867
	u8 new_delay;

868
	spin_lock(&mchdev_lock);
869

870 871
	I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));

872
	new_delay = dev_priv->ips.cur_delay;
873

874
	I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
875 876
	busy_up = I915_READ(RCPREVBSYTUPAVG);
	busy_down = I915_READ(RCPREVBSYTDNAVG);
877 878 879 880
	max_avg = I915_READ(RCBMAXAVG);
	min_avg = I915_READ(RCBMINAVG);

	/* Handle RCS change request from hw */
881
	if (busy_up > max_avg) {
882 883 884 885
		if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
			new_delay = dev_priv->ips.cur_delay - 1;
		if (new_delay < dev_priv->ips.max_delay)
			new_delay = dev_priv->ips.max_delay;
886
	} else if (busy_down < min_avg) {
887 888 889 890
		if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
			new_delay = dev_priv->ips.cur_delay + 1;
		if (new_delay > dev_priv->ips.min_delay)
			new_delay = dev_priv->ips.min_delay;
891 892
	}

893
	if (ironlake_set_drps(dev, new_delay))
894
		dev_priv->ips.cur_delay = new_delay;
895

896
	spin_unlock(&mchdev_lock);
897

898 899 900
	return;
}

901 902 903
static void notify_ring(struct drm_device *dev,
			struct intel_ring_buffer *ring)
{
904 905 906
	if (ring->obj == NULL)
		return;

907
	trace_i915_gem_request_complete(ring);
908

909
	wake_up_all(&ring->irq_queue);
910
	i915_queue_hangcheck(dev);
911 912
}

913
static void gen6_pm_rps_work(struct work_struct *work)
914
{
915
	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
916
						    rps.work);
P
Paulo Zanoni 已提交
917
	u32 pm_iir;
918
	int new_delay, adj;
919

920
	spin_lock_irq(&dev_priv->irq_lock);
921 922
	pm_iir = dev_priv->rps.pm_iir;
	dev_priv->rps.pm_iir = 0;
923
	/* Make sure not to corrupt PMIMR state used by ringbuffer code */
P
Paulo Zanoni 已提交
924
	snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
925
	spin_unlock_irq(&dev_priv->irq_lock);
926

927 928 929
	/* Make sure we didn't queue anything we're not going to process. */
	WARN_ON(pm_iir & ~GEN6_PM_RPS_EVENTS);

930
	if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
931 932
		return;

933
	mutex_lock(&dev_priv->rps.hw_lock);
934

935
	adj = dev_priv->rps.last_adj;
936
	if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
937 938 939 940 941
		if (adj > 0)
			adj *= 2;
		else
			adj = 1;
		new_delay = dev_priv->rps.cur_delay + adj;
942 943 944 945 946

		/*
		 * For better performance, jump directly
		 * to RPe if we're below it.
		 */
947 948 949 950
		if (new_delay < dev_priv->rps.rpe_delay)
			new_delay = dev_priv->rps.rpe_delay;
	} else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
		if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
951
			new_delay = dev_priv->rps.rpe_delay;
952 953 954 955 956 957 958 959 960 961 962 963
		else
			new_delay = dev_priv->rps.min_delay;
		adj = 0;
	} else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
		if (adj < 0)
			adj *= 2;
		else
			adj = -1;
		new_delay = dev_priv->rps.cur_delay + adj;
	} else { /* unknown event */
		new_delay = dev_priv->rps.cur_delay;
	}
964

965 966 967
	/* sysfs frequency interfaces may have snuck in while servicing the
	 * interrupt
	 */
968 969 970 971 972 973 974 975 976 977
	if (new_delay < (int)dev_priv->rps.min_delay)
		new_delay = dev_priv->rps.min_delay;
	if (new_delay > (int)dev_priv->rps.max_delay)
		new_delay = dev_priv->rps.max_delay;
	dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay;

	if (IS_VALLEYVIEW(dev_priv->dev))
		valleyview_set_rps(dev_priv->dev, new_delay);
	else
		gen6_set_rps(dev_priv->dev, new_delay);
978

979
	mutex_unlock(&dev_priv->rps.hw_lock);
980 981
}

982 983 984 985 986 987 988 989 990 991 992 993 994

/**
 * ivybridge_parity_work - Workqueue called when a parity error interrupt
 * occurred.
 * @work: workqueue struct
 *
 * Doesn't actually do anything except notify userspace. As a consequence of
 * this event, userspace should try to remap the bad rows since statistically
 * it is likely the same row is more likely to go bad again.
 */
static void ivybridge_parity_work(struct work_struct *work)
{
	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
995
						    l3_parity.error_work);
996
	u32 error_status, row, bank, subbank;
997
	char *parity_event[6];
998 999
	uint32_t misccpctl;
	unsigned long flags;
1000
	uint8_t slice = 0;
1001 1002 1003 1004 1005 1006 1007

	/* We must turn off DOP level clock gating to access the L3 registers.
	 * In order to prevent a get/put style interface, acquire struct mutex
	 * any time we access those registers.
	 */
	mutex_lock(&dev_priv->dev->struct_mutex);

1008 1009 1010 1011
	/* If we've screwed up tracking, just let the interrupt fire again */
	if (WARN_ON(!dev_priv->l3_parity.which_slice))
		goto out;

1012 1013 1014 1015
	misccpctl = I915_READ(GEN7_MISCCPCTL);
	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
	POSTING_READ(GEN7_MISCCPCTL);

1016 1017
	while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
		u32 reg;
1018

1019 1020 1021
		slice--;
		if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
			break;
1022

1023
		dev_priv->l3_parity.which_slice &= ~(1<<slice);
1024

1025
		reg = GEN7_L3CDERRST1 + (slice * 0x200);
1026

1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043
		error_status = I915_READ(reg);
		row = GEN7_PARITY_ERROR_ROW(error_status);
		bank = GEN7_PARITY_ERROR_BANK(error_status);
		subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);

		I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
		POSTING_READ(reg);

		parity_event[0] = I915_L3_PARITY_UEVENT "=1";
		parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
		parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
		parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
		parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
		parity_event[5] = NULL;

		kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
				   KOBJ_CHANGE, parity_event);
1044

1045 1046
		DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
			  slice, row, bank, subbank);
1047

1048 1049 1050 1051 1052
		kfree(parity_event[4]);
		kfree(parity_event[3]);
		kfree(parity_event[2]);
		kfree(parity_event[1]);
	}
1053

1054
	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1055

1056 1057 1058 1059 1060 1061 1062
out:
	WARN_ON(dev_priv->l3_parity.which_slice);
	spin_lock_irqsave(&dev_priv->irq_lock, flags);
	ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);

	mutex_unlock(&dev_priv->dev->struct_mutex);
1063 1064
}

1065
static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1066 1067 1068
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;

1069
	if (!HAS_L3_DPF(dev))
1070 1071
		return;

1072
	spin_lock(&dev_priv->irq_lock);
1073
	ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1074
	spin_unlock(&dev_priv->irq_lock);
1075

1076 1077 1078 1079 1080 1081 1082
	iir &= GT_PARITY_ERROR(dev);
	if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
		dev_priv->l3_parity.which_slice |= 1 << 1;

	if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
		dev_priv->l3_parity.which_slice |= 1 << 0;

1083
	queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1084 1085
}

1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096
static void ilk_gt_irq_handler(struct drm_device *dev,
			       struct drm_i915_private *dev_priv,
			       u32 gt_iir)
{
	if (gt_iir &
	    (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
		notify_ring(dev, &dev_priv->ring[RCS]);
	if (gt_iir & ILK_BSD_USER_INTERRUPT)
		notify_ring(dev, &dev_priv->ring[VCS]);
}

1097 1098 1099 1100 1101
static void snb_gt_irq_handler(struct drm_device *dev,
			       struct drm_i915_private *dev_priv,
			       u32 gt_iir)
{

1102 1103
	if (gt_iir &
	    (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1104
		notify_ring(dev, &dev_priv->ring[RCS]);
1105
	if (gt_iir & GT_BSD_USER_INTERRUPT)
1106
		notify_ring(dev, &dev_priv->ring[VCS]);
1107
	if (gt_iir & GT_BLT_USER_INTERRUPT)
1108 1109
		notify_ring(dev, &dev_priv->ring[BCS]);

1110 1111 1112
	if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
		      GT_BSD_CS_ERROR_INTERRUPT |
		      GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
1113 1114 1115
		DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
		i915_handle_error(dev, false);
	}
1116

1117 1118
	if (gt_iir & GT_PARITY_ERROR(dev))
		ivybridge_parity_error_irq_handler(dev, gt_iir);
1119 1120
}

1121 1122 1123
#define HPD_STORM_DETECT_PERIOD 1000
#define HPD_STORM_THRESHOLD 5

1124
static inline void intel_hpd_irq_handler(struct drm_device *dev,
1125 1126
					 u32 hotplug_trigger,
					 const u32 *hpd)
1127 1128 1129
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	int i;
1130
	bool storm_detected = false;
1131

1132 1133 1134
	if (!hotplug_trigger)
		return;

1135
	spin_lock(&dev_priv->irq_lock);
1136
	for (i = 1; i < HPD_NUM_PINS; i++) {
1137

1138 1139 1140 1141
		WARN(((hpd[i] & hotplug_trigger) &&
		      dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED),
		     "Received HPD interrupt although disabled\n");

1142 1143 1144 1145
		if (!(hpd[i] & hotplug_trigger) ||
		    dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
			continue;

1146
		dev_priv->hpd_event_bits |= (1 << i);
1147 1148 1149 1150 1151
		if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
				   dev_priv->hpd_stats[i].hpd_last_jiffies
				   + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
			dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
			dev_priv->hpd_stats[i].hpd_cnt = 0;
1152
			DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1153 1154
		} else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
			dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1155
			dev_priv->hpd_event_bits &= ~(1 << i);
1156
			DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1157
			storm_detected = true;
1158 1159
		} else {
			dev_priv->hpd_stats[i].hpd_cnt++;
1160 1161
			DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
				      dev_priv->hpd_stats[i].hpd_cnt);
1162 1163 1164
		}
	}

1165 1166
	if (storm_detected)
		dev_priv->display.hpd_irq_setup(dev);
1167
	spin_unlock(&dev_priv->irq_lock);
1168

1169 1170 1171 1172 1173 1174 1175
	/*
	 * Our hotplug handler can grab modeset locks (by calling down into the
	 * fb helpers). Hence it must not be run on our own dev-priv->wq work
	 * queue for otherwise the flush_work in the pageflip code will
	 * deadlock.
	 */
	schedule_work(&dev_priv->hotplug_work);
1176 1177
}

1178 1179
static void gmbus_irq_handler(struct drm_device *dev)
{
1180 1181 1182
	struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;

	wake_up_all(&dev_priv->gmbus_wait_queue);
1183 1184
}

1185 1186
static void dp_aux_irq_handler(struct drm_device *dev)
{
1187 1188 1189
	struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;

	wake_up_all(&dev_priv->gmbus_wait_queue);
1190 1191
}

1192 1193 1194 1195 1196 1197
#if defined(CONFIG_DEBUG_FS)
static void ivb_pipe_crc_update(struct drm_device *dev, enum pipe pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
	struct intel_pipe_crc_entry *entry;
1198
	int head, tail;
1199

1200 1201 1202 1203 1204
	if (!pipe_crc->entries) {
		DRM_ERROR("spurious interrupt\n");
		return;
	}

1205 1206 1207 1208 1209 1210 1211 1212 1213
	head = atomic_read(&pipe_crc->head);
	tail = atomic_read(&pipe_crc->tail);

	if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
		DRM_ERROR("CRC buffer overflowing\n");
		return;
	}

	entry = &pipe_crc->entries[head];
1214

1215
	entry->frame = I915_READ(PIPEFRAME(pipe));
1216 1217 1218 1219 1220
	entry->crc[0] = I915_READ(PIPE_CRC_RES_1_IVB(pipe));
	entry->crc[1] = I915_READ(PIPE_CRC_RES_2_IVB(pipe));
	entry->crc[2] = I915_READ(PIPE_CRC_RES_3_IVB(pipe));
	entry->crc[3] = I915_READ(PIPE_CRC_RES_4_IVB(pipe));
	entry->crc[4] = I915_READ(PIPE_CRC_RES_5_IVB(pipe));
1221 1222 1223

	head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
	atomic_set(&pipe_crc->head, head);
1224 1225 1226 1227 1228
}
#else
static void ivb_pipe_crc_update(struct drm_device *dev, int pipe) {}
#endif

1229 1230 1231 1232
/* The RPS events need forcewake, so we add them to a work queue and mask their
 * IMR bits until the work is done. Other interrupts can be processed without
 * the work queue. */
static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1233
{
1234
	if (pm_iir & GEN6_PM_RPS_EVENTS) {
1235
		spin_lock(&dev_priv->irq_lock);
1236
		dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
1237
		snb_disable_pm_irq(dev_priv, pm_iir & GEN6_PM_RPS_EVENTS);
1238
		spin_unlock(&dev_priv->irq_lock);
1239 1240

		queue_work(dev_priv->wq, &dev_priv->rps.work);
1241 1242
	}

1243 1244 1245
	if (HAS_VEBOX(dev_priv->dev)) {
		if (pm_iir & PM_VEBOX_USER_INTERRUPT)
			notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
B
Ben Widawsky 已提交
1246

1247 1248 1249 1250
		if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
			DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
			i915_handle_error(dev_priv->dev, false);
		}
B
Ben Widawsky 已提交
1251
	}
1252 1253
}

1254
static irqreturn_t valleyview_irq_handler(int irq, void *arg)
J
Jesse Barnes 已提交
1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275
{
	struct drm_device *dev = (struct drm_device *) arg;
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u32 iir, gt_iir, pm_iir;
	irqreturn_t ret = IRQ_NONE;
	unsigned long irqflags;
	int pipe;
	u32 pipe_stats[I915_MAX_PIPES];

	atomic_inc(&dev_priv->irq_received);

	while (true) {
		iir = I915_READ(VLV_IIR);
		gt_iir = I915_READ(GTIIR);
		pm_iir = I915_READ(GEN6_PMIIR);

		if (gt_iir == 0 && pm_iir == 0 && iir == 0)
			goto out;

		ret = IRQ_HANDLED;

1276
		snb_gt_irq_handler(dev, dev_priv, gt_iir);
J
Jesse Barnes 已提交
1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294

		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
		for_each_pipe(pipe) {
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);

			/*
			 * Clear the PIPE*STAT regs before the IIR
			 */
			if (pipe_stats[pipe] & 0x8000ffff) {
				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
					DRM_DEBUG_DRIVER("pipe %c underrun\n",
							 pipe_name(pipe));
				I915_WRITE(reg, pipe_stats[pipe]);
			}
		}
		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

1295 1296 1297 1298 1299 1300 1301 1302 1303 1304
		for_each_pipe(pipe) {
			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
				drm_handle_vblank(dev, pipe);

			if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
				intel_prepare_page_flip(dev, pipe);
				intel_finish_page_flip(dev, pipe);
			}
		}

J
Jesse Barnes 已提交
1305 1306 1307
		/* Consume port.  Then clear IIR or we'll miss events */
		if (iir & I915_DISPLAY_PORT_INTERRUPT) {
			u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1308
			u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
J
Jesse Barnes 已提交
1309 1310 1311

			DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
					 hotplug_status);
1312 1313 1314

			intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);

J
Jesse Barnes 已提交
1315 1316 1317 1318
			I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
			I915_READ(PORT_HOTPLUG_STAT);
		}

1319 1320
		if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
			gmbus_irq_handler(dev);
J
Jesse Barnes 已提交
1321

1322
		if (pm_iir)
1323
			gen6_rps_irq_handler(dev_priv, pm_iir);
J
Jesse Barnes 已提交
1324 1325 1326 1327 1328 1329 1330 1331 1332 1333

		I915_WRITE(GTIIR, gt_iir);
		I915_WRITE(GEN6_PMIIR, pm_iir);
		I915_WRITE(VLV_IIR, iir);
	}

out:
	return ret;
}

1334
static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1335 1336
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1337
	int pipe;
1338
	u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1339

1340 1341
	intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);

1342 1343 1344
	if (pch_iir & SDE_AUDIO_POWER_MASK) {
		int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
			       SDE_AUDIO_POWER_SHIFT);
1345
		DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1346 1347
				 port_name(port));
	}
1348

1349 1350 1351
	if (pch_iir & SDE_AUX_MASK)
		dp_aux_irq_handler(dev);

1352
	if (pch_iir & SDE_GMBUS)
1353
		gmbus_irq_handler(dev);
1354 1355 1356 1357 1358 1359 1360 1361 1362 1363

	if (pch_iir & SDE_AUDIO_HDCP_MASK)
		DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");

	if (pch_iir & SDE_AUDIO_TRANS_MASK)
		DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");

	if (pch_iir & SDE_POISON)
		DRM_ERROR("PCH poison interrupt\n");

1364 1365 1366 1367 1368
	if (pch_iir & SDE_FDI_MASK)
		for_each_pipe(pipe)
			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
					 pipe_name(pipe),
					 I915_READ(FDI_RX_IIR(pipe)));
1369 1370 1371 1372 1373 1374 1375 1376

	if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
		DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");

	if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
		DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");

	if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391
		if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
							  false))
			DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");

	if (pch_iir & SDE_TRANSB_FIFO_UNDER)
		if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
							  false))
			DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
}

static void ivb_err_int_handler(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 err_int = I915_READ(GEN7_ERR_INT);

1392 1393 1394
	if (err_int & ERR_INT_POISON)
		DRM_ERROR("Poison interrupt\n");

1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406
	if (err_int & ERR_INT_FIFO_UNDERRUN_A)
		if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
			DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");

	if (err_int & ERR_INT_FIFO_UNDERRUN_B)
		if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
			DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");

	if (err_int & ERR_INT_FIFO_UNDERRUN_C)
		if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false))
			DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");

1407 1408 1409 1410 1411 1412 1413 1414 1415
	if (err_int & ERR_INT_PIPE_CRC_DONE_A)
		ivb_pipe_crc_update(dev, PIPE_A);

	if (err_int & ERR_INT_PIPE_CRC_DONE_B)
		ivb_pipe_crc_update(dev, PIPE_B);

	if (err_int & ERR_INT_PIPE_CRC_DONE_C)
		ivb_pipe_crc_update(dev, PIPE_C);

1416 1417 1418 1419 1420 1421 1422 1423
	I915_WRITE(GEN7_ERR_INT, err_int);
}

static void cpt_serr_int_handler(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 serr_int = I915_READ(SERR_INT);

1424 1425 1426
	if (serr_int & SERR_INT_POISON)
		DRM_ERROR("PCH poison interrupt\n");

1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442
	if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
		if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
							  false))
			DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");

	if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
		if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
							  false))
			DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");

	if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
		if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
							  false))
			DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");

	I915_WRITE(SERR_INT, serr_int);
1443 1444
}

1445 1446 1447 1448
static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;
1449
	u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1450

1451 1452
	intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);

1453 1454 1455 1456 1457 1458
	if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
		int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
			       SDE_AUDIO_POWER_SHIFT_CPT);
		DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
				 port_name(port));
	}
1459 1460

	if (pch_iir & SDE_AUX_MASK_CPT)
1461
		dp_aux_irq_handler(dev);
1462 1463

	if (pch_iir & SDE_GMBUS_CPT)
1464
		gmbus_irq_handler(dev);
1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476

	if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
		DRM_DEBUG_DRIVER("Audio CP request interrupt\n");

	if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
		DRM_DEBUG_DRIVER("Audio CP change interrupt\n");

	if (pch_iir & SDE_FDI_MASK_CPT)
		for_each_pipe(pipe)
			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
					 pipe_name(pipe),
					 I915_READ(FDI_RX_IIR(pipe)));
1477 1478 1479

	if (pch_iir & SDE_ERROR_CPT)
		cpt_serr_int_handler(dev);
1480 1481
}

1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535
static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (de_iir & DE_AUX_CHANNEL_A)
		dp_aux_irq_handler(dev);

	if (de_iir & DE_GSE)
		intel_opregion_asle_intr(dev);

	if (de_iir & DE_PIPEA_VBLANK)
		drm_handle_vblank(dev, 0);

	if (de_iir & DE_PIPEB_VBLANK)
		drm_handle_vblank(dev, 1);

	if (de_iir & DE_POISON)
		DRM_ERROR("Poison interrupt\n");

	if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
		if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
			DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");

	if (de_iir & DE_PIPEB_FIFO_UNDERRUN)
		if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
			DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");

	if (de_iir & DE_PLANEA_FLIP_DONE) {
		intel_prepare_page_flip(dev, 0);
		intel_finish_page_flip_plane(dev, 0);
	}

	if (de_iir & DE_PLANEB_FLIP_DONE) {
		intel_prepare_page_flip(dev, 1);
		intel_finish_page_flip_plane(dev, 1);
	}

	/* check event from PCH */
	if (de_iir & DE_PCH_EVENT) {
		u32 pch_iir = I915_READ(SDEIIR);

		if (HAS_PCH_CPT(dev))
			cpt_irq_handler(dev, pch_iir);
		else
			ibx_irq_handler(dev, pch_iir);

		/* should clear PCH hotplug event before clear CPU irq */
		I915_WRITE(SDEIIR, pch_iir);
	}

	if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
		ironlake_rps_change_irq_handler(dev);
}

1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569
static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;

	if (de_iir & DE_ERR_INT_IVB)
		ivb_err_int_handler(dev);

	if (de_iir & DE_AUX_CHANNEL_A_IVB)
		dp_aux_irq_handler(dev);

	if (de_iir & DE_GSE_IVB)
		intel_opregion_asle_intr(dev);

	for (i = 0; i < 3; i++) {
		if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
			drm_handle_vblank(dev, i);
		if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
			intel_prepare_page_flip(dev, i);
			intel_finish_page_flip_plane(dev, i);
		}
	}

	/* check event from PCH */
	if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
		u32 pch_iir = I915_READ(SDEIIR);

		cpt_irq_handler(dev, pch_iir);

		/* clear PCH hotplug event before clear CPU irq */
		I915_WRITE(SDEIIR, pch_iir);
	}
}

1570
static irqreturn_t ironlake_irq_handler(int irq, void *arg)
1571 1572 1573
{
	struct drm_device *dev = (struct drm_device *) arg;
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1574
	u32 de_iir, gt_iir, de_ier, sde_ier = 0;
1575
	irqreturn_t ret = IRQ_NONE;
1576 1577 1578

	atomic_inc(&dev_priv->irq_received);

1579 1580
	/* We get interrupts on unclaimed registers, so check for this before we
	 * do any I915_{READ,WRITE}. */
1581
	intel_uncore_check_errors(dev);
1582

1583 1584 1585
	/* disable master interrupt before clearing iir  */
	de_ier = I915_READ(DEIER);
	I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
1586
	POSTING_READ(DEIER);
1587

1588 1589 1590 1591 1592
	/* Disable south interrupts. We'll only write to SDEIIR once, so further
	 * interrupts will will be stored on its back queue, and then we'll be
	 * able to process them after we restore SDEIER (as soon as we restore
	 * it, we'll get an interrupt if SDEIIR still has something to process
	 * due to its back queue). */
1593 1594 1595 1596 1597
	if (!HAS_PCH_NOP(dev)) {
		sde_ier = I915_READ(SDEIER);
		I915_WRITE(SDEIER, 0);
		POSTING_READ(SDEIER);
	}
1598

1599
	gt_iir = I915_READ(GTIIR);
1600
	if (gt_iir) {
1601
		if (INTEL_INFO(dev)->gen >= 6)
1602
			snb_gt_irq_handler(dev, dev_priv, gt_iir);
1603 1604
		else
			ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1605 1606
		I915_WRITE(GTIIR, gt_iir);
		ret = IRQ_HANDLED;
1607 1608
	}

1609 1610
	de_iir = I915_READ(DEIIR);
	if (de_iir) {
1611 1612 1613 1614
		if (INTEL_INFO(dev)->gen >= 7)
			ivb_display_irq_handler(dev, de_iir);
		else
			ilk_display_irq_handler(dev, de_iir);
1615 1616
		I915_WRITE(DEIIR, de_iir);
		ret = IRQ_HANDLED;
1617 1618
	}

1619 1620 1621
	if (INTEL_INFO(dev)->gen >= 6) {
		u32 pm_iir = I915_READ(GEN6_PMIIR);
		if (pm_iir) {
1622
			gen6_rps_irq_handler(dev_priv, pm_iir);
1623 1624 1625
			I915_WRITE(GEN6_PMIIR, pm_iir);
			ret = IRQ_HANDLED;
		}
1626
	}
1627 1628 1629

	I915_WRITE(DEIER, de_ier);
	POSTING_READ(DEIER);
1630 1631 1632 1633
	if (!HAS_PCH_NOP(dev)) {
		I915_WRITE(SDEIER, sde_ier);
		POSTING_READ(SDEIER);
	}
1634 1635 1636 1637

	return ret;
}

1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665
static void i915_error_wake_up(struct drm_i915_private *dev_priv,
			       bool reset_completed)
{
	struct intel_ring_buffer *ring;
	int i;

	/*
	 * Notify all waiters for GPU completion events that reset state has
	 * been changed, and that they need to restart their wait after
	 * checking for potential errors (and bail out to drop locks if there is
	 * a gpu reset pending so that i915_error_work_func can acquire them).
	 */

	/* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
	for_each_ring(ring, dev_priv, i)
		wake_up_all(&ring->irq_queue);

	/* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
	wake_up_all(&dev_priv->pending_flip_queue);

	/*
	 * Signal tasks blocked in i915_gem_wait_for_error that the pending
	 * reset state is cleared.
	 */
	if (reset_completed)
		wake_up_all(&dev_priv->gpu_error.reset_queue);
}

1666 1667 1668 1669 1670 1671 1672 1673 1674
/**
 * i915_error_work_func - do process context error handling work
 * @work: work struct
 *
 * Fire an error uevent so userspace can see that a hang or error
 * was detected.
 */
static void i915_error_work_func(struct work_struct *work)
{
1675 1676 1677 1678
	struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
						    work);
	drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
						    gpu_error);
1679
	struct drm_device *dev = dev_priv->dev;
1680 1681 1682
	char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
	char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
	char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
1683
	int ret;
1684

1685 1686
	kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);

1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697
	/*
	 * Note that there's only one work item which does gpu resets, so we
	 * need not worry about concurrent gpu resets potentially incrementing
	 * error->reset_counter twice. We only need to take care of another
	 * racing irq/hangcheck declaring the gpu dead for a second time. A
	 * quick check for that is good enough: schedule_work ensures the
	 * correct ordering between hang detection and this work item, and since
	 * the reset in-progress bit is only ever set by code outside of this
	 * work we don't need to worry about any other races.
	 */
	if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
1698
		DRM_DEBUG_DRIVER("resetting chip\n");
1699 1700
		kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
				   reset_event);
1701

1702 1703 1704 1705 1706 1707
		/*
		 * All state reset _must_ be completed before we update the
		 * reset counter, for otherwise waiters might miss the reset
		 * pending state and not properly drop locks, resulting in
		 * deadlocks with the reset work.
		 */
1708 1709
		ret = i915_reset(dev);

1710 1711
		intel_display_handle_reset(dev);

1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727
		if (ret == 0) {
			/*
			 * After all the gem state is reset, increment the reset
			 * counter and wake up everyone waiting for the reset to
			 * complete.
			 *
			 * Since unlock operations are a one-sided barrier only,
			 * we need to insert a barrier here to order any seqno
			 * updates before
			 * the counter increment.
			 */
			smp_mb__before_atomic_inc();
			atomic_inc(&dev_priv->gpu_error.reset_counter);

			kobject_uevent_env(&dev->primary->kdev.kobj,
					   KOBJ_CHANGE, reset_done_event);
1728 1729
		} else {
			atomic_set(&error->reset_counter, I915_WEDGED);
1730
		}
1731

1732 1733 1734 1735 1736
		/*
		 * Note: The wake_up also serves as a memory barrier so that
		 * waiters see the update value of the reset counter atomic_t.
		 */
		i915_error_wake_up(dev_priv, true);
1737
	}
1738 1739
}

1740
static void i915_report_and_clear_eir(struct drm_device *dev)
1741 1742
{
	struct drm_i915_private *dev_priv = dev->dev_private;
1743
	uint32_t instdone[I915_NUM_INSTDONE_REG];
1744
	u32 eir = I915_READ(EIR);
1745
	int pipe, i;
1746

1747 1748
	if (!eir)
		return;
1749

1750
	pr_err("render error detected, EIR: 0x%08x\n", eir);
1751

1752 1753
	i915_get_extra_instdone(dev, instdone);

1754 1755 1756 1757
	if (IS_G4X(dev)) {
		if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
			u32 ipeir = I915_READ(IPEIR_I965);

1758 1759
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1760 1761
			for (i = 0; i < ARRAY_SIZE(instdone); i++)
				pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1762 1763
			pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1764
			I915_WRITE(IPEIR_I965, ipeir);
1765
			POSTING_READ(IPEIR_I965);
1766 1767 1768
		}
		if (eir & GM45_ERROR_PAGE_TABLE) {
			u32 pgtbl_err = I915_READ(PGTBL_ER);
1769 1770
			pr_err("page table error\n");
			pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1771
			I915_WRITE(PGTBL_ER, pgtbl_err);
1772
			POSTING_READ(PGTBL_ER);
1773 1774 1775
		}
	}

1776
	if (!IS_GEN2(dev)) {
1777 1778
		if (eir & I915_ERROR_PAGE_TABLE) {
			u32 pgtbl_err = I915_READ(PGTBL_ER);
1779 1780
			pr_err("page table error\n");
			pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1781
			I915_WRITE(PGTBL_ER, pgtbl_err);
1782
			POSTING_READ(PGTBL_ER);
1783 1784 1785 1786
		}
	}

	if (eir & I915_ERROR_MEMORY_REFRESH) {
1787
		pr_err("memory refresh error:\n");
1788
		for_each_pipe(pipe)
1789
			pr_err("pipe %c stat: 0x%08x\n",
1790
			       pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1791 1792 1793
		/* pipestat has already been acked */
	}
	if (eir & I915_ERROR_INSTRUCTION) {
1794 1795
		pr_err("instruction error\n");
		pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
1796 1797
		for (i = 0; i < ARRAY_SIZE(instdone); i++)
			pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1798
		if (INTEL_INFO(dev)->gen < 4) {
1799 1800
			u32 ipeir = I915_READ(IPEIR);

1801 1802 1803
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
1804
			I915_WRITE(IPEIR, ipeir);
1805
			POSTING_READ(IPEIR);
1806 1807 1808
		} else {
			u32 ipeir = I915_READ(IPEIR_I965);

1809 1810 1811 1812
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
			pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1813
			I915_WRITE(IPEIR_I965, ipeir);
1814
			POSTING_READ(IPEIR_I965);
1815 1816 1817 1818
		}
	}

	I915_WRITE(EIR, eir);
1819
	POSTING_READ(EIR);
1820 1821 1822 1823 1824 1825 1826 1827 1828 1829
	eir = I915_READ(EIR);
	if (eir) {
		/*
		 * some errors might have become stuck,
		 * mask them.
		 */
		DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
		I915_WRITE(EMR, I915_READ(EMR) | eir);
		I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
	}
1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841
}

/**
 * i915_handle_error - handle an error interrupt
 * @dev: drm device
 *
 * Do some basic checking of regsiter state at error interrupt time and
 * dump it to the syslog.  Also call i915_capture_error_state() to make
 * sure we get a record and make it available in debugfs.  Fire a uevent
 * so userspace knows something bad happened (should trigger collection
 * of a ring dump etc.).
 */
1842
void i915_handle_error(struct drm_device *dev, bool wedged)
1843 1844 1845 1846 1847
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	i915_capture_error_state(dev);
	i915_report_and_clear_eir(dev);
1848

1849
	if (wedged) {
1850 1851
		atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
				&dev_priv->gpu_error.reset_counter);
1852

1853
		/*
1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864
		 * Wakeup waiting processes so that the reset work function
		 * i915_error_work_func doesn't deadlock trying to grab various
		 * locks. By bumping the reset counter first, the woken
		 * processes will see a reset in progress and back off,
		 * releasing their locks and then wait for the reset completion.
		 * We must do this for _all_ gpu waiters that might hold locks
		 * that the reset work needs to acquire.
		 *
		 * Note: The wake_up serves as the required memory barrier to
		 * ensure that the waiters see the updated value of the reset
		 * counter atomic_t.
1865
		 */
1866
		i915_error_wake_up(dev_priv, false);
1867 1868
	}

1869 1870 1871 1872 1873 1874 1875
	/*
	 * Our reset work can grab modeset locks (since it needs to reset the
	 * state of outstanding pagelips). Hence it must not be run on our own
	 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
	 * code will deadlock.
	 */
	schedule_work(&dev_priv->gpu_error.work);
1876 1877
}

1878
static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1879 1880 1881 1882
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1883
	struct drm_i915_gem_object *obj;
1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894
	struct intel_unpin_work *work;
	unsigned long flags;
	bool stall_detected;

	/* Ignore early vblank irqs */
	if (intel_crtc == NULL)
		return;

	spin_lock_irqsave(&dev->event_lock, flags);
	work = intel_crtc->unpin_work;

1895 1896 1897
	if (work == NULL ||
	    atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
	    !work->enable_stall_check) {
1898 1899 1900 1901 1902 1903
		/* Either the pending flip IRQ arrived, or we're too early. Don't check */
		spin_unlock_irqrestore(&dev->event_lock, flags);
		return;
	}

	/* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1904
	obj = work->pending_flip_obj;
1905
	if (INTEL_INFO(dev)->gen >= 4) {
1906
		int dspsurf = DSPSURF(intel_crtc->plane);
1907
		stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1908
					i915_gem_obj_ggtt_offset(obj);
1909
	} else {
1910
		int dspaddr = DSPADDR(intel_crtc->plane);
1911
		stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
1912
							crtc->y * crtc->fb->pitches[0] +
1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923
							crtc->x * crtc->fb->bits_per_pixel/8);
	}

	spin_unlock_irqrestore(&dev->event_lock, flags);

	if (stall_detected) {
		DRM_DEBUG_DRIVER("Pageflip stall detected\n");
		intel_prepare_page_flip(dev, intel_crtc->plane);
	}
}

1924 1925 1926
/* Called from drm generic code, passed 'crtc' which
 * we use as a pipe index
 */
1927
static int i915_enable_vblank(struct drm_device *dev, int pipe)
1928 1929
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1930
	unsigned long irqflags;
1931

1932
	if (!i915_pipe_enabled(dev, pipe))
1933
		return -EINVAL;
1934

1935
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1936
	if (INTEL_INFO(dev)->gen >= 4)
1937 1938
		i915_enable_pipestat(dev_priv, pipe,
				     PIPE_START_VBLANK_INTERRUPT_ENABLE);
1939
	else
1940 1941
		i915_enable_pipestat(dev_priv, pipe,
				     PIPE_VBLANK_INTERRUPT_ENABLE);
1942 1943 1944

	/* maintain vblank delivery even in deep C-states */
	if (dev_priv->info->gen == 3)
1945
		I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1946
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1947

1948 1949 1950
	return 0;
}

1951
static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1952 1953 1954
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;
1955 1956
	uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
						     DE_PIPE_VBLANK_ILK(pipe);
1957 1958 1959 1960 1961

	if (!i915_pipe_enabled(dev, pipe))
		return -EINVAL;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1962
	ironlake_enable_display_irq(dev_priv, bit);
1963 1964 1965 1966 1967
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

	return 0;
}

J
Jesse Barnes 已提交
1968 1969 1970 1971
static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;
1972
	u32 imr;
J
Jesse Barnes 已提交
1973 1974 1975 1976 1977 1978

	if (!i915_pipe_enabled(dev, pipe))
		return -EINVAL;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
	imr = I915_READ(VLV_IMR);
1979
	if (pipe == 0)
J
Jesse Barnes 已提交
1980
		imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1981
	else
J
Jesse Barnes 已提交
1982 1983
		imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
	I915_WRITE(VLV_IMR, imr);
1984 1985
	i915_enable_pipestat(dev_priv, pipe,
			     PIPE_START_VBLANK_INTERRUPT_ENABLE);
J
Jesse Barnes 已提交
1986 1987 1988 1989 1990
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

	return 0;
}

1991 1992 1993
/* Called from drm generic code, passed 'crtc' which
 * we use as a pipe index
 */
1994
static void i915_disable_vblank(struct drm_device *dev, int pipe)
1995 1996
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1997
	unsigned long irqflags;
1998

1999
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2000
	if (dev_priv->info->gen == 3)
2001
		I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
2002

2003 2004 2005 2006 2007 2008
	i915_disable_pipestat(dev_priv, pipe,
			      PIPE_VBLANK_INTERRUPT_ENABLE |
			      PIPE_START_VBLANK_INTERRUPT_ENABLE);
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

2009
static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2010 2011 2012
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;
2013 2014
	uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
						     DE_PIPE_VBLANK_ILK(pipe);
2015 2016

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2017
	ironlake_disable_display_irq(dev_priv, bit);
2018 2019 2020
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

J
Jesse Barnes 已提交
2021 2022 2023 2024
static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;
2025
	u32 imr;
J
Jesse Barnes 已提交
2026 2027

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2028 2029
	i915_disable_pipestat(dev_priv, pipe,
			      PIPE_START_VBLANK_INTERRUPT_ENABLE);
J
Jesse Barnes 已提交
2030
	imr = I915_READ(VLV_IMR);
2031
	if (pipe == 0)
J
Jesse Barnes 已提交
2032
		imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
2033
	else
J
Jesse Barnes 已提交
2034 2035 2036 2037 2038
		imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
	I915_WRITE(VLV_IMR, imr);
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

2039 2040
static u32
ring_last_seqno(struct intel_ring_buffer *ring)
2041
{
2042 2043 2044 2045
	return list_entry(ring->request_list.prev,
			  struct drm_i915_gem_request, list)->seqno;
}

2046 2047 2048 2049 2050
static bool
ring_idle(struct intel_ring_buffer *ring, u32 seqno)
{
	return (list_empty(&ring->request_list) ||
		i915_seqno_passed(seqno, ring_last_seqno(ring)));
B
Ben Gamari 已提交
2051 2052
}

2053 2054
static struct intel_ring_buffer *
semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
2055 2056
{
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
2057
	u32 cmd, ipehr, acthd, acthd_min;
2058 2059 2060 2061

	ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
	if ((ipehr & ~(0x3 << 16)) !=
	    (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
2062
		return NULL;
2063 2064 2065 2066

	/* ACTHD is likely pointing to the dword after the actual command,
	 * so scan backwards until we find the MBOX.
	 */
2067
	acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
2068 2069 2070 2071 2072 2073 2074 2075
	acthd_min = max((int)acthd - 3 * 4, 0);
	do {
		cmd = ioread32(ring->virtual_start + acthd);
		if (cmd == ipehr)
			break;

		acthd -= 4;
		if (acthd < acthd_min)
2076
			return NULL;
2077 2078
	} while (1);

2079 2080
	*seqno = ioread32(ring->virtual_start+acthd+4)+1;
	return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
2081 2082
}

2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111
static int semaphore_passed(struct intel_ring_buffer *ring)
{
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
	struct intel_ring_buffer *signaller;
	u32 seqno, ctl;

	ring->hangcheck.deadlock = true;

	signaller = semaphore_waits_for(ring, &seqno);
	if (signaller == NULL || signaller->hangcheck.deadlock)
		return -1;

	/* cursory check for an unkickable deadlock */
	ctl = I915_READ_CTL(signaller);
	if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
		return -1;

	return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
}

static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
{
	struct intel_ring_buffer *ring;
	int i;

	for_each_ring(ring, dev_priv, i)
		ring->hangcheck.deadlock = false;
}

2112 2113
static enum intel_ring_hangcheck_action
ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
2114 2115 2116
{
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2117 2118
	u32 tmp;

2119
	if (ring->hangcheck.acthd != acthd)
2120
		return HANGCHECK_ACTIVE;
2121

2122
	if (IS_GEN2(dev))
2123
		return HANGCHECK_HUNG;
2124 2125 2126 2127 2128 2129 2130

	/* Is the chip hanging on a WAIT_FOR_EVENT?
	 * If so we can simply poke the RB_WAIT bit
	 * and break the hang. This should work on
	 * all but the second generation chipsets.
	 */
	tmp = I915_READ_CTL(ring);
2131 2132 2133
	if (tmp & RING_WAIT) {
		DRM_ERROR("Kicking stuck wait on %s\n",
			  ring->name);
2134
		i915_handle_error(dev, false);
2135
		I915_WRITE_CTL(ring, tmp);
2136
		return HANGCHECK_KICK;
2137 2138 2139 2140 2141
	}

	if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
		switch (semaphore_passed(ring)) {
		default:
2142
			return HANGCHECK_HUNG;
2143 2144 2145
		case 1:
			DRM_ERROR("Kicking stuck semaphore on %s\n",
				  ring->name);
2146
			i915_handle_error(dev, false);
2147
			I915_WRITE_CTL(ring, tmp);
2148
			return HANGCHECK_KICK;
2149
		case 0:
2150
			return HANGCHECK_WAIT;
2151
		}
2152
	}
2153

2154
	return HANGCHECK_HUNG;
2155 2156
}

B
Ben Gamari 已提交
2157 2158
/**
 * This is called when the chip hasn't reported back with completed
2159 2160 2161 2162 2163
 * batchbuffers in a long time. We keep track per ring seqno progress and
 * if there are no progress, hangcheck score for that ring is increased.
 * Further, acthd is inspected to see if the ring is stuck. On stuck case
 * we kick the ring. If we see no progress on three subsequent calls
 * we assume chip is wedged and try to fix it by resetting the chip.
B
Ben Gamari 已提交
2164
 */
2165
static void i915_hangcheck_elapsed(unsigned long data)
B
Ben Gamari 已提交
2166 2167 2168
{
	struct drm_device *dev = (struct drm_device *)data;
	drm_i915_private_t *dev_priv = dev->dev_private;
2169 2170
	struct intel_ring_buffer *ring;
	int i;
2171
	int busy_count = 0, rings_hung = 0;
2172 2173 2174 2175 2176
	bool stuck[I915_NUM_RINGS] = { 0 };
#define BUSY 1
#define KICK 5
#define HUNG 20
#define FIRE 30
2177

2178 2179 2180
	if (!i915_enable_hangcheck)
		return;

2181
	for_each_ring(ring, dev_priv, i) {
2182
		u32 seqno, acthd;
2183
		bool busy = true;
2184

2185 2186
		semaphore_clear_deadlocks(dev_priv);

2187 2188
		seqno = ring->get_seqno(ring, false);
		acthd = intel_ring_get_active_head(ring);
2189

2190 2191
		if (ring->hangcheck.seqno == seqno) {
			if (ring_idle(ring, seqno)) {
2192 2193
				ring->hangcheck.action = HANGCHECK_IDLE;

2194 2195
				if (waitqueue_active(&ring->irq_queue)) {
					/* Issue a wake-up to catch stuck h/w. */
2196 2197 2198 2199 2200 2201 2202
					if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
						DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
							  ring->name);
						wake_up_all(&ring->irq_queue);
					}
					/* Safeguard against driver failure */
					ring->hangcheck.score += BUSY;
2203 2204
				} else
					busy = false;
2205
			} else {
2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220
				/* We always increment the hangcheck score
				 * if the ring is busy and still processing
				 * the same request, so that no single request
				 * can run indefinitely (such as a chain of
				 * batches). The only time we do not increment
				 * the hangcheck score on this ring, if this
				 * ring is in a legitimate wait for another
				 * ring. In that case the waiting ring is a
				 * victim and we want to be sure we catch the
				 * right culprit. Then every time we do kick
				 * the ring, add a small increment to the
				 * score so that we can catch a batch that is
				 * being repeatedly kicked and so responsible
				 * for stalling the machine.
				 */
2221 2222 2223 2224
				ring->hangcheck.action = ring_stuck(ring,
								    acthd);

				switch (ring->hangcheck.action) {
2225
				case HANGCHECK_IDLE:
2226
				case HANGCHECK_WAIT:
2227
					break;
2228
				case HANGCHECK_ACTIVE:
2229
					ring->hangcheck.score += BUSY;
2230
					break;
2231
				case HANGCHECK_KICK:
2232
					ring->hangcheck.score += KICK;
2233
					break;
2234
				case HANGCHECK_HUNG:
2235
					ring->hangcheck.score += HUNG;
2236 2237 2238
					stuck[i] = true;
					break;
				}
2239
			}
2240
		} else {
2241 2242
			ring->hangcheck.action = HANGCHECK_ACTIVE;

2243 2244 2245 2246 2247
			/* Gradually reduce the count so that we catch DoS
			 * attempts across multiple batches.
			 */
			if (ring->hangcheck.score > 0)
				ring->hangcheck.score--;
2248 2249
		}

2250 2251
		ring->hangcheck.seqno = seqno;
		ring->hangcheck.acthd = acthd;
2252
		busy_count += busy;
2253
	}
2254

2255
	for_each_ring(ring, dev_priv, i) {
2256
		if (ring->hangcheck.score > FIRE) {
2257 2258 2259
			DRM_INFO("%s on %s\n",
				 stuck[i] ? "stuck" : "no progress",
				 ring->name);
2260
			rings_hung++;
2261 2262 2263
		}
	}

2264 2265
	if (rings_hung)
		return i915_handle_error(dev, true);
B
Ben Gamari 已提交
2266

2267 2268 2269
	if (busy_count)
		/* Reset timer case chip hangs without another request
		 * being added */
2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280
		i915_queue_hangcheck(dev);
}

void i915_queue_hangcheck(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	if (!i915_enable_hangcheck)
		return;

	mod_timer(&dev_priv->gpu_error.hangcheck_timer,
		  round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
B
Ben Gamari 已提交
2281 2282
}

P
Paulo Zanoni 已提交
2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301
static void ibx_irq_preinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (HAS_PCH_NOP(dev))
		return;

	/* south display irq */
	I915_WRITE(SDEIMR, 0xffffffff);
	/*
	 * SDEIER is also touched by the interrupt handler to work around missed
	 * PCH interrupts. Hence we can't update it after the interrupt handler
	 * is enabled - instead we unconditionally enable all PCH interrupt
	 * sources here, but then only unmask them as needed with SDEIMR.
	 */
	I915_WRITE(SDEIER, 0xffffffff);
	POSTING_READ(SDEIER);
}

2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318
static void gen5_gt_irq_preinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	/* and GT */
	I915_WRITE(GTIMR, 0xffffffff);
	I915_WRITE(GTIER, 0x0);
	POSTING_READ(GTIER);

	if (INTEL_INFO(dev)->gen >= 6) {
		/* and PM */
		I915_WRITE(GEN6_PMIMR, 0xffffffff);
		I915_WRITE(GEN6_PMIER, 0x0);
		POSTING_READ(GEN6_PMIER);
	}
}

L
Linus Torvalds 已提交
2319 2320
/* drm_dma.h hooks
*/
2321
static void ironlake_irq_preinstall(struct drm_device *dev)
2322 2323 2324
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;

2325 2326
	atomic_set(&dev_priv->irq_received, 0);

2327
	I915_WRITE(HWSTAM, 0xeffe);
2328

2329 2330
	I915_WRITE(DEIMR, 0xffffffff);
	I915_WRITE(DEIER, 0x0);
2331
	POSTING_READ(DEIER);
2332

2333
	gen5_gt_irq_preinstall(dev);
2334

P
Paulo Zanoni 已提交
2335
	ibx_irq_preinstall(dev);
2336 2337
}

J
Jesse Barnes 已提交
2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353
static void valleyview_irq_preinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;

	atomic_set(&dev_priv->irq_received, 0);

	/* VLV magic */
	I915_WRITE(VLV_IMR, 0);
	I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
	I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
	I915_WRITE(RING_IMR(BLT_RING_BASE), 0);

	/* and GT */
	I915_WRITE(GTIIR, I915_READ(GTIIR));
	I915_WRITE(GTIIR, I915_READ(GTIIR));
2354 2355

	gen5_gt_irq_preinstall(dev);
J
Jesse Barnes 已提交
2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368

	I915_WRITE(DPINVGTT, 0xff);

	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0xffff);
	I915_WRITE(VLV_IIR, 0xffffffff);
	I915_WRITE(VLV_IMR, 0xffffffff);
	I915_WRITE(VLV_IER, 0x0);
	POSTING_READ(VLV_IER);
}

2369
static void ibx_hpd_irq_setup(struct drm_device *dev)
2370 2371
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2372 2373
	struct drm_mode_config *mode_config = &dev->mode_config;
	struct intel_encoder *intel_encoder;
2374
	u32 hotplug_irqs, hotplug, enabled_irqs = 0;
2375 2376

	if (HAS_PCH_IBX(dev)) {
2377
		hotplug_irqs = SDE_HOTPLUG_MASK;
2378
		list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2379
			if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2380
				enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
2381
	} else {
2382
		hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
2383
		list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2384
			if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2385
				enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
2386
	}
2387

2388
	ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
2389 2390 2391 2392 2393 2394 2395

	/*
	 * Enable digital hotplug on the PCH, and configure the DP short pulse
	 * duration to 2ms (which is the minimum in the Display Port spec)
	 *
	 * This register is the same on all known PCH chips.
	 */
2396 2397 2398 2399 2400 2401 2402 2403
	hotplug = I915_READ(PCH_PORT_HOTPLUG);
	hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
	hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
	hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
	hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
}

P
Paulo Zanoni 已提交
2404 2405 2406
static void ibx_irq_postinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2407
	u32 mask;
2408

D
Daniel Vetter 已提交
2409 2410 2411
	if (HAS_PCH_NOP(dev))
		return;

2412 2413
	if (HAS_PCH_IBX(dev)) {
		mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
2414
		       SDE_TRANSA_FIFO_UNDER | SDE_POISON;
2415 2416 2417 2418 2419
	} else {
		mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;

		I915_WRITE(SERR_INT, I915_READ(SERR_INT));
	}
2420

P
Paulo Zanoni 已提交
2421 2422 2423 2424
	I915_WRITE(SDEIIR, I915_READ(SDEIIR));
	I915_WRITE(SDEIMR, ~mask);
}

2425 2426 2427 2428 2429 2430 2431 2432
static void gen5_gt_irq_postinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pm_irqs, gt_irqs;

	pm_irqs = gt_irqs = 0;

	dev_priv->gt_irq_mask = ~0;
2433
	if (HAS_L3_DPF(dev)) {
2434
		/* L3 parity interrupt is always unmasked. */
2435 2436
		dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
		gt_irqs |= GT_PARITY_ERROR(dev);
2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457
	}

	gt_irqs |= GT_RENDER_USER_INTERRUPT;
	if (IS_GEN5(dev)) {
		gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
			   ILK_BSD_USER_INTERRUPT;
	} else {
		gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
	}

	I915_WRITE(GTIIR, I915_READ(GTIIR));
	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
	I915_WRITE(GTIER, gt_irqs);
	POSTING_READ(GTIER);

	if (INTEL_INFO(dev)->gen >= 6) {
		pm_irqs |= GEN6_PM_RPS_EVENTS;

		if (HAS_VEBOX(dev))
			pm_irqs |= PM_VEBOX_USER_INTERRUPT;

2458
		dev_priv->pm_irq_mask = 0xffffffff;
2459
		I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2460
		I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
2461 2462 2463 2464 2465
		I915_WRITE(GEN6_PMIER, pm_irqs);
		POSTING_READ(GEN6_PMIER);
	}
}

2466
static int ironlake_irq_postinstall(struct drm_device *dev)
2467
{
2468
	unsigned long irqflags;
2469
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488
	u32 display_mask, extra_mask;

	if (INTEL_INFO(dev)->gen >= 7) {
		display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
				DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
				DE_PLANEB_FLIP_DONE_IVB |
				DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB |
				DE_ERR_INT_IVB);
		extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
			      DE_PIPEA_VBLANK_IVB);

		I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
	} else {
		display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
				DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
				DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
				DE_PIPEA_FIFO_UNDERRUN | DE_POISON);
		extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT;
	}
2489

2490
	dev_priv->irq_mask = ~display_mask;
2491 2492 2493

	/* should always can generate irq */
	I915_WRITE(DEIIR, I915_READ(DEIIR));
2494
	I915_WRITE(DEIMR, dev_priv->irq_mask);
2495
	I915_WRITE(DEIER, display_mask | extra_mask);
2496
	POSTING_READ(DEIER);
2497

2498
	gen5_gt_irq_postinstall(dev);
2499

P
Paulo Zanoni 已提交
2500
	ibx_irq_postinstall(dev);
2501

2502
	if (IS_IRONLAKE_M(dev)) {
2503 2504 2505
		/* Enable PCU event interrupts
		 *
		 * spinlocking not required here for correctness since interrupt
2506 2507 2508
		 * setup is guaranteed to run in single-threaded context. But we
		 * need it to make the assert_spin_locked happy. */
		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2509
		ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2510
		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2511 2512
	}

2513 2514 2515
	return 0;
}

J
Jesse Barnes 已提交
2516 2517 2518 2519
static int valleyview_irq_postinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u32 enable_mask;
2520
	u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
2521
	unsigned long irqflags;
J
Jesse Barnes 已提交
2522 2523

	enable_mask = I915_DISPLAY_PORT_INTERRUPT;
2524 2525 2526
	enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
J
Jesse Barnes 已提交
2527 2528
		I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;

2529 2530 2531 2532 2533 2534 2535
	/*
	 *Leave vblank interrupts masked initially.  enable/disable will
	 * toggle them based on usage.
	 */
	dev_priv->irq_mask = (~enable_mask) |
		I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
		I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
J
Jesse Barnes 已提交
2536

2537 2538 2539
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	POSTING_READ(PORT_HOTPLUG_EN);

J
Jesse Barnes 已提交
2540 2541 2542 2543 2544 2545 2546
	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
	I915_WRITE(VLV_IER, enable_mask);
	I915_WRITE(VLV_IIR, 0xffffffff);
	I915_WRITE(PIPESTAT(0), 0xffff);
	I915_WRITE(PIPESTAT(1), 0xffff);
	POSTING_READ(VLV_IER);

2547 2548 2549
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2550
	i915_enable_pipestat(dev_priv, 0, pipestat_enable);
2551
	i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
2552
	i915_enable_pipestat(dev_priv, 1, pipestat_enable);
2553
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2554

J
Jesse Barnes 已提交
2555 2556 2557
	I915_WRITE(VLV_IIR, 0xffffffff);
	I915_WRITE(VLV_IIR, 0xffffffff);

2558
	gen5_gt_irq_postinstall(dev);
J
Jesse Barnes 已提交
2559 2560 2561 2562 2563 2564 2565 2566

	/* ack & enable invalid PTE error interrupts */
#if 0 /* FIXME: add support to irq handler for checking these bits */
	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
	I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
#endif

	I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2567 2568 2569 2570

	return 0;
}

J
Jesse Barnes 已提交
2571 2572 2573 2574 2575 2576 2577 2578
static void valleyview_irq_uninstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;

	if (!dev_priv)
		return;

2579 2580
	del_timer_sync(&dev_priv->hotplug_reenable_timer);

J
Jesse Barnes 已提交
2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0xffff);

	I915_WRITE(HWSTAM, 0xffffffff);
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0xffff);
	I915_WRITE(VLV_IIR, 0xffffffff);
	I915_WRITE(VLV_IMR, 0xffffffff);
	I915_WRITE(VLV_IER, 0x0);
	POSTING_READ(VLV_IER);
}

2595
static void ironlake_irq_uninstall(struct drm_device *dev)
2596 2597
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2598 2599 2600 2601

	if (!dev_priv)
		return;

2602 2603
	del_timer_sync(&dev_priv->hotplug_reenable_timer);

2604 2605 2606 2607 2608
	I915_WRITE(HWSTAM, 0xffffffff);

	I915_WRITE(DEIMR, 0xffffffff);
	I915_WRITE(DEIER, 0x0);
	I915_WRITE(DEIIR, I915_READ(DEIIR));
2609 2610
	if (IS_GEN7(dev))
		I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2611 2612 2613 2614

	I915_WRITE(GTIMR, 0xffffffff);
	I915_WRITE(GTIER, 0x0);
	I915_WRITE(GTIIR, I915_READ(GTIIR));
2615

2616 2617 2618
	if (HAS_PCH_NOP(dev))
		return;

2619 2620 2621
	I915_WRITE(SDEIMR, 0xffffffff);
	I915_WRITE(SDEIER, 0x0);
	I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2622 2623
	if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
		I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2624 2625
}

2626
static void i8xx_irq_preinstall(struct drm_device * dev)
L
Linus Torvalds 已提交
2627 2628
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2629
	int pipe;
2630

2631
	atomic_set(&dev_priv->irq_received, 0);
2632

2633 2634
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0);
2635 2636 2637
	I915_WRITE16(IMR, 0xffff);
	I915_WRITE16(IER, 0x0);
	POSTING_READ16(IER);
C
Chris Wilson 已提交
2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665
}

static int i8xx_irq_postinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;

	I915_WRITE16(EMR,
		     ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));

	/* Unmask the interrupts that we always want on. */
	dev_priv->irq_mask =
		~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
		  I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
	I915_WRITE16(IMR, dev_priv->irq_mask);

	I915_WRITE16(IER,
		     I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		     I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		     I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
		     I915_USER_INTERRUPT);
	POSTING_READ16(IER);

	return 0;
}

2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696
/*
 * Returns true when a page flip has completed.
 */
static bool i8xx_handle_vblank(struct drm_device *dev,
			       int pipe, u16 iir)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);

	if (!drm_handle_vblank(dev, pipe))
		return false;

	if ((iir & flip_pending) == 0)
		return false;

	intel_prepare_page_flip(dev, pipe);

	/* We detect FlipDone by looking for the change in PendingFlip from '1'
	 * to '0' on the following vblank, i.e. IIR has the Pendingflip
	 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
	 * the flip is completed (no longer pending). Since this doesn't raise
	 * an interrupt per se, we watch for the change at vblank.
	 */
	if (I915_READ16(ISR) & flip_pending)
		return false;

	intel_finish_page_flip(dev, pipe);

	return true;
}

2697
static irqreturn_t i8xx_irq_handler(int irq, void *arg)
C
Chris Wilson 已提交
2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743
{
	struct drm_device *dev = (struct drm_device *) arg;
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u16 iir, new_iir;
	u32 pipe_stats[2];
	unsigned long irqflags;
	int pipe;
	u16 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;

	atomic_inc(&dev_priv->irq_received);

	iir = I915_READ16(IIR);
	if (iir == 0)
		return IRQ_NONE;

	while (iir & ~flip_mask) {
		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
			i915_handle_error(dev, false);

		for_each_pipe(pipe) {
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);

			/*
			 * Clear the PIPE*STAT regs before the IIR
			 */
			if (pipe_stats[pipe] & 0x8000ffff) {
				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
					DRM_DEBUG_DRIVER("pipe %c underrun\n",
							 pipe_name(pipe));
				I915_WRITE(reg, pipe_stats[pipe]);
			}
		}
		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

		I915_WRITE16(IIR, iir & ~flip_mask);
		new_iir = I915_READ16(IIR); /* Flush posted writes */

2744
		i915_update_dri1_breadcrumb(dev);
C
Chris Wilson 已提交
2745 2746 2747 2748 2749

		if (iir & I915_USER_INTERRUPT)
			notify_ring(dev, &dev_priv->ring[RCS]);

		if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2750 2751
		    i8xx_handle_vblank(dev, 0, iir))
			flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
C
Chris Wilson 已提交
2752 2753

		if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2754 2755
		    i8xx_handle_vblank(dev, 1, iir))
			flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
C
Chris Wilson 已提交
2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767 2768 2769 2770 2771 2772 2773 2774 2775 2776 2777

		iir = new_iir;
	}

	return IRQ_HANDLED;
}

static void i8xx_irq_uninstall(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;

	for_each_pipe(pipe) {
		/* Clear enable bits; then clear status bits */
		I915_WRITE(PIPESTAT(pipe), 0);
		I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
	}
	I915_WRITE16(IMR, 0xffff);
	I915_WRITE16(IER, 0x0);
	I915_WRITE16(IIR, I915_READ16(IIR));
}

2778 2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789
static void i915_irq_preinstall(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;

	atomic_set(&dev_priv->irq_received, 0);

	if (I915_HAS_HOTPLUG(dev)) {
		I915_WRITE(PORT_HOTPLUG_EN, 0);
		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	}

2790
	I915_WRITE16(HWSTAM, 0xeffe);
2791 2792 2793 2794 2795 2796 2797 2798 2799 2800
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);
	POSTING_READ(IER);
}

static int i915_irq_postinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2801
	u32 enable_mask;
2802

2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820
	I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));

	/* Unmask the interrupts that we always want on. */
	dev_priv->irq_mask =
		~(I915_ASLE_INTERRUPT |
		  I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
		  I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);

	enable_mask =
		I915_ASLE_INTERRUPT |
		I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
		I915_USER_INTERRUPT;

2821
	if (I915_HAS_HOTPLUG(dev)) {
2822 2823 2824
		I915_WRITE(PORT_HOTPLUG_EN, 0);
		POSTING_READ(PORT_HOTPLUG_EN);

2825 2826 2827 2828 2829 2830 2831 2832 2833 2834
		/* Enable in IER... */
		enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
		/* and unmask in IMR */
		dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
	}

	I915_WRITE(IMR, dev_priv->irq_mask);
	I915_WRITE(IER, enable_mask);
	POSTING_READ(IER);

2835
	i915_enable_asle_pipestat(dev);
2836 2837 2838 2839

	return 0;
}

2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869 2870
/*
 * Returns true when a page flip has completed.
 */
static bool i915_handle_vblank(struct drm_device *dev,
			       int plane, int pipe, u32 iir)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);

	if (!drm_handle_vblank(dev, pipe))
		return false;

	if ((iir & flip_pending) == 0)
		return false;

	intel_prepare_page_flip(dev, plane);

	/* We detect FlipDone by looking for the change in PendingFlip from '1'
	 * to '0' on the following vblank, i.e. IIR has the Pendingflip
	 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
	 * the flip is completed (no longer pending). Since this doesn't raise
	 * an interrupt per se, we watch for the change at vblank.
	 */
	if (I915_READ(ISR) & flip_pending)
		return false;

	intel_finish_page_flip(dev, pipe);

	return true;
}

2871
static irqreturn_t i915_irq_handler(int irq, void *arg)
2872 2873 2874
{
	struct drm_device *dev = (struct drm_device *) arg;
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2875
	u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
2876
	unsigned long irqflags;
2877 2878 2879 2880
	u32 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
	int pipe, ret = IRQ_NONE;
2881 2882 2883 2884

	atomic_inc(&dev_priv->irq_received);

	iir = I915_READ(IIR);
2885 2886
	do {
		bool irq_received = (iir & ~flip_mask) != 0;
2887
		bool blc_event = false;
2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900 2901

		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
			i915_handle_error(dev, false);

		for_each_pipe(pipe) {
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);

2902
			/* Clear the PIPE*STAT regs before the IIR */
2903 2904 2905 2906 2907
			if (pipe_stats[pipe] & 0x8000ffff) {
				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
					DRM_DEBUG_DRIVER("pipe %c underrun\n",
							 pipe_name(pipe));
				I915_WRITE(reg, pipe_stats[pipe]);
2908
				irq_received = true;
2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919
			}
		}
		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

		if (!irq_received)
			break;

		/* Consume port.  Then clear IIR or we'll miss events */
		if ((I915_HAS_HOTPLUG(dev)) &&
		    (iir & I915_DISPLAY_PORT_INTERRUPT)) {
			u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2920
			u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
2921 2922 2923

			DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
				  hotplug_status);
2924 2925 2926

			intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);

2927
			I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2928
			POSTING_READ(PORT_HOTPLUG_STAT);
2929 2930
		}

2931
		I915_WRITE(IIR, iir & ~flip_mask);
2932 2933 2934 2935 2936 2937
		new_iir = I915_READ(IIR); /* Flush posted writes */

		if (iir & I915_USER_INTERRUPT)
			notify_ring(dev, &dev_priv->ring[RCS]);

		for_each_pipe(pipe) {
2938 2939 2940
			int plane = pipe;
			if (IS_MOBILE(dev))
				plane = !plane;
2941

2942
			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
2943 2944
			    i915_handle_vblank(dev, plane, pipe, iir))
				flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 2956 2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967

			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
				blc_event = true;
		}

		if (blc_event || (iir & I915_ASLE_INTERRUPT))
			intel_opregion_asle_intr(dev);

		/* With MSI, interrupts are only generated when iir
		 * transitions from zero to nonzero.  If another bit got
		 * set while we were handling the existing iir bits, then
		 * we would never get another interrupt.
		 *
		 * This is fine on non-MSI as well, as if we hit this path
		 * we avoid exiting the interrupt handler only to generate
		 * another one.
		 *
		 * Note that for MSI this could cause a stray interrupt report
		 * if an interrupt landed in the time between writing IIR and
		 * the posting read.  This should be rare enough to never
		 * trigger the 99% of 100,000 interrupts test for disabling
		 * stray interrupts.
		 */
2968
		ret = IRQ_HANDLED;
2969
		iir = new_iir;
2970
	} while (iir & ~flip_mask);
2971

2972
	i915_update_dri1_breadcrumb(dev);
2973

2974 2975 2976 2977 2978 2979 2980 2981
	return ret;
}

static void i915_irq_uninstall(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;

2982 2983
	del_timer_sync(&dev_priv->hotplug_reenable_timer);

2984 2985 2986 2987 2988
	if (I915_HAS_HOTPLUG(dev)) {
		I915_WRITE(PORT_HOTPLUG_EN, 0);
		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	}

2989
	I915_WRITE16(HWSTAM, 0xffff);
2990 2991
	for_each_pipe(pipe) {
		/* Clear enable bits; then clear status bits */
2992
		I915_WRITE(PIPESTAT(pipe), 0);
2993 2994
		I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
	}
2995 2996 2997 2998 2999 3000 3001 3002 3003 3004 3005 3006 3007
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);

	I915_WRITE(IIR, I915_READ(IIR));
}

static void i965_irq_preinstall(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;

	atomic_set(&dev_priv->irq_received, 0);

3008 3009
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020 3021

	I915_WRITE(HWSTAM, 0xeffe);
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);
	POSTING_READ(IER);
}

static int i965_irq_postinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3022
	u32 enable_mask;
3023
	u32 error_mask;
3024
	unsigned long irqflags;
3025 3026

	/* Unmask the interrupts that we always want on. */
3027
	dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
3028
			       I915_DISPLAY_PORT_INTERRUPT |
3029 3030 3031 3032 3033 3034 3035
			       I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
			       I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
			       I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
			       I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
			       I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);

	enable_mask = ~dev_priv->irq_mask;
3036 3037
	enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
			 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3038 3039 3040 3041
	enable_mask |= I915_USER_INTERRUPT;

	if (IS_G4X(dev))
		enable_mask |= I915_BSD_USER_INTERRUPT;
3042

3043 3044 3045
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3046
	i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
3047
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3048 3049 3050 3051 3052 3053 3054 3055 3056 3057 3058 3059 3060 3061 3062 3063 3064 3065 3066 3067

	/*
	 * Enable some error detection, note the instruction error mask
	 * bit is reserved, so we leave it masked.
	 */
	if (IS_G4X(dev)) {
		error_mask = ~(GM45_ERROR_PAGE_TABLE |
			       GM45_ERROR_MEM_PRIV |
			       GM45_ERROR_CP_PRIV |
			       I915_ERROR_MEMORY_REFRESH);
	} else {
		error_mask = ~(I915_ERROR_PAGE_TABLE |
			       I915_ERROR_MEMORY_REFRESH);
	}
	I915_WRITE(EMR, error_mask);

	I915_WRITE(IMR, dev_priv->irq_mask);
	I915_WRITE(IER, enable_mask);
	POSTING_READ(IER);

3068 3069 3070
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	POSTING_READ(PORT_HOTPLUG_EN);

3071
	i915_enable_asle_pipestat(dev);
3072 3073 3074 3075

	return 0;
}

3076
static void i915_hpd_irq_setup(struct drm_device *dev)
3077 3078
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3079
	struct drm_mode_config *mode_config = &dev->mode_config;
3080
	struct intel_encoder *intel_encoder;
3081 3082
	u32 hotplug_en;

3083 3084
	assert_spin_locked(&dev_priv->irq_lock);

3085 3086 3087 3088
	if (I915_HAS_HOTPLUG(dev)) {
		hotplug_en = I915_READ(PORT_HOTPLUG_EN);
		hotplug_en &= ~HOTPLUG_INT_EN_MASK;
		/* Note HDMI and DP share hotplug bits */
3089
		/* enable bits are the same for all generations */
3090 3091 3092
		list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
			if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
				hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
3093 3094 3095 3096 3097 3098
		/* Programming the CRT detection parameters tends
		   to generate a spurious hotplug event about three
		   seconds later.  So just do it once.
		*/
		if (IS_G4X(dev))
			hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
3099
		hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
3100
		hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
3101

3102 3103 3104
		/* Ignore TV since it's buggy */
		I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
	}
3105 3106
}

3107
static irqreturn_t i965_irq_handler(int irq, void *arg)
3108 3109 3110 3111 3112 3113 3114 3115
{
	struct drm_device *dev = (struct drm_device *) arg;
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u32 iir, new_iir;
	u32 pipe_stats[I915_MAX_PIPES];
	unsigned long irqflags;
	int irq_received;
	int ret = IRQ_NONE, pipe;
3116 3117 3118
	u32 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3119 3120 3121 3122 3123 3124

	atomic_inc(&dev_priv->irq_received);

	iir = I915_READ(IIR);

	for (;;) {
3125 3126
		bool blc_event = false;

3127
		irq_received = (iir & ~flip_mask) != 0;
3128 3129 3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160

		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
			i915_handle_error(dev, false);

		for_each_pipe(pipe) {
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);

			/*
			 * Clear the PIPE*STAT regs before the IIR
			 */
			if (pipe_stats[pipe] & 0x8000ffff) {
				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
					DRM_DEBUG_DRIVER("pipe %c underrun\n",
							 pipe_name(pipe));
				I915_WRITE(reg, pipe_stats[pipe]);
				irq_received = 1;
			}
		}
		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

		if (!irq_received)
			break;

		ret = IRQ_HANDLED;

		/* Consume port.  Then clear IIR or we'll miss events */
3161
		if (iir & I915_DISPLAY_PORT_INTERRUPT) {
3162
			u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3163 3164
			u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
								  HOTPLUG_INT_STATUS_G4X :
3165
								  HOTPLUG_INT_STATUS_I915);
3166 3167 3168

			DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
				  hotplug_status);
3169 3170 3171 3172

			intel_hpd_irq_handler(dev, hotplug_trigger,
					      IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i915);

3173 3174 3175 3176
			I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
			I915_READ(PORT_HOTPLUG_STAT);
		}

3177
		I915_WRITE(IIR, iir & ~flip_mask);
3178 3179 3180 3181 3182 3183 3184 3185
		new_iir = I915_READ(IIR); /* Flush posted writes */

		if (iir & I915_USER_INTERRUPT)
			notify_ring(dev, &dev_priv->ring[RCS]);
		if (iir & I915_BSD_USER_INTERRUPT)
			notify_ring(dev, &dev_priv->ring[VCS]);

		for_each_pipe(pipe) {
3186
			if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
3187 3188
			    i915_handle_vblank(dev, pipe, pipe, iir))
				flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
3189 3190 3191 3192 3193 3194 3195 3196 3197

			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
				blc_event = true;
		}


		if (blc_event || (iir & I915_ASLE_INTERRUPT))
			intel_opregion_asle_intr(dev);

3198 3199 3200
		if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
			gmbus_irq_handler(dev);

3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211 3212 3213 3214 3215 3216 3217 3218
		/* With MSI, interrupts are only generated when iir
		 * transitions from zero to nonzero.  If another bit got
		 * set while we were handling the existing iir bits, then
		 * we would never get another interrupt.
		 *
		 * This is fine on non-MSI as well, as if we hit this path
		 * we avoid exiting the interrupt handler only to generate
		 * another one.
		 *
		 * Note that for MSI this could cause a stray interrupt report
		 * if an interrupt landed in the time between writing IIR and
		 * the posting read.  This should be rare enough to never
		 * trigger the 99% of 100,000 interrupts test for disabling
		 * stray interrupts.
		 */
		iir = new_iir;
	}

3219
	i915_update_dri1_breadcrumb(dev);
3220

3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231
	return ret;
}

static void i965_irq_uninstall(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;

	if (!dev_priv)
		return;

3232 3233
	del_timer_sync(&dev_priv->hotplug_reenable_timer);

3234 3235
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247 3248

	I915_WRITE(HWSTAM, 0xffffffff);
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);

	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe),
			   I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
	I915_WRITE(IIR, I915_READ(IIR));
}

3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260 3261 3262 3263 3264 3265 3266 3267 3268 3269 3270 3271 3272 3273 3274 3275 3276 3277 3278 3279 3280 3281 3282 3283
static void i915_reenable_hotplug_timer_func(unsigned long data)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
	struct drm_device *dev = dev_priv->dev;
	struct drm_mode_config *mode_config = &dev->mode_config;
	unsigned long irqflags;
	int i;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
	for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
		struct drm_connector *connector;

		if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
			continue;

		dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;

		list_for_each_entry(connector, &mode_config->connector_list, head) {
			struct intel_connector *intel_connector = to_intel_connector(connector);

			if (intel_connector->encoder->hpd_pin == i) {
				if (connector->polled != intel_connector->polled)
					DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
							 drm_get_connector_name(connector));
				connector->polled = intel_connector->polled;
				if (!connector->polled)
					connector->polled = DRM_CONNECTOR_POLL_HPD;
			}
		}
	}
	if (dev_priv->display.hpd_irq_setup)
		dev_priv->display.hpd_irq_setup(dev);
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

3284 3285
void intel_irq_init(struct drm_device *dev)
{
3286 3287 3288
	struct drm_i915_private *dev_priv = dev->dev_private;

	INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
3289
	INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
3290
	INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
3291
	INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
3292

3293 3294
	setup_timer(&dev_priv->gpu_error.hangcheck_timer,
		    i915_hangcheck_elapsed,
3295
		    (unsigned long) dev);
3296 3297
	setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
		    (unsigned long) dev_priv);
3298

3299
	pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
3300

3301 3302 3303 3304
	if (IS_GEN2(dev)) {
		dev->max_vblank_count = 0;
		dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
	} else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
3305 3306
		dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
		dev->driver->get_vblank_counter = gm45_get_vblank_counter;
3307 3308 3309
	} else {
		dev->driver->get_vblank_counter = i915_get_vblank_counter;
		dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
3310 3311
	}

3312
	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
3313
		dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
3314 3315
		dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
	}
3316

J
Jesse Barnes 已提交
3317 3318 3319 3320 3321 3322 3323
	if (IS_VALLEYVIEW(dev)) {
		dev->driver->irq_handler = valleyview_irq_handler;
		dev->driver->irq_preinstall = valleyview_irq_preinstall;
		dev->driver->irq_postinstall = valleyview_irq_postinstall;
		dev->driver->irq_uninstall = valleyview_irq_uninstall;
		dev->driver->enable_vblank = valleyview_enable_vblank;
		dev->driver->disable_vblank = valleyview_disable_vblank;
3324
		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3325 3326 3327 3328 3329 3330 3331
	} else if (HAS_PCH_SPLIT(dev)) {
		dev->driver->irq_handler = ironlake_irq_handler;
		dev->driver->irq_preinstall = ironlake_irq_preinstall;
		dev->driver->irq_postinstall = ironlake_irq_postinstall;
		dev->driver->irq_uninstall = ironlake_irq_uninstall;
		dev->driver->enable_vblank = ironlake_enable_vblank;
		dev->driver->disable_vblank = ironlake_disable_vblank;
3332
		dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3333
	} else {
C
Chris Wilson 已提交
3334 3335 3336 3337 3338
		if (INTEL_INFO(dev)->gen == 2) {
			dev->driver->irq_preinstall = i8xx_irq_preinstall;
			dev->driver->irq_postinstall = i8xx_irq_postinstall;
			dev->driver->irq_handler = i8xx_irq_handler;
			dev->driver->irq_uninstall = i8xx_irq_uninstall;
3339 3340 3341 3342 3343
		} else if (INTEL_INFO(dev)->gen == 3) {
			dev->driver->irq_preinstall = i915_irq_preinstall;
			dev->driver->irq_postinstall = i915_irq_postinstall;
			dev->driver->irq_uninstall = i915_irq_uninstall;
			dev->driver->irq_handler = i915_irq_handler;
3344
			dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
C
Chris Wilson 已提交
3345
		} else {
3346 3347 3348 3349
			dev->driver->irq_preinstall = i965_irq_preinstall;
			dev->driver->irq_postinstall = i965_irq_postinstall;
			dev->driver->irq_uninstall = i965_irq_uninstall;
			dev->driver->irq_handler = i965_irq_handler;
3350
			dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
C
Chris Wilson 已提交
3351
		}
3352 3353 3354 3355
		dev->driver->enable_vblank = i915_enable_vblank;
		dev->driver->disable_vblank = i915_disable_vblank;
	}
}
3356 3357 3358 3359

void intel_hpd_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
3360 3361
	struct drm_mode_config *mode_config = &dev->mode_config;
	struct drm_connector *connector;
3362
	unsigned long irqflags;
3363
	int i;
3364

3365 3366 3367 3368 3369 3370 3371 3372 3373 3374
	for (i = 1; i < HPD_NUM_PINS; i++) {
		dev_priv->hpd_stats[i].hpd_cnt = 0;
		dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
	}
	list_for_each_entry(connector, &mode_config->connector_list, head) {
		struct intel_connector *intel_connector = to_intel_connector(connector);
		connector->polled = intel_connector->polled;
		if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
			connector->polled = DRM_CONNECTOR_POLL_HPD;
	}
3375 3376 3377 3378

	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked checks happy. */
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3379 3380
	if (dev_priv->display.hpd_irq_setup)
		dev_priv->display.hpd_irq_setup(dev);
3381
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3382
}
3383 3384 3385 3386 3387 3388 3389 3390 3391 3392 3393 3394 3395 3396 3397 3398 3399 3400 3401 3402 3403 3404 3405 3406 3407 3408 3409 3410 3411 3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423 3424 3425 3426 3427 3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438 3439 3440 3441 3442 3443 3444 3445 3446

/* Disable interrupts so we can allow Package C8+. */
void hsw_pc8_disable_interrupts(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);

	dev_priv->pc8.regsave.deimr = I915_READ(DEIMR);
	dev_priv->pc8.regsave.sdeimr = I915_READ(SDEIMR);
	dev_priv->pc8.regsave.gtimr = I915_READ(GTIMR);
	dev_priv->pc8.regsave.gtier = I915_READ(GTIER);
	dev_priv->pc8.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR);

	ironlake_disable_display_irq(dev_priv, ~DE_PCH_EVENT_IVB);
	ibx_disable_display_interrupt(dev_priv, ~SDE_HOTPLUG_MASK_CPT);
	ilk_disable_gt_irq(dev_priv, 0xffffffff);
	snb_disable_pm_irq(dev_priv, 0xffffffff);

	dev_priv->pc8.irqs_disabled = true;

	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

/* Restore interrupts so we can recover from Package C8+. */
void hsw_pc8_restore_interrupts(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long irqflags;
	uint32_t val, expected;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);

	val = I915_READ(DEIMR);
	expected = ~DE_PCH_EVENT_IVB;
	WARN(val != expected, "DEIMR is 0x%08x, not 0x%08x\n", val, expected);

	val = I915_READ(SDEIMR) & ~SDE_HOTPLUG_MASK_CPT;
	expected = ~SDE_HOTPLUG_MASK_CPT;
	WARN(val != expected, "SDEIMR non-HPD bits are 0x%08x, not 0x%08x\n",
	     val, expected);

	val = I915_READ(GTIMR);
	expected = 0xffffffff;
	WARN(val != expected, "GTIMR is 0x%08x, not 0x%08x\n", val, expected);

	val = I915_READ(GEN6_PMIMR);
	expected = 0xffffffff;
	WARN(val != expected, "GEN6_PMIMR is 0x%08x, not 0x%08x\n", val,
	     expected);

	dev_priv->pc8.irqs_disabled = false;

	ironlake_enable_display_irq(dev_priv, ~dev_priv->pc8.regsave.deimr);
	ibx_enable_display_interrupt(dev_priv,
				     ~dev_priv->pc8.regsave.sdeimr &
				     ~SDE_HOTPLUG_MASK_CPT);
	ilk_enable_gt_irq(dev_priv, ~dev_priv->pc8.regsave.gtimr);
	snb_enable_pm_irq(dev_priv, ~dev_priv->pc8.regsave.gen6_pmimr);
	I915_WRITE(GTIER, dev_priv->pc8.regsave.gtier);

	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}