i915_irq.c 126.4 KB
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/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
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 */
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/*
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

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#include <linux/sysrq.h>
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#include <linux/slab.h>
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#include <linux/circ_buf.h>
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#include <drm/drmP.h>
#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#include "i915_trace.h"
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#include "intel_drv.h"
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/**
 * DOC: interrupt handling
 *
 * These functions provide the basic support for enabling and disabling the
 * interrupt handling support. There's a lot more functionality in i915_irq.c
 * and related files, but that will be described in separate chapters.
 */

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static const u32 hpd_ilk[HPD_NUM_PINS] = {
	[HPD_PORT_A] = DE_DP_A_HOTPLUG,
};

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static const u32 hpd_ivb[HPD_NUM_PINS] = {
	[HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
};

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static const u32 hpd_bdw[HPD_NUM_PINS] = {
	[HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
};

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static const u32 hpd_ibx[HPD_NUM_PINS] = {
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	[HPD_CRT] = SDE_CRT_HOTPLUG,
	[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
	[HPD_PORT_B] = SDE_PORTB_HOTPLUG,
	[HPD_PORT_C] = SDE_PORTC_HOTPLUG,
	[HPD_PORT_D] = SDE_PORTD_HOTPLUG
};

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static const u32 hpd_cpt[HPD_NUM_PINS] = {
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	[HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
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	[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
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	[HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
	[HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
	[HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
};

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static const u32 hpd_spt[HPD_NUM_PINS] = {
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	[HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
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	[HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
	[HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
	[HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
	[HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
};

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static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
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	[HPD_CRT] = CRT_HOTPLUG_INT_EN,
	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
	[HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
	[HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
	[HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
};

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static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
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	[HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
	[HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
	[HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
	[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
};

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static const u32 hpd_status_i915[HPD_NUM_PINS] = {
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	[HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
	[HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
	[HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
	[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
};

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/* BXT hpd list */
static const u32 hpd_bxt[HPD_NUM_PINS] = {
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	[HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
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	[HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
	[HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
};

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/* IIR can theoretically queue up two events. Be paranoid. */
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#define GEN8_IRQ_RESET_NDX(type, which) do { \
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	I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
	POSTING_READ(GEN8_##type##_IMR(which)); \
	I915_WRITE(GEN8_##type##_IER(which), 0); \
	I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
	POSTING_READ(GEN8_##type##_IIR(which)); \
	I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
	POSTING_READ(GEN8_##type##_IIR(which)); \
} while (0)

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#define GEN5_IRQ_RESET(type) do { \
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	I915_WRITE(type##IMR, 0xffffffff); \
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	POSTING_READ(type##IMR); \
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	I915_WRITE(type##IER, 0); \
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	I915_WRITE(type##IIR, 0xffffffff); \
	POSTING_READ(type##IIR); \
	I915_WRITE(type##IIR, 0xffffffff); \
	POSTING_READ(type##IIR); \
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} while (0)

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/*
 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
 */
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static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv,
				    i915_reg_t reg)
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{
	u32 val = I915_READ(reg);

	if (val == 0)
		return;

	WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
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	     i915_mmio_reg_offset(reg), val);
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	I915_WRITE(reg, 0xffffffff);
	POSTING_READ(reg);
	I915_WRITE(reg, 0xffffffff);
	POSTING_READ(reg);
}
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#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
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	gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
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	I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
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	I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
	POSTING_READ(GEN8_##type##_IMR(which)); \
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} while (0)

#define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
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	gen5_assert_iir_is_zero(dev_priv, type##IIR); \
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	I915_WRITE(type##IER, (ier_val)); \
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	I915_WRITE(type##IMR, (imr_val)); \
	POSTING_READ(type##IMR); \
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} while (0)

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static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);

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/* For display hotplug interrupt */
static inline void
i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
				     uint32_t mask,
				     uint32_t bits)
{
	uint32_t val;

	assert_spin_locked(&dev_priv->irq_lock);
	WARN_ON(bits & ~mask);

	val = I915_READ(PORT_HOTPLUG_EN);
	val &= ~mask;
	val |= bits;
	I915_WRITE(PORT_HOTPLUG_EN, val);
}

/**
 * i915_hotplug_interrupt_update - update hotplug interrupt enable
 * @dev_priv: driver private
 * @mask: bits to update
 * @bits: bits to enable
 * NOTE: the HPD enable bits are modified both inside and outside
 * of an interrupt context. To avoid that read-modify-write cycles
 * interfer, these bits are protected by a spinlock. Since this
 * function is usually not called from a context where the lock is
 * held already, this function acquires the lock itself. A non-locking
 * version is also available.
 */
void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
				   uint32_t mask,
				   uint32_t bits)
{
	spin_lock_irq(&dev_priv->irq_lock);
	i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
	spin_unlock_irq(&dev_priv->irq_lock);
}

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/**
 * ilk_update_display_irq - update DEIMR
 * @dev_priv: driver private
 * @interrupt_mask: mask of interrupt bits to update
 * @enabled_irq_mask: mask of interrupt bits to enable
 */
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void ilk_update_display_irq(struct drm_i915_private *dev_priv,
			    uint32_t interrupt_mask,
			    uint32_t enabled_irq_mask)
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{
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	uint32_t new_val;

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	assert_spin_locked(&dev_priv->irq_lock);

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	WARN_ON(enabled_irq_mask & ~interrupt_mask);

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	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
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		return;

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	new_val = dev_priv->irq_mask;
	new_val &= ~interrupt_mask;
	new_val |= (~enabled_irq_mask & interrupt_mask);

	if (new_val != dev_priv->irq_mask) {
		dev_priv->irq_mask = new_val;
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		I915_WRITE(DEIMR, dev_priv->irq_mask);
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		POSTING_READ(DEIMR);
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	}
}

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/**
 * ilk_update_gt_irq - update GTIMR
 * @dev_priv: driver private
 * @interrupt_mask: mask of interrupt bits to update
 * @enabled_irq_mask: mask of interrupt bits to enable
 */
static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
			      uint32_t interrupt_mask,
			      uint32_t enabled_irq_mask)
{
	assert_spin_locked(&dev_priv->irq_lock);

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	WARN_ON(enabled_irq_mask & ~interrupt_mask);

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	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
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		return;

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	dev_priv->gt_irq_mask &= ~interrupt_mask;
	dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
	POSTING_READ(GTIMR);
}

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void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
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{
	ilk_update_gt_irq(dev_priv, mask, mask);
}

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void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
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{
	ilk_update_gt_irq(dev_priv, mask, 0);
}

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static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
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{
	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
}

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static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
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{
	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
}

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static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
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{
	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
}

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/**
  * snb_update_pm_irq - update GEN6_PMIMR
  * @dev_priv: driver private
  * @interrupt_mask: mask of interrupt bits to update
  * @enabled_irq_mask: mask of interrupt bits to enable
  */
static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
			      uint32_t interrupt_mask,
			      uint32_t enabled_irq_mask)
{
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	uint32_t new_val;
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	WARN_ON(enabled_irq_mask & ~interrupt_mask);

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	assert_spin_locked(&dev_priv->irq_lock);

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	new_val = dev_priv->pm_irq_mask;
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	new_val &= ~interrupt_mask;
	new_val |= (~enabled_irq_mask & interrupt_mask);

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	if (new_val != dev_priv->pm_irq_mask) {
		dev_priv->pm_irq_mask = new_val;
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		I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
		POSTING_READ(gen6_pm_imr(dev_priv));
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	}
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}

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void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
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{
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	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
		return;

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	snb_update_pm_irq(dev_priv, mask, mask);
}

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static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
				  uint32_t mask)
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{
	snb_update_pm_irq(dev_priv, mask, 0);
}

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void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
{
	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
		return;

	__gen6_disable_pm_irq(dev_priv, mask);
}

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void gen6_reset_rps_interrupts(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
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	i915_reg_t reg = gen6_pm_iir(dev_priv);
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	spin_lock_irq(&dev_priv->irq_lock);
	I915_WRITE(reg, dev_priv->pm_rps_events);
	I915_WRITE(reg, dev_priv->pm_rps_events);
	POSTING_READ(reg);
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	dev_priv->rps.pm_iir = 0;
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	spin_unlock_irq(&dev_priv->irq_lock);
}

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void gen6_enable_rps_interrupts(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	spin_lock_irq(&dev_priv->irq_lock);
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	WARN_ON(dev_priv->rps.pm_iir);
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	WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
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	dev_priv->rps.interrupts_enabled = true;
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	I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
				dev_priv->pm_rps_events);
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	gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
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	spin_unlock_irq(&dev_priv->irq_lock);
}

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u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
{
	/*
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	 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
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	 * if GEN6_PM_UP_EI_EXPIRED is masked.
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	 *
	 * TODO: verify if this can be reproduced on VLV,CHV.
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	 */
	if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
		mask &= ~GEN6_PM_RP_UP_EI_EXPIRED;

	if (INTEL_INFO(dev_priv)->gen >= 8)
		mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;

	return mask;
}

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void gen6_disable_rps_interrupts(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

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	spin_lock_irq(&dev_priv->irq_lock);
	dev_priv->rps.interrupts_enabled = false;
	spin_unlock_irq(&dev_priv->irq_lock);

	cancel_work_sync(&dev_priv->rps.work);

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	spin_lock_irq(&dev_priv->irq_lock);

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	I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0));
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	__gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
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	I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
				~dev_priv->pm_rps_events);
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	spin_unlock_irq(&dev_priv->irq_lock);

	synchronize_irq(dev->irq);
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}

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/**
  * bdw_update_port_irq - update DE port interrupt
  * @dev_priv: driver private
  * @interrupt_mask: mask of interrupt bits to update
  * @enabled_irq_mask: mask of interrupt bits to enable
  */
static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
				uint32_t interrupt_mask,
				uint32_t enabled_irq_mask)
{
	uint32_t new_val;
	uint32_t old_val;

	assert_spin_locked(&dev_priv->irq_lock);

	WARN_ON(enabled_irq_mask & ~interrupt_mask);

	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
		return;

	old_val = I915_READ(GEN8_DE_PORT_IMR);

	new_val = old_val;
	new_val &= ~interrupt_mask;
	new_val |= (~enabled_irq_mask & interrupt_mask);

	if (new_val != old_val) {
		I915_WRITE(GEN8_DE_PORT_IMR, new_val);
		POSTING_READ(GEN8_DE_PORT_IMR);
	}
}

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/**
 * ibx_display_interrupt_update - update SDEIMR
 * @dev_priv: driver private
 * @interrupt_mask: mask of interrupt bits to update
 * @enabled_irq_mask: mask of interrupt bits to enable
 */
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void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
				  uint32_t interrupt_mask,
				  uint32_t enabled_irq_mask)
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{
	uint32_t sdeimr = I915_READ(SDEIMR);
	sdeimr &= ~interrupt_mask;
	sdeimr |= (~enabled_irq_mask & interrupt_mask);

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	WARN_ON(enabled_irq_mask & ~interrupt_mask);

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	assert_spin_locked(&dev_priv->irq_lock);

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	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
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		return;

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	I915_WRITE(SDEIMR, sdeimr);
	POSTING_READ(SDEIMR);
}
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static void
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__i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		       u32 enable_mask, u32 status_mask)
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{
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	i915_reg_t reg = PIPESTAT(pipe);
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	u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
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	assert_spin_locked(&dev_priv->irq_lock);
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	WARN_ON(!intel_irqs_enabled(dev_priv));
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	if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
		      status_mask & ~PIPESTAT_INT_STATUS_MASK,
		      "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
		      pipe_name(pipe), enable_mask, status_mask))
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		return;

	if ((pipestat & enable_mask) == enable_mask)
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		return;

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	dev_priv->pipestat_irq_mask[pipe] |= status_mask;

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	/* Enable the interrupt, clear any pending status */
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	pipestat |= enable_mask | status_mask;
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	I915_WRITE(reg, pipestat);
	POSTING_READ(reg);
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}

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static void
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__i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		        u32 enable_mask, u32 status_mask)
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{
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	i915_reg_t reg = PIPESTAT(pipe);
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	u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
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	assert_spin_locked(&dev_priv->irq_lock);
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	WARN_ON(!intel_irqs_enabled(dev_priv));
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	if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
		      status_mask & ~PIPESTAT_INT_STATUS_MASK,
		      "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
		      pipe_name(pipe), enable_mask, status_mask))
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		return;

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	if ((pipestat & enable_mask) == 0)
		return;

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	dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;

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	pipestat &= ~enable_mask;
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	I915_WRITE(reg, pipestat);
	POSTING_READ(reg);
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}

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static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
{
	u32 enable_mask = status_mask << 16;

	/*
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	 * On pipe A we don't support the PSR interrupt yet,
	 * on pipe B and C the same bit MBZ.
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	 */
	if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
		return 0;
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	/*
	 * On pipe B and C we don't support the PSR interrupt yet, on pipe
	 * A the same bit is for perf counters which we don't use either.
	 */
	if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
		return 0;
534 535 536 537 538 539 540 541 542 543 544 545

	enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
			 SPRITE0_FLIP_DONE_INT_EN_VLV |
			 SPRITE1_FLIP_DONE_INT_EN_VLV);
	if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
		enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
	if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
		enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;

	return enable_mask;
}

546 547 548 549 550 551
void
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		     u32 status_mask)
{
	u32 enable_mask;

552 553 554 555 556
	if (IS_VALLEYVIEW(dev_priv->dev))
		enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
							   status_mask);
	else
		enable_mask = status_mask << 16;
557 558 559 560 561 562 563 564 565
	__i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
}

void
i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		      u32 status_mask)
{
	u32 enable_mask;

566 567 568 569 570
	if (IS_VALLEYVIEW(dev_priv->dev))
		enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
							   status_mask);
	else
		enable_mask = status_mask << 16;
571 572 573
	__i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
}

574
/**
575
 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
576
 * @dev: drm device
577
 */
578
static void i915_enable_asle_pipestat(struct drm_device *dev)
579
{
580
	struct drm_i915_private *dev_priv = dev->dev_private;
581

582 583 584
	if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
		return;

585
	spin_lock_irq(&dev_priv->irq_lock);
586

587
	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
588
	if (INTEL_INFO(dev)->gen >= 4)
589
		i915_enable_pipestat(dev_priv, PIPE_A,
590
				     PIPE_LEGACY_BLC_EVENT_STATUS);
591

592
	spin_unlock_irq(&dev_priv->irq_lock);
593 594
}

595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644
/*
 * This timing diagram depicts the video signal in and
 * around the vertical blanking period.
 *
 * Assumptions about the fictitious mode used in this example:
 *  vblank_start >= 3
 *  vsync_start = vblank_start + 1
 *  vsync_end = vblank_start + 2
 *  vtotal = vblank_start + 3
 *
 *           start of vblank:
 *           latch double buffered registers
 *           increment frame counter (ctg+)
 *           generate start of vblank interrupt (gen4+)
 *           |
 *           |          frame start:
 *           |          generate frame start interrupt (aka. vblank interrupt) (gmch)
 *           |          may be shifted forward 1-3 extra lines via PIPECONF
 *           |          |
 *           |          |  start of vsync:
 *           |          |  generate vsync interrupt
 *           |          |  |
 * ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx
 *       .   \hs/   .      \hs/          \hs/          \hs/   .      \hs/
 * ----va---> <-----------------vb--------------------> <--------va-------------
 *       |          |       <----vs----->                     |
 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
 *       |          |                                         |
 *       last visible pixel                                   first visible pixel
 *                  |                                         increment frame counter (gen3/4)
 *                  pixel counter = vblank_start * htotal     pixel counter = 0 (gen3/4)
 *
 * x  = horizontal active
 * _  = horizontal blanking
 * hs = horizontal sync
 * va = vertical active
 * vb = vertical blanking
 * vs = vertical sync
 * vbs = vblank_start (number)
 *
 * Summary:
 * - most events happen at the start of horizontal sync
 * - frame start happens at the start of horizontal blank, 1-4 lines
 *   (depending on PIPECONF settings) after the start of vblank
 * - gen3/4 pixel and frame counter are synchronized with the start
 *   of horizontal active on the first line of vertical active
 */

645
static u32 i8xx_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
646 647 648 649 650
{
	/* Gen2 doesn't have a hardware frame counter */
	return 0;
}

651 652 653
/* Called from drm generic code, passed a 'crtc', which
 * we use as a pipe index
 */
654
static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
655
{
656
	struct drm_i915_private *dev_priv = dev->dev_private;
657
	i915_reg_t high_frame, low_frame;
658
	u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
659 660
	struct intel_crtc *intel_crtc =
		to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
661
	const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
662

663 664 665 666 667
	htotal = mode->crtc_htotal;
	hsync_start = mode->crtc_hsync_start;
	vbl_start = mode->crtc_vblank_start;
	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
		vbl_start = DIV_ROUND_UP(vbl_start, 2);
668

669 670 671 672 673 674
	/* Convert to pixel count */
	vbl_start *= htotal;

	/* Start of vblank event occurs at start of hsync */
	vbl_start -= htotal - hsync_start;

675 676
	high_frame = PIPEFRAME(pipe);
	low_frame = PIPEFRAMEPIXEL(pipe);
677

678 679 680 681 682 683
	/*
	 * High & low register fields aren't synchronized, so make sure
	 * we get a low value that's stable across two reads of the high
	 * register.
	 */
	do {
684
		high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
685
		low   = I915_READ(low_frame);
686
		high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
687 688
	} while (high1 != high2);

689
	high1 >>= PIPE_FRAME_HIGH_SHIFT;
690
	pixel = low & PIPE_PIXEL_MASK;
691
	low >>= PIPE_FRAME_LOW_SHIFT;
692 693 694 695 696 697

	/*
	 * The frame counter increments at beginning of active.
	 * Cook up a vblank counter by also checking the pixel
	 * counter against vblank start.
	 */
698
	return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
699 700
}

701
static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
702
{
703
	struct drm_i915_private *dev_priv = dev->dev_private;
704

705
	return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
706 707
}

708
/* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
709 710 711 712
static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
713
	const struct drm_display_mode *mode = &crtc->base.hwmode;
714
	enum pipe pipe = crtc->pipe;
715
	int position, vtotal;
716

717
	vtotal = mode->crtc_vtotal;
718 719 720 721
	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
		vtotal /= 2;

	if (IS_GEN2(dev))
722
		position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
723
	else
724
		position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
725

726 727 728 729 730 731 732 733 734 735 736 737
	/*
	 * On HSW, the DSL reg (0x70000) appears to return 0 if we
	 * read it just before the start of vblank.  So try it again
	 * so we don't accidentally end up spanning a vblank frame
	 * increment, causing the pipe_update_end() code to squak at us.
	 *
	 * The nature of this problem means we can't simply check the ISR
	 * bit and return the vblank start value; nor can we use the scanline
	 * debug register in the transcoder as it appears to have the same
	 * problem.  We may need to extend this to include other platforms,
	 * but so far testing only shows the problem on HSW.
	 */
738
	if (HAS_DDI(dev) && !position) {
739 740 741 742 743 744 745 746 747 748 749 750 751
		int i, temp;

		for (i = 0; i < 100; i++) {
			udelay(1);
			temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) &
				DSL_LINEMASK_GEN3;
			if (temp != position) {
				position = temp;
				break;
			}
		}
	}

752
	/*
753 754
	 * See update_scanline_offset() for the details on the
	 * scanline_offset adjustment.
755
	 */
756
	return (position + crtc->scanline_offset) % vtotal;
757 758
}

759
static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
760
				    unsigned int flags, int *vpos, int *hpos,
761 762
				    ktime_t *stime, ktime_t *etime,
				    const struct drm_display_mode *mode)
763
{
764 765 766
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
767
	int position;
768
	int vbl_start, vbl_end, hsync_start, htotal, vtotal;
769 770
	bool in_vbl = true;
	int ret = 0;
771
	unsigned long irqflags;
772

773
	if (WARN_ON(!mode->crtc_clock)) {
774
		DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
775
				 "pipe %c\n", pipe_name(pipe));
776 777 778
		return 0;
	}

779
	htotal = mode->crtc_htotal;
780
	hsync_start = mode->crtc_hsync_start;
781 782 783
	vtotal = mode->crtc_vtotal;
	vbl_start = mode->crtc_vblank_start;
	vbl_end = mode->crtc_vblank_end;
784

785 786 787 788 789 790
	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
		vbl_start = DIV_ROUND_UP(vbl_start, 2);
		vbl_end /= 2;
		vtotal /= 2;
	}

791 792
	ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;

793 794 795 796 797 798
	/*
	 * Lock uncore.lock, as we will do multiple timing critical raw
	 * register reads, potentially with preemption disabled, so the
	 * following code must not block on uncore.lock.
	 */
	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
799

800 801 802 803 804 805
	/* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */

	/* Get optional system timestamp before query. */
	if (stime)
		*stime = ktime_get();

806
	if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
807 808 809
		/* No obvious pixelcount register. Only query vertical
		 * scanout position from Display scan line register.
		 */
810
		position = __intel_get_crtc_scanline(intel_crtc);
811 812 813 814 815
	} else {
		/* Have access to pixelcount since start of frame.
		 * We can split this into vertical and horizontal
		 * scanout position.
		 */
816
		position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
817

818 819 820 821
		/* convert to pixel counts */
		vbl_start *= htotal;
		vbl_end *= htotal;
		vtotal *= htotal;
822

823 824 825 826 827 828 829 830 831 832 833 834
		/*
		 * In interlaced modes, the pixel counter counts all pixels,
		 * so one field will have htotal more pixels. In order to avoid
		 * the reported position from jumping backwards when the pixel
		 * counter is beyond the length of the shorter field, just
		 * clamp the position the length of the shorter field. This
		 * matches how the scanline counter based position works since
		 * the scanline counter doesn't count the two half lines.
		 */
		if (position >= vtotal)
			position = vtotal - 1;

835 836 837 838 839 840 841 842 843 844
		/*
		 * Start of vblank interrupt is triggered at start of hsync,
		 * just prior to the first active line of vblank. However we
		 * consider lines to start at the leading edge of horizontal
		 * active. So, should we get here before we've crossed into
		 * the horizontal active of the first line in vblank, we would
		 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
		 * always add htotal-hsync_start to the current pixel position.
		 */
		position = (position + htotal - hsync_start) % vtotal;
845 846
	}

847 848 849 850 851 852 853 854
	/* Get optional system timestamp after query. */
	if (etime)
		*etime = ktime_get();

	/* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */

	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

855 856 857 858 859 860 861 862 863 864 865 866
	in_vbl = position >= vbl_start && position < vbl_end;

	/*
	 * While in vblank, position will be negative
	 * counting up towards 0 at vbl_end. And outside
	 * vblank, position will be positive counting
	 * up since vbl_end.
	 */
	if (position >= vbl_start)
		position -= vbl_end;
	else
		position += vtotal - vbl_end;
867

868
	if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
869 870 871 872 873 874
		*vpos = position;
		*hpos = 0;
	} else {
		*vpos = position / htotal;
		*hpos = position - (*vpos * htotal);
	}
875 876 877

	/* In vblank? */
	if (in_vbl)
878
		ret |= DRM_SCANOUTPOS_IN_VBLANK;
879 880 881 882

	return ret;
}

883 884 885 886 887 888 889 890 891 892 893 894 895
int intel_get_crtc_scanline(struct intel_crtc *crtc)
{
	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
	unsigned long irqflags;
	int position;

	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
	position = __intel_get_crtc_scanline(crtc);
	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

	return position;
}

896
static int i915_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe,
897 898 899 900
			      int *max_error,
			      struct timeval *vblank_time,
			      unsigned flags)
{
901
	struct drm_crtc *crtc;
902

903 904
	if (pipe >= INTEL_INFO(dev)->num_pipes) {
		DRM_ERROR("Invalid crtc %u\n", pipe);
905 906 907 908
		return -EINVAL;
	}

	/* Get drm_crtc to timestamp: */
909 910
	crtc = intel_get_crtc_for_pipe(dev, pipe);
	if (crtc == NULL) {
911
		DRM_ERROR("Invalid crtc %u\n", pipe);
912 913 914
		return -EINVAL;
	}

915
	if (!crtc->hwmode.crtc_clock) {
916
		DRM_DEBUG_KMS("crtc %u is disabled\n", pipe);
917 918
		return -EBUSY;
	}
919 920

	/* Helper routine in DRM core does all the work: */
921 922
	return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
						     vblank_time, flags,
923
						     &crtc->hwmode);
924 925
}

926
static void ironlake_rps_change_irq_handler(struct drm_device *dev)
927
{
928
	struct drm_i915_private *dev_priv = dev->dev_private;
929
	u32 busy_up, busy_down, max_avg, min_avg;
930 931
	u8 new_delay;

932
	spin_lock(&mchdev_lock);
933

934 935
	I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));

936
	new_delay = dev_priv->ips.cur_delay;
937

938
	I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
939 940
	busy_up = I915_READ(RCPREVBSYTUPAVG);
	busy_down = I915_READ(RCPREVBSYTDNAVG);
941 942 943 944
	max_avg = I915_READ(RCBMAXAVG);
	min_avg = I915_READ(RCBMINAVG);

	/* Handle RCS change request from hw */
945
	if (busy_up > max_avg) {
946 947 948 949
		if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
			new_delay = dev_priv->ips.cur_delay - 1;
		if (new_delay < dev_priv->ips.max_delay)
			new_delay = dev_priv->ips.max_delay;
950
	} else if (busy_down < min_avg) {
951 952 953 954
		if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
			new_delay = dev_priv->ips.cur_delay + 1;
		if (new_delay > dev_priv->ips.min_delay)
			new_delay = dev_priv->ips.min_delay;
955 956
	}

957
	if (ironlake_set_drps(dev, new_delay))
958
		dev_priv->ips.cur_delay = new_delay;
959

960
	spin_unlock(&mchdev_lock);
961

962 963 964
	return;
}

C
Chris Wilson 已提交
965
static void notify_ring(struct intel_engine_cs *ring)
966
{
967
	if (!intel_ring_initialized(ring))
968 969
		return;

970
	trace_i915_gem_request_notify(ring);
971

972 973 974
	wake_up_all(&ring->irq_queue);
}

975 976
static void vlv_c0_read(struct drm_i915_private *dev_priv,
			struct intel_rps_ei *ei)
977
{
978 979 980 981
	ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
	ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
	ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
}
982

983 984 985 986 987 988
static bool vlv_c0_above(struct drm_i915_private *dev_priv,
			 const struct intel_rps_ei *old,
			 const struct intel_rps_ei *now,
			 int threshold)
{
	u64 time, c0;
989
	unsigned int mul = 100;
990

991 992
	if (old->cz_clock == 0)
		return false;
993

994 995 996
	if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
		mul <<= 8;

997
	time = now->cz_clock - old->cz_clock;
998
	time *= threshold * dev_priv->czclk_freq;
999

1000 1001 1002
	/* Workload can be split between render + media, e.g. SwapBuffers
	 * being blitted in X after being rendered in mesa. To account for
	 * this we need to combine both engines into our activity counter.
1003
	 */
1004 1005
	c0 = now->render_c0 - old->render_c0;
	c0 += now->media_c0 - old->media_c0;
1006
	c0 *= mul * VLV_CZ_CLOCK_TO_MILLI_SEC;
1007

1008
	return c0 >= time;
1009 1010
}

1011
void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1012
{
1013 1014 1015
	vlv_c0_read(dev_priv, &dev_priv->rps.down_ei);
	dev_priv->rps.up_ei = dev_priv->rps.down_ei;
}
1016

1017 1018 1019 1020
static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
{
	struct intel_rps_ei now;
	u32 events = 0;
1021

1022
	if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0)
1023
		return 0;
1024

1025 1026 1027
	vlv_c0_read(dev_priv, &now);
	if (now.cz_clock == 0)
		return 0;
1028

1029 1030 1031
	if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
		if (!vlv_c0_above(dev_priv,
				  &dev_priv->rps.down_ei, &now,
1032
				  dev_priv->rps.down_threshold))
1033 1034 1035
			events |= GEN6_PM_RP_DOWN_THRESHOLD;
		dev_priv->rps.down_ei = now;
	}
1036

1037 1038 1039
	if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
		if (vlv_c0_above(dev_priv,
				 &dev_priv->rps.up_ei, &now,
1040
				 dev_priv->rps.up_threshold))
1041 1042
			events |= GEN6_PM_RP_UP_THRESHOLD;
		dev_priv->rps.up_ei = now;
1043 1044
	}

1045
	return events;
1046 1047
}

1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059
static bool any_waiters(struct drm_i915_private *dev_priv)
{
	struct intel_engine_cs *ring;
	int i;

	for_each_ring(ring, dev_priv, i)
		if (ring->irq_refcount)
			return true;

	return false;
}

1060
static void gen6_pm_rps_work(struct work_struct *work)
1061
{
1062 1063
	struct drm_i915_private *dev_priv =
		container_of(work, struct drm_i915_private, rps.work);
1064 1065
	bool client_boost;
	int new_delay, adj, min, max;
P
Paulo Zanoni 已提交
1066
	u32 pm_iir;
1067

1068
	spin_lock_irq(&dev_priv->irq_lock);
I
Imre Deak 已提交
1069 1070 1071 1072 1073
	/* Speed up work cancelation during disabling rps interrupts. */
	if (!dev_priv->rps.interrupts_enabled) {
		spin_unlock_irq(&dev_priv->irq_lock);
		return;
	}
1074 1075
	pm_iir = dev_priv->rps.pm_iir;
	dev_priv->rps.pm_iir = 0;
1076 1077
	/* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
	gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1078 1079
	client_boost = dev_priv->rps.client_boost;
	dev_priv->rps.client_boost = false;
1080
	spin_unlock_irq(&dev_priv->irq_lock);
1081

1082
	/* Make sure we didn't queue anything we're not going to process. */
1083
	WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1084

1085
	if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1086 1087
		return;

1088
	mutex_lock(&dev_priv->rps.hw_lock);
1089

1090 1091
	pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);

1092
	adj = dev_priv->rps.last_adj;
1093
	new_delay = dev_priv->rps.cur_freq;
1094 1095 1096 1097 1098 1099 1100
	min = dev_priv->rps.min_freq_softlimit;
	max = dev_priv->rps.max_freq_softlimit;

	if (client_boost) {
		new_delay = dev_priv->rps.max_freq_softlimit;
		adj = 0;
	} else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1101 1102
		if (adj > 0)
			adj *= 2;
1103 1104
		else /* CHV needs even encode values */
			adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1105 1106 1107 1108
		/*
		 * For better performance, jump directly
		 * to RPe if we're below it.
		 */
1109
		if (new_delay < dev_priv->rps.efficient_freq - adj) {
1110
			new_delay = dev_priv->rps.efficient_freq;
1111 1112
			adj = 0;
		}
1113 1114
	} else if (any_waiters(dev_priv)) {
		adj = 0;
1115
	} else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1116 1117
		if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
			new_delay = dev_priv->rps.efficient_freq;
1118
		else
1119
			new_delay = dev_priv->rps.min_freq_softlimit;
1120 1121 1122 1123
		adj = 0;
	} else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
		if (adj < 0)
			adj *= 2;
1124 1125
		else /* CHV needs even encode values */
			adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1126
	} else { /* unknown event */
1127
		adj = 0;
1128
	}
1129

1130 1131
	dev_priv->rps.last_adj = adj;

1132 1133 1134
	/* sysfs frequency interfaces may have snuck in while servicing the
	 * interrupt
	 */
1135
	new_delay += adj;
1136
	new_delay = clamp_t(int, new_delay, min, max);
1137

1138
	intel_set_rps(dev_priv->dev, new_delay);
1139

1140
	mutex_unlock(&dev_priv->rps.hw_lock);
1141 1142
}

1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154

/**
 * ivybridge_parity_work - Workqueue called when a parity error interrupt
 * occurred.
 * @work: workqueue struct
 *
 * Doesn't actually do anything except notify userspace. As a consequence of
 * this event, userspace should try to remap the bad rows since statistically
 * it is likely the same row is more likely to go bad again.
 */
static void ivybridge_parity_work(struct work_struct *work)
{
1155 1156
	struct drm_i915_private *dev_priv =
		container_of(work, struct drm_i915_private, l3_parity.error_work);
1157
	u32 error_status, row, bank, subbank;
1158
	char *parity_event[6];
1159
	uint32_t misccpctl;
1160
	uint8_t slice = 0;
1161 1162 1163 1164 1165 1166 1167

	/* We must turn off DOP level clock gating to access the L3 registers.
	 * In order to prevent a get/put style interface, acquire struct mutex
	 * any time we access those registers.
	 */
	mutex_lock(&dev_priv->dev->struct_mutex);

1168 1169 1170 1171
	/* If we've screwed up tracking, just let the interrupt fire again */
	if (WARN_ON(!dev_priv->l3_parity.which_slice))
		goto out;

1172 1173 1174 1175
	misccpctl = I915_READ(GEN7_MISCCPCTL);
	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
	POSTING_READ(GEN7_MISCCPCTL);

1176
	while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1177
		i915_reg_t reg;
1178

1179 1180 1181
		slice--;
		if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
			break;
1182

1183
		dev_priv->l3_parity.which_slice &= ~(1<<slice);
1184

1185
		reg = GEN7_L3CDERRST1(slice);
1186

1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201
		error_status = I915_READ(reg);
		row = GEN7_PARITY_ERROR_ROW(error_status);
		bank = GEN7_PARITY_ERROR_BANK(error_status);
		subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);

		I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
		POSTING_READ(reg);

		parity_event[0] = I915_L3_PARITY_UEVENT "=1";
		parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
		parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
		parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
		parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
		parity_event[5] = NULL;

1202
		kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1203
				   KOBJ_CHANGE, parity_event);
1204

1205 1206
		DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
			  slice, row, bank, subbank);
1207

1208 1209 1210 1211 1212
		kfree(parity_event[4]);
		kfree(parity_event[3]);
		kfree(parity_event[2]);
		kfree(parity_event[1]);
	}
1213

1214
	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1215

1216 1217
out:
	WARN_ON(dev_priv->l3_parity.which_slice);
1218
	spin_lock_irq(&dev_priv->irq_lock);
1219
	gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1220
	spin_unlock_irq(&dev_priv->irq_lock);
1221 1222

	mutex_unlock(&dev_priv->dev->struct_mutex);
1223 1224
}

1225
static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1226
{
1227
	struct drm_i915_private *dev_priv = dev->dev_private;
1228

1229
	if (!HAS_L3_DPF(dev))
1230 1231
		return;

1232
	spin_lock(&dev_priv->irq_lock);
1233
	gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1234
	spin_unlock(&dev_priv->irq_lock);
1235

1236 1237 1238 1239 1240 1241 1242
	iir &= GT_PARITY_ERROR(dev);
	if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
		dev_priv->l3_parity.which_slice |= 1 << 1;

	if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
		dev_priv->l3_parity.which_slice |= 1 << 0;

1243
	queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1244 1245
}

1246 1247 1248 1249 1250 1251
static void ilk_gt_irq_handler(struct drm_device *dev,
			       struct drm_i915_private *dev_priv,
			       u32 gt_iir)
{
	if (gt_iir &
	    (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
C
Chris Wilson 已提交
1252
		notify_ring(&dev_priv->ring[RCS]);
1253
	if (gt_iir & ILK_BSD_USER_INTERRUPT)
C
Chris Wilson 已提交
1254
		notify_ring(&dev_priv->ring[VCS]);
1255 1256
}

1257 1258 1259 1260 1261
static void snb_gt_irq_handler(struct drm_device *dev,
			       struct drm_i915_private *dev_priv,
			       u32 gt_iir)
{

1262 1263
	if (gt_iir &
	    (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
C
Chris Wilson 已提交
1264
		notify_ring(&dev_priv->ring[RCS]);
1265
	if (gt_iir & GT_BSD_USER_INTERRUPT)
C
Chris Wilson 已提交
1266
		notify_ring(&dev_priv->ring[VCS]);
1267
	if (gt_iir & GT_BLT_USER_INTERRUPT)
C
Chris Wilson 已提交
1268
		notify_ring(&dev_priv->ring[BCS]);
1269

1270 1271
	if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
		      GT_BSD_CS_ERROR_INTERRUPT |
1272 1273
		      GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
		DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1274

1275 1276
	if (gt_iir & GT_PARITY_ERROR(dev))
		ivybridge_parity_error_irq_handler(dev, gt_iir);
1277 1278
}

1279
static __always_inline void
1280
gen8_cs_irq_handler(struct intel_engine_cs *ring, u32 iir, int test_shift)
1281 1282 1283 1284 1285 1286 1287
{
	if (iir & (GT_RENDER_USER_INTERRUPT << test_shift))
		notify_ring(ring);
	if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift))
		intel_lrc_irq_handler(ring);
}

C
Chris Wilson 已提交
1288
static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
1289 1290 1291 1292 1293
				       u32 master_ctl)
{
	irqreturn_t ret = IRQ_NONE;

	if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1294 1295 1296
		u32 iir = I915_READ_FW(GEN8_GT_IIR(0));
		if (iir) {
			I915_WRITE_FW(GEN8_GT_IIR(0), iir);
1297
			ret = IRQ_HANDLED;
1298

1299 1300
			gen8_cs_irq_handler(&dev_priv->ring[RCS],
					iir, GEN8_RCS_IRQ_SHIFT);
C
Chris Wilson 已提交
1301

1302 1303
			gen8_cs_irq_handler(&dev_priv->ring[BCS],
					iir, GEN8_BCS_IRQ_SHIFT);
1304 1305 1306 1307
		} else
			DRM_ERROR("The master control interrupt lied (GT0)!\n");
	}

1308
	if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1309 1310 1311
		u32 iir = I915_READ_FW(GEN8_GT_IIR(1));
		if (iir) {
			I915_WRITE_FW(GEN8_GT_IIR(1), iir);
1312
			ret = IRQ_HANDLED;
1313

1314 1315
			gen8_cs_irq_handler(&dev_priv->ring[VCS],
					iir, GEN8_VCS1_IRQ_SHIFT);
1316

1317 1318
			gen8_cs_irq_handler(&dev_priv->ring[VCS2],
					iir, GEN8_VCS2_IRQ_SHIFT);
1319
		} else
1320
			DRM_ERROR("The master control interrupt lied (GT1)!\n");
1321 1322
	}

1323
	if (master_ctl & GEN8_GT_VECS_IRQ) {
1324 1325 1326
		u32 iir = I915_READ_FW(GEN8_GT_IIR(3));
		if (iir) {
			I915_WRITE_FW(GEN8_GT_IIR(3), iir);
1327
			ret = IRQ_HANDLED;
1328

1329 1330
			gen8_cs_irq_handler(&dev_priv->ring[VECS],
					iir, GEN8_VECS_IRQ_SHIFT);
1331 1332 1333 1334
		} else
			DRM_ERROR("The master control interrupt lied (GT3)!\n");
	}

1335
	if (master_ctl & GEN8_GT_PM_IRQ) {
1336 1337
		u32 iir = I915_READ_FW(GEN8_GT_IIR(2));
		if (iir & dev_priv->pm_rps_events) {
1338
			I915_WRITE_FW(GEN8_GT_IIR(2),
1339
				      iir & dev_priv->pm_rps_events);
1340
			ret = IRQ_HANDLED;
1341
			gen6_rps_irq_handler(dev_priv, iir);
1342 1343 1344 1345
		} else
			DRM_ERROR("The master control interrupt lied (PM)!\n");
	}

1346 1347 1348
	return ret;
}

1349 1350 1351 1352
static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
{
	switch (port) {
	case PORT_A:
1353
		return val & PORTA_HOTPLUG_LONG_DETECT;
1354 1355 1356 1357 1358 1359 1360 1361 1362
	case PORT_B:
		return val & PORTB_HOTPLUG_LONG_DETECT;
	case PORT_C:
		return val & PORTC_HOTPLUG_LONG_DETECT;
	default:
		return false;
	}
}

1363 1364 1365 1366 1367 1368 1369 1370 1371 1372
static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
{
	switch (port) {
	case PORT_E:
		return val & PORTE_HOTPLUG_LONG_DETECT;
	default:
		return false;
	}
}

1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388
static bool spt_port_hotplug_long_detect(enum port port, u32 val)
{
	switch (port) {
	case PORT_A:
		return val & PORTA_HOTPLUG_LONG_DETECT;
	case PORT_B:
		return val & PORTB_HOTPLUG_LONG_DETECT;
	case PORT_C:
		return val & PORTC_HOTPLUG_LONG_DETECT;
	case PORT_D:
		return val & PORTD_HOTPLUG_LONG_DETECT;
	default:
		return false;
	}
}

1389 1390 1391 1392 1393 1394 1395 1396 1397 1398
static bool ilk_port_hotplug_long_detect(enum port port, u32 val)
{
	switch (port) {
	case PORT_A:
		return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
	default:
		return false;
	}
}

1399
static bool pch_port_hotplug_long_detect(enum port port, u32 val)
1400 1401 1402
{
	switch (port) {
	case PORT_B:
1403
		return val & PORTB_HOTPLUG_LONG_DETECT;
1404
	case PORT_C:
1405
		return val & PORTC_HOTPLUG_LONG_DETECT;
1406
	case PORT_D:
1407 1408 1409
		return val & PORTD_HOTPLUG_LONG_DETECT;
	default:
		return false;
1410 1411 1412
	}
}

1413
static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
1414 1415 1416
{
	switch (port) {
	case PORT_B:
1417
		return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1418
	case PORT_C:
1419
		return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1420
	case PORT_D:
1421 1422 1423
		return val & PORTD_HOTPLUG_INT_LONG_PULSE;
	default:
		return false;
1424 1425 1426
	}
}

1427 1428 1429 1430 1431 1432 1433
/*
 * Get a bit mask of pins that have triggered, and which ones may be long.
 * This can be called multiple times with the same masks to accumulate
 * hotplug detection results from several registers.
 *
 * Note that the caller is expected to zero out the masks initially.
 */
1434
static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
1435
			     u32 hotplug_trigger, u32 dig_hotplug_reg,
1436 1437
			     const u32 hpd[HPD_NUM_PINS],
			     bool long_pulse_detect(enum port port, u32 val))
1438
{
1439
	enum port port;
1440 1441 1442
	int i;

	for_each_hpd_pin(i) {
1443 1444
		if ((hpd[i] & hotplug_trigger) == 0)
			continue;
1445

1446 1447
		*pin_mask |= BIT(i);

1448 1449 1450
		if (!intel_hpd_pin_to_port(i, &port))
			continue;

1451
		if (long_pulse_detect(port, dig_hotplug_reg))
1452
			*long_mask |= BIT(i);
1453 1454 1455 1456 1457 1458 1459
	}

	DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
			 hotplug_trigger, dig_hotplug_reg, *pin_mask);

}

1460 1461
static void gmbus_irq_handler(struct drm_device *dev)
{
1462
	struct drm_i915_private *dev_priv = dev->dev_private;
1463 1464

	wake_up_all(&dev_priv->gmbus_wait_queue);
1465 1466
}

1467 1468
static void dp_aux_irq_handler(struct drm_device *dev)
{
1469
	struct drm_i915_private *dev_priv = dev->dev_private;
1470 1471

	wake_up_all(&dev_priv->gmbus_wait_queue);
1472 1473
}

1474
#if defined(CONFIG_DEBUG_FS)
1475 1476 1477 1478
static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
					 uint32_t crc0, uint32_t crc1,
					 uint32_t crc2, uint32_t crc3,
					 uint32_t crc4)
1479 1480 1481 1482
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
	struct intel_pipe_crc_entry *entry;
1483
	int head, tail;
1484

1485 1486
	spin_lock(&pipe_crc->lock);

1487
	if (!pipe_crc->entries) {
1488
		spin_unlock(&pipe_crc->lock);
1489
		DRM_DEBUG_KMS("spurious interrupt\n");
1490 1491 1492
		return;
	}

1493 1494
	head = pipe_crc->head;
	tail = pipe_crc->tail;
1495 1496

	if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1497
		spin_unlock(&pipe_crc->lock);
1498 1499 1500 1501 1502
		DRM_ERROR("CRC buffer overflowing\n");
		return;
	}

	entry = &pipe_crc->entries[head];
1503

1504
	entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1505 1506 1507 1508 1509
	entry->crc[0] = crc0;
	entry->crc[1] = crc1;
	entry->crc[2] = crc2;
	entry->crc[3] = crc3;
	entry->crc[4] = crc4;
1510 1511

	head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1512 1513 1514
	pipe_crc->head = head;

	spin_unlock(&pipe_crc->lock);
1515 1516

	wake_up_interruptible(&pipe_crc->wq);
1517
}
1518 1519 1520 1521 1522 1523 1524 1525
#else
static inline void
display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
			     uint32_t crc0, uint32_t crc1,
			     uint32_t crc2, uint32_t crc3,
			     uint32_t crc4) {}
#endif

1526

1527
static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
D
Daniel Vetter 已提交
1528 1529 1530
{
	struct drm_i915_private *dev_priv = dev->dev_private;

1531 1532 1533
	display_pipe_crc_irq_handler(dev, pipe,
				     I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
				     0, 0, 0, 0);
D
Daniel Vetter 已提交
1534 1535
}

1536
static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1537 1538 1539
{
	struct drm_i915_private *dev_priv = dev->dev_private;

1540 1541 1542 1543 1544 1545
	display_pipe_crc_irq_handler(dev, pipe,
				     I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
				     I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
				     I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
				     I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
				     I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1546
}
1547

1548
static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1549 1550
{
	struct drm_i915_private *dev_priv = dev->dev_private;
1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561
	uint32_t res1, res2;

	if (INTEL_INFO(dev)->gen >= 3)
		res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
	else
		res1 = 0;

	if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
		res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
	else
		res2 = 0;
1562

1563 1564 1565 1566 1567
	display_pipe_crc_irq_handler(dev, pipe,
				     I915_READ(PIPE_CRC_RES_RED(pipe)),
				     I915_READ(PIPE_CRC_RES_GREEN(pipe)),
				     I915_READ(PIPE_CRC_RES_BLUE(pipe)),
				     res1, res2);
1568
}
1569

1570 1571 1572 1573
/* The RPS events need forcewake, so we add them to a work queue and mask their
 * IMR bits until the work is done. Other interrupts can be processed without
 * the work queue. */
static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1574
{
1575
	if (pm_iir & dev_priv->pm_rps_events) {
1576
		spin_lock(&dev_priv->irq_lock);
1577
		gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
I
Imre Deak 已提交
1578 1579 1580 1581
		if (dev_priv->rps.interrupts_enabled) {
			dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
			queue_work(dev_priv->wq, &dev_priv->rps.work);
		}
1582
		spin_unlock(&dev_priv->irq_lock);
1583 1584
	}

1585 1586 1587
	if (INTEL_INFO(dev_priv)->gen >= 8)
		return;

1588 1589
	if (HAS_VEBOX(dev_priv->dev)) {
		if (pm_iir & PM_VEBOX_USER_INTERRUPT)
C
Chris Wilson 已提交
1590
			notify_ring(&dev_priv->ring[VECS]);
B
Ben Widawsky 已提交
1591

1592 1593
		if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
			DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
B
Ben Widawsky 已提交
1594
	}
1595 1596
}

1597 1598 1599 1600 1601 1602 1603 1604
static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
{
	if (!drm_handle_vblank(dev, pipe))
		return false;

	return true;
}

1605 1606 1607
static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
1608
	u32 pipe_stats[I915_MAX_PIPES] = { };
1609 1610
	int pipe;

1611
	spin_lock(&dev_priv->irq_lock);
1612
	for_each_pipe(dev_priv, pipe) {
1613
		i915_reg_t reg;
1614
		u32 mask, iir_bit = 0;
1615

1616 1617 1618 1619 1620 1621 1622
		/*
		 * PIPESTAT bits get signalled even when the interrupt is
		 * disabled with the mask bits, and some of the status bits do
		 * not generate interrupts at all (like the underrun bit). Hence
		 * we need to be careful that we only handle what we want to
		 * handle.
		 */
1623 1624 1625

		/* fifo underruns are filterered in the underrun handler. */
		mask = PIPE_FIFO_UNDERRUN_STATUS;
1626 1627 1628 1629 1630 1631 1632 1633

		switch (pipe) {
		case PIPE_A:
			iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
			break;
		case PIPE_B:
			iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
			break;
1634 1635 1636
		case PIPE_C:
			iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
			break;
1637 1638 1639 1640 1641
		}
		if (iir & iir_bit)
			mask |= dev_priv->pipestat_irq_mask[pipe];

		if (!mask)
1642 1643 1644
			continue;

		reg = PIPESTAT(pipe);
1645 1646
		mask |= PIPESTAT_INT_ENABLE_MASK;
		pipe_stats[pipe] = I915_READ(reg) & mask;
1647 1648 1649 1650

		/*
		 * Clear the PIPE*STAT regs before the IIR
		 */
1651 1652
		if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
					PIPESTAT_INT_STATUS_MASK))
1653 1654
			I915_WRITE(reg, pipe_stats[pipe]);
	}
1655
	spin_unlock(&dev_priv->irq_lock);
1656

1657
	for_each_pipe(dev_priv, pipe) {
1658 1659 1660
		if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
		    intel_pipe_handle_vblank(dev, pipe))
			intel_check_page_flip(dev, pipe);
1661

1662
		if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
1663 1664 1665 1666 1667 1668 1669
			intel_prepare_page_flip(dev, pipe);
			intel_finish_page_flip(dev, pipe);
		}

		if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
			i9xx_pipe_crc_irq_handler(dev, pipe);

1670 1671
		if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1672 1673 1674 1675 1676 1677
	}

	if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
		gmbus_irq_handler(dev);
}

1678 1679 1680 1681
static void i9xx_hpd_irq_handler(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1682
	u32 pin_mask = 0, long_mask = 0;
1683

1684 1685
	if (!hotplug_status)
		return;
1686

1687 1688 1689 1690 1691 1692
	I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
	/*
	 * Make sure hotplug status is cleared before we clear IIR, or else we
	 * may miss hotplug events.
	 */
	POSTING_READ(PORT_HOTPLUG_STAT);
1693

1694 1695
	if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
		u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1696

1697 1698 1699 1700 1701 1702 1703
		if (hotplug_trigger) {
			intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
					   hotplug_trigger, hpd_status_g4x,
					   i9xx_port_hotplug_long_detect);

			intel_hpd_irq_handler(dev, pin_mask, long_mask);
		}
1704 1705 1706

		if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
			dp_aux_irq_handler(dev);
1707 1708
	} else {
		u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1709

1710 1711
		if (hotplug_trigger) {
			intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1712
					   hotplug_trigger, hpd_status_i915,
1713 1714 1715
					   i9xx_port_hotplug_long_detect);
			intel_hpd_irq_handler(dev, pin_mask, long_mask);
		}
1716
	}
1717 1718
}

1719
static irqreturn_t valleyview_irq_handler(int irq, void *arg)
J
Jesse Barnes 已提交
1720
{
1721
	struct drm_device *dev = arg;
1722
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
1723 1724 1725
	u32 iir, gt_iir, pm_iir;
	irqreturn_t ret = IRQ_NONE;

1726 1727 1728
	if (!intel_irqs_enabled(dev_priv))
		return IRQ_NONE;

J
Jesse Barnes 已提交
1729
	while (true) {
1730 1731
		/* Find, clear, then process each source of interrupt */

J
Jesse Barnes 已提交
1732
		gt_iir = I915_READ(GTIIR);
1733 1734 1735
		if (gt_iir)
			I915_WRITE(GTIIR, gt_iir);

J
Jesse Barnes 已提交
1736
		pm_iir = I915_READ(GEN6_PMIIR);
1737 1738 1739 1740 1741 1742 1743 1744 1745 1746
		if (pm_iir)
			I915_WRITE(GEN6_PMIIR, pm_iir);

		iir = I915_READ(VLV_IIR);
		if (iir) {
			/* Consume port before clearing IIR or we'll miss events */
			if (iir & I915_DISPLAY_PORT_INTERRUPT)
				i9xx_hpd_irq_handler(dev);
			I915_WRITE(VLV_IIR, iir);
		}
J
Jesse Barnes 已提交
1747 1748 1749 1750 1751 1752

		if (gt_iir == 0 && pm_iir == 0 && iir == 0)
			goto out;

		ret = IRQ_HANDLED;

1753 1754
		if (gt_iir)
			snb_gt_irq_handler(dev, dev_priv, gt_iir);
1755
		if (pm_iir)
1756
			gen6_rps_irq_handler(dev_priv, pm_iir);
1757 1758 1759
		/* Call regardless, as some status bits might not be
		 * signalled in iir */
		valleyview_pipestat_irq_handler(dev, iir);
J
Jesse Barnes 已提交
1760 1761 1762 1763 1764 1765
	}

out:
	return ret;
}

1766 1767
static irqreturn_t cherryview_irq_handler(int irq, void *arg)
{
1768
	struct drm_device *dev = arg;
1769 1770 1771 1772
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 master_ctl, iir;
	irqreturn_t ret = IRQ_NONE;

1773 1774 1775
	if (!intel_irqs_enabled(dev_priv))
		return IRQ_NONE;

1776 1777 1778
	for (;;) {
		master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
		iir = I915_READ(VLV_IIR);
1779

1780 1781
		if (master_ctl == 0 && iir == 0)
			break;
1782

1783 1784
		ret = IRQ_HANDLED;

1785
		I915_WRITE(GEN8_MASTER_IRQ, 0);
1786

1787
		/* Find, clear, then process each source of interrupt */
1788

1789 1790 1791 1792 1793 1794
		if (iir) {
			/* Consume port before clearing IIR or we'll miss events */
			if (iir & I915_DISPLAY_PORT_INTERRUPT)
				i9xx_hpd_irq_handler(dev);
			I915_WRITE(VLV_IIR, iir);
		}
1795

C
Chris Wilson 已提交
1796
		gen8_gt_irq_handler(dev_priv, master_ctl);
1797

1798 1799 1800
		/* Call regardless, as some status bits might not be
		 * signalled in iir */
		valleyview_pipestat_irq_handler(dev, iir);
1801

1802 1803 1804
		I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
		POSTING_READ(GEN8_MASTER_IRQ);
	}
1805

1806 1807 1808
	return ret;
}

1809 1810 1811 1812 1813 1814
static void ibx_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger,
				const u32 hpd[HPD_NUM_PINS])
{
	struct drm_i915_private *dev_priv = to_i915(dev);
	u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;

1815 1816 1817 1818 1819 1820
	/*
	 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
	 * unless we touch the hotplug register, even if hotplug_trigger is
	 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
	 * errors.
	 */
1821
	dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1822 1823 1824 1825 1826 1827 1828 1829
	if (!hotplug_trigger) {
		u32 mask = PORTA_HOTPLUG_STATUS_MASK |
			PORTD_HOTPLUG_STATUS_MASK |
			PORTC_HOTPLUG_STATUS_MASK |
			PORTB_HOTPLUG_STATUS_MASK;
		dig_hotplug_reg &= ~mask;
	}

1830
	I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1831 1832
	if (!hotplug_trigger)
		return;
1833 1834 1835 1836 1837 1838 1839 1840

	intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
			   dig_hotplug_reg, hpd,
			   pch_port_hotplug_long_detect);

	intel_hpd_irq_handler(dev, pin_mask, long_mask);
}

1841
static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1842
{
1843
	struct drm_i915_private *dev_priv = dev->dev_private;
1844
	int pipe;
1845
	u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1846

1847
	ibx_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1848

1849 1850 1851
	if (pch_iir & SDE_AUDIO_POWER_MASK) {
		int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
			       SDE_AUDIO_POWER_SHIFT);
1852
		DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1853 1854
				 port_name(port));
	}
1855

1856 1857 1858
	if (pch_iir & SDE_AUX_MASK)
		dp_aux_irq_handler(dev);

1859
	if (pch_iir & SDE_GMBUS)
1860
		gmbus_irq_handler(dev);
1861 1862 1863 1864 1865 1866 1867 1868 1869 1870

	if (pch_iir & SDE_AUDIO_HDCP_MASK)
		DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");

	if (pch_iir & SDE_AUDIO_TRANS_MASK)
		DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");

	if (pch_iir & SDE_POISON)
		DRM_ERROR("PCH poison interrupt\n");

1871
	if (pch_iir & SDE_FDI_MASK)
1872
		for_each_pipe(dev_priv, pipe)
1873 1874 1875
			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
					 pipe_name(pipe),
					 I915_READ(FDI_RX_IIR(pipe)));
1876 1877 1878 1879 1880 1881 1882 1883

	if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
		DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");

	if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
		DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");

	if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1884
		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
1885 1886

	if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1887
		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
1888 1889 1890 1891 1892 1893
}

static void ivb_err_int_handler(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 err_int = I915_READ(GEN7_ERR_INT);
D
Daniel Vetter 已提交
1894
	enum pipe pipe;
1895

1896 1897 1898
	if (err_int & ERR_INT_POISON)
		DRM_ERROR("Poison interrupt\n");

1899
	for_each_pipe(dev_priv, pipe) {
1900 1901
		if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1902

D
Daniel Vetter 已提交
1903 1904
		if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
			if (IS_IVYBRIDGE(dev))
1905
				ivb_pipe_crc_irq_handler(dev, pipe);
D
Daniel Vetter 已提交
1906
			else
1907
				hsw_pipe_crc_irq_handler(dev, pipe);
D
Daniel Vetter 已提交
1908 1909
		}
	}
1910

1911 1912 1913 1914 1915 1916 1917 1918
	I915_WRITE(GEN7_ERR_INT, err_int);
}

static void cpt_serr_int_handler(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 serr_int = I915_READ(SERR_INT);

1919 1920 1921
	if (serr_int & SERR_INT_POISON)
		DRM_ERROR("PCH poison interrupt\n");

1922
	if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1923
		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
1924 1925

	if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1926
		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
1927 1928

	if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1929
		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
1930 1931

	I915_WRITE(SERR_INT, serr_int);
1932 1933
}

1934 1935
static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
{
1936
	struct drm_i915_private *dev_priv = dev->dev_private;
1937
	int pipe;
1938
	u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1939

1940
	ibx_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1941

1942 1943 1944 1945 1946 1947
	if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
		int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
			       SDE_AUDIO_POWER_SHIFT_CPT);
		DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
				 port_name(port));
	}
1948 1949

	if (pch_iir & SDE_AUX_MASK_CPT)
1950
		dp_aux_irq_handler(dev);
1951 1952

	if (pch_iir & SDE_GMBUS_CPT)
1953
		gmbus_irq_handler(dev);
1954 1955 1956 1957 1958 1959 1960 1961

	if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
		DRM_DEBUG_DRIVER("Audio CP request interrupt\n");

	if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
		DRM_DEBUG_DRIVER("Audio CP change interrupt\n");

	if (pch_iir & SDE_FDI_MASK_CPT)
1962
		for_each_pipe(dev_priv, pipe)
1963 1964 1965
			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
					 pipe_name(pipe),
					 I915_READ(FDI_RX_IIR(pipe)));
1966 1967 1968

	if (pch_iir & SDE_ERROR_CPT)
		cpt_serr_int_handler(dev);
1969 1970
}

1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986
static void spt_irq_handler(struct drm_device *dev, u32 pch_iir)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
		~SDE_PORTE_HOTPLUG_SPT;
	u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
	u32 pin_mask = 0, long_mask = 0;

	if (hotplug_trigger) {
		u32 dig_hotplug_reg;

		dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
		I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);

		intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
				   dig_hotplug_reg, hpd_spt,
1987
				   spt_port_hotplug_long_detect);
1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007
	}

	if (hotplug2_trigger) {
		u32 dig_hotplug_reg;

		dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
		I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);

		intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger,
				   dig_hotplug_reg, hpd_spt,
				   spt_port_hotplug2_long_detect);
	}

	if (pin_mask)
		intel_hpd_irq_handler(dev, pin_mask, long_mask);

	if (pch_iir & SDE_GMBUS_CPT)
		gmbus_irq_handler(dev);
}

2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023
static void ilk_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger,
				const u32 hpd[HPD_NUM_PINS])
{
	struct drm_i915_private *dev_priv = to_i915(dev);
	u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;

	dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
	I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);

	intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
			   dig_hotplug_reg, hpd,
			   ilk_port_hotplug_long_detect);

	intel_hpd_irq_handler(dev, pin_mask, long_mask);
}

2024 2025 2026
static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2027
	enum pipe pipe;
2028 2029
	u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;

2030 2031
	if (hotplug_trigger)
		ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_ilk);
2032 2033 2034 2035 2036 2037 2038 2039 2040 2041

	if (de_iir & DE_AUX_CHANNEL_A)
		dp_aux_irq_handler(dev);

	if (de_iir & DE_GSE)
		intel_opregion_asle_intr(dev);

	if (de_iir & DE_POISON)
		DRM_ERROR("Poison interrupt\n");

2042
	for_each_pipe(dev_priv, pipe) {
2043 2044 2045
		if (de_iir & DE_PIPE_VBLANK(pipe) &&
		    intel_pipe_handle_vblank(dev, pipe))
			intel_check_page_flip(dev, pipe);
2046

2047
		if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2048
			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2049

2050 2051
		if (de_iir & DE_PIPE_CRC_DONE(pipe))
			i9xx_pipe_crc_irq_handler(dev, pipe);
2052

2053 2054 2055 2056 2057
		/* plane/pipes map 1:1 on ilk+ */
		if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
			intel_prepare_page_flip(dev, pipe);
			intel_finish_page_flip_plane(dev, pipe);
		}
2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076
	}

	/* check event from PCH */
	if (de_iir & DE_PCH_EVENT) {
		u32 pch_iir = I915_READ(SDEIIR);

		if (HAS_PCH_CPT(dev))
			cpt_irq_handler(dev, pch_iir);
		else
			ibx_irq_handler(dev, pch_iir);

		/* should clear PCH hotplug event before clear CPU irq */
		I915_WRITE(SDEIIR, pch_iir);
	}

	if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
		ironlake_rps_change_irq_handler(dev);
}

2077 2078 2079
static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2080
	enum pipe pipe;
2081 2082
	u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;

2083 2084
	if (hotplug_trigger)
		ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_ivb);
2085 2086 2087 2088 2089 2090 2091 2092 2093 2094

	if (de_iir & DE_ERR_INT_IVB)
		ivb_err_int_handler(dev);

	if (de_iir & DE_AUX_CHANNEL_A_IVB)
		dp_aux_irq_handler(dev);

	if (de_iir & DE_GSE_IVB)
		intel_opregion_asle_intr(dev);

2095
	for_each_pipe(dev_priv, pipe) {
2096 2097 2098
		if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
		    intel_pipe_handle_vblank(dev, pipe))
			intel_check_page_flip(dev, pipe);
2099 2100

		/* plane/pipes map 1:1 on ilk+ */
2101 2102 2103
		if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
			intel_prepare_page_flip(dev, pipe);
			intel_finish_page_flip_plane(dev, pipe);
2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117
		}
	}

	/* check event from PCH */
	if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
		u32 pch_iir = I915_READ(SDEIIR);

		cpt_irq_handler(dev, pch_iir);

		/* clear PCH hotplug event before clear CPU irq */
		I915_WRITE(SDEIIR, pch_iir);
	}
}

2118 2119 2120 2121 2122 2123 2124 2125
/*
 * To handle irqs with the minimum potential races with fresh interrupts, we:
 * 1 - Disable Master Interrupt Control.
 * 2 - Find the source(s) of the interrupt.
 * 3 - Clear the Interrupt Identity bits (IIR).
 * 4 - Process the interrupt(s) that had bits set in the IIRs.
 * 5 - Re-enable Master Interrupt Control.
 */
2126
static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2127
{
2128
	struct drm_device *dev = arg;
2129
	struct drm_i915_private *dev_priv = dev->dev_private;
2130
	u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2131
	irqreturn_t ret = IRQ_NONE;
2132

2133 2134 2135
	if (!intel_irqs_enabled(dev_priv))
		return IRQ_NONE;

2136 2137
	/* We get interrupts on unclaimed registers, so check for this before we
	 * do any I915_{READ,WRITE}. */
2138
	intel_uncore_check_errors(dev);
2139

2140 2141 2142
	/* disable master interrupt before clearing iir  */
	de_ier = I915_READ(DEIER);
	I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2143
	POSTING_READ(DEIER);
2144

2145 2146 2147 2148 2149
	/* Disable south interrupts. We'll only write to SDEIIR once, so further
	 * interrupts will will be stored on its back queue, and then we'll be
	 * able to process them after we restore SDEIER (as soon as we restore
	 * it, we'll get an interrupt if SDEIIR still has something to process
	 * due to its back queue). */
2150 2151 2152 2153 2154
	if (!HAS_PCH_NOP(dev)) {
		sde_ier = I915_READ(SDEIER);
		I915_WRITE(SDEIER, 0);
		POSTING_READ(SDEIER);
	}
2155

2156 2157
	/* Find, clear, then process each source of interrupt */

2158
	gt_iir = I915_READ(GTIIR);
2159
	if (gt_iir) {
2160 2161
		I915_WRITE(GTIIR, gt_iir);
		ret = IRQ_HANDLED;
2162
		if (INTEL_INFO(dev)->gen >= 6)
2163
			snb_gt_irq_handler(dev, dev_priv, gt_iir);
2164 2165
		else
			ilk_gt_irq_handler(dev, dev_priv, gt_iir);
2166 2167
	}

2168 2169
	de_iir = I915_READ(DEIIR);
	if (de_iir) {
2170 2171
		I915_WRITE(DEIIR, de_iir);
		ret = IRQ_HANDLED;
2172 2173 2174 2175
		if (INTEL_INFO(dev)->gen >= 7)
			ivb_display_irq_handler(dev, de_iir);
		else
			ilk_display_irq_handler(dev, de_iir);
2176 2177
	}

2178 2179 2180 2181 2182
	if (INTEL_INFO(dev)->gen >= 6) {
		u32 pm_iir = I915_READ(GEN6_PMIIR);
		if (pm_iir) {
			I915_WRITE(GEN6_PMIIR, pm_iir);
			ret = IRQ_HANDLED;
2183
			gen6_rps_irq_handler(dev_priv, pm_iir);
2184
		}
2185
	}
2186 2187 2188

	I915_WRITE(DEIER, de_ier);
	POSTING_READ(DEIER);
2189 2190 2191 2192
	if (!HAS_PCH_NOP(dev)) {
		I915_WRITE(SDEIER, sde_ier);
		POSTING_READ(SDEIER);
	}
2193 2194 2195 2196

	return ret;
}

2197 2198
static void bxt_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger,
				const u32 hpd[HPD_NUM_PINS])
2199
{
2200 2201
	struct drm_i915_private *dev_priv = to_i915(dev);
	u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2202

2203 2204
	dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
	I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2205

2206
	intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2207
			   dig_hotplug_reg, hpd,
2208
			   bxt_port_hotplug_long_detect);
2209

2210
	intel_hpd_irq_handler(dev, pin_mask, long_mask);
2211 2212
}

2213 2214 2215 2216 2217 2218 2219
static irqreturn_t gen8_irq_handler(int irq, void *arg)
{
	struct drm_device *dev = arg;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 master_ctl;
	irqreturn_t ret = IRQ_NONE;
	uint32_t tmp = 0;
2220
	enum pipe pipe;
J
Jesse Barnes 已提交
2221 2222
	u32 aux_mask = GEN8_AUX_CHANNEL_A;

2223 2224 2225
	if (!intel_irqs_enabled(dev_priv))
		return IRQ_NONE;

2226
	if (INTEL_INFO(dev_priv)->gen >= 9)
J
Jesse Barnes 已提交
2227 2228
		aux_mask |=  GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
			GEN9_AUX_CHANNEL_D;
2229

2230
	master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
2231 2232 2233 2234
	master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
	if (!master_ctl)
		return IRQ_NONE;

2235
	I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
2236

2237 2238
	/* Find, clear, then process each source of interrupt */

C
Chris Wilson 已提交
2239
	ret = gen8_gt_irq_handler(dev_priv, master_ctl);
2240 2241 2242 2243 2244 2245

	if (master_ctl & GEN8_DE_MISC_IRQ) {
		tmp = I915_READ(GEN8_DE_MISC_IIR);
		if (tmp) {
			I915_WRITE(GEN8_DE_MISC_IIR, tmp);
			ret = IRQ_HANDLED;
2246 2247 2248 2249
			if (tmp & GEN8_DE_MISC_GSE)
				intel_opregion_asle_intr(dev);
			else
				DRM_ERROR("Unexpected DE Misc interrupt\n");
2250
		}
2251 2252
		else
			DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2253 2254
	}

2255 2256 2257
	if (master_ctl & GEN8_DE_PORT_IRQ) {
		tmp = I915_READ(GEN8_DE_PORT_IIR);
		if (tmp) {
2258
			bool found = false;
2259 2260 2261 2262 2263 2264
			u32 hotplug_trigger = 0;

			if (IS_BROXTON(dev_priv))
				hotplug_trigger = tmp & BXT_DE_PORT_HOTPLUG_MASK;
			else if (IS_BROADWELL(dev_priv))
				hotplug_trigger = tmp & GEN8_PORT_DP_A_HOTPLUG;
2265

2266 2267
			I915_WRITE(GEN8_DE_PORT_IIR, tmp);
			ret = IRQ_HANDLED;
J
Jesse Barnes 已提交
2268

2269
			if (tmp & aux_mask) {
2270
				dp_aux_irq_handler(dev);
2271 2272 2273
				found = true;
			}

2274 2275 2276 2277 2278
			if (hotplug_trigger) {
				if (IS_BROXTON(dev))
					bxt_hpd_irq_handler(dev, hotplug_trigger, hpd_bxt);
				else
					ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_bdw);
2279 2280 2281
				found = true;
			}

S
Shashank Sharma 已提交
2282 2283 2284 2285 2286
			if (IS_BROXTON(dev) && (tmp & BXT_DE_PORT_GMBUS)) {
				gmbus_irq_handler(dev);
				found = true;
			}

2287
			if (!found)
2288
				DRM_ERROR("Unexpected DE Port interrupt\n");
2289
		}
2290 2291
		else
			DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2292 2293
	}

2294
	for_each_pipe(dev_priv, pipe) {
2295
		uint32_t pipe_iir, flip_done = 0, fault_errors = 0;
2296

2297 2298
		if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
			continue;
2299

2300 2301 2302 2303
		pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
		if (pipe_iir) {
			ret = IRQ_HANDLED;
			I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2304

2305 2306 2307
			if (pipe_iir & GEN8_PIPE_VBLANK &&
			    intel_pipe_handle_vblank(dev, pipe))
				intel_check_page_flip(dev, pipe);
2308

2309
			if (INTEL_INFO(dev_priv)->gen >= 9)
2310 2311 2312 2313 2314
				flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE;
			else
				flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE;

			if (flip_done) {
2315 2316 2317 2318 2319 2320 2321
				intel_prepare_page_flip(dev, pipe);
				intel_finish_page_flip_plane(dev, pipe);
			}

			if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
				hsw_pipe_crc_irq_handler(dev, pipe);

2322 2323 2324
			if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN)
				intel_cpu_fifo_underrun_irq_handler(dev_priv,
								    pipe);
2325

2326

2327
			if (INTEL_INFO(dev_priv)->gen >= 9)
2328 2329 2330 2331 2332
				fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
			else
				fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS;

			if (fault_errors)
2333 2334 2335
				DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
					  pipe_name(pipe),
					  pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2336
		} else
2337 2338 2339
			DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
	}

2340 2341
	if (HAS_PCH_SPLIT(dev) && !HAS_PCH_NOP(dev) &&
	    master_ctl & GEN8_DE_PCH_IRQ) {
2342 2343 2344 2345 2346 2347 2348 2349 2350
		/*
		 * FIXME(BDW): Assume for now that the new interrupt handling
		 * scheme also closed the SDE interrupt handling race we've seen
		 * on older pch-split platforms. But this needs testing.
		 */
		u32 pch_iir = I915_READ(SDEIIR);
		if (pch_iir) {
			I915_WRITE(SDEIIR, pch_iir);
			ret = IRQ_HANDLED;
2351 2352 2353 2354 2355

			if (HAS_PCH_SPT(dev_priv))
				spt_irq_handler(dev, pch_iir);
			else
				cpt_irq_handler(dev, pch_iir);
2356 2357 2358
		} else
			DRM_ERROR("The master control interrupt lied (SDE)!\n");

2359 2360
	}

2361 2362
	I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
	POSTING_READ_FW(GEN8_MASTER_IRQ);
2363 2364 2365 2366

	return ret;
}

2367 2368 2369
static void i915_error_wake_up(struct drm_i915_private *dev_priv,
			       bool reset_completed)
{
2370
	struct intel_engine_cs *ring;
2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394
	int i;

	/*
	 * Notify all waiters for GPU completion events that reset state has
	 * been changed, and that they need to restart their wait after
	 * checking for potential errors (and bail out to drop locks if there is
	 * a gpu reset pending so that i915_error_work_func can acquire them).
	 */

	/* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
	for_each_ring(ring, dev_priv, i)
		wake_up_all(&ring->irq_queue);

	/* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
	wake_up_all(&dev_priv->pending_flip_queue);

	/*
	 * Signal tasks blocked in i915_gem_wait_for_error that the pending
	 * reset state is cleared.
	 */
	if (reset_completed)
		wake_up_all(&dev_priv->gpu_error.reset_queue);
}

2395
/**
2396
 * i915_reset_and_wakeup - do process context error handling work
2397
 * @dev: drm device
2398 2399 2400 2401
 *
 * Fire an error uevent so userspace can see that a hang or error
 * was detected.
 */
2402
static void i915_reset_and_wakeup(struct drm_device *dev)
2403
{
2404 2405
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct i915_gpu_error *error = &dev_priv->gpu_error;
2406 2407 2408
	char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
	char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
	char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2409
	int ret;
2410

2411
	kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2412

2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423
	/*
	 * Note that there's only one work item which does gpu resets, so we
	 * need not worry about concurrent gpu resets potentially incrementing
	 * error->reset_counter twice. We only need to take care of another
	 * racing irq/hangcheck declaring the gpu dead for a second time. A
	 * quick check for that is good enough: schedule_work ensures the
	 * correct ordering between hang detection and this work item, and since
	 * the reset in-progress bit is only ever set by code outside of this
	 * work we don't need to worry about any other races.
	 */
	if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2424
		DRM_DEBUG_DRIVER("resetting chip\n");
2425
		kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2426
				   reset_event);
2427

2428 2429 2430 2431 2432 2433 2434 2435
		/*
		 * In most cases it's guaranteed that we get here with an RPM
		 * reference held, for example because there is a pending GPU
		 * request that won't finish until the reset is done. This
		 * isn't the case at least when we get here by doing a
		 * simulated reset via debugs, so get an RPM reference.
		 */
		intel_runtime_pm_get(dev_priv);
2436 2437 2438

		intel_prepare_reset(dev);

2439 2440 2441 2442 2443 2444
		/*
		 * All state reset _must_ be completed before we update the
		 * reset counter, for otherwise waiters might miss the reset
		 * pending state and not properly drop locks, resulting in
		 * deadlocks with the reset work.
		 */
2445 2446
		ret = i915_reset(dev);

2447
		intel_finish_reset(dev);
2448

2449 2450
		intel_runtime_pm_put(dev_priv);

2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461
		if (ret == 0) {
			/*
			 * After all the gem state is reset, increment the reset
			 * counter and wake up everyone waiting for the reset to
			 * complete.
			 *
			 * Since unlock operations are a one-sided barrier only,
			 * we need to insert a barrier here to order any seqno
			 * updates before
			 * the counter increment.
			 */
2462
			smp_mb__before_atomic();
2463 2464
			atomic_inc(&dev_priv->gpu_error.reset_counter);

2465
			kobject_uevent_env(&dev->primary->kdev->kobj,
2466
					   KOBJ_CHANGE, reset_done_event);
2467
		} else {
2468
			atomic_or(I915_WEDGED, &error->reset_counter);
2469
		}
2470

2471 2472 2473 2474 2475
		/*
		 * Note: The wake_up also serves as a memory barrier so that
		 * waiters see the update value of the reset counter atomic_t.
		 */
		i915_error_wake_up(dev_priv, true);
2476
	}
2477 2478
}

2479
static void i915_report_and_clear_eir(struct drm_device *dev)
2480 2481
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2482
	uint32_t instdone[I915_NUM_INSTDONE_REG];
2483
	u32 eir = I915_READ(EIR);
2484
	int pipe, i;
2485

2486 2487
	if (!eir)
		return;
2488

2489
	pr_err("render error detected, EIR: 0x%08x\n", eir);
2490

2491 2492
	i915_get_extra_instdone(dev, instdone);

2493 2494 2495 2496
	if (IS_G4X(dev)) {
		if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
			u32 ipeir = I915_READ(IPEIR_I965);

2497 2498
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2499 2500
			for (i = 0; i < ARRAY_SIZE(instdone); i++)
				pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2501 2502
			pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2503
			I915_WRITE(IPEIR_I965, ipeir);
2504
			POSTING_READ(IPEIR_I965);
2505 2506 2507
		}
		if (eir & GM45_ERROR_PAGE_TABLE) {
			u32 pgtbl_err = I915_READ(PGTBL_ER);
2508 2509
			pr_err("page table error\n");
			pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2510
			I915_WRITE(PGTBL_ER, pgtbl_err);
2511
			POSTING_READ(PGTBL_ER);
2512 2513 2514
		}
	}

2515
	if (!IS_GEN2(dev)) {
2516 2517
		if (eir & I915_ERROR_PAGE_TABLE) {
			u32 pgtbl_err = I915_READ(PGTBL_ER);
2518 2519
			pr_err("page table error\n");
			pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2520
			I915_WRITE(PGTBL_ER, pgtbl_err);
2521
			POSTING_READ(PGTBL_ER);
2522 2523 2524 2525
		}
	}

	if (eir & I915_ERROR_MEMORY_REFRESH) {
2526
		pr_err("memory refresh error:\n");
2527
		for_each_pipe(dev_priv, pipe)
2528
			pr_err("pipe %c stat: 0x%08x\n",
2529
			       pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2530 2531 2532
		/* pipestat has already been acked */
	}
	if (eir & I915_ERROR_INSTRUCTION) {
2533 2534
		pr_err("instruction error\n");
		pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
2535 2536
		for (i = 0; i < ARRAY_SIZE(instdone); i++)
			pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2537
		if (INTEL_INFO(dev)->gen < 4) {
2538 2539
			u32 ipeir = I915_READ(IPEIR);

2540 2541 2542
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
2543
			I915_WRITE(IPEIR, ipeir);
2544
			POSTING_READ(IPEIR);
2545 2546 2547
		} else {
			u32 ipeir = I915_READ(IPEIR_I965);

2548 2549 2550 2551
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
			pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2552
			I915_WRITE(IPEIR_I965, ipeir);
2553
			POSTING_READ(IPEIR_I965);
2554 2555 2556 2557
		}
	}

	I915_WRITE(EIR, eir);
2558
	POSTING_READ(EIR);
2559 2560 2561 2562 2563 2564 2565 2566 2567 2568
	eir = I915_READ(EIR);
	if (eir) {
		/*
		 * some errors might have become stuck,
		 * mask them.
		 */
		DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
		I915_WRITE(EMR, I915_READ(EMR) | eir);
		I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
	}
2569 2570 2571
}

/**
2572
 * i915_handle_error - handle a gpu error
2573 2574
 * @dev: drm device
 *
2575
 * Do some basic checking of register state at error time and
2576 2577 2578 2579 2580
 * dump it to the syslog.  Also call i915_capture_error_state() to make
 * sure we get a record and make it available in debugfs.  Fire a uevent
 * so userspace knows something bad happened (should trigger collection
 * of a ring dump etc.).
 */
2581 2582
void i915_handle_error(struct drm_device *dev, bool wedged,
		       const char *fmt, ...)
2583 2584
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2585 2586
	va_list args;
	char error_msg[80];
2587

2588 2589 2590 2591 2592
	va_start(args, fmt);
	vscnprintf(error_msg, sizeof(error_msg), fmt, args);
	va_end(args);

	i915_capture_error_state(dev, wedged, error_msg);
2593
	i915_report_and_clear_eir(dev);
2594

2595
	if (wedged) {
2596
		atomic_or(I915_RESET_IN_PROGRESS_FLAG,
2597
				&dev_priv->gpu_error.reset_counter);
2598

2599
		/*
2600 2601 2602
		 * Wakeup waiting processes so that the reset function
		 * i915_reset_and_wakeup doesn't deadlock trying to grab
		 * various locks. By bumping the reset counter first, the woken
2603 2604 2605 2606 2607 2608 2609 2610
		 * processes will see a reset in progress and back off,
		 * releasing their locks and then wait for the reset completion.
		 * We must do this for _all_ gpu waiters that might hold locks
		 * that the reset work needs to acquire.
		 *
		 * Note: The wake_up serves as the required memory barrier to
		 * ensure that the waiters see the updated value of the reset
		 * counter atomic_t.
2611
		 */
2612
		i915_error_wake_up(dev_priv, false);
2613 2614
	}

2615
	i915_reset_and_wakeup(dev);
2616 2617
}

2618 2619 2620
/* Called from drm generic code, passed 'crtc' which
 * we use as a pipe index
 */
2621
static int i915_enable_vblank(struct drm_device *dev, unsigned int pipe)
2622
{
2623
	struct drm_i915_private *dev_priv = dev->dev_private;
2624
	unsigned long irqflags;
2625

2626
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2627
	if (INTEL_INFO(dev)->gen >= 4)
2628
		i915_enable_pipestat(dev_priv, pipe,
2629
				     PIPE_START_VBLANK_INTERRUPT_STATUS);
2630
	else
2631
		i915_enable_pipestat(dev_priv, pipe,
2632
				     PIPE_VBLANK_INTERRUPT_STATUS);
2633
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2634

2635 2636 2637
	return 0;
}

2638
static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
2639
{
2640
	struct drm_i915_private *dev_priv = dev->dev_private;
2641
	unsigned long irqflags;
2642
	uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2643
						     DE_PIPE_VBLANK(pipe);
2644 2645

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2646
	ilk_enable_display_irq(dev_priv, bit);
2647 2648 2649 2650 2651
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

	return 0;
}

2652
static int valleyview_enable_vblank(struct drm_device *dev, unsigned int pipe)
J
Jesse Barnes 已提交
2653
{
2654
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
2655 2656 2657
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2658
	i915_enable_pipestat(dev_priv, pipe,
2659
			     PIPE_START_VBLANK_INTERRUPT_STATUS);
J
Jesse Barnes 已提交
2660 2661 2662 2663 2664
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

	return 0;
}

2665
static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
2666 2667 2668 2669 2670
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2671 2672 2673
	dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
	I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
	POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2674 2675 2676 2677
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
	return 0;
}

2678 2679 2680
/* Called from drm generic code, passed 'crtc' which
 * we use as a pipe index
 */
2681
static void i915_disable_vblank(struct drm_device *dev, unsigned int pipe)
2682
{
2683
	struct drm_i915_private *dev_priv = dev->dev_private;
2684
	unsigned long irqflags;
2685

2686
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2687
	i915_disable_pipestat(dev_priv, pipe,
2688 2689
			      PIPE_VBLANK_INTERRUPT_STATUS |
			      PIPE_START_VBLANK_INTERRUPT_STATUS);
2690 2691 2692
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

2693
static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
2694
{
2695
	struct drm_i915_private *dev_priv = dev->dev_private;
2696
	unsigned long irqflags;
2697
	uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2698
						     DE_PIPE_VBLANK(pipe);
2699 2700

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2701
	ilk_disable_display_irq(dev_priv, bit);
2702 2703 2704
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

2705
static void valleyview_disable_vblank(struct drm_device *dev, unsigned int pipe)
J
Jesse Barnes 已提交
2706
{
2707
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
2708 2709 2710
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2711
	i915_disable_pipestat(dev_priv, pipe,
2712
			      PIPE_START_VBLANK_INTERRUPT_STATUS);
J
Jesse Barnes 已提交
2713 2714 2715
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

2716
static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
2717 2718 2719 2720 2721
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2722 2723 2724
	dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
	I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
	POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2725 2726 2727
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

2728
static bool
2729
ring_idle(struct intel_engine_cs *ring, u32 seqno)
2730 2731
{
	return (list_empty(&ring->request_list) ||
2732
		i915_seqno_passed(seqno, ring->last_submitted_seqno));
B
Ben Gamari 已提交
2733 2734
}

2735 2736 2737 2738
static bool
ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
{
	if (INTEL_INFO(dev)->gen >= 8) {
2739
		return (ipehr >> 23) == 0x1c;
2740 2741 2742 2743 2744 2745 2746
	} else {
		ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
		return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
				 MI_SEMAPHORE_REGISTER);
	}
}

2747
static struct intel_engine_cs *
2748
semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset)
2749 2750
{
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
2751
	struct intel_engine_cs *signaller;
2752 2753 2754
	int i;

	if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
2755 2756 2757 2758 2759 2760 2761
		for_each_ring(signaller, dev_priv, i) {
			if (ring == signaller)
				continue;

			if (offset == signaller->semaphore.signal_ggtt[ring->id])
				return signaller;
		}
2762 2763 2764 2765 2766 2767 2768
	} else {
		u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;

		for_each_ring(signaller, dev_priv, i) {
			if(ring == signaller)
				continue;

2769
			if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
2770 2771 2772 2773
				return signaller;
		}
	}

2774 2775
	DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
		  ring->id, ipehr, offset);
2776 2777 2778 2779

	return NULL;
}

2780 2781
static struct intel_engine_cs *
semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
2782 2783
{
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
2784
	u32 cmd, ipehr, head;
2785 2786
	u64 offset = 0;
	int i, backwards;
2787

2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807
	/*
	 * This function does not support execlist mode - any attempt to
	 * proceed further into this function will result in a kernel panic
	 * when dereferencing ring->buffer, which is not set up in execlist
	 * mode.
	 *
	 * The correct way of doing it would be to derive the currently
	 * executing ring buffer from the current context, which is derived
	 * from the currently running request. Unfortunately, to get the
	 * current request we would have to grab the struct_mutex before doing
	 * anything else, which would be ill-advised since some other thread
	 * might have grabbed it already and managed to hang itself, causing
	 * the hang checker to deadlock.
	 *
	 * Therefore, this function does not support execlist mode in its
	 * current form. Just return NULL and move on.
	 */
	if (ring->buffer == NULL)
		return NULL;

2808
	ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2809
	if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
2810
		return NULL;
2811

2812 2813 2814
	/*
	 * HEAD is likely pointing to the dword after the actual command,
	 * so scan backwards until we find the MBOX. But limit it to just 3
2815 2816
	 * or 4 dwords depending on the semaphore wait command size.
	 * Note that we don't care about ACTHD here since that might
2817 2818
	 * point at at batch, and semaphores are always emitted into the
	 * ringbuffer itself.
2819
	 */
2820
	head = I915_READ_HEAD(ring) & HEAD_ADDR;
2821
	backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4;
2822

2823
	for (i = backwards; i; --i) {
2824 2825 2826 2827 2828
		/*
		 * Be paranoid and presume the hw has gone off into the wild -
		 * our ring is smaller than what the hardware (and hence
		 * HEAD_ADDR) allows. Also handles wrap-around.
		 */
2829
		head &= ring->buffer->size - 1;
2830 2831

		/* This here seems to blow up */
2832
		cmd = ioread32(ring->buffer->virtual_start + head);
2833 2834 2835
		if (cmd == ipehr)
			break;

2836 2837
		head -= 4;
	}
2838

2839 2840
	if (!i)
		return NULL;
2841

2842
	*seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
2843 2844 2845 2846 2847 2848
	if (INTEL_INFO(ring->dev)->gen >= 8) {
		offset = ioread32(ring->buffer->virtual_start + head + 12);
		offset <<= 32;
		offset = ioread32(ring->buffer->virtual_start + head + 8);
	}
	return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
2849 2850
}

2851
static int semaphore_passed(struct intel_engine_cs *ring)
2852 2853
{
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
2854
	struct intel_engine_cs *signaller;
2855
	u32 seqno;
2856

2857
	ring->hangcheck.deadlock++;
2858 2859

	signaller = semaphore_waits_for(ring, &seqno);
2860 2861 2862 2863 2864
	if (signaller == NULL)
		return -1;

	/* Prevent pathological recursion due to driver bugs */
	if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
2865 2866
		return -1;

2867 2868 2869
	if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
		return 1;

2870 2871 2872
	/* cursory check for an unkickable deadlock */
	if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
	    semaphore_passed(signaller) < 0)
2873 2874 2875
		return -1;

	return 0;
2876 2877 2878 2879
}

static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
{
2880
	struct intel_engine_cs *ring;
2881 2882 2883
	int i;

	for_each_ring(ring, dev_priv, i)
2884
		ring->hangcheck.deadlock = 0;
2885 2886
}

2887
static enum intel_ring_hangcheck_action
2888
ring_stuck(struct intel_engine_cs *ring, u64 acthd)
2889 2890 2891
{
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2892 2893
	u32 tmp;

2894 2895 2896 2897 2898 2899 2900 2901
	if (acthd != ring->hangcheck.acthd) {
		if (acthd > ring->hangcheck.max_acthd) {
			ring->hangcheck.max_acthd = acthd;
			return HANGCHECK_ACTIVE;
		}

		return HANGCHECK_ACTIVE_LOOP;
	}
2902

2903
	if (IS_GEN2(dev))
2904
		return HANGCHECK_HUNG;
2905 2906 2907 2908 2909 2910 2911

	/* Is the chip hanging on a WAIT_FOR_EVENT?
	 * If so we can simply poke the RB_WAIT bit
	 * and break the hang. This should work on
	 * all but the second generation chipsets.
	 */
	tmp = I915_READ_CTL(ring);
2912
	if (tmp & RING_WAIT) {
2913 2914 2915
		i915_handle_error(dev, false,
				  "Kicking stuck wait on %s",
				  ring->name);
2916
		I915_WRITE_CTL(ring, tmp);
2917
		return HANGCHECK_KICK;
2918 2919 2920 2921 2922
	}

	if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
		switch (semaphore_passed(ring)) {
		default:
2923
			return HANGCHECK_HUNG;
2924
		case 1:
2925 2926 2927
			i915_handle_error(dev, false,
					  "Kicking stuck semaphore on %s",
					  ring->name);
2928
			I915_WRITE_CTL(ring, tmp);
2929
			return HANGCHECK_KICK;
2930
		case 0:
2931
			return HANGCHECK_WAIT;
2932
		}
2933
	}
2934

2935
	return HANGCHECK_HUNG;
2936 2937
}

2938
/*
B
Ben Gamari 已提交
2939
 * This is called when the chip hasn't reported back with completed
2940 2941 2942 2943 2944
 * batchbuffers in a long time. We keep track per ring seqno progress and
 * if there are no progress, hangcheck score for that ring is increased.
 * Further, acthd is inspected to see if the ring is stuck. On stuck case
 * we kick the ring. If we see no progress on three subsequent calls
 * we assume chip is wedged and try to fix it by resetting the chip.
B
Ben Gamari 已提交
2945
 */
2946
static void i915_hangcheck_elapsed(struct work_struct *work)
B
Ben Gamari 已提交
2947
{
2948 2949 2950 2951
	struct drm_i915_private *dev_priv =
		container_of(work, typeof(*dev_priv),
			     gpu_error.hangcheck_work.work);
	struct drm_device *dev = dev_priv->dev;
2952
	struct intel_engine_cs *ring;
2953
	int i;
2954
	int busy_count = 0, rings_hung = 0;
2955 2956 2957 2958
	bool stuck[I915_NUM_RINGS] = { 0 };
#define BUSY 1
#define KICK 5
#define HUNG 20
2959

2960
	if (!i915.enable_hangcheck)
2961 2962
		return;

2963
	for_each_ring(ring, dev_priv, i) {
2964 2965
		u64 acthd;
		u32 seqno;
2966
		bool busy = true;
2967

2968 2969
		semaphore_clear_deadlocks(dev_priv);

2970 2971
		seqno = ring->get_seqno(ring, false);
		acthd = intel_ring_get_active_head(ring);
2972

2973
		if (ring->hangcheck.seqno == seqno) {
2974
			if (ring_idle(ring, seqno)) {
2975 2976
				ring->hangcheck.action = HANGCHECK_IDLE;

2977 2978
				if (waitqueue_active(&ring->irq_queue)) {
					/* Issue a wake-up to catch stuck h/w. */
2979
					if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2980 2981 2982 2983 2984 2985
						if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
							DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
								  ring->name);
						else
							DRM_INFO("Fake missed irq on %s\n",
								 ring->name);
2986 2987 2988 2989
						wake_up_all(&ring->irq_queue);
					}
					/* Safeguard against driver failure */
					ring->hangcheck.score += BUSY;
2990 2991
				} else
					busy = false;
2992
			} else {
2993 2994 2995 2996 2997 2998 2999 3000 3001 3002 3003 3004 3005 3006 3007
				/* We always increment the hangcheck score
				 * if the ring is busy and still processing
				 * the same request, so that no single request
				 * can run indefinitely (such as a chain of
				 * batches). The only time we do not increment
				 * the hangcheck score on this ring, if this
				 * ring is in a legitimate wait for another
				 * ring. In that case the waiting ring is a
				 * victim and we want to be sure we catch the
				 * right culprit. Then every time we do kick
				 * the ring, add a small increment to the
				 * score so that we can catch a batch that is
				 * being repeatedly kicked and so responsible
				 * for stalling the machine.
				 */
3008 3009 3010 3011
				ring->hangcheck.action = ring_stuck(ring,
								    acthd);

				switch (ring->hangcheck.action) {
3012
				case HANGCHECK_IDLE:
3013 3014
				case HANGCHECK_WAIT:
				case HANGCHECK_ACTIVE:
3015 3016
					break;
				case HANGCHECK_ACTIVE_LOOP:
3017
					ring->hangcheck.score += BUSY;
3018
					break;
3019
				case HANGCHECK_KICK:
3020
					ring->hangcheck.score += KICK;
3021
					break;
3022
				case HANGCHECK_HUNG:
3023
					ring->hangcheck.score += HUNG;
3024 3025 3026
					stuck[i] = true;
					break;
				}
3027
			}
3028
		} else {
3029 3030
			ring->hangcheck.action = HANGCHECK_ACTIVE;

3031 3032 3033 3034 3035
			/* Gradually reduce the count so that we catch DoS
			 * attempts across multiple batches.
			 */
			if (ring->hangcheck.score > 0)
				ring->hangcheck.score--;
3036 3037

			ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0;
3038 3039
		}

3040 3041
		ring->hangcheck.seqno = seqno;
		ring->hangcheck.acthd = acthd;
3042
		busy_count += busy;
3043
	}
3044

3045
	for_each_ring(ring, dev_priv, i) {
3046
		if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3047 3048 3049
			DRM_INFO("%s on %s\n",
				 stuck[i] ? "stuck" : "no progress",
				 ring->name);
3050
			rings_hung++;
3051 3052 3053
		}
	}

3054
	if (rings_hung)
3055
		return i915_handle_error(dev, true, "Ring hung");
B
Ben Gamari 已提交
3056

3057 3058 3059
	if (busy_count)
		/* Reset timer case chip hangs without another request
		 * being added */
3060 3061 3062 3063 3064
		i915_queue_hangcheck(dev);
}

void i915_queue_hangcheck(struct drm_device *dev)
{
3065
	struct i915_gpu_error *e = &to_i915(dev)->gpu_error;
3066

3067
	if (!i915.enable_hangcheck)
3068 3069
		return;

3070 3071 3072 3073 3074 3075 3076
	/* Don't continually defer the hangcheck so that it is always run at
	 * least once after work has been scheduled on any ring. Otherwise,
	 * we will ignore a hung ring if a second ring is kept busy.
	 */

	queue_delayed_work(e->hangcheck_wq, &e->hangcheck_work,
			   round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES));
B
Ben Gamari 已提交
3077 3078
}

3079
static void ibx_irq_reset(struct drm_device *dev)
P
Paulo Zanoni 已提交
3080 3081 3082 3083 3084 3085
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (HAS_PCH_NOP(dev))
		return;

3086
	GEN5_IRQ_RESET(SDE);
3087 3088 3089

	if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
		I915_WRITE(SERR_INT, 0xffffffff);
P
Paulo Zanoni 已提交
3090
}
3091

P
Paulo Zanoni 已提交
3092 3093 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103 3104 3105 3106 3107
/*
 * SDEIER is also touched by the interrupt handler to work around missed PCH
 * interrupts. Hence we can't update it after the interrupt handler is enabled -
 * instead we unconditionally enable all PCH interrupt sources here, but then
 * only unmask them as needed with SDEIMR.
 *
 * This function needs to be called before interrupts are enabled.
 */
static void ibx_irq_pre_postinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (HAS_PCH_NOP(dev))
		return;

	WARN_ON(I915_READ(SDEIER) != 0);
P
Paulo Zanoni 已提交
3108 3109 3110 3111
	I915_WRITE(SDEIER, 0xffffffff);
	POSTING_READ(SDEIER);
}

3112
static void gen5_gt_irq_reset(struct drm_device *dev)
3113 3114 3115
{
	struct drm_i915_private *dev_priv = dev->dev_private;

3116
	GEN5_IRQ_RESET(GT);
P
Paulo Zanoni 已提交
3117
	if (INTEL_INFO(dev)->gen >= 6)
3118
		GEN5_IRQ_RESET(GEN6_PM);
3119 3120
}

L
Linus Torvalds 已提交
3121 3122
/* drm_dma.h hooks
*/
P
Paulo Zanoni 已提交
3123
static void ironlake_irq_reset(struct drm_device *dev)
3124
{
3125
	struct drm_i915_private *dev_priv = dev->dev_private;
3126

3127
	I915_WRITE(HWSTAM, 0xffffffff);
3128

3129
	GEN5_IRQ_RESET(DE);
3130 3131
	if (IS_GEN7(dev))
		I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3132

3133
	gen5_gt_irq_reset(dev);
3134

3135
	ibx_irq_reset(dev);
3136
}
3137

3138 3139 3140 3141
static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
{
	enum pipe pipe;

3142
	i915_hotplug_interrupt_update(dev_priv, 0xFFFFFFFF, 0);
3143 3144 3145 3146 3147 3148 3149 3150
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));

	for_each_pipe(dev_priv, pipe)
		I915_WRITE(PIPESTAT(pipe), 0xffff);

	GEN5_IRQ_RESET(VLV_);
}

J
Jesse Barnes 已提交
3151 3152
static void valleyview_irq_preinstall(struct drm_device *dev)
{
3153
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
3154 3155 3156 3157 3158 3159 3160

	/* VLV magic */
	I915_WRITE(VLV_IMR, 0);
	I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
	I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
	I915_WRITE(RING_IMR(BLT_RING_BASE), 0);

3161
	gen5_gt_irq_reset(dev);
J
Jesse Barnes 已提交
3162

3163
	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
J
Jesse Barnes 已提交
3164

3165
	vlv_display_irq_reset(dev_priv);
J
Jesse Barnes 已提交
3166 3167
}

3168 3169 3170 3171 3172 3173 3174 3175
static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
{
	GEN8_IRQ_RESET_NDX(GT, 0);
	GEN8_IRQ_RESET_NDX(GT, 1);
	GEN8_IRQ_RESET_NDX(GT, 2);
	GEN8_IRQ_RESET_NDX(GT, 3);
}

P
Paulo Zanoni 已提交
3176
static void gen8_irq_reset(struct drm_device *dev)
3177 3178 3179 3180 3181 3182 3183
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int pipe;

	I915_WRITE(GEN8_MASTER_IRQ, 0);
	POSTING_READ(GEN8_MASTER_IRQ);

3184
	gen8_gt_irq_reset(dev_priv);
3185

3186
	for_each_pipe(dev_priv, pipe)
3187 3188
		if (intel_display_power_is_enabled(dev_priv,
						   POWER_DOMAIN_PIPE(pipe)))
3189
			GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3190

3191 3192 3193
	GEN5_IRQ_RESET(GEN8_DE_PORT_);
	GEN5_IRQ_RESET(GEN8_DE_MISC_);
	GEN5_IRQ_RESET(GEN8_PCU_);
3194

3195 3196
	if (HAS_PCH_SPLIT(dev))
		ibx_irq_reset(dev);
3197
}
3198

3199 3200
void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
				     unsigned int pipe_mask)
3201
{
3202
	uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3203

3204
	spin_lock_irq(&dev_priv->irq_lock);
3205 3206 3207 3208
	if (pipe_mask & 1 << PIPE_A)
		GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_A,
				  dev_priv->de_irq_mask[PIPE_A],
				  ~dev_priv->de_irq_mask[PIPE_A] | extra_ier);
3209 3210 3211 3212 3213 3214 3215 3216
	if (pipe_mask & 1 << PIPE_B)
		GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B,
				  dev_priv->de_irq_mask[PIPE_B],
				  ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
	if (pipe_mask & 1 << PIPE_C)
		GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C,
				  dev_priv->de_irq_mask[PIPE_C],
				  ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
3217
	spin_unlock_irq(&dev_priv->irq_lock);
3218 3219
}

3220 3221 3222 3223 3224 3225 3226
static void cherryview_irq_preinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	I915_WRITE(GEN8_MASTER_IRQ, 0);
	POSTING_READ(GEN8_MASTER_IRQ);

3227
	gen8_gt_irq_reset(dev_priv);
3228 3229 3230 3231 3232

	GEN5_IRQ_RESET(GEN8_PCU_);

	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);

3233
	vlv_display_irq_reset(dev_priv);
3234 3235
}

3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247 3248 3249
static u32 intel_hpd_enabled_irqs(struct drm_device *dev,
				  const u32 hpd[HPD_NUM_PINS])
{
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct intel_encoder *encoder;
	u32 enabled_irqs = 0;

	for_each_intel_encoder(dev, encoder)
		if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
			enabled_irqs |= hpd[encoder->hpd_pin];

	return enabled_irqs;
}

3250
static void ibx_hpd_irq_setup(struct drm_device *dev)
3251
{
3252
	struct drm_i915_private *dev_priv = dev->dev_private;
3253
	u32 hotplug_irqs, hotplug, enabled_irqs;
3254 3255

	if (HAS_PCH_IBX(dev)) {
3256
		hotplug_irqs = SDE_HOTPLUG_MASK;
3257
		enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ibx);
3258
	} else {
3259
		hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3260
		enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_cpt);
3261
	}
3262

3263
	ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3264 3265 3266

	/*
	 * Enable digital hotplug on the PCH, and configure the DP short pulse
3267 3268
	 * duration to 2ms (which is the minimum in the Display Port spec).
	 * The pulse duration bits are reserved on LPT+.
3269
	 */
3270 3271 3272 3273 3274
	hotplug = I915_READ(PCH_PORT_HOTPLUG);
	hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
	hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
	hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
	hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3275 3276 3277 3278 3279 3280
	/*
	 * When CPU and PCH are on the same package, port A
	 * HPD must be enabled in both north and south.
	 */
	if (HAS_PCH_LPT_LP(dev))
		hotplug |= PORTA_HOTPLUG_ENABLE;
3281
	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3282
}
X
Xiong Zhang 已提交
3283

3284 3285 3286 3287 3288 3289 3290 3291 3292 3293 3294 3295 3296
static void spt_hpd_irq_setup(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 hotplug_irqs, hotplug, enabled_irqs;

	hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
	enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_spt);

	ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);

	/* Enable digital hotplug on the PCH */
	hotplug = I915_READ(PCH_PORT_HOTPLUG);
	hotplug |= PORTD_HOTPLUG_ENABLE | PORTC_HOTPLUG_ENABLE |
3297
		PORTB_HOTPLUG_ENABLE | PORTA_HOTPLUG_ENABLE;
3298 3299 3300 3301 3302
	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);

	hotplug = I915_READ(PCH_PORT_HOTPLUG2);
	hotplug |= PORTE_HOTPLUG_ENABLE;
	I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3303 3304
}

3305 3306 3307 3308 3309
static void ilk_hpd_irq_setup(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 hotplug_irqs, hotplug, enabled_irqs;

3310 3311 3312 3313 3314 3315
	if (INTEL_INFO(dev)->gen >= 8) {
		hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
		enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_bdw);

		bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
	} else if (INTEL_INFO(dev)->gen >= 7) {
3316 3317
		hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
		enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ivb);
3318 3319

		ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3320 3321 3322
	} else {
		hotplug_irqs = DE_DP_A_HOTPLUG;
		enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ilk);
3323

3324 3325
		ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
	}
3326 3327 3328 3329

	/*
	 * Enable digital hotplug on the CPU, and configure the DP short pulse
	 * duration to 2ms (which is the minimum in the Display Port spec)
3330
	 * The pulse duration bits are reserved on HSW+.
3331 3332 3333 3334 3335 3336 3337 3338 3339
	 */
	hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
	hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
	hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | DIGITAL_PORTA_PULSE_DURATION_2ms;
	I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);

	ibx_hpd_irq_setup(dev);
}

3340 3341 3342
static void bxt_hpd_irq_setup(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
3343
	u32 hotplug_irqs, hotplug, enabled_irqs;
3344

3345 3346
	enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_bxt);
	hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
3347

3348
	bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3349

3350 3351 3352 3353
	hotplug = I915_READ(PCH_PORT_HOTPLUG);
	hotplug |= PORTC_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |
		PORTA_HOTPLUG_ENABLE;
	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3354 3355
}

P
Paulo Zanoni 已提交
3356 3357
static void ibx_irq_postinstall(struct drm_device *dev)
{
3358
	struct drm_i915_private *dev_priv = dev->dev_private;
3359
	u32 mask;
3360

D
Daniel Vetter 已提交
3361 3362 3363
	if (HAS_PCH_NOP(dev))
		return;

3364
	if (HAS_PCH_IBX(dev))
3365
		mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3366
	else
3367
		mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3368

3369
	gen5_assert_iir_is_zero(dev_priv, SDEIIR);
P
Paulo Zanoni 已提交
3370 3371 3372
	I915_WRITE(SDEIMR, ~mask);
}

3373 3374 3375 3376 3377 3378 3379 3380
static void gen5_gt_irq_postinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pm_irqs, gt_irqs;

	pm_irqs = gt_irqs = 0;

	dev_priv->gt_irq_mask = ~0;
3381
	if (HAS_L3_DPF(dev)) {
3382
		/* L3 parity interrupt is always unmasked. */
3383 3384
		dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
		gt_irqs |= GT_PARITY_ERROR(dev);
3385 3386 3387 3388 3389 3390 3391 3392 3393 3394
	}

	gt_irqs |= GT_RENDER_USER_INTERRUPT;
	if (IS_GEN5(dev)) {
		gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
			   ILK_BSD_USER_INTERRUPT;
	} else {
		gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
	}

P
Paulo Zanoni 已提交
3395
	GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3396 3397

	if (INTEL_INFO(dev)->gen >= 6) {
3398 3399 3400 3401
		/*
		 * RPS interrupts will get enabled/disabled on demand when RPS
		 * itself is enabled/disabled.
		 */
3402 3403 3404
		if (HAS_VEBOX(dev))
			pm_irqs |= PM_VEBOX_USER_INTERRUPT;

3405
		dev_priv->pm_irq_mask = 0xffffffff;
P
Paulo Zanoni 已提交
3406
		GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3407 3408 3409
	}
}

3410
static int ironlake_irq_postinstall(struct drm_device *dev)
3411
{
3412
	struct drm_i915_private *dev_priv = dev->dev_private;
3413 3414 3415 3416 3417 3418
	u32 display_mask, extra_mask;

	if (INTEL_INFO(dev)->gen >= 7) {
		display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
				DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
				DE_PLANEB_FLIP_DONE_IVB |
3419
				DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3420
		extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3421 3422
			      DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
			      DE_DP_A_HOTPLUG_IVB);
3423 3424 3425
	} else {
		display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
				DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3426 3427 3428
				DE_AUX_CHANNEL_A |
				DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
				DE_POISON);
3429 3430 3431
		extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
			      DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
			      DE_DP_A_HOTPLUG);
3432
	}
3433

3434
	dev_priv->irq_mask = ~display_mask;
3435

3436 3437
	I915_WRITE(HWSTAM, 0xeffe);

P
Paulo Zanoni 已提交
3438 3439
	ibx_irq_pre_postinstall(dev);

P
Paulo Zanoni 已提交
3440
	GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3441

3442
	gen5_gt_irq_postinstall(dev);
3443

P
Paulo Zanoni 已提交
3444
	ibx_irq_postinstall(dev);
3445

3446
	if (IS_IRONLAKE_M(dev)) {
3447 3448 3449
		/* Enable PCU event interrupts
		 *
		 * spinlocking not required here for correctness since interrupt
3450 3451
		 * setup is guaranteed to run in single-threaded context. But we
		 * need it to make the assert_spin_locked happy. */
3452
		spin_lock_irq(&dev_priv->irq_lock);
3453
		ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
3454
		spin_unlock_irq(&dev_priv->irq_lock);
3455 3456
	}

3457 3458 3459
	return 0;
}

3460 3461 3462 3463
static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
{
	u32 pipestat_mask;
	u32 iir_mask;
3464
	enum pipe pipe;
3465 3466 3467 3468

	pipestat_mask = PIPESTAT_INT_STATUS_MASK |
			PIPE_FIFO_UNDERRUN_STATUS;

3469 3470
	for_each_pipe(dev_priv, pipe)
		I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3471 3472 3473 3474 3475
	POSTING_READ(PIPESTAT(PIPE_A));

	pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
			PIPE_CRC_DONE_INTERRUPT_STATUS;

3476 3477 3478
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
	for_each_pipe(dev_priv, pipe)
		      i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3479 3480 3481 3482

	iir_mask = I915_DISPLAY_PORT_INTERRUPT |
		   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3483 3484
	if (IS_CHERRYVIEW(dev_priv))
		iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3485 3486 3487 3488 3489
	dev_priv->irq_mask &= ~iir_mask;

	I915_WRITE(VLV_IIR, iir_mask);
	I915_WRITE(VLV_IIR, iir_mask);
	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3490 3491
	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
	POSTING_READ(VLV_IMR);
3492 3493 3494 3495 3496 3497
}

static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
{
	u32 pipestat_mask;
	u32 iir_mask;
3498
	enum pipe pipe;
3499 3500 3501

	iir_mask = I915_DISPLAY_PORT_INTERRUPT |
		   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3502
		   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3503 3504
	if (IS_CHERRYVIEW(dev_priv))
		iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3505 3506 3507

	dev_priv->irq_mask |= iir_mask;
	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3508
	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3509 3510 3511 3512 3513 3514 3515
	I915_WRITE(VLV_IIR, iir_mask);
	I915_WRITE(VLV_IIR, iir_mask);
	POSTING_READ(VLV_IIR);

	pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
			PIPE_CRC_DONE_INTERRUPT_STATUS;

3516 3517 3518
	i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
	for_each_pipe(dev_priv, pipe)
		i915_disable_pipestat(dev_priv, pipe, pipestat_mask);
3519 3520 3521

	pipestat_mask = PIPESTAT_INT_STATUS_MASK |
			PIPE_FIFO_UNDERRUN_STATUS;
3522 3523 3524

	for_each_pipe(dev_priv, pipe)
		I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3525 3526 3527 3528 3529 3530 3531 3532 3533 3534 3535 3536
	POSTING_READ(PIPESTAT(PIPE_A));
}

void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
{
	assert_spin_locked(&dev_priv->irq_lock);

	if (dev_priv->display_irqs_enabled)
		return;

	dev_priv->display_irqs_enabled = true;

3537
	if (intel_irqs_enabled(dev_priv))
3538 3539 3540 3541 3542 3543 3544 3545 3546 3547 3548 3549
		valleyview_display_irqs_install(dev_priv);
}

void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
{
	assert_spin_locked(&dev_priv->irq_lock);

	if (!dev_priv->display_irqs_enabled)
		return;

	dev_priv->display_irqs_enabled = false;

3550
	if (intel_irqs_enabled(dev_priv))
3551 3552 3553
		valleyview_display_irqs_uninstall(dev_priv);
}

3554
static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
J
Jesse Barnes 已提交
3555
{
3556
	dev_priv->irq_mask = ~0;
J
Jesse Barnes 已提交
3557

3558
	i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3559 3560
	POSTING_READ(PORT_HOTPLUG_EN);

J
Jesse Barnes 已提交
3561
	I915_WRITE(VLV_IIR, 0xffffffff);
3562 3563 3564 3565
	I915_WRITE(VLV_IIR, 0xffffffff);
	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
	POSTING_READ(VLV_IMR);
J
Jesse Barnes 已提交
3566

3567 3568
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
3569
	spin_lock_irq(&dev_priv->irq_lock);
3570 3571
	if (dev_priv->display_irqs_enabled)
		valleyview_display_irqs_install(dev_priv);
3572
	spin_unlock_irq(&dev_priv->irq_lock);
3573 3574 3575 3576 3577 3578 3579
}

static int valleyview_irq_postinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	vlv_display_irq_postinstall(dev_priv);
J
Jesse Barnes 已提交
3580

3581
	gen5_gt_irq_postinstall(dev);
J
Jesse Barnes 已提交
3582 3583 3584 3585 3586 3587 3588 3589

	/* ack & enable invalid PTE error interrupts */
#if 0 /* FIXME: add support to irq handler for checking these bits */
	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
	I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
#endif

	I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3590 3591 3592 3593

	return 0;
}

3594 3595 3596 3597 3598
static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
{
	/* These are interrupts we'll toggle with the ring mask register */
	uint32_t gt_interrupts[] = {
		GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3599
			GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3600
			GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
3601 3602
			GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
			GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3603
		GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3604 3605 3606
			GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
			GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
			GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3607
		0,
3608 3609
		GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
			GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3610 3611
		};

3612
	dev_priv->pm_irq_mask = 0xffffffff;
3613 3614
	GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
	GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3615 3616 3617 3618 3619
	/*
	 * RPS interrupts will get enabled/disabled on demand when RPS itself
	 * is enabled/disabled.
	 */
	GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
3620
	GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3621 3622 3623 3624
}

static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
{
3625 3626
	uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
	uint32_t de_pipe_enables;
3627 3628 3629
	u32 de_port_masked = GEN8_AUX_CHANNEL_A;
	u32 de_port_enables;
	enum pipe pipe;
3630

3631
	if (INTEL_INFO(dev_priv)->gen >= 9) {
3632 3633
		de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
				  GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3634 3635
		de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
				  GEN9_AUX_CHANNEL_D;
S
Shashank Sharma 已提交
3636
		if (IS_BROXTON(dev_priv))
3637 3638
			de_port_masked |= BXT_DE_PORT_GMBUS;
	} else {
3639 3640
		de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
				  GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3641
	}
3642 3643 3644 3645

	de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
					   GEN8_PIPE_FIFO_UNDERRUN;

3646
	de_port_enables = de_port_masked;
3647 3648 3649
	if (IS_BROXTON(dev_priv))
		de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
	else if (IS_BROADWELL(dev_priv))
3650 3651
		de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;

3652 3653 3654
	dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
	dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
	dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3655

3656
	for_each_pipe(dev_priv, pipe)
3657
		if (intel_display_power_is_enabled(dev_priv,
3658 3659 3660 3661
				POWER_DOMAIN_PIPE(pipe)))
			GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
					  dev_priv->de_irq_mask[pipe],
					  de_pipe_enables);
3662

3663
	GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3664 3665 3666 3667 3668 3669
}

static int gen8_irq_postinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

3670 3671
	if (HAS_PCH_SPLIT(dev))
		ibx_irq_pre_postinstall(dev);
P
Paulo Zanoni 已提交
3672

3673 3674 3675
	gen8_gt_irq_postinstall(dev_priv);
	gen8_de_irq_postinstall(dev_priv);

3676 3677
	if (HAS_PCH_SPLIT(dev))
		ibx_irq_postinstall(dev);
3678 3679 3680 3681 3682 3683 3684

	I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
	POSTING_READ(GEN8_MASTER_IRQ);

	return 0;
}

3685 3686 3687 3688
static int cherryview_irq_postinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

3689
	vlv_display_irq_postinstall(dev_priv);
3690 3691 3692 3693 3694 3695 3696 3697 3698

	gen8_gt_irq_postinstall(dev_priv);

	I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
	POSTING_READ(GEN8_MASTER_IRQ);

	return 0;
}

3699 3700 3701 3702 3703 3704 3705
static void gen8_irq_uninstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (!dev_priv)
		return;

P
Paulo Zanoni 已提交
3706
	gen8_irq_reset(dev);
3707 3708
}

3709 3710 3711 3712 3713 3714 3715 3716 3717 3718 3719
static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv)
{
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
	spin_lock_irq(&dev_priv->irq_lock);
	if (dev_priv->display_irqs_enabled)
		valleyview_display_irqs_uninstall(dev_priv);
	spin_unlock_irq(&dev_priv->irq_lock);

	vlv_display_irq_reset(dev_priv);

3720
	dev_priv->irq_mask = ~0;
3721 3722
}

J
Jesse Barnes 已提交
3723 3724
static void valleyview_irq_uninstall(struct drm_device *dev)
{
3725
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
3726 3727 3728 3729

	if (!dev_priv)
		return;

3730 3731
	I915_WRITE(VLV_MASTER_IER, 0);

3732 3733
	gen5_gt_irq_reset(dev);

J
Jesse Barnes 已提交
3734
	I915_WRITE(HWSTAM, 0xffffffff);
3735

3736
	vlv_display_irq_uninstall(dev_priv);
J
Jesse Barnes 已提交
3737 3738
}

3739 3740 3741 3742 3743 3744 3745 3746 3747 3748
static void cherryview_irq_uninstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (!dev_priv)
		return;

	I915_WRITE(GEN8_MASTER_IRQ, 0);
	POSTING_READ(GEN8_MASTER_IRQ);

3749
	gen8_gt_irq_reset(dev_priv);
3750

3751
	GEN5_IRQ_RESET(GEN8_PCU_);
3752

3753
	vlv_display_irq_uninstall(dev_priv);
3754 3755
}

3756
static void ironlake_irq_uninstall(struct drm_device *dev)
3757
{
3758
	struct drm_i915_private *dev_priv = dev->dev_private;
3759 3760 3761 3762

	if (!dev_priv)
		return;

P
Paulo Zanoni 已提交
3763
	ironlake_irq_reset(dev);
3764 3765
}

3766
static void i8xx_irq_preinstall(struct drm_device * dev)
L
Linus Torvalds 已提交
3767
{
3768
	struct drm_i915_private *dev_priv = dev->dev_private;
3769
	int pipe;
3770

3771
	for_each_pipe(dev_priv, pipe)
3772
		I915_WRITE(PIPESTAT(pipe), 0);
3773 3774 3775
	I915_WRITE16(IMR, 0xffff);
	I915_WRITE16(IER, 0x0);
	POSTING_READ16(IER);
C
Chris Wilson 已提交
3776 3777 3778 3779
}

static int i8xx_irq_postinstall(struct drm_device *dev)
{
3780
	struct drm_i915_private *dev_priv = dev->dev_private;
C
Chris Wilson 已提交
3781 3782 3783 3784 3785 3786 3787 3788 3789

	I915_WRITE16(EMR,
		     ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));

	/* Unmask the interrupts that we always want on. */
	dev_priv->irq_mask =
		~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3790
		  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
C
Chris Wilson 已提交
3791 3792 3793 3794 3795 3796 3797 3798
	I915_WRITE16(IMR, dev_priv->irq_mask);

	I915_WRITE16(IER,
		     I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		     I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		     I915_USER_INTERRUPT);
	POSTING_READ16(IER);

3799 3800
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
3801
	spin_lock_irq(&dev_priv->irq_lock);
3802 3803
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3804
	spin_unlock_irq(&dev_priv->irq_lock);
3805

C
Chris Wilson 已提交
3806 3807 3808
	return 0;
}

3809 3810 3811 3812
/*
 * Returns true when a page flip has completed.
 */
static bool i8xx_handle_vblank(struct drm_device *dev,
3813
			       int plane, int pipe, u32 iir)
3814
{
3815
	struct drm_i915_private *dev_priv = dev->dev_private;
3816
	u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3817

3818
	if (!intel_pipe_handle_vblank(dev, pipe))
3819 3820 3821
		return false;

	if ((iir & flip_pending) == 0)
3822
		goto check_page_flip;
3823 3824 3825 3826 3827 3828 3829 3830

	/* We detect FlipDone by looking for the change in PendingFlip from '1'
	 * to '0' on the following vblank, i.e. IIR has the Pendingflip
	 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
	 * the flip is completed (no longer pending). Since this doesn't raise
	 * an interrupt per se, we watch for the change at vblank.
	 */
	if (I915_READ16(ISR) & flip_pending)
3831
		goto check_page_flip;
3832

3833
	intel_prepare_page_flip(dev, plane);
3834 3835
	intel_finish_page_flip(dev, pipe);
	return true;
3836 3837 3838 3839

check_page_flip:
	intel_check_page_flip(dev, pipe);
	return false;
3840 3841
}

3842
static irqreturn_t i8xx_irq_handler(int irq, void *arg)
C
Chris Wilson 已提交
3843
{
3844
	struct drm_device *dev = arg;
3845
	struct drm_i915_private *dev_priv = dev->dev_private;
C
Chris Wilson 已提交
3846 3847 3848 3849 3850 3851 3852
	u16 iir, new_iir;
	u32 pipe_stats[2];
	int pipe;
	u16 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;

3853 3854 3855
	if (!intel_irqs_enabled(dev_priv))
		return IRQ_NONE;

C
Chris Wilson 已提交
3856 3857 3858 3859 3860 3861 3862 3863 3864 3865
	iir = I915_READ16(IIR);
	if (iir == 0)
		return IRQ_NONE;

	while (iir & ~flip_mask) {
		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
3866
		spin_lock(&dev_priv->irq_lock);
C
Chris Wilson 已提交
3867
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3868
			DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
C
Chris Wilson 已提交
3869

3870
		for_each_pipe(dev_priv, pipe) {
3871
			i915_reg_t reg = PIPESTAT(pipe);
C
Chris Wilson 已提交
3872 3873 3874 3875 3876
			pipe_stats[pipe] = I915_READ(reg);

			/*
			 * Clear the PIPE*STAT regs before the IIR
			 */
3877
			if (pipe_stats[pipe] & 0x8000ffff)
C
Chris Wilson 已提交
3878 3879
				I915_WRITE(reg, pipe_stats[pipe]);
		}
3880
		spin_unlock(&dev_priv->irq_lock);
C
Chris Wilson 已提交
3881 3882 3883 3884 3885

		I915_WRITE16(IIR, iir & ~flip_mask);
		new_iir = I915_READ16(IIR); /* Flush posted writes */

		if (iir & I915_USER_INTERRUPT)
C
Chris Wilson 已提交
3886
			notify_ring(&dev_priv->ring[RCS]);
C
Chris Wilson 已提交
3887

3888
		for_each_pipe(dev_priv, pipe) {
3889
			int plane = pipe;
3890
			if (HAS_FBC(dev))
3891 3892
				plane = !plane;

3893
			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3894 3895
			    i8xx_handle_vblank(dev, plane, pipe, iir))
				flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
C
Chris Wilson 已提交
3896

3897
			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3898
				i9xx_pipe_crc_irq_handler(dev, pipe);
3899

3900 3901 3902
			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
				intel_cpu_fifo_underrun_irq_handler(dev_priv,
								    pipe);
3903
		}
C
Chris Wilson 已提交
3904 3905 3906 3907 3908 3909 3910 3911 3912

		iir = new_iir;
	}

	return IRQ_HANDLED;
}

static void i8xx_irq_uninstall(struct drm_device * dev)
{
3913
	struct drm_i915_private *dev_priv = dev->dev_private;
C
Chris Wilson 已提交
3914 3915
	int pipe;

3916
	for_each_pipe(dev_priv, pipe) {
C
Chris Wilson 已提交
3917 3918 3919 3920 3921 3922 3923 3924 3925
		/* Clear enable bits; then clear status bits */
		I915_WRITE(PIPESTAT(pipe), 0);
		I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
	}
	I915_WRITE16(IMR, 0xffff);
	I915_WRITE16(IER, 0x0);
	I915_WRITE16(IIR, I915_READ16(IIR));
}

3926 3927
static void i915_irq_preinstall(struct drm_device * dev)
{
3928
	struct drm_i915_private *dev_priv = dev->dev_private;
3929 3930 3931
	int pipe;

	if (I915_HAS_HOTPLUG(dev)) {
3932
		i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3933 3934 3935
		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	}

3936
	I915_WRITE16(HWSTAM, 0xeffe);
3937
	for_each_pipe(dev_priv, pipe)
3938 3939 3940 3941 3942 3943 3944 3945
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);
	POSTING_READ(IER);
}

static int i915_irq_postinstall(struct drm_device *dev)
{
3946
	struct drm_i915_private *dev_priv = dev->dev_private;
3947
	u32 enable_mask;
3948

3949 3950 3951 3952 3953 3954 3955 3956
	I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));

	/* Unmask the interrupts that we always want on. */
	dev_priv->irq_mask =
		~(I915_ASLE_INTERRUPT |
		  I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3957
		  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3958 3959 3960 3961 3962 3963 3964

	enable_mask =
		I915_ASLE_INTERRUPT |
		I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		I915_USER_INTERRUPT;

3965
	if (I915_HAS_HOTPLUG(dev)) {
3966
		i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3967 3968
		POSTING_READ(PORT_HOTPLUG_EN);

3969 3970 3971 3972 3973 3974 3975 3976 3977 3978
		/* Enable in IER... */
		enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
		/* and unmask in IMR */
		dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
	}

	I915_WRITE(IMR, dev_priv->irq_mask);
	I915_WRITE(IER, enable_mask);
	POSTING_READ(IER);

3979
	i915_enable_asle_pipestat(dev);
3980

3981 3982
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
3983
	spin_lock_irq(&dev_priv->irq_lock);
3984 3985
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3986
	spin_unlock_irq(&dev_priv->irq_lock);
3987

3988 3989 3990
	return 0;
}

3991 3992 3993 3994 3995 3996
/*
 * Returns true when a page flip has completed.
 */
static bool i915_handle_vblank(struct drm_device *dev,
			       int plane, int pipe, u32 iir)
{
3997
	struct drm_i915_private *dev_priv = dev->dev_private;
3998 3999
	u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);

4000
	if (!intel_pipe_handle_vblank(dev, pipe))
4001 4002 4003
		return false;

	if ((iir & flip_pending) == 0)
4004
		goto check_page_flip;
4005 4006 4007 4008 4009 4010 4011 4012

	/* We detect FlipDone by looking for the change in PendingFlip from '1'
	 * to '0' on the following vblank, i.e. IIR has the Pendingflip
	 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
	 * the flip is completed (no longer pending). Since this doesn't raise
	 * an interrupt per se, we watch for the change at vblank.
	 */
	if (I915_READ(ISR) & flip_pending)
4013
		goto check_page_flip;
4014

4015
	intel_prepare_page_flip(dev, plane);
4016 4017
	intel_finish_page_flip(dev, pipe);
	return true;
4018 4019 4020 4021

check_page_flip:
	intel_check_page_flip(dev, pipe);
	return false;
4022 4023
}

4024
static irqreturn_t i915_irq_handler(int irq, void *arg)
4025
{
4026
	struct drm_device *dev = arg;
4027
	struct drm_i915_private *dev_priv = dev->dev_private;
4028
	u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
4029 4030 4031 4032
	u32 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
	int pipe, ret = IRQ_NONE;
4033

4034 4035 4036
	if (!intel_irqs_enabled(dev_priv))
		return IRQ_NONE;

4037
	iir = I915_READ(IIR);
4038 4039
	do {
		bool irq_received = (iir & ~flip_mask) != 0;
4040
		bool blc_event = false;
4041 4042 4043 4044 4045 4046

		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
4047
		spin_lock(&dev_priv->irq_lock);
4048
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4049
			DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4050

4051
		for_each_pipe(dev_priv, pipe) {
4052
			i915_reg_t reg = PIPESTAT(pipe);
4053 4054
			pipe_stats[pipe] = I915_READ(reg);

4055
			/* Clear the PIPE*STAT regs before the IIR */
4056 4057
			if (pipe_stats[pipe] & 0x8000ffff) {
				I915_WRITE(reg, pipe_stats[pipe]);
4058
				irq_received = true;
4059 4060
			}
		}
4061
		spin_unlock(&dev_priv->irq_lock);
4062 4063 4064 4065 4066

		if (!irq_received)
			break;

		/* Consume port.  Then clear IIR or we'll miss events */
4067 4068 4069
		if (I915_HAS_HOTPLUG(dev) &&
		    iir & I915_DISPLAY_PORT_INTERRUPT)
			i9xx_hpd_irq_handler(dev);
4070

4071
		I915_WRITE(IIR, iir & ~flip_mask);
4072 4073 4074
		new_iir = I915_READ(IIR); /* Flush posted writes */

		if (iir & I915_USER_INTERRUPT)
C
Chris Wilson 已提交
4075
			notify_ring(&dev_priv->ring[RCS]);
4076

4077
		for_each_pipe(dev_priv, pipe) {
4078
			int plane = pipe;
4079
			if (HAS_FBC(dev))
4080
				plane = !plane;
4081

4082
			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4083 4084
			    i915_handle_vblank(dev, plane, pipe, iir))
				flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4085 4086 4087

			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
				blc_event = true;
4088 4089

			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4090
				i9xx_pipe_crc_irq_handler(dev, pipe);
4091

4092 4093 4094
			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
				intel_cpu_fifo_underrun_irq_handler(dev_priv,
								    pipe);
4095 4096 4097 4098 4099 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 4110 4111 4112 4113 4114
		}

		if (blc_event || (iir & I915_ASLE_INTERRUPT))
			intel_opregion_asle_intr(dev);

		/* With MSI, interrupts are only generated when iir
		 * transitions from zero to nonzero.  If another bit got
		 * set while we were handling the existing iir bits, then
		 * we would never get another interrupt.
		 *
		 * This is fine on non-MSI as well, as if we hit this path
		 * we avoid exiting the interrupt handler only to generate
		 * another one.
		 *
		 * Note that for MSI this could cause a stray interrupt report
		 * if an interrupt landed in the time between writing IIR and
		 * the posting read.  This should be rare enough to never
		 * trigger the 99% of 100,000 interrupts test for disabling
		 * stray interrupts.
		 */
4115
		ret = IRQ_HANDLED;
4116
		iir = new_iir;
4117
	} while (iir & ~flip_mask);
4118 4119 4120 4121 4122 4123

	return ret;
}

static void i915_irq_uninstall(struct drm_device * dev)
{
4124
	struct drm_i915_private *dev_priv = dev->dev_private;
4125 4126 4127
	int pipe;

	if (I915_HAS_HOTPLUG(dev)) {
4128
		i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4129 4130 4131
		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	}

4132
	I915_WRITE16(HWSTAM, 0xffff);
4133
	for_each_pipe(dev_priv, pipe) {
4134
		/* Clear enable bits; then clear status bits */
4135
		I915_WRITE(PIPESTAT(pipe), 0);
4136 4137
		I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
	}
4138 4139 4140 4141 4142 4143 4144 4145
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);

	I915_WRITE(IIR, I915_READ(IIR));
}

static void i965_irq_preinstall(struct drm_device * dev)
{
4146
	struct drm_i915_private *dev_priv = dev->dev_private;
4147 4148
	int pipe;

4149
	i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4150
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4151 4152

	I915_WRITE(HWSTAM, 0xeffe);
4153
	for_each_pipe(dev_priv, pipe)
4154 4155 4156 4157 4158 4159 4160 4161
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);
	POSTING_READ(IER);
}

static int i965_irq_postinstall(struct drm_device *dev)
{
4162
	struct drm_i915_private *dev_priv = dev->dev_private;
4163
	u32 enable_mask;
4164 4165 4166
	u32 error_mask;

	/* Unmask the interrupts that we always want on. */
4167
	dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4168
			       I915_DISPLAY_PORT_INTERRUPT |
4169 4170 4171 4172 4173 4174 4175
			       I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
			       I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
			       I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
			       I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
			       I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);

	enable_mask = ~dev_priv->irq_mask;
4176 4177
	enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
			 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4178 4179 4180 4181
	enable_mask |= I915_USER_INTERRUPT;

	if (IS_G4X(dev))
		enable_mask |= I915_BSD_USER_INTERRUPT;
4182

4183 4184
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
4185
	spin_lock_irq(&dev_priv->irq_lock);
4186 4187 4188
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4189
	spin_unlock_irq(&dev_priv->irq_lock);
4190 4191 4192 4193 4194 4195 4196 4197 4198 4199 4200 4201 4202 4203 4204 4205 4206 4207 4208 4209

	/*
	 * Enable some error detection, note the instruction error mask
	 * bit is reserved, so we leave it masked.
	 */
	if (IS_G4X(dev)) {
		error_mask = ~(GM45_ERROR_PAGE_TABLE |
			       GM45_ERROR_MEM_PRIV |
			       GM45_ERROR_CP_PRIV |
			       I915_ERROR_MEMORY_REFRESH);
	} else {
		error_mask = ~(I915_ERROR_PAGE_TABLE |
			       I915_ERROR_MEMORY_REFRESH);
	}
	I915_WRITE(EMR, error_mask);

	I915_WRITE(IMR, dev_priv->irq_mask);
	I915_WRITE(IER, enable_mask);
	POSTING_READ(IER);

4210
	i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4211 4212
	POSTING_READ(PORT_HOTPLUG_EN);

4213
	i915_enable_asle_pipestat(dev);
4214 4215 4216 4217

	return 0;
}

4218
static void i915_hpd_irq_setup(struct drm_device *dev)
4219
{
4220
	struct drm_i915_private *dev_priv = dev->dev_private;
4221 4222
	u32 hotplug_en;

4223 4224
	assert_spin_locked(&dev_priv->irq_lock);

4225 4226
	/* Note HDMI and DP share hotplug bits */
	/* enable bits are the same for all generations */
4227
	hotplug_en = intel_hpd_enabled_irqs(dev, hpd_mask_i915);
4228 4229 4230 4231 4232 4233 4234 4235 4236
	/* Programming the CRT detection parameters tends
	   to generate a spurious hotplug event about three
	   seconds later.  So just do it once.
	*/
	if (IS_G4X(dev))
		hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
	hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;

	/* Ignore TV since it's buggy */
4237
	i915_hotplug_interrupt_update_locked(dev_priv,
4238 4239 4240 4241
					     HOTPLUG_INT_EN_MASK |
					     CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
					     CRT_HOTPLUG_ACTIVATION_PERIOD_64,
					     hotplug_en);
4242 4243
}

4244
static irqreturn_t i965_irq_handler(int irq, void *arg)
4245
{
4246
	struct drm_device *dev = arg;
4247
	struct drm_i915_private *dev_priv = dev->dev_private;
4248 4249 4250
	u32 iir, new_iir;
	u32 pipe_stats[I915_MAX_PIPES];
	int ret = IRQ_NONE, pipe;
4251 4252 4253
	u32 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4254

4255 4256 4257
	if (!intel_irqs_enabled(dev_priv))
		return IRQ_NONE;

4258 4259 4260
	iir = I915_READ(IIR);

	for (;;) {
4261
		bool irq_received = (iir & ~flip_mask) != 0;
4262 4263
		bool blc_event = false;

4264 4265 4266 4267 4268
		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
4269
		spin_lock(&dev_priv->irq_lock);
4270
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4271
			DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4272

4273
		for_each_pipe(dev_priv, pipe) {
4274
			i915_reg_t reg = PIPESTAT(pipe);
4275 4276 4277 4278 4279 4280 4281
			pipe_stats[pipe] = I915_READ(reg);

			/*
			 * Clear the PIPE*STAT regs before the IIR
			 */
			if (pipe_stats[pipe] & 0x8000ffff) {
				I915_WRITE(reg, pipe_stats[pipe]);
4282
				irq_received = true;
4283 4284
			}
		}
4285
		spin_unlock(&dev_priv->irq_lock);
4286 4287 4288 4289 4290 4291 4292

		if (!irq_received)
			break;

		ret = IRQ_HANDLED;

		/* Consume port.  Then clear IIR or we'll miss events */
4293 4294
		if (iir & I915_DISPLAY_PORT_INTERRUPT)
			i9xx_hpd_irq_handler(dev);
4295

4296
		I915_WRITE(IIR, iir & ~flip_mask);
4297 4298 4299
		new_iir = I915_READ(IIR); /* Flush posted writes */

		if (iir & I915_USER_INTERRUPT)
C
Chris Wilson 已提交
4300
			notify_ring(&dev_priv->ring[RCS]);
4301
		if (iir & I915_BSD_USER_INTERRUPT)
C
Chris Wilson 已提交
4302
			notify_ring(&dev_priv->ring[VCS]);
4303

4304
		for_each_pipe(dev_priv, pipe) {
4305
			if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4306 4307
			    i915_handle_vblank(dev, pipe, pipe, iir))
				flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4308 4309 4310

			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
				blc_event = true;
4311 4312

			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4313
				i9xx_pipe_crc_irq_handler(dev, pipe);
4314

4315 4316
			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
				intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4317
		}
4318 4319 4320 4321

		if (blc_event || (iir & I915_ASLE_INTERRUPT))
			intel_opregion_asle_intr(dev);

4322 4323 4324
		if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
			gmbus_irq_handler(dev);

4325 4326 4327 4328 4329 4330 4331 4332 4333 4334 4335 4336 4337 4338 4339 4340 4341 4342 4343 4344 4345 4346 4347
		/* With MSI, interrupts are only generated when iir
		 * transitions from zero to nonzero.  If another bit got
		 * set while we were handling the existing iir bits, then
		 * we would never get another interrupt.
		 *
		 * This is fine on non-MSI as well, as if we hit this path
		 * we avoid exiting the interrupt handler only to generate
		 * another one.
		 *
		 * Note that for MSI this could cause a stray interrupt report
		 * if an interrupt landed in the time between writing IIR and
		 * the posting read.  This should be rare enough to never
		 * trigger the 99% of 100,000 interrupts test for disabling
		 * stray interrupts.
		 */
		iir = new_iir;
	}

	return ret;
}

static void i965_irq_uninstall(struct drm_device * dev)
{
4348
	struct drm_i915_private *dev_priv = dev->dev_private;
4349 4350 4351 4352 4353
	int pipe;

	if (!dev_priv)
		return;

4354
	i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4355
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4356 4357

	I915_WRITE(HWSTAM, 0xffffffff);
4358
	for_each_pipe(dev_priv, pipe)
4359 4360 4361 4362
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);

4363
	for_each_pipe(dev_priv, pipe)
4364 4365 4366 4367 4368
		I915_WRITE(PIPESTAT(pipe),
			   I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
	I915_WRITE(IIR, I915_READ(IIR));
}

4369 4370 4371 4372 4373 4374 4375
/**
 * intel_irq_init - initializes irq support
 * @dev_priv: i915 device instance
 *
 * This function initializes all the irq support including work items, timers
 * and all the vtables. It does not setup the interrupt itself though.
 */
4376
void intel_irq_init(struct drm_i915_private *dev_priv)
4377
{
4378
	struct drm_device *dev = dev_priv->dev;
4379

4380 4381
	intel_hpd_init_work(dev_priv);

4382
	INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4383
	INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4384

4385
	/* Let's track the enabled rps events */
4386
	if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
4387
		/* WaGsvRC0ResidencyMethod:vlv */
4388
		dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
4389 4390
	else
		dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4391

4392 4393
	INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
			  i915_hangcheck_elapsed);
4394

4395
	pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4396

4397
	if (IS_GEN2(dev_priv)) {
4398 4399
		dev->max_vblank_count = 0;
		dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4400
	} else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4401
		dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4402
		dev->driver->get_vblank_counter = g4x_get_vblank_counter;
4403 4404 4405
	} else {
		dev->driver->get_vblank_counter = i915_get_vblank_counter;
		dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4406 4407
	}

4408 4409 4410 4411 4412
	/*
	 * Opt out of the vblank disable timer on everything except gen2.
	 * Gen2 doesn't have a hardware frame counter and so depends on
	 * vblank interrupts to produce sane vblank seuquence numbers.
	 */
4413
	if (!IS_GEN2(dev_priv))
4414 4415
		dev->vblank_disable_immediate = true;

4416 4417
	dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
	dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4418

4419
	if (IS_CHERRYVIEW(dev_priv)) {
4420 4421 4422 4423 4424 4425 4426
		dev->driver->irq_handler = cherryview_irq_handler;
		dev->driver->irq_preinstall = cherryview_irq_preinstall;
		dev->driver->irq_postinstall = cherryview_irq_postinstall;
		dev->driver->irq_uninstall = cherryview_irq_uninstall;
		dev->driver->enable_vblank = valleyview_enable_vblank;
		dev->driver->disable_vblank = valleyview_disable_vblank;
		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4427
	} else if (IS_VALLEYVIEW(dev_priv)) {
J
Jesse Barnes 已提交
4428 4429 4430 4431 4432 4433
		dev->driver->irq_handler = valleyview_irq_handler;
		dev->driver->irq_preinstall = valleyview_irq_preinstall;
		dev->driver->irq_postinstall = valleyview_irq_postinstall;
		dev->driver->irq_uninstall = valleyview_irq_uninstall;
		dev->driver->enable_vblank = valleyview_enable_vblank;
		dev->driver->disable_vblank = valleyview_disable_vblank;
4434
		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4435
	} else if (INTEL_INFO(dev_priv)->gen >= 8) {
4436
		dev->driver->irq_handler = gen8_irq_handler;
4437
		dev->driver->irq_preinstall = gen8_irq_reset;
4438 4439 4440 4441
		dev->driver->irq_postinstall = gen8_irq_postinstall;
		dev->driver->irq_uninstall = gen8_irq_uninstall;
		dev->driver->enable_vblank = gen8_enable_vblank;
		dev->driver->disable_vblank = gen8_disable_vblank;
4442
		if (IS_BROXTON(dev))
4443
			dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4444 4445 4446
		else if (HAS_PCH_SPT(dev))
			dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
		else
4447
			dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4448 4449
	} else if (HAS_PCH_SPLIT(dev)) {
		dev->driver->irq_handler = ironlake_irq_handler;
4450
		dev->driver->irq_preinstall = ironlake_irq_reset;
4451 4452 4453 4454
		dev->driver->irq_postinstall = ironlake_irq_postinstall;
		dev->driver->irq_uninstall = ironlake_irq_uninstall;
		dev->driver->enable_vblank = ironlake_enable_vblank;
		dev->driver->disable_vblank = ironlake_disable_vblank;
4455
		dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4456
	} else {
4457
		if (INTEL_INFO(dev_priv)->gen == 2) {
C
Chris Wilson 已提交
4458 4459 4460 4461
			dev->driver->irq_preinstall = i8xx_irq_preinstall;
			dev->driver->irq_postinstall = i8xx_irq_postinstall;
			dev->driver->irq_handler = i8xx_irq_handler;
			dev->driver->irq_uninstall = i8xx_irq_uninstall;
4462
		} else if (INTEL_INFO(dev_priv)->gen == 3) {
4463 4464 4465 4466
			dev->driver->irq_preinstall = i915_irq_preinstall;
			dev->driver->irq_postinstall = i915_irq_postinstall;
			dev->driver->irq_uninstall = i915_irq_uninstall;
			dev->driver->irq_handler = i915_irq_handler;
C
Chris Wilson 已提交
4467
		} else {
4468 4469 4470 4471
			dev->driver->irq_preinstall = i965_irq_preinstall;
			dev->driver->irq_postinstall = i965_irq_postinstall;
			dev->driver->irq_uninstall = i965_irq_uninstall;
			dev->driver->irq_handler = i965_irq_handler;
C
Chris Wilson 已提交
4472
		}
4473 4474
		if (I915_HAS_HOTPLUG(dev_priv))
			dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4475 4476 4477 4478
		dev->driver->enable_vblank = i915_enable_vblank;
		dev->driver->disable_vblank = i915_disable_vblank;
	}
}
4479

4480 4481 4482 4483 4484 4485 4486 4487 4488 4489 4490
/**
 * intel_irq_install - enables the hardware interrupt
 * @dev_priv: i915 device instance
 *
 * This function enables the hardware interrupt handling, but leaves the hotplug
 * handling still disabled. It is called after intel_irq_init().
 *
 * In the driver load and resume code we need working interrupts in a few places
 * but don't want to deal with the hassle of concurrent probe and hotplug
 * workers. Hence the split into this two-stage approach.
 */
4491 4492 4493 4494 4495 4496 4497 4498 4499 4500 4501 4502
int intel_irq_install(struct drm_i915_private *dev_priv)
{
	/*
	 * We enable some interrupt sources in our postinstall hooks, so mark
	 * interrupts as enabled _before_ actually enabling them to avoid
	 * special cases in our ordering checks.
	 */
	dev_priv->pm.irqs_enabled = true;

	return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
}

4503 4504 4505 4506 4507 4508 4509
/**
 * intel_irq_uninstall - finilizes all irq handling
 * @dev_priv: i915 device instance
 *
 * This stops interrupt and hotplug handling and unregisters and frees all
 * resources acquired in the init functions.
 */
4510 4511 4512 4513 4514 4515 4516
void intel_irq_uninstall(struct drm_i915_private *dev_priv)
{
	drm_irq_uninstall(dev_priv->dev);
	intel_hpd_cancel_work(dev_priv);
	dev_priv->pm.irqs_enabled = false;
}

4517 4518 4519 4520 4521 4522 4523
/**
 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
 * @dev_priv: i915 device instance
 *
 * This function is used to disable interrupts at runtime, both in the runtime
 * pm and the system suspend/resume code.
 */
4524
void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4525
{
4526
	dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
4527
	dev_priv->pm.irqs_enabled = false;
4528
	synchronize_irq(dev_priv->dev->irq);
4529 4530
}

4531 4532 4533 4534 4535 4536 4537
/**
 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
 * @dev_priv: i915 device instance
 *
 * This function is used to enable interrupts at runtime, both in the runtime
 * pm and the system suspend/resume code.
 */
4538
void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4539
{
4540
	dev_priv->pm.irqs_enabled = true;
4541 4542
	dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
	dev_priv->dev->driver->irq_postinstall(dev_priv->dev);
4543
}