i915_irq.c 102.8 KB
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Dave Airlie 已提交
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/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
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Linus Torvalds 已提交
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 */
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/*
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

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#include <linux/sysrq.h>
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#include <linux/slab.h>
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#include <drm/drmP.h>
#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#include "i915_trace.h"
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#include "intel_drv.h"
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static const u32 hpd_ibx[] = {
	[HPD_CRT] = SDE_CRT_HOTPLUG,
	[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
	[HPD_PORT_B] = SDE_PORTB_HOTPLUG,
	[HPD_PORT_C] = SDE_PORTC_HOTPLUG,
	[HPD_PORT_D] = SDE_PORTD_HOTPLUG
};

static const u32 hpd_cpt[] = {
	[HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
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	[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
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	[HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
	[HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
	[HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
};

static const u32 hpd_mask_i915[] = {
	[HPD_CRT] = CRT_HOTPLUG_INT_EN,
	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
	[HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
	[HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
	[HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
};

static const u32 hpd_status_gen4[] = {
	[HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
	[HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
	[HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
	[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
};

static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
	[HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
	[HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
	[HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
	[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
};

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/* For display hotplug interrupt */
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static void
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ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
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{
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	assert_spin_locked(&dev_priv->irq_lock);

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	if ((dev_priv->irq_mask & mask) != 0) {
		dev_priv->irq_mask &= ~mask;
		I915_WRITE(DEIMR, dev_priv->irq_mask);
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		POSTING_READ(DEIMR);
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	}
}

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static void
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ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
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{
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	assert_spin_locked(&dev_priv->irq_lock);

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	if ((dev_priv->irq_mask & mask) != mask) {
		dev_priv->irq_mask |= mask;
		I915_WRITE(DEIMR, dev_priv->irq_mask);
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		POSTING_READ(DEIMR);
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	}
}

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static bool ivb_can_enable_err_int(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *crtc;
	enum pipe pipe;

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	assert_spin_locked(&dev_priv->irq_lock);

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	for_each_pipe(pipe) {
		crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);

		if (crtc->cpu_fifo_underrun_disabled)
			return false;
	}

	return true;
}

static bool cpt_can_enable_serr_int(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum pipe pipe;
	struct intel_crtc *crtc;

	for_each_pipe(pipe) {
		crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);

		if (crtc->pch_fifo_underrun_disabled)
			return false;
	}

	return true;
}

static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
						 enum pipe pipe, bool enable)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
					  DE_PIPEB_FIFO_UNDERRUN;

	if (enable)
		ironlake_enable_display_irq(dev_priv, bit);
	else
		ironlake_disable_display_irq(dev_priv, bit);
}

static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
						  bool enable)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (enable) {
		if (!ivb_can_enable_err_int(dev))
			return;

		I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN_A |
					 ERR_INT_FIFO_UNDERRUN_B |
					 ERR_INT_FIFO_UNDERRUN_C);

		ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
	} else {
		ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
	}
}

static void ibx_set_fifo_underrun_reporting(struct intel_crtc *crtc,
					    bool enable)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t bit = (crtc->pipe == PIPE_A) ? SDE_TRANSA_FIFO_UNDER :
						SDE_TRANSB_FIFO_UNDER;

	if (enable)
		I915_WRITE(SDEIMR, I915_READ(SDEIMR) & ~bit);
	else
		I915_WRITE(SDEIMR, I915_READ(SDEIMR) | bit);

	POSTING_READ(SDEIMR);
}

static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
					    enum transcoder pch_transcoder,
					    bool enable)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (enable) {
		if (!cpt_can_enable_serr_int(dev))
			return;

		I915_WRITE(SERR_INT, SERR_INT_TRANS_A_FIFO_UNDERRUN |
				     SERR_INT_TRANS_B_FIFO_UNDERRUN |
				     SERR_INT_TRANS_C_FIFO_UNDERRUN);

		I915_WRITE(SDEIMR, I915_READ(SDEIMR) & ~SDE_ERROR_CPT);
	} else {
		I915_WRITE(SDEIMR, I915_READ(SDEIMR) | SDE_ERROR_CPT);
	}

	POSTING_READ(SDEIMR);
}

/**
 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
 * @dev: drm device
 * @pipe: pipe
 * @enable: true if we want to report FIFO underrun errors, false otherwise
 *
 * This function makes us disable or enable CPU fifo underruns for a specific
 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
 * reporting for one pipe may also disable all the other CPU error interruts for
 * the other pipes, due to the fact that there's just one interrupt mask/enable
 * bit for all the pipes.
 *
 * Returns the previous state of underrun reporting.
 */
bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
					   enum pipe pipe, bool enable)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	unsigned long flags;
	bool ret;

	spin_lock_irqsave(&dev_priv->irq_lock, flags);

	ret = !intel_crtc->cpu_fifo_underrun_disabled;

	if (enable == ret)
		goto done;

	intel_crtc->cpu_fifo_underrun_disabled = !enable;

	if (IS_GEN5(dev) || IS_GEN6(dev))
		ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
	else if (IS_GEN7(dev))
		ivybridge_set_fifo_underrun_reporting(dev, enable);

done:
	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
	return ret;
}

/**
 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
 * @dev: drm device
 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
 * @enable: true if we want to report FIFO underrun errors, false otherwise
 *
 * This function makes us disable or enable PCH fifo underruns for a specific
 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
 * underrun reporting for one transcoder may also disable all the other PCH
 * error interruts for the other transcoders, due to the fact that there's just
 * one interrupt mask/enable bit for all the transcoders.
 *
 * Returns the previous state of underrun reporting.
 */
bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
					   enum transcoder pch_transcoder,
					   bool enable)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum pipe p;
	struct drm_crtc *crtc;
	struct intel_crtc *intel_crtc;
	unsigned long flags;
	bool ret;

	if (HAS_PCH_LPT(dev)) {
		crtc = NULL;
		for_each_pipe(p) {
			struct drm_crtc *c = dev_priv->pipe_to_crtc_mapping[p];
			if (intel_pipe_has_type(c, INTEL_OUTPUT_ANALOG)) {
				crtc = c;
				break;
			}
		}
		if (!crtc) {
			DRM_ERROR("PCH FIFO underrun, but no CRTC using the PCH found\n");
			return false;
		}
	} else {
		crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
	}
	intel_crtc = to_intel_crtc(crtc);

	spin_lock_irqsave(&dev_priv->irq_lock, flags);

	ret = !intel_crtc->pch_fifo_underrun_disabled;

	if (enable == ret)
		goto done;

	intel_crtc->pch_fifo_underrun_disabled = !enable;

	if (HAS_PCH_IBX(dev))
		ibx_set_fifo_underrun_reporting(intel_crtc, enable);
	else
		cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);

done:
	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
	return ret;
}


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void
i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
{
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	u32 reg = PIPESTAT(pipe);
	u32 pipestat = I915_READ(reg) & 0x7fff0000;
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	if ((pipestat & mask) == mask)
		return;

	/* Enable the interrupt, clear any pending status */
	pipestat |= mask | (mask >> 16);
	I915_WRITE(reg, pipestat);
	POSTING_READ(reg);
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}

void
i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
{
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	u32 reg = PIPESTAT(pipe);
	u32 pipestat = I915_READ(reg) & 0x7fff0000;
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	if ((pipestat & mask) == 0)
		return;

	pipestat &= ~mask;
	I915_WRITE(reg, pipestat);
	POSTING_READ(reg);
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}

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/**
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 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
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 */
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static void i915_enable_asle_pipestat(struct drm_device *dev)
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{
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	drm_i915_private_t *dev_priv = dev->dev_private;
	unsigned long irqflags;

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	if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
		return;

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	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
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	i915_enable_pipestat(dev_priv, 1, PIPE_LEGACY_BLC_EVENT_ENABLE);
	if (INTEL_INFO(dev)->gen >= 4)
		i915_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE);
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	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
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}

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/**
 * i915_pipe_enabled - check if a pipe is enabled
 * @dev: DRM device
 * @pipe: pipe to check
 *
 * Reading certain registers when the pipe is disabled can hang the chip.
 * Use this routine to make sure the PLL is running and the pipe is active
 * before reading such registers if unsure.
 */
static int
i915_pipe_enabled(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
		/* Locking is horribly broken here, but whatever. */
		struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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		return intel_crtc->active;
	} else {
		return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
	}
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}

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/* Called from drm generic code, passed a 'crtc', which
 * we use as a pipe index
 */
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static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
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{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long high_frame;
	unsigned long low_frame;
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	u32 high1, high2, low;
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	if (!i915_pipe_enabled(dev, pipe)) {
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		DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
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				"pipe %c\n", pipe_name(pipe));
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		return 0;
	}

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	high_frame = PIPEFRAME(pipe);
	low_frame = PIPEFRAMEPIXEL(pipe);
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	/*
	 * High & low register fields aren't synchronized, so make sure
	 * we get a low value that's stable across two reads of the high
	 * register.
	 */
	do {
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		high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
		low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
		high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
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	} while (high1 != high2);

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	high1 >>= PIPE_FRAME_HIGH_SHIFT;
	low >>= PIPE_FRAME_LOW_SHIFT;
	return (high1 << 8) | low;
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}

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static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
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{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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	int reg = PIPE_FRMCOUNT_GM45(pipe);
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	if (!i915_pipe_enabled(dev, pipe)) {
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		DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
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				 "pipe %c\n", pipe_name(pipe));
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		return 0;
	}

	return I915_READ(reg);
}

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static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
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			     int *vpos, int *hpos)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u32 vbl = 0, position = 0;
	int vbl_start, vbl_end, htotal, vtotal;
	bool in_vbl = true;
	int ret = 0;
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	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
								      pipe);
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	if (!i915_pipe_enabled(dev, pipe)) {
		DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
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				 "pipe %c\n", pipe_name(pipe));
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		return 0;
	}

	/* Get vtotal. */
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	vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
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	if (INTEL_INFO(dev)->gen >= 4) {
		/* No obvious pixelcount register. Only query vertical
		 * scanout position from Display scan line register.
		 */
		position = I915_READ(PIPEDSL(pipe));

		/* Decode into vertical scanout position. Don't have
		 * horizontal scanout position.
		 */
		*vpos = position & 0x1fff;
		*hpos = 0;
	} else {
		/* Have access to pixelcount since start of frame.
		 * We can split this into vertical and horizontal
		 * scanout position.
		 */
		position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;

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		htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
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		*vpos = position / htotal;
		*hpos = position - (*vpos * htotal);
	}

	/* Query vblank area. */
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	vbl = I915_READ(VBLANK(cpu_transcoder));
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	/* Test position against vblank region. */
	vbl_start = vbl & 0x1fff;
	vbl_end = (vbl >> 16) & 0x1fff;

	if ((*vpos < vbl_start) || (*vpos > vbl_end))
		in_vbl = false;

	/* Inside "upper part" of vblank area? Apply corrective offset: */
	if (in_vbl && (*vpos >= vbl_start))
		*vpos = *vpos - vtotal;

	/* Readouts valid? */
	if (vbl > 0)
		ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;

	/* In vblank? */
	if (in_vbl)
		ret |= DRM_SCANOUTPOS_INVBL;

	return ret;
}

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static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
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			      int *max_error,
			      struct timeval *vblank_time,
			      unsigned flags)
{
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	struct drm_crtc *crtc;
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	if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
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		DRM_ERROR("Invalid crtc %d\n", pipe);
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		return -EINVAL;
	}

	/* Get drm_crtc to timestamp: */
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	crtc = intel_get_crtc_for_pipe(dev, pipe);
	if (crtc == NULL) {
		DRM_ERROR("Invalid crtc %d\n", pipe);
		return -EINVAL;
	}

	if (!crtc->enabled) {
		DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
		return -EBUSY;
	}
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	/* Helper routine in DRM core does all the work: */
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	return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
						     vblank_time, flags,
						     crtc);
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}

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static int intel_hpd_irq_event(struct drm_device *dev, struct drm_connector *connector)
{
	enum drm_connector_status old_status;

	WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
	old_status = connector->status;

	connector->status = connector->funcs->detect(connector, false);
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n",
		      connector->base.id,
		      drm_get_connector_name(connector),
		      old_status, connector->status);
	return (old_status != connector->status);
}

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/*
 * Handle hotplug events outside the interrupt handler proper.
 */
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#define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)

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static void i915_hotplug_work_func(struct work_struct *work)
{
	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
						    hotplug_work);
	struct drm_device *dev = dev_priv->dev;
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	struct drm_mode_config *mode_config = &dev->mode_config;
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	struct intel_connector *intel_connector;
	struct intel_encoder *intel_encoder;
	struct drm_connector *connector;
	unsigned long irqflags;
	bool hpd_disabled = false;
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	bool changed = false;
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	u32 hpd_event_bits;
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	/* HPD irq before everything is fully set up. */
	if (!dev_priv->enable_hotplug_processing)
		return;

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	mutex_lock(&mode_config->mutex);
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	DRM_DEBUG_KMS("running encoder hotplug functions\n");

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	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
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	hpd_event_bits = dev_priv->hpd_event_bits;
	dev_priv->hpd_event_bits = 0;
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	list_for_each_entry(connector, &mode_config->connector_list, head) {
		intel_connector = to_intel_connector(connector);
		intel_encoder = intel_connector->encoder;
		if (intel_encoder->hpd_pin > HPD_NONE &&
		    dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
		    connector->polled == DRM_CONNECTOR_POLL_HPD) {
			DRM_INFO("HPD interrupt storm detected on connector %s: "
				 "switching from hotplug detection to polling\n",
				drm_get_connector_name(connector));
			dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
			connector->polled = DRM_CONNECTOR_POLL_CONNECT
				| DRM_CONNECTOR_POLL_DISCONNECT;
			hpd_disabled = true;
		}
596 597 598 599
		if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
			DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
				      drm_get_connector_name(connector), intel_encoder->hpd_pin);
		}
600 601 602 603
	}
	 /* if there were no outputs to poll, poll was disabled,
	  * therefore make sure it's enabled when disabling HPD on
	  * some connectors */
604
	if (hpd_disabled) {
605
		drm_kms_helper_poll_enable(dev);
606 607 608
		mod_timer(&dev_priv->hotplug_reenable_timer,
			  jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
	}
609 610 611

	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

612 613 614 615 616 617 618 619 620 621
	list_for_each_entry(connector, &mode_config->connector_list, head) {
		intel_connector = to_intel_connector(connector);
		intel_encoder = intel_connector->encoder;
		if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
			if (intel_encoder->hot_plug)
				intel_encoder->hot_plug(intel_encoder);
			if (intel_hpd_irq_event(dev, connector))
				changed = true;
		}
	}
622 623
	mutex_unlock(&mode_config->mutex);

624 625
	if (changed)
		drm_kms_helper_hotplug_event(dev);
626 627
}

628
static void ironlake_handle_rps_change(struct drm_device *dev)
629 630
{
	drm_i915_private_t *dev_priv = dev->dev_private;
631
	u32 busy_up, busy_down, max_avg, min_avg;
632 633 634 635
	u8 new_delay;
	unsigned long flags;

	spin_lock_irqsave(&mchdev_lock, flags);
636

637 638
	I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));

639
	new_delay = dev_priv->ips.cur_delay;
640

641
	I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
642 643
	busy_up = I915_READ(RCPREVBSYTUPAVG);
	busy_down = I915_READ(RCPREVBSYTDNAVG);
644 645 646 647
	max_avg = I915_READ(RCBMAXAVG);
	min_avg = I915_READ(RCBMINAVG);

	/* Handle RCS change request from hw */
648
	if (busy_up > max_avg) {
649 650 651 652
		if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
			new_delay = dev_priv->ips.cur_delay - 1;
		if (new_delay < dev_priv->ips.max_delay)
			new_delay = dev_priv->ips.max_delay;
653
	} else if (busy_down < min_avg) {
654 655 656 657
		if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
			new_delay = dev_priv->ips.cur_delay + 1;
		if (new_delay > dev_priv->ips.min_delay)
			new_delay = dev_priv->ips.min_delay;
658 659
	}

660
	if (ironlake_set_drps(dev, new_delay))
661
		dev_priv->ips.cur_delay = new_delay;
662

663 664
	spin_unlock_irqrestore(&mchdev_lock, flags);

665 666 667
	return;
}

668 669 670 671
static void notify_ring(struct drm_device *dev,
			struct intel_ring_buffer *ring)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
672

673 674 675
	if (ring->obj == NULL)
		return;

676
	trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
677

678
	wake_up_all(&ring->irq_queue);
679
	if (i915_enable_hangcheck) {
680
		mod_timer(&dev_priv->gpu_error.hangcheck_timer,
681
			  round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
682
	}
683 684
}

685
static void gen6_pm_rps_work(struct work_struct *work)
686
{
687
	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
688
						    rps.work);
689
	u32 pm_iir, pm_imr;
690
	u8 new_delay;
691

692 693 694
	spin_lock_irq(&dev_priv->rps.lock);
	pm_iir = dev_priv->rps.pm_iir;
	dev_priv->rps.pm_iir = 0;
695
	pm_imr = I915_READ(GEN6_PMIMR);
696 697
	/* Make sure not to corrupt PMIMR state used by ringbuffer code */
	I915_WRITE(GEN6_PMIMR, pm_imr & ~GEN6_PM_RPS_EVENTS);
698
	spin_unlock_irq(&dev_priv->rps.lock);
699

700
	if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
701 702
		return;

703
	mutex_lock(&dev_priv->rps.hw_lock);
704

705
	if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
706
		new_delay = dev_priv->rps.cur_delay + 1;
707 708 709 710 711 712 713 714 715

		/*
		 * For better performance, jump directly
		 * to RPe if we're below it.
		 */
		if (IS_VALLEYVIEW(dev_priv->dev) &&
		    dev_priv->rps.cur_delay < dev_priv->rps.rpe_delay)
			new_delay = dev_priv->rps.rpe_delay;
	} else
716
		new_delay = dev_priv->rps.cur_delay - 1;
717

718 719 720
	/* sysfs frequency interfaces may have snuck in while servicing the
	 * interrupt
	 */
721 722
	if (new_delay >= dev_priv->rps.min_delay &&
	    new_delay <= dev_priv->rps.max_delay) {
723 724 725 726
		if (IS_VALLEYVIEW(dev_priv->dev))
			valleyview_set_rps(dev_priv->dev, new_delay);
		else
			gen6_set_rps(dev_priv->dev, new_delay);
727
	}
728

729 730 731 732 733 734 735 736 737 738 739
	if (IS_VALLEYVIEW(dev_priv->dev)) {
		/*
		 * On VLV, when we enter RC6 we may not be at the minimum
		 * voltage level, so arm a timer to check.  It should only
		 * fire when there's activity or once after we've entered
		 * RC6, and then won't be re-armed until the next RPS interrupt.
		 */
		mod_delayed_work(dev_priv->wq, &dev_priv->rps.vlv_work,
				 msecs_to_jiffies(100));
	}

740
	mutex_unlock(&dev_priv->rps.hw_lock);
741 742
}

743 744 745 746 747 748 749 750 751 752 753 754 755

/**
 * ivybridge_parity_work - Workqueue called when a parity error interrupt
 * occurred.
 * @work: workqueue struct
 *
 * Doesn't actually do anything except notify userspace. As a consequence of
 * this event, userspace should try to remap the bad rows since statistically
 * it is likely the same row is more likely to go bad again.
 */
static void ivybridge_parity_work(struct work_struct *work)
{
	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
756
						    l3_parity.error_work);
757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783
	u32 error_status, row, bank, subbank;
	char *parity_event[5];
	uint32_t misccpctl;
	unsigned long flags;

	/* We must turn off DOP level clock gating to access the L3 registers.
	 * In order to prevent a get/put style interface, acquire struct mutex
	 * any time we access those registers.
	 */
	mutex_lock(&dev_priv->dev->struct_mutex);

	misccpctl = I915_READ(GEN7_MISCCPCTL);
	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
	POSTING_READ(GEN7_MISCCPCTL);

	error_status = I915_READ(GEN7_L3CDERRST1);
	row = GEN7_PARITY_ERROR_ROW(error_status);
	bank = GEN7_PARITY_ERROR_BANK(error_status);
	subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);

	I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
				    GEN7_L3CDERRST1_ENABLE);
	POSTING_READ(GEN7_L3CDERRST1);

	I915_WRITE(GEN7_MISCCPCTL, misccpctl);

	spin_lock_irqsave(&dev_priv->irq_lock, flags);
784
	dev_priv->gt_irq_mask &= ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806
	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);

	mutex_unlock(&dev_priv->dev->struct_mutex);

	parity_event[0] = "L3_PARITY_ERROR=1";
	parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
	parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
	parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
	parity_event[4] = NULL;

	kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
			   KOBJ_CHANGE, parity_event);

	DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
		  row, bank, subbank);

	kfree(parity_event[3]);
	kfree(parity_event[2]);
	kfree(parity_event[1]);
}

807
static void ivybridge_handle_parity_error(struct drm_device *dev)
808 809 810 811
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long flags;

812
	if (!HAS_L3_GPU_CACHE(dev))
813 814 815
		return;

	spin_lock_irqsave(&dev_priv->irq_lock, flags);
816
	dev_priv->gt_irq_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
817 818 819
	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);

820
	queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
821 822
}

823 824 825 826 827
static void snb_gt_irq_handler(struct drm_device *dev,
			       struct drm_i915_private *dev_priv,
			       u32 gt_iir)
{

828 829
	if (gt_iir &
	    (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
830
		notify_ring(dev, &dev_priv->ring[RCS]);
831
	if (gt_iir & GT_BSD_USER_INTERRUPT)
832
		notify_ring(dev, &dev_priv->ring[VCS]);
833
	if (gt_iir & GT_BLT_USER_INTERRUPT)
834 835
		notify_ring(dev, &dev_priv->ring[BCS]);

836 837 838
	if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
		      GT_BSD_CS_ERROR_INTERRUPT |
		      GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
839 840 841
		DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
		i915_handle_error(dev, false);
	}
842

843
	if (gt_iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
844
		ivybridge_handle_parity_error(dev);
845 846
}

847
/* Legacy way of handling PM interrupts */
848 849 850 851 852 853 854 855 856
static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
				u32 pm_iir)
{
	unsigned long flags;

	/*
	 * IIR bits should never already be set because IMR should
	 * prevent an interrupt from being shown in IIR. The warning
	 * displays a case where we've unsafely cleared
857
	 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
858 859
	 * type is not a problem, it displays a problem in the logic.
	 *
860
	 * The mask bit in IMR is cleared by dev_priv->rps.work.
861 862
	 */

863 864 865
	spin_lock_irqsave(&dev_priv->rps.lock, flags);
	dev_priv->rps.pm_iir |= pm_iir;
	I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
866
	POSTING_READ(GEN6_PMIMR);
867
	spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
868

869
	queue_work(dev_priv->wq, &dev_priv->rps.work);
870 871
}

872 873 874
#define HPD_STORM_DETECT_PERIOD 1000
#define HPD_STORM_THRESHOLD 5

875
static inline void intel_hpd_irq_handler(struct drm_device *dev,
876 877
					 u32 hotplug_trigger,
					 const u32 *hpd)
878 879 880 881
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	unsigned long irqflags;
	int i;
882
	bool storm_detected = false;
883

884 885 886
	if (!hotplug_trigger)
		return;

887 888 889
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);

	for (i = 1; i < HPD_NUM_PINS; i++) {
890

891 892 893 894
		if (!(hpd[i] & hotplug_trigger) ||
		    dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
			continue;

895
		dev_priv->hpd_event_bits |= (1 << i);
896 897 898 899 900 901 902
		if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
				   dev_priv->hpd_stats[i].hpd_last_jiffies
				   + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
			dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
			dev_priv->hpd_stats[i].hpd_cnt = 0;
		} else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
			dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
903
			dev_priv->hpd_event_bits &= ~(1 << i);
904
			DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
905
			storm_detected = true;
906 907 908 909 910 911
		} else {
			dev_priv->hpd_stats[i].hpd_cnt++;
		}
	}

	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
912

913 914
	if (storm_detected)
		dev_priv->display.hpd_irq_setup(dev);
915 916 917

	queue_work(dev_priv->wq,
		   &dev_priv->hotplug_work);
918 919
}

920 921
static void gmbus_irq_handler(struct drm_device *dev)
{
922 923 924
	struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;

	wake_up_all(&dev_priv->gmbus_wait_queue);
925 926
}

927 928
static void dp_aux_irq_handler(struct drm_device *dev)
{
929 930 931
	struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;

	wake_up_all(&dev_priv->gmbus_wait_queue);
932 933
}

934 935 936 937 938 939 940 941 942 943 944
/* Unlike gen6_queue_rps_work() from which this function is originally derived,
 * we must be able to deal with other PM interrupts. This is complicated because
 * of the way in which we use the masks to defer the RPS work (which for
 * posterity is necessary because of forcewake).
 */
static void hsw_pm_irq_handler(struct drm_i915_private *dev_priv,
			       u32 pm_iir)
{
	unsigned long flags;

	spin_lock_irqsave(&dev_priv->rps.lock, flags);
945
	dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
946 947 948
	if (dev_priv->rps.pm_iir) {
		I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
		/* never want to mask useful interrupts. (also posting read) */
949
		WARN_ON(I915_READ_NOTRACE(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS);
950 951 952 953 954
		/* TODO: if queue_work is slow, move it out of the spinlock */
		queue_work(dev_priv->wq, &dev_priv->rps.work);
	}
	spin_unlock_irqrestore(&dev_priv->rps.lock, flags);

B
Ben Widawsky 已提交
955 956 957 958 959 960 961 962 963
	if (pm_iir & ~GEN6_PM_RPS_EVENTS) {
		if (pm_iir & PM_VEBOX_USER_INTERRUPT)
			notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);

		if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
			DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
			i915_handle_error(dev_priv->dev, false);
		}
	}
964 965
}

966
static irqreturn_t valleyview_irq_handler(int irq, void *arg)
J
Jesse Barnes 已提交
967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987
{
	struct drm_device *dev = (struct drm_device *) arg;
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u32 iir, gt_iir, pm_iir;
	irqreturn_t ret = IRQ_NONE;
	unsigned long irqflags;
	int pipe;
	u32 pipe_stats[I915_MAX_PIPES];

	atomic_inc(&dev_priv->irq_received);

	while (true) {
		iir = I915_READ(VLV_IIR);
		gt_iir = I915_READ(GTIIR);
		pm_iir = I915_READ(GEN6_PMIIR);

		if (gt_iir == 0 && pm_iir == 0 && iir == 0)
			goto out;

		ret = IRQ_HANDLED;

988
		snb_gt_irq_handler(dev, dev_priv, gt_iir);
J
Jesse Barnes 已提交
989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006

		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
		for_each_pipe(pipe) {
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);

			/*
			 * Clear the PIPE*STAT regs before the IIR
			 */
			if (pipe_stats[pipe] & 0x8000ffff) {
				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
					DRM_DEBUG_DRIVER("pipe %c underrun\n",
							 pipe_name(pipe));
				I915_WRITE(reg, pipe_stats[pipe]);
			}
		}
		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

1007 1008 1009 1010 1011 1012 1013 1014 1015 1016
		for_each_pipe(pipe) {
			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
				drm_handle_vblank(dev, pipe);

			if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
				intel_prepare_page_flip(dev, pipe);
				intel_finish_page_flip(dev, pipe);
			}
		}

J
Jesse Barnes 已提交
1017 1018 1019
		/* Consume port.  Then clear IIR or we'll miss events */
		if (iir & I915_DISPLAY_PORT_INTERRUPT) {
			u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1020
			u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
J
Jesse Barnes 已提交
1021 1022 1023

			DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
					 hotplug_status);
1024 1025 1026

			intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);

J
Jesse Barnes 已提交
1027 1028 1029 1030
			I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
			I915_READ(PORT_HOTPLUG_STAT);
		}

1031 1032
		if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
			gmbus_irq_handler(dev);
J
Jesse Barnes 已提交
1033

1034
		if (pm_iir & GEN6_PM_RPS_EVENTS)
1035
			gen6_queue_rps_work(dev_priv, pm_iir);
J
Jesse Barnes 已提交
1036 1037 1038 1039 1040 1041 1042 1043 1044 1045

		I915_WRITE(GTIIR, gt_iir);
		I915_WRITE(GEN6_PMIIR, pm_iir);
		I915_WRITE(VLV_IIR, iir);
	}

out:
	return ret;
}

1046
static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1047 1048
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1049
	int pipe;
1050
	u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1051

1052 1053
	intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);

1054 1055 1056
	if (pch_iir & SDE_AUDIO_POWER_MASK) {
		int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
			       SDE_AUDIO_POWER_SHIFT);
1057
		DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1058 1059
				 port_name(port));
	}
1060

1061 1062 1063
	if (pch_iir & SDE_AUX_MASK)
		dp_aux_irq_handler(dev);

1064
	if (pch_iir & SDE_GMBUS)
1065
		gmbus_irq_handler(dev);
1066 1067 1068 1069 1070 1071 1072 1073 1074 1075

	if (pch_iir & SDE_AUDIO_HDCP_MASK)
		DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");

	if (pch_iir & SDE_AUDIO_TRANS_MASK)
		DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");

	if (pch_iir & SDE_POISON)
		DRM_ERROR("PCH poison interrupt\n");

1076 1077 1078 1079 1080
	if (pch_iir & SDE_FDI_MASK)
		for_each_pipe(pipe)
			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
					 pipe_name(pipe),
					 I915_READ(FDI_RX_IIR(pipe)));
1081 1082 1083 1084 1085 1086 1087 1088

	if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
		DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");

	if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
		DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");

	if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103
		if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
							  false))
			DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");

	if (pch_iir & SDE_TRANSB_FIFO_UNDER)
		if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
							  false))
			DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
}

static void ivb_err_int_handler(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 err_int = I915_READ(GEN7_ERR_INT);

1104 1105 1106
	if (err_int & ERR_INT_POISON)
		DRM_ERROR("Poison interrupt\n");

1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126
	if (err_int & ERR_INT_FIFO_UNDERRUN_A)
		if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
			DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");

	if (err_int & ERR_INT_FIFO_UNDERRUN_B)
		if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
			DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");

	if (err_int & ERR_INT_FIFO_UNDERRUN_C)
		if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false))
			DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");

	I915_WRITE(GEN7_ERR_INT, err_int);
}

static void cpt_serr_int_handler(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 serr_int = I915_READ(SERR_INT);

1127 1128 1129
	if (serr_int & SERR_INT_POISON)
		DRM_ERROR("PCH poison interrupt\n");

1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145
	if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
		if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
							  false))
			DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");

	if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
		if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
							  false))
			DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");

	if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
		if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
							  false))
			DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");

	I915_WRITE(SERR_INT, serr_int);
1146 1147
}

1148 1149 1150 1151
static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;
1152
	u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1153

1154 1155
	intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);

1156 1157 1158 1159 1160 1161
	if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
		int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
			       SDE_AUDIO_POWER_SHIFT_CPT);
		DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
				 port_name(port));
	}
1162 1163

	if (pch_iir & SDE_AUX_MASK_CPT)
1164
		dp_aux_irq_handler(dev);
1165 1166

	if (pch_iir & SDE_GMBUS_CPT)
1167
		gmbus_irq_handler(dev);
1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179

	if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
		DRM_DEBUG_DRIVER("Audio CP request interrupt\n");

	if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
		DRM_DEBUG_DRIVER("Audio CP change interrupt\n");

	if (pch_iir & SDE_FDI_MASK_CPT)
		for_each_pipe(pipe)
			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
					 pipe_name(pipe),
					 I915_READ(FDI_RX_IIR(pipe)));
1180 1181 1182

	if (pch_iir & SDE_ERROR_CPT)
		cpt_serr_int_handler(dev);
1183 1184
}

1185
static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
1186 1187 1188
{
	struct drm_device *dev = (struct drm_device *) arg;
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1189
	u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier = 0;
1190 1191
	irqreturn_t ret = IRQ_NONE;
	int i;
1192 1193 1194

	atomic_inc(&dev_priv->irq_received);

1195 1196 1197 1198 1199 1200 1201 1202
	/* We get interrupts on unclaimed registers, so check for this before we
	 * do any I915_{READ,WRITE}. */
	if (IS_HASWELL(dev) &&
	    (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
		DRM_ERROR("Unclaimed register before interrupt\n");
		I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
	}

1203 1204 1205 1206
	/* disable master interrupt before clearing iir  */
	de_ier = I915_READ(DEIER);
	I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);

1207 1208 1209 1210 1211
	/* Disable south interrupts. We'll only write to SDEIIR once, so further
	 * interrupts will will be stored on its back queue, and then we'll be
	 * able to process them after we restore SDEIER (as soon as we restore
	 * it, we'll get an interrupt if SDEIIR still has something to process
	 * due to its back queue). */
1212 1213 1214 1215 1216
	if (!HAS_PCH_NOP(dev)) {
		sde_ier = I915_READ(SDEIER);
		I915_WRITE(SDEIER, 0);
		POSTING_READ(SDEIER);
	}
1217

1218 1219 1220
	/* On Haswell, also mask ERR_INT because we don't want to risk
	 * generating "unclaimed register" interrupts from inside the interrupt
	 * handler. */
1221 1222
	if (IS_HASWELL(dev)) {
		spin_lock(&dev_priv->irq_lock);
1223
		ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
1224 1225
		spin_unlock(&dev_priv->irq_lock);
	}
1226

1227
	gt_iir = I915_READ(GTIIR);
1228 1229 1230 1231
	if (gt_iir) {
		snb_gt_irq_handler(dev, dev_priv, gt_iir);
		I915_WRITE(GTIIR, gt_iir);
		ret = IRQ_HANDLED;
1232 1233
	}

1234 1235
	de_iir = I915_READ(DEIIR);
	if (de_iir) {
1236 1237 1238
		if (de_iir & DE_ERR_INT_IVB)
			ivb_err_int_handler(dev);

1239 1240 1241
		if (de_iir & DE_AUX_CHANNEL_A_IVB)
			dp_aux_irq_handler(dev);

1242
		if (de_iir & DE_GSE_IVB)
1243
			intel_opregion_asle_intr(dev);
1244 1245

		for (i = 0; i < 3; i++) {
1246 1247
			if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
				drm_handle_vblank(dev, i);
1248 1249 1250 1251 1252
			if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
				intel_prepare_page_flip(dev, i);
				intel_finish_page_flip_plane(dev, i);
			}
		}
1253

1254
		/* check event from PCH */
1255
		if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1256
			u32 pch_iir = I915_READ(SDEIIR);
1257

1258
			cpt_irq_handler(dev, pch_iir);
1259

1260 1261 1262
			/* clear PCH hotplug event before clear CPU irq */
			I915_WRITE(SDEIIR, pch_iir);
		}
1263

1264 1265
		I915_WRITE(DEIIR, de_iir);
		ret = IRQ_HANDLED;
1266 1267
	}

1268 1269
	pm_iir = I915_READ(GEN6_PMIIR);
	if (pm_iir) {
1270 1271
		if (IS_HASWELL(dev))
			hsw_pm_irq_handler(dev_priv, pm_iir);
1272
		else if (pm_iir & GEN6_PM_RPS_EVENTS)
1273 1274 1275 1276
			gen6_queue_rps_work(dev_priv, pm_iir);
		I915_WRITE(GEN6_PMIIR, pm_iir);
		ret = IRQ_HANDLED;
	}
1277

1278 1279 1280 1281 1282 1283
	if (IS_HASWELL(dev)) {
		spin_lock(&dev_priv->irq_lock);
		if (ivb_can_enable_err_int(dev))
			ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
		spin_unlock(&dev_priv->irq_lock);
	}
1284

1285 1286
	I915_WRITE(DEIER, de_ier);
	POSTING_READ(DEIER);
1287 1288 1289 1290
	if (!HAS_PCH_NOP(dev)) {
		I915_WRITE(SDEIER, sde_ier);
		POSTING_READ(SDEIER);
	}
1291 1292 1293 1294

	return ret;
}

1295 1296 1297 1298
static void ilk_gt_irq_handler(struct drm_device *dev,
			       struct drm_i915_private *dev_priv,
			       u32 gt_iir)
{
1299 1300
	if (gt_iir &
	    (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1301
		notify_ring(dev, &dev_priv->ring[RCS]);
1302
	if (gt_iir & ILK_BSD_USER_INTERRUPT)
1303 1304 1305
		notify_ring(dev, &dev_priv->ring[VCS]);
}

1306
static irqreturn_t ironlake_irq_handler(int irq, void *arg)
1307
{
1308
	struct drm_device *dev = (struct drm_device *) arg;
1309 1310
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int ret = IRQ_NONE;
1311
	u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
1312

1313 1314
	atomic_inc(&dev_priv->irq_received);

1315 1316 1317
	/* disable master interrupt before clearing iir  */
	de_ier = I915_READ(DEIER);
	I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
1318
	POSTING_READ(DEIER);
1319

1320 1321 1322 1323 1324 1325 1326 1327 1328
	/* Disable south interrupts. We'll only write to SDEIIR once, so further
	 * interrupts will will be stored on its back queue, and then we'll be
	 * able to process them after we restore SDEIER (as soon as we restore
	 * it, we'll get an interrupt if SDEIIR still has something to process
	 * due to its back queue). */
	sde_ier = I915_READ(SDEIER);
	I915_WRITE(SDEIER, 0);
	POSTING_READ(SDEIER);

1329 1330
	de_iir = I915_READ(DEIIR);
	gt_iir = I915_READ(GTIIR);
1331
	pm_iir = I915_READ(GEN6_PMIIR);
1332

1333
	if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
1334
		goto done;
1335

1336
	ret = IRQ_HANDLED;
1337

1338 1339 1340 1341
	if (IS_GEN5(dev))
		ilk_gt_irq_handler(dev, dev_priv, gt_iir);
	else
		snb_gt_irq_handler(dev, dev_priv, gt_iir);
1342

1343 1344 1345
	if (de_iir & DE_AUX_CHANNEL_A)
		dp_aux_irq_handler(dev);

1346
	if (de_iir & DE_GSE)
1347
		intel_opregion_asle_intr(dev);
1348

1349 1350 1351 1352 1353 1354
	if (de_iir & DE_PIPEA_VBLANK)
		drm_handle_vblank(dev, 0);

	if (de_iir & DE_PIPEB_VBLANK)
		drm_handle_vblank(dev, 1);

1355 1356 1357
	if (de_iir & DE_POISON)
		DRM_ERROR("Poison interrupt\n");

1358 1359 1360 1361 1362 1363 1364 1365
	if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
		if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
			DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");

	if (de_iir & DE_PIPEB_FIFO_UNDERRUN)
		if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
			DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");

1366
	if (de_iir & DE_PLANEA_FLIP_DONE) {
1367
		intel_prepare_page_flip(dev, 0);
1368
		intel_finish_page_flip_plane(dev, 0);
1369
	}
1370

1371
	if (de_iir & DE_PLANEB_FLIP_DONE) {
1372
		intel_prepare_page_flip(dev, 1);
1373
		intel_finish_page_flip_plane(dev, 1);
1374
	}
1375

1376
	/* check event from PCH */
1377
	if (de_iir & DE_PCH_EVENT) {
1378 1379
		u32 pch_iir = I915_READ(SDEIIR);

1380 1381 1382 1383
		if (HAS_PCH_CPT(dev))
			cpt_irq_handler(dev, pch_iir);
		else
			ibx_irq_handler(dev, pch_iir);
1384 1385 1386

		/* should clear PCH hotplug event before clear CPU irq */
		I915_WRITE(SDEIIR, pch_iir);
1387
	}
1388

1389 1390
	if (IS_GEN5(dev) &&  de_iir & DE_PCU_EVENT)
		ironlake_handle_rps_change(dev);
1391

1392
	if (IS_GEN6(dev) && pm_iir & GEN6_PM_RPS_EVENTS)
1393
		gen6_queue_rps_work(dev_priv, pm_iir);
1394

1395 1396
	I915_WRITE(GTIIR, gt_iir);
	I915_WRITE(DEIIR, de_iir);
1397
	I915_WRITE(GEN6_PMIIR, pm_iir);
1398 1399

done:
1400
	I915_WRITE(DEIER, de_ier);
1401
	POSTING_READ(DEIER);
1402 1403
	I915_WRITE(SDEIER, sde_ier);
	POSTING_READ(SDEIER);
1404

1405 1406 1407
	return ret;
}

1408 1409 1410 1411 1412 1413 1414 1415 1416
/**
 * i915_error_work_func - do process context error handling work
 * @work: work struct
 *
 * Fire an error uevent so userspace can see that a hang or error
 * was detected.
 */
static void i915_error_work_func(struct work_struct *work)
{
1417 1418 1419 1420
	struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
						    work);
	drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
						    gpu_error);
1421
	struct drm_device *dev = dev_priv->dev;
1422
	struct intel_ring_buffer *ring;
1423 1424 1425
	char *error_event[] = { "ERROR=1", NULL };
	char *reset_event[] = { "RESET=1", NULL };
	char *reset_done_event[] = { "ERROR=0", NULL };
1426
	int i, ret;
1427

1428 1429
	kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);

1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440
	/*
	 * Note that there's only one work item which does gpu resets, so we
	 * need not worry about concurrent gpu resets potentially incrementing
	 * error->reset_counter twice. We only need to take care of another
	 * racing irq/hangcheck declaring the gpu dead for a second time. A
	 * quick check for that is good enough: schedule_work ensures the
	 * correct ordering between hang detection and this work item, and since
	 * the reset in-progress bit is only ever set by code outside of this
	 * work we don't need to worry about any other races.
	 */
	if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
1441
		DRM_DEBUG_DRIVER("resetting chip\n");
1442 1443
		kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
				   reset_event);
1444

1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462
		ret = i915_reset(dev);

		if (ret == 0) {
			/*
			 * After all the gem state is reset, increment the reset
			 * counter and wake up everyone waiting for the reset to
			 * complete.
			 *
			 * Since unlock operations are a one-sided barrier only,
			 * we need to insert a barrier here to order any seqno
			 * updates before
			 * the counter increment.
			 */
			smp_mb__before_atomic_inc();
			atomic_inc(&dev_priv->gpu_error.reset_counter);

			kobject_uevent_env(&dev->primary->kdev.kobj,
					   KOBJ_CHANGE, reset_done_event);
1463 1464
		} else {
			atomic_set(&error->reset_counter, I915_WEDGED);
1465
		}
1466

1467 1468 1469
		for_each_ring(ring, dev_priv, i)
			wake_up_all(&ring->irq_queue);

1470 1471
		intel_display_handle_reset(dev);

1472
		wake_up_all(&dev_priv->gpu_error.reset_queue);
1473
	}
1474 1475
}

1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504
/* NB: please notice the memset */
static void i915_get_extra_instdone(struct drm_device *dev,
				    uint32_t *instdone)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);

	switch(INTEL_INFO(dev)->gen) {
	case 2:
	case 3:
		instdone[0] = I915_READ(INSTDONE);
		break;
	case 4:
	case 5:
	case 6:
		instdone[0] = I915_READ(INSTDONE_I965);
		instdone[1] = I915_READ(INSTDONE1);
		break;
	default:
		WARN_ONCE(1, "Unsupported platform\n");
	case 7:
		instdone[0] = I915_READ(GEN7_INSTDONE_1);
		instdone[1] = I915_READ(GEN7_SC_INSTDONE);
		instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
		instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
		break;
	}
}

1505
#ifdef CONFIG_DEBUG_FS
1506
static struct drm_i915_error_object *
1507 1508 1509
i915_error_object_create_sized(struct drm_i915_private *dev_priv,
			       struct drm_i915_gem_object *src,
			       const int num_pages)
1510 1511
{
	struct drm_i915_error_object *dst;
1512
	int i;
1513
	u32 reloc_offset;
1514

1515
	if (src == NULL || src->pages == NULL)
1516 1517
		return NULL;

1518
	dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
1519 1520 1521
	if (dst == NULL)
		return NULL;

1522
	reloc_offset = src->gtt_offset;
1523
	for (i = 0; i < num_pages; i++) {
1524
		unsigned long flags;
1525
		void *d;
1526

1527
		d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
1528 1529
		if (d == NULL)
			goto unwind;
1530

1531
		local_irq_save(flags);
B
Ben Widawsky 已提交
1532
		if (reloc_offset < dev_priv->gtt.mappable_end &&
1533
		    src->has_global_gtt_mapping) {
1534 1535 1536 1537 1538 1539 1540
			void __iomem *s;

			/* Simply ignore tiling or any overlapping fence.
			 * It's part of the error state, and this hopefully
			 * captures what the GPU read.
			 */

B
Ben Widawsky 已提交
1541
			s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
1542 1543 1544
						     reloc_offset);
			memcpy_fromio(d, s, PAGE_SIZE);
			io_mapping_unmap_atomic(s);
1545 1546 1547 1548 1549 1550 1551
		} else if (src->stolen) {
			unsigned long offset;

			offset = dev_priv->mm.stolen_base;
			offset += src->stolen->start;
			offset += i << PAGE_SHIFT;

D
Daniel Vetter 已提交
1552
			memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
1553
		} else {
1554
			struct page *page;
1555 1556
			void *s;

1557
			page = i915_gem_object_get_page(src, i);
1558

1559 1560 1561
			drm_clflush_pages(&page, 1);

			s = kmap_atomic(page);
1562 1563 1564
			memcpy(d, s, PAGE_SIZE);
			kunmap_atomic(s);

1565
			drm_clflush_pages(&page, 1);
1566
		}
1567
		local_irq_restore(flags);
1568

1569
		dst->pages[i] = d;
1570 1571

		reloc_offset += PAGE_SIZE;
1572
	}
1573
	dst->page_count = num_pages;
1574
	dst->gtt_offset = src->gtt_offset;
1575 1576 1577 1578

	return dst;

unwind:
1579 1580
	while (i--)
		kfree(dst->pages[i]);
1581 1582 1583
	kfree(dst);
	return NULL;
}
1584 1585 1586
#define i915_error_object_create(dev_priv, src) \
	i915_error_object_create_sized((dev_priv), (src), \
				       (src)->base.size>>PAGE_SHIFT)
1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601

static void
i915_error_object_free(struct drm_i915_error_object *obj)
{
	int page;

	if (obj == NULL)
		return;

	for (page = 0; page < obj->page_count; page++)
		kfree(obj->pages[page]);

	kfree(obj);
}

1602 1603
void
i915_error_state_free(struct kref *error_ref)
1604
{
1605 1606
	struct drm_i915_error_state *error = container_of(error_ref,
							  typeof(*error), ref);
1607 1608
	int i;

1609 1610 1611
	for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
		i915_error_object_free(error->ring[i].batchbuffer);
		i915_error_object_free(error->ring[i].ringbuffer);
1612
		i915_error_object_free(error->ring[i].ctx);
1613 1614
		kfree(error->ring[i].requests);
	}
1615

1616
	kfree(error->active_bo);
1617
	kfree(error->overlay);
1618
	kfree(error->display);
1619 1620
	kfree(error);
}
1621 1622 1623 1624 1625
static void capture_bo(struct drm_i915_error_buffer *err,
		       struct drm_i915_gem_object *obj)
{
	err->size = obj->base.size;
	err->name = obj->base.name;
1626 1627
	err->rseqno = obj->last_read_seqno;
	err->wseqno = obj->last_write_seqno;
1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642
	err->gtt_offset = obj->gtt_offset;
	err->read_domains = obj->base.read_domains;
	err->write_domain = obj->base.write_domain;
	err->fence_reg = obj->fence_reg;
	err->pinned = 0;
	if (obj->pin_count > 0)
		err->pinned = 1;
	if (obj->user_pin_count > 0)
		err->pinned = -1;
	err->tiling = obj->tiling_mode;
	err->dirty = obj->dirty;
	err->purgeable = obj->madv != I915_MADV_WILLNEED;
	err->ring = obj->ring ? obj->ring->id : -1;
	err->cache_level = obj->cache_level;
}
1643

1644 1645
static u32 capture_active_bo(struct drm_i915_error_buffer *err,
			     int count, struct list_head *head)
1646 1647 1648 1649 1650
{
	struct drm_i915_gem_object *obj;
	int i = 0;

	list_for_each_entry(obj, head, mm_list) {
1651
		capture_bo(err++, obj);
1652 1653
		if (++i == count)
			break;
1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664
	}

	return i;
}

static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
			     int count, struct list_head *head)
{
	struct drm_i915_gem_object *obj;
	int i = 0;

1665
	list_for_each_entry(obj, head, global_list) {
1666 1667
		if (obj->pin_count == 0)
			continue;
1668

1669 1670 1671
		capture_bo(err++, obj);
		if (++i == count)
			break;
1672 1673 1674 1675 1676
	}

	return i;
}

1677 1678 1679 1680 1681 1682 1683 1684
static void i915_gem_record_fences(struct drm_device *dev,
				   struct drm_i915_error_state *error)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;

	/* Fences */
	switch (INTEL_INFO(dev)->gen) {
1685
	case 7:
1686
	case 6:
1687
		for (i = 0; i < dev_priv->num_fence_regs; i++)
1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703
			error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
		break;
	case 5:
	case 4:
		for (i = 0; i < 16; i++)
			error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
		break;
	case 3:
		if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
			for (i = 0; i < 8; i++)
				error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
	case 2:
		for (i = 0; i < 8; i++)
			error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
		break;

1704 1705
	default:
		BUG();
1706 1707 1708
	}
}

1709 1710 1711 1712 1713 1714 1715 1716 1717 1718
static struct drm_i915_error_object *
i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
			     struct intel_ring_buffer *ring)
{
	struct drm_i915_gem_object *obj;
	u32 seqno;

	if (!ring->get_seqno)
		return NULL;

1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730
	if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
		u32 acthd = I915_READ(ACTHD);

		if (WARN_ON(ring->id != RCS))
			return NULL;

		obj = ring->private;
		if (acthd >= obj->gtt_offset &&
		    acthd < obj->gtt_offset + obj->base.size)
			return i915_error_object_create(dev_priv, obj);
	}

1731
	seqno = ring->get_seqno(ring, false);
1732 1733 1734 1735
	list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
		if (obj->ring != ring)
			continue;

1736
		if (i915_seqno_passed(seqno, obj->last_read_seqno))
1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750
			continue;

		if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
			continue;

		/* We need to copy these to an anonymous buffer as the simplest
		 * method to avoid being overwritten by userspace.
		 */
		return i915_error_object_create(dev_priv, obj);
	}

	return NULL;
}

1751 1752 1753 1754 1755 1756
static void i915_record_ring_state(struct drm_device *dev,
				   struct drm_i915_error_state *error,
				   struct intel_ring_buffer *ring)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

1757
	if (INTEL_INFO(dev)->gen >= 6) {
1758
		error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
1759
		error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
1760 1761 1762 1763
		error->semaphore_mboxes[ring->id][0]
			= I915_READ(RING_SYNC_0(ring->mmio_base));
		error->semaphore_mboxes[ring->id][1]
			= I915_READ(RING_SYNC_1(ring->mmio_base));
1764 1765
		error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
		error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
1766
	}
1767

1768
	if (INTEL_INFO(dev)->gen >= 4) {
1769
		error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
1770 1771 1772
		error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
		error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
		error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
1773
		error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
1774
		if (ring->id == RCS)
1775 1776
			error->bbaddr = I915_READ64(BB_ADDR);
	} else {
1777
		error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
1778 1779 1780 1781 1782
		error->ipeir[ring->id] = I915_READ(IPEIR);
		error->ipehr[ring->id] = I915_READ(IPEHR);
		error->instdone[ring->id] = I915_READ(INSTDONE);
	}

B
Ben Widawsky 已提交
1783
	error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
1784
	error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
1785
	error->seqno[ring->id] = ring->get_seqno(ring, false);
1786
	error->acthd[ring->id] = intel_ring_get_active_head(ring);
1787 1788
	error->head[ring->id] = I915_READ_HEAD(ring);
	error->tail[ring->id] = I915_READ_TAIL(ring);
1789
	error->ctl[ring->id] = I915_READ_CTL(ring);
1790 1791 1792

	error->cpu_ring_head[ring->id] = ring->head;
	error->cpu_ring_tail[ring->id] = ring->tail;
1793 1794
}

1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806

static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
					   struct drm_i915_error_state *error,
					   struct drm_i915_error_ring *ering)
{
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
	struct drm_i915_gem_object *obj;

	/* Currently render ring is the only HW context user */
	if (ring->id != RCS || !error->ccid)
		return;

1807
	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1808 1809 1810 1811 1812 1813 1814
		if ((error->ccid & PAGE_MASK) == obj->gtt_offset) {
			ering->ctx = i915_error_object_create_sized(dev_priv,
								    obj, 1);
		}
	}
}

1815 1816 1817 1818
static void i915_gem_record_rings(struct drm_device *dev,
				  struct drm_i915_error_state *error)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
1819
	struct intel_ring_buffer *ring;
1820 1821 1822
	struct drm_i915_gem_request *request;
	int i, count;

1823
	for_each_ring(ring, dev_priv, i) {
1824 1825 1826 1827 1828 1829 1830 1831
		i915_record_ring_state(dev, error, ring);

		error->ring[i].batchbuffer =
			i915_error_first_batchbuffer(dev_priv, ring);

		error->ring[i].ringbuffer =
			i915_error_object_create(dev_priv, ring->obj);

1832 1833 1834

		i915_gem_record_active_context(ring, error, &error->ring[i]);

1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854
		count = 0;
		list_for_each_entry(request, &ring->request_list, list)
			count++;

		error->ring[i].num_requests = count;
		error->ring[i].requests =
			kmalloc(count*sizeof(struct drm_i915_error_request),
				GFP_ATOMIC);
		if (error->ring[i].requests == NULL) {
			error->ring[i].num_requests = 0;
			continue;
		}

		count = 0;
		list_for_each_entry(request, &ring->request_list, list) {
			struct drm_i915_error_request *erq;

			erq = &error->ring[i].requests[count++];
			erq->seqno = request->seqno;
			erq->jiffies = request->emitted_jiffies;
1855
			erq->tail = request->tail;
1856 1857 1858 1859
		}
	}
}

1860 1861 1862 1863 1864 1865 1866 1867 1868
/**
 * i915_capture_error_state - capture an error record for later analysis
 * @dev: drm device
 *
 * Should be called when an error is detected (either a hang or an error
 * interrupt) to capture error state from the time of the error.  Fills
 * out a structure which becomes available in debugfs for user level tools
 * to pick up.
 */
1869 1870 1871
static void i915_capture_error_state(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
1872
	struct drm_i915_gem_object *obj;
1873 1874
	struct drm_i915_error_state *error;
	unsigned long flags;
1875
	int i, pipe;
1876

1877 1878 1879
	spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
	error = dev_priv->gpu_error.first_error;
	spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1880 1881
	if (error)
		return;
1882

1883
	/* Account for pipe specific data like PIPE*STAT */
1884
	error = kzalloc(sizeof(*error), GFP_ATOMIC);
1885
	if (!error) {
1886 1887
		DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
		return;
1888 1889
	}

1890
	DRM_INFO("capturing error event; look for more information in "
1891
		 "/sys/kernel/debug/dri/%d/i915_error_state\n",
1892
		 dev->primary->index);
1893

1894
	kref_init(&error->ref);
1895 1896
	error->eir = I915_READ(EIR);
	error->pgtbl_er = I915_READ(PGTBL_ER);
1897 1898
	if (HAS_HW_CONTEXTS(dev))
		error->ccid = I915_READ(CCID);
1899 1900 1901 1902 1903 1904 1905 1906 1907 1908

	if (HAS_PCH_SPLIT(dev))
		error->ier = I915_READ(DEIER) | I915_READ(GTIER);
	else if (IS_VALLEYVIEW(dev))
		error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
	else if (IS_GEN2(dev))
		error->ier = I915_READ16(IER);
	else
		error->ier = I915_READ(IER);

1909 1910 1911 1912 1913 1914 1915 1916 1917 1918
	if (INTEL_INFO(dev)->gen >= 6)
		error->derrmr = I915_READ(DERRMR);

	if (IS_VALLEYVIEW(dev))
		error->forcewake = I915_READ(FORCEWAKE_VLV);
	else if (INTEL_INFO(dev)->gen >= 7)
		error->forcewake = I915_READ(FORCEWAKE_MT);
	else if (INTEL_INFO(dev)->gen == 6)
		error->forcewake = I915_READ(FORCEWAKE);

1919 1920 1921
	if (!HAS_PCH_SPLIT(dev))
		for_each_pipe(pipe)
			error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1922

1923
	if (INTEL_INFO(dev)->gen >= 6) {
1924
		error->error = I915_READ(ERROR_GEN6);
1925 1926
		error->done_reg = I915_READ(DONE_REG);
	}
1927

1928 1929 1930
	if (INTEL_INFO(dev)->gen == 7)
		error->err_int = I915_READ(GEN7_ERR_INT);

1931 1932
	i915_get_extra_instdone(dev, error->extra_instdone);

1933
	i915_gem_record_fences(dev, error);
1934
	i915_gem_record_rings(dev, error);
1935

1936
	/* Record buffers on the active and pinned lists. */
1937
	error->active_bo = NULL;
1938
	error->pinned_bo = NULL;
1939

1940 1941 1942 1943
	i = 0;
	list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
		i++;
	error->active_bo_count = i;
1944
	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1945 1946
		if (obj->pin_count)
			i++;
1947
	error->pinned_bo_count = i - error->active_bo_count;
1948

1949 1950
	error->active_bo = NULL;
	error->pinned_bo = NULL;
1951 1952
	if (i) {
		error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
1953
					   GFP_ATOMIC);
1954 1955 1956
		if (error->active_bo)
			error->pinned_bo =
				error->active_bo + error->active_bo_count;
1957 1958
	}

1959 1960
	if (error->active_bo)
		error->active_bo_count =
1961 1962 1963
			capture_active_bo(error->active_bo,
					  error->active_bo_count,
					  &dev_priv->mm.active_list);
1964 1965 1966

	if (error->pinned_bo)
		error->pinned_bo_count =
1967 1968
			capture_pinned_bo(error->pinned_bo,
					  error->pinned_bo_count,
C
Chris Wilson 已提交
1969
					  &dev_priv->mm.bound_list);
1970

1971 1972
	do_gettimeofday(&error->time);

1973
	error->overlay = intel_overlay_capture_error_state(dev);
1974
	error->display = intel_display_capture_error_state(dev);
1975

1976 1977 1978
	spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
	if (dev_priv->gpu_error.first_error == NULL) {
		dev_priv->gpu_error.first_error = error;
1979 1980
		error = NULL;
	}
1981
	spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1982 1983

	if (error)
1984
		i915_error_state_free(&error->ref);
1985 1986 1987 1988 1989 1990
}

void i915_destroy_error_state(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_error_state *error;
1991
	unsigned long flags;
1992

1993 1994 1995 1996
	spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
	error = dev_priv->gpu_error.first_error;
	dev_priv->gpu_error.first_error = NULL;
	spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1997 1998

	if (error)
1999
		kref_put(&error->ref, i915_error_state_free);
2000
}
2001 2002 2003
#else
#define i915_capture_error_state(x)
#endif
2004

2005
static void i915_report_and_clear_eir(struct drm_device *dev)
2006 2007
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2008
	uint32_t instdone[I915_NUM_INSTDONE_REG];
2009
	u32 eir = I915_READ(EIR);
2010
	int pipe, i;
2011

2012 2013
	if (!eir)
		return;
2014

2015
	pr_err("render error detected, EIR: 0x%08x\n", eir);
2016

2017 2018
	i915_get_extra_instdone(dev, instdone);

2019 2020 2021 2022
	if (IS_G4X(dev)) {
		if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
			u32 ipeir = I915_READ(IPEIR_I965);

2023 2024
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2025 2026
			for (i = 0; i < ARRAY_SIZE(instdone); i++)
				pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2027 2028
			pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2029
			I915_WRITE(IPEIR_I965, ipeir);
2030
			POSTING_READ(IPEIR_I965);
2031 2032 2033
		}
		if (eir & GM45_ERROR_PAGE_TABLE) {
			u32 pgtbl_err = I915_READ(PGTBL_ER);
2034 2035
			pr_err("page table error\n");
			pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2036
			I915_WRITE(PGTBL_ER, pgtbl_err);
2037
			POSTING_READ(PGTBL_ER);
2038 2039 2040
		}
	}

2041
	if (!IS_GEN2(dev)) {
2042 2043
		if (eir & I915_ERROR_PAGE_TABLE) {
			u32 pgtbl_err = I915_READ(PGTBL_ER);
2044 2045
			pr_err("page table error\n");
			pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2046
			I915_WRITE(PGTBL_ER, pgtbl_err);
2047
			POSTING_READ(PGTBL_ER);
2048 2049 2050 2051
		}
	}

	if (eir & I915_ERROR_MEMORY_REFRESH) {
2052
		pr_err("memory refresh error:\n");
2053
		for_each_pipe(pipe)
2054
			pr_err("pipe %c stat: 0x%08x\n",
2055
			       pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2056 2057 2058
		/* pipestat has already been acked */
	}
	if (eir & I915_ERROR_INSTRUCTION) {
2059 2060
		pr_err("instruction error\n");
		pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
2061 2062
		for (i = 0; i < ARRAY_SIZE(instdone); i++)
			pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2063
		if (INTEL_INFO(dev)->gen < 4) {
2064 2065
			u32 ipeir = I915_READ(IPEIR);

2066 2067 2068
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
2069
			I915_WRITE(IPEIR, ipeir);
2070
			POSTING_READ(IPEIR);
2071 2072 2073
		} else {
			u32 ipeir = I915_READ(IPEIR_I965);

2074 2075 2076 2077
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
			pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2078
			I915_WRITE(IPEIR_I965, ipeir);
2079
			POSTING_READ(IPEIR_I965);
2080 2081 2082 2083
		}
	}

	I915_WRITE(EIR, eir);
2084
	POSTING_READ(EIR);
2085 2086 2087 2088 2089 2090 2091 2092 2093 2094
	eir = I915_READ(EIR);
	if (eir) {
		/*
		 * some errors might have become stuck,
		 * mask them.
		 */
		DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
		I915_WRITE(EMR, I915_READ(EMR) | eir);
		I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
	}
2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106
}

/**
 * i915_handle_error - handle an error interrupt
 * @dev: drm device
 *
 * Do some basic checking of regsiter state at error interrupt time and
 * dump it to the syslog.  Also call i915_capture_error_state() to make
 * sure we get a record and make it available in debugfs.  Fire a uevent
 * so userspace knows something bad happened (should trigger collection
 * of a ring dump etc.).
 */
2107
void i915_handle_error(struct drm_device *dev, bool wedged)
2108 2109
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2110 2111
	struct intel_ring_buffer *ring;
	int i;
2112 2113 2114

	i915_capture_error_state(dev);
	i915_report_and_clear_eir(dev);
2115

2116
	if (wedged) {
2117 2118
		atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
				&dev_priv->gpu_error.reset_counter);
2119

2120
		/*
2121 2122
		 * Wakeup waiting processes so that the reset work item
		 * doesn't deadlock trying to grab various locks.
2123
		 */
2124 2125
		for_each_ring(ring, dev_priv, i)
			wake_up_all(&ring->irq_queue);
2126 2127
	}

2128
	queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
2129 2130
}

2131
static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
2132 2133 2134 2135
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2136
	struct drm_i915_gem_object *obj;
2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147
	struct intel_unpin_work *work;
	unsigned long flags;
	bool stall_detected;

	/* Ignore early vblank irqs */
	if (intel_crtc == NULL)
		return;

	spin_lock_irqsave(&dev->event_lock, flags);
	work = intel_crtc->unpin_work;

2148 2149 2150
	if (work == NULL ||
	    atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
	    !work->enable_stall_check) {
2151 2152 2153 2154 2155 2156
		/* Either the pending flip IRQ arrived, or we're too early. Don't check */
		spin_unlock_irqrestore(&dev->event_lock, flags);
		return;
	}

	/* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2157
	obj = work->pending_flip_obj;
2158
	if (INTEL_INFO(dev)->gen >= 4) {
2159
		int dspsurf = DSPSURF(intel_crtc->plane);
2160 2161
		stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
					obj->gtt_offset;
2162
	} else {
2163
		int dspaddr = DSPADDR(intel_crtc->plane);
2164
		stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
2165
							crtc->y * crtc->fb->pitches[0] +
2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176
							crtc->x * crtc->fb->bits_per_pixel/8);
	}

	spin_unlock_irqrestore(&dev->event_lock, flags);

	if (stall_detected) {
		DRM_DEBUG_DRIVER("Pageflip stall detected\n");
		intel_prepare_page_flip(dev, intel_crtc->plane);
	}
}

2177 2178 2179
/* Called from drm generic code, passed 'crtc' which
 * we use as a pipe index
 */
2180
static int i915_enable_vblank(struct drm_device *dev, int pipe)
2181 2182
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2183
	unsigned long irqflags;
2184

2185
	if (!i915_pipe_enabled(dev, pipe))
2186
		return -EINVAL;
2187

2188
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2189
	if (INTEL_INFO(dev)->gen >= 4)
2190 2191
		i915_enable_pipestat(dev_priv, pipe,
				     PIPE_START_VBLANK_INTERRUPT_ENABLE);
2192
	else
2193 2194
		i915_enable_pipestat(dev_priv, pipe,
				     PIPE_VBLANK_INTERRUPT_ENABLE);
2195 2196 2197

	/* maintain vblank delivery even in deep C-states */
	if (dev_priv->info->gen == 3)
2198
		I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
2199
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2200

2201 2202 2203
	return 0;
}

2204
static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2205 2206 2207 2208 2209 2210 2211 2212 2213
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;

	if (!i915_pipe_enabled(dev, pipe))
		return -EINVAL;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
	ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
2214
				    DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
2215 2216 2217 2218 2219
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

	return 0;
}

2220
static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
2221 2222 2223 2224 2225 2226 2227 2228
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;

	if (!i915_pipe_enabled(dev, pipe))
		return -EINVAL;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2229 2230
	ironlake_enable_display_irq(dev_priv,
				    DE_PIPEA_VBLANK_IVB << (5 * pipe));
2231 2232 2233 2234 2235
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

	return 0;
}

J
Jesse Barnes 已提交
2236 2237 2238 2239
static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;
2240
	u32 imr;
J
Jesse Barnes 已提交
2241 2242 2243 2244 2245 2246

	if (!i915_pipe_enabled(dev, pipe))
		return -EINVAL;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
	imr = I915_READ(VLV_IMR);
2247
	if (pipe == 0)
J
Jesse Barnes 已提交
2248
		imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
2249
	else
J
Jesse Barnes 已提交
2250 2251
		imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
	I915_WRITE(VLV_IMR, imr);
2252 2253
	i915_enable_pipestat(dev_priv, pipe,
			     PIPE_START_VBLANK_INTERRUPT_ENABLE);
J
Jesse Barnes 已提交
2254 2255 2256 2257 2258
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

	return 0;
}

2259 2260 2261
/* Called from drm generic code, passed 'crtc' which
 * we use as a pipe index
 */
2262
static void i915_disable_vblank(struct drm_device *dev, int pipe)
2263 2264
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2265
	unsigned long irqflags;
2266

2267
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2268
	if (dev_priv->info->gen == 3)
2269
		I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
2270

2271 2272 2273 2274 2275 2276
	i915_disable_pipestat(dev_priv, pipe,
			      PIPE_VBLANK_INTERRUPT_ENABLE |
			      PIPE_START_VBLANK_INTERRUPT_ENABLE);
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

2277
static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2278 2279 2280 2281 2282 2283
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
	ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
2284
				     DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
2285
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2286 2287
}

2288
static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
2289 2290 2291 2292 2293
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2294 2295
	ironlake_disable_display_irq(dev_priv,
				     DE_PIPEA_VBLANK_IVB << (pipe * 5));
2296 2297 2298
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

J
Jesse Barnes 已提交
2299 2300 2301 2302
static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;
2303
	u32 imr;
J
Jesse Barnes 已提交
2304 2305

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2306 2307
	i915_disable_pipestat(dev_priv, pipe,
			      PIPE_START_VBLANK_INTERRUPT_ENABLE);
J
Jesse Barnes 已提交
2308
	imr = I915_READ(VLV_IMR);
2309
	if (pipe == 0)
J
Jesse Barnes 已提交
2310
		imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
2311
	else
J
Jesse Barnes 已提交
2312 2313 2314 2315 2316
		imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
	I915_WRITE(VLV_IMR, imr);
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

2317 2318
static u32
ring_last_seqno(struct intel_ring_buffer *ring)
2319
{
2320 2321 2322 2323
	return list_entry(ring->request_list.prev,
			  struct drm_i915_gem_request, list)->seqno;
}

2324 2325 2326 2327 2328
static bool
ring_idle(struct intel_ring_buffer *ring, u32 seqno)
{
	return (list_empty(&ring->request_list) ||
		i915_seqno_passed(seqno, ring_last_seqno(ring)));
B
Ben Gamari 已提交
2329 2330
}

2331 2332
static struct intel_ring_buffer *
semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
2333 2334
{
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
2335
	u32 cmd, ipehr, acthd, acthd_min;
2336 2337 2338 2339

	ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
	if ((ipehr & ~(0x3 << 16)) !=
	    (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
2340
		return NULL;
2341 2342 2343 2344

	/* ACTHD is likely pointing to the dword after the actual command,
	 * so scan backwards until we find the MBOX.
	 */
2345
	acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
2346 2347 2348 2349 2350 2351 2352 2353
	acthd_min = max((int)acthd - 3 * 4, 0);
	do {
		cmd = ioread32(ring->virtual_start + acthd);
		if (cmd == ipehr)
			break;

		acthd -= 4;
		if (acthd < acthd_min)
2354
			return NULL;
2355 2356
	} while (1);

2357 2358
	*seqno = ioread32(ring->virtual_start+acthd+4)+1;
	return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
2359 2360
}

2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389
static int semaphore_passed(struct intel_ring_buffer *ring)
{
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
	struct intel_ring_buffer *signaller;
	u32 seqno, ctl;

	ring->hangcheck.deadlock = true;

	signaller = semaphore_waits_for(ring, &seqno);
	if (signaller == NULL || signaller->hangcheck.deadlock)
		return -1;

	/* cursory check for an unkickable deadlock */
	ctl = I915_READ_CTL(signaller);
	if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
		return -1;

	return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
}

static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
{
	struct intel_ring_buffer *ring;
	int i;

	for_each_ring(ring, dev_priv, i)
		ring->hangcheck.deadlock = false;
}

2390 2391
static enum intel_ring_hangcheck_action
ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
2392 2393 2394
{
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2395 2396
	u32 tmp;

2397 2398 2399
	if (ring->hangcheck.acthd != acthd)
		return active;

2400
	if (IS_GEN2(dev))
2401
		return hung;
2402 2403 2404 2405 2406 2407 2408

	/* Is the chip hanging on a WAIT_FOR_EVENT?
	 * If so we can simply poke the RB_WAIT bit
	 * and break the hang. This should work on
	 * all but the second generation chipsets.
	 */
	tmp = I915_READ_CTL(ring);
2409 2410 2411 2412
	if (tmp & RING_WAIT) {
		DRM_ERROR("Kicking stuck wait on %s\n",
			  ring->name);
		I915_WRITE_CTL(ring, tmp);
2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427
		return kick;
	}

	if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
		switch (semaphore_passed(ring)) {
		default:
			return hung;
		case 1:
			DRM_ERROR("Kicking stuck semaphore on %s\n",
				  ring->name);
			I915_WRITE_CTL(ring, tmp);
			return kick;
		case 0:
			return wait;
		}
2428
	}
2429

2430
	return hung;
2431 2432
}

B
Ben Gamari 已提交
2433 2434
/**
 * This is called when the chip hasn't reported back with completed
2435 2436 2437 2438 2439
 * batchbuffers in a long time. We keep track per ring seqno progress and
 * if there are no progress, hangcheck score for that ring is increased.
 * Further, acthd is inspected to see if the ring is stuck. On stuck case
 * we kick the ring. If we see no progress on three subsequent calls
 * we assume chip is wedged and try to fix it by resetting the chip.
B
Ben Gamari 已提交
2440 2441 2442 2443 2444
 */
void i915_hangcheck_elapsed(unsigned long data)
{
	struct drm_device *dev = (struct drm_device *)data;
	drm_i915_private_t *dev_priv = dev->dev_private;
2445 2446
	struct intel_ring_buffer *ring;
	int i;
2447
	int busy_count = 0, rings_hung = 0;
2448 2449 2450 2451 2452
	bool stuck[I915_NUM_RINGS] = { 0 };
#define BUSY 1
#define KICK 5
#define HUNG 20
#define FIRE 30
2453

2454 2455 2456
	if (!i915_enable_hangcheck)
		return;

2457
	for_each_ring(ring, dev_priv, i) {
2458
		u32 seqno, acthd;
2459
		bool busy = true;
2460

2461 2462
		semaphore_clear_deadlocks(dev_priv);

2463 2464
		seqno = ring->get_seqno(ring, false);
		acthd = intel_ring_get_active_head(ring);
2465

2466 2467 2468 2469 2470 2471 2472 2473 2474 2475
		if (ring->hangcheck.seqno == seqno) {
			if (ring_idle(ring, seqno)) {
				if (waitqueue_active(&ring->irq_queue)) {
					/* Issue a wake-up to catch stuck h/w. */
					DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
						  ring->name);
					wake_up_all(&ring->irq_queue);
					ring->hangcheck.score += HUNG;
				} else
					busy = false;
2476
			} else {
2477 2478
				int score;

2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493
				/* We always increment the hangcheck score
				 * if the ring is busy and still processing
				 * the same request, so that no single request
				 * can run indefinitely (such as a chain of
				 * batches). The only time we do not increment
				 * the hangcheck score on this ring, if this
				 * ring is in a legitimate wait for another
				 * ring. In that case the waiting ring is a
				 * victim and we want to be sure we catch the
				 * right culprit. Then every time we do kick
				 * the ring, add a small increment to the
				 * score so that we can catch a batch that is
				 * being repeatedly kicked and so responsible
				 * for stalling the machine.
				 */
2494 2495 2496 2497
				ring->hangcheck.action = ring_stuck(ring,
								    acthd);

				switch (ring->hangcheck.action) {
2498 2499 2500 2501
				case wait:
					score = 0;
					break;
				case active:
2502
					score = BUSY;
2503 2504 2505 2506 2507 2508 2509 2510 2511
					break;
				case kick:
					score = KICK;
					break;
				case hung:
					score = HUNG;
					stuck[i] = true;
					break;
				}
2512
				ring->hangcheck.score += score;
2513
			}
2514 2515 2516 2517 2518 2519
		} else {
			/* Gradually reduce the count so that we catch DoS
			 * attempts across multiple batches.
			 */
			if (ring->hangcheck.score > 0)
				ring->hangcheck.score--;
2520 2521
		}

2522 2523
		ring->hangcheck.seqno = seqno;
		ring->hangcheck.acthd = acthd;
2524
		busy_count += busy;
2525
	}
2526

2527
	for_each_ring(ring, dev_priv, i) {
2528
		if (ring->hangcheck.score > FIRE) {
2529
			DRM_ERROR("%s on %s\n",
2530
				  stuck[i] ? "stuck" : "no progress",
2531 2532
				  ring->name);
			rings_hung++;
2533 2534 2535
		}
	}

2536 2537
	if (rings_hung)
		return i915_handle_error(dev, true);
B
Ben Gamari 已提交
2538

2539 2540 2541 2542 2543 2544
	if (busy_count)
		/* Reset timer case chip hangs without another request
		 * being added */
		mod_timer(&dev_priv->gpu_error.hangcheck_timer,
			  round_jiffies_up(jiffies +
					   DRM_I915_HANGCHECK_JIFFIES));
B
Ben Gamari 已提交
2545 2546
}

P
Paulo Zanoni 已提交
2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565
static void ibx_irq_preinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (HAS_PCH_NOP(dev))
		return;

	/* south display irq */
	I915_WRITE(SDEIMR, 0xffffffff);
	/*
	 * SDEIER is also touched by the interrupt handler to work around missed
	 * PCH interrupts. Hence we can't update it after the interrupt handler
	 * is enabled - instead we unconditionally enable all PCH interrupt
	 * sources here, but then only unmask them as needed with SDEIMR.
	 */
	I915_WRITE(SDEIER, 0xffffffff);
	POSTING_READ(SDEIER);
}

L
Linus Torvalds 已提交
2566 2567
/* drm_dma.h hooks
*/
2568
static void ironlake_irq_preinstall(struct drm_device *dev)
2569 2570 2571
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;

2572 2573
	atomic_set(&dev_priv->irq_received, 0);

2574
	I915_WRITE(HWSTAM, 0xeffe);
2575

2576 2577 2578 2579
	/* XXX hotplug from PCH */

	I915_WRITE(DEIMR, 0xffffffff);
	I915_WRITE(DEIER, 0x0);
2580
	POSTING_READ(DEIER);
2581 2582 2583 2584

	/* and GT */
	I915_WRITE(GTIMR, 0xffffffff);
	I915_WRITE(GTIER, 0x0);
2585
	POSTING_READ(GTIER);
2586

P
Paulo Zanoni 已提交
2587
	ibx_irq_preinstall(dev);
2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608
}

static void ivybridge_irq_preinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;

	atomic_set(&dev_priv->irq_received, 0);

	I915_WRITE(HWSTAM, 0xeffe);

	/* XXX hotplug from PCH */

	I915_WRITE(DEIMR, 0xffffffff);
	I915_WRITE(DEIER, 0x0);
	POSTING_READ(DEIER);

	/* and GT */
	I915_WRITE(GTIMR, 0xffffffff);
	I915_WRITE(GTIER, 0x0);
	POSTING_READ(GTIER);

2609 2610 2611 2612 2613
	/* Power management */
	I915_WRITE(GEN6_PMIMR, 0xffffffff);
	I915_WRITE(GEN6_PMIER, 0x0);
	POSTING_READ(GEN6_PMIER);

P
Paulo Zanoni 已提交
2614
	ibx_irq_preinstall(dev);
2615 2616
}

J
Jesse Barnes 已提交
2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648
static void valleyview_irq_preinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;

	atomic_set(&dev_priv->irq_received, 0);

	/* VLV magic */
	I915_WRITE(VLV_IMR, 0);
	I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
	I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
	I915_WRITE(RING_IMR(BLT_RING_BASE), 0);

	/* and GT */
	I915_WRITE(GTIIR, I915_READ(GTIIR));
	I915_WRITE(GTIIR, I915_READ(GTIIR));
	I915_WRITE(GTIMR, 0xffffffff);
	I915_WRITE(GTIER, 0x0);
	POSTING_READ(GTIER);

	I915_WRITE(DPINVGTT, 0xff);

	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0xffff);
	I915_WRITE(VLV_IIR, 0xffffffff);
	I915_WRITE(VLV_IMR, 0xffffffff);
	I915_WRITE(VLV_IER, 0x0);
	POSTING_READ(VLV_IER);
}

2649
static void ibx_hpd_irq_setup(struct drm_device *dev)
2650 2651
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2652 2653 2654 2655 2656 2657
	struct drm_mode_config *mode_config = &dev->mode_config;
	struct intel_encoder *intel_encoder;
	u32 mask = ~I915_READ(SDEIMR);
	u32 hotplug;

	if (HAS_PCH_IBX(dev)) {
2658
		mask &= ~SDE_HOTPLUG_MASK;
2659
		list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2660 2661
			if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
				mask |= hpd_ibx[intel_encoder->hpd_pin];
2662
	} else {
2663
		mask &= ~SDE_HOTPLUG_MASK_CPT;
2664
		list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2665 2666
			if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
				mask |= hpd_cpt[intel_encoder->hpd_pin];
2667
	}
2668

2669 2670 2671 2672 2673 2674 2675 2676
	I915_WRITE(SDEIMR, ~mask);

	/*
	 * Enable digital hotplug on the PCH, and configure the DP short pulse
	 * duration to 2ms (which is the minimum in the Display Port spec)
	 *
	 * This register is the same on all known PCH chips.
	 */
2677 2678 2679 2680 2681 2682 2683 2684
	hotplug = I915_READ(PCH_PORT_HOTPLUG);
	hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
	hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
	hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
	hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
}

P
Paulo Zanoni 已提交
2685 2686 2687
static void ibx_irq_postinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2688
	u32 mask;
2689

D
Daniel Vetter 已提交
2690 2691 2692
	if (HAS_PCH_NOP(dev))
		return;

2693 2694
	if (HAS_PCH_IBX(dev)) {
		mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
2695
		       SDE_TRANSA_FIFO_UNDER | SDE_POISON;
2696 2697 2698 2699 2700
	} else {
		mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;

		I915_WRITE(SERR_INT, I915_READ(SERR_INT));
	}
2701

P
Paulo Zanoni 已提交
2702 2703 2704 2705
	I915_WRITE(SDEIIR, I915_READ(SDEIIR));
	I915_WRITE(SDEIMR, ~mask);
}

2706
static int ironlake_irq_postinstall(struct drm_device *dev)
2707
{
2708 2709
	unsigned long irqflags;

2710 2711
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	/* enable kind of interrupts always enabled */
2712
	u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2713
			   DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
2714
			   DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
2715
			   DE_PIPEA_FIFO_UNDERRUN | DE_POISON;
2716
	u32 gt_irqs;
2717

2718
	dev_priv->irq_mask = ~display_mask;
2719 2720 2721

	/* should always can generate irq */
	I915_WRITE(DEIIR, I915_READ(DEIIR));
2722
	I915_WRITE(DEIMR, dev_priv->irq_mask);
2723 2724
	I915_WRITE(DEIER, display_mask |
			  DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT);
2725
	POSTING_READ(DEIER);
2726

2727
	dev_priv->gt_irq_mask = ~0;
2728 2729

	I915_WRITE(GTIIR, I915_READ(GTIIR));
2730
	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2731

2732 2733
	gt_irqs = GT_RENDER_USER_INTERRUPT;

2734
	if (IS_GEN6(dev))
2735
		gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
2736
	else
2737 2738 2739 2740
		gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
			   ILK_BSD_USER_INTERRUPT;

	I915_WRITE(GTIER, gt_irqs);
2741
	POSTING_READ(GTIER);
2742

P
Paulo Zanoni 已提交
2743
	ibx_irq_postinstall(dev);
2744

2745
	if (IS_IRONLAKE_M(dev)) {
2746 2747 2748
		/* Enable PCU event interrupts
		 *
		 * spinlocking not required here for correctness since interrupt
2749 2750 2751
		 * setup is guaranteed to run in single-threaded context. But we
		 * need it to make the assert_spin_locked happy. */
		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2752
		ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2753
		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2754 2755
	}

2756 2757 2758
	return 0;
}

2759
static int ivybridge_irq_postinstall(struct drm_device *dev)
2760 2761 2762
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	/* enable kind of interrupts always enabled */
2763 2764 2765 2766
	u32 display_mask =
		DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
		DE_PLANEC_FLIP_DONE_IVB |
		DE_PLANEB_FLIP_DONE_IVB |
2767
		DE_PLANEA_FLIP_DONE_IVB |
2768 2769
		DE_AUX_CHANNEL_A_IVB |
		DE_ERR_INT_IVB;
B
Ben Widawsky 已提交
2770
	u32 pm_irqs = GEN6_PM_RPS_EVENTS;
2771
	u32 gt_irqs;
2772 2773 2774 2775

	dev_priv->irq_mask = ~display_mask;

	/* should always can generate irq */
2776
	I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2777 2778
	I915_WRITE(DEIIR, I915_READ(DEIIR));
	I915_WRITE(DEIMR, dev_priv->irq_mask);
2779 2780 2781 2782 2783
	I915_WRITE(DEIER,
		   display_mask |
		   DE_PIPEC_VBLANK_IVB |
		   DE_PIPEB_VBLANK_IVB |
		   DE_PIPEA_VBLANK_IVB);
2784 2785
	POSTING_READ(DEIER);

2786
	dev_priv->gt_irq_mask = ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2787 2788 2789 2790

	I915_WRITE(GTIIR, I915_READ(GTIIR));
	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);

2791 2792 2793
	gt_irqs = GT_RENDER_USER_INTERRUPT | GT_BSD_USER_INTERRUPT |
		  GT_BLT_USER_INTERRUPT | GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
	I915_WRITE(GTIER, gt_irqs);
2794 2795
	POSTING_READ(GTIER);

B
Ben Widawsky 已提交
2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810
	I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
	if (HAS_VEBOX(dev))
		pm_irqs |= PM_VEBOX_USER_INTERRUPT |
			PM_VEBOX_CS_ERROR_INTERRUPT;

	/* Our enable/disable rps functions may touch these registers so
	 * make sure to set a known state for only the non-RPS bits.
	 * The RMW is extra paranoia since this should be called after being set
	 * to a known state in preinstall.
	 * */
	I915_WRITE(GEN6_PMIMR,
		   (I915_READ(GEN6_PMIMR) | ~GEN6_PM_RPS_EVENTS) & ~pm_irqs);
	I915_WRITE(GEN6_PMIER,
		   (I915_READ(GEN6_PMIER) & GEN6_PM_RPS_EVENTS) | pm_irqs);
	POSTING_READ(GEN6_PMIER);
2811

P
Paulo Zanoni 已提交
2812
	ibx_irq_postinstall(dev);
2813

2814 2815 2816
	return 0;
}

J
Jesse Barnes 已提交
2817 2818 2819
static int valleyview_irq_postinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2820
	u32 gt_irqs;
J
Jesse Barnes 已提交
2821
	u32 enable_mask;
2822
	u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
J
Jesse Barnes 已提交
2823 2824

	enable_mask = I915_DISPLAY_PORT_INTERRUPT;
2825 2826 2827
	enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
J
Jesse Barnes 已提交
2828 2829
		I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;

2830 2831 2832 2833 2834 2835 2836
	/*
	 *Leave vblank interrupts masked initially.  enable/disable will
	 * toggle them based on usage.
	 */
	dev_priv->irq_mask = (~enable_mask) |
		I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
		I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
J
Jesse Barnes 已提交
2837

2838 2839 2840
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	POSTING_READ(PORT_HOTPLUG_EN);

J
Jesse Barnes 已提交
2841 2842 2843 2844 2845 2846 2847
	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
	I915_WRITE(VLV_IER, enable_mask);
	I915_WRITE(VLV_IIR, 0xffffffff);
	I915_WRITE(PIPESTAT(0), 0xffff);
	I915_WRITE(PIPESTAT(1), 0xffff);
	POSTING_READ(VLV_IER);

2848
	i915_enable_pipestat(dev_priv, 0, pipestat_enable);
2849
	i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
2850 2851
	i915_enable_pipestat(dev_priv, 1, pipestat_enable);

J
Jesse Barnes 已提交
2852 2853 2854 2855
	I915_WRITE(VLV_IIR, 0xffffffff);
	I915_WRITE(VLV_IIR, 0xffffffff);

	I915_WRITE(GTIIR, I915_READ(GTIIR));
2856
	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2857

2858 2859 2860
	gt_irqs = GT_RENDER_USER_INTERRUPT | GT_BSD_USER_INTERRUPT |
		GT_BLT_USER_INTERRUPT;
	I915_WRITE(GTIER, gt_irqs);
J
Jesse Barnes 已提交
2861 2862 2863 2864 2865 2866 2867 2868 2869
	POSTING_READ(GTIER);

	/* ack & enable invalid PTE error interrupts */
#if 0 /* FIXME: add support to irq handler for checking these bits */
	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
	I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
#endif

	I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2870 2871 2872 2873

	return 0;
}

J
Jesse Barnes 已提交
2874 2875 2876 2877 2878 2879 2880 2881
static void valleyview_irq_uninstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;

	if (!dev_priv)
		return;

2882 2883
	del_timer_sync(&dev_priv->hotplug_reenable_timer);

J
Jesse Barnes 已提交
2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0xffff);

	I915_WRITE(HWSTAM, 0xffffffff);
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0xffff);
	I915_WRITE(VLV_IIR, 0xffffffff);
	I915_WRITE(VLV_IMR, 0xffffffff);
	I915_WRITE(VLV_IER, 0x0);
	POSTING_READ(VLV_IER);
}

2898
static void ironlake_irq_uninstall(struct drm_device *dev)
2899 2900
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2901 2902 2903 2904

	if (!dev_priv)
		return;

2905 2906
	del_timer_sync(&dev_priv->hotplug_reenable_timer);

2907 2908 2909 2910 2911
	I915_WRITE(HWSTAM, 0xffffffff);

	I915_WRITE(DEIMR, 0xffffffff);
	I915_WRITE(DEIER, 0x0);
	I915_WRITE(DEIIR, I915_READ(DEIIR));
2912 2913
	if (IS_GEN7(dev))
		I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2914 2915 2916 2917

	I915_WRITE(GTIMR, 0xffffffff);
	I915_WRITE(GTIER, 0x0);
	I915_WRITE(GTIIR, I915_READ(GTIIR));
2918

2919 2920 2921
	if (HAS_PCH_NOP(dev))
		return;

2922 2923 2924
	I915_WRITE(SDEIMR, 0xffffffff);
	I915_WRITE(SDEIER, 0x0);
	I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2925 2926
	if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
		I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2927 2928
}

2929
static void i8xx_irq_preinstall(struct drm_device * dev)
L
Linus Torvalds 已提交
2930 2931
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2932
	int pipe;
2933

2934
	atomic_set(&dev_priv->irq_received, 0);
2935

2936 2937
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0);
2938 2939 2940
	I915_WRITE16(IMR, 0xffff);
	I915_WRITE16(IER, 0x0);
	POSTING_READ16(IER);
C
Chris Wilson 已提交
2941 2942 2943 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 2956 2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968
}

static int i8xx_irq_postinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;

	I915_WRITE16(EMR,
		     ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));

	/* Unmask the interrupts that we always want on. */
	dev_priv->irq_mask =
		~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
		  I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
	I915_WRITE16(IMR, dev_priv->irq_mask);

	I915_WRITE16(IER,
		     I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		     I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		     I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
		     I915_USER_INTERRUPT);
	POSTING_READ16(IER);

	return 0;
}

2969 2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991 2992 2993 2994 2995 2996 2997 2998 2999
/*
 * Returns true when a page flip has completed.
 */
static bool i8xx_handle_vblank(struct drm_device *dev,
			       int pipe, u16 iir)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);

	if (!drm_handle_vblank(dev, pipe))
		return false;

	if ((iir & flip_pending) == 0)
		return false;

	intel_prepare_page_flip(dev, pipe);

	/* We detect FlipDone by looking for the change in PendingFlip from '1'
	 * to '0' on the following vblank, i.e. IIR has the Pendingflip
	 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
	 * the flip is completed (no longer pending). Since this doesn't raise
	 * an interrupt per se, we watch for the change at vblank.
	 */
	if (I915_READ16(ISR) & flip_pending)
		return false;

	intel_finish_page_flip(dev, pipe);

	return true;
}

3000
static irqreturn_t i8xx_irq_handler(int irq, void *arg)
C
Chris Wilson 已提交
3001 3002 3003 3004 3005 3006 3007 3008 3009 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 3027 3028 3029 3030 3031 3032 3033 3034 3035 3036 3037 3038 3039 3040 3041 3042 3043 3044 3045 3046 3047 3048
{
	struct drm_device *dev = (struct drm_device *) arg;
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u16 iir, new_iir;
	u32 pipe_stats[2];
	unsigned long irqflags;
	int irq_received;
	int pipe;
	u16 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;

	atomic_inc(&dev_priv->irq_received);

	iir = I915_READ16(IIR);
	if (iir == 0)
		return IRQ_NONE;

	while (iir & ~flip_mask) {
		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
			i915_handle_error(dev, false);

		for_each_pipe(pipe) {
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);

			/*
			 * Clear the PIPE*STAT regs before the IIR
			 */
			if (pipe_stats[pipe] & 0x8000ffff) {
				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
					DRM_DEBUG_DRIVER("pipe %c underrun\n",
							 pipe_name(pipe));
				I915_WRITE(reg, pipe_stats[pipe]);
				irq_received = 1;
			}
		}
		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

		I915_WRITE16(IIR, iir & ~flip_mask);
		new_iir = I915_READ16(IIR); /* Flush posted writes */

3049
		i915_update_dri1_breadcrumb(dev);
C
Chris Wilson 已提交
3050 3051 3052 3053 3054

		if (iir & I915_USER_INTERRUPT)
			notify_ring(dev, &dev_priv->ring[RCS]);

		if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
3055 3056
		    i8xx_handle_vblank(dev, 0, iir))
			flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
C
Chris Wilson 已提交
3057 3058

		if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
3059 3060
		    i8xx_handle_vblank(dev, 1, iir))
			flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
C
Chris Wilson 已提交
3061 3062 3063 3064 3065 3066 3067 3068 3069 3070 3071 3072 3073 3074 3075 3076 3077 3078 3079 3080 3081 3082

		iir = new_iir;
	}

	return IRQ_HANDLED;
}

static void i8xx_irq_uninstall(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;

	for_each_pipe(pipe) {
		/* Clear enable bits; then clear status bits */
		I915_WRITE(PIPESTAT(pipe), 0);
		I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
	}
	I915_WRITE16(IMR, 0xffff);
	I915_WRITE16(IER, 0x0);
	I915_WRITE16(IIR, I915_READ16(IIR));
}

3083 3084 3085 3086 3087 3088 3089 3090 3091 3092 3093 3094
static void i915_irq_preinstall(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;

	atomic_set(&dev_priv->irq_received, 0);

	if (I915_HAS_HOTPLUG(dev)) {
		I915_WRITE(PORT_HOTPLUG_EN, 0);
		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	}

3095
	I915_WRITE16(HWSTAM, 0xeffe);
3096 3097 3098 3099 3100 3101 3102 3103 3104 3105
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);
	POSTING_READ(IER);
}

static int i915_irq_postinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3106
	u32 enable_mask;
3107

3108 3109 3110 3111 3112 3113 3114 3115 3116 3117 3118 3119 3120 3121 3122 3123 3124 3125
	I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));

	/* Unmask the interrupts that we always want on. */
	dev_priv->irq_mask =
		~(I915_ASLE_INTERRUPT |
		  I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
		  I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);

	enable_mask =
		I915_ASLE_INTERRUPT |
		I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
		I915_USER_INTERRUPT;

3126
	if (I915_HAS_HOTPLUG(dev)) {
3127 3128 3129
		I915_WRITE(PORT_HOTPLUG_EN, 0);
		POSTING_READ(PORT_HOTPLUG_EN);

3130 3131 3132 3133 3134 3135 3136 3137 3138 3139
		/* Enable in IER... */
		enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
		/* and unmask in IMR */
		dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
	}

	I915_WRITE(IMR, dev_priv->irq_mask);
	I915_WRITE(IER, enable_mask);
	POSTING_READ(IER);

3140
	i915_enable_asle_pipestat(dev);
3141 3142 3143 3144

	return 0;
}

3145 3146 3147 3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167 3168 3169 3170 3171 3172 3173 3174 3175
/*
 * Returns true when a page flip has completed.
 */
static bool i915_handle_vblank(struct drm_device *dev,
			       int plane, int pipe, u32 iir)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);

	if (!drm_handle_vblank(dev, pipe))
		return false;

	if ((iir & flip_pending) == 0)
		return false;

	intel_prepare_page_flip(dev, plane);

	/* We detect FlipDone by looking for the change in PendingFlip from '1'
	 * to '0' on the following vblank, i.e. IIR has the Pendingflip
	 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
	 * the flip is completed (no longer pending). Since this doesn't raise
	 * an interrupt per se, we watch for the change at vblank.
	 */
	if (I915_READ(ISR) & flip_pending)
		return false;

	intel_finish_page_flip(dev, pipe);

	return true;
}

3176
static irqreturn_t i915_irq_handler(int irq, void *arg)
3177 3178 3179
{
	struct drm_device *dev = (struct drm_device *) arg;
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3180
	u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3181
	unsigned long irqflags;
3182 3183 3184 3185
	u32 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
	int pipe, ret = IRQ_NONE;
3186 3187 3188 3189

	atomic_inc(&dev_priv->irq_received);

	iir = I915_READ(IIR);
3190 3191
	do {
		bool irq_received = (iir & ~flip_mask) != 0;
3192
		bool blc_event = false;
3193 3194 3195 3196 3197 3198 3199 3200 3201 3202 3203 3204 3205 3206

		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
			i915_handle_error(dev, false);

		for_each_pipe(pipe) {
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);

3207
			/* Clear the PIPE*STAT regs before the IIR */
3208 3209 3210 3211 3212
			if (pipe_stats[pipe] & 0x8000ffff) {
				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
					DRM_DEBUG_DRIVER("pipe %c underrun\n",
							 pipe_name(pipe));
				I915_WRITE(reg, pipe_stats[pipe]);
3213
				irq_received = true;
3214 3215 3216 3217 3218 3219 3220 3221 3222 3223 3224
			}
		}
		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

		if (!irq_received)
			break;

		/* Consume port.  Then clear IIR or we'll miss events */
		if ((I915_HAS_HOTPLUG(dev)) &&
		    (iir & I915_DISPLAY_PORT_INTERRUPT)) {
			u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3225
			u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
3226 3227 3228

			DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
				  hotplug_status);
3229 3230 3231

			intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);

3232
			I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3233
			POSTING_READ(PORT_HOTPLUG_STAT);
3234 3235
		}

3236
		I915_WRITE(IIR, iir & ~flip_mask);
3237 3238 3239 3240 3241 3242
		new_iir = I915_READ(IIR); /* Flush posted writes */

		if (iir & I915_USER_INTERRUPT)
			notify_ring(dev, &dev_priv->ring[RCS]);

		for_each_pipe(pipe) {
3243 3244 3245
			int plane = pipe;
			if (IS_MOBILE(dev))
				plane = !plane;
3246

3247
			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3248 3249
			    i915_handle_vblank(dev, plane, pipe, iir))
				flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260 3261 3262 3263 3264 3265 3266 3267 3268 3269 3270 3271 3272

			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
				blc_event = true;
		}

		if (blc_event || (iir & I915_ASLE_INTERRUPT))
			intel_opregion_asle_intr(dev);

		/* With MSI, interrupts are only generated when iir
		 * transitions from zero to nonzero.  If another bit got
		 * set while we were handling the existing iir bits, then
		 * we would never get another interrupt.
		 *
		 * This is fine on non-MSI as well, as if we hit this path
		 * we avoid exiting the interrupt handler only to generate
		 * another one.
		 *
		 * Note that for MSI this could cause a stray interrupt report
		 * if an interrupt landed in the time between writing IIR and
		 * the posting read.  This should be rare enough to never
		 * trigger the 99% of 100,000 interrupts test for disabling
		 * stray interrupts.
		 */
3273
		ret = IRQ_HANDLED;
3274
		iir = new_iir;
3275
	} while (iir & ~flip_mask);
3276

3277
	i915_update_dri1_breadcrumb(dev);
3278

3279 3280 3281 3282 3283 3284 3285 3286
	return ret;
}

static void i915_irq_uninstall(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;

3287 3288
	del_timer_sync(&dev_priv->hotplug_reenable_timer);

3289 3290 3291 3292 3293
	if (I915_HAS_HOTPLUG(dev)) {
		I915_WRITE(PORT_HOTPLUG_EN, 0);
		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	}

3294
	I915_WRITE16(HWSTAM, 0xffff);
3295 3296
	for_each_pipe(pipe) {
		/* Clear enable bits; then clear status bits */
3297
		I915_WRITE(PIPESTAT(pipe), 0);
3298 3299
		I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
	}
3300 3301 3302 3303 3304 3305 3306 3307 3308 3309 3310 3311 3312
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);

	I915_WRITE(IIR, I915_READ(IIR));
}

static void i965_irq_preinstall(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;

	atomic_set(&dev_priv->irq_received, 0);

3313 3314
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3315 3316 3317 3318 3319 3320 3321 3322 3323 3324 3325 3326

	I915_WRITE(HWSTAM, 0xeffe);
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);
	POSTING_READ(IER);
}

static int i965_irq_postinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3327
	u32 enable_mask;
3328 3329 3330
	u32 error_mask;

	/* Unmask the interrupts that we always want on. */
3331
	dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
3332
			       I915_DISPLAY_PORT_INTERRUPT |
3333 3334 3335 3336 3337 3338 3339
			       I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
			       I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
			       I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
			       I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
			       I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);

	enable_mask = ~dev_priv->irq_mask;
3340 3341
	enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
			 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3342 3343 3344 3345
	enable_mask |= I915_USER_INTERRUPT;

	if (IS_G4X(dev))
		enable_mask |= I915_BSD_USER_INTERRUPT;
3346

3347
	i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
3348 3349 3350 3351 3352 3353 3354 3355 3356 3357 3358 3359 3360 3361 3362 3363 3364 3365 3366 3367

	/*
	 * Enable some error detection, note the instruction error mask
	 * bit is reserved, so we leave it masked.
	 */
	if (IS_G4X(dev)) {
		error_mask = ~(GM45_ERROR_PAGE_TABLE |
			       GM45_ERROR_MEM_PRIV |
			       GM45_ERROR_CP_PRIV |
			       I915_ERROR_MEMORY_REFRESH);
	} else {
		error_mask = ~(I915_ERROR_PAGE_TABLE |
			       I915_ERROR_MEMORY_REFRESH);
	}
	I915_WRITE(EMR, error_mask);

	I915_WRITE(IMR, dev_priv->irq_mask);
	I915_WRITE(IER, enable_mask);
	POSTING_READ(IER);

3368 3369 3370
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	POSTING_READ(PORT_HOTPLUG_EN);

3371
	i915_enable_asle_pipestat(dev);
3372 3373 3374 3375

	return 0;
}

3376
static void i915_hpd_irq_setup(struct drm_device *dev)
3377 3378
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3379
	struct drm_mode_config *mode_config = &dev->mode_config;
3380
	struct intel_encoder *intel_encoder;
3381 3382
	u32 hotplug_en;

3383 3384 3385 3386
	if (I915_HAS_HOTPLUG(dev)) {
		hotplug_en = I915_READ(PORT_HOTPLUG_EN);
		hotplug_en &= ~HOTPLUG_INT_EN_MASK;
		/* Note HDMI and DP share hotplug bits */
3387
		/* enable bits are the same for all generations */
3388 3389 3390
		list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
			if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
				hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
3391 3392 3393 3394 3395 3396
		/* Programming the CRT detection parameters tends
		   to generate a spurious hotplug event about three
		   seconds later.  So just do it once.
		*/
		if (IS_G4X(dev))
			hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
3397
		hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
3398
		hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
3399

3400 3401 3402
		/* Ignore TV since it's buggy */
		I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
	}
3403 3404
}

3405
static irqreturn_t i965_irq_handler(int irq, void *arg)
3406 3407 3408 3409 3410 3411 3412 3413
{
	struct drm_device *dev = (struct drm_device *) arg;
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u32 iir, new_iir;
	u32 pipe_stats[I915_MAX_PIPES];
	unsigned long irqflags;
	int irq_received;
	int ret = IRQ_NONE, pipe;
3414 3415 3416
	u32 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3417 3418 3419 3420 3421 3422

	atomic_inc(&dev_priv->irq_received);

	iir = I915_READ(IIR);

	for (;;) {
3423 3424
		bool blc_event = false;

3425
		irq_received = (iir & ~flip_mask) != 0;
3426 3427 3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438 3439 3440 3441 3442 3443 3444 3445 3446 3447 3448 3449 3450 3451 3452 3453 3454 3455 3456 3457 3458

		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
			i915_handle_error(dev, false);

		for_each_pipe(pipe) {
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);

			/*
			 * Clear the PIPE*STAT regs before the IIR
			 */
			if (pipe_stats[pipe] & 0x8000ffff) {
				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
					DRM_DEBUG_DRIVER("pipe %c underrun\n",
							 pipe_name(pipe));
				I915_WRITE(reg, pipe_stats[pipe]);
				irq_received = 1;
			}
		}
		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

		if (!irq_received)
			break;

		ret = IRQ_HANDLED;

		/* Consume port.  Then clear IIR or we'll miss events */
3459
		if (iir & I915_DISPLAY_PORT_INTERRUPT) {
3460
			u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3461 3462
			u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
								  HOTPLUG_INT_STATUS_G4X :
3463
								  HOTPLUG_INT_STATUS_I915);
3464 3465 3466

			DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
				  hotplug_status);
3467 3468 3469 3470

			intel_hpd_irq_handler(dev, hotplug_trigger,
					      IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i915);

3471 3472 3473 3474
			I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
			I915_READ(PORT_HOTPLUG_STAT);
		}

3475
		I915_WRITE(IIR, iir & ~flip_mask);
3476 3477 3478 3479 3480 3481 3482 3483
		new_iir = I915_READ(IIR); /* Flush posted writes */

		if (iir & I915_USER_INTERRUPT)
			notify_ring(dev, &dev_priv->ring[RCS]);
		if (iir & I915_BSD_USER_INTERRUPT)
			notify_ring(dev, &dev_priv->ring[VCS]);

		for_each_pipe(pipe) {
3484
			if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
3485 3486
			    i915_handle_vblank(dev, pipe, pipe, iir))
				flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
3487 3488 3489 3490 3491 3492 3493 3494 3495

			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
				blc_event = true;
		}


		if (blc_event || (iir & I915_ASLE_INTERRUPT))
			intel_opregion_asle_intr(dev);

3496 3497 3498
		if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
			gmbus_irq_handler(dev);

3499 3500 3501 3502 3503 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516
		/* With MSI, interrupts are only generated when iir
		 * transitions from zero to nonzero.  If another bit got
		 * set while we were handling the existing iir bits, then
		 * we would never get another interrupt.
		 *
		 * This is fine on non-MSI as well, as if we hit this path
		 * we avoid exiting the interrupt handler only to generate
		 * another one.
		 *
		 * Note that for MSI this could cause a stray interrupt report
		 * if an interrupt landed in the time between writing IIR and
		 * the posting read.  This should be rare enough to never
		 * trigger the 99% of 100,000 interrupts test for disabling
		 * stray interrupts.
		 */
		iir = new_iir;
	}

3517
	i915_update_dri1_breadcrumb(dev);
3518

3519 3520 3521 3522 3523 3524 3525 3526 3527 3528 3529
	return ret;
}

static void i965_irq_uninstall(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;

	if (!dev_priv)
		return;

3530 3531
	del_timer_sync(&dev_priv->hotplug_reenable_timer);

3532 3533
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3534 3535 3536 3537 3538 3539 3540 3541 3542 3543 3544 3545 3546

	I915_WRITE(HWSTAM, 0xffffffff);
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);

	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe),
			   I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
	I915_WRITE(IIR, I915_READ(IIR));
}

3547 3548 3549 3550 3551 3552 3553 3554 3555 3556 3557 3558 3559 3560 3561 3562 3563 3564 3565 3566 3567 3568 3569 3570 3571 3572 3573 3574 3575 3576 3577 3578 3579 3580 3581
static void i915_reenable_hotplug_timer_func(unsigned long data)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
	struct drm_device *dev = dev_priv->dev;
	struct drm_mode_config *mode_config = &dev->mode_config;
	unsigned long irqflags;
	int i;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
	for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
		struct drm_connector *connector;

		if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
			continue;

		dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;

		list_for_each_entry(connector, &mode_config->connector_list, head) {
			struct intel_connector *intel_connector = to_intel_connector(connector);

			if (intel_connector->encoder->hpd_pin == i) {
				if (connector->polled != intel_connector->polled)
					DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
							 drm_get_connector_name(connector));
				connector->polled = intel_connector->polled;
				if (!connector->polled)
					connector->polled = DRM_CONNECTOR_POLL_HPD;
			}
		}
	}
	if (dev_priv->display.hpd_irq_setup)
		dev_priv->display.hpd_irq_setup(dev);
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

3582 3583
void intel_irq_init(struct drm_device *dev)
{
3584 3585 3586
	struct drm_i915_private *dev_priv = dev->dev_private;

	INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
3587
	INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
3588
	INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
3589
	INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
3590

3591 3592
	setup_timer(&dev_priv->gpu_error.hangcheck_timer,
		    i915_hangcheck_elapsed,
3593
		    (unsigned long) dev);
3594 3595
	setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
		    (unsigned long) dev_priv);
3596

3597
	pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
3598

3599 3600
	dev->driver->get_vblank_counter = i915_get_vblank_counter;
	dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
3601
	if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
3602 3603 3604 3605
		dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
		dev->driver->get_vblank_counter = gm45_get_vblank_counter;
	}

3606 3607 3608 3609
	if (drm_core_check_feature(dev, DRIVER_MODESET))
		dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
	else
		dev->driver->get_vblank_timestamp = NULL;
3610 3611
	dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;

J
Jesse Barnes 已提交
3612 3613 3614 3615 3616 3617 3618
	if (IS_VALLEYVIEW(dev)) {
		dev->driver->irq_handler = valleyview_irq_handler;
		dev->driver->irq_preinstall = valleyview_irq_preinstall;
		dev->driver->irq_postinstall = valleyview_irq_postinstall;
		dev->driver->irq_uninstall = valleyview_irq_uninstall;
		dev->driver->enable_vblank = valleyview_enable_vblank;
		dev->driver->disable_vblank = valleyview_disable_vblank;
3619
		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3620
	} else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
3621
		/* Share uninstall handlers with ILK/SNB */
3622
		dev->driver->irq_handler = ivybridge_irq_handler;
3623
		dev->driver->irq_preinstall = ivybridge_irq_preinstall;
3624 3625 3626 3627
		dev->driver->irq_postinstall = ivybridge_irq_postinstall;
		dev->driver->irq_uninstall = ironlake_irq_uninstall;
		dev->driver->enable_vblank = ivybridge_enable_vblank;
		dev->driver->disable_vblank = ivybridge_disable_vblank;
3628
		dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3629 3630 3631 3632 3633 3634 3635
	} else if (HAS_PCH_SPLIT(dev)) {
		dev->driver->irq_handler = ironlake_irq_handler;
		dev->driver->irq_preinstall = ironlake_irq_preinstall;
		dev->driver->irq_postinstall = ironlake_irq_postinstall;
		dev->driver->irq_uninstall = ironlake_irq_uninstall;
		dev->driver->enable_vblank = ironlake_enable_vblank;
		dev->driver->disable_vblank = ironlake_disable_vblank;
3636
		dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3637
	} else {
C
Chris Wilson 已提交
3638 3639 3640 3641 3642
		if (INTEL_INFO(dev)->gen == 2) {
			dev->driver->irq_preinstall = i8xx_irq_preinstall;
			dev->driver->irq_postinstall = i8xx_irq_postinstall;
			dev->driver->irq_handler = i8xx_irq_handler;
			dev->driver->irq_uninstall = i8xx_irq_uninstall;
3643 3644 3645 3646 3647
		} else if (INTEL_INFO(dev)->gen == 3) {
			dev->driver->irq_preinstall = i915_irq_preinstall;
			dev->driver->irq_postinstall = i915_irq_postinstall;
			dev->driver->irq_uninstall = i915_irq_uninstall;
			dev->driver->irq_handler = i915_irq_handler;
3648
			dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
C
Chris Wilson 已提交
3649
		} else {
3650 3651 3652 3653
			dev->driver->irq_preinstall = i965_irq_preinstall;
			dev->driver->irq_postinstall = i965_irq_postinstall;
			dev->driver->irq_uninstall = i965_irq_uninstall;
			dev->driver->irq_handler = i965_irq_handler;
3654
			dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
C
Chris Wilson 已提交
3655
		}
3656 3657 3658 3659
		dev->driver->enable_vblank = i915_enable_vblank;
		dev->driver->disable_vblank = i915_disable_vblank;
	}
}
3660 3661 3662 3663

void intel_hpd_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
3664 3665 3666
	struct drm_mode_config *mode_config = &dev->mode_config;
	struct drm_connector *connector;
	int i;
3667

3668 3669 3670 3671 3672 3673 3674 3675 3676 3677
	for (i = 1; i < HPD_NUM_PINS; i++) {
		dev_priv->hpd_stats[i].hpd_cnt = 0;
		dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
	}
	list_for_each_entry(connector, &mode_config->connector_list, head) {
		struct intel_connector *intel_connector = to_intel_connector(connector);
		connector->polled = intel_connector->polled;
		if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
			connector->polled = DRM_CONNECTOR_POLL_HPD;
	}
3678 3679 3680
	if (dev_priv->display.hpd_irq_setup)
		dev_priv->display.hpd_irq_setup(dev);
}