i915_irq.c 119.6 KB
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/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
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 */
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/*
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

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#include <linux/sysrq.h>
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#include <linux/slab.h>
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#include <linux/circ_buf.h>
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#include <drm/drmP.h>
#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#include "i915_trace.h"
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#include "intel_drv.h"
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/**
 * DOC: interrupt handling
 *
 * These functions provide the basic support for enabling and disabling the
 * interrupt handling support. There's a lot more functionality in i915_irq.c
 * and related files, but that will be described in separate chapters.
 */

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static const u32 hpd_ibx[HPD_NUM_PINS] = {
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	[HPD_CRT] = SDE_CRT_HOTPLUG,
	[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
	[HPD_PORT_B] = SDE_PORTB_HOTPLUG,
	[HPD_PORT_C] = SDE_PORTC_HOTPLUG,
	[HPD_PORT_D] = SDE_PORTD_HOTPLUG
};

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static const u32 hpd_cpt[HPD_NUM_PINS] = {
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	[HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
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	[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
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	[HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
	[HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
	[HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
};

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static const u32 hpd_spt[HPD_NUM_PINS] = {
	[HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
	[HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
	[HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
	[HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
};

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static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
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	[HPD_CRT] = CRT_HOTPLUG_INT_EN,
	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
	[HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
	[HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
	[HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
};

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static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
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	[HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
	[HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
	[HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
	[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
};

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static const u32 hpd_status_i915[HPD_NUM_PINS] = {
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	[HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
	[HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
	[HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
	[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
};

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/* BXT hpd list */
static const u32 hpd_bxt[HPD_NUM_PINS] = {
	[HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
	[HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
};

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/* IIR can theoretically queue up two events. Be paranoid. */
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#define GEN8_IRQ_RESET_NDX(type, which) do { \
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	I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
	POSTING_READ(GEN8_##type##_IMR(which)); \
	I915_WRITE(GEN8_##type##_IER(which), 0); \
	I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
	POSTING_READ(GEN8_##type##_IIR(which)); \
	I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
	POSTING_READ(GEN8_##type##_IIR(which)); \
} while (0)

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#define GEN5_IRQ_RESET(type) do { \
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	I915_WRITE(type##IMR, 0xffffffff); \
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	POSTING_READ(type##IMR); \
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	I915_WRITE(type##IER, 0); \
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	I915_WRITE(type##IIR, 0xffffffff); \
	POSTING_READ(type##IIR); \
	I915_WRITE(type##IIR, 0xffffffff); \
	POSTING_READ(type##IIR); \
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} while (0)

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/*
 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
 */
#define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
	u32 val = I915_READ(reg); \
	if (val) { \
		WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
		     (reg), val); \
		I915_WRITE((reg), 0xffffffff); \
		POSTING_READ(reg); \
		I915_WRITE((reg), 0xffffffff); \
		POSTING_READ(reg); \
	} \
} while (0)

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#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
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	GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
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	I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
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	I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
	POSTING_READ(GEN8_##type##_IMR(which)); \
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} while (0)

#define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
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	GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
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	I915_WRITE(type##IER, (ier_val)); \
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	I915_WRITE(type##IMR, (imr_val)); \
	POSTING_READ(type##IMR); \
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} while (0)

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static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);

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/* For display hotplug interrupt */
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void
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ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
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{
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	assert_spin_locked(&dev_priv->irq_lock);

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	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
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		return;

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	if ((dev_priv->irq_mask & mask) != 0) {
		dev_priv->irq_mask &= ~mask;
		I915_WRITE(DEIMR, dev_priv->irq_mask);
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		POSTING_READ(DEIMR);
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	}
}

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void
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ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
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{
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	assert_spin_locked(&dev_priv->irq_lock);

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	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
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		return;

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	if ((dev_priv->irq_mask & mask) != mask) {
		dev_priv->irq_mask |= mask;
		I915_WRITE(DEIMR, dev_priv->irq_mask);
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		POSTING_READ(DEIMR);
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	}
}

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/**
 * ilk_update_gt_irq - update GTIMR
 * @dev_priv: driver private
 * @interrupt_mask: mask of interrupt bits to update
 * @enabled_irq_mask: mask of interrupt bits to enable
 */
static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
			      uint32_t interrupt_mask,
			      uint32_t enabled_irq_mask)
{
	assert_spin_locked(&dev_priv->irq_lock);

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	WARN_ON(enabled_irq_mask & ~interrupt_mask);

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	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
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		return;

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	dev_priv->gt_irq_mask &= ~interrupt_mask;
	dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
	POSTING_READ(GTIMR);
}

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void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
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{
	ilk_update_gt_irq(dev_priv, mask, mask);
}

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void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
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{
	ilk_update_gt_irq(dev_priv, mask, 0);
}

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static u32 gen6_pm_iir(struct drm_i915_private *dev_priv)
{
	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
}

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static u32 gen6_pm_imr(struct drm_i915_private *dev_priv)
{
	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
}

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static u32 gen6_pm_ier(struct drm_i915_private *dev_priv)
{
	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
}

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/**
  * snb_update_pm_irq - update GEN6_PMIMR
  * @dev_priv: driver private
  * @interrupt_mask: mask of interrupt bits to update
  * @enabled_irq_mask: mask of interrupt bits to enable
  */
static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
			      uint32_t interrupt_mask,
			      uint32_t enabled_irq_mask)
{
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	uint32_t new_val;
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	WARN_ON(enabled_irq_mask & ~interrupt_mask);

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	assert_spin_locked(&dev_priv->irq_lock);

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	new_val = dev_priv->pm_irq_mask;
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	new_val &= ~interrupt_mask;
	new_val |= (~enabled_irq_mask & interrupt_mask);

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	if (new_val != dev_priv->pm_irq_mask) {
		dev_priv->pm_irq_mask = new_val;
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		I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
		POSTING_READ(gen6_pm_imr(dev_priv));
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	}
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}

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void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
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{
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	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
		return;

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	snb_update_pm_irq(dev_priv, mask, mask);
}

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static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
				  uint32_t mask)
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{
	snb_update_pm_irq(dev_priv, mask, 0);
}

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void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
{
	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
		return;

	__gen6_disable_pm_irq(dev_priv, mask);
}

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void gen6_reset_rps_interrupts(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t reg = gen6_pm_iir(dev_priv);

	spin_lock_irq(&dev_priv->irq_lock);
	I915_WRITE(reg, dev_priv->pm_rps_events);
	I915_WRITE(reg, dev_priv->pm_rps_events);
	POSTING_READ(reg);
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	dev_priv->rps.pm_iir = 0;
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	spin_unlock_irq(&dev_priv->irq_lock);
}

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void gen6_enable_rps_interrupts(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	spin_lock_irq(&dev_priv->irq_lock);
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	WARN_ON(dev_priv->rps.pm_iir);
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	WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
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	dev_priv->rps.interrupts_enabled = true;
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	I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
				dev_priv->pm_rps_events);
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	gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
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	spin_unlock_irq(&dev_priv->irq_lock);
}

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u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
{
	/*
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	 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
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	 * if GEN6_PM_UP_EI_EXPIRED is masked.
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	 *
	 * TODO: verify if this can be reproduced on VLV,CHV.
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	 */
	if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
		mask &= ~GEN6_PM_RP_UP_EI_EXPIRED;

	if (INTEL_INFO(dev_priv)->gen >= 8)
		mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;

	return mask;
}

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void gen6_disable_rps_interrupts(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

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	spin_lock_irq(&dev_priv->irq_lock);
	dev_priv->rps.interrupts_enabled = false;
	spin_unlock_irq(&dev_priv->irq_lock);

	cancel_work_sync(&dev_priv->rps.work);

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	spin_lock_irq(&dev_priv->irq_lock);

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	I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0));
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	__gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
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	I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
				~dev_priv->pm_rps_events);
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	spin_unlock_irq(&dev_priv->irq_lock);

	synchronize_irq(dev->irq);
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}

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/**
 * ibx_display_interrupt_update - update SDEIMR
 * @dev_priv: driver private
 * @interrupt_mask: mask of interrupt bits to update
 * @enabled_irq_mask: mask of interrupt bits to enable
 */
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void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
				  uint32_t interrupt_mask,
				  uint32_t enabled_irq_mask)
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{
	uint32_t sdeimr = I915_READ(SDEIMR);
	sdeimr &= ~interrupt_mask;
	sdeimr |= (~enabled_irq_mask & interrupt_mask);

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	WARN_ON(enabled_irq_mask & ~interrupt_mask);

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	assert_spin_locked(&dev_priv->irq_lock);

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	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
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		return;

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	I915_WRITE(SDEIMR, sdeimr);
	POSTING_READ(SDEIMR);
}
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static void
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__i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		       u32 enable_mask, u32 status_mask)
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{
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	u32 reg = PIPESTAT(pipe);
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	u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
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	assert_spin_locked(&dev_priv->irq_lock);
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	WARN_ON(!intel_irqs_enabled(dev_priv));
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	if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
		      status_mask & ~PIPESTAT_INT_STATUS_MASK,
		      "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
		      pipe_name(pipe), enable_mask, status_mask))
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		return;

	if ((pipestat & enable_mask) == enable_mask)
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		return;

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	dev_priv->pipestat_irq_mask[pipe] |= status_mask;

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	/* Enable the interrupt, clear any pending status */
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	pipestat |= enable_mask | status_mask;
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	I915_WRITE(reg, pipestat);
	POSTING_READ(reg);
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}

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static void
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__i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		        u32 enable_mask, u32 status_mask)
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{
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	u32 reg = PIPESTAT(pipe);
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	u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
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	assert_spin_locked(&dev_priv->irq_lock);
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	WARN_ON(!intel_irqs_enabled(dev_priv));
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	if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
		      status_mask & ~PIPESTAT_INT_STATUS_MASK,
		      "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
		      pipe_name(pipe), enable_mask, status_mask))
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		return;

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	if ((pipestat & enable_mask) == 0)
		return;

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	dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;

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	pipestat &= ~enable_mask;
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	I915_WRITE(reg, pipestat);
	POSTING_READ(reg);
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}

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static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
{
	u32 enable_mask = status_mask << 16;

	/*
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	 * On pipe A we don't support the PSR interrupt yet,
	 * on pipe B and C the same bit MBZ.
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	 */
	if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
		return 0;
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	/*
	 * On pipe B and C we don't support the PSR interrupt yet, on pipe
	 * A the same bit is for perf counters which we don't use either.
	 */
	if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
		return 0;
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	enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
			 SPRITE0_FLIP_DONE_INT_EN_VLV |
			 SPRITE1_FLIP_DONE_INT_EN_VLV);
	if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
		enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
	if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
		enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;

	return enable_mask;
}

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void
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		     u32 status_mask)
{
	u32 enable_mask;

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	if (IS_VALLEYVIEW(dev_priv->dev))
		enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
							   status_mask);
	else
		enable_mask = status_mask << 16;
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	__i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
}

void
i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		      u32 status_mask)
{
	u32 enable_mask;

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	if (IS_VALLEYVIEW(dev_priv->dev))
		enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
							   status_mask);
	else
		enable_mask = status_mask << 16;
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	__i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
}

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/**
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 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
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 */
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static void i915_enable_asle_pipestat(struct drm_device *dev)
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{
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	struct drm_i915_private *dev_priv = dev->dev_private;
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	if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
		return;

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	spin_lock_irq(&dev_priv->irq_lock);
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	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
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	if (INTEL_INFO(dev)->gen >= 4)
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		i915_enable_pipestat(dev_priv, PIPE_A,
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				     PIPE_LEGACY_BLC_EVENT_STATUS);
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	spin_unlock_irq(&dev_priv->irq_lock);
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}

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/*
 * This timing diagram depicts the video signal in and
 * around the vertical blanking period.
 *
 * Assumptions about the fictitious mode used in this example:
 *  vblank_start >= 3
 *  vsync_start = vblank_start + 1
 *  vsync_end = vblank_start + 2
 *  vtotal = vblank_start + 3
 *
 *           start of vblank:
 *           latch double buffered registers
 *           increment frame counter (ctg+)
 *           generate start of vblank interrupt (gen4+)
 *           |
 *           |          frame start:
 *           |          generate frame start interrupt (aka. vblank interrupt) (gmch)
 *           |          may be shifted forward 1-3 extra lines via PIPECONF
 *           |          |
 *           |          |  start of vsync:
 *           |          |  generate vsync interrupt
 *           |          |  |
 * ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx
 *       .   \hs/   .      \hs/          \hs/          \hs/   .      \hs/
 * ----va---> <-----------------vb--------------------> <--------va-------------
 *       |          |       <----vs----->                     |
 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
 *       |          |                                         |
 *       last visible pixel                                   first visible pixel
 *                  |                                         increment frame counter (gen3/4)
 *                  pixel counter = vblank_start * htotal     pixel counter = 0 (gen3/4)
 *
 * x  = horizontal active
 * _  = horizontal blanking
 * hs = horizontal sync
 * va = vertical active
 * vb = vertical blanking
 * vs = vertical sync
 * vbs = vblank_start (number)
 *
 * Summary:
 * - most events happen at the start of horizontal sync
 * - frame start happens at the start of horizontal blank, 1-4 lines
 *   (depending on PIPECONF settings) after the start of vblank
 * - gen3/4 pixel and frame counter are synchronized with the start
 *   of horizontal active on the first line of vertical active
 */

557 558 559 560 561 562
static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
{
	/* Gen2 doesn't have a hardware frame counter */
	return 0;
}

563 564 565
/* Called from drm generic code, passed a 'crtc', which
 * we use as a pipe index
 */
566
static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
567
{
568
	struct drm_i915_private *dev_priv = dev->dev_private;
569 570
	unsigned long high_frame;
	unsigned long low_frame;
571
	u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
572 573
	struct intel_crtc *intel_crtc =
		to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
574
	const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
575

576 577 578 579 580
	htotal = mode->crtc_htotal;
	hsync_start = mode->crtc_hsync_start;
	vbl_start = mode->crtc_vblank_start;
	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
		vbl_start = DIV_ROUND_UP(vbl_start, 2);
581

582 583 584 585 586 587
	/* Convert to pixel count */
	vbl_start *= htotal;

	/* Start of vblank event occurs at start of hsync */
	vbl_start -= htotal - hsync_start;

588 589
	high_frame = PIPEFRAME(pipe);
	low_frame = PIPEFRAMEPIXEL(pipe);
590

591 592 593 594 595 596
	/*
	 * High & low register fields aren't synchronized, so make sure
	 * we get a low value that's stable across two reads of the high
	 * register.
	 */
	do {
597
		high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
598
		low   = I915_READ(low_frame);
599
		high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
600 601
	} while (high1 != high2);

602
	high1 >>= PIPE_FRAME_HIGH_SHIFT;
603
	pixel = low & PIPE_PIXEL_MASK;
604
	low >>= PIPE_FRAME_LOW_SHIFT;
605 606 607 608 609 610

	/*
	 * The frame counter increments at beginning of active.
	 * Cook up a vblank counter by also checking the pixel
	 * counter against vblank start.
	 */
611
	return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
612 613
}

614
static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
615
{
616
	struct drm_i915_private *dev_priv = dev->dev_private;
617
	int reg = PIPE_FRMCOUNT_GM45(pipe);
618 619 620 621

	return I915_READ(reg);
}

622 623 624
/* raw reads, only for fast reads of display block, no need for forcewake etc. */
#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))

625 626 627 628
static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
629
	const struct drm_display_mode *mode = &crtc->base.hwmode;
630
	enum pipe pipe = crtc->pipe;
631
	int position, vtotal;
632

633
	vtotal = mode->crtc_vtotal;
634 635 636 637 638 639 640 641
	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
		vtotal /= 2;

	if (IS_GEN2(dev))
		position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
	else
		position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;

642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667
	/*
	 * On HSW, the DSL reg (0x70000) appears to return 0 if we
	 * read it just before the start of vblank.  So try it again
	 * so we don't accidentally end up spanning a vblank frame
	 * increment, causing the pipe_update_end() code to squak at us.
	 *
	 * The nature of this problem means we can't simply check the ISR
	 * bit and return the vblank start value; nor can we use the scanline
	 * debug register in the transcoder as it appears to have the same
	 * problem.  We may need to extend this to include other platforms,
	 * but so far testing only shows the problem on HSW.
	 */
	if (IS_HASWELL(dev) && !position) {
		int i, temp;

		for (i = 0; i < 100; i++) {
			udelay(1);
			temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) &
				DSL_LINEMASK_GEN3;
			if (temp != position) {
				position = temp;
				break;
			}
		}
	}

668
	/*
669 670
	 * See update_scanline_offset() for the details on the
	 * scanline_offset adjustment.
671
	 */
672
	return (position + crtc->scanline_offset) % vtotal;
673 674
}

675
static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
676
				    unsigned int flags, int *vpos, int *hpos,
677 678
				    ktime_t *stime, ktime_t *etime,
				    const struct drm_display_mode *mode)
679
{
680 681 682
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
683
	int position;
684
	int vbl_start, vbl_end, hsync_start, htotal, vtotal;
685 686
	bool in_vbl = true;
	int ret = 0;
687
	unsigned long irqflags;
688

689
	if (WARN_ON(!mode->crtc_clock)) {
690
		DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
691
				 "pipe %c\n", pipe_name(pipe));
692 693 694
		return 0;
	}

695
	htotal = mode->crtc_htotal;
696
	hsync_start = mode->crtc_hsync_start;
697 698 699
	vtotal = mode->crtc_vtotal;
	vbl_start = mode->crtc_vblank_start;
	vbl_end = mode->crtc_vblank_end;
700

701 702 703 704 705 706
	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
		vbl_start = DIV_ROUND_UP(vbl_start, 2);
		vbl_end /= 2;
		vtotal /= 2;
	}

707 708
	ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;

709 710 711 712 713 714
	/*
	 * Lock uncore.lock, as we will do multiple timing critical raw
	 * register reads, potentially with preemption disabled, so the
	 * following code must not block on uncore.lock.
	 */
	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
715

716 717 718 719 720 721
	/* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */

	/* Get optional system timestamp before query. */
	if (stime)
		*stime = ktime_get();

722
	if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
723 724 725
		/* No obvious pixelcount register. Only query vertical
		 * scanout position from Display scan line register.
		 */
726
		position = __intel_get_crtc_scanline(intel_crtc);
727 728 729 730 731
	} else {
		/* Have access to pixelcount since start of frame.
		 * We can split this into vertical and horizontal
		 * scanout position.
		 */
732
		position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
733

734 735 736 737
		/* convert to pixel counts */
		vbl_start *= htotal;
		vbl_end *= htotal;
		vtotal *= htotal;
738

739 740 741 742 743 744 745 746 747 748 749 750
		/*
		 * In interlaced modes, the pixel counter counts all pixels,
		 * so one field will have htotal more pixels. In order to avoid
		 * the reported position from jumping backwards when the pixel
		 * counter is beyond the length of the shorter field, just
		 * clamp the position the length of the shorter field. This
		 * matches how the scanline counter based position works since
		 * the scanline counter doesn't count the two half lines.
		 */
		if (position >= vtotal)
			position = vtotal - 1;

751 752 753 754 755 756 757 758 759 760
		/*
		 * Start of vblank interrupt is triggered at start of hsync,
		 * just prior to the first active line of vblank. However we
		 * consider lines to start at the leading edge of horizontal
		 * active. So, should we get here before we've crossed into
		 * the horizontal active of the first line in vblank, we would
		 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
		 * always add htotal-hsync_start to the current pixel position.
		 */
		position = (position + htotal - hsync_start) % vtotal;
761 762
	}

763 764 765 766 767 768 769 770
	/* Get optional system timestamp after query. */
	if (etime)
		*etime = ktime_get();

	/* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */

	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

771 772 773 774 775 776 777 778 779 780 781 782
	in_vbl = position >= vbl_start && position < vbl_end;

	/*
	 * While in vblank, position will be negative
	 * counting up towards 0 at vbl_end. And outside
	 * vblank, position will be positive counting
	 * up since vbl_end.
	 */
	if (position >= vbl_start)
		position -= vbl_end;
	else
		position += vtotal - vbl_end;
783

784
	if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
785 786 787 788 789 790
		*vpos = position;
		*hpos = 0;
	} else {
		*vpos = position / htotal;
		*hpos = position - (*vpos * htotal);
	}
791 792 793

	/* In vblank? */
	if (in_vbl)
794
		ret |= DRM_SCANOUTPOS_IN_VBLANK;
795 796 797 798

	return ret;
}

799 800 801 802 803 804 805 806 807 808 809 810 811
int intel_get_crtc_scanline(struct intel_crtc *crtc)
{
	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
	unsigned long irqflags;
	int position;

	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
	position = __intel_get_crtc_scanline(crtc);
	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

	return position;
}

812
static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
813 814 815 816
			      int *max_error,
			      struct timeval *vblank_time,
			      unsigned flags)
{
817
	struct drm_crtc *crtc;
818

819
	if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
820
		DRM_ERROR("Invalid crtc %d\n", pipe);
821 822 823 824
		return -EINVAL;
	}

	/* Get drm_crtc to timestamp: */
825 826 827 828 829 830
	crtc = intel_get_crtc_for_pipe(dev, pipe);
	if (crtc == NULL) {
		DRM_ERROR("Invalid crtc %d\n", pipe);
		return -EINVAL;
	}

831
	if (!crtc->hwmode.crtc_clock) {
832 833 834
		DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
		return -EBUSY;
	}
835 836

	/* Helper routine in DRM core does all the work: */
837 838
	return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
						     vblank_time, flags,
839
						     &crtc->hwmode);
840 841
}

842
static void ironlake_rps_change_irq_handler(struct drm_device *dev)
843
{
844
	struct drm_i915_private *dev_priv = dev->dev_private;
845
	u32 busy_up, busy_down, max_avg, min_avg;
846 847
	u8 new_delay;

848
	spin_lock(&mchdev_lock);
849

850 851
	I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));

852
	new_delay = dev_priv->ips.cur_delay;
853

854
	I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
855 856
	busy_up = I915_READ(RCPREVBSYTUPAVG);
	busy_down = I915_READ(RCPREVBSYTDNAVG);
857 858 859 860
	max_avg = I915_READ(RCBMAXAVG);
	min_avg = I915_READ(RCBMINAVG);

	/* Handle RCS change request from hw */
861
	if (busy_up > max_avg) {
862 863 864 865
		if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
			new_delay = dev_priv->ips.cur_delay - 1;
		if (new_delay < dev_priv->ips.max_delay)
			new_delay = dev_priv->ips.max_delay;
866
	} else if (busy_down < min_avg) {
867 868 869 870
		if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
			new_delay = dev_priv->ips.cur_delay + 1;
		if (new_delay > dev_priv->ips.min_delay)
			new_delay = dev_priv->ips.min_delay;
871 872
	}

873
	if (ironlake_set_drps(dev, new_delay))
874
		dev_priv->ips.cur_delay = new_delay;
875

876
	spin_unlock(&mchdev_lock);
877

878 879 880
	return;
}

C
Chris Wilson 已提交
881
static void notify_ring(struct intel_engine_cs *ring)
882
{
883
	if (!intel_ring_initialized(ring))
884 885
		return;

886
	trace_i915_gem_request_notify(ring);
887

888 889 890
	wake_up_all(&ring->irq_queue);
}

891 892
static void vlv_c0_read(struct drm_i915_private *dev_priv,
			struct intel_rps_ei *ei)
893
{
894 895 896 897
	ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
	ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
	ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
}
898

899 900 901 902 903 904
static bool vlv_c0_above(struct drm_i915_private *dev_priv,
			 const struct intel_rps_ei *old,
			 const struct intel_rps_ei *now,
			 int threshold)
{
	u64 time, c0;
905

906 907
	if (old->cz_clock == 0)
		return false;
908

909 910
	time = now->cz_clock - old->cz_clock;
	time *= threshold * dev_priv->mem_freq;
911

912 913 914
	/* Workload can be split between render + media, e.g. SwapBuffers
	 * being blitted in X after being rendered in mesa. To account for
	 * this we need to combine both engines into our activity counter.
915
	 */
916 917 918
	c0 = now->render_c0 - old->render_c0;
	c0 += now->media_c0 - old->media_c0;
	c0 *= 100 * VLV_CZ_CLOCK_TO_MILLI_SEC * 4 / 1000;
919

920
	return c0 >= time;
921 922
}

923
void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
924
{
925 926 927
	vlv_c0_read(dev_priv, &dev_priv->rps.down_ei);
	dev_priv->rps.up_ei = dev_priv->rps.down_ei;
}
928

929 930 931 932
static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
{
	struct intel_rps_ei now;
	u32 events = 0;
933

934
	if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0)
935
		return 0;
936

937 938 939
	vlv_c0_read(dev_priv, &now);
	if (now.cz_clock == 0)
		return 0;
940

941 942 943
	if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
		if (!vlv_c0_above(dev_priv,
				  &dev_priv->rps.down_ei, &now,
944
				  dev_priv->rps.down_threshold))
945 946 947
			events |= GEN6_PM_RP_DOWN_THRESHOLD;
		dev_priv->rps.down_ei = now;
	}
948

949 950 951
	if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
		if (vlv_c0_above(dev_priv,
				 &dev_priv->rps.up_ei, &now,
952
				 dev_priv->rps.up_threshold))
953 954
			events |= GEN6_PM_RP_UP_THRESHOLD;
		dev_priv->rps.up_ei = now;
955 956
	}

957
	return events;
958 959
}

960 961 962 963 964 965 966 967 968 969 970 971
static bool any_waiters(struct drm_i915_private *dev_priv)
{
	struct intel_engine_cs *ring;
	int i;

	for_each_ring(ring, dev_priv, i)
		if (ring->irq_refcount)
			return true;

	return false;
}

972
static void gen6_pm_rps_work(struct work_struct *work)
973
{
974 975
	struct drm_i915_private *dev_priv =
		container_of(work, struct drm_i915_private, rps.work);
976 977
	bool client_boost;
	int new_delay, adj, min, max;
P
Paulo Zanoni 已提交
978
	u32 pm_iir;
979

980
	spin_lock_irq(&dev_priv->irq_lock);
I
Imre Deak 已提交
981 982 983 984 985
	/* Speed up work cancelation during disabling rps interrupts. */
	if (!dev_priv->rps.interrupts_enabled) {
		spin_unlock_irq(&dev_priv->irq_lock);
		return;
	}
986 987
	pm_iir = dev_priv->rps.pm_iir;
	dev_priv->rps.pm_iir = 0;
988 989
	/* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
	gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
990 991
	client_boost = dev_priv->rps.client_boost;
	dev_priv->rps.client_boost = false;
992
	spin_unlock_irq(&dev_priv->irq_lock);
993

994
	/* Make sure we didn't queue anything we're not going to process. */
995
	WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
996

997
	if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
998 999
		return;

1000
	mutex_lock(&dev_priv->rps.hw_lock);
1001

1002 1003
	pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);

1004
	adj = dev_priv->rps.last_adj;
1005
	new_delay = dev_priv->rps.cur_freq;
1006 1007 1008 1009 1010 1011 1012
	min = dev_priv->rps.min_freq_softlimit;
	max = dev_priv->rps.max_freq_softlimit;

	if (client_boost) {
		new_delay = dev_priv->rps.max_freq_softlimit;
		adj = 0;
	} else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1013 1014
		if (adj > 0)
			adj *= 2;
1015 1016
		else /* CHV needs even encode values */
			adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1017 1018 1019 1020
		/*
		 * For better performance, jump directly
		 * to RPe if we're below it.
		 */
1021
		if (new_delay < dev_priv->rps.efficient_freq - adj) {
1022
			new_delay = dev_priv->rps.efficient_freq;
1023 1024
			adj = 0;
		}
1025 1026
	} else if (any_waiters(dev_priv)) {
		adj = 0;
1027
	} else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1028 1029
		if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
			new_delay = dev_priv->rps.efficient_freq;
1030
		else
1031
			new_delay = dev_priv->rps.min_freq_softlimit;
1032 1033 1034 1035
		adj = 0;
	} else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
		if (adj < 0)
			adj *= 2;
1036 1037
		else /* CHV needs even encode values */
			adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1038
	} else { /* unknown event */
1039
		adj = 0;
1040
	}
1041

1042 1043
	dev_priv->rps.last_adj = adj;

1044 1045 1046
	/* sysfs frequency interfaces may have snuck in while servicing the
	 * interrupt
	 */
1047
	new_delay += adj;
1048
	new_delay = clamp_t(int, new_delay, min, max);
1049

1050
	intel_set_rps(dev_priv->dev, new_delay);
1051

1052
	mutex_unlock(&dev_priv->rps.hw_lock);
1053 1054
}

1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066

/**
 * ivybridge_parity_work - Workqueue called when a parity error interrupt
 * occurred.
 * @work: workqueue struct
 *
 * Doesn't actually do anything except notify userspace. As a consequence of
 * this event, userspace should try to remap the bad rows since statistically
 * it is likely the same row is more likely to go bad again.
 */
static void ivybridge_parity_work(struct work_struct *work)
{
1067 1068
	struct drm_i915_private *dev_priv =
		container_of(work, struct drm_i915_private, l3_parity.error_work);
1069
	u32 error_status, row, bank, subbank;
1070
	char *parity_event[6];
1071
	uint32_t misccpctl;
1072
	uint8_t slice = 0;
1073 1074 1075 1076 1077 1078 1079

	/* We must turn off DOP level clock gating to access the L3 registers.
	 * In order to prevent a get/put style interface, acquire struct mutex
	 * any time we access those registers.
	 */
	mutex_lock(&dev_priv->dev->struct_mutex);

1080 1081 1082 1083
	/* If we've screwed up tracking, just let the interrupt fire again */
	if (WARN_ON(!dev_priv->l3_parity.which_slice))
		goto out;

1084 1085 1086 1087
	misccpctl = I915_READ(GEN7_MISCCPCTL);
	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
	POSTING_READ(GEN7_MISCCPCTL);

1088 1089
	while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
		u32 reg;
1090

1091 1092 1093
		slice--;
		if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
			break;
1094

1095
		dev_priv->l3_parity.which_slice &= ~(1<<slice);
1096

1097
		reg = GEN7_L3CDERRST1 + (slice * 0x200);
1098

1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113
		error_status = I915_READ(reg);
		row = GEN7_PARITY_ERROR_ROW(error_status);
		bank = GEN7_PARITY_ERROR_BANK(error_status);
		subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);

		I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
		POSTING_READ(reg);

		parity_event[0] = I915_L3_PARITY_UEVENT "=1";
		parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
		parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
		parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
		parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
		parity_event[5] = NULL;

1114
		kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1115
				   KOBJ_CHANGE, parity_event);
1116

1117 1118
		DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
			  slice, row, bank, subbank);
1119

1120 1121 1122 1123 1124
		kfree(parity_event[4]);
		kfree(parity_event[3]);
		kfree(parity_event[2]);
		kfree(parity_event[1]);
	}
1125

1126
	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1127

1128 1129
out:
	WARN_ON(dev_priv->l3_parity.which_slice);
1130
	spin_lock_irq(&dev_priv->irq_lock);
1131
	gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1132
	spin_unlock_irq(&dev_priv->irq_lock);
1133 1134

	mutex_unlock(&dev_priv->dev->struct_mutex);
1135 1136
}

1137
static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1138
{
1139
	struct drm_i915_private *dev_priv = dev->dev_private;
1140

1141
	if (!HAS_L3_DPF(dev))
1142 1143
		return;

1144
	spin_lock(&dev_priv->irq_lock);
1145
	gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1146
	spin_unlock(&dev_priv->irq_lock);
1147

1148 1149 1150 1151 1152 1153 1154
	iir &= GT_PARITY_ERROR(dev);
	if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
		dev_priv->l3_parity.which_slice |= 1 << 1;

	if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
		dev_priv->l3_parity.which_slice |= 1 << 0;

1155
	queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1156 1157
}

1158 1159 1160 1161 1162 1163
static void ilk_gt_irq_handler(struct drm_device *dev,
			       struct drm_i915_private *dev_priv,
			       u32 gt_iir)
{
	if (gt_iir &
	    (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
C
Chris Wilson 已提交
1164
		notify_ring(&dev_priv->ring[RCS]);
1165
	if (gt_iir & ILK_BSD_USER_INTERRUPT)
C
Chris Wilson 已提交
1166
		notify_ring(&dev_priv->ring[VCS]);
1167 1168
}

1169 1170 1171 1172 1173
static void snb_gt_irq_handler(struct drm_device *dev,
			       struct drm_i915_private *dev_priv,
			       u32 gt_iir)
{

1174 1175
	if (gt_iir &
	    (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
C
Chris Wilson 已提交
1176
		notify_ring(&dev_priv->ring[RCS]);
1177
	if (gt_iir & GT_BSD_USER_INTERRUPT)
C
Chris Wilson 已提交
1178
		notify_ring(&dev_priv->ring[VCS]);
1179
	if (gt_iir & GT_BLT_USER_INTERRUPT)
C
Chris Wilson 已提交
1180
		notify_ring(&dev_priv->ring[BCS]);
1181

1182 1183
	if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
		      GT_BSD_CS_ERROR_INTERRUPT |
1184 1185
		      GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
		DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1186

1187 1188
	if (gt_iir & GT_PARITY_ERROR(dev))
		ivybridge_parity_error_irq_handler(dev, gt_iir);
1189 1190
}

C
Chris Wilson 已提交
1191
static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
1192 1193 1194 1195 1196
				       u32 master_ctl)
{
	irqreturn_t ret = IRQ_NONE;

	if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
C
Chris Wilson 已提交
1197
		u32 tmp = I915_READ_FW(GEN8_GT_IIR(0));
1198
		if (tmp) {
1199
			I915_WRITE_FW(GEN8_GT_IIR(0), tmp);
1200
			ret = IRQ_HANDLED;
1201

C
Chris Wilson 已提交
1202 1203 1204 1205 1206 1207 1208 1209 1210
			if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
				intel_lrc_irq_handler(&dev_priv->ring[RCS]);
			if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
				notify_ring(&dev_priv->ring[RCS]);

			if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
				intel_lrc_irq_handler(&dev_priv->ring[BCS]);
			if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
				notify_ring(&dev_priv->ring[BCS]);
1211 1212 1213 1214
		} else
			DRM_ERROR("The master control interrupt lied (GT0)!\n");
	}

1215
	if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
C
Chris Wilson 已提交
1216
		u32 tmp = I915_READ_FW(GEN8_GT_IIR(1));
1217
		if (tmp) {
1218
			I915_WRITE_FW(GEN8_GT_IIR(1), tmp);
1219
			ret = IRQ_HANDLED;
1220

C
Chris Wilson 已提交
1221 1222 1223 1224
			if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
				intel_lrc_irq_handler(&dev_priv->ring[VCS]);
			if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
				notify_ring(&dev_priv->ring[VCS]);
1225

C
Chris Wilson 已提交
1226 1227 1228 1229
			if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
				intel_lrc_irq_handler(&dev_priv->ring[VCS2]);
			if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
				notify_ring(&dev_priv->ring[VCS2]);
1230
		} else
1231
			DRM_ERROR("The master control interrupt lied (GT1)!\n");
1232 1233
	}

1234
	if (master_ctl & GEN8_GT_VECS_IRQ) {
C
Chris Wilson 已提交
1235
		u32 tmp = I915_READ_FW(GEN8_GT_IIR(3));
1236
		if (tmp) {
C
Chris Wilson 已提交
1237
			I915_WRITE_FW(GEN8_GT_IIR(3), tmp);
1238
			ret = IRQ_HANDLED;
1239

C
Chris Wilson 已提交
1240 1241 1242 1243
			if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
				intel_lrc_irq_handler(&dev_priv->ring[VECS]);
			if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
				notify_ring(&dev_priv->ring[VECS]);
1244 1245 1246 1247
		} else
			DRM_ERROR("The master control interrupt lied (GT3)!\n");
	}

1248
	if (master_ctl & GEN8_GT_PM_IRQ) {
C
Chris Wilson 已提交
1249
		u32 tmp = I915_READ_FW(GEN8_GT_IIR(2));
1250
		if (tmp & dev_priv->pm_rps_events) {
1251 1252
			I915_WRITE_FW(GEN8_GT_IIR(2),
				      tmp & dev_priv->pm_rps_events);
1253
			ret = IRQ_HANDLED;
1254
			gen6_rps_irq_handler(dev_priv, tmp);
1255 1256 1257 1258
		} else
			DRM_ERROR("The master control interrupt lied (PM)!\n");
	}

1259 1260 1261
	return ret;
}

1262
static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
1263 1264 1265
{
	switch (port) {
	case PORT_A:
1266
		return val & BXT_PORTA_HOTPLUG_LONG_DETECT;
1267
	case PORT_B:
1268
		return val & PORTB_HOTPLUG_LONG_DETECT;
1269
	case PORT_C:
1270
		return val & PORTC_HOTPLUG_LONG_DETECT;
1271
	case PORT_D:
1272 1273 1274
		return val & PORTD_HOTPLUG_LONG_DETECT;
	default:
		return false;
1275 1276 1277
	}
}

1278
static bool pch_port_hotplug_long_detect(enum port port, u32 val)
1279 1280 1281
{
	switch (port) {
	case PORT_B:
1282
		return val & PORTB_HOTPLUG_LONG_DETECT;
1283
	case PORT_C:
1284
		return val & PORTC_HOTPLUG_LONG_DETECT;
1285
	case PORT_D:
1286
		return val & PORTD_HOTPLUG_LONG_DETECT;
X
Xiong Zhang 已提交
1287 1288
	case PORT_E:
		return val & PORTE_HOTPLUG_LONG_DETECT;
1289 1290
	default:
		return false;
1291 1292 1293
	}
}

1294
static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
1295 1296 1297
{
	switch (port) {
	case PORT_B:
1298
		return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1299
	case PORT_C:
1300
		return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1301
	case PORT_D:
1302
		return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1303
	default:
1304
		return false;
1305 1306 1307
	}
}

1308
/* Get a bit mask of pins that have triggered, and which ones may be long. */
1309
static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
1310
			     u32 hotplug_trigger, u32 dig_hotplug_reg,
1311 1312
			     const u32 hpd[HPD_NUM_PINS],
			     bool long_pulse_detect(enum port port, u32 val))
1313
{
1314
	enum port port;
1315
	int i;
1316

1317 1318
	*pin_mask = 0;
	*long_mask = 0;
1319

1320
	for_each_hpd_pin(i) {
1321
		if ((hpd[i] & hotplug_trigger) == 0)
1322 1323
			continue;

1324
		*pin_mask |= BIT(i);
1325

1326
		if (!intel_hpd_pin_to_port(i, &port))
1327
			continue;
1328

1329
		if (long_pulse_detect(port, dig_hotplug_reg))
1330
			*long_mask |= BIT(i);
1331 1332
	}

1333 1334
	DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
			 hotplug_trigger, dig_hotplug_reg, *pin_mask);
1335

1336 1337
}

1338 1339
static void gmbus_irq_handler(struct drm_device *dev)
{
1340
	struct drm_i915_private *dev_priv = dev->dev_private;
1341 1342

	wake_up_all(&dev_priv->gmbus_wait_queue);
1343 1344
}

1345 1346
static void dp_aux_irq_handler(struct drm_device *dev)
{
1347
	struct drm_i915_private *dev_priv = dev->dev_private;
1348 1349

	wake_up_all(&dev_priv->gmbus_wait_queue);
1350 1351
}

1352
#if defined(CONFIG_DEBUG_FS)
1353 1354 1355 1356
static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
					 uint32_t crc0, uint32_t crc1,
					 uint32_t crc2, uint32_t crc3,
					 uint32_t crc4)
1357 1358 1359 1360
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
	struct intel_pipe_crc_entry *entry;
1361
	int head, tail;
1362

1363 1364
	spin_lock(&pipe_crc->lock);

1365
	if (!pipe_crc->entries) {
1366
		spin_unlock(&pipe_crc->lock);
1367
		DRM_DEBUG_KMS("spurious interrupt\n");
1368 1369 1370
		return;
	}

1371 1372
	head = pipe_crc->head;
	tail = pipe_crc->tail;
1373 1374

	if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1375
		spin_unlock(&pipe_crc->lock);
1376 1377 1378 1379 1380
		DRM_ERROR("CRC buffer overflowing\n");
		return;
	}

	entry = &pipe_crc->entries[head];
1381

1382
	entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1383 1384 1385 1386 1387
	entry->crc[0] = crc0;
	entry->crc[1] = crc1;
	entry->crc[2] = crc2;
	entry->crc[3] = crc3;
	entry->crc[4] = crc4;
1388 1389

	head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1390 1391 1392
	pipe_crc->head = head;

	spin_unlock(&pipe_crc->lock);
1393 1394

	wake_up_interruptible(&pipe_crc->wq);
1395
}
1396 1397 1398 1399 1400 1401 1402 1403
#else
static inline void
display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
			     uint32_t crc0, uint32_t crc1,
			     uint32_t crc2, uint32_t crc3,
			     uint32_t crc4) {}
#endif

1404

1405
static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
D
Daniel Vetter 已提交
1406 1407 1408
{
	struct drm_i915_private *dev_priv = dev->dev_private;

1409 1410 1411
	display_pipe_crc_irq_handler(dev, pipe,
				     I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
				     0, 0, 0, 0);
D
Daniel Vetter 已提交
1412 1413
}

1414
static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1415 1416 1417
{
	struct drm_i915_private *dev_priv = dev->dev_private;

1418 1419 1420 1421 1422 1423
	display_pipe_crc_irq_handler(dev, pipe,
				     I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
				     I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
				     I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
				     I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
				     I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1424
}
1425

1426
static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1427 1428
{
	struct drm_i915_private *dev_priv = dev->dev_private;
1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439
	uint32_t res1, res2;

	if (INTEL_INFO(dev)->gen >= 3)
		res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
	else
		res1 = 0;

	if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
		res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
	else
		res2 = 0;
1440

1441 1442 1443 1444 1445
	display_pipe_crc_irq_handler(dev, pipe,
				     I915_READ(PIPE_CRC_RES_RED(pipe)),
				     I915_READ(PIPE_CRC_RES_GREEN(pipe)),
				     I915_READ(PIPE_CRC_RES_BLUE(pipe)),
				     res1, res2);
1446
}
1447

1448 1449 1450 1451
/* The RPS events need forcewake, so we add them to a work queue and mask their
 * IMR bits until the work is done. Other interrupts can be processed without
 * the work queue. */
static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1452
{
1453
	if (pm_iir & dev_priv->pm_rps_events) {
1454
		spin_lock(&dev_priv->irq_lock);
1455
		gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
I
Imre Deak 已提交
1456 1457 1458 1459
		if (dev_priv->rps.interrupts_enabled) {
			dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
			queue_work(dev_priv->wq, &dev_priv->rps.work);
		}
1460
		spin_unlock(&dev_priv->irq_lock);
1461 1462
	}

1463 1464 1465
	if (INTEL_INFO(dev_priv)->gen >= 8)
		return;

1466 1467
	if (HAS_VEBOX(dev_priv->dev)) {
		if (pm_iir & PM_VEBOX_USER_INTERRUPT)
C
Chris Wilson 已提交
1468
			notify_ring(&dev_priv->ring[VECS]);
B
Ben Widawsky 已提交
1469

1470 1471
		if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
			DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
B
Ben Widawsky 已提交
1472
	}
1473 1474
}

1475 1476 1477 1478 1479 1480 1481 1482
static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
{
	if (!drm_handle_vblank(dev, pipe))
		return false;

	return true;
}

1483 1484 1485
static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
1486
	u32 pipe_stats[I915_MAX_PIPES] = { };
1487 1488
	int pipe;

1489
	spin_lock(&dev_priv->irq_lock);
1490
	for_each_pipe(dev_priv, pipe) {
1491
		int reg;
1492
		u32 mask, iir_bit = 0;
1493

1494 1495 1496 1497 1498 1499 1500
		/*
		 * PIPESTAT bits get signalled even when the interrupt is
		 * disabled with the mask bits, and some of the status bits do
		 * not generate interrupts at all (like the underrun bit). Hence
		 * we need to be careful that we only handle what we want to
		 * handle.
		 */
1501 1502 1503

		/* fifo underruns are filterered in the underrun handler. */
		mask = PIPE_FIFO_UNDERRUN_STATUS;
1504 1505 1506 1507 1508 1509 1510 1511

		switch (pipe) {
		case PIPE_A:
			iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
			break;
		case PIPE_B:
			iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
			break;
1512 1513 1514
		case PIPE_C:
			iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
			break;
1515 1516 1517 1518 1519
		}
		if (iir & iir_bit)
			mask |= dev_priv->pipestat_irq_mask[pipe];

		if (!mask)
1520 1521 1522
			continue;

		reg = PIPESTAT(pipe);
1523 1524
		mask |= PIPESTAT_INT_ENABLE_MASK;
		pipe_stats[pipe] = I915_READ(reg) & mask;
1525 1526 1527 1528

		/*
		 * Clear the PIPE*STAT regs before the IIR
		 */
1529 1530
		if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
					PIPESTAT_INT_STATUS_MASK))
1531 1532
			I915_WRITE(reg, pipe_stats[pipe]);
	}
1533
	spin_unlock(&dev_priv->irq_lock);
1534

1535
	for_each_pipe(dev_priv, pipe) {
1536 1537 1538
		if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
		    intel_pipe_handle_vblank(dev, pipe))
			intel_check_page_flip(dev, pipe);
1539

1540
		if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
1541 1542 1543 1544 1545 1546 1547
			intel_prepare_page_flip(dev, pipe);
			intel_finish_page_flip(dev, pipe);
		}

		if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
			i9xx_pipe_crc_irq_handler(dev, pipe);

1548 1549
		if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1550 1551 1552 1553 1554 1555
	}

	if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
		gmbus_irq_handler(dev);
}

1556 1557 1558 1559
static void i9xx_hpd_irq_handler(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1560
	u32 pin_mask, long_mask;
1561

1562 1563
	if (!hotplug_status)
		return;
1564

1565 1566 1567 1568 1569 1570
	I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
	/*
	 * Make sure hotplug status is cleared before we clear IIR, or else we
	 * may miss hotplug events.
	 */
	POSTING_READ(PORT_HOTPLUG_STAT);
1571

1572 1573
	if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
		u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1574

1575 1576 1577
		intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
				   hotplug_trigger, hpd_status_g4x,
				   i9xx_port_hotplug_long_detect);
1578
		intel_hpd_irq_handler(dev, pin_mask, long_mask);
1579

1580
		if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1581
			dp_aux_irq_handler(dev);
1582 1583
	} else {
		u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1584

1585
		intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1586
				   hotplug_trigger, hpd_status_i915,
1587
				   i9xx_port_hotplug_long_detect);
1588
		intel_hpd_irq_handler(dev, pin_mask, long_mask);
1589
	}
1590 1591
}

1592
static irqreturn_t valleyview_irq_handler(int irq, void *arg)
J
Jesse Barnes 已提交
1593
{
1594
	struct drm_device *dev = arg;
1595
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
1596 1597 1598
	u32 iir, gt_iir, pm_iir;
	irqreturn_t ret = IRQ_NONE;

1599 1600 1601
	if (!intel_irqs_enabled(dev_priv))
		return IRQ_NONE;

J
Jesse Barnes 已提交
1602
	while (true) {
1603 1604
		/* Find, clear, then process each source of interrupt */

J
Jesse Barnes 已提交
1605
		gt_iir = I915_READ(GTIIR);
1606 1607 1608
		if (gt_iir)
			I915_WRITE(GTIIR, gt_iir);

J
Jesse Barnes 已提交
1609
		pm_iir = I915_READ(GEN6_PMIIR);
1610 1611 1612 1613 1614 1615 1616 1617 1618 1619
		if (pm_iir)
			I915_WRITE(GEN6_PMIIR, pm_iir);

		iir = I915_READ(VLV_IIR);
		if (iir) {
			/* Consume port before clearing IIR or we'll miss events */
			if (iir & I915_DISPLAY_PORT_INTERRUPT)
				i9xx_hpd_irq_handler(dev);
			I915_WRITE(VLV_IIR, iir);
		}
J
Jesse Barnes 已提交
1620 1621 1622 1623 1624 1625

		if (gt_iir == 0 && pm_iir == 0 && iir == 0)
			goto out;

		ret = IRQ_HANDLED;

1626 1627
		if (gt_iir)
			snb_gt_irq_handler(dev, dev_priv, gt_iir);
1628
		if (pm_iir)
1629
			gen6_rps_irq_handler(dev_priv, pm_iir);
1630 1631 1632
		/* Call regardless, as some status bits might not be
		 * signalled in iir */
		valleyview_pipestat_irq_handler(dev, iir);
J
Jesse Barnes 已提交
1633 1634 1635 1636 1637 1638
	}

out:
	return ret;
}

1639 1640
static irqreturn_t cherryview_irq_handler(int irq, void *arg)
{
1641
	struct drm_device *dev = arg;
1642 1643 1644 1645
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 master_ctl, iir;
	irqreturn_t ret = IRQ_NONE;

1646 1647 1648
	if (!intel_irqs_enabled(dev_priv))
		return IRQ_NONE;

1649 1650 1651
	for (;;) {
		master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
		iir = I915_READ(VLV_IIR);
1652

1653 1654
		if (master_ctl == 0 && iir == 0)
			break;
1655

1656 1657
		ret = IRQ_HANDLED;

1658
		I915_WRITE(GEN8_MASTER_IRQ, 0);
1659

1660
		/* Find, clear, then process each source of interrupt */
1661

1662 1663 1664 1665 1666 1667
		if (iir) {
			/* Consume port before clearing IIR or we'll miss events */
			if (iir & I915_DISPLAY_PORT_INTERRUPT)
				i9xx_hpd_irq_handler(dev);
			I915_WRITE(VLV_IIR, iir);
		}
1668

C
Chris Wilson 已提交
1669
		gen8_gt_irq_handler(dev_priv, master_ctl);
1670

1671 1672 1673
		/* Call regardless, as some status bits might not be
		 * signalled in iir */
		valleyview_pipestat_irq_handler(dev, iir);
1674

1675 1676 1677
		I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
		POSTING_READ(GEN8_MASTER_IRQ);
	}
1678

1679 1680 1681
	return ret;
}

1682
static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1683
{
1684
	struct drm_i915_private *dev_priv = dev->dev_private;
1685
	int pipe;
1686
	u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1687

1688 1689 1690 1691 1692
	if (hotplug_trigger) {
		u32 dig_hotplug_reg, pin_mask, long_mask;

		dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
		I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1693

1694 1695 1696
		intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
				   dig_hotplug_reg, hpd_ibx,
				   pch_port_hotplug_long_detect);
1697 1698
		intel_hpd_irq_handler(dev, pin_mask, long_mask);
	}
1699

1700 1701 1702
	if (pch_iir & SDE_AUDIO_POWER_MASK) {
		int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
			       SDE_AUDIO_POWER_SHIFT);
1703
		DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1704 1705
				 port_name(port));
	}
1706

1707 1708 1709
	if (pch_iir & SDE_AUX_MASK)
		dp_aux_irq_handler(dev);

1710
	if (pch_iir & SDE_GMBUS)
1711
		gmbus_irq_handler(dev);
1712 1713 1714 1715 1716 1717 1718 1719 1720 1721

	if (pch_iir & SDE_AUDIO_HDCP_MASK)
		DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");

	if (pch_iir & SDE_AUDIO_TRANS_MASK)
		DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");

	if (pch_iir & SDE_POISON)
		DRM_ERROR("PCH poison interrupt\n");

1722
	if (pch_iir & SDE_FDI_MASK)
1723
		for_each_pipe(dev_priv, pipe)
1724 1725 1726
			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
					 pipe_name(pipe),
					 I915_READ(FDI_RX_IIR(pipe)));
1727 1728 1729 1730 1731 1732 1733 1734

	if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
		DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");

	if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
		DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");

	if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1735
		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
1736 1737

	if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1738
		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
1739 1740 1741 1742 1743 1744
}

static void ivb_err_int_handler(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 err_int = I915_READ(GEN7_ERR_INT);
D
Daniel Vetter 已提交
1745
	enum pipe pipe;
1746

1747 1748 1749
	if (err_int & ERR_INT_POISON)
		DRM_ERROR("Poison interrupt\n");

1750
	for_each_pipe(dev_priv, pipe) {
1751 1752
		if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1753

D
Daniel Vetter 已提交
1754 1755
		if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
			if (IS_IVYBRIDGE(dev))
1756
				ivb_pipe_crc_irq_handler(dev, pipe);
D
Daniel Vetter 已提交
1757
			else
1758
				hsw_pipe_crc_irq_handler(dev, pipe);
D
Daniel Vetter 已提交
1759 1760
		}
	}
1761

1762 1763 1764 1765 1766 1767 1768 1769
	I915_WRITE(GEN7_ERR_INT, err_int);
}

static void cpt_serr_int_handler(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 serr_int = I915_READ(SERR_INT);

1770 1771 1772
	if (serr_int & SERR_INT_POISON)
		DRM_ERROR("PCH poison interrupt\n");

1773
	if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1774
		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
1775 1776

	if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1777
		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
1778 1779

	if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1780
		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
1781 1782

	I915_WRITE(SERR_INT, serr_int);
1783 1784
}

1785 1786
static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
{
1787
	struct drm_i915_private *dev_priv = dev->dev_private;
1788
	int pipe;
X
Xiong Zhang 已提交
1789 1790 1791 1792 1793 1794
	u32 hotplug_trigger;

	if (HAS_PCH_SPT(dev))
		hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT;
	else
		hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1795

1796 1797
	if (hotplug_trigger) {
		u32 dig_hotplug_reg, pin_mask, long_mask;
1798

1799 1800
		dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
		I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1801

X
Xiong Zhang 已提交
1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818
		if (HAS_PCH_SPT(dev)) {
			intel_get_hpd_pins(&pin_mask, &long_mask,
					   hotplug_trigger,
					   dig_hotplug_reg, hpd_spt,
					   pch_port_hotplug_long_detect);

			/* detect PORTE HP event */
			dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
			if (pch_port_hotplug_long_detect(PORT_E,
							 dig_hotplug_reg))
				long_mask |= 1 << HPD_PORT_E;
		} else
			intel_get_hpd_pins(&pin_mask, &long_mask,
					   hotplug_trigger,
					   dig_hotplug_reg, hpd_cpt,
					   pch_port_hotplug_long_detect);

1819 1820
		intel_hpd_irq_handler(dev, pin_mask, long_mask);
	}
1821

1822 1823 1824 1825 1826 1827
	if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
		int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
			       SDE_AUDIO_POWER_SHIFT_CPT);
		DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
				 port_name(port));
	}
1828 1829

	if (pch_iir & SDE_AUX_MASK_CPT)
1830
		dp_aux_irq_handler(dev);
1831 1832

	if (pch_iir & SDE_GMBUS_CPT)
1833
		gmbus_irq_handler(dev);
1834 1835 1836 1837 1838 1839 1840 1841

	if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
		DRM_DEBUG_DRIVER("Audio CP request interrupt\n");

	if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
		DRM_DEBUG_DRIVER("Audio CP change interrupt\n");

	if (pch_iir & SDE_FDI_MASK_CPT)
1842
		for_each_pipe(dev_priv, pipe)
1843 1844 1845
			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
					 pipe_name(pipe),
					 I915_READ(FDI_RX_IIR(pipe)));
1846 1847 1848

	if (pch_iir & SDE_ERROR_CPT)
		cpt_serr_int_handler(dev);
1849 1850
}

1851 1852 1853
static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
1854
	enum pipe pipe;
1855 1856 1857 1858 1859 1860 1861 1862 1863 1864

	if (de_iir & DE_AUX_CHANNEL_A)
		dp_aux_irq_handler(dev);

	if (de_iir & DE_GSE)
		intel_opregion_asle_intr(dev);

	if (de_iir & DE_POISON)
		DRM_ERROR("Poison interrupt\n");

1865
	for_each_pipe(dev_priv, pipe) {
1866 1867 1868
		if (de_iir & DE_PIPE_VBLANK(pipe) &&
		    intel_pipe_handle_vblank(dev, pipe))
			intel_check_page_flip(dev, pipe);
1869

1870
		if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
1871
			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1872

1873 1874
		if (de_iir & DE_PIPE_CRC_DONE(pipe))
			i9xx_pipe_crc_irq_handler(dev, pipe);
1875

1876 1877 1878 1879 1880
		/* plane/pipes map 1:1 on ilk+ */
		if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
			intel_prepare_page_flip(dev, pipe);
			intel_finish_page_flip_plane(dev, pipe);
		}
1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899
	}

	/* check event from PCH */
	if (de_iir & DE_PCH_EVENT) {
		u32 pch_iir = I915_READ(SDEIIR);

		if (HAS_PCH_CPT(dev))
			cpt_irq_handler(dev, pch_iir);
		else
			ibx_irq_handler(dev, pch_iir);

		/* should clear PCH hotplug event before clear CPU irq */
		I915_WRITE(SDEIIR, pch_iir);
	}

	if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
		ironlake_rps_change_irq_handler(dev);
}

1900 1901 1902
static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
1903
	enum pipe pipe;
1904 1905 1906 1907 1908 1909 1910 1911 1912 1913

	if (de_iir & DE_ERR_INT_IVB)
		ivb_err_int_handler(dev);

	if (de_iir & DE_AUX_CHANNEL_A_IVB)
		dp_aux_irq_handler(dev);

	if (de_iir & DE_GSE_IVB)
		intel_opregion_asle_intr(dev);

1914
	for_each_pipe(dev_priv, pipe) {
1915 1916 1917
		if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
		    intel_pipe_handle_vblank(dev, pipe))
			intel_check_page_flip(dev, pipe);
1918 1919

		/* plane/pipes map 1:1 on ilk+ */
1920 1921 1922
		if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
			intel_prepare_page_flip(dev, pipe);
			intel_finish_page_flip_plane(dev, pipe);
1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936
		}
	}

	/* check event from PCH */
	if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
		u32 pch_iir = I915_READ(SDEIIR);

		cpt_irq_handler(dev, pch_iir);

		/* clear PCH hotplug event before clear CPU irq */
		I915_WRITE(SDEIIR, pch_iir);
	}
}

1937 1938 1939 1940 1941 1942 1943 1944
/*
 * To handle irqs with the minimum potential races with fresh interrupts, we:
 * 1 - Disable Master Interrupt Control.
 * 2 - Find the source(s) of the interrupt.
 * 3 - Clear the Interrupt Identity bits (IIR).
 * 4 - Process the interrupt(s) that had bits set in the IIRs.
 * 5 - Re-enable Master Interrupt Control.
 */
1945
static irqreturn_t ironlake_irq_handler(int irq, void *arg)
1946
{
1947
	struct drm_device *dev = arg;
1948
	struct drm_i915_private *dev_priv = dev->dev_private;
1949
	u32 de_iir, gt_iir, de_ier, sde_ier = 0;
1950
	irqreturn_t ret = IRQ_NONE;
1951

1952 1953 1954
	if (!intel_irqs_enabled(dev_priv))
		return IRQ_NONE;

1955 1956
	/* We get interrupts on unclaimed registers, so check for this before we
	 * do any I915_{READ,WRITE}. */
1957
	intel_uncore_check_errors(dev);
1958

1959 1960 1961
	/* disable master interrupt before clearing iir  */
	de_ier = I915_READ(DEIER);
	I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
1962
	POSTING_READ(DEIER);
1963

1964 1965 1966 1967 1968
	/* Disable south interrupts. We'll only write to SDEIIR once, so further
	 * interrupts will will be stored on its back queue, and then we'll be
	 * able to process them after we restore SDEIER (as soon as we restore
	 * it, we'll get an interrupt if SDEIIR still has something to process
	 * due to its back queue). */
1969 1970 1971 1972 1973
	if (!HAS_PCH_NOP(dev)) {
		sde_ier = I915_READ(SDEIER);
		I915_WRITE(SDEIER, 0);
		POSTING_READ(SDEIER);
	}
1974

1975 1976
	/* Find, clear, then process each source of interrupt */

1977
	gt_iir = I915_READ(GTIIR);
1978
	if (gt_iir) {
1979 1980
		I915_WRITE(GTIIR, gt_iir);
		ret = IRQ_HANDLED;
1981
		if (INTEL_INFO(dev)->gen >= 6)
1982
			snb_gt_irq_handler(dev, dev_priv, gt_iir);
1983 1984
		else
			ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1985 1986
	}

1987 1988
	de_iir = I915_READ(DEIIR);
	if (de_iir) {
1989 1990
		I915_WRITE(DEIIR, de_iir);
		ret = IRQ_HANDLED;
1991 1992 1993 1994
		if (INTEL_INFO(dev)->gen >= 7)
			ivb_display_irq_handler(dev, de_iir);
		else
			ilk_display_irq_handler(dev, de_iir);
1995 1996
	}

1997 1998 1999 2000 2001
	if (INTEL_INFO(dev)->gen >= 6) {
		u32 pm_iir = I915_READ(GEN6_PMIIR);
		if (pm_iir) {
			I915_WRITE(GEN6_PMIIR, pm_iir);
			ret = IRQ_HANDLED;
2002
			gen6_rps_irq_handler(dev_priv, pm_iir);
2003
		}
2004
	}
2005 2006 2007

	I915_WRITE(DEIER, de_ier);
	POSTING_READ(DEIER);
2008 2009 2010 2011
	if (!HAS_PCH_NOP(dev)) {
		I915_WRITE(SDEIER, sde_ier);
		POSTING_READ(SDEIER);
	}
2012 2013 2014 2015

	return ret;
}

2016 2017 2018
static void bxt_hpd_handler(struct drm_device *dev, uint32_t iir_status)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2019 2020
	u32 hp_control, hp_trigger;
	u32 pin_mask, long_mask;
2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034

	/* Get the status */
	hp_trigger = iir_status & BXT_DE_PORT_HOTPLUG_MASK;
	hp_control = I915_READ(BXT_HOTPLUG_CTL);

	/* Hotplug not enabled ? */
	if (!(hp_control & BXT_HOTPLUG_CTL_MASK)) {
		DRM_ERROR("Interrupt when HPD disabled\n");
		return;
	}

	/* Clear sticky bits in hpd status */
	I915_WRITE(BXT_HOTPLUG_CTL, hp_control);

2035
	intel_get_hpd_pins(&pin_mask, &long_mask, hp_trigger, hp_control,
2036
			   hpd_bxt, bxt_port_hotplug_long_detect);
2037
	intel_hpd_irq_handler(dev, pin_mask, long_mask);
2038 2039
}

2040 2041 2042 2043 2044 2045 2046
static irqreturn_t gen8_irq_handler(int irq, void *arg)
{
	struct drm_device *dev = arg;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 master_ctl;
	irqreturn_t ret = IRQ_NONE;
	uint32_t tmp = 0;
2047
	enum pipe pipe;
J
Jesse Barnes 已提交
2048 2049
	u32 aux_mask = GEN8_AUX_CHANNEL_A;

2050 2051 2052
	if (!intel_irqs_enabled(dev_priv))
		return IRQ_NONE;

J
Jesse Barnes 已提交
2053 2054 2055
	if (IS_GEN9(dev))
		aux_mask |=  GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
			GEN9_AUX_CHANNEL_D;
2056

2057
	master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
2058 2059 2060 2061
	master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
	if (!master_ctl)
		return IRQ_NONE;

2062
	I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
2063

2064 2065
	/* Find, clear, then process each source of interrupt */

C
Chris Wilson 已提交
2066
	ret = gen8_gt_irq_handler(dev_priv, master_ctl);
2067 2068 2069 2070 2071 2072

	if (master_ctl & GEN8_DE_MISC_IRQ) {
		tmp = I915_READ(GEN8_DE_MISC_IIR);
		if (tmp) {
			I915_WRITE(GEN8_DE_MISC_IIR, tmp);
			ret = IRQ_HANDLED;
2073 2074 2075 2076
			if (tmp & GEN8_DE_MISC_GSE)
				intel_opregion_asle_intr(dev);
			else
				DRM_ERROR("Unexpected DE Misc interrupt\n");
2077
		}
2078 2079
		else
			DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2080 2081
	}

2082 2083 2084
	if (master_ctl & GEN8_DE_PORT_IRQ) {
		tmp = I915_READ(GEN8_DE_PORT_IIR);
		if (tmp) {
2085 2086
			bool found = false;

2087 2088
			I915_WRITE(GEN8_DE_PORT_IIR, tmp);
			ret = IRQ_HANDLED;
J
Jesse Barnes 已提交
2089

2090
			if (tmp & aux_mask) {
2091
				dp_aux_irq_handler(dev);
2092 2093 2094 2095 2096 2097 2098 2099
				found = true;
			}

			if (IS_BROXTON(dev) && tmp & BXT_DE_PORT_HOTPLUG_MASK) {
				bxt_hpd_handler(dev, tmp);
				found = true;
			}

S
Shashank Sharma 已提交
2100 2101 2102 2103 2104
			if (IS_BROXTON(dev) && (tmp & BXT_DE_PORT_GMBUS)) {
				gmbus_irq_handler(dev);
				found = true;
			}

2105
			if (!found)
2106
				DRM_ERROR("Unexpected DE Port interrupt\n");
2107
		}
2108 2109
		else
			DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2110 2111
	}

2112
	for_each_pipe(dev_priv, pipe) {
2113
		uint32_t pipe_iir, flip_done = 0, fault_errors = 0;
2114

2115 2116
		if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
			continue;
2117

2118 2119 2120 2121
		pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
		if (pipe_iir) {
			ret = IRQ_HANDLED;
			I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2122

2123 2124 2125
			if (pipe_iir & GEN8_PIPE_VBLANK &&
			    intel_pipe_handle_vblank(dev, pipe))
				intel_check_page_flip(dev, pipe);
2126

2127 2128 2129 2130 2131 2132
			if (IS_GEN9(dev))
				flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE;
			else
				flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE;

			if (flip_done) {
2133 2134 2135 2136 2137 2138 2139
				intel_prepare_page_flip(dev, pipe);
				intel_finish_page_flip_plane(dev, pipe);
			}

			if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
				hsw_pipe_crc_irq_handler(dev, pipe);

2140 2141 2142
			if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN)
				intel_cpu_fifo_underrun_irq_handler(dev_priv,
								    pipe);
2143

2144 2145 2146 2147 2148 2149 2150

			if (IS_GEN9(dev))
				fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
			else
				fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS;

			if (fault_errors)
2151 2152 2153
				DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
					  pipe_name(pipe),
					  pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2154
		} else
2155 2156 2157
			DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
	}

2158 2159
	if (HAS_PCH_SPLIT(dev) && !HAS_PCH_NOP(dev) &&
	    master_ctl & GEN8_DE_PCH_IRQ) {
2160 2161 2162 2163 2164 2165 2166 2167 2168
		/*
		 * FIXME(BDW): Assume for now that the new interrupt handling
		 * scheme also closed the SDE interrupt handling race we've seen
		 * on older pch-split platforms. But this needs testing.
		 */
		u32 pch_iir = I915_READ(SDEIIR);
		if (pch_iir) {
			I915_WRITE(SDEIIR, pch_iir);
			ret = IRQ_HANDLED;
2169 2170 2171 2172
			cpt_irq_handler(dev, pch_iir);
		} else
			DRM_ERROR("The master control interrupt lied (SDE)!\n");

2173 2174
	}

2175 2176
	I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
	POSTING_READ_FW(GEN8_MASTER_IRQ);
2177 2178 2179 2180

	return ret;
}

2181 2182 2183
static void i915_error_wake_up(struct drm_i915_private *dev_priv,
			       bool reset_completed)
{
2184
	struct intel_engine_cs *ring;
2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208
	int i;

	/*
	 * Notify all waiters for GPU completion events that reset state has
	 * been changed, and that they need to restart their wait after
	 * checking for potential errors (and bail out to drop locks if there is
	 * a gpu reset pending so that i915_error_work_func can acquire them).
	 */

	/* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
	for_each_ring(ring, dev_priv, i)
		wake_up_all(&ring->irq_queue);

	/* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
	wake_up_all(&dev_priv->pending_flip_queue);

	/*
	 * Signal tasks blocked in i915_gem_wait_for_error that the pending
	 * reset state is cleared.
	 */
	if (reset_completed)
		wake_up_all(&dev_priv->gpu_error.reset_queue);
}

2209
/**
2210
 * i915_reset_and_wakeup - do process context error handling work
2211 2212 2213 2214
 *
 * Fire an error uevent so userspace can see that a hang or error
 * was detected.
 */
2215
static void i915_reset_and_wakeup(struct drm_device *dev)
2216
{
2217 2218
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct i915_gpu_error *error = &dev_priv->gpu_error;
2219 2220 2221
	char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
	char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
	char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2222
	int ret;
2223

2224
	kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2225

2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236
	/*
	 * Note that there's only one work item which does gpu resets, so we
	 * need not worry about concurrent gpu resets potentially incrementing
	 * error->reset_counter twice. We only need to take care of another
	 * racing irq/hangcheck declaring the gpu dead for a second time. A
	 * quick check for that is good enough: schedule_work ensures the
	 * correct ordering between hang detection and this work item, and since
	 * the reset in-progress bit is only ever set by code outside of this
	 * work we don't need to worry about any other races.
	 */
	if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2237
		DRM_DEBUG_DRIVER("resetting chip\n");
2238
		kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2239
				   reset_event);
2240

2241 2242 2243 2244 2245 2246 2247 2248
		/*
		 * In most cases it's guaranteed that we get here with an RPM
		 * reference held, for example because there is a pending GPU
		 * request that won't finish until the reset is done. This
		 * isn't the case at least when we get here by doing a
		 * simulated reset via debugs, so get an RPM reference.
		 */
		intel_runtime_pm_get(dev_priv);
2249 2250 2251

		intel_prepare_reset(dev);

2252 2253 2254 2255 2256 2257
		/*
		 * All state reset _must_ be completed before we update the
		 * reset counter, for otherwise waiters might miss the reset
		 * pending state and not properly drop locks, resulting in
		 * deadlocks with the reset work.
		 */
2258 2259
		ret = i915_reset(dev);

2260
		intel_finish_reset(dev);
2261

2262 2263
		intel_runtime_pm_put(dev_priv);

2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274
		if (ret == 0) {
			/*
			 * After all the gem state is reset, increment the reset
			 * counter and wake up everyone waiting for the reset to
			 * complete.
			 *
			 * Since unlock operations are a one-sided barrier only,
			 * we need to insert a barrier here to order any seqno
			 * updates before
			 * the counter increment.
			 */
2275
			smp_mb__before_atomic();
2276 2277
			atomic_inc(&dev_priv->gpu_error.reset_counter);

2278
			kobject_uevent_env(&dev->primary->kdev->kobj,
2279
					   KOBJ_CHANGE, reset_done_event);
2280
		} else {
2281
			atomic_or(I915_WEDGED, &error->reset_counter);
2282
		}
2283

2284 2285 2286 2287 2288
		/*
		 * Note: The wake_up also serves as a memory barrier so that
		 * waiters see the update value of the reset counter atomic_t.
		 */
		i915_error_wake_up(dev_priv, true);
2289
	}
2290 2291
}

2292
static void i915_report_and_clear_eir(struct drm_device *dev)
2293 2294
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2295
	uint32_t instdone[I915_NUM_INSTDONE_REG];
2296
	u32 eir = I915_READ(EIR);
2297
	int pipe, i;
2298

2299 2300
	if (!eir)
		return;
2301

2302
	pr_err("render error detected, EIR: 0x%08x\n", eir);
2303

2304 2305
	i915_get_extra_instdone(dev, instdone);

2306 2307 2308 2309
	if (IS_G4X(dev)) {
		if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
			u32 ipeir = I915_READ(IPEIR_I965);

2310 2311
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2312 2313
			for (i = 0; i < ARRAY_SIZE(instdone); i++)
				pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2314 2315
			pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2316
			I915_WRITE(IPEIR_I965, ipeir);
2317
			POSTING_READ(IPEIR_I965);
2318 2319 2320
		}
		if (eir & GM45_ERROR_PAGE_TABLE) {
			u32 pgtbl_err = I915_READ(PGTBL_ER);
2321 2322
			pr_err("page table error\n");
			pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2323
			I915_WRITE(PGTBL_ER, pgtbl_err);
2324
			POSTING_READ(PGTBL_ER);
2325 2326 2327
		}
	}

2328
	if (!IS_GEN2(dev)) {
2329 2330
		if (eir & I915_ERROR_PAGE_TABLE) {
			u32 pgtbl_err = I915_READ(PGTBL_ER);
2331 2332
			pr_err("page table error\n");
			pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2333
			I915_WRITE(PGTBL_ER, pgtbl_err);
2334
			POSTING_READ(PGTBL_ER);
2335 2336 2337 2338
		}
	}

	if (eir & I915_ERROR_MEMORY_REFRESH) {
2339
		pr_err("memory refresh error:\n");
2340
		for_each_pipe(dev_priv, pipe)
2341
			pr_err("pipe %c stat: 0x%08x\n",
2342
			       pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2343 2344 2345
		/* pipestat has already been acked */
	}
	if (eir & I915_ERROR_INSTRUCTION) {
2346 2347
		pr_err("instruction error\n");
		pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
2348 2349
		for (i = 0; i < ARRAY_SIZE(instdone); i++)
			pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2350
		if (INTEL_INFO(dev)->gen < 4) {
2351 2352
			u32 ipeir = I915_READ(IPEIR);

2353 2354 2355
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
2356
			I915_WRITE(IPEIR, ipeir);
2357
			POSTING_READ(IPEIR);
2358 2359 2360
		} else {
			u32 ipeir = I915_READ(IPEIR_I965);

2361 2362 2363 2364
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
			pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2365
			I915_WRITE(IPEIR_I965, ipeir);
2366
			POSTING_READ(IPEIR_I965);
2367 2368 2369 2370
		}
	}

	I915_WRITE(EIR, eir);
2371
	POSTING_READ(EIR);
2372 2373 2374 2375 2376 2377 2378 2379 2380 2381
	eir = I915_READ(EIR);
	if (eir) {
		/*
		 * some errors might have become stuck,
		 * mask them.
		 */
		DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
		I915_WRITE(EMR, I915_READ(EMR) | eir);
		I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
	}
2382 2383 2384
}

/**
2385
 * i915_handle_error - handle a gpu error
2386 2387
 * @dev: drm device
 *
2388
 * Do some basic checking of regsiter state at error time and
2389 2390 2391 2392 2393
 * dump it to the syslog.  Also call i915_capture_error_state() to make
 * sure we get a record and make it available in debugfs.  Fire a uevent
 * so userspace knows something bad happened (should trigger collection
 * of a ring dump etc.).
 */
2394 2395
void i915_handle_error(struct drm_device *dev, bool wedged,
		       const char *fmt, ...)
2396 2397
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2398 2399
	va_list args;
	char error_msg[80];
2400

2401 2402 2403 2404 2405
	va_start(args, fmt);
	vscnprintf(error_msg, sizeof(error_msg), fmt, args);
	va_end(args);

	i915_capture_error_state(dev, wedged, error_msg);
2406
	i915_report_and_clear_eir(dev);
2407

2408
	if (wedged) {
2409
		atomic_or(I915_RESET_IN_PROGRESS_FLAG,
2410
				&dev_priv->gpu_error.reset_counter);
2411

2412
		/*
2413 2414 2415
		 * Wakeup waiting processes so that the reset function
		 * i915_reset_and_wakeup doesn't deadlock trying to grab
		 * various locks. By bumping the reset counter first, the woken
2416 2417 2418 2419 2420 2421 2422 2423
		 * processes will see a reset in progress and back off,
		 * releasing their locks and then wait for the reset completion.
		 * We must do this for _all_ gpu waiters that might hold locks
		 * that the reset work needs to acquire.
		 *
		 * Note: The wake_up serves as the required memory barrier to
		 * ensure that the waiters see the updated value of the reset
		 * counter atomic_t.
2424
		 */
2425
		i915_error_wake_up(dev_priv, false);
2426 2427
	}

2428
	i915_reset_and_wakeup(dev);
2429 2430
}

2431 2432 2433
/* Called from drm generic code, passed 'crtc' which
 * we use as a pipe index
 */
2434
static int i915_enable_vblank(struct drm_device *dev, int pipe)
2435
{
2436
	struct drm_i915_private *dev_priv = dev->dev_private;
2437
	unsigned long irqflags;
2438

2439
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2440
	if (INTEL_INFO(dev)->gen >= 4)
2441
		i915_enable_pipestat(dev_priv, pipe,
2442
				     PIPE_START_VBLANK_INTERRUPT_STATUS);
2443
	else
2444
		i915_enable_pipestat(dev_priv, pipe,
2445
				     PIPE_VBLANK_INTERRUPT_STATUS);
2446
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2447

2448 2449 2450
	return 0;
}

2451
static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2452
{
2453
	struct drm_i915_private *dev_priv = dev->dev_private;
2454
	unsigned long irqflags;
2455
	uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2456
						     DE_PIPE_VBLANK(pipe);
2457 2458

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2459
	ironlake_enable_display_irq(dev_priv, bit);
2460 2461 2462 2463 2464
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

	return 0;
}

J
Jesse Barnes 已提交
2465 2466
static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
{
2467
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
2468 2469 2470
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2471
	i915_enable_pipestat(dev_priv, pipe,
2472
			     PIPE_START_VBLANK_INTERRUPT_STATUS);
J
Jesse Barnes 已提交
2473 2474 2475 2476 2477
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

	return 0;
}

2478 2479 2480 2481 2482 2483
static int gen8_enable_vblank(struct drm_device *dev, int pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2484 2485 2486
	dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
	I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
	POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2487 2488 2489 2490
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
	return 0;
}

2491 2492 2493
/* Called from drm generic code, passed 'crtc' which
 * we use as a pipe index
 */
2494
static void i915_disable_vblank(struct drm_device *dev, int pipe)
2495
{
2496
	struct drm_i915_private *dev_priv = dev->dev_private;
2497
	unsigned long irqflags;
2498

2499
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2500
	i915_disable_pipestat(dev_priv, pipe,
2501 2502
			      PIPE_VBLANK_INTERRUPT_STATUS |
			      PIPE_START_VBLANK_INTERRUPT_STATUS);
2503 2504 2505
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

2506
static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2507
{
2508
	struct drm_i915_private *dev_priv = dev->dev_private;
2509
	unsigned long irqflags;
2510
	uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2511
						     DE_PIPE_VBLANK(pipe);
2512 2513

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2514
	ironlake_disable_display_irq(dev_priv, bit);
2515 2516 2517
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

J
Jesse Barnes 已提交
2518 2519
static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
{
2520
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
2521 2522 2523
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2524
	i915_disable_pipestat(dev_priv, pipe,
2525
			      PIPE_START_VBLANK_INTERRUPT_STATUS);
J
Jesse Barnes 已提交
2526 2527 2528
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

2529 2530 2531 2532 2533 2534
static void gen8_disable_vblank(struct drm_device *dev, int pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2535 2536 2537
	dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
	I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
	POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2538 2539 2540
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

2541
static bool
2542
ring_idle(struct intel_engine_cs *ring, u32 seqno)
2543 2544
{
	return (list_empty(&ring->request_list) ||
2545
		i915_seqno_passed(seqno, ring->last_submitted_seqno));
B
Ben Gamari 已提交
2546 2547
}

2548 2549 2550 2551
static bool
ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
{
	if (INTEL_INFO(dev)->gen >= 8) {
2552
		return (ipehr >> 23) == 0x1c;
2553 2554 2555 2556 2557 2558 2559
	} else {
		ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
		return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
				 MI_SEMAPHORE_REGISTER);
	}
}

2560
static struct intel_engine_cs *
2561
semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset)
2562 2563
{
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
2564
	struct intel_engine_cs *signaller;
2565 2566 2567
	int i;

	if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
2568 2569 2570 2571 2572 2573 2574
		for_each_ring(signaller, dev_priv, i) {
			if (ring == signaller)
				continue;

			if (offset == signaller->semaphore.signal_ggtt[ring->id])
				return signaller;
		}
2575 2576 2577 2578 2579 2580 2581
	} else {
		u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;

		for_each_ring(signaller, dev_priv, i) {
			if(ring == signaller)
				continue;

2582
			if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
2583 2584 2585 2586
				return signaller;
		}
	}

2587 2588
	DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
		  ring->id, ipehr, offset);
2589 2590 2591 2592

	return NULL;
}

2593 2594
static struct intel_engine_cs *
semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
2595 2596
{
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
2597
	u32 cmd, ipehr, head;
2598 2599
	u64 offset = 0;
	int i, backwards;
2600 2601

	ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2602
	if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
2603
		return NULL;
2604

2605 2606 2607
	/*
	 * HEAD is likely pointing to the dword after the actual command,
	 * so scan backwards until we find the MBOX. But limit it to just 3
2608 2609
	 * or 4 dwords depending on the semaphore wait command size.
	 * Note that we don't care about ACTHD here since that might
2610 2611
	 * point at at batch, and semaphores are always emitted into the
	 * ringbuffer itself.
2612
	 */
2613
	head = I915_READ_HEAD(ring) & HEAD_ADDR;
2614
	backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4;
2615

2616
	for (i = backwards; i; --i) {
2617 2618 2619 2620 2621
		/*
		 * Be paranoid and presume the hw has gone off into the wild -
		 * our ring is smaller than what the hardware (and hence
		 * HEAD_ADDR) allows. Also handles wrap-around.
		 */
2622
		head &= ring->buffer->size - 1;
2623 2624

		/* This here seems to blow up */
2625
		cmd = ioread32(ring->buffer->virtual_start + head);
2626 2627 2628
		if (cmd == ipehr)
			break;

2629 2630
		head -= 4;
	}
2631

2632 2633
	if (!i)
		return NULL;
2634

2635
	*seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
2636 2637 2638 2639 2640 2641
	if (INTEL_INFO(ring->dev)->gen >= 8) {
		offset = ioread32(ring->buffer->virtual_start + head + 12);
		offset <<= 32;
		offset = ioread32(ring->buffer->virtual_start + head + 8);
	}
	return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
2642 2643
}

2644
static int semaphore_passed(struct intel_engine_cs *ring)
2645 2646
{
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
2647
	struct intel_engine_cs *signaller;
2648
	u32 seqno;
2649

2650
	ring->hangcheck.deadlock++;
2651 2652

	signaller = semaphore_waits_for(ring, &seqno);
2653 2654 2655 2656 2657
	if (signaller == NULL)
		return -1;

	/* Prevent pathological recursion due to driver bugs */
	if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
2658 2659
		return -1;

2660 2661 2662
	if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
		return 1;

2663 2664 2665
	/* cursory check for an unkickable deadlock */
	if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
	    semaphore_passed(signaller) < 0)
2666 2667 2668
		return -1;

	return 0;
2669 2670 2671 2672
}

static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
{
2673
	struct intel_engine_cs *ring;
2674 2675 2676
	int i;

	for_each_ring(ring, dev_priv, i)
2677
		ring->hangcheck.deadlock = 0;
2678 2679
}

2680
static enum intel_ring_hangcheck_action
2681
ring_stuck(struct intel_engine_cs *ring, u64 acthd)
2682 2683 2684
{
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2685 2686
	u32 tmp;

2687 2688 2689 2690 2691 2692 2693 2694
	if (acthd != ring->hangcheck.acthd) {
		if (acthd > ring->hangcheck.max_acthd) {
			ring->hangcheck.max_acthd = acthd;
			return HANGCHECK_ACTIVE;
		}

		return HANGCHECK_ACTIVE_LOOP;
	}
2695

2696
	if (IS_GEN2(dev))
2697
		return HANGCHECK_HUNG;
2698 2699 2700 2701 2702 2703 2704

	/* Is the chip hanging on a WAIT_FOR_EVENT?
	 * If so we can simply poke the RB_WAIT bit
	 * and break the hang. This should work on
	 * all but the second generation chipsets.
	 */
	tmp = I915_READ_CTL(ring);
2705
	if (tmp & RING_WAIT) {
2706 2707 2708
		i915_handle_error(dev, false,
				  "Kicking stuck wait on %s",
				  ring->name);
2709
		I915_WRITE_CTL(ring, tmp);
2710
		return HANGCHECK_KICK;
2711 2712 2713 2714 2715
	}

	if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
		switch (semaphore_passed(ring)) {
		default:
2716
			return HANGCHECK_HUNG;
2717
		case 1:
2718 2719 2720
			i915_handle_error(dev, false,
					  "Kicking stuck semaphore on %s",
					  ring->name);
2721
			I915_WRITE_CTL(ring, tmp);
2722
			return HANGCHECK_KICK;
2723
		case 0:
2724
			return HANGCHECK_WAIT;
2725
		}
2726
	}
2727

2728
	return HANGCHECK_HUNG;
2729 2730
}

2731
/*
B
Ben Gamari 已提交
2732
 * This is called when the chip hasn't reported back with completed
2733 2734 2735 2736 2737
 * batchbuffers in a long time. We keep track per ring seqno progress and
 * if there are no progress, hangcheck score for that ring is increased.
 * Further, acthd is inspected to see if the ring is stuck. On stuck case
 * we kick the ring. If we see no progress on three subsequent calls
 * we assume chip is wedged and try to fix it by resetting the chip.
B
Ben Gamari 已提交
2738
 */
2739
static void i915_hangcheck_elapsed(struct work_struct *work)
B
Ben Gamari 已提交
2740
{
2741 2742 2743 2744
	struct drm_i915_private *dev_priv =
		container_of(work, typeof(*dev_priv),
			     gpu_error.hangcheck_work.work);
	struct drm_device *dev = dev_priv->dev;
2745
	struct intel_engine_cs *ring;
2746
	int i;
2747
	int busy_count = 0, rings_hung = 0;
2748 2749 2750 2751
	bool stuck[I915_NUM_RINGS] = { 0 };
#define BUSY 1
#define KICK 5
#define HUNG 20
2752

2753
	if (!i915.enable_hangcheck)
2754 2755
		return;

2756
	for_each_ring(ring, dev_priv, i) {
2757 2758
		u64 acthd;
		u32 seqno;
2759
		bool busy = true;
2760

2761 2762
		semaphore_clear_deadlocks(dev_priv);

2763 2764
		seqno = ring->get_seqno(ring, false);
		acthd = intel_ring_get_active_head(ring);
2765

2766
		if (ring->hangcheck.seqno == seqno) {
2767
			if (ring_idle(ring, seqno)) {
2768 2769
				ring->hangcheck.action = HANGCHECK_IDLE;

2770 2771
				if (waitqueue_active(&ring->irq_queue)) {
					/* Issue a wake-up to catch stuck h/w. */
2772
					if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2773 2774 2775 2776 2777 2778
						if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
							DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
								  ring->name);
						else
							DRM_INFO("Fake missed irq on %s\n",
								 ring->name);
2779 2780 2781 2782
						wake_up_all(&ring->irq_queue);
					}
					/* Safeguard against driver failure */
					ring->hangcheck.score += BUSY;
2783 2784
				} else
					busy = false;
2785
			} else {
2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800
				/* We always increment the hangcheck score
				 * if the ring is busy and still processing
				 * the same request, so that no single request
				 * can run indefinitely (such as a chain of
				 * batches). The only time we do not increment
				 * the hangcheck score on this ring, if this
				 * ring is in a legitimate wait for another
				 * ring. In that case the waiting ring is a
				 * victim and we want to be sure we catch the
				 * right culprit. Then every time we do kick
				 * the ring, add a small increment to the
				 * score so that we can catch a batch that is
				 * being repeatedly kicked and so responsible
				 * for stalling the machine.
				 */
2801 2802 2803 2804
				ring->hangcheck.action = ring_stuck(ring,
								    acthd);

				switch (ring->hangcheck.action) {
2805
				case HANGCHECK_IDLE:
2806 2807
				case HANGCHECK_WAIT:
				case HANGCHECK_ACTIVE:
2808 2809
					break;
				case HANGCHECK_ACTIVE_LOOP:
2810
					ring->hangcheck.score += BUSY;
2811
					break;
2812
				case HANGCHECK_KICK:
2813
					ring->hangcheck.score += KICK;
2814
					break;
2815
				case HANGCHECK_HUNG:
2816
					ring->hangcheck.score += HUNG;
2817 2818 2819
					stuck[i] = true;
					break;
				}
2820
			}
2821
		} else {
2822 2823
			ring->hangcheck.action = HANGCHECK_ACTIVE;

2824 2825 2826 2827 2828
			/* Gradually reduce the count so that we catch DoS
			 * attempts across multiple batches.
			 */
			if (ring->hangcheck.score > 0)
				ring->hangcheck.score--;
2829 2830

			ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0;
2831 2832
		}

2833 2834
		ring->hangcheck.seqno = seqno;
		ring->hangcheck.acthd = acthd;
2835
		busy_count += busy;
2836
	}
2837

2838
	for_each_ring(ring, dev_priv, i) {
2839
		if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
2840 2841 2842
			DRM_INFO("%s on %s\n",
				 stuck[i] ? "stuck" : "no progress",
				 ring->name);
2843
			rings_hung++;
2844 2845 2846
		}
	}

2847
	if (rings_hung)
2848
		return i915_handle_error(dev, true, "Ring hung");
B
Ben Gamari 已提交
2849

2850 2851 2852
	if (busy_count)
		/* Reset timer case chip hangs without another request
		 * being added */
2853 2854 2855 2856 2857
		i915_queue_hangcheck(dev);
}

void i915_queue_hangcheck(struct drm_device *dev)
{
2858
	struct i915_gpu_error *e = &to_i915(dev)->gpu_error;
2859

2860
	if (!i915.enable_hangcheck)
2861 2862
		return;

2863 2864 2865 2866 2867 2868 2869
	/* Don't continually defer the hangcheck so that it is always run at
	 * least once after work has been scheduled on any ring. Otherwise,
	 * we will ignore a hung ring if a second ring is kept busy.
	 */

	queue_delayed_work(e->hangcheck_wq, &e->hangcheck_work,
			   round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES));
B
Ben Gamari 已提交
2870 2871
}

2872
static void ibx_irq_reset(struct drm_device *dev)
P
Paulo Zanoni 已提交
2873 2874 2875 2876 2877 2878
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (HAS_PCH_NOP(dev))
		return;

2879
	GEN5_IRQ_RESET(SDE);
2880 2881 2882

	if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
		I915_WRITE(SERR_INT, 0xffffffff);
P
Paulo Zanoni 已提交
2883
}
2884

P
Paulo Zanoni 已提交
2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900
/*
 * SDEIER is also touched by the interrupt handler to work around missed PCH
 * interrupts. Hence we can't update it after the interrupt handler is enabled -
 * instead we unconditionally enable all PCH interrupt sources here, but then
 * only unmask them as needed with SDEIMR.
 *
 * This function needs to be called before interrupts are enabled.
 */
static void ibx_irq_pre_postinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (HAS_PCH_NOP(dev))
		return;

	WARN_ON(I915_READ(SDEIER) != 0);
P
Paulo Zanoni 已提交
2901 2902 2903 2904
	I915_WRITE(SDEIER, 0xffffffff);
	POSTING_READ(SDEIER);
}

2905
static void gen5_gt_irq_reset(struct drm_device *dev)
2906 2907 2908
{
	struct drm_i915_private *dev_priv = dev->dev_private;

2909
	GEN5_IRQ_RESET(GT);
P
Paulo Zanoni 已提交
2910
	if (INTEL_INFO(dev)->gen >= 6)
2911
		GEN5_IRQ_RESET(GEN6_PM);
2912 2913
}

L
Linus Torvalds 已提交
2914 2915
/* drm_dma.h hooks
*/
P
Paulo Zanoni 已提交
2916
static void ironlake_irq_reset(struct drm_device *dev)
2917
{
2918
	struct drm_i915_private *dev_priv = dev->dev_private;
2919

2920
	I915_WRITE(HWSTAM, 0xffffffff);
2921

2922
	GEN5_IRQ_RESET(DE);
2923 2924
	if (IS_GEN7(dev))
		I915_WRITE(GEN7_ERR_INT, 0xffffffff);
2925

2926
	gen5_gt_irq_reset(dev);
2927

2928
	ibx_irq_reset(dev);
2929
}
2930

2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943
static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
{
	enum pipe pipe;

	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));

	for_each_pipe(dev_priv, pipe)
		I915_WRITE(PIPESTAT(pipe), 0xffff);

	GEN5_IRQ_RESET(VLV_);
}

J
Jesse Barnes 已提交
2944 2945
static void valleyview_irq_preinstall(struct drm_device *dev)
{
2946
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
2947 2948 2949 2950 2951 2952 2953

	/* VLV magic */
	I915_WRITE(VLV_IMR, 0);
	I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
	I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
	I915_WRITE(RING_IMR(BLT_RING_BASE), 0);

2954
	gen5_gt_irq_reset(dev);
J
Jesse Barnes 已提交
2955

2956
	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
J
Jesse Barnes 已提交
2957

2958
	vlv_display_irq_reset(dev_priv);
J
Jesse Barnes 已提交
2959 2960
}

2961 2962 2963 2964 2965 2966 2967 2968
static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
{
	GEN8_IRQ_RESET_NDX(GT, 0);
	GEN8_IRQ_RESET_NDX(GT, 1);
	GEN8_IRQ_RESET_NDX(GT, 2);
	GEN8_IRQ_RESET_NDX(GT, 3);
}

P
Paulo Zanoni 已提交
2969
static void gen8_irq_reset(struct drm_device *dev)
2970 2971 2972 2973 2974 2975 2976
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int pipe;

	I915_WRITE(GEN8_MASTER_IRQ, 0);
	POSTING_READ(GEN8_MASTER_IRQ);

2977
	gen8_gt_irq_reset(dev_priv);
2978

2979
	for_each_pipe(dev_priv, pipe)
2980 2981
		if (intel_display_power_is_enabled(dev_priv,
						   POWER_DOMAIN_PIPE(pipe)))
2982
			GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
2983

2984 2985 2986
	GEN5_IRQ_RESET(GEN8_DE_PORT_);
	GEN5_IRQ_RESET(GEN8_DE_MISC_);
	GEN5_IRQ_RESET(GEN8_PCU_);
2987

2988 2989
	if (HAS_PCH_SPLIT(dev))
		ibx_irq_reset(dev);
2990
}
2991

2992 2993
void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
				     unsigned int pipe_mask)
2994
{
2995
	uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
2996

2997
	spin_lock_irq(&dev_priv->irq_lock);
2998 2999 3000 3001
	if (pipe_mask & 1 << PIPE_A)
		GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_A,
				  dev_priv->de_irq_mask[PIPE_A],
				  ~dev_priv->de_irq_mask[PIPE_A] | extra_ier);
3002 3003 3004 3005 3006 3007 3008 3009
	if (pipe_mask & 1 << PIPE_B)
		GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B,
				  dev_priv->de_irq_mask[PIPE_B],
				  ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
	if (pipe_mask & 1 << PIPE_C)
		GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C,
				  dev_priv->de_irq_mask[PIPE_C],
				  ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
3010
	spin_unlock_irq(&dev_priv->irq_lock);
3011 3012
}

3013 3014 3015 3016 3017 3018 3019
static void cherryview_irq_preinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	I915_WRITE(GEN8_MASTER_IRQ, 0);
	POSTING_READ(GEN8_MASTER_IRQ);

3020
	gen8_gt_irq_reset(dev_priv);
3021 3022 3023 3024 3025

	GEN5_IRQ_RESET(GEN8_PCU_);

	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);

3026
	vlv_display_irq_reset(dev_priv);
3027 3028
}

3029
static void ibx_hpd_irq_setup(struct drm_device *dev)
3030
{
3031
	struct drm_i915_private *dev_priv = dev->dev_private;
3032
	struct intel_encoder *intel_encoder;
3033
	u32 hotplug_irqs, hotplug, enabled_irqs = 0;
3034 3035

	if (HAS_PCH_IBX(dev)) {
3036
		hotplug_irqs = SDE_HOTPLUG_MASK;
3037
		for_each_intel_encoder(dev, intel_encoder)
3038
			if (dev_priv->hotplug.stats[intel_encoder->hpd_pin].state == HPD_ENABLED)
3039
				enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
X
Xiong Zhang 已提交
3040 3041 3042 3043 3044
	} else if (HAS_PCH_SPT(dev)) {
		hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
		for_each_intel_encoder(dev, intel_encoder)
			if (dev_priv->hotplug.stats[intel_encoder->hpd_pin].state == HPD_ENABLED)
				enabled_irqs |= hpd_spt[intel_encoder->hpd_pin];
3045
	} else {
3046
		hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3047
		for_each_intel_encoder(dev, intel_encoder)
3048
			if (dev_priv->hotplug.stats[intel_encoder->hpd_pin].state == HPD_ENABLED)
3049
				enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
3050
	}
3051

3052
	ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3053 3054 3055 3056 3057 3058 3059

	/*
	 * Enable digital hotplug on the PCH, and configure the DP short pulse
	 * duration to 2ms (which is the minimum in the Display Port spec)
	 *
	 * This register is the same on all known PCH chips.
	 */
3060 3061 3062 3063 3064 3065
	hotplug = I915_READ(PCH_PORT_HOTPLUG);
	hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
	hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
	hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
	hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
X
Xiong Zhang 已提交
3066 3067 3068 3069 3070 3071 3072

	/* enable SPT PORTE hot plug */
	if (HAS_PCH_SPT(dev)) {
		hotplug = I915_READ(PCH_PORT_HOTPLUG2);
		hotplug |= PORTE_HOTPLUG_ENABLE;
		I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
	}
3073 3074
}

3075 3076 3077 3078 3079 3080 3081 3082 3083
static void bxt_hpd_irq_setup(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_encoder *intel_encoder;
	u32 hotplug_port = 0;
	u32 hotplug_ctrl;

	/* Now, enable HPD */
	for_each_intel_encoder(dev, intel_encoder) {
3084
		if (dev_priv->hotplug.stats[intel_encoder->hpd_pin].state
3085 3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110
				== HPD_ENABLED)
			hotplug_port |= hpd_bxt[intel_encoder->hpd_pin];
	}

	/* Mask all HPD control bits */
	hotplug_ctrl = I915_READ(BXT_HOTPLUG_CTL) & ~BXT_HOTPLUG_CTL_MASK;

	/* Enable requested port in hotplug control */
	/* TODO: implement (short) HPD support on port A */
	WARN_ON_ONCE(hotplug_port & BXT_DE_PORT_HP_DDIA);
	if (hotplug_port & BXT_DE_PORT_HP_DDIB)
		hotplug_ctrl |= BXT_DDIB_HPD_ENABLE;
	if (hotplug_port & BXT_DE_PORT_HP_DDIC)
		hotplug_ctrl |= BXT_DDIC_HPD_ENABLE;
	I915_WRITE(BXT_HOTPLUG_CTL, hotplug_ctrl);

	/* Unmask DDI hotplug in IMR */
	hotplug_ctrl = I915_READ(GEN8_DE_PORT_IMR) & ~hotplug_port;
	I915_WRITE(GEN8_DE_PORT_IMR, hotplug_ctrl);

	/* Enable DDI hotplug in IER */
	hotplug_ctrl = I915_READ(GEN8_DE_PORT_IER) | hotplug_port;
	I915_WRITE(GEN8_DE_PORT_IER, hotplug_ctrl);
	POSTING_READ(GEN8_DE_PORT_IER);
}

P
Paulo Zanoni 已提交
3111 3112
static void ibx_irq_postinstall(struct drm_device *dev)
{
3113
	struct drm_i915_private *dev_priv = dev->dev_private;
3114
	u32 mask;
3115

D
Daniel Vetter 已提交
3116 3117 3118
	if (HAS_PCH_NOP(dev))
		return;

3119
	if (HAS_PCH_IBX(dev))
3120
		mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3121
	else
3122
		mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3123

3124
	GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
P
Paulo Zanoni 已提交
3125 3126 3127
	I915_WRITE(SDEIMR, ~mask);
}

3128 3129 3130 3131 3132 3133 3134 3135
static void gen5_gt_irq_postinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pm_irqs, gt_irqs;

	pm_irqs = gt_irqs = 0;

	dev_priv->gt_irq_mask = ~0;
3136
	if (HAS_L3_DPF(dev)) {
3137
		/* L3 parity interrupt is always unmasked. */
3138 3139
		dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
		gt_irqs |= GT_PARITY_ERROR(dev);
3140 3141 3142 3143 3144 3145 3146 3147 3148 3149
	}

	gt_irqs |= GT_RENDER_USER_INTERRUPT;
	if (IS_GEN5(dev)) {
		gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
			   ILK_BSD_USER_INTERRUPT;
	} else {
		gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
	}

P
Paulo Zanoni 已提交
3150
	GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3151 3152

	if (INTEL_INFO(dev)->gen >= 6) {
3153 3154 3155 3156
		/*
		 * RPS interrupts will get enabled/disabled on demand when RPS
		 * itself is enabled/disabled.
		 */
3157 3158 3159
		if (HAS_VEBOX(dev))
			pm_irqs |= PM_VEBOX_USER_INTERRUPT;

3160
		dev_priv->pm_irq_mask = 0xffffffff;
P
Paulo Zanoni 已提交
3161
		GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3162 3163 3164
	}
}

3165
static int ironlake_irq_postinstall(struct drm_device *dev)
3166
{
3167
	struct drm_i915_private *dev_priv = dev->dev_private;
3168 3169 3170 3171 3172 3173
	u32 display_mask, extra_mask;

	if (INTEL_INFO(dev)->gen >= 7) {
		display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
				DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
				DE_PLANEB_FLIP_DONE_IVB |
3174
				DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3175
		extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3176
			      DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
3177 3178 3179
	} else {
		display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
				DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3180 3181 3182
				DE_AUX_CHANNEL_A |
				DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
				DE_POISON);
3183 3184
		extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
				DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
3185
	}
3186

3187
	dev_priv->irq_mask = ~display_mask;
3188

3189 3190
	I915_WRITE(HWSTAM, 0xeffe);

P
Paulo Zanoni 已提交
3191 3192
	ibx_irq_pre_postinstall(dev);

P
Paulo Zanoni 已提交
3193
	GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3194

3195
	gen5_gt_irq_postinstall(dev);
3196

P
Paulo Zanoni 已提交
3197
	ibx_irq_postinstall(dev);
3198

3199
	if (IS_IRONLAKE_M(dev)) {
3200 3201 3202
		/* Enable PCU event interrupts
		 *
		 * spinlocking not required here for correctness since interrupt
3203 3204
		 * setup is guaranteed to run in single-threaded context. But we
		 * need it to make the assert_spin_locked happy. */
3205
		spin_lock_irq(&dev_priv->irq_lock);
3206
		ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
3207
		spin_unlock_irq(&dev_priv->irq_lock);
3208 3209
	}

3210 3211 3212
	return 0;
}

3213 3214 3215 3216
static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
{
	u32 pipestat_mask;
	u32 iir_mask;
3217
	enum pipe pipe;
3218 3219 3220 3221

	pipestat_mask = PIPESTAT_INT_STATUS_MASK |
			PIPE_FIFO_UNDERRUN_STATUS;

3222 3223
	for_each_pipe(dev_priv, pipe)
		I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3224 3225 3226 3227 3228
	POSTING_READ(PIPESTAT(PIPE_A));

	pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
			PIPE_CRC_DONE_INTERRUPT_STATUS;

3229 3230 3231
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
	for_each_pipe(dev_priv, pipe)
		      i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3232 3233 3234 3235

	iir_mask = I915_DISPLAY_PORT_INTERRUPT |
		   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3236 3237
	if (IS_CHERRYVIEW(dev_priv))
		iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3238 3239 3240 3241 3242
	dev_priv->irq_mask &= ~iir_mask;

	I915_WRITE(VLV_IIR, iir_mask);
	I915_WRITE(VLV_IIR, iir_mask);
	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3243 3244
	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
	POSTING_READ(VLV_IMR);
3245 3246 3247 3248 3249 3250
}

static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
{
	u32 pipestat_mask;
	u32 iir_mask;
3251
	enum pipe pipe;
3252 3253 3254

	iir_mask = I915_DISPLAY_PORT_INTERRUPT |
		   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3255
		   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3256 3257
	if (IS_CHERRYVIEW(dev_priv))
		iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3258 3259 3260

	dev_priv->irq_mask |= iir_mask;
	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3261
	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3262 3263 3264 3265 3266 3267 3268
	I915_WRITE(VLV_IIR, iir_mask);
	I915_WRITE(VLV_IIR, iir_mask);
	POSTING_READ(VLV_IIR);

	pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
			PIPE_CRC_DONE_INTERRUPT_STATUS;

3269 3270 3271
	i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
	for_each_pipe(dev_priv, pipe)
		i915_disable_pipestat(dev_priv, pipe, pipestat_mask);
3272 3273 3274

	pipestat_mask = PIPESTAT_INT_STATUS_MASK |
			PIPE_FIFO_UNDERRUN_STATUS;
3275 3276 3277

	for_each_pipe(dev_priv, pipe)
		I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3278 3279 3280 3281 3282 3283 3284 3285 3286 3287 3288 3289
	POSTING_READ(PIPESTAT(PIPE_A));
}

void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
{
	assert_spin_locked(&dev_priv->irq_lock);

	if (dev_priv->display_irqs_enabled)
		return;

	dev_priv->display_irqs_enabled = true;

3290
	if (intel_irqs_enabled(dev_priv))
3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301 3302
		valleyview_display_irqs_install(dev_priv);
}

void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
{
	assert_spin_locked(&dev_priv->irq_lock);

	if (!dev_priv->display_irqs_enabled)
		return;

	dev_priv->display_irqs_enabled = false;

3303
	if (intel_irqs_enabled(dev_priv))
3304 3305 3306
		valleyview_display_irqs_uninstall(dev_priv);
}

3307
static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
J
Jesse Barnes 已提交
3308
{
3309
	dev_priv->irq_mask = ~0;
J
Jesse Barnes 已提交
3310

3311 3312 3313
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	POSTING_READ(PORT_HOTPLUG_EN);

J
Jesse Barnes 已提交
3314
	I915_WRITE(VLV_IIR, 0xffffffff);
3315 3316 3317 3318
	I915_WRITE(VLV_IIR, 0xffffffff);
	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
	POSTING_READ(VLV_IMR);
J
Jesse Barnes 已提交
3319

3320 3321
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
3322
	spin_lock_irq(&dev_priv->irq_lock);
3323 3324
	if (dev_priv->display_irqs_enabled)
		valleyview_display_irqs_install(dev_priv);
3325
	spin_unlock_irq(&dev_priv->irq_lock);
3326 3327 3328 3329 3330 3331 3332
}

static int valleyview_irq_postinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	vlv_display_irq_postinstall(dev_priv);
J
Jesse Barnes 已提交
3333

3334
	gen5_gt_irq_postinstall(dev);
J
Jesse Barnes 已提交
3335 3336 3337 3338 3339 3340 3341 3342

	/* ack & enable invalid PTE error interrupts */
#if 0 /* FIXME: add support to irq handler for checking these bits */
	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
	I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
#endif

	I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3343 3344 3345 3346

	return 0;
}

3347 3348 3349 3350 3351
static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
{
	/* These are interrupts we'll toggle with the ring mask register */
	uint32_t gt_interrupts[] = {
		GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3352
			GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3353
			GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
3354 3355
			GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
			GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3356
		GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3357 3358 3359
			GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
			GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
			GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3360
		0,
3361 3362
		GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
			GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3363 3364
		};

3365
	dev_priv->pm_irq_mask = 0xffffffff;
3366 3367
	GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
	GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3368 3369 3370 3371 3372
	/*
	 * RPS interrupts will get enabled/disabled on demand when RPS itself
	 * is enabled/disabled.
	 */
	GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
3373
	GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3374 3375 3376 3377
}

static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
{
3378 3379
	uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
	uint32_t de_pipe_enables;
3380
	int pipe;
S
Shashank Sharma 已提交
3381
	u32 de_port_en = GEN8_AUX_CHANNEL_A;
3382

J
Jesse Barnes 已提交
3383
	if (IS_GEN9(dev_priv)) {
3384 3385
		de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
				  GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
S
Shashank Sharma 已提交
3386
		de_port_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
J
Jesse Barnes 已提交
3387
			GEN9_AUX_CHANNEL_D;
S
Shashank Sharma 已提交
3388 3389 3390

		if (IS_BROXTON(dev_priv))
			de_port_en |= BXT_DE_PORT_GMBUS;
J
Jesse Barnes 已提交
3391
	} else
3392 3393 3394 3395 3396 3397
		de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
				  GEN8_DE_PIPE_IRQ_FAULT_ERRORS;

	de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
					   GEN8_PIPE_FIFO_UNDERRUN;

3398 3399 3400
	dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
	dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
	dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3401

3402
	for_each_pipe(dev_priv, pipe)
3403
		if (intel_display_power_is_enabled(dev_priv,
3404 3405 3406 3407
				POWER_DOMAIN_PIPE(pipe)))
			GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
					  dev_priv->de_irq_mask[pipe],
					  de_pipe_enables);
3408

S
Shashank Sharma 已提交
3409
	GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_en, de_port_en);
3410 3411 3412 3413 3414 3415
}

static int gen8_irq_postinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

3416 3417
	if (HAS_PCH_SPLIT(dev))
		ibx_irq_pre_postinstall(dev);
P
Paulo Zanoni 已提交
3418

3419 3420 3421
	gen8_gt_irq_postinstall(dev_priv);
	gen8_de_irq_postinstall(dev_priv);

3422 3423
	if (HAS_PCH_SPLIT(dev))
		ibx_irq_postinstall(dev);
3424 3425 3426 3427 3428 3429 3430

	I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
	POSTING_READ(GEN8_MASTER_IRQ);

	return 0;
}

3431 3432 3433 3434
static int cherryview_irq_postinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

3435
	vlv_display_irq_postinstall(dev_priv);
3436 3437 3438 3439 3440 3441 3442 3443 3444

	gen8_gt_irq_postinstall(dev_priv);

	I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
	POSTING_READ(GEN8_MASTER_IRQ);

	return 0;
}

3445 3446 3447 3448 3449 3450 3451
static void gen8_irq_uninstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (!dev_priv)
		return;

P
Paulo Zanoni 已提交
3452
	gen8_irq_reset(dev);
3453 3454
}

3455 3456 3457 3458 3459 3460 3461 3462 3463 3464 3465
static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv)
{
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
	spin_lock_irq(&dev_priv->irq_lock);
	if (dev_priv->display_irqs_enabled)
		valleyview_display_irqs_uninstall(dev_priv);
	spin_unlock_irq(&dev_priv->irq_lock);

	vlv_display_irq_reset(dev_priv);

3466
	dev_priv->irq_mask = ~0;
3467 3468
}

J
Jesse Barnes 已提交
3469 3470
static void valleyview_irq_uninstall(struct drm_device *dev)
{
3471
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
3472 3473 3474 3475

	if (!dev_priv)
		return;

3476 3477
	I915_WRITE(VLV_MASTER_IER, 0);

3478 3479
	gen5_gt_irq_reset(dev);

J
Jesse Barnes 已提交
3480
	I915_WRITE(HWSTAM, 0xffffffff);
3481

3482
	vlv_display_irq_uninstall(dev_priv);
J
Jesse Barnes 已提交
3483 3484
}

3485 3486 3487 3488 3489 3490 3491 3492 3493 3494
static void cherryview_irq_uninstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (!dev_priv)
		return;

	I915_WRITE(GEN8_MASTER_IRQ, 0);
	POSTING_READ(GEN8_MASTER_IRQ);

3495
	gen8_gt_irq_reset(dev_priv);
3496

3497
	GEN5_IRQ_RESET(GEN8_PCU_);
3498

3499
	vlv_display_irq_uninstall(dev_priv);
3500 3501
}

3502
static void ironlake_irq_uninstall(struct drm_device *dev)
3503
{
3504
	struct drm_i915_private *dev_priv = dev->dev_private;
3505 3506 3507 3508

	if (!dev_priv)
		return;

P
Paulo Zanoni 已提交
3509
	ironlake_irq_reset(dev);
3510 3511
}

3512
static void i8xx_irq_preinstall(struct drm_device * dev)
L
Linus Torvalds 已提交
3513
{
3514
	struct drm_i915_private *dev_priv = dev->dev_private;
3515
	int pipe;
3516

3517
	for_each_pipe(dev_priv, pipe)
3518
		I915_WRITE(PIPESTAT(pipe), 0);
3519 3520 3521
	I915_WRITE16(IMR, 0xffff);
	I915_WRITE16(IER, 0x0);
	POSTING_READ16(IER);
C
Chris Wilson 已提交
3522 3523 3524 3525
}

static int i8xx_irq_postinstall(struct drm_device *dev)
{
3526
	struct drm_i915_private *dev_priv = dev->dev_private;
C
Chris Wilson 已提交
3527 3528 3529 3530 3531 3532 3533 3534 3535

	I915_WRITE16(EMR,
		     ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));

	/* Unmask the interrupts that we always want on. */
	dev_priv->irq_mask =
		~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3536
		  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
C
Chris Wilson 已提交
3537 3538 3539 3540 3541 3542 3543 3544
	I915_WRITE16(IMR, dev_priv->irq_mask);

	I915_WRITE16(IER,
		     I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		     I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		     I915_USER_INTERRUPT);
	POSTING_READ16(IER);

3545 3546
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
3547
	spin_lock_irq(&dev_priv->irq_lock);
3548 3549
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3550
	spin_unlock_irq(&dev_priv->irq_lock);
3551

C
Chris Wilson 已提交
3552 3553 3554
	return 0;
}

3555 3556 3557 3558
/*
 * Returns true when a page flip has completed.
 */
static bool i8xx_handle_vblank(struct drm_device *dev,
3559
			       int plane, int pipe, u32 iir)
3560
{
3561
	struct drm_i915_private *dev_priv = dev->dev_private;
3562
	u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3563

3564
	if (!intel_pipe_handle_vblank(dev, pipe))
3565 3566 3567
		return false;

	if ((iir & flip_pending) == 0)
3568
		goto check_page_flip;
3569 3570 3571 3572 3573 3574 3575 3576

	/* We detect FlipDone by looking for the change in PendingFlip from '1'
	 * to '0' on the following vblank, i.e. IIR has the Pendingflip
	 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
	 * the flip is completed (no longer pending). Since this doesn't raise
	 * an interrupt per se, we watch for the change at vblank.
	 */
	if (I915_READ16(ISR) & flip_pending)
3577
		goto check_page_flip;
3578

3579
	intel_prepare_page_flip(dev, plane);
3580 3581
	intel_finish_page_flip(dev, pipe);
	return true;
3582 3583 3584 3585

check_page_flip:
	intel_check_page_flip(dev, pipe);
	return false;
3586 3587
}

3588
static irqreturn_t i8xx_irq_handler(int irq, void *arg)
C
Chris Wilson 已提交
3589
{
3590
	struct drm_device *dev = arg;
3591
	struct drm_i915_private *dev_priv = dev->dev_private;
C
Chris Wilson 已提交
3592 3593 3594 3595 3596 3597 3598
	u16 iir, new_iir;
	u32 pipe_stats[2];
	int pipe;
	u16 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;

3599 3600 3601
	if (!intel_irqs_enabled(dev_priv))
		return IRQ_NONE;

C
Chris Wilson 已提交
3602 3603 3604 3605 3606 3607 3608 3609 3610 3611
	iir = I915_READ16(IIR);
	if (iir == 0)
		return IRQ_NONE;

	while (iir & ~flip_mask) {
		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
3612
		spin_lock(&dev_priv->irq_lock);
C
Chris Wilson 已提交
3613
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3614
			DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
C
Chris Wilson 已提交
3615

3616
		for_each_pipe(dev_priv, pipe) {
C
Chris Wilson 已提交
3617 3618 3619 3620 3621 3622
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);

			/*
			 * Clear the PIPE*STAT regs before the IIR
			 */
3623
			if (pipe_stats[pipe] & 0x8000ffff)
C
Chris Wilson 已提交
3624 3625
				I915_WRITE(reg, pipe_stats[pipe]);
		}
3626
		spin_unlock(&dev_priv->irq_lock);
C
Chris Wilson 已提交
3627 3628 3629 3630 3631

		I915_WRITE16(IIR, iir & ~flip_mask);
		new_iir = I915_READ16(IIR); /* Flush posted writes */

		if (iir & I915_USER_INTERRUPT)
C
Chris Wilson 已提交
3632
			notify_ring(&dev_priv->ring[RCS]);
C
Chris Wilson 已提交
3633

3634
		for_each_pipe(dev_priv, pipe) {
3635
			int plane = pipe;
3636
			if (HAS_FBC(dev))
3637 3638
				plane = !plane;

3639
			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3640 3641
			    i8xx_handle_vblank(dev, plane, pipe, iir))
				flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
C
Chris Wilson 已提交
3642

3643
			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3644
				i9xx_pipe_crc_irq_handler(dev, pipe);
3645

3646 3647 3648
			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
				intel_cpu_fifo_underrun_irq_handler(dev_priv,
								    pipe);
3649
		}
C
Chris Wilson 已提交
3650 3651 3652 3653 3654 3655 3656 3657 3658

		iir = new_iir;
	}

	return IRQ_HANDLED;
}

static void i8xx_irq_uninstall(struct drm_device * dev)
{
3659
	struct drm_i915_private *dev_priv = dev->dev_private;
C
Chris Wilson 已提交
3660 3661
	int pipe;

3662
	for_each_pipe(dev_priv, pipe) {
C
Chris Wilson 已提交
3663 3664 3665 3666 3667 3668 3669 3670 3671
		/* Clear enable bits; then clear status bits */
		I915_WRITE(PIPESTAT(pipe), 0);
		I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
	}
	I915_WRITE16(IMR, 0xffff);
	I915_WRITE16(IER, 0x0);
	I915_WRITE16(IIR, I915_READ16(IIR));
}

3672 3673
static void i915_irq_preinstall(struct drm_device * dev)
{
3674
	struct drm_i915_private *dev_priv = dev->dev_private;
3675 3676 3677 3678 3679 3680 3681
	int pipe;

	if (I915_HAS_HOTPLUG(dev)) {
		I915_WRITE(PORT_HOTPLUG_EN, 0);
		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	}

3682
	I915_WRITE16(HWSTAM, 0xeffe);
3683
	for_each_pipe(dev_priv, pipe)
3684 3685 3686 3687 3688 3689 3690 3691
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);
	POSTING_READ(IER);
}

static int i915_irq_postinstall(struct drm_device *dev)
{
3692
	struct drm_i915_private *dev_priv = dev->dev_private;
3693
	u32 enable_mask;
3694

3695 3696 3697 3698 3699 3700 3701 3702
	I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));

	/* Unmask the interrupts that we always want on. */
	dev_priv->irq_mask =
		~(I915_ASLE_INTERRUPT |
		  I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3703
		  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3704 3705 3706 3707 3708 3709 3710

	enable_mask =
		I915_ASLE_INTERRUPT |
		I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		I915_USER_INTERRUPT;

3711
	if (I915_HAS_HOTPLUG(dev)) {
3712 3713 3714
		I915_WRITE(PORT_HOTPLUG_EN, 0);
		POSTING_READ(PORT_HOTPLUG_EN);

3715 3716 3717 3718 3719 3720 3721 3722 3723 3724
		/* Enable in IER... */
		enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
		/* and unmask in IMR */
		dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
	}

	I915_WRITE(IMR, dev_priv->irq_mask);
	I915_WRITE(IER, enable_mask);
	POSTING_READ(IER);

3725
	i915_enable_asle_pipestat(dev);
3726

3727 3728
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
3729
	spin_lock_irq(&dev_priv->irq_lock);
3730 3731
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3732
	spin_unlock_irq(&dev_priv->irq_lock);
3733

3734 3735 3736
	return 0;
}

3737 3738 3739 3740 3741 3742
/*
 * Returns true when a page flip has completed.
 */
static bool i915_handle_vblank(struct drm_device *dev,
			       int plane, int pipe, u32 iir)
{
3743
	struct drm_i915_private *dev_priv = dev->dev_private;
3744 3745
	u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);

3746
	if (!intel_pipe_handle_vblank(dev, pipe))
3747 3748 3749
		return false;

	if ((iir & flip_pending) == 0)
3750
		goto check_page_flip;
3751 3752 3753 3754 3755 3756 3757 3758

	/* We detect FlipDone by looking for the change in PendingFlip from '1'
	 * to '0' on the following vblank, i.e. IIR has the Pendingflip
	 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
	 * the flip is completed (no longer pending). Since this doesn't raise
	 * an interrupt per se, we watch for the change at vblank.
	 */
	if (I915_READ(ISR) & flip_pending)
3759
		goto check_page_flip;
3760

3761
	intel_prepare_page_flip(dev, plane);
3762 3763
	intel_finish_page_flip(dev, pipe);
	return true;
3764 3765 3766 3767

check_page_flip:
	intel_check_page_flip(dev, pipe);
	return false;
3768 3769
}

3770
static irqreturn_t i915_irq_handler(int irq, void *arg)
3771
{
3772
	struct drm_device *dev = arg;
3773
	struct drm_i915_private *dev_priv = dev->dev_private;
3774
	u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3775 3776 3777 3778
	u32 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
	int pipe, ret = IRQ_NONE;
3779

3780 3781 3782
	if (!intel_irqs_enabled(dev_priv))
		return IRQ_NONE;

3783
	iir = I915_READ(IIR);
3784 3785
	do {
		bool irq_received = (iir & ~flip_mask) != 0;
3786
		bool blc_event = false;
3787 3788 3789 3790 3791 3792

		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
3793
		spin_lock(&dev_priv->irq_lock);
3794
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3795
			DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3796

3797
		for_each_pipe(dev_priv, pipe) {
3798 3799 3800
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);

3801
			/* Clear the PIPE*STAT regs before the IIR */
3802 3803
			if (pipe_stats[pipe] & 0x8000ffff) {
				I915_WRITE(reg, pipe_stats[pipe]);
3804
				irq_received = true;
3805 3806
			}
		}
3807
		spin_unlock(&dev_priv->irq_lock);
3808 3809 3810 3811 3812

		if (!irq_received)
			break;

		/* Consume port.  Then clear IIR or we'll miss events */
3813 3814 3815
		if (I915_HAS_HOTPLUG(dev) &&
		    iir & I915_DISPLAY_PORT_INTERRUPT)
			i9xx_hpd_irq_handler(dev);
3816

3817
		I915_WRITE(IIR, iir & ~flip_mask);
3818 3819 3820
		new_iir = I915_READ(IIR); /* Flush posted writes */

		if (iir & I915_USER_INTERRUPT)
C
Chris Wilson 已提交
3821
			notify_ring(&dev_priv->ring[RCS]);
3822

3823
		for_each_pipe(dev_priv, pipe) {
3824
			int plane = pipe;
3825
			if (HAS_FBC(dev))
3826
				plane = !plane;
3827

3828
			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3829 3830
			    i915_handle_vblank(dev, plane, pipe, iir))
				flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3831 3832 3833

			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
				blc_event = true;
3834 3835

			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3836
				i9xx_pipe_crc_irq_handler(dev, pipe);
3837

3838 3839 3840
			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
				intel_cpu_fifo_underrun_irq_handler(dev_priv,
								    pipe);
3841 3842 3843 3844 3845 3846 3847 3848 3849 3850 3851 3852 3853 3854 3855 3856 3857 3858 3859 3860
		}

		if (blc_event || (iir & I915_ASLE_INTERRUPT))
			intel_opregion_asle_intr(dev);

		/* With MSI, interrupts are only generated when iir
		 * transitions from zero to nonzero.  If another bit got
		 * set while we were handling the existing iir bits, then
		 * we would never get another interrupt.
		 *
		 * This is fine on non-MSI as well, as if we hit this path
		 * we avoid exiting the interrupt handler only to generate
		 * another one.
		 *
		 * Note that for MSI this could cause a stray interrupt report
		 * if an interrupt landed in the time between writing IIR and
		 * the posting read.  This should be rare enough to never
		 * trigger the 99% of 100,000 interrupts test for disabling
		 * stray interrupts.
		 */
3861
		ret = IRQ_HANDLED;
3862
		iir = new_iir;
3863
	} while (iir & ~flip_mask);
3864 3865 3866 3867 3868 3869

	return ret;
}

static void i915_irq_uninstall(struct drm_device * dev)
{
3870
	struct drm_i915_private *dev_priv = dev->dev_private;
3871 3872 3873 3874 3875 3876 3877
	int pipe;

	if (I915_HAS_HOTPLUG(dev)) {
		I915_WRITE(PORT_HOTPLUG_EN, 0);
		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	}

3878
	I915_WRITE16(HWSTAM, 0xffff);
3879
	for_each_pipe(dev_priv, pipe) {
3880
		/* Clear enable bits; then clear status bits */
3881
		I915_WRITE(PIPESTAT(pipe), 0);
3882 3883
		I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
	}
3884 3885 3886 3887 3888 3889 3890 3891
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);

	I915_WRITE(IIR, I915_READ(IIR));
}

static void i965_irq_preinstall(struct drm_device * dev)
{
3892
	struct drm_i915_private *dev_priv = dev->dev_private;
3893 3894
	int pipe;

3895 3896
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3897 3898

	I915_WRITE(HWSTAM, 0xeffe);
3899
	for_each_pipe(dev_priv, pipe)
3900 3901 3902 3903 3904 3905 3906 3907
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);
	POSTING_READ(IER);
}

static int i965_irq_postinstall(struct drm_device *dev)
{
3908
	struct drm_i915_private *dev_priv = dev->dev_private;
3909
	u32 enable_mask;
3910 3911 3912
	u32 error_mask;

	/* Unmask the interrupts that we always want on. */
3913
	dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
3914
			       I915_DISPLAY_PORT_INTERRUPT |
3915 3916 3917 3918 3919 3920 3921
			       I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
			       I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
			       I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
			       I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
			       I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);

	enable_mask = ~dev_priv->irq_mask;
3922 3923
	enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
			 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3924 3925 3926 3927
	enable_mask |= I915_USER_INTERRUPT;

	if (IS_G4X(dev))
		enable_mask |= I915_BSD_USER_INTERRUPT;
3928

3929 3930
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
3931
	spin_lock_irq(&dev_priv->irq_lock);
3932 3933 3934
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3935
	spin_unlock_irq(&dev_priv->irq_lock);
3936 3937 3938 3939 3940 3941 3942 3943 3944 3945 3946 3947 3948 3949 3950 3951 3952 3953 3954 3955

	/*
	 * Enable some error detection, note the instruction error mask
	 * bit is reserved, so we leave it masked.
	 */
	if (IS_G4X(dev)) {
		error_mask = ~(GM45_ERROR_PAGE_TABLE |
			       GM45_ERROR_MEM_PRIV |
			       GM45_ERROR_CP_PRIV |
			       I915_ERROR_MEMORY_REFRESH);
	} else {
		error_mask = ~(I915_ERROR_PAGE_TABLE |
			       I915_ERROR_MEMORY_REFRESH);
	}
	I915_WRITE(EMR, error_mask);

	I915_WRITE(IMR, dev_priv->irq_mask);
	I915_WRITE(IER, enable_mask);
	POSTING_READ(IER);

3956 3957 3958
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	POSTING_READ(PORT_HOTPLUG_EN);

3959
	i915_enable_asle_pipestat(dev);
3960 3961 3962 3963

	return 0;
}

3964
static void i915_hpd_irq_setup(struct drm_device *dev)
3965
{
3966
	struct drm_i915_private *dev_priv = dev->dev_private;
3967
	struct intel_encoder *intel_encoder;
3968 3969
	u32 hotplug_en;

3970 3971
	assert_spin_locked(&dev_priv->irq_lock);

3972 3973 3974 3975 3976
	hotplug_en = I915_READ(PORT_HOTPLUG_EN);
	hotplug_en &= ~HOTPLUG_INT_EN_MASK;
	/* Note HDMI and DP share hotplug bits */
	/* enable bits are the same for all generations */
	for_each_intel_encoder(dev, intel_encoder)
3977
		if (dev_priv->hotplug.stats[intel_encoder->hpd_pin].state == HPD_ENABLED)
3978 3979 3980 3981 3982 3983 3984 3985 3986 3987 3988 3989
			hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
	/* Programming the CRT detection parameters tends
	   to generate a spurious hotplug event about three
	   seconds later.  So just do it once.
	*/
	if (IS_G4X(dev))
		hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
	hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
	hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;

	/* Ignore TV since it's buggy */
	I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3990 3991
}

3992
static irqreturn_t i965_irq_handler(int irq, void *arg)
3993
{
3994
	struct drm_device *dev = arg;
3995
	struct drm_i915_private *dev_priv = dev->dev_private;
3996 3997 3998
	u32 iir, new_iir;
	u32 pipe_stats[I915_MAX_PIPES];
	int ret = IRQ_NONE, pipe;
3999 4000 4001
	u32 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4002

4003 4004 4005
	if (!intel_irqs_enabled(dev_priv))
		return IRQ_NONE;

4006 4007 4008
	iir = I915_READ(IIR);

	for (;;) {
4009
		bool irq_received = (iir & ~flip_mask) != 0;
4010 4011
		bool blc_event = false;

4012 4013 4014 4015 4016
		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
4017
		spin_lock(&dev_priv->irq_lock);
4018
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4019
			DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4020

4021
		for_each_pipe(dev_priv, pipe) {
4022 4023 4024 4025 4026 4027 4028 4029
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);

			/*
			 * Clear the PIPE*STAT regs before the IIR
			 */
			if (pipe_stats[pipe] & 0x8000ffff) {
				I915_WRITE(reg, pipe_stats[pipe]);
4030
				irq_received = true;
4031 4032
			}
		}
4033
		spin_unlock(&dev_priv->irq_lock);
4034 4035 4036 4037 4038 4039 4040

		if (!irq_received)
			break;

		ret = IRQ_HANDLED;

		/* Consume port.  Then clear IIR or we'll miss events */
4041 4042
		if (iir & I915_DISPLAY_PORT_INTERRUPT)
			i9xx_hpd_irq_handler(dev);
4043

4044
		I915_WRITE(IIR, iir & ~flip_mask);
4045 4046 4047
		new_iir = I915_READ(IIR); /* Flush posted writes */

		if (iir & I915_USER_INTERRUPT)
C
Chris Wilson 已提交
4048
			notify_ring(&dev_priv->ring[RCS]);
4049
		if (iir & I915_BSD_USER_INTERRUPT)
C
Chris Wilson 已提交
4050
			notify_ring(&dev_priv->ring[VCS]);
4051

4052
		for_each_pipe(dev_priv, pipe) {
4053
			if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4054 4055
			    i915_handle_vblank(dev, pipe, pipe, iir))
				flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4056 4057 4058

			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
				blc_event = true;
4059 4060

			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4061
				i9xx_pipe_crc_irq_handler(dev, pipe);
4062

4063 4064
			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
				intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4065
		}
4066 4067 4068 4069

		if (blc_event || (iir & I915_ASLE_INTERRUPT))
			intel_opregion_asle_intr(dev);

4070 4071 4072
		if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
			gmbus_irq_handler(dev);

4073 4074 4075 4076 4077 4078 4079 4080 4081 4082 4083 4084 4085 4086 4087 4088 4089 4090 4091 4092 4093 4094 4095
		/* With MSI, interrupts are only generated when iir
		 * transitions from zero to nonzero.  If another bit got
		 * set while we were handling the existing iir bits, then
		 * we would never get another interrupt.
		 *
		 * This is fine on non-MSI as well, as if we hit this path
		 * we avoid exiting the interrupt handler only to generate
		 * another one.
		 *
		 * Note that for MSI this could cause a stray interrupt report
		 * if an interrupt landed in the time between writing IIR and
		 * the posting read.  This should be rare enough to never
		 * trigger the 99% of 100,000 interrupts test for disabling
		 * stray interrupts.
		 */
		iir = new_iir;
	}

	return ret;
}

static void i965_irq_uninstall(struct drm_device * dev)
{
4096
	struct drm_i915_private *dev_priv = dev->dev_private;
4097 4098 4099 4100 4101
	int pipe;

	if (!dev_priv)
		return;

4102 4103
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4104 4105

	I915_WRITE(HWSTAM, 0xffffffff);
4106
	for_each_pipe(dev_priv, pipe)
4107 4108 4109 4110
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);

4111
	for_each_pipe(dev_priv, pipe)
4112 4113 4114 4115 4116
		I915_WRITE(PIPESTAT(pipe),
			   I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
	I915_WRITE(IIR, I915_READ(IIR));
}

4117 4118 4119 4120 4121 4122 4123
/**
 * intel_irq_init - initializes irq support
 * @dev_priv: i915 device instance
 *
 * This function initializes all the irq support including work items, timers
 * and all the vtables. It does not setup the interrupt itself though.
 */
4124
void intel_irq_init(struct drm_i915_private *dev_priv)
4125
{
4126
	struct drm_device *dev = dev_priv->dev;
4127

4128 4129
	intel_hpd_init_work(dev_priv);

4130
	INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4131
	INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4132

4133
	/* Let's track the enabled rps events */
4134
	if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
4135
		/* WaGsvRC0ResidencyMethod:vlv */
4136
		dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
4137 4138
	else
		dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4139

4140 4141
	INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
			  i915_hangcheck_elapsed);
4142

4143
	pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4144

4145
	if (IS_GEN2(dev_priv)) {
4146 4147
		dev->max_vblank_count = 0;
		dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4148
	} else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4149 4150
		dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
		dev->driver->get_vblank_counter = gm45_get_vblank_counter;
4151 4152 4153
	} else {
		dev->driver->get_vblank_counter = i915_get_vblank_counter;
		dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4154 4155
	}

4156 4157 4158 4159 4160
	/*
	 * Opt out of the vblank disable timer on everything except gen2.
	 * Gen2 doesn't have a hardware frame counter and so depends on
	 * vblank interrupts to produce sane vblank seuquence numbers.
	 */
4161
	if (!IS_GEN2(dev_priv))
4162 4163
		dev->vblank_disable_immediate = true;

4164 4165
	dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
	dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4166

4167
	if (IS_CHERRYVIEW(dev_priv)) {
4168 4169 4170 4171 4172 4173 4174
		dev->driver->irq_handler = cherryview_irq_handler;
		dev->driver->irq_preinstall = cherryview_irq_preinstall;
		dev->driver->irq_postinstall = cherryview_irq_postinstall;
		dev->driver->irq_uninstall = cherryview_irq_uninstall;
		dev->driver->enable_vblank = valleyview_enable_vblank;
		dev->driver->disable_vblank = valleyview_disable_vblank;
		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4175
	} else if (IS_VALLEYVIEW(dev_priv)) {
J
Jesse Barnes 已提交
4176 4177 4178 4179 4180 4181
		dev->driver->irq_handler = valleyview_irq_handler;
		dev->driver->irq_preinstall = valleyview_irq_preinstall;
		dev->driver->irq_postinstall = valleyview_irq_postinstall;
		dev->driver->irq_uninstall = valleyview_irq_uninstall;
		dev->driver->enable_vblank = valleyview_enable_vblank;
		dev->driver->disable_vblank = valleyview_disable_vblank;
4182
		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4183
	} else if (INTEL_INFO(dev_priv)->gen >= 8) {
4184
		dev->driver->irq_handler = gen8_irq_handler;
4185
		dev->driver->irq_preinstall = gen8_irq_reset;
4186 4187 4188 4189
		dev->driver->irq_postinstall = gen8_irq_postinstall;
		dev->driver->irq_uninstall = gen8_irq_uninstall;
		dev->driver->enable_vblank = gen8_enable_vblank;
		dev->driver->disable_vblank = gen8_disable_vblank;
4190 4191 4192 4193
		if (HAS_PCH_SPLIT(dev))
			dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
		else
			dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4194 4195
	} else if (HAS_PCH_SPLIT(dev)) {
		dev->driver->irq_handler = ironlake_irq_handler;
4196
		dev->driver->irq_preinstall = ironlake_irq_reset;
4197 4198 4199 4200
		dev->driver->irq_postinstall = ironlake_irq_postinstall;
		dev->driver->irq_uninstall = ironlake_irq_uninstall;
		dev->driver->enable_vblank = ironlake_enable_vblank;
		dev->driver->disable_vblank = ironlake_disable_vblank;
4201
		dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4202
	} else {
4203
		if (INTEL_INFO(dev_priv)->gen == 2) {
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			dev->driver->irq_preinstall = i8xx_irq_preinstall;
			dev->driver->irq_postinstall = i8xx_irq_postinstall;
			dev->driver->irq_handler = i8xx_irq_handler;
			dev->driver->irq_uninstall = i8xx_irq_uninstall;
4208
		} else if (INTEL_INFO(dev_priv)->gen == 3) {
4209 4210 4211 4212
			dev->driver->irq_preinstall = i915_irq_preinstall;
			dev->driver->irq_postinstall = i915_irq_postinstall;
			dev->driver->irq_uninstall = i915_irq_uninstall;
			dev->driver->irq_handler = i915_irq_handler;
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Chris Wilson 已提交
4213
		} else {
4214 4215 4216 4217
			dev->driver->irq_preinstall = i965_irq_preinstall;
			dev->driver->irq_postinstall = i965_irq_postinstall;
			dev->driver->irq_uninstall = i965_irq_uninstall;
			dev->driver->irq_handler = i965_irq_handler;
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Chris Wilson 已提交
4218
		}
4219 4220
		if (I915_HAS_HOTPLUG(dev_priv))
			dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4221 4222 4223 4224
		dev->driver->enable_vblank = i915_enable_vblank;
		dev->driver->disable_vblank = i915_disable_vblank;
	}
}
4225

4226 4227 4228 4229 4230 4231 4232 4233 4234 4235 4236
/**
 * intel_irq_install - enables the hardware interrupt
 * @dev_priv: i915 device instance
 *
 * This function enables the hardware interrupt handling, but leaves the hotplug
 * handling still disabled. It is called after intel_irq_init().
 *
 * In the driver load and resume code we need working interrupts in a few places
 * but don't want to deal with the hassle of concurrent probe and hotplug
 * workers. Hence the split into this two-stage approach.
 */
4237 4238 4239 4240 4241 4242 4243 4244 4245 4246 4247 4248
int intel_irq_install(struct drm_i915_private *dev_priv)
{
	/*
	 * We enable some interrupt sources in our postinstall hooks, so mark
	 * interrupts as enabled _before_ actually enabling them to avoid
	 * special cases in our ordering checks.
	 */
	dev_priv->pm.irqs_enabled = true;

	return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
}

4249 4250 4251 4252 4253 4254 4255
/**
 * intel_irq_uninstall - finilizes all irq handling
 * @dev_priv: i915 device instance
 *
 * This stops interrupt and hotplug handling and unregisters and frees all
 * resources acquired in the init functions.
 */
4256 4257 4258 4259 4260 4261 4262
void intel_irq_uninstall(struct drm_i915_private *dev_priv)
{
	drm_irq_uninstall(dev_priv->dev);
	intel_hpd_cancel_work(dev_priv);
	dev_priv->pm.irqs_enabled = false;
}

4263 4264 4265 4266 4267 4268 4269
/**
 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
 * @dev_priv: i915 device instance
 *
 * This function is used to disable interrupts at runtime, both in the runtime
 * pm and the system suspend/resume code.
 */
4270
void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4271
{
4272
	dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
4273
	dev_priv->pm.irqs_enabled = false;
4274
	synchronize_irq(dev_priv->dev->irq);
4275 4276
}

4277 4278 4279 4280 4281 4282 4283
/**
 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
 * @dev_priv: i915 device instance
 *
 * This function is used to enable interrupts at runtime, both in the runtime
 * pm and the system suspend/resume code.
 */
4284
void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4285
{
4286
	dev_priv->pm.irqs_enabled = true;
4287 4288
	dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
	dev_priv->dev->driver->irq_postinstall(dev_priv->dev);
4289
}