i915_irq.c 127.4 KB
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/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
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 */
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/*
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

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#include <linux/sysrq.h>
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#include <linux/slab.h>
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#include <linux/circ_buf.h>
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#include <drm/drmP.h>
#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#include "i915_trace.h"
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#include "intel_drv.h"
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/**
 * DOC: interrupt handling
 *
 * These functions provide the basic support for enabling and disabling the
 * interrupt handling support. There's a lot more functionality in i915_irq.c
 * and related files, but that will be described in separate chapters.
 */

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static const u32 hpd_ibx[] = {
	[HPD_CRT] = SDE_CRT_HOTPLUG,
	[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
	[HPD_PORT_B] = SDE_PORTB_HOTPLUG,
	[HPD_PORT_C] = SDE_PORTC_HOTPLUG,
	[HPD_PORT_D] = SDE_PORTD_HOTPLUG
};

static const u32 hpd_cpt[] = {
	[HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
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	[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
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	[HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
	[HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
	[HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
};

static const u32 hpd_mask_i915[] = {
	[HPD_CRT] = CRT_HOTPLUG_INT_EN,
	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
	[HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
	[HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
	[HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
};

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static const u32 hpd_status_g4x[] = {
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	[HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
	[HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
	[HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
	[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
};

static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
	[HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
	[HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
	[HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
	[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
};

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/* IIR can theoretically queue up two events. Be paranoid. */
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#define GEN8_IRQ_RESET_NDX(type, which) do { \
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	I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
	POSTING_READ(GEN8_##type##_IMR(which)); \
	I915_WRITE(GEN8_##type##_IER(which), 0); \
	I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
	POSTING_READ(GEN8_##type##_IIR(which)); \
	I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
	POSTING_READ(GEN8_##type##_IIR(which)); \
} while (0)

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#define GEN5_IRQ_RESET(type) do { \
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	I915_WRITE(type##IMR, 0xffffffff); \
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	POSTING_READ(type##IMR); \
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	I915_WRITE(type##IER, 0); \
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	I915_WRITE(type##IIR, 0xffffffff); \
	POSTING_READ(type##IIR); \
	I915_WRITE(type##IIR, 0xffffffff); \
	POSTING_READ(type##IIR); \
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} while (0)

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/*
 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
 */
#define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
	u32 val = I915_READ(reg); \
	if (val) { \
		WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
		     (reg), val); \
		I915_WRITE((reg), 0xffffffff); \
		POSTING_READ(reg); \
		I915_WRITE((reg), 0xffffffff); \
		POSTING_READ(reg); \
	} \
} while (0)

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#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
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	GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
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	I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
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	I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
	POSTING_READ(GEN8_##type##_IMR(which)); \
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} while (0)

#define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
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	GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
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	I915_WRITE(type##IER, (ier_val)); \
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	I915_WRITE(type##IMR, (imr_val)); \
	POSTING_READ(type##IMR); \
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} while (0)

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static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);

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/* For display hotplug interrupt */
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void
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ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
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{
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	assert_spin_locked(&dev_priv->irq_lock);

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	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
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		return;

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	if ((dev_priv->irq_mask & mask) != 0) {
		dev_priv->irq_mask &= ~mask;
		I915_WRITE(DEIMR, dev_priv->irq_mask);
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		POSTING_READ(DEIMR);
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	}
}

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void
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ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
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{
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	assert_spin_locked(&dev_priv->irq_lock);

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	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
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		return;

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	if ((dev_priv->irq_mask & mask) != mask) {
		dev_priv->irq_mask |= mask;
		I915_WRITE(DEIMR, dev_priv->irq_mask);
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		POSTING_READ(DEIMR);
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	}
}

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/**
 * ilk_update_gt_irq - update GTIMR
 * @dev_priv: driver private
 * @interrupt_mask: mask of interrupt bits to update
 * @enabled_irq_mask: mask of interrupt bits to enable
 */
static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
			      uint32_t interrupt_mask,
			      uint32_t enabled_irq_mask)
{
	assert_spin_locked(&dev_priv->irq_lock);

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	WARN_ON(enabled_irq_mask & ~interrupt_mask);

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	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
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		return;

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	dev_priv->gt_irq_mask &= ~interrupt_mask;
	dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
	POSTING_READ(GTIMR);
}

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void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
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{
	ilk_update_gt_irq(dev_priv, mask, mask);
}

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void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
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{
	ilk_update_gt_irq(dev_priv, mask, 0);
}

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static u32 gen6_pm_iir(struct drm_i915_private *dev_priv)
{
	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
}

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static u32 gen6_pm_imr(struct drm_i915_private *dev_priv)
{
	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
}

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static u32 gen6_pm_ier(struct drm_i915_private *dev_priv)
{
	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
}

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/**
  * snb_update_pm_irq - update GEN6_PMIMR
  * @dev_priv: driver private
  * @interrupt_mask: mask of interrupt bits to update
  * @enabled_irq_mask: mask of interrupt bits to enable
  */
static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
			      uint32_t interrupt_mask,
			      uint32_t enabled_irq_mask)
{
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	uint32_t new_val;
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	WARN_ON(enabled_irq_mask & ~interrupt_mask);

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	assert_spin_locked(&dev_priv->irq_lock);

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	new_val = dev_priv->pm_irq_mask;
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	new_val &= ~interrupt_mask;
	new_val |= (~enabled_irq_mask & interrupt_mask);

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	if (new_val != dev_priv->pm_irq_mask) {
		dev_priv->pm_irq_mask = new_val;
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		I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
		POSTING_READ(gen6_pm_imr(dev_priv));
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	}
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}

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void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
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{
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	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
		return;

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	snb_update_pm_irq(dev_priv, mask, mask);
}

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static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
				  uint32_t mask)
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{
	snb_update_pm_irq(dev_priv, mask, 0);
}

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void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
{
	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
		return;

	__gen6_disable_pm_irq(dev_priv, mask);
}

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void gen6_reset_rps_interrupts(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t reg = gen6_pm_iir(dev_priv);

	spin_lock_irq(&dev_priv->irq_lock);
	I915_WRITE(reg, dev_priv->pm_rps_events);
	I915_WRITE(reg, dev_priv->pm_rps_events);
	POSTING_READ(reg);
	spin_unlock_irq(&dev_priv->irq_lock);
}

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void gen6_enable_rps_interrupts(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	spin_lock_irq(&dev_priv->irq_lock);
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	WARN_ON(dev_priv->rps.pm_iir);
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	WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
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	dev_priv->rps.interrupts_enabled = true;
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	I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
				dev_priv->pm_rps_events);
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	gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
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	spin_unlock_irq(&dev_priv->irq_lock);
}

void gen6_disable_rps_interrupts(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

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	spin_lock_irq(&dev_priv->irq_lock);
	dev_priv->rps.interrupts_enabled = false;
	spin_unlock_irq(&dev_priv->irq_lock);

	cancel_work_sync(&dev_priv->rps.work);

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	spin_lock_irq(&dev_priv->irq_lock);

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	I915_WRITE(GEN6_PMINTRMSK, INTEL_INFO(dev_priv)->gen >= 8 ?
		   ~GEN8_PMINTR_REDIRECT_TO_NON_DISP : ~0);
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	__gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
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	I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
				~dev_priv->pm_rps_events);
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	I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events);
	I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events);
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	dev_priv->rps.pm_iir = 0;

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	spin_unlock_irq(&dev_priv->irq_lock);
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}

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/**
 * ibx_display_interrupt_update - update SDEIMR
 * @dev_priv: driver private
 * @interrupt_mask: mask of interrupt bits to update
 * @enabled_irq_mask: mask of interrupt bits to enable
 */
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void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
				  uint32_t interrupt_mask,
				  uint32_t enabled_irq_mask)
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{
	uint32_t sdeimr = I915_READ(SDEIMR);
	sdeimr &= ~interrupt_mask;
	sdeimr |= (~enabled_irq_mask & interrupt_mask);

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	WARN_ON(enabled_irq_mask & ~interrupt_mask);

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	assert_spin_locked(&dev_priv->irq_lock);

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	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
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		return;

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	I915_WRITE(SDEIMR, sdeimr);
	POSTING_READ(SDEIMR);
}
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static void
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__i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		       u32 enable_mask, u32 status_mask)
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{
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	u32 reg = PIPESTAT(pipe);
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	u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
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	assert_spin_locked(&dev_priv->irq_lock);
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	WARN_ON(!intel_irqs_enabled(dev_priv));
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	if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
		      status_mask & ~PIPESTAT_INT_STATUS_MASK,
		      "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
		      pipe_name(pipe), enable_mask, status_mask))
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		return;

	if ((pipestat & enable_mask) == enable_mask)
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		return;

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	dev_priv->pipestat_irq_mask[pipe] |= status_mask;

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	/* Enable the interrupt, clear any pending status */
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	pipestat |= enable_mask | status_mask;
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	I915_WRITE(reg, pipestat);
	POSTING_READ(reg);
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}

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static void
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__i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		        u32 enable_mask, u32 status_mask)
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{
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	u32 reg = PIPESTAT(pipe);
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	u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
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	assert_spin_locked(&dev_priv->irq_lock);
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	WARN_ON(!intel_irqs_enabled(dev_priv));
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	if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
		      status_mask & ~PIPESTAT_INT_STATUS_MASK,
		      "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
		      pipe_name(pipe), enable_mask, status_mask))
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		return;

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	if ((pipestat & enable_mask) == 0)
		return;

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	dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;

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	pipestat &= ~enable_mask;
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	I915_WRITE(reg, pipestat);
	POSTING_READ(reg);
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}

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static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
{
	u32 enable_mask = status_mask << 16;

	/*
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	 * On pipe A we don't support the PSR interrupt yet,
	 * on pipe B and C the same bit MBZ.
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	 */
	if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
		return 0;
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	/*
	 * On pipe B and C we don't support the PSR interrupt yet, on pipe
	 * A the same bit is for perf counters which we don't use either.
	 */
	if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
		return 0;
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	enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
			 SPRITE0_FLIP_DONE_INT_EN_VLV |
			 SPRITE1_FLIP_DONE_INT_EN_VLV);
	if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
		enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
	if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
		enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;

	return enable_mask;
}

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void
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		     u32 status_mask)
{
	u32 enable_mask;

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	if (IS_VALLEYVIEW(dev_priv->dev))
		enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
							   status_mask);
	else
		enable_mask = status_mask << 16;
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	__i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
}

void
i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		      u32 status_mask)
{
	u32 enable_mask;

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	if (IS_VALLEYVIEW(dev_priv->dev))
		enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
							   status_mask);
	else
		enable_mask = status_mask << 16;
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	__i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
}

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/**
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 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
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 */
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static void i915_enable_asle_pipestat(struct drm_device *dev)
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{
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	struct drm_i915_private *dev_priv = dev->dev_private;
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	if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
		return;

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	spin_lock_irq(&dev_priv->irq_lock);
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	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
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	if (INTEL_INFO(dev)->gen >= 4)
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		i915_enable_pipestat(dev_priv, PIPE_A,
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				     PIPE_LEGACY_BLC_EVENT_STATUS);
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	spin_unlock_irq(&dev_priv->irq_lock);
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}

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/**
 * i915_pipe_enabled - check if a pipe is enabled
 * @dev: DRM device
 * @pipe: pipe to check
 *
 * Reading certain registers when the pipe is disabled can hang the chip.
 * Use this routine to make sure the PLL is running and the pipe is active
 * before reading such registers if unsure.
 */
static int
i915_pipe_enabled(struct drm_device *dev, int pipe)
{
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	struct drm_i915_private *dev_priv = dev->dev_private;
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	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
		/* Locking is horribly broken here, but whatever. */
		struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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		return intel_crtc->active;
	} else {
		return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
	}
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}

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/*
 * This timing diagram depicts the video signal in and
 * around the vertical blanking period.
 *
 * Assumptions about the fictitious mode used in this example:
 *  vblank_start >= 3
 *  vsync_start = vblank_start + 1
 *  vsync_end = vblank_start + 2
 *  vtotal = vblank_start + 3
 *
 *           start of vblank:
 *           latch double buffered registers
 *           increment frame counter (ctg+)
 *           generate start of vblank interrupt (gen4+)
 *           |
 *           |          frame start:
 *           |          generate frame start interrupt (aka. vblank interrupt) (gmch)
 *           |          may be shifted forward 1-3 extra lines via PIPECONF
 *           |          |
 *           |          |  start of vsync:
 *           |          |  generate vsync interrupt
 *           |          |  |
 * ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx
 *       .   \hs/   .      \hs/          \hs/          \hs/   .      \hs/
 * ----va---> <-----------------vb--------------------> <--------va-------------
 *       |          |       <----vs----->                     |
 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
 *       |          |                                         |
 *       last visible pixel                                   first visible pixel
 *                  |                                         increment frame counter (gen3/4)
 *                  pixel counter = vblank_start * htotal     pixel counter = 0 (gen3/4)
 *
 * x  = horizontal active
 * _  = horizontal blanking
 * hs = horizontal sync
 * va = vertical active
 * vb = vertical blanking
 * vs = vertical sync
 * vbs = vblank_start (number)
 *
 * Summary:
 * - most events happen at the start of horizontal sync
 * - frame start happens at the start of horizontal blank, 1-4 lines
 *   (depending on PIPECONF settings) after the start of vblank
 * - gen3/4 pixel and frame counter are synchronized with the start
 *   of horizontal active on the first line of vertical active
 */

554 555 556 557 558 559
static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
{
	/* Gen2 doesn't have a hardware frame counter */
	return 0;
}

560 561 562
/* Called from drm generic code, passed a 'crtc', which
 * we use as a pipe index
 */
563
static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
564
{
565
	struct drm_i915_private *dev_priv = dev->dev_private;
566 567
	unsigned long high_frame;
	unsigned long low_frame;
568
	u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
569 570

	if (!i915_pipe_enabled(dev, pipe)) {
571
		DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
572
				"pipe %c\n", pipe_name(pipe));
573 574 575
		return 0;
	}

576 577 578 579 580 581
	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
		struct intel_crtc *intel_crtc =
			to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
		const struct drm_display_mode *mode =
			&intel_crtc->config.adjusted_mode;

582 583 584 585 586
		htotal = mode->crtc_htotal;
		hsync_start = mode->crtc_hsync_start;
		vbl_start = mode->crtc_vblank_start;
		if (mode->flags & DRM_MODE_FLAG_INTERLACE)
			vbl_start = DIV_ROUND_UP(vbl_start, 2);
587
	} else {
588
		enum transcoder cpu_transcoder = (enum transcoder) pipe;
589 590

		htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
591
		hsync_start = (I915_READ(HSYNC(cpu_transcoder))  & 0x1fff) + 1;
592
		vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
593 594 595
		if ((I915_READ(PIPECONF(cpu_transcoder)) &
		     PIPECONF_INTERLACE_MASK) != PIPECONF_PROGRESSIVE)
			vbl_start = DIV_ROUND_UP(vbl_start, 2);
596 597
	}

598 599 600 601 602 603
	/* Convert to pixel count */
	vbl_start *= htotal;

	/* Start of vblank event occurs at start of hsync */
	vbl_start -= htotal - hsync_start;

604 605
	high_frame = PIPEFRAME(pipe);
	low_frame = PIPEFRAMEPIXEL(pipe);
606

607 608 609 610 611 612
	/*
	 * High & low register fields aren't synchronized, so make sure
	 * we get a low value that's stable across two reads of the high
	 * register.
	 */
	do {
613
		high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
614
		low   = I915_READ(low_frame);
615
		high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
616 617
	} while (high1 != high2);

618
	high1 >>= PIPE_FRAME_HIGH_SHIFT;
619
	pixel = low & PIPE_PIXEL_MASK;
620
	low >>= PIPE_FRAME_LOW_SHIFT;
621 622 623 624 625 626

	/*
	 * The frame counter increments at beginning of active.
	 * Cook up a vblank counter by also checking the pixel
	 * counter against vblank start.
	 */
627
	return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
628 629
}

630
static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
631
{
632
	struct drm_i915_private *dev_priv = dev->dev_private;
633
	int reg = PIPE_FRMCOUNT_GM45(pipe);
634 635

	if (!i915_pipe_enabled(dev, pipe)) {
636
		DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
637
				 "pipe %c\n", pipe_name(pipe));
638 639 640 641 642 643
		return 0;
	}

	return I915_READ(reg);
}

644 645 646
/* raw reads, only for fast reads of display block, no need for forcewake etc. */
#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))

647 648 649 650 651 652
static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
	enum pipe pipe = crtc->pipe;
653
	int position, vtotal;
654

655
	vtotal = mode->crtc_vtotal;
656 657 658 659 660 661 662 663 664
	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
		vtotal /= 2;

	if (IS_GEN2(dev))
		position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
	else
		position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;

	/*
665 666
	 * See update_scanline_offset() for the details on the
	 * scanline_offset adjustment.
667
	 */
668
	return (position + crtc->scanline_offset) % vtotal;
669 670
}

671
static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
672 673
				    unsigned int flags, int *vpos, int *hpos,
				    ktime_t *stime, ktime_t *etime)
674
{
675 676 677 678
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
679
	int position;
680
	int vbl_start, vbl_end, hsync_start, htotal, vtotal;
681 682
	bool in_vbl = true;
	int ret = 0;
683
	unsigned long irqflags;
684

685
	if (!intel_crtc->active) {
686
		DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
687
				 "pipe %c\n", pipe_name(pipe));
688 689 690
		return 0;
	}

691
	htotal = mode->crtc_htotal;
692
	hsync_start = mode->crtc_hsync_start;
693 694 695
	vtotal = mode->crtc_vtotal;
	vbl_start = mode->crtc_vblank_start;
	vbl_end = mode->crtc_vblank_end;
696

697 698 699 700 701 702
	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
		vbl_start = DIV_ROUND_UP(vbl_start, 2);
		vbl_end /= 2;
		vtotal /= 2;
	}

703 704
	ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;

705 706 707 708 709 710
	/*
	 * Lock uncore.lock, as we will do multiple timing critical raw
	 * register reads, potentially with preemption disabled, so the
	 * following code must not block on uncore.lock.
	 */
	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
711

712 713 714 715 716 717
	/* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */

	/* Get optional system timestamp before query. */
	if (stime)
		*stime = ktime_get();

718
	if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
719 720 721
		/* No obvious pixelcount register. Only query vertical
		 * scanout position from Display scan line register.
		 */
722
		position = __intel_get_crtc_scanline(intel_crtc);
723 724 725 726 727
	} else {
		/* Have access to pixelcount since start of frame.
		 * We can split this into vertical and horizontal
		 * scanout position.
		 */
728
		position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
729

730 731 732 733
		/* convert to pixel counts */
		vbl_start *= htotal;
		vbl_end *= htotal;
		vtotal *= htotal;
734

735 736 737 738 739 740 741 742 743 744 745 746
		/*
		 * In interlaced modes, the pixel counter counts all pixels,
		 * so one field will have htotal more pixels. In order to avoid
		 * the reported position from jumping backwards when the pixel
		 * counter is beyond the length of the shorter field, just
		 * clamp the position the length of the shorter field. This
		 * matches how the scanline counter based position works since
		 * the scanline counter doesn't count the two half lines.
		 */
		if (position >= vtotal)
			position = vtotal - 1;

747 748 749 750 751 752 753 754 755 756
		/*
		 * Start of vblank interrupt is triggered at start of hsync,
		 * just prior to the first active line of vblank. However we
		 * consider lines to start at the leading edge of horizontal
		 * active. So, should we get here before we've crossed into
		 * the horizontal active of the first line in vblank, we would
		 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
		 * always add htotal-hsync_start to the current pixel position.
		 */
		position = (position + htotal - hsync_start) % vtotal;
757 758
	}

759 760 761 762 763 764 765 766
	/* Get optional system timestamp after query. */
	if (etime)
		*etime = ktime_get();

	/* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */

	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

767 768 769 770 771 772 773 774 775 776 777 778
	in_vbl = position >= vbl_start && position < vbl_end;

	/*
	 * While in vblank, position will be negative
	 * counting up towards 0 at vbl_end. And outside
	 * vblank, position will be positive counting
	 * up since vbl_end.
	 */
	if (position >= vbl_start)
		position -= vbl_end;
	else
		position += vtotal - vbl_end;
779

780
	if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
781 782 783 784 785 786
		*vpos = position;
		*hpos = 0;
	} else {
		*vpos = position / htotal;
		*hpos = position - (*vpos * htotal);
	}
787 788 789

	/* In vblank? */
	if (in_vbl)
790
		ret |= DRM_SCANOUTPOS_IN_VBLANK;
791 792 793 794

	return ret;
}

795 796 797 798 799 800 801 802 803 804 805 806 807
int intel_get_crtc_scanline(struct intel_crtc *crtc)
{
	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
	unsigned long irqflags;
	int position;

	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
	position = __intel_get_crtc_scanline(crtc);
	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

	return position;
}

808
static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
809 810 811 812
			      int *max_error,
			      struct timeval *vblank_time,
			      unsigned flags)
{
813
	struct drm_crtc *crtc;
814

815
	if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
816
		DRM_ERROR("Invalid crtc %d\n", pipe);
817 818 819 820
		return -EINVAL;
	}

	/* Get drm_crtc to timestamp: */
821 822 823 824 825 826 827 828 829 830
	crtc = intel_get_crtc_for_pipe(dev, pipe);
	if (crtc == NULL) {
		DRM_ERROR("Invalid crtc %d\n", pipe);
		return -EINVAL;
	}

	if (!crtc->enabled) {
		DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
		return -EBUSY;
	}
831 832

	/* Helper routine in DRM core does all the work: */
833 834
	return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
						     vblank_time, flags,
835 836
						     crtc,
						     &to_intel_crtc(crtc)->config.adjusted_mode);
837 838
}

839 840
static bool intel_hpd_irq_event(struct drm_device *dev,
				struct drm_connector *connector)
841 842 843 844 845 846 847
{
	enum drm_connector_status old_status;

	WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
	old_status = connector->status;

	connector->status = connector->funcs->detect(connector, false);
848 849 850 851
	if (old_status == connector->status)
		return false;

	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
852
		      connector->base.id,
853
		      connector->name,
854 855 856 857
		      drm_get_connector_status_name(old_status),
		      drm_get_connector_status_name(connector->status));

	return true;
858 859
}

860 861 862 863 864 865 866 867 868
static void i915_digport_work_func(struct work_struct *work)
{
	struct drm_i915_private *dev_priv =
		container_of(work, struct drm_i915_private, dig_port_work);
	u32 long_port_mask, short_port_mask;
	struct intel_digital_port *intel_dig_port;
	int i, ret;
	u32 old_bits = 0;

869
	spin_lock_irq(&dev_priv->irq_lock);
870 871 872 873
	long_port_mask = dev_priv->long_hpd_port_mask;
	dev_priv->long_hpd_port_mask = 0;
	short_port_mask = dev_priv->short_hpd_port_mask;
	dev_priv->short_hpd_port_mask = 0;
874
	spin_unlock_irq(&dev_priv->irq_lock);
875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898

	for (i = 0; i < I915_MAX_PORTS; i++) {
		bool valid = false;
		bool long_hpd = false;
		intel_dig_port = dev_priv->hpd_irq_port[i];
		if (!intel_dig_port || !intel_dig_port->hpd_pulse)
			continue;

		if (long_port_mask & (1 << i))  {
			valid = true;
			long_hpd = true;
		} else if (short_port_mask & (1 << i))
			valid = true;

		if (valid) {
			ret = intel_dig_port->hpd_pulse(intel_dig_port, long_hpd);
			if (ret == true) {
				/* if we get true fallback to old school hpd */
				old_bits |= (1 << intel_dig_port->base.hpd_pin);
			}
		}
	}

	if (old_bits) {
899
		spin_lock_irq(&dev_priv->irq_lock);
900
		dev_priv->hpd_event_bits |= old_bits;
901
		spin_unlock_irq(&dev_priv->irq_lock);
902 903 904 905
		schedule_work(&dev_priv->hotplug_work);
	}
}

906 907 908
/*
 * Handle hotplug events outside the interrupt handler proper.
 */
909 910
#define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)

911 912
static void i915_hotplug_work_func(struct work_struct *work)
{
913 914
	struct drm_i915_private *dev_priv =
		container_of(work, struct drm_i915_private, hotplug_work);
915
	struct drm_device *dev = dev_priv->dev;
916
	struct drm_mode_config *mode_config = &dev->mode_config;
917 918 919 920
	struct intel_connector *intel_connector;
	struct intel_encoder *intel_encoder;
	struct drm_connector *connector;
	bool hpd_disabled = false;
921
	bool changed = false;
922
	u32 hpd_event_bits;
923

924
	mutex_lock(&mode_config->mutex);
925 926
	DRM_DEBUG_KMS("running encoder hotplug functions\n");

927
	spin_lock_irq(&dev_priv->irq_lock);
928 929 930

	hpd_event_bits = dev_priv->hpd_event_bits;
	dev_priv->hpd_event_bits = 0;
931 932
	list_for_each_entry(connector, &mode_config->connector_list, head) {
		intel_connector = to_intel_connector(connector);
933 934
		if (!intel_connector->encoder)
			continue;
935 936 937 938 939 940
		intel_encoder = intel_connector->encoder;
		if (intel_encoder->hpd_pin > HPD_NONE &&
		    dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
		    connector->polled == DRM_CONNECTOR_POLL_HPD) {
			DRM_INFO("HPD interrupt storm detected on connector %s: "
				 "switching from hotplug detection to polling\n",
941
				connector->name);
942 943 944 945 946
			dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
			connector->polled = DRM_CONNECTOR_POLL_CONNECT
				| DRM_CONNECTOR_POLL_DISCONNECT;
			hpd_disabled = true;
		}
947 948
		if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
			DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
949
				      connector->name, intel_encoder->hpd_pin);
950
		}
951 952 953 954
	}
	 /* if there were no outputs to poll, poll was disabled,
	  * therefore make sure it's enabled when disabling HPD on
	  * some connectors */
955
	if (hpd_disabled) {
956
		drm_kms_helper_poll_enable(dev);
957 958
		mod_delayed_work(system_wq, &dev_priv->hotplug_reenable_work,
				 msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
959
	}
960

961
	spin_unlock_irq(&dev_priv->irq_lock);
962

963 964
	list_for_each_entry(connector, &mode_config->connector_list, head) {
		intel_connector = to_intel_connector(connector);
965 966
		if (!intel_connector->encoder)
			continue;
967 968 969 970 971 972 973 974
		intel_encoder = intel_connector->encoder;
		if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
			if (intel_encoder->hot_plug)
				intel_encoder->hot_plug(intel_encoder);
			if (intel_hpd_irq_event(dev, connector))
				changed = true;
		}
	}
975 976
	mutex_unlock(&mode_config->mutex);

977 978
	if (changed)
		drm_kms_helper_hotplug_event(dev);
979 980
}

981
static void ironlake_rps_change_irq_handler(struct drm_device *dev)
982
{
983
	struct drm_i915_private *dev_priv = dev->dev_private;
984
	u32 busy_up, busy_down, max_avg, min_avg;
985 986
	u8 new_delay;

987
	spin_lock(&mchdev_lock);
988

989 990
	I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));

991
	new_delay = dev_priv->ips.cur_delay;
992

993
	I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
994 995
	busy_up = I915_READ(RCPREVBSYTUPAVG);
	busy_down = I915_READ(RCPREVBSYTDNAVG);
996 997 998 999
	max_avg = I915_READ(RCBMAXAVG);
	min_avg = I915_READ(RCBMINAVG);

	/* Handle RCS change request from hw */
1000
	if (busy_up > max_avg) {
1001 1002 1003 1004
		if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
			new_delay = dev_priv->ips.cur_delay - 1;
		if (new_delay < dev_priv->ips.max_delay)
			new_delay = dev_priv->ips.max_delay;
1005
	} else if (busy_down < min_avg) {
1006 1007 1008 1009
		if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
			new_delay = dev_priv->ips.cur_delay + 1;
		if (new_delay > dev_priv->ips.min_delay)
			new_delay = dev_priv->ips.min_delay;
1010 1011
	}

1012
	if (ironlake_set_drps(dev, new_delay))
1013
		dev_priv->ips.cur_delay = new_delay;
1014

1015
	spin_unlock(&mchdev_lock);
1016

1017 1018 1019
	return;
}

1020
static void notify_ring(struct drm_device *dev,
1021
			struct intel_engine_cs *ring)
1022
{
1023
	if (!intel_ring_initialized(ring))
1024 1025
		return;

1026
	trace_i915_gem_request_notify(ring);
1027

1028 1029 1030
	wake_up_all(&ring->irq_queue);
}

1031
static u32 vlv_c0_residency(struct drm_i915_private *dev_priv,
1032
			    struct intel_rps_ei *rps_ei)
1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044
{
	u32 cz_ts, cz_freq_khz;
	u32 render_count, media_count;
	u32 elapsed_render, elapsed_media, elapsed_time;
	u32 residency = 0;

	cz_ts = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
	cz_freq_khz = DIV_ROUND_CLOSEST(dev_priv->mem_freq * 1000, 4);

	render_count = I915_READ(VLV_RENDER_C0_COUNT_REG);
	media_count = I915_READ(VLV_MEDIA_C0_COUNT_REG);

1045 1046 1047 1048
	if (rps_ei->cz_clock == 0) {
		rps_ei->cz_clock = cz_ts;
		rps_ei->render_c0 = render_count;
		rps_ei->media_c0 = media_count;
1049 1050 1051 1052

		return dev_priv->rps.cur_freq;
	}

1053 1054
	elapsed_time = cz_ts - rps_ei->cz_clock;
	rps_ei->cz_clock = cz_ts;
1055

1056 1057
	elapsed_render = render_count - rps_ei->render_c0;
	rps_ei->render_c0 = render_count;
1058

1059 1060
	elapsed_media = media_count - rps_ei->media_c0;
	rps_ei->media_c0 = media_count;
1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085

	/* Convert all the counters into common unit of milli sec */
	elapsed_time /= VLV_CZ_CLOCK_TO_MILLI_SEC;
	elapsed_render /=  cz_freq_khz;
	elapsed_media /= cz_freq_khz;

	/*
	 * Calculate overall C0 residency percentage
	 * only if elapsed time is non zero
	 */
	if (elapsed_time) {
		residency =
			((max(elapsed_render, elapsed_media) * 100)
				/ elapsed_time);
	}

	return residency;
}

/**
 * vlv_calc_delay_from_C0_counters - Increase/Decrease freq based on GPU
 * busy-ness calculated from C0 counters of render & media power wells
 * @dev_priv: DRM device private
 *
 */
1086
static int vlv_calc_delay_from_C0_counters(struct drm_i915_private *dev_priv)
1087 1088
{
	u32 residency_C0_up = 0, residency_C0_down = 0;
1089
	int new_delay, adj;
1090 1091 1092 1093 1094 1095

	dev_priv->rps.ei_interrupt_count++;

	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));


1096 1097 1098
	if (dev_priv->rps.up_ei.cz_clock == 0) {
		vlv_c0_residency(dev_priv, &dev_priv->rps.up_ei);
		vlv_c0_residency(dev_priv, &dev_priv->rps.down_ei);
1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112
		return dev_priv->rps.cur_freq;
	}


	/*
	 * To down throttle, C0 residency should be less than down threshold
	 * for continous EI intervals. So calculate down EI counters
	 * once in VLV_INT_COUNT_FOR_DOWN_EI
	 */
	if (dev_priv->rps.ei_interrupt_count == VLV_INT_COUNT_FOR_DOWN_EI) {

		dev_priv->rps.ei_interrupt_count = 0;

		residency_C0_down = vlv_c0_residency(dev_priv,
1113
						     &dev_priv->rps.down_ei);
1114 1115
	} else {
		residency_C0_up = vlv_c0_residency(dev_priv,
1116
						   &dev_priv->rps.up_ei);
1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155
	}

	new_delay = dev_priv->rps.cur_freq;

	adj = dev_priv->rps.last_adj;
	/* C0 residency is greater than UP threshold. Increase Frequency */
	if (residency_C0_up >= VLV_RP_UP_EI_THRESHOLD) {
		if (adj > 0)
			adj *= 2;
		else
			adj = 1;

		if (dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit)
			new_delay = dev_priv->rps.cur_freq + adj;

		/*
		 * For better performance, jump directly
		 * to RPe if we're below it.
		 */
		if (new_delay < dev_priv->rps.efficient_freq)
			new_delay = dev_priv->rps.efficient_freq;

	} else if (!dev_priv->rps.ei_interrupt_count &&
			(residency_C0_down < VLV_RP_DOWN_EI_THRESHOLD)) {
		if (adj < 0)
			adj *= 2;
		else
			adj = -1;
		/*
		 * This means, C0 residency is less than down threshold over
		 * a period of VLV_INT_COUNT_FOR_DOWN_EI. So, reduce the freq
		 */
		if (dev_priv->rps.cur_freq > dev_priv->rps.min_freq_softlimit)
			new_delay = dev_priv->rps.cur_freq + adj;
	}

	return new_delay;
}

1156
static void gen6_pm_rps_work(struct work_struct *work)
1157
{
1158 1159
	struct drm_i915_private *dev_priv =
		container_of(work, struct drm_i915_private, rps.work);
P
Paulo Zanoni 已提交
1160
	u32 pm_iir;
1161
	int new_delay, adj;
1162

1163
	spin_lock_irq(&dev_priv->irq_lock);
I
Imre Deak 已提交
1164 1165 1166 1167 1168
	/* Speed up work cancelation during disabling rps interrupts. */
	if (!dev_priv->rps.interrupts_enabled) {
		spin_unlock_irq(&dev_priv->irq_lock);
		return;
	}
1169 1170
	pm_iir = dev_priv->rps.pm_iir;
	dev_priv->rps.pm_iir = 0;
1171 1172
	/* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
	gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1173
	spin_unlock_irq(&dev_priv->irq_lock);
1174

1175
	/* Make sure we didn't queue anything we're not going to process. */
1176
	WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1177

1178
	if ((pm_iir & dev_priv->pm_rps_events) == 0)
1179 1180
		return;

1181
	mutex_lock(&dev_priv->rps.hw_lock);
1182

1183
	adj = dev_priv->rps.last_adj;
1184
	if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1185 1186
		if (adj > 0)
			adj *= 2;
1187 1188 1189 1190
		else {
			/* CHV needs even encode values */
			adj = IS_CHERRYVIEW(dev_priv->dev) ? 2 : 1;
		}
1191
		new_delay = dev_priv->rps.cur_freq + adj;
1192 1193 1194 1195 1196

		/*
		 * For better performance, jump directly
		 * to RPe if we're below it.
		 */
1197 1198
		if (new_delay < dev_priv->rps.efficient_freq)
			new_delay = dev_priv->rps.efficient_freq;
1199
	} else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1200 1201
		if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
			new_delay = dev_priv->rps.efficient_freq;
1202
		else
1203
			new_delay = dev_priv->rps.min_freq_softlimit;
1204
		adj = 0;
1205 1206
	} else if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
		new_delay = vlv_calc_delay_from_C0_counters(dev_priv);
1207 1208 1209
	} else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
		if (adj < 0)
			adj *= 2;
1210 1211 1212 1213
		else {
			/* CHV needs even encode values */
			adj = IS_CHERRYVIEW(dev_priv->dev) ? -2 : -1;
		}
1214
		new_delay = dev_priv->rps.cur_freq + adj;
1215
	} else { /* unknown event */
1216
		new_delay = dev_priv->rps.cur_freq;
1217
	}
1218

1219 1220 1221
	/* sysfs frequency interfaces may have snuck in while servicing the
	 * interrupt
	 */
1222
	new_delay = clamp_t(int, new_delay,
1223 1224
			    dev_priv->rps.min_freq_softlimit,
			    dev_priv->rps.max_freq_softlimit);
1225

1226
	dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq;
1227 1228 1229 1230 1231

	if (IS_VALLEYVIEW(dev_priv->dev))
		valleyview_set_rps(dev_priv->dev, new_delay);
	else
		gen6_set_rps(dev_priv->dev, new_delay);
1232

1233
	mutex_unlock(&dev_priv->rps.hw_lock);
1234 1235
}

1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247

/**
 * ivybridge_parity_work - Workqueue called when a parity error interrupt
 * occurred.
 * @work: workqueue struct
 *
 * Doesn't actually do anything except notify userspace. As a consequence of
 * this event, userspace should try to remap the bad rows since statistically
 * it is likely the same row is more likely to go bad again.
 */
static void ivybridge_parity_work(struct work_struct *work)
{
1248 1249
	struct drm_i915_private *dev_priv =
		container_of(work, struct drm_i915_private, l3_parity.error_work);
1250
	u32 error_status, row, bank, subbank;
1251
	char *parity_event[6];
1252
	uint32_t misccpctl;
1253
	uint8_t slice = 0;
1254 1255 1256 1257 1258 1259 1260

	/* We must turn off DOP level clock gating to access the L3 registers.
	 * In order to prevent a get/put style interface, acquire struct mutex
	 * any time we access those registers.
	 */
	mutex_lock(&dev_priv->dev->struct_mutex);

1261 1262 1263 1264
	/* If we've screwed up tracking, just let the interrupt fire again */
	if (WARN_ON(!dev_priv->l3_parity.which_slice))
		goto out;

1265 1266 1267 1268
	misccpctl = I915_READ(GEN7_MISCCPCTL);
	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
	POSTING_READ(GEN7_MISCCPCTL);

1269 1270
	while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
		u32 reg;
1271

1272 1273 1274
		slice--;
		if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
			break;
1275

1276
		dev_priv->l3_parity.which_slice &= ~(1<<slice);
1277

1278
		reg = GEN7_L3CDERRST1 + (slice * 0x200);
1279

1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294
		error_status = I915_READ(reg);
		row = GEN7_PARITY_ERROR_ROW(error_status);
		bank = GEN7_PARITY_ERROR_BANK(error_status);
		subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);

		I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
		POSTING_READ(reg);

		parity_event[0] = I915_L3_PARITY_UEVENT "=1";
		parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
		parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
		parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
		parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
		parity_event[5] = NULL;

1295
		kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1296
				   KOBJ_CHANGE, parity_event);
1297

1298 1299
		DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
			  slice, row, bank, subbank);
1300

1301 1302 1303 1304 1305
		kfree(parity_event[4]);
		kfree(parity_event[3]);
		kfree(parity_event[2]);
		kfree(parity_event[1]);
	}
1306

1307
	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1308

1309 1310
out:
	WARN_ON(dev_priv->l3_parity.which_slice);
1311
	spin_lock_irq(&dev_priv->irq_lock);
1312
	gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1313
	spin_unlock_irq(&dev_priv->irq_lock);
1314 1315

	mutex_unlock(&dev_priv->dev->struct_mutex);
1316 1317
}

1318
static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1319
{
1320
	struct drm_i915_private *dev_priv = dev->dev_private;
1321

1322
	if (!HAS_L3_DPF(dev))
1323 1324
		return;

1325
	spin_lock(&dev_priv->irq_lock);
1326
	gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1327
	spin_unlock(&dev_priv->irq_lock);
1328

1329 1330 1331 1332 1333 1334 1335
	iir &= GT_PARITY_ERROR(dev);
	if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
		dev_priv->l3_parity.which_slice |= 1 << 1;

	if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
		dev_priv->l3_parity.which_slice |= 1 << 0;

1336
	queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1337 1338
}

1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349
static void ilk_gt_irq_handler(struct drm_device *dev,
			       struct drm_i915_private *dev_priv,
			       u32 gt_iir)
{
	if (gt_iir &
	    (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
		notify_ring(dev, &dev_priv->ring[RCS]);
	if (gt_iir & ILK_BSD_USER_INTERRUPT)
		notify_ring(dev, &dev_priv->ring[VCS]);
}

1350 1351 1352 1353 1354
static void snb_gt_irq_handler(struct drm_device *dev,
			       struct drm_i915_private *dev_priv,
			       u32 gt_iir)
{

1355 1356
	if (gt_iir &
	    (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1357
		notify_ring(dev, &dev_priv->ring[RCS]);
1358
	if (gt_iir & GT_BSD_USER_INTERRUPT)
1359
		notify_ring(dev, &dev_priv->ring[VCS]);
1360
	if (gt_iir & GT_BLT_USER_INTERRUPT)
1361 1362
		notify_ring(dev, &dev_priv->ring[BCS]);

1363 1364
	if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
		      GT_BSD_CS_ERROR_INTERRUPT |
1365 1366
		      GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
		DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1367

1368 1369
	if (gt_iir & GT_PARITY_ERROR(dev))
		ivybridge_parity_error_irq_handler(dev, gt_iir);
1370 1371
}

1372 1373 1374 1375
static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
				       struct drm_i915_private *dev_priv,
				       u32 master_ctl)
{
1376
	struct intel_engine_cs *ring;
1377 1378 1379 1380 1381 1382 1383
	u32 rcs, bcs, vcs;
	uint32_t tmp = 0;
	irqreturn_t ret = IRQ_NONE;

	if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
		tmp = I915_READ(GEN8_GT_IIR(0));
		if (tmp) {
1384
			I915_WRITE(GEN8_GT_IIR(0), tmp);
1385
			ret = IRQ_HANDLED;
1386

1387
			rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1388
			ring = &dev_priv->ring[RCS];
1389
			if (rcs & GT_RENDER_USER_INTERRUPT)
1390 1391
				notify_ring(dev, ring);
			if (rcs & GT_CONTEXT_SWITCH_INTERRUPT)
1392
				intel_lrc_irq_handler(ring);
1393 1394 1395

			bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
			ring = &dev_priv->ring[BCS];
1396
			if (bcs & GT_RENDER_USER_INTERRUPT)
1397 1398
				notify_ring(dev, ring);
			if (bcs & GT_CONTEXT_SWITCH_INTERRUPT)
1399
				intel_lrc_irq_handler(ring);
1400 1401 1402 1403
		} else
			DRM_ERROR("The master control interrupt lied (GT0)!\n");
	}

1404
	if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1405 1406
		tmp = I915_READ(GEN8_GT_IIR(1));
		if (tmp) {
1407
			I915_WRITE(GEN8_GT_IIR(1), tmp);
1408
			ret = IRQ_HANDLED;
1409

1410
			vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1411
			ring = &dev_priv->ring[VCS];
1412
			if (vcs & GT_RENDER_USER_INTERRUPT)
1413
				notify_ring(dev, ring);
1414
			if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1415
				intel_lrc_irq_handler(ring);
1416

1417
			vcs = tmp >> GEN8_VCS2_IRQ_SHIFT;
1418
			ring = &dev_priv->ring[VCS2];
1419
			if (vcs & GT_RENDER_USER_INTERRUPT)
1420
				notify_ring(dev, ring);
1421
			if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1422
				intel_lrc_irq_handler(ring);
1423 1424 1425 1426
		} else
			DRM_ERROR("The master control interrupt lied (GT1)!\n");
	}

1427 1428 1429 1430 1431
	if (master_ctl & GEN8_GT_PM_IRQ) {
		tmp = I915_READ(GEN8_GT_IIR(2));
		if (tmp & dev_priv->pm_rps_events) {
			I915_WRITE(GEN8_GT_IIR(2),
				   tmp & dev_priv->pm_rps_events);
1432
			ret = IRQ_HANDLED;
1433
			gen6_rps_irq_handler(dev_priv, tmp);
1434 1435 1436 1437
		} else
			DRM_ERROR("The master control interrupt lied (PM)!\n");
	}

1438 1439 1440
	if (master_ctl & GEN8_GT_VECS_IRQ) {
		tmp = I915_READ(GEN8_GT_IIR(3));
		if (tmp) {
1441
			I915_WRITE(GEN8_GT_IIR(3), tmp);
1442
			ret = IRQ_HANDLED;
1443

1444
			vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1445
			ring = &dev_priv->ring[VECS];
1446
			if (vcs & GT_RENDER_USER_INTERRUPT)
1447
				notify_ring(dev, ring);
1448
			if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1449
				intel_lrc_irq_handler(ring);
1450 1451 1452 1453 1454 1455 1456
		} else
			DRM_ERROR("The master control interrupt lied (GT3)!\n");
	}

	return ret;
}

1457 1458 1459
#define HPD_STORM_DETECT_PERIOD 1000
#define HPD_STORM_THRESHOLD 5

1460
static int pch_port_to_hotplug_shift(enum port port)
1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475
{
	switch (port) {
	case PORT_A:
	case PORT_E:
	default:
		return -1;
	case PORT_B:
		return 0;
	case PORT_C:
		return 8;
	case PORT_D:
		return 16;
	}
}

1476
static int i915_port_to_hotplug_shift(enum port port)
1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505
{
	switch (port) {
	case PORT_A:
	case PORT_E:
	default:
		return -1;
	case PORT_B:
		return 17;
	case PORT_C:
		return 19;
	case PORT_D:
		return 21;
	}
}

static inline enum port get_port_from_pin(enum hpd_pin pin)
{
	switch (pin) {
	case HPD_PORT_B:
		return PORT_B;
	case HPD_PORT_C:
		return PORT_C;
	case HPD_PORT_D:
		return PORT_D;
	default:
		return PORT_A; /* no hpd */
	}
}

1506
static inline void intel_hpd_irq_handler(struct drm_device *dev,
1507
					 u32 hotplug_trigger,
1508
					 u32 dig_hotplug_reg,
1509
					 const u32 *hpd)
1510
{
1511
	struct drm_i915_private *dev_priv = dev->dev_private;
1512
	int i;
1513
	enum port port;
1514
	bool storm_detected = false;
1515 1516 1517
	bool queue_dig = false, queue_hp = false;
	u32 dig_shift;
	u32 dig_port_mask = 0;
1518

1519 1520 1521
	if (!hotplug_trigger)
		return;

1522 1523
	DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x\n",
			 hotplug_trigger, dig_hotplug_reg);
1524

1525
	spin_lock(&dev_priv->irq_lock);
1526
	for (i = 1; i < HPD_NUM_PINS; i++) {
1527 1528 1529 1530 1531 1532 1533
		if (!(hpd[i] & hotplug_trigger))
			continue;

		port = get_port_from_pin(i);
		if (port && dev_priv->hpd_irq_port[port]) {
			bool long_hpd;

1534 1535
			if (HAS_PCH_SPLIT(dev)) {
				dig_shift = pch_port_to_hotplug_shift(port);
1536
				long_hpd = (dig_hotplug_reg >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
1537 1538 1539
			} else {
				dig_shift = i915_port_to_hotplug_shift(port);
				long_hpd = (hotplug_trigger >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
1540 1541
			}

1542 1543 1544
			DRM_DEBUG_DRIVER("digital hpd port %c - %s\n",
					 port_name(port),
					 long_hpd ? "long" : "short");
1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557
			/* for long HPD pulses we want to have the digital queue happen,
			   but we still want HPD storm detection to function. */
			if (long_hpd) {
				dev_priv->long_hpd_port_mask |= (1 << port);
				dig_port_mask |= hpd[i];
			} else {
				/* for short HPD just trigger the digital queue */
				dev_priv->short_hpd_port_mask |= (1 << port);
				hotplug_trigger &= ~hpd[i];
			}
			queue_dig = true;
		}
	}
1558

1559
	for (i = 1; i < HPD_NUM_PINS; i++) {
1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573
		if (hpd[i] & hotplug_trigger &&
		    dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) {
			/*
			 * On GMCH platforms the interrupt mask bits only
			 * prevent irq generation, not the setting of the
			 * hotplug bits itself. So only WARN about unexpected
			 * interrupts on saner platforms.
			 */
			WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
				  "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
				  hotplug_trigger, i, hpd[i]);

			continue;
		}
1574

1575 1576 1577 1578
		if (!(hpd[i] & hotplug_trigger) ||
		    dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
			continue;

1579 1580 1581 1582 1583
		if (!(dig_port_mask & hpd[i])) {
			dev_priv->hpd_event_bits |= (1 << i);
			queue_hp = true;
		}

1584 1585 1586 1587 1588
		if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
				   dev_priv->hpd_stats[i].hpd_last_jiffies
				   + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
			dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
			dev_priv->hpd_stats[i].hpd_cnt = 0;
1589
			DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1590 1591
		} else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
			dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1592
			dev_priv->hpd_event_bits &= ~(1 << i);
1593
			DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1594
			storm_detected = true;
1595 1596
		} else {
			dev_priv->hpd_stats[i].hpd_cnt++;
1597 1598
			DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
				      dev_priv->hpd_stats[i].hpd_cnt);
1599 1600 1601
		}
	}

1602 1603
	if (storm_detected)
		dev_priv->display.hpd_irq_setup(dev);
1604
	spin_unlock(&dev_priv->irq_lock);
1605

1606 1607 1608 1609 1610 1611
	/*
	 * Our hotplug handler can grab modeset locks (by calling down into the
	 * fb helpers). Hence it must not be run on our own dev-priv->wq work
	 * queue for otherwise the flush_work in the pageflip code will
	 * deadlock.
	 */
1612
	if (queue_dig)
1613
		queue_work(dev_priv->dp_wq, &dev_priv->dig_port_work);
1614 1615
	if (queue_hp)
		schedule_work(&dev_priv->hotplug_work);
1616 1617
}

1618 1619
static void gmbus_irq_handler(struct drm_device *dev)
{
1620
	struct drm_i915_private *dev_priv = dev->dev_private;
1621 1622

	wake_up_all(&dev_priv->gmbus_wait_queue);
1623 1624
}

1625 1626
static void dp_aux_irq_handler(struct drm_device *dev)
{
1627
	struct drm_i915_private *dev_priv = dev->dev_private;
1628 1629

	wake_up_all(&dev_priv->gmbus_wait_queue);
1630 1631
}

1632
#if defined(CONFIG_DEBUG_FS)
1633 1634 1635 1636
static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
					 uint32_t crc0, uint32_t crc1,
					 uint32_t crc2, uint32_t crc3,
					 uint32_t crc4)
1637 1638 1639 1640
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
	struct intel_pipe_crc_entry *entry;
1641
	int head, tail;
1642

1643 1644
	spin_lock(&pipe_crc->lock);

1645
	if (!pipe_crc->entries) {
1646
		spin_unlock(&pipe_crc->lock);
1647
		DRM_DEBUG_KMS("spurious interrupt\n");
1648 1649 1650
		return;
	}

1651 1652
	head = pipe_crc->head;
	tail = pipe_crc->tail;
1653 1654

	if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1655
		spin_unlock(&pipe_crc->lock);
1656 1657 1658 1659 1660
		DRM_ERROR("CRC buffer overflowing\n");
		return;
	}

	entry = &pipe_crc->entries[head];
1661

1662
	entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1663 1664 1665 1666 1667
	entry->crc[0] = crc0;
	entry->crc[1] = crc1;
	entry->crc[2] = crc2;
	entry->crc[3] = crc3;
	entry->crc[4] = crc4;
1668 1669

	head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1670 1671 1672
	pipe_crc->head = head;

	spin_unlock(&pipe_crc->lock);
1673 1674

	wake_up_interruptible(&pipe_crc->wq);
1675
}
1676 1677 1678 1679 1680 1681 1682 1683
#else
static inline void
display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
			     uint32_t crc0, uint32_t crc1,
			     uint32_t crc2, uint32_t crc3,
			     uint32_t crc4) {}
#endif

1684

1685
static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
D
Daniel Vetter 已提交
1686 1687 1688
{
	struct drm_i915_private *dev_priv = dev->dev_private;

1689 1690 1691
	display_pipe_crc_irq_handler(dev, pipe,
				     I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
				     0, 0, 0, 0);
D
Daniel Vetter 已提交
1692 1693
}

1694
static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1695 1696 1697
{
	struct drm_i915_private *dev_priv = dev->dev_private;

1698 1699 1700 1701 1702 1703
	display_pipe_crc_irq_handler(dev, pipe,
				     I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
				     I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
				     I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
				     I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
				     I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1704
}
1705

1706
static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1707 1708
{
	struct drm_i915_private *dev_priv = dev->dev_private;
1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719
	uint32_t res1, res2;

	if (INTEL_INFO(dev)->gen >= 3)
		res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
	else
		res1 = 0;

	if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
		res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
	else
		res2 = 0;
1720

1721 1722 1723 1724 1725
	display_pipe_crc_irq_handler(dev, pipe,
				     I915_READ(PIPE_CRC_RES_RED(pipe)),
				     I915_READ(PIPE_CRC_RES_GREEN(pipe)),
				     I915_READ(PIPE_CRC_RES_BLUE(pipe)),
				     res1, res2);
1726
}
1727

1728 1729 1730 1731
/* The RPS events need forcewake, so we add them to a work queue and mask their
 * IMR bits until the work is done. Other interrupts can be processed without
 * the work queue. */
static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1732
{
1733 1734 1735
	/* TODO: RPS on GEN9+ is not supported yet. */
	if (WARN_ONCE(INTEL_INFO(dev_priv)->gen >= 9,
		      "GEN9+: unexpected RPS IRQ\n"))
1736 1737
		return;

1738
	if (pm_iir & dev_priv->pm_rps_events) {
1739
		spin_lock(&dev_priv->irq_lock);
1740
		gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
I
Imre Deak 已提交
1741 1742 1743 1744
		if (dev_priv->rps.interrupts_enabled) {
			dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
			queue_work(dev_priv->wq, &dev_priv->rps.work);
		}
1745
		spin_unlock(&dev_priv->irq_lock);
1746 1747
	}

1748 1749 1750
	if (INTEL_INFO(dev_priv)->gen >= 8)
		return;

1751 1752 1753
	if (HAS_VEBOX(dev_priv->dev)) {
		if (pm_iir & PM_VEBOX_USER_INTERRUPT)
			notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
B
Ben Widawsky 已提交
1754

1755 1756
		if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
			DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
B
Ben Widawsky 已提交
1757
	}
1758 1759
}

1760 1761 1762 1763 1764 1765 1766 1767
static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
{
	if (!drm_handle_vblank(dev, pipe))
		return false;

	return true;
}

1768 1769 1770
static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
1771
	u32 pipe_stats[I915_MAX_PIPES] = { };
1772 1773
	int pipe;

1774
	spin_lock(&dev_priv->irq_lock);
1775
	for_each_pipe(dev_priv, pipe) {
1776
		int reg;
1777
		u32 mask, iir_bit = 0;
1778

1779 1780 1781 1782 1783 1784 1785
		/*
		 * PIPESTAT bits get signalled even when the interrupt is
		 * disabled with the mask bits, and some of the status bits do
		 * not generate interrupts at all (like the underrun bit). Hence
		 * we need to be careful that we only handle what we want to
		 * handle.
		 */
1786 1787 1788

		/* fifo underruns are filterered in the underrun handler. */
		mask = PIPE_FIFO_UNDERRUN_STATUS;
1789 1790 1791 1792 1793 1794 1795 1796

		switch (pipe) {
		case PIPE_A:
			iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
			break;
		case PIPE_B:
			iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
			break;
1797 1798 1799
		case PIPE_C:
			iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
			break;
1800 1801 1802 1803 1804
		}
		if (iir & iir_bit)
			mask |= dev_priv->pipestat_irq_mask[pipe];

		if (!mask)
1805 1806 1807
			continue;

		reg = PIPESTAT(pipe);
1808 1809
		mask |= PIPESTAT_INT_ENABLE_MASK;
		pipe_stats[pipe] = I915_READ(reg) & mask;
1810 1811 1812 1813

		/*
		 * Clear the PIPE*STAT regs before the IIR
		 */
1814 1815
		if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
					PIPESTAT_INT_STATUS_MASK))
1816 1817
			I915_WRITE(reg, pipe_stats[pipe]);
	}
1818
	spin_unlock(&dev_priv->irq_lock);
1819

1820
	for_each_pipe(dev_priv, pipe) {
1821 1822 1823
		if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
		    intel_pipe_handle_vblank(dev, pipe))
			intel_check_page_flip(dev, pipe);
1824

1825
		if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
1826 1827 1828 1829 1830 1831 1832
			intel_prepare_page_flip(dev, pipe);
			intel_finish_page_flip(dev, pipe);
		}

		if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
			i9xx_pipe_crc_irq_handler(dev, pipe);

1833 1834
		if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1835 1836 1837 1838 1839 1840
	}

	if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
		gmbus_irq_handler(dev);
}

1841 1842 1843 1844 1845
static void i9xx_hpd_irq_handler(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);

1846 1847 1848 1849 1850 1851 1852
	if (hotplug_status) {
		I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
		/*
		 * Make sure hotplug status is cleared before we clear IIR, or else we
		 * may miss hotplug events.
		 */
		POSTING_READ(PORT_HOTPLUG_STAT);
1853

1854 1855
		if (IS_G4X(dev)) {
			u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1856

1857
			intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_g4x);
1858 1859
		} else {
			u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1860

1861
			intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_i915);
1862
		}
1863

1864 1865 1866 1867
		if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) &&
		    hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
			dp_aux_irq_handler(dev);
	}
1868 1869
}

1870
static irqreturn_t valleyview_irq_handler(int irq, void *arg)
J
Jesse Barnes 已提交
1871
{
1872
	struct drm_device *dev = arg;
1873
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
1874 1875 1876 1877
	u32 iir, gt_iir, pm_iir;
	irqreturn_t ret = IRQ_NONE;

	while (true) {
1878 1879
		/* Find, clear, then process each source of interrupt */

J
Jesse Barnes 已提交
1880
		gt_iir = I915_READ(GTIIR);
1881 1882 1883
		if (gt_iir)
			I915_WRITE(GTIIR, gt_iir);

J
Jesse Barnes 已提交
1884
		pm_iir = I915_READ(GEN6_PMIIR);
1885 1886 1887 1888 1889 1890 1891 1892 1893 1894
		if (pm_iir)
			I915_WRITE(GEN6_PMIIR, pm_iir);

		iir = I915_READ(VLV_IIR);
		if (iir) {
			/* Consume port before clearing IIR or we'll miss events */
			if (iir & I915_DISPLAY_PORT_INTERRUPT)
				i9xx_hpd_irq_handler(dev);
			I915_WRITE(VLV_IIR, iir);
		}
J
Jesse Barnes 已提交
1895 1896 1897 1898 1899 1900

		if (gt_iir == 0 && pm_iir == 0 && iir == 0)
			goto out;

		ret = IRQ_HANDLED;

1901 1902
		if (gt_iir)
			snb_gt_irq_handler(dev, dev_priv, gt_iir);
1903
		if (pm_iir)
1904
			gen6_rps_irq_handler(dev_priv, pm_iir);
1905 1906 1907
		/* Call regardless, as some status bits might not be
		 * signalled in iir */
		valleyview_pipestat_irq_handler(dev, iir);
J
Jesse Barnes 已提交
1908 1909 1910 1911 1912 1913
	}

out:
	return ret;
}

1914 1915
static irqreturn_t cherryview_irq_handler(int irq, void *arg)
{
1916
	struct drm_device *dev = arg;
1917 1918 1919 1920
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 master_ctl, iir;
	irqreturn_t ret = IRQ_NONE;

1921 1922 1923
	for (;;) {
		master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
		iir = I915_READ(VLV_IIR);
1924

1925 1926
		if (master_ctl == 0 && iir == 0)
			break;
1927

1928 1929
		ret = IRQ_HANDLED;

1930
		I915_WRITE(GEN8_MASTER_IRQ, 0);
1931

1932
		/* Find, clear, then process each source of interrupt */
1933

1934 1935 1936 1937 1938 1939
		if (iir) {
			/* Consume port before clearing IIR or we'll miss events */
			if (iir & I915_DISPLAY_PORT_INTERRUPT)
				i9xx_hpd_irq_handler(dev);
			I915_WRITE(VLV_IIR, iir);
		}
1940

1941
		gen8_gt_irq_handler(dev, dev_priv, master_ctl);
1942

1943 1944 1945
		/* Call regardless, as some status bits might not be
		 * signalled in iir */
		valleyview_pipestat_irq_handler(dev, iir);
1946

1947 1948 1949
		I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
		POSTING_READ(GEN8_MASTER_IRQ);
	}
1950

1951 1952 1953
	return ret;
}

1954
static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1955
{
1956
	struct drm_i915_private *dev_priv = dev->dev_private;
1957
	int pipe;
1958
	u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1959 1960 1961 1962
	u32 dig_hotplug_reg;

	dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
	I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1963

1964
	intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_ibx);
1965

1966 1967 1968
	if (pch_iir & SDE_AUDIO_POWER_MASK) {
		int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
			       SDE_AUDIO_POWER_SHIFT);
1969
		DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1970 1971
				 port_name(port));
	}
1972

1973 1974 1975
	if (pch_iir & SDE_AUX_MASK)
		dp_aux_irq_handler(dev);

1976
	if (pch_iir & SDE_GMBUS)
1977
		gmbus_irq_handler(dev);
1978 1979 1980 1981 1982 1983 1984 1985 1986 1987

	if (pch_iir & SDE_AUDIO_HDCP_MASK)
		DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");

	if (pch_iir & SDE_AUDIO_TRANS_MASK)
		DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");

	if (pch_iir & SDE_POISON)
		DRM_ERROR("PCH poison interrupt\n");

1988
	if (pch_iir & SDE_FDI_MASK)
1989
		for_each_pipe(dev_priv, pipe)
1990 1991 1992
			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
					 pipe_name(pipe),
					 I915_READ(FDI_RX_IIR(pipe)));
1993 1994 1995 1996 1997 1998 1999 2000

	if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
		DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");

	if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
		DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");

	if (pch_iir & SDE_TRANSA_FIFO_UNDER)
2001
		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2002 2003

	if (pch_iir & SDE_TRANSB_FIFO_UNDER)
2004
		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2005 2006 2007 2008 2009 2010
}

static void ivb_err_int_handler(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 err_int = I915_READ(GEN7_ERR_INT);
D
Daniel Vetter 已提交
2011
	enum pipe pipe;
2012

2013 2014 2015
	if (err_int & ERR_INT_POISON)
		DRM_ERROR("Poison interrupt\n");

2016
	for_each_pipe(dev_priv, pipe) {
2017 2018
		if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2019

D
Daniel Vetter 已提交
2020 2021
		if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
			if (IS_IVYBRIDGE(dev))
2022
				ivb_pipe_crc_irq_handler(dev, pipe);
D
Daniel Vetter 已提交
2023
			else
2024
				hsw_pipe_crc_irq_handler(dev, pipe);
D
Daniel Vetter 已提交
2025 2026
		}
	}
2027

2028 2029 2030 2031 2032 2033 2034 2035
	I915_WRITE(GEN7_ERR_INT, err_int);
}

static void cpt_serr_int_handler(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 serr_int = I915_READ(SERR_INT);

2036 2037 2038
	if (serr_int & SERR_INT_POISON)
		DRM_ERROR("PCH poison interrupt\n");

2039
	if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2040
		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2041 2042

	if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2043
		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2044 2045

	if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2046
		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
2047 2048

	I915_WRITE(SERR_INT, serr_int);
2049 2050
}

2051 2052
static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
{
2053
	struct drm_i915_private *dev_priv = dev->dev_private;
2054
	int pipe;
2055
	u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2056 2057 2058 2059
	u32 dig_hotplug_reg;

	dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
	I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2060

2061
	intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_cpt);
2062

2063 2064 2065 2066 2067 2068
	if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
		int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
			       SDE_AUDIO_POWER_SHIFT_CPT);
		DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
				 port_name(port));
	}
2069 2070

	if (pch_iir & SDE_AUX_MASK_CPT)
2071
		dp_aux_irq_handler(dev);
2072 2073

	if (pch_iir & SDE_GMBUS_CPT)
2074
		gmbus_irq_handler(dev);
2075 2076 2077 2078 2079 2080 2081 2082

	if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
		DRM_DEBUG_DRIVER("Audio CP request interrupt\n");

	if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
		DRM_DEBUG_DRIVER("Audio CP change interrupt\n");

	if (pch_iir & SDE_FDI_MASK_CPT)
2083
		for_each_pipe(dev_priv, pipe)
2084 2085 2086
			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
					 pipe_name(pipe),
					 I915_READ(FDI_RX_IIR(pipe)));
2087 2088 2089

	if (pch_iir & SDE_ERROR_CPT)
		cpt_serr_int_handler(dev);
2090 2091
}

2092 2093 2094
static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2095
	enum pipe pipe;
2096 2097 2098 2099 2100 2101 2102 2103 2104 2105

	if (de_iir & DE_AUX_CHANNEL_A)
		dp_aux_irq_handler(dev);

	if (de_iir & DE_GSE)
		intel_opregion_asle_intr(dev);

	if (de_iir & DE_POISON)
		DRM_ERROR("Poison interrupt\n");

2106
	for_each_pipe(dev_priv, pipe) {
2107 2108 2109
		if (de_iir & DE_PIPE_VBLANK(pipe) &&
		    intel_pipe_handle_vblank(dev, pipe))
			intel_check_page_flip(dev, pipe);
2110

2111
		if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2112
			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2113

2114 2115
		if (de_iir & DE_PIPE_CRC_DONE(pipe))
			i9xx_pipe_crc_irq_handler(dev, pipe);
2116

2117 2118 2119 2120 2121
		/* plane/pipes map 1:1 on ilk+ */
		if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
			intel_prepare_page_flip(dev, pipe);
			intel_finish_page_flip_plane(dev, pipe);
		}
2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140
	}

	/* check event from PCH */
	if (de_iir & DE_PCH_EVENT) {
		u32 pch_iir = I915_READ(SDEIIR);

		if (HAS_PCH_CPT(dev))
			cpt_irq_handler(dev, pch_iir);
		else
			ibx_irq_handler(dev, pch_iir);

		/* should clear PCH hotplug event before clear CPU irq */
		I915_WRITE(SDEIIR, pch_iir);
	}

	if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
		ironlake_rps_change_irq_handler(dev);
}

2141 2142 2143
static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2144
	enum pipe pipe;
2145 2146 2147 2148 2149 2150 2151 2152 2153 2154

	if (de_iir & DE_ERR_INT_IVB)
		ivb_err_int_handler(dev);

	if (de_iir & DE_AUX_CHANNEL_A_IVB)
		dp_aux_irq_handler(dev);

	if (de_iir & DE_GSE_IVB)
		intel_opregion_asle_intr(dev);

2155
	for_each_pipe(dev_priv, pipe) {
2156 2157 2158
		if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
		    intel_pipe_handle_vblank(dev, pipe))
			intel_check_page_flip(dev, pipe);
2159 2160

		/* plane/pipes map 1:1 on ilk+ */
2161 2162 2163
		if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
			intel_prepare_page_flip(dev, pipe);
			intel_finish_page_flip_plane(dev, pipe);
2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177
		}
	}

	/* check event from PCH */
	if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
		u32 pch_iir = I915_READ(SDEIIR);

		cpt_irq_handler(dev, pch_iir);

		/* clear PCH hotplug event before clear CPU irq */
		I915_WRITE(SDEIIR, pch_iir);
	}
}

2178 2179 2180 2181 2182 2183 2184 2185
/*
 * To handle irqs with the minimum potential races with fresh interrupts, we:
 * 1 - Disable Master Interrupt Control.
 * 2 - Find the source(s) of the interrupt.
 * 3 - Clear the Interrupt Identity bits (IIR).
 * 4 - Process the interrupt(s) that had bits set in the IIRs.
 * 5 - Re-enable Master Interrupt Control.
 */
2186
static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2187
{
2188
	struct drm_device *dev = arg;
2189
	struct drm_i915_private *dev_priv = dev->dev_private;
2190
	u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2191
	irqreturn_t ret = IRQ_NONE;
2192

2193 2194
	/* We get interrupts on unclaimed registers, so check for this before we
	 * do any I915_{READ,WRITE}. */
2195
	intel_uncore_check_errors(dev);
2196

2197 2198 2199
	/* disable master interrupt before clearing iir  */
	de_ier = I915_READ(DEIER);
	I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2200
	POSTING_READ(DEIER);
2201

2202 2203 2204 2205 2206
	/* Disable south interrupts. We'll only write to SDEIIR once, so further
	 * interrupts will will be stored on its back queue, and then we'll be
	 * able to process them after we restore SDEIER (as soon as we restore
	 * it, we'll get an interrupt if SDEIIR still has something to process
	 * due to its back queue). */
2207 2208 2209 2210 2211
	if (!HAS_PCH_NOP(dev)) {
		sde_ier = I915_READ(SDEIER);
		I915_WRITE(SDEIER, 0);
		POSTING_READ(SDEIER);
	}
2212

2213 2214
	/* Find, clear, then process each source of interrupt */

2215
	gt_iir = I915_READ(GTIIR);
2216
	if (gt_iir) {
2217 2218
		I915_WRITE(GTIIR, gt_iir);
		ret = IRQ_HANDLED;
2219
		if (INTEL_INFO(dev)->gen >= 6)
2220
			snb_gt_irq_handler(dev, dev_priv, gt_iir);
2221 2222
		else
			ilk_gt_irq_handler(dev, dev_priv, gt_iir);
2223 2224
	}

2225 2226
	de_iir = I915_READ(DEIIR);
	if (de_iir) {
2227 2228
		I915_WRITE(DEIIR, de_iir);
		ret = IRQ_HANDLED;
2229 2230 2231 2232
		if (INTEL_INFO(dev)->gen >= 7)
			ivb_display_irq_handler(dev, de_iir);
		else
			ilk_display_irq_handler(dev, de_iir);
2233 2234
	}

2235 2236 2237 2238 2239
	if (INTEL_INFO(dev)->gen >= 6) {
		u32 pm_iir = I915_READ(GEN6_PMIIR);
		if (pm_iir) {
			I915_WRITE(GEN6_PMIIR, pm_iir);
			ret = IRQ_HANDLED;
2240
			gen6_rps_irq_handler(dev_priv, pm_iir);
2241
		}
2242
	}
2243 2244 2245

	I915_WRITE(DEIER, de_ier);
	POSTING_READ(DEIER);
2246 2247 2248 2249
	if (!HAS_PCH_NOP(dev)) {
		I915_WRITE(SDEIER, sde_ier);
		POSTING_READ(SDEIER);
	}
2250 2251 2252 2253

	return ret;
}

2254 2255 2256 2257 2258 2259 2260
static irqreturn_t gen8_irq_handler(int irq, void *arg)
{
	struct drm_device *dev = arg;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 master_ctl;
	irqreturn_t ret = IRQ_NONE;
	uint32_t tmp = 0;
2261
	enum pipe pipe;
J
Jesse Barnes 已提交
2262 2263 2264 2265 2266
	u32 aux_mask = GEN8_AUX_CHANNEL_A;

	if (IS_GEN9(dev))
		aux_mask |=  GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
			GEN9_AUX_CHANNEL_D;
2267 2268 2269 2270 2271 2272 2273 2274 2275

	master_ctl = I915_READ(GEN8_MASTER_IRQ);
	master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
	if (!master_ctl)
		return IRQ_NONE;

	I915_WRITE(GEN8_MASTER_IRQ, 0);
	POSTING_READ(GEN8_MASTER_IRQ);

2276 2277
	/* Find, clear, then process each source of interrupt */

2278 2279 2280 2281 2282 2283 2284
	ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);

	if (master_ctl & GEN8_DE_MISC_IRQ) {
		tmp = I915_READ(GEN8_DE_MISC_IIR);
		if (tmp) {
			I915_WRITE(GEN8_DE_MISC_IIR, tmp);
			ret = IRQ_HANDLED;
2285 2286 2287 2288
			if (tmp & GEN8_DE_MISC_GSE)
				intel_opregion_asle_intr(dev);
			else
				DRM_ERROR("Unexpected DE Misc interrupt\n");
2289
		}
2290 2291
		else
			DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2292 2293
	}

2294 2295 2296 2297 2298
	if (master_ctl & GEN8_DE_PORT_IRQ) {
		tmp = I915_READ(GEN8_DE_PORT_IIR);
		if (tmp) {
			I915_WRITE(GEN8_DE_PORT_IIR, tmp);
			ret = IRQ_HANDLED;
J
Jesse Barnes 已提交
2299 2300

			if (tmp & aux_mask)
2301 2302 2303
				dp_aux_irq_handler(dev);
			else
				DRM_ERROR("Unexpected DE Port interrupt\n");
2304
		}
2305 2306
		else
			DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2307 2308
	}

2309
	for_each_pipe(dev_priv, pipe) {
2310
		uint32_t pipe_iir, flip_done = 0, fault_errors = 0;
2311

2312 2313
		if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
			continue;
2314

2315 2316 2317 2318
		pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
		if (pipe_iir) {
			ret = IRQ_HANDLED;
			I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2319

2320 2321 2322
			if (pipe_iir & GEN8_PIPE_VBLANK &&
			    intel_pipe_handle_vblank(dev, pipe))
				intel_check_page_flip(dev, pipe);
2323

2324 2325 2326 2327 2328 2329
			if (IS_GEN9(dev))
				flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE;
			else
				flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE;

			if (flip_done) {
2330 2331 2332 2333 2334 2335 2336
				intel_prepare_page_flip(dev, pipe);
				intel_finish_page_flip_plane(dev, pipe);
			}

			if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
				hsw_pipe_crc_irq_handler(dev, pipe);

2337 2338 2339
			if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN)
				intel_cpu_fifo_underrun_irq_handler(dev_priv,
								    pipe);
2340

2341 2342 2343 2344 2345 2346 2347

			if (IS_GEN9(dev))
				fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
			else
				fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS;

			if (fault_errors)
2348 2349 2350
				DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
					  pipe_name(pipe),
					  pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2351
		} else
2352 2353 2354
			DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
	}

2355 2356 2357 2358 2359 2360 2361 2362 2363 2364
	if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
		/*
		 * FIXME(BDW): Assume for now that the new interrupt handling
		 * scheme also closed the SDE interrupt handling race we've seen
		 * on older pch-split platforms. But this needs testing.
		 */
		u32 pch_iir = I915_READ(SDEIIR);
		if (pch_iir) {
			I915_WRITE(SDEIIR, pch_iir);
			ret = IRQ_HANDLED;
2365 2366 2367 2368
			cpt_irq_handler(dev, pch_iir);
		} else
			DRM_ERROR("The master control interrupt lied (SDE)!\n");

2369 2370
	}

2371 2372 2373 2374 2375 2376
	I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
	POSTING_READ(GEN8_MASTER_IRQ);

	return ret;
}

2377 2378 2379
static void i915_error_wake_up(struct drm_i915_private *dev_priv,
			       bool reset_completed)
{
2380
	struct intel_engine_cs *ring;
2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404
	int i;

	/*
	 * Notify all waiters for GPU completion events that reset state has
	 * been changed, and that they need to restart their wait after
	 * checking for potential errors (and bail out to drop locks if there is
	 * a gpu reset pending so that i915_error_work_func can acquire them).
	 */

	/* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
	for_each_ring(ring, dev_priv, i)
		wake_up_all(&ring->irq_queue);

	/* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
	wake_up_all(&dev_priv->pending_flip_queue);

	/*
	 * Signal tasks blocked in i915_gem_wait_for_error that the pending
	 * reset state is cleared.
	 */
	if (reset_completed)
		wake_up_all(&dev_priv->gpu_error.reset_queue);
}

2405 2406 2407 2408 2409 2410 2411 2412 2413
/**
 * i915_error_work_func - do process context error handling work
 * @work: work struct
 *
 * Fire an error uevent so userspace can see that a hang or error
 * was detected.
 */
static void i915_error_work_func(struct work_struct *work)
{
2414 2415
	struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
						    work);
2416 2417
	struct drm_i915_private *dev_priv =
		container_of(error, struct drm_i915_private, gpu_error);
2418
	struct drm_device *dev = dev_priv->dev;
2419 2420 2421
	char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
	char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
	char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2422
	int ret;
2423

2424
	kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2425

2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436
	/*
	 * Note that there's only one work item which does gpu resets, so we
	 * need not worry about concurrent gpu resets potentially incrementing
	 * error->reset_counter twice. We only need to take care of another
	 * racing irq/hangcheck declaring the gpu dead for a second time. A
	 * quick check for that is good enough: schedule_work ensures the
	 * correct ordering between hang detection and this work item, and since
	 * the reset in-progress bit is only ever set by code outside of this
	 * work we don't need to worry about any other races.
	 */
	if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2437
		DRM_DEBUG_DRIVER("resetting chip\n");
2438
		kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2439
				   reset_event);
2440

2441 2442 2443 2444 2445 2446 2447 2448
		/*
		 * In most cases it's guaranteed that we get here with an RPM
		 * reference held, for example because there is a pending GPU
		 * request that won't finish until the reset is done. This
		 * isn't the case at least when we get here by doing a
		 * simulated reset via debugs, so get an RPM reference.
		 */
		intel_runtime_pm_get(dev_priv);
2449 2450 2451

		intel_prepare_reset(dev);

2452 2453 2454 2455 2456 2457
		/*
		 * All state reset _must_ be completed before we update the
		 * reset counter, for otherwise waiters might miss the reset
		 * pending state and not properly drop locks, resulting in
		 * deadlocks with the reset work.
		 */
2458 2459
		ret = i915_reset(dev);

2460
		intel_finish_reset(dev);
2461

2462 2463
		intel_runtime_pm_put(dev_priv);

2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474
		if (ret == 0) {
			/*
			 * After all the gem state is reset, increment the reset
			 * counter and wake up everyone waiting for the reset to
			 * complete.
			 *
			 * Since unlock operations are a one-sided barrier only,
			 * we need to insert a barrier here to order any seqno
			 * updates before
			 * the counter increment.
			 */
2475
			smp_mb__before_atomic();
2476 2477
			atomic_inc(&dev_priv->gpu_error.reset_counter);

2478
			kobject_uevent_env(&dev->primary->kdev->kobj,
2479
					   KOBJ_CHANGE, reset_done_event);
2480
		} else {
M
Mika Kuoppala 已提交
2481
			atomic_set_mask(I915_WEDGED, &error->reset_counter);
2482
		}
2483

2484 2485 2486 2487 2488
		/*
		 * Note: The wake_up also serves as a memory barrier so that
		 * waiters see the update value of the reset counter atomic_t.
		 */
		i915_error_wake_up(dev_priv, true);
2489
	}
2490 2491
}

2492
static void i915_report_and_clear_eir(struct drm_device *dev)
2493 2494
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2495
	uint32_t instdone[I915_NUM_INSTDONE_REG];
2496
	u32 eir = I915_READ(EIR);
2497
	int pipe, i;
2498

2499 2500
	if (!eir)
		return;
2501

2502
	pr_err("render error detected, EIR: 0x%08x\n", eir);
2503

2504 2505
	i915_get_extra_instdone(dev, instdone);

2506 2507 2508 2509
	if (IS_G4X(dev)) {
		if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
			u32 ipeir = I915_READ(IPEIR_I965);

2510 2511
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2512 2513
			for (i = 0; i < ARRAY_SIZE(instdone); i++)
				pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2514 2515
			pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2516
			I915_WRITE(IPEIR_I965, ipeir);
2517
			POSTING_READ(IPEIR_I965);
2518 2519 2520
		}
		if (eir & GM45_ERROR_PAGE_TABLE) {
			u32 pgtbl_err = I915_READ(PGTBL_ER);
2521 2522
			pr_err("page table error\n");
			pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2523
			I915_WRITE(PGTBL_ER, pgtbl_err);
2524
			POSTING_READ(PGTBL_ER);
2525 2526 2527
		}
	}

2528
	if (!IS_GEN2(dev)) {
2529 2530
		if (eir & I915_ERROR_PAGE_TABLE) {
			u32 pgtbl_err = I915_READ(PGTBL_ER);
2531 2532
			pr_err("page table error\n");
			pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2533
			I915_WRITE(PGTBL_ER, pgtbl_err);
2534
			POSTING_READ(PGTBL_ER);
2535 2536 2537 2538
		}
	}

	if (eir & I915_ERROR_MEMORY_REFRESH) {
2539
		pr_err("memory refresh error:\n");
2540
		for_each_pipe(dev_priv, pipe)
2541
			pr_err("pipe %c stat: 0x%08x\n",
2542
			       pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2543 2544 2545
		/* pipestat has already been acked */
	}
	if (eir & I915_ERROR_INSTRUCTION) {
2546 2547
		pr_err("instruction error\n");
		pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
2548 2549
		for (i = 0; i < ARRAY_SIZE(instdone); i++)
			pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2550
		if (INTEL_INFO(dev)->gen < 4) {
2551 2552
			u32 ipeir = I915_READ(IPEIR);

2553 2554 2555
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
2556
			I915_WRITE(IPEIR, ipeir);
2557
			POSTING_READ(IPEIR);
2558 2559 2560
		} else {
			u32 ipeir = I915_READ(IPEIR_I965);

2561 2562 2563 2564
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
			pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2565
			I915_WRITE(IPEIR_I965, ipeir);
2566
			POSTING_READ(IPEIR_I965);
2567 2568 2569 2570
		}
	}

	I915_WRITE(EIR, eir);
2571
	POSTING_READ(EIR);
2572 2573 2574 2575 2576 2577 2578 2579 2580 2581
	eir = I915_READ(EIR);
	if (eir) {
		/*
		 * some errors might have become stuck,
		 * mask them.
		 */
		DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
		I915_WRITE(EMR, I915_READ(EMR) | eir);
		I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
	}
2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593
}

/**
 * i915_handle_error - handle an error interrupt
 * @dev: drm device
 *
 * Do some basic checking of regsiter state at error interrupt time and
 * dump it to the syslog.  Also call i915_capture_error_state() to make
 * sure we get a record and make it available in debugfs.  Fire a uevent
 * so userspace knows something bad happened (should trigger collection
 * of a ring dump etc.).
 */
2594 2595
void i915_handle_error(struct drm_device *dev, bool wedged,
		       const char *fmt, ...)
2596 2597
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2598 2599
	va_list args;
	char error_msg[80];
2600

2601 2602 2603 2604 2605
	va_start(args, fmt);
	vscnprintf(error_msg, sizeof(error_msg), fmt, args);
	va_end(args);

	i915_capture_error_state(dev, wedged, error_msg);
2606
	i915_report_and_clear_eir(dev);
2607

2608
	if (wedged) {
2609 2610
		atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
				&dev_priv->gpu_error.reset_counter);
2611

2612
		/*
2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623
		 * Wakeup waiting processes so that the reset work function
		 * i915_error_work_func doesn't deadlock trying to grab various
		 * locks. By bumping the reset counter first, the woken
		 * processes will see a reset in progress and back off,
		 * releasing their locks and then wait for the reset completion.
		 * We must do this for _all_ gpu waiters that might hold locks
		 * that the reset work needs to acquire.
		 *
		 * Note: The wake_up serves as the required memory barrier to
		 * ensure that the waiters see the updated value of the reset
		 * counter atomic_t.
2624
		 */
2625
		i915_error_wake_up(dev_priv, false);
2626 2627
	}

2628 2629 2630 2631 2632 2633 2634
	/*
	 * Our reset work can grab modeset locks (since it needs to reset the
	 * state of outstanding pagelips). Hence it must not be run on our own
	 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
	 * code will deadlock.
	 */
	schedule_work(&dev_priv->gpu_error.work);
2635 2636
}

2637 2638 2639
/* Called from drm generic code, passed 'crtc' which
 * we use as a pipe index
 */
2640
static int i915_enable_vblank(struct drm_device *dev, int pipe)
2641
{
2642
	struct drm_i915_private *dev_priv = dev->dev_private;
2643
	unsigned long irqflags;
2644

2645
	if (!i915_pipe_enabled(dev, pipe))
2646
		return -EINVAL;
2647

2648
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2649
	if (INTEL_INFO(dev)->gen >= 4)
2650
		i915_enable_pipestat(dev_priv, pipe,
2651
				     PIPE_START_VBLANK_INTERRUPT_STATUS);
2652
	else
2653
		i915_enable_pipestat(dev_priv, pipe,
2654
				     PIPE_VBLANK_INTERRUPT_STATUS);
2655
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2656

2657 2658 2659
	return 0;
}

2660
static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2661
{
2662
	struct drm_i915_private *dev_priv = dev->dev_private;
2663
	unsigned long irqflags;
2664
	uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2665
						     DE_PIPE_VBLANK(pipe);
2666 2667 2668 2669 2670

	if (!i915_pipe_enabled(dev, pipe))
		return -EINVAL;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2671
	ironlake_enable_display_irq(dev_priv, bit);
2672 2673 2674 2675 2676
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

	return 0;
}

J
Jesse Barnes 已提交
2677 2678
static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
{
2679
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
2680 2681 2682 2683 2684 2685
	unsigned long irqflags;

	if (!i915_pipe_enabled(dev, pipe))
		return -EINVAL;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2686
	i915_enable_pipestat(dev_priv, pipe,
2687
			     PIPE_START_VBLANK_INTERRUPT_STATUS);
J
Jesse Barnes 已提交
2688 2689 2690 2691 2692
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

	return 0;
}

2693 2694 2695 2696 2697 2698 2699 2700 2701
static int gen8_enable_vblank(struct drm_device *dev, int pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long irqflags;

	if (!i915_pipe_enabled(dev, pipe))
		return -EINVAL;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2702 2703 2704
	dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
	I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
	POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2705 2706 2707 2708
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
	return 0;
}

2709 2710 2711
/* Called from drm generic code, passed 'crtc' which
 * we use as a pipe index
 */
2712
static void i915_disable_vblank(struct drm_device *dev, int pipe)
2713
{
2714
	struct drm_i915_private *dev_priv = dev->dev_private;
2715
	unsigned long irqflags;
2716

2717
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2718
	i915_disable_pipestat(dev_priv, pipe,
2719 2720
			      PIPE_VBLANK_INTERRUPT_STATUS |
			      PIPE_START_VBLANK_INTERRUPT_STATUS);
2721 2722 2723
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

2724
static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2725
{
2726
	struct drm_i915_private *dev_priv = dev->dev_private;
2727
	unsigned long irqflags;
2728
	uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2729
						     DE_PIPE_VBLANK(pipe);
2730 2731

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2732
	ironlake_disable_display_irq(dev_priv, bit);
2733 2734 2735
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

J
Jesse Barnes 已提交
2736 2737
static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
{
2738
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
2739 2740 2741
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2742
	i915_disable_pipestat(dev_priv, pipe,
2743
			      PIPE_START_VBLANK_INTERRUPT_STATUS);
J
Jesse Barnes 已提交
2744 2745 2746
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

2747 2748 2749 2750 2751 2752 2753 2754 2755
static void gen8_disable_vblank(struct drm_device *dev, int pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long irqflags;

	if (!i915_pipe_enabled(dev, pipe))
		return;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2756 2757 2758
	dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
	I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
	POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2759 2760 2761
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

2762 2763
static struct drm_i915_gem_request *
ring_last_request(struct intel_engine_cs *ring)
2764
{
2765
	return list_entry(ring->request_list.prev,
2766
			  struct drm_i915_gem_request, list);
2767 2768
}

2769
static bool
2770
ring_idle(struct intel_engine_cs *ring)
2771 2772
{
	return (list_empty(&ring->request_list) ||
2773
		i915_gem_request_completed(ring_last_request(ring), false));
B
Ben Gamari 已提交
2774 2775
}

2776 2777 2778 2779
static bool
ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
{
	if (INTEL_INFO(dev)->gen >= 8) {
2780
		return (ipehr >> 23) == 0x1c;
2781 2782 2783 2784 2785 2786 2787
	} else {
		ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
		return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
				 MI_SEMAPHORE_REGISTER);
	}
}

2788
static struct intel_engine_cs *
2789
semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset)
2790 2791
{
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
2792
	struct intel_engine_cs *signaller;
2793 2794 2795
	int i;

	if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
2796 2797 2798 2799 2800 2801 2802
		for_each_ring(signaller, dev_priv, i) {
			if (ring == signaller)
				continue;

			if (offset == signaller->semaphore.signal_ggtt[ring->id])
				return signaller;
		}
2803 2804 2805 2806 2807 2808 2809
	} else {
		u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;

		for_each_ring(signaller, dev_priv, i) {
			if(ring == signaller)
				continue;

2810
			if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
2811 2812 2813 2814
				return signaller;
		}
	}

2815 2816
	DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
		  ring->id, ipehr, offset);
2817 2818 2819 2820

	return NULL;
}

2821 2822
static struct intel_engine_cs *
semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
2823 2824
{
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
2825
	u32 cmd, ipehr, head;
2826 2827
	u64 offset = 0;
	int i, backwards;
2828 2829

	ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2830
	if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
2831
		return NULL;
2832

2833 2834 2835
	/*
	 * HEAD is likely pointing to the dword after the actual command,
	 * so scan backwards until we find the MBOX. But limit it to just 3
2836 2837
	 * or 4 dwords depending on the semaphore wait command size.
	 * Note that we don't care about ACTHD here since that might
2838 2839
	 * point at at batch, and semaphores are always emitted into the
	 * ringbuffer itself.
2840
	 */
2841
	head = I915_READ_HEAD(ring) & HEAD_ADDR;
2842
	backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4;
2843

2844
	for (i = backwards; i; --i) {
2845 2846 2847 2848 2849
		/*
		 * Be paranoid and presume the hw has gone off into the wild -
		 * our ring is smaller than what the hardware (and hence
		 * HEAD_ADDR) allows. Also handles wrap-around.
		 */
2850
		head &= ring->buffer->size - 1;
2851 2852

		/* This here seems to blow up */
2853
		cmd = ioread32(ring->buffer->virtual_start + head);
2854 2855 2856
		if (cmd == ipehr)
			break;

2857 2858
		head -= 4;
	}
2859

2860 2861
	if (!i)
		return NULL;
2862

2863
	*seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
2864 2865 2866 2867 2868 2869
	if (INTEL_INFO(ring->dev)->gen >= 8) {
		offset = ioread32(ring->buffer->virtual_start + head + 12);
		offset <<= 32;
		offset = ioread32(ring->buffer->virtual_start + head + 8);
	}
	return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
2870 2871
}

2872
static int semaphore_passed(struct intel_engine_cs *ring)
2873 2874
{
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
2875
	struct intel_engine_cs *signaller;
2876
	u32 seqno;
2877

2878
	ring->hangcheck.deadlock++;
2879 2880

	signaller = semaphore_waits_for(ring, &seqno);
2881 2882 2883 2884 2885
	if (signaller == NULL)
		return -1;

	/* Prevent pathological recursion due to driver bugs */
	if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
2886 2887
		return -1;

2888 2889 2890
	if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
		return 1;

2891 2892 2893
	/* cursory check for an unkickable deadlock */
	if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
	    semaphore_passed(signaller) < 0)
2894 2895 2896
		return -1;

	return 0;
2897 2898 2899 2900
}

static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
{
2901
	struct intel_engine_cs *ring;
2902 2903 2904
	int i;

	for_each_ring(ring, dev_priv, i)
2905
		ring->hangcheck.deadlock = 0;
2906 2907
}

2908
static enum intel_ring_hangcheck_action
2909
ring_stuck(struct intel_engine_cs *ring, u64 acthd)
2910 2911 2912
{
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2913 2914
	u32 tmp;

2915 2916 2917 2918 2919 2920 2921 2922
	if (acthd != ring->hangcheck.acthd) {
		if (acthd > ring->hangcheck.max_acthd) {
			ring->hangcheck.max_acthd = acthd;
			return HANGCHECK_ACTIVE;
		}

		return HANGCHECK_ACTIVE_LOOP;
	}
2923

2924
	if (IS_GEN2(dev))
2925
		return HANGCHECK_HUNG;
2926 2927 2928 2929 2930 2931 2932

	/* Is the chip hanging on a WAIT_FOR_EVENT?
	 * If so we can simply poke the RB_WAIT bit
	 * and break the hang. This should work on
	 * all but the second generation chipsets.
	 */
	tmp = I915_READ_CTL(ring);
2933
	if (tmp & RING_WAIT) {
2934 2935 2936
		i915_handle_error(dev, false,
				  "Kicking stuck wait on %s",
				  ring->name);
2937
		I915_WRITE_CTL(ring, tmp);
2938
		return HANGCHECK_KICK;
2939 2940 2941 2942 2943
	}

	if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
		switch (semaphore_passed(ring)) {
		default:
2944
			return HANGCHECK_HUNG;
2945
		case 1:
2946 2947 2948
			i915_handle_error(dev, false,
					  "Kicking stuck semaphore on %s",
					  ring->name);
2949
			I915_WRITE_CTL(ring, tmp);
2950
			return HANGCHECK_KICK;
2951
		case 0:
2952
			return HANGCHECK_WAIT;
2953
		}
2954
	}
2955

2956
	return HANGCHECK_HUNG;
2957 2958
}

B
Ben Gamari 已提交
2959 2960
/**
 * This is called when the chip hasn't reported back with completed
2961 2962 2963 2964 2965
 * batchbuffers in a long time. We keep track per ring seqno progress and
 * if there are no progress, hangcheck score for that ring is increased.
 * Further, acthd is inspected to see if the ring is stuck. On stuck case
 * we kick the ring. If we see no progress on three subsequent calls
 * we assume chip is wedged and try to fix it by resetting the chip.
B
Ben Gamari 已提交
2966
 */
2967
static void i915_hangcheck_elapsed(unsigned long data)
B
Ben Gamari 已提交
2968 2969
{
	struct drm_device *dev = (struct drm_device *)data;
2970
	struct drm_i915_private *dev_priv = dev->dev_private;
2971
	struct intel_engine_cs *ring;
2972
	int i;
2973
	int busy_count = 0, rings_hung = 0;
2974 2975 2976 2977
	bool stuck[I915_NUM_RINGS] = { 0 };
#define BUSY 1
#define KICK 5
#define HUNG 20
2978

2979
	if (!i915.enable_hangcheck)
2980 2981
		return;

2982
	for_each_ring(ring, dev_priv, i) {
2983 2984
		u64 acthd;
		u32 seqno;
2985
		bool busy = true;
2986

2987 2988
		semaphore_clear_deadlocks(dev_priv);

2989 2990
		seqno = ring->get_seqno(ring, false);
		acthd = intel_ring_get_active_head(ring);
2991

2992
		if (ring->hangcheck.seqno == seqno) {
2993
			if (ring_idle(ring)) {
2994 2995
				ring->hangcheck.action = HANGCHECK_IDLE;

2996 2997
				if (waitqueue_active(&ring->irq_queue)) {
					/* Issue a wake-up to catch stuck h/w. */
2998
					if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2999 3000 3001 3002 3003 3004
						if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
							DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
								  ring->name);
						else
							DRM_INFO("Fake missed irq on %s\n",
								 ring->name);
3005 3006 3007 3008
						wake_up_all(&ring->irq_queue);
					}
					/* Safeguard against driver failure */
					ring->hangcheck.score += BUSY;
3009 3010
				} else
					busy = false;
3011
			} else {
3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025 3026
				/* We always increment the hangcheck score
				 * if the ring is busy and still processing
				 * the same request, so that no single request
				 * can run indefinitely (such as a chain of
				 * batches). The only time we do not increment
				 * the hangcheck score on this ring, if this
				 * ring is in a legitimate wait for another
				 * ring. In that case the waiting ring is a
				 * victim and we want to be sure we catch the
				 * right culprit. Then every time we do kick
				 * the ring, add a small increment to the
				 * score so that we can catch a batch that is
				 * being repeatedly kicked and so responsible
				 * for stalling the machine.
				 */
3027 3028 3029 3030
				ring->hangcheck.action = ring_stuck(ring,
								    acthd);

				switch (ring->hangcheck.action) {
3031
				case HANGCHECK_IDLE:
3032 3033
				case HANGCHECK_WAIT:
				case HANGCHECK_ACTIVE:
3034 3035
					break;
				case HANGCHECK_ACTIVE_LOOP:
3036
					ring->hangcheck.score += BUSY;
3037
					break;
3038
				case HANGCHECK_KICK:
3039
					ring->hangcheck.score += KICK;
3040
					break;
3041
				case HANGCHECK_HUNG:
3042
					ring->hangcheck.score += HUNG;
3043 3044 3045
					stuck[i] = true;
					break;
				}
3046
			}
3047
		} else {
3048 3049
			ring->hangcheck.action = HANGCHECK_ACTIVE;

3050 3051 3052 3053 3054
			/* Gradually reduce the count so that we catch DoS
			 * attempts across multiple batches.
			 */
			if (ring->hangcheck.score > 0)
				ring->hangcheck.score--;
3055 3056

			ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0;
3057 3058
		}

3059 3060
		ring->hangcheck.seqno = seqno;
		ring->hangcheck.acthd = acthd;
3061
		busy_count += busy;
3062
	}
3063

3064
	for_each_ring(ring, dev_priv, i) {
3065
		if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3066 3067 3068
			DRM_INFO("%s on %s\n",
				 stuck[i] ? "stuck" : "no progress",
				 ring->name);
3069
			rings_hung++;
3070 3071 3072
		}
	}

3073
	if (rings_hung)
3074
		return i915_handle_error(dev, true, "Ring hung");
B
Ben Gamari 已提交
3075

3076 3077 3078
	if (busy_count)
		/* Reset timer case chip hangs without another request
		 * being added */
3079 3080 3081 3082 3083 3084
		i915_queue_hangcheck(dev);
}

void i915_queue_hangcheck(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
3085 3086
	struct timer_list *timer = &dev_priv->gpu_error.hangcheck_timer;

3087
	if (!i915.enable_hangcheck)
3088 3089
		return;

3090
	/* Don't continually defer the hangcheck, but make sure it is active */
3091 3092 3093 3094
	if (timer_pending(timer))
		return;
	mod_timer(timer,
		  round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
B
Ben Gamari 已提交
3095 3096
}

3097
static void ibx_irq_reset(struct drm_device *dev)
P
Paulo Zanoni 已提交
3098 3099 3100 3101 3102 3103
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (HAS_PCH_NOP(dev))
		return;

3104
	GEN5_IRQ_RESET(SDE);
3105 3106 3107

	if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
		I915_WRITE(SERR_INT, 0xffffffff);
P
Paulo Zanoni 已提交
3108
}
3109

P
Paulo Zanoni 已提交
3110 3111 3112 3113 3114 3115 3116 3117 3118 3119 3120 3121 3122 3123 3124 3125
/*
 * SDEIER is also touched by the interrupt handler to work around missed PCH
 * interrupts. Hence we can't update it after the interrupt handler is enabled -
 * instead we unconditionally enable all PCH interrupt sources here, but then
 * only unmask them as needed with SDEIMR.
 *
 * This function needs to be called before interrupts are enabled.
 */
static void ibx_irq_pre_postinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (HAS_PCH_NOP(dev))
		return;

	WARN_ON(I915_READ(SDEIER) != 0);
P
Paulo Zanoni 已提交
3126 3127 3128 3129
	I915_WRITE(SDEIER, 0xffffffff);
	POSTING_READ(SDEIER);
}

3130
static void gen5_gt_irq_reset(struct drm_device *dev)
3131 3132 3133
{
	struct drm_i915_private *dev_priv = dev->dev_private;

3134
	GEN5_IRQ_RESET(GT);
P
Paulo Zanoni 已提交
3135
	if (INTEL_INFO(dev)->gen >= 6)
3136
		GEN5_IRQ_RESET(GEN6_PM);
3137 3138
}

L
Linus Torvalds 已提交
3139 3140
/* drm_dma.h hooks
*/
P
Paulo Zanoni 已提交
3141
static void ironlake_irq_reset(struct drm_device *dev)
3142
{
3143
	struct drm_i915_private *dev_priv = dev->dev_private;
3144

3145
	I915_WRITE(HWSTAM, 0xffffffff);
3146

3147
	GEN5_IRQ_RESET(DE);
3148 3149
	if (IS_GEN7(dev))
		I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3150

3151
	gen5_gt_irq_reset(dev);
3152

3153
	ibx_irq_reset(dev);
3154
}
3155

3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167 3168
static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
{
	enum pipe pipe;

	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));

	for_each_pipe(dev_priv, pipe)
		I915_WRITE(PIPESTAT(pipe), 0xffff);

	GEN5_IRQ_RESET(VLV_);
}

J
Jesse Barnes 已提交
3169 3170
static void valleyview_irq_preinstall(struct drm_device *dev)
{
3171
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
3172 3173 3174 3175 3176 3177 3178

	/* VLV magic */
	I915_WRITE(VLV_IMR, 0);
	I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
	I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
	I915_WRITE(RING_IMR(BLT_RING_BASE), 0);

3179
	gen5_gt_irq_reset(dev);
J
Jesse Barnes 已提交
3180

3181
	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
J
Jesse Barnes 已提交
3182

3183
	vlv_display_irq_reset(dev_priv);
J
Jesse Barnes 已提交
3184 3185
}

3186 3187 3188 3189 3190 3191 3192 3193
static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
{
	GEN8_IRQ_RESET_NDX(GT, 0);
	GEN8_IRQ_RESET_NDX(GT, 1);
	GEN8_IRQ_RESET_NDX(GT, 2);
	GEN8_IRQ_RESET_NDX(GT, 3);
}

P
Paulo Zanoni 已提交
3194
static void gen8_irq_reset(struct drm_device *dev)
3195 3196 3197 3198 3199 3200 3201
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int pipe;

	I915_WRITE(GEN8_MASTER_IRQ, 0);
	POSTING_READ(GEN8_MASTER_IRQ);

3202
	gen8_gt_irq_reset(dev_priv);
3203

3204
	for_each_pipe(dev_priv, pipe)
3205 3206
		if (intel_display_power_is_enabled(dev_priv,
						   POWER_DOMAIN_PIPE(pipe)))
3207
			GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3208

3209 3210 3211
	GEN5_IRQ_RESET(GEN8_DE_PORT_);
	GEN5_IRQ_RESET(GEN8_DE_MISC_);
	GEN5_IRQ_RESET(GEN8_PCU_);
3212

3213
	ibx_irq_reset(dev);
3214
}
3215

3216 3217
void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv)
{
3218
	uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3219

3220
	spin_lock_irq(&dev_priv->irq_lock);
3221
	GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B],
3222
			  ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
3223
	GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C],
3224
			  ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
3225
	spin_unlock_irq(&dev_priv->irq_lock);
3226 3227
}

3228 3229 3230 3231 3232 3233 3234
static void cherryview_irq_preinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	I915_WRITE(GEN8_MASTER_IRQ, 0);
	POSTING_READ(GEN8_MASTER_IRQ);

3235
	gen8_gt_irq_reset(dev_priv);
3236 3237 3238 3239 3240

	GEN5_IRQ_RESET(GEN8_PCU_);

	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);

3241
	vlv_display_irq_reset(dev_priv);
3242 3243
}

3244
static void ibx_hpd_irq_setup(struct drm_device *dev)
3245
{
3246
	struct drm_i915_private *dev_priv = dev->dev_private;
3247
	struct intel_encoder *intel_encoder;
3248
	u32 hotplug_irqs, hotplug, enabled_irqs = 0;
3249 3250

	if (HAS_PCH_IBX(dev)) {
3251
		hotplug_irqs = SDE_HOTPLUG_MASK;
3252
		for_each_intel_encoder(dev, intel_encoder)
3253
			if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3254
				enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
3255
	} else {
3256
		hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3257
		for_each_intel_encoder(dev, intel_encoder)
3258
			if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3259
				enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
3260
	}
3261

3262
	ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3263 3264 3265 3266 3267 3268 3269

	/*
	 * Enable digital hotplug on the PCH, and configure the DP short pulse
	 * duration to 2ms (which is the minimum in the Display Port spec)
	 *
	 * This register is the same on all known PCH chips.
	 */
3270 3271 3272 3273 3274 3275 3276 3277
	hotplug = I915_READ(PCH_PORT_HOTPLUG);
	hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
	hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
	hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
	hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
}

P
Paulo Zanoni 已提交
3278 3279
static void ibx_irq_postinstall(struct drm_device *dev)
{
3280
	struct drm_i915_private *dev_priv = dev->dev_private;
3281
	u32 mask;
3282

D
Daniel Vetter 已提交
3283 3284 3285
	if (HAS_PCH_NOP(dev))
		return;

3286
	if (HAS_PCH_IBX(dev))
3287
		mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3288
	else
3289
		mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3290

3291
	GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
P
Paulo Zanoni 已提交
3292 3293 3294
	I915_WRITE(SDEIMR, ~mask);
}

3295 3296 3297 3298 3299 3300 3301 3302
static void gen5_gt_irq_postinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pm_irqs, gt_irqs;

	pm_irqs = gt_irqs = 0;

	dev_priv->gt_irq_mask = ~0;
3303
	if (HAS_L3_DPF(dev)) {
3304
		/* L3 parity interrupt is always unmasked. */
3305 3306
		dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
		gt_irqs |= GT_PARITY_ERROR(dev);
3307 3308 3309 3310 3311 3312 3313 3314 3315 3316
	}

	gt_irqs |= GT_RENDER_USER_INTERRUPT;
	if (IS_GEN5(dev)) {
		gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
			   ILK_BSD_USER_INTERRUPT;
	} else {
		gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
	}

P
Paulo Zanoni 已提交
3317
	GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3318 3319

	if (INTEL_INFO(dev)->gen >= 6) {
3320 3321 3322 3323
		/*
		 * RPS interrupts will get enabled/disabled on demand when RPS
		 * itself is enabled/disabled.
		 */
3324 3325 3326
		if (HAS_VEBOX(dev))
			pm_irqs |= PM_VEBOX_USER_INTERRUPT;

3327
		dev_priv->pm_irq_mask = 0xffffffff;
P
Paulo Zanoni 已提交
3328
		GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3329 3330 3331
	}
}

3332
static int ironlake_irq_postinstall(struct drm_device *dev)
3333
{
3334
	struct drm_i915_private *dev_priv = dev->dev_private;
3335 3336 3337 3338 3339 3340
	u32 display_mask, extra_mask;

	if (INTEL_INFO(dev)->gen >= 7) {
		display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
				DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
				DE_PLANEB_FLIP_DONE_IVB |
3341
				DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3342
		extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3343
			      DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
3344 3345 3346
	} else {
		display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
				DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3347 3348 3349
				DE_AUX_CHANNEL_A |
				DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
				DE_POISON);
3350 3351
		extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
				DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
3352
	}
3353

3354
	dev_priv->irq_mask = ~display_mask;
3355

3356 3357
	I915_WRITE(HWSTAM, 0xeffe);

P
Paulo Zanoni 已提交
3358 3359
	ibx_irq_pre_postinstall(dev);

P
Paulo Zanoni 已提交
3360
	GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3361

3362
	gen5_gt_irq_postinstall(dev);
3363

P
Paulo Zanoni 已提交
3364
	ibx_irq_postinstall(dev);
3365

3366
	if (IS_IRONLAKE_M(dev)) {
3367 3368 3369
		/* Enable PCU event interrupts
		 *
		 * spinlocking not required here for correctness since interrupt
3370 3371
		 * setup is guaranteed to run in single-threaded context. But we
		 * need it to make the assert_spin_locked happy. */
3372
		spin_lock_irq(&dev_priv->irq_lock);
3373
		ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
3374
		spin_unlock_irq(&dev_priv->irq_lock);
3375 3376
	}

3377 3378 3379
	return 0;
}

3380 3381 3382 3383
static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
{
	u32 pipestat_mask;
	u32 iir_mask;
3384
	enum pipe pipe;
3385 3386 3387 3388

	pipestat_mask = PIPESTAT_INT_STATUS_MASK |
			PIPE_FIFO_UNDERRUN_STATUS;

3389 3390
	for_each_pipe(dev_priv, pipe)
		I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3391 3392 3393 3394 3395
	POSTING_READ(PIPESTAT(PIPE_A));

	pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
			PIPE_CRC_DONE_INTERRUPT_STATUS;

3396 3397 3398
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
	for_each_pipe(dev_priv, pipe)
		      i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3399 3400 3401 3402

	iir_mask = I915_DISPLAY_PORT_INTERRUPT |
		   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3403 3404
	if (IS_CHERRYVIEW(dev_priv))
		iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3405 3406 3407 3408 3409
	dev_priv->irq_mask &= ~iir_mask;

	I915_WRITE(VLV_IIR, iir_mask);
	I915_WRITE(VLV_IIR, iir_mask);
	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3410 3411
	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
	POSTING_READ(VLV_IMR);
3412 3413 3414 3415 3416 3417
}

static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
{
	u32 pipestat_mask;
	u32 iir_mask;
3418
	enum pipe pipe;
3419 3420 3421

	iir_mask = I915_DISPLAY_PORT_INTERRUPT |
		   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3422
		   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3423 3424
	if (IS_CHERRYVIEW(dev_priv))
		iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3425 3426 3427

	dev_priv->irq_mask |= iir_mask;
	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3428
	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3429 3430 3431 3432 3433 3434 3435
	I915_WRITE(VLV_IIR, iir_mask);
	I915_WRITE(VLV_IIR, iir_mask);
	POSTING_READ(VLV_IIR);

	pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
			PIPE_CRC_DONE_INTERRUPT_STATUS;

3436 3437 3438
	i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
	for_each_pipe(dev_priv, pipe)
		i915_disable_pipestat(dev_priv, pipe, pipestat_mask);
3439 3440 3441

	pipestat_mask = PIPESTAT_INT_STATUS_MASK |
			PIPE_FIFO_UNDERRUN_STATUS;
3442 3443 3444

	for_each_pipe(dev_priv, pipe)
		I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3445 3446 3447 3448 3449 3450 3451 3452 3453 3454 3455 3456
	POSTING_READ(PIPESTAT(PIPE_A));
}

void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
{
	assert_spin_locked(&dev_priv->irq_lock);

	if (dev_priv->display_irqs_enabled)
		return;

	dev_priv->display_irqs_enabled = true;

3457
	if (intel_irqs_enabled(dev_priv))
3458 3459 3460 3461 3462 3463 3464 3465 3466 3467 3468 3469
		valleyview_display_irqs_install(dev_priv);
}

void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
{
	assert_spin_locked(&dev_priv->irq_lock);

	if (!dev_priv->display_irqs_enabled)
		return;

	dev_priv->display_irqs_enabled = false;

3470
	if (intel_irqs_enabled(dev_priv))
3471 3472 3473
		valleyview_display_irqs_uninstall(dev_priv);
}

3474
static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
J
Jesse Barnes 已提交
3475
{
3476
	dev_priv->irq_mask = ~0;
J
Jesse Barnes 已提交
3477

3478 3479 3480
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	POSTING_READ(PORT_HOTPLUG_EN);

J
Jesse Barnes 已提交
3481
	I915_WRITE(VLV_IIR, 0xffffffff);
3482 3483 3484 3485
	I915_WRITE(VLV_IIR, 0xffffffff);
	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
	POSTING_READ(VLV_IMR);
J
Jesse Barnes 已提交
3486

3487 3488
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
3489
	spin_lock_irq(&dev_priv->irq_lock);
3490 3491
	if (dev_priv->display_irqs_enabled)
		valleyview_display_irqs_install(dev_priv);
3492
	spin_unlock_irq(&dev_priv->irq_lock);
3493 3494 3495 3496 3497 3498 3499
}

static int valleyview_irq_postinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	vlv_display_irq_postinstall(dev_priv);
J
Jesse Barnes 已提交
3500

3501
	gen5_gt_irq_postinstall(dev);
J
Jesse Barnes 已提交
3502 3503 3504 3505 3506 3507 3508 3509

	/* ack & enable invalid PTE error interrupts */
#if 0 /* FIXME: add support to irq handler for checking these bits */
	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
	I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
#endif

	I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3510 3511 3512 3513

	return 0;
}

3514 3515 3516 3517 3518
static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
{
	/* These are interrupts we'll toggle with the ring mask register */
	uint32_t gt_interrupts[] = {
		GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3519
			GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3520
			GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
3521 3522
			GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
			GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3523
		GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3524 3525 3526
			GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
			GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
			GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3527
		0,
3528 3529
		GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
			GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3530 3531
		};

3532
	dev_priv->pm_irq_mask = 0xffffffff;
3533 3534
	GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
	GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3535 3536 3537 3538 3539
	/*
	 * RPS interrupts will get enabled/disabled on demand when RPS itself
	 * is enabled/disabled.
	 */
	GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
3540
	GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3541 3542 3543 3544
}

static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
{
3545 3546
	uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
	uint32_t de_pipe_enables;
3547
	int pipe;
J
Jesse Barnes 已提交
3548
	u32 aux_en = GEN8_AUX_CHANNEL_A;
3549

J
Jesse Barnes 已提交
3550
	if (IS_GEN9(dev_priv)) {
3551 3552
		de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
				  GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
J
Jesse Barnes 已提交
3553 3554 3555
		aux_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
			GEN9_AUX_CHANNEL_D;
	} else
3556 3557 3558 3559 3560 3561
		de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
				  GEN8_DE_PIPE_IRQ_FAULT_ERRORS;

	de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
					   GEN8_PIPE_FIFO_UNDERRUN;

3562 3563 3564
	dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
	dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
	dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3565

3566
	for_each_pipe(dev_priv, pipe)
3567
		if (intel_display_power_is_enabled(dev_priv,
3568 3569 3570 3571
				POWER_DOMAIN_PIPE(pipe)))
			GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
					  dev_priv->de_irq_mask[pipe],
					  de_pipe_enables);
3572

J
Jesse Barnes 已提交
3573
	GEN5_IRQ_INIT(GEN8_DE_PORT_, ~aux_en, aux_en);
3574 3575 3576 3577 3578 3579
}

static int gen8_irq_postinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

P
Paulo Zanoni 已提交
3580 3581
	ibx_irq_pre_postinstall(dev);

3582 3583 3584 3585 3586 3587 3588 3589 3590 3591 3592
	gen8_gt_irq_postinstall(dev_priv);
	gen8_de_irq_postinstall(dev_priv);

	ibx_irq_postinstall(dev);

	I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
	POSTING_READ(GEN8_MASTER_IRQ);

	return 0;
}

3593 3594 3595 3596
static int cherryview_irq_postinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

3597
	vlv_display_irq_postinstall(dev_priv);
3598 3599 3600 3601 3602 3603 3604 3605 3606

	gen8_gt_irq_postinstall(dev_priv);

	I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
	POSTING_READ(GEN8_MASTER_IRQ);

	return 0;
}

3607 3608 3609 3610 3611 3612 3613
static void gen8_irq_uninstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (!dev_priv)
		return;

P
Paulo Zanoni 已提交
3614
	gen8_irq_reset(dev);
3615 3616
}

3617 3618 3619 3620 3621 3622 3623 3624 3625 3626 3627
static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv)
{
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
	spin_lock_irq(&dev_priv->irq_lock);
	if (dev_priv->display_irqs_enabled)
		valleyview_display_irqs_uninstall(dev_priv);
	spin_unlock_irq(&dev_priv->irq_lock);

	vlv_display_irq_reset(dev_priv);

3628
	dev_priv->irq_mask = ~0;
3629 3630
}

J
Jesse Barnes 已提交
3631 3632
static void valleyview_irq_uninstall(struct drm_device *dev)
{
3633
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
3634 3635 3636 3637

	if (!dev_priv)
		return;

3638 3639
	I915_WRITE(VLV_MASTER_IER, 0);

3640 3641
	gen5_gt_irq_reset(dev);

J
Jesse Barnes 已提交
3642
	I915_WRITE(HWSTAM, 0xffffffff);
3643

3644
	vlv_display_irq_uninstall(dev_priv);
J
Jesse Barnes 已提交
3645 3646
}

3647 3648 3649 3650 3651 3652 3653 3654 3655 3656
static void cherryview_irq_uninstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (!dev_priv)
		return;

	I915_WRITE(GEN8_MASTER_IRQ, 0);
	POSTING_READ(GEN8_MASTER_IRQ);

3657
	gen8_gt_irq_reset(dev_priv);
3658

3659
	GEN5_IRQ_RESET(GEN8_PCU_);
3660

3661
	vlv_display_irq_uninstall(dev_priv);
3662 3663
}

3664
static void ironlake_irq_uninstall(struct drm_device *dev)
3665
{
3666
	struct drm_i915_private *dev_priv = dev->dev_private;
3667 3668 3669 3670

	if (!dev_priv)
		return;

P
Paulo Zanoni 已提交
3671
	ironlake_irq_reset(dev);
3672 3673
}

3674
static void i8xx_irq_preinstall(struct drm_device * dev)
L
Linus Torvalds 已提交
3675
{
3676
	struct drm_i915_private *dev_priv = dev->dev_private;
3677
	int pipe;
3678

3679
	for_each_pipe(dev_priv, pipe)
3680
		I915_WRITE(PIPESTAT(pipe), 0);
3681 3682 3683
	I915_WRITE16(IMR, 0xffff);
	I915_WRITE16(IER, 0x0);
	POSTING_READ16(IER);
C
Chris Wilson 已提交
3684 3685 3686 3687
}

static int i8xx_irq_postinstall(struct drm_device *dev)
{
3688
	struct drm_i915_private *dev_priv = dev->dev_private;
C
Chris Wilson 已提交
3689 3690 3691 3692 3693 3694 3695 3696 3697 3698 3699 3700 3701 3702 3703 3704 3705 3706 3707 3708

	I915_WRITE16(EMR,
		     ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));

	/* Unmask the interrupts that we always want on. */
	dev_priv->irq_mask =
		~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
		  I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
	I915_WRITE16(IMR, dev_priv->irq_mask);

	I915_WRITE16(IER,
		     I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		     I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		     I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
		     I915_USER_INTERRUPT);
	POSTING_READ16(IER);

3709 3710
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
3711
	spin_lock_irq(&dev_priv->irq_lock);
3712 3713
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3714
	spin_unlock_irq(&dev_priv->irq_lock);
3715

C
Chris Wilson 已提交
3716 3717 3718
	return 0;
}

3719 3720 3721 3722
/*
 * Returns true when a page flip has completed.
 */
static bool i8xx_handle_vblank(struct drm_device *dev,
3723
			       int plane, int pipe, u32 iir)
3724
{
3725
	struct drm_i915_private *dev_priv = dev->dev_private;
3726
	u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3727

3728
	if (!intel_pipe_handle_vblank(dev, pipe))
3729 3730 3731
		return false;

	if ((iir & flip_pending) == 0)
3732
		goto check_page_flip;
3733 3734 3735 3736 3737 3738 3739 3740

	/* We detect FlipDone by looking for the change in PendingFlip from '1'
	 * to '0' on the following vblank, i.e. IIR has the Pendingflip
	 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
	 * the flip is completed (no longer pending). Since this doesn't raise
	 * an interrupt per se, we watch for the change at vblank.
	 */
	if (I915_READ16(ISR) & flip_pending)
3741
		goto check_page_flip;
3742

3743
	intel_prepare_page_flip(dev, plane);
3744 3745
	intel_finish_page_flip(dev, pipe);
	return true;
3746 3747 3748 3749

check_page_flip:
	intel_check_page_flip(dev, pipe);
	return false;
3750 3751
}

3752
static irqreturn_t i8xx_irq_handler(int irq, void *arg)
C
Chris Wilson 已提交
3753
{
3754
	struct drm_device *dev = arg;
3755
	struct drm_i915_private *dev_priv = dev->dev_private;
C
Chris Wilson 已提交
3756 3757 3758 3759 3760 3761 3762 3763 3764 3765 3766 3767 3768 3769 3770 3771 3772
	u16 iir, new_iir;
	u32 pipe_stats[2];
	int pipe;
	u16 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;

	iir = I915_READ16(IIR);
	if (iir == 0)
		return IRQ_NONE;

	while (iir & ~flip_mask) {
		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
3773
		spin_lock(&dev_priv->irq_lock);
C
Chris Wilson 已提交
3774
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3775
			DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
C
Chris Wilson 已提交
3776

3777
		for_each_pipe(dev_priv, pipe) {
C
Chris Wilson 已提交
3778 3779 3780 3781 3782 3783
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);

			/*
			 * Clear the PIPE*STAT regs before the IIR
			 */
3784
			if (pipe_stats[pipe] & 0x8000ffff)
C
Chris Wilson 已提交
3785 3786
				I915_WRITE(reg, pipe_stats[pipe]);
		}
3787
		spin_unlock(&dev_priv->irq_lock);
C
Chris Wilson 已提交
3788 3789 3790 3791 3792 3793 3794

		I915_WRITE16(IIR, iir & ~flip_mask);
		new_iir = I915_READ16(IIR); /* Flush posted writes */

		if (iir & I915_USER_INTERRUPT)
			notify_ring(dev, &dev_priv->ring[RCS]);

3795
		for_each_pipe(dev_priv, pipe) {
3796
			int plane = pipe;
3797
			if (HAS_FBC(dev))
3798 3799
				plane = !plane;

3800
			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3801 3802
			    i8xx_handle_vblank(dev, plane, pipe, iir))
				flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
C
Chris Wilson 已提交
3803

3804
			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3805
				i9xx_pipe_crc_irq_handler(dev, pipe);
3806

3807 3808 3809
			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
				intel_cpu_fifo_underrun_irq_handler(dev_priv,
								    pipe);
3810
		}
C
Chris Wilson 已提交
3811 3812 3813 3814 3815 3816 3817 3818 3819

		iir = new_iir;
	}

	return IRQ_HANDLED;
}

static void i8xx_irq_uninstall(struct drm_device * dev)
{
3820
	struct drm_i915_private *dev_priv = dev->dev_private;
C
Chris Wilson 已提交
3821 3822
	int pipe;

3823
	for_each_pipe(dev_priv, pipe) {
C
Chris Wilson 已提交
3824 3825 3826 3827 3828 3829 3830 3831 3832
		/* Clear enable bits; then clear status bits */
		I915_WRITE(PIPESTAT(pipe), 0);
		I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
	}
	I915_WRITE16(IMR, 0xffff);
	I915_WRITE16(IER, 0x0);
	I915_WRITE16(IIR, I915_READ16(IIR));
}

3833 3834
static void i915_irq_preinstall(struct drm_device * dev)
{
3835
	struct drm_i915_private *dev_priv = dev->dev_private;
3836 3837 3838 3839 3840 3841 3842
	int pipe;

	if (I915_HAS_HOTPLUG(dev)) {
		I915_WRITE(PORT_HOTPLUG_EN, 0);
		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	}

3843
	I915_WRITE16(HWSTAM, 0xeffe);
3844
	for_each_pipe(dev_priv, pipe)
3845 3846 3847 3848 3849 3850 3851 3852
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);
	POSTING_READ(IER);
}

static int i915_irq_postinstall(struct drm_device *dev)
{
3853
	struct drm_i915_private *dev_priv = dev->dev_private;
3854
	u32 enable_mask;
3855

3856 3857 3858 3859 3860 3861 3862 3863 3864 3865 3866 3867 3868 3869 3870 3871 3872 3873
	I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));

	/* Unmask the interrupts that we always want on. */
	dev_priv->irq_mask =
		~(I915_ASLE_INTERRUPT |
		  I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
		  I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);

	enable_mask =
		I915_ASLE_INTERRUPT |
		I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
		I915_USER_INTERRUPT;

3874
	if (I915_HAS_HOTPLUG(dev)) {
3875 3876 3877
		I915_WRITE(PORT_HOTPLUG_EN, 0);
		POSTING_READ(PORT_HOTPLUG_EN);

3878 3879 3880 3881 3882 3883 3884 3885 3886 3887
		/* Enable in IER... */
		enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
		/* and unmask in IMR */
		dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
	}

	I915_WRITE(IMR, dev_priv->irq_mask);
	I915_WRITE(IER, enable_mask);
	POSTING_READ(IER);

3888
	i915_enable_asle_pipestat(dev);
3889

3890 3891
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
3892
	spin_lock_irq(&dev_priv->irq_lock);
3893 3894
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3895
	spin_unlock_irq(&dev_priv->irq_lock);
3896

3897 3898 3899
	return 0;
}

3900 3901 3902 3903 3904 3905
/*
 * Returns true when a page flip has completed.
 */
static bool i915_handle_vblank(struct drm_device *dev,
			       int plane, int pipe, u32 iir)
{
3906
	struct drm_i915_private *dev_priv = dev->dev_private;
3907 3908
	u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);

3909
	if (!intel_pipe_handle_vblank(dev, pipe))
3910 3911 3912
		return false;

	if ((iir & flip_pending) == 0)
3913
		goto check_page_flip;
3914 3915 3916 3917 3918 3919 3920 3921

	/* We detect FlipDone by looking for the change in PendingFlip from '1'
	 * to '0' on the following vblank, i.e. IIR has the Pendingflip
	 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
	 * the flip is completed (no longer pending). Since this doesn't raise
	 * an interrupt per se, we watch for the change at vblank.
	 */
	if (I915_READ(ISR) & flip_pending)
3922
		goto check_page_flip;
3923

3924
	intel_prepare_page_flip(dev, plane);
3925 3926
	intel_finish_page_flip(dev, pipe);
	return true;
3927 3928 3929 3930

check_page_flip:
	intel_check_page_flip(dev, pipe);
	return false;
3931 3932
}

3933
static irqreturn_t i915_irq_handler(int irq, void *arg)
3934
{
3935
	struct drm_device *dev = arg;
3936
	struct drm_i915_private *dev_priv = dev->dev_private;
3937
	u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3938 3939 3940 3941
	u32 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
	int pipe, ret = IRQ_NONE;
3942 3943

	iir = I915_READ(IIR);
3944 3945
	do {
		bool irq_received = (iir & ~flip_mask) != 0;
3946
		bool blc_event = false;
3947 3948 3949 3950 3951 3952

		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
3953
		spin_lock(&dev_priv->irq_lock);
3954
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3955
			DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3956

3957
		for_each_pipe(dev_priv, pipe) {
3958 3959 3960
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);

3961
			/* Clear the PIPE*STAT regs before the IIR */
3962 3963
			if (pipe_stats[pipe] & 0x8000ffff) {
				I915_WRITE(reg, pipe_stats[pipe]);
3964
				irq_received = true;
3965 3966
			}
		}
3967
		spin_unlock(&dev_priv->irq_lock);
3968 3969 3970 3971 3972

		if (!irq_received)
			break;

		/* Consume port.  Then clear IIR or we'll miss events */
3973 3974 3975
		if (I915_HAS_HOTPLUG(dev) &&
		    iir & I915_DISPLAY_PORT_INTERRUPT)
			i9xx_hpd_irq_handler(dev);
3976

3977
		I915_WRITE(IIR, iir & ~flip_mask);
3978 3979 3980 3981 3982
		new_iir = I915_READ(IIR); /* Flush posted writes */

		if (iir & I915_USER_INTERRUPT)
			notify_ring(dev, &dev_priv->ring[RCS]);

3983
		for_each_pipe(dev_priv, pipe) {
3984
			int plane = pipe;
3985
			if (HAS_FBC(dev))
3986
				plane = !plane;
3987

3988
			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3989 3990
			    i915_handle_vblank(dev, plane, pipe, iir))
				flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3991 3992 3993

			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
				blc_event = true;
3994 3995

			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3996
				i9xx_pipe_crc_irq_handler(dev, pipe);
3997

3998 3999 4000
			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
				intel_cpu_fifo_underrun_irq_handler(dev_priv,
								    pipe);
4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012 4013 4014 4015 4016 4017 4018 4019 4020
		}

		if (blc_event || (iir & I915_ASLE_INTERRUPT))
			intel_opregion_asle_intr(dev);

		/* With MSI, interrupts are only generated when iir
		 * transitions from zero to nonzero.  If another bit got
		 * set while we were handling the existing iir bits, then
		 * we would never get another interrupt.
		 *
		 * This is fine on non-MSI as well, as if we hit this path
		 * we avoid exiting the interrupt handler only to generate
		 * another one.
		 *
		 * Note that for MSI this could cause a stray interrupt report
		 * if an interrupt landed in the time between writing IIR and
		 * the posting read.  This should be rare enough to never
		 * trigger the 99% of 100,000 interrupts test for disabling
		 * stray interrupts.
		 */
4021
		ret = IRQ_HANDLED;
4022
		iir = new_iir;
4023
	} while (iir & ~flip_mask);
4024 4025 4026 4027 4028 4029

	return ret;
}

static void i915_irq_uninstall(struct drm_device * dev)
{
4030
	struct drm_i915_private *dev_priv = dev->dev_private;
4031 4032 4033 4034 4035 4036 4037
	int pipe;

	if (I915_HAS_HOTPLUG(dev)) {
		I915_WRITE(PORT_HOTPLUG_EN, 0);
		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	}

4038
	I915_WRITE16(HWSTAM, 0xffff);
4039
	for_each_pipe(dev_priv, pipe) {
4040
		/* Clear enable bits; then clear status bits */
4041
		I915_WRITE(PIPESTAT(pipe), 0);
4042 4043
		I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
	}
4044 4045 4046 4047 4048 4049 4050 4051
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);

	I915_WRITE(IIR, I915_READ(IIR));
}

static void i965_irq_preinstall(struct drm_device * dev)
{
4052
	struct drm_i915_private *dev_priv = dev->dev_private;
4053 4054
	int pipe;

4055 4056
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4057 4058

	I915_WRITE(HWSTAM, 0xeffe);
4059
	for_each_pipe(dev_priv, pipe)
4060 4061 4062 4063 4064 4065 4066 4067
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);
	POSTING_READ(IER);
}

static int i965_irq_postinstall(struct drm_device *dev)
{
4068
	struct drm_i915_private *dev_priv = dev->dev_private;
4069
	u32 enable_mask;
4070 4071 4072
	u32 error_mask;

	/* Unmask the interrupts that we always want on. */
4073
	dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4074
			       I915_DISPLAY_PORT_INTERRUPT |
4075 4076 4077 4078 4079 4080 4081
			       I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
			       I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
			       I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
			       I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
			       I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);

	enable_mask = ~dev_priv->irq_mask;
4082 4083
	enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
			 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4084 4085 4086 4087
	enable_mask |= I915_USER_INTERRUPT;

	if (IS_G4X(dev))
		enable_mask |= I915_BSD_USER_INTERRUPT;
4088

4089 4090
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
4091
	spin_lock_irq(&dev_priv->irq_lock);
4092 4093 4094
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4095
	spin_unlock_irq(&dev_priv->irq_lock);
4096 4097 4098 4099 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 4110 4111 4112 4113 4114 4115

	/*
	 * Enable some error detection, note the instruction error mask
	 * bit is reserved, so we leave it masked.
	 */
	if (IS_G4X(dev)) {
		error_mask = ~(GM45_ERROR_PAGE_TABLE |
			       GM45_ERROR_MEM_PRIV |
			       GM45_ERROR_CP_PRIV |
			       I915_ERROR_MEMORY_REFRESH);
	} else {
		error_mask = ~(I915_ERROR_PAGE_TABLE |
			       I915_ERROR_MEMORY_REFRESH);
	}
	I915_WRITE(EMR, error_mask);

	I915_WRITE(IMR, dev_priv->irq_mask);
	I915_WRITE(IER, enable_mask);
	POSTING_READ(IER);

4116 4117 4118
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	POSTING_READ(PORT_HOTPLUG_EN);

4119
	i915_enable_asle_pipestat(dev);
4120 4121 4122 4123

	return 0;
}

4124
static void i915_hpd_irq_setup(struct drm_device *dev)
4125
{
4126
	struct drm_i915_private *dev_priv = dev->dev_private;
4127
	struct intel_encoder *intel_encoder;
4128 4129
	u32 hotplug_en;

4130 4131
	assert_spin_locked(&dev_priv->irq_lock);

4132 4133 4134 4135
	if (I915_HAS_HOTPLUG(dev)) {
		hotplug_en = I915_READ(PORT_HOTPLUG_EN);
		hotplug_en &= ~HOTPLUG_INT_EN_MASK;
		/* Note HDMI and DP share hotplug bits */
4136
		/* enable bits are the same for all generations */
4137
		for_each_intel_encoder(dev, intel_encoder)
4138 4139
			if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
				hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
4140 4141 4142 4143 4144 4145
		/* Programming the CRT detection parameters tends
		   to generate a spurious hotplug event about three
		   seconds later.  So just do it once.
		*/
		if (IS_G4X(dev))
			hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4146
		hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
4147
		hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4148

4149 4150 4151
		/* Ignore TV since it's buggy */
		I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
	}
4152 4153
}

4154
static irqreturn_t i965_irq_handler(int irq, void *arg)
4155
{
4156
	struct drm_device *dev = arg;
4157
	struct drm_i915_private *dev_priv = dev->dev_private;
4158 4159 4160
	u32 iir, new_iir;
	u32 pipe_stats[I915_MAX_PIPES];
	int ret = IRQ_NONE, pipe;
4161 4162 4163
	u32 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4164 4165 4166 4167

	iir = I915_READ(IIR);

	for (;;) {
4168
		bool irq_received = (iir & ~flip_mask) != 0;
4169 4170
		bool blc_event = false;

4171 4172 4173 4174 4175
		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
4176
		spin_lock(&dev_priv->irq_lock);
4177
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4178
			DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4179

4180
		for_each_pipe(dev_priv, pipe) {
4181 4182 4183 4184 4185 4186 4187 4188
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);

			/*
			 * Clear the PIPE*STAT regs before the IIR
			 */
			if (pipe_stats[pipe] & 0x8000ffff) {
				I915_WRITE(reg, pipe_stats[pipe]);
4189
				irq_received = true;
4190 4191
			}
		}
4192
		spin_unlock(&dev_priv->irq_lock);
4193 4194 4195 4196 4197 4198 4199

		if (!irq_received)
			break;

		ret = IRQ_HANDLED;

		/* Consume port.  Then clear IIR or we'll miss events */
4200 4201
		if (iir & I915_DISPLAY_PORT_INTERRUPT)
			i9xx_hpd_irq_handler(dev);
4202

4203
		I915_WRITE(IIR, iir & ~flip_mask);
4204 4205 4206 4207 4208 4209 4210
		new_iir = I915_READ(IIR); /* Flush posted writes */

		if (iir & I915_USER_INTERRUPT)
			notify_ring(dev, &dev_priv->ring[RCS]);
		if (iir & I915_BSD_USER_INTERRUPT)
			notify_ring(dev, &dev_priv->ring[VCS]);

4211
		for_each_pipe(dev_priv, pipe) {
4212
			if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4213 4214
			    i915_handle_vblank(dev, pipe, pipe, iir))
				flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4215 4216 4217

			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
				blc_event = true;
4218 4219

			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4220
				i9xx_pipe_crc_irq_handler(dev, pipe);
4221

4222 4223
			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
				intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4224
		}
4225 4226 4227 4228

		if (blc_event || (iir & I915_ASLE_INTERRUPT))
			intel_opregion_asle_intr(dev);

4229 4230 4231
		if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
			gmbus_irq_handler(dev);

4232 4233 4234 4235 4236 4237 4238 4239 4240 4241 4242 4243 4244 4245 4246 4247 4248 4249 4250 4251 4252 4253 4254
		/* With MSI, interrupts are only generated when iir
		 * transitions from zero to nonzero.  If another bit got
		 * set while we were handling the existing iir bits, then
		 * we would never get another interrupt.
		 *
		 * This is fine on non-MSI as well, as if we hit this path
		 * we avoid exiting the interrupt handler only to generate
		 * another one.
		 *
		 * Note that for MSI this could cause a stray interrupt report
		 * if an interrupt landed in the time between writing IIR and
		 * the posting read.  This should be rare enough to never
		 * trigger the 99% of 100,000 interrupts test for disabling
		 * stray interrupts.
		 */
		iir = new_iir;
	}

	return ret;
}

static void i965_irq_uninstall(struct drm_device * dev)
{
4255
	struct drm_i915_private *dev_priv = dev->dev_private;
4256 4257 4258 4259 4260
	int pipe;

	if (!dev_priv)
		return;

4261 4262
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4263 4264

	I915_WRITE(HWSTAM, 0xffffffff);
4265
	for_each_pipe(dev_priv, pipe)
4266 4267 4268 4269
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);

4270
	for_each_pipe(dev_priv, pipe)
4271 4272 4273 4274 4275
		I915_WRITE(PIPESTAT(pipe),
			   I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
	I915_WRITE(IIR, I915_READ(IIR));
}

4276
static void intel_hpd_irq_reenable_work(struct work_struct *work)
4277
{
4278 4279 4280
	struct drm_i915_private *dev_priv =
		container_of(work, typeof(*dev_priv),
			     hotplug_reenable_work.work);
4281 4282 4283 4284
	struct drm_device *dev = dev_priv->dev;
	struct drm_mode_config *mode_config = &dev->mode_config;
	int i;

4285 4286
	intel_runtime_pm_get(dev_priv);

4287
	spin_lock_irq(&dev_priv->irq_lock);
4288 4289 4290 4291 4292 4293 4294 4295 4296 4297 4298 4299 4300 4301
	for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
		struct drm_connector *connector;

		if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
			continue;

		dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;

		list_for_each_entry(connector, &mode_config->connector_list, head) {
			struct intel_connector *intel_connector = to_intel_connector(connector);

			if (intel_connector->encoder->hpd_pin == i) {
				if (connector->polled != intel_connector->polled)
					DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
4302
							 connector->name);
4303 4304 4305 4306 4307 4308 4309 4310
				connector->polled = intel_connector->polled;
				if (!connector->polled)
					connector->polled = DRM_CONNECTOR_POLL_HPD;
			}
		}
	}
	if (dev_priv->display.hpd_irq_setup)
		dev_priv->display.hpd_irq_setup(dev);
4311
	spin_unlock_irq(&dev_priv->irq_lock);
4312 4313

	intel_runtime_pm_put(dev_priv);
4314 4315
}

4316 4317 4318 4319 4320 4321 4322
/**
 * intel_irq_init - initializes irq support
 * @dev_priv: i915 device instance
 *
 * This function initializes all the irq support including work items, timers
 * and all the vtables. It does not setup the interrupt itself though.
 */
4323
void intel_irq_init(struct drm_i915_private *dev_priv)
4324
{
4325
	struct drm_device *dev = dev_priv->dev;
4326 4327

	INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
4328
	INIT_WORK(&dev_priv->dig_port_work, i915_digport_work_func);
4329
	INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
4330
	INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4331
	INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4332

4333
	/* Let's track the enabled rps events */
4334
	if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
4335
		/* WaGsvRC0ResidencyMethod:vlv */
4336 4337 4338
		dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
	else
		dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4339

4340 4341
	setup_timer(&dev_priv->gpu_error.hangcheck_timer,
		    i915_hangcheck_elapsed,
4342
		    (unsigned long) dev);
4343
	INIT_DELAYED_WORK(&dev_priv->hotplug_reenable_work,
4344
			  intel_hpd_irq_reenable_work);
4345

4346
	pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4347

4348
	if (IS_GEN2(dev_priv)) {
4349 4350
		dev->max_vblank_count = 0;
		dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4351
	} else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4352 4353
		dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
		dev->driver->get_vblank_counter = gm45_get_vblank_counter;
4354 4355 4356
	} else {
		dev->driver->get_vblank_counter = i915_get_vblank_counter;
		dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4357 4358
	}

4359 4360 4361 4362 4363
	/*
	 * Opt out of the vblank disable timer on everything except gen2.
	 * Gen2 doesn't have a hardware frame counter and so depends on
	 * vblank interrupts to produce sane vblank seuquence numbers.
	 */
4364
	if (!IS_GEN2(dev_priv))
4365 4366
		dev->vblank_disable_immediate = true;

4367
	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
4368
		dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4369 4370
		dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
	}
4371

4372
	if (IS_CHERRYVIEW(dev_priv)) {
4373 4374 4375 4376 4377 4378 4379
		dev->driver->irq_handler = cherryview_irq_handler;
		dev->driver->irq_preinstall = cherryview_irq_preinstall;
		dev->driver->irq_postinstall = cherryview_irq_postinstall;
		dev->driver->irq_uninstall = cherryview_irq_uninstall;
		dev->driver->enable_vblank = valleyview_enable_vblank;
		dev->driver->disable_vblank = valleyview_disable_vblank;
		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4380
	} else if (IS_VALLEYVIEW(dev_priv)) {
J
Jesse Barnes 已提交
4381 4382 4383 4384 4385 4386
		dev->driver->irq_handler = valleyview_irq_handler;
		dev->driver->irq_preinstall = valleyview_irq_preinstall;
		dev->driver->irq_postinstall = valleyview_irq_postinstall;
		dev->driver->irq_uninstall = valleyview_irq_uninstall;
		dev->driver->enable_vblank = valleyview_enable_vblank;
		dev->driver->disable_vblank = valleyview_disable_vblank;
4387
		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4388
	} else if (INTEL_INFO(dev_priv)->gen >= 8) {
4389
		dev->driver->irq_handler = gen8_irq_handler;
4390
		dev->driver->irq_preinstall = gen8_irq_reset;
4391 4392 4393 4394 4395
		dev->driver->irq_postinstall = gen8_irq_postinstall;
		dev->driver->irq_uninstall = gen8_irq_uninstall;
		dev->driver->enable_vblank = gen8_enable_vblank;
		dev->driver->disable_vblank = gen8_disable_vblank;
		dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4396 4397
	} else if (HAS_PCH_SPLIT(dev)) {
		dev->driver->irq_handler = ironlake_irq_handler;
4398
		dev->driver->irq_preinstall = ironlake_irq_reset;
4399 4400 4401 4402
		dev->driver->irq_postinstall = ironlake_irq_postinstall;
		dev->driver->irq_uninstall = ironlake_irq_uninstall;
		dev->driver->enable_vblank = ironlake_enable_vblank;
		dev->driver->disable_vblank = ironlake_disable_vblank;
4403
		dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4404
	} else {
4405
		if (INTEL_INFO(dev_priv)->gen == 2) {
C
Chris Wilson 已提交
4406 4407 4408 4409
			dev->driver->irq_preinstall = i8xx_irq_preinstall;
			dev->driver->irq_postinstall = i8xx_irq_postinstall;
			dev->driver->irq_handler = i8xx_irq_handler;
			dev->driver->irq_uninstall = i8xx_irq_uninstall;
4410
		} else if (INTEL_INFO(dev_priv)->gen == 3) {
4411 4412 4413 4414
			dev->driver->irq_preinstall = i915_irq_preinstall;
			dev->driver->irq_postinstall = i915_irq_postinstall;
			dev->driver->irq_uninstall = i915_irq_uninstall;
			dev->driver->irq_handler = i915_irq_handler;
4415
			dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
C
Chris Wilson 已提交
4416
		} else {
4417 4418 4419 4420
			dev->driver->irq_preinstall = i965_irq_preinstall;
			dev->driver->irq_postinstall = i965_irq_postinstall;
			dev->driver->irq_uninstall = i965_irq_uninstall;
			dev->driver->irq_handler = i965_irq_handler;
4421
			dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
C
Chris Wilson 已提交
4422
		}
4423 4424 4425 4426
		dev->driver->enable_vblank = i915_enable_vblank;
		dev->driver->disable_vblank = i915_disable_vblank;
	}
}
4427

4428 4429 4430 4431 4432 4433 4434 4435 4436 4437 4438 4439
/**
 * intel_hpd_init - initializes and enables hpd support
 * @dev_priv: i915 device instance
 *
 * This function enables the hotplug support. It requires that interrupts have
 * already been enabled with intel_irq_init_hw(). From this point on hotplug and
 * poll request can run concurrently to other code, so locking rules must be
 * obeyed.
 *
 * This is a separate step from interrupt enabling to simplify the locking rules
 * in the driver load and resume code.
 */
4440
void intel_hpd_init(struct drm_i915_private *dev_priv)
4441
{
4442
	struct drm_device *dev = dev_priv->dev;
4443 4444 4445
	struct drm_mode_config *mode_config = &dev->mode_config;
	struct drm_connector *connector;
	int i;
4446

4447 4448 4449 4450 4451 4452 4453
	for (i = 1; i < HPD_NUM_PINS; i++) {
		dev_priv->hpd_stats[i].hpd_cnt = 0;
		dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
	}
	list_for_each_entry(connector, &mode_config->connector_list, head) {
		struct intel_connector *intel_connector = to_intel_connector(connector);
		connector->polled = intel_connector->polled;
4454 4455 4456
		if (connector->encoder && !connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
			connector->polled = DRM_CONNECTOR_POLL_HPD;
		if (intel_connector->mst_port)
4457 4458
			connector->polled = DRM_CONNECTOR_POLL_HPD;
	}
4459 4460 4461

	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked checks happy. */
4462
	spin_lock_irq(&dev_priv->irq_lock);
4463 4464
	if (dev_priv->display.hpd_irq_setup)
		dev_priv->display.hpd_irq_setup(dev);
4465
	spin_unlock_irq(&dev_priv->irq_lock);
4466
}
4467

4468 4469 4470 4471 4472 4473 4474 4475 4476 4477 4478
/**
 * intel_irq_install - enables the hardware interrupt
 * @dev_priv: i915 device instance
 *
 * This function enables the hardware interrupt handling, but leaves the hotplug
 * handling still disabled. It is called after intel_irq_init().
 *
 * In the driver load and resume code we need working interrupts in a few places
 * but don't want to deal with the hassle of concurrent probe and hotplug
 * workers. Hence the split into this two-stage approach.
 */
4479 4480 4481 4482 4483 4484 4485 4486 4487 4488 4489 4490
int intel_irq_install(struct drm_i915_private *dev_priv)
{
	/*
	 * We enable some interrupt sources in our postinstall hooks, so mark
	 * interrupts as enabled _before_ actually enabling them to avoid
	 * special cases in our ordering checks.
	 */
	dev_priv->pm.irqs_enabled = true;

	return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
}

4491 4492 4493 4494 4495 4496 4497
/**
 * intel_irq_uninstall - finilizes all irq handling
 * @dev_priv: i915 device instance
 *
 * This stops interrupt and hotplug handling and unregisters and frees all
 * resources acquired in the init functions.
 */
4498 4499 4500 4501 4502 4503 4504
void intel_irq_uninstall(struct drm_i915_private *dev_priv)
{
	drm_irq_uninstall(dev_priv->dev);
	intel_hpd_cancel_work(dev_priv);
	dev_priv->pm.irqs_enabled = false;
}

4505 4506 4507 4508 4509 4510 4511
/**
 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
 * @dev_priv: i915 device instance
 *
 * This function is used to disable interrupts at runtime, both in the runtime
 * pm and the system suspend/resume code.
 */
4512
void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4513
{
4514
	dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
4515
	dev_priv->pm.irqs_enabled = false;
4516 4517
}

4518 4519 4520 4521 4522 4523 4524
/**
 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
 * @dev_priv: i915 device instance
 *
 * This function is used to enable interrupts at runtime, both in the runtime
 * pm and the system suspend/resume code.
 */
4525
void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4526
{
4527
	dev_priv->pm.irqs_enabled = true;
4528 4529
	dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
	dev_priv->dev->driver->irq_postinstall(dev_priv->dev);
4530
}