i915_irq.c 126.8 KB
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/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
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 */
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/*
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

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#include <linux/sysrq.h>
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#include <linux/slab.h>
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#include <linux/circ_buf.h>
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#include <drm/drmP.h>
#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#include "i915_trace.h"
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#include "intel_drv.h"
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/**
 * DOC: interrupt handling
 *
 * These functions provide the basic support for enabling and disabling the
 * interrupt handling support. There's a lot more functionality in i915_irq.c
 * and related files, but that will be described in separate chapters.
 */

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static const u32 hpd_ibx[HPD_NUM_PINS] = {
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	[HPD_CRT] = SDE_CRT_HOTPLUG,
	[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
	[HPD_PORT_B] = SDE_PORTB_HOTPLUG,
	[HPD_PORT_C] = SDE_PORTC_HOTPLUG,
	[HPD_PORT_D] = SDE_PORTD_HOTPLUG
};

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static const u32 hpd_cpt[HPD_NUM_PINS] = {
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	[HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
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	[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
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	[HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
	[HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
	[HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
};

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static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
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	[HPD_CRT] = CRT_HOTPLUG_INT_EN,
	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
	[HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
	[HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
	[HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
};

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static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
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	[HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
	[HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
	[HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
	[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
};

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static const u32 hpd_status_i915[HPD_NUM_PINS] = { /* i915 and valleyview are the same */
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	[HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
	[HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
	[HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
	[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
};

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/* BXT hpd list */
static const u32 hpd_bxt[HPD_NUM_PINS] = {
	[HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
	[HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
};

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/* IIR can theoretically queue up two events. Be paranoid. */
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#define GEN8_IRQ_RESET_NDX(type, which) do { \
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	I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
	POSTING_READ(GEN8_##type##_IMR(which)); \
	I915_WRITE(GEN8_##type##_IER(which), 0); \
	I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
	POSTING_READ(GEN8_##type##_IIR(which)); \
	I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
	POSTING_READ(GEN8_##type##_IIR(which)); \
} while (0)

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#define GEN5_IRQ_RESET(type) do { \
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	I915_WRITE(type##IMR, 0xffffffff); \
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	POSTING_READ(type##IMR); \
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	I915_WRITE(type##IER, 0); \
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	I915_WRITE(type##IIR, 0xffffffff); \
	POSTING_READ(type##IIR); \
	I915_WRITE(type##IIR, 0xffffffff); \
	POSTING_READ(type##IIR); \
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} while (0)

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/*
 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
 */
#define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
	u32 val = I915_READ(reg); \
	if (val) { \
		WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
		     (reg), val); \
		I915_WRITE((reg), 0xffffffff); \
		POSTING_READ(reg); \
		I915_WRITE((reg), 0xffffffff); \
		POSTING_READ(reg); \
	} \
} while (0)

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#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
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	GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
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	I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
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	I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
	POSTING_READ(GEN8_##type##_IMR(which)); \
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} while (0)

#define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
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	GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
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	I915_WRITE(type##IER, (ier_val)); \
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	I915_WRITE(type##IMR, (imr_val)); \
	POSTING_READ(type##IMR); \
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} while (0)

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static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);

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/* For display hotplug interrupt */
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void
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ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
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{
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	assert_spin_locked(&dev_priv->irq_lock);

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	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
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		return;

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	if ((dev_priv->irq_mask & mask) != 0) {
		dev_priv->irq_mask &= ~mask;
		I915_WRITE(DEIMR, dev_priv->irq_mask);
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		POSTING_READ(DEIMR);
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	}
}

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void
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ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
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{
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	assert_spin_locked(&dev_priv->irq_lock);

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	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
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		return;

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	if ((dev_priv->irq_mask & mask) != mask) {
		dev_priv->irq_mask |= mask;
		I915_WRITE(DEIMR, dev_priv->irq_mask);
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		POSTING_READ(DEIMR);
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	}
}

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/**
 * ilk_update_gt_irq - update GTIMR
 * @dev_priv: driver private
 * @interrupt_mask: mask of interrupt bits to update
 * @enabled_irq_mask: mask of interrupt bits to enable
 */
static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
			      uint32_t interrupt_mask,
			      uint32_t enabled_irq_mask)
{
	assert_spin_locked(&dev_priv->irq_lock);

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	WARN_ON(enabled_irq_mask & ~interrupt_mask);

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	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
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		return;

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	dev_priv->gt_irq_mask &= ~interrupt_mask;
	dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
	POSTING_READ(GTIMR);
}

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void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
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{
	ilk_update_gt_irq(dev_priv, mask, mask);
}

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void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
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{
	ilk_update_gt_irq(dev_priv, mask, 0);
}

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static u32 gen6_pm_iir(struct drm_i915_private *dev_priv)
{
	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
}

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static u32 gen6_pm_imr(struct drm_i915_private *dev_priv)
{
	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
}

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static u32 gen6_pm_ier(struct drm_i915_private *dev_priv)
{
	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
}

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/**
  * snb_update_pm_irq - update GEN6_PMIMR
  * @dev_priv: driver private
  * @interrupt_mask: mask of interrupt bits to update
  * @enabled_irq_mask: mask of interrupt bits to enable
  */
static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
			      uint32_t interrupt_mask,
			      uint32_t enabled_irq_mask)
{
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	uint32_t new_val;
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	WARN_ON(enabled_irq_mask & ~interrupt_mask);

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	assert_spin_locked(&dev_priv->irq_lock);

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	new_val = dev_priv->pm_irq_mask;
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	new_val &= ~interrupt_mask;
	new_val |= (~enabled_irq_mask & interrupt_mask);

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	if (new_val != dev_priv->pm_irq_mask) {
		dev_priv->pm_irq_mask = new_val;
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		I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
		POSTING_READ(gen6_pm_imr(dev_priv));
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	}
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}

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void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
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{
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	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
		return;

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	snb_update_pm_irq(dev_priv, mask, mask);
}

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static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
				  uint32_t mask)
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{
	snb_update_pm_irq(dev_priv, mask, 0);
}

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void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
{
	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
		return;

	__gen6_disable_pm_irq(dev_priv, mask);
}

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void gen6_reset_rps_interrupts(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t reg = gen6_pm_iir(dev_priv);

	spin_lock_irq(&dev_priv->irq_lock);
	I915_WRITE(reg, dev_priv->pm_rps_events);
	I915_WRITE(reg, dev_priv->pm_rps_events);
	POSTING_READ(reg);
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	dev_priv->rps.pm_iir = 0;
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	spin_unlock_irq(&dev_priv->irq_lock);
}

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void gen6_enable_rps_interrupts(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	spin_lock_irq(&dev_priv->irq_lock);
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	WARN_ON(dev_priv->rps.pm_iir);
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	WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
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	dev_priv->rps.interrupts_enabled = true;
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	I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
				dev_priv->pm_rps_events);
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	gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
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	spin_unlock_irq(&dev_priv->irq_lock);
}

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u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
{
	/*
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	 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
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	 * if GEN6_PM_UP_EI_EXPIRED is masked.
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	 *
	 * TODO: verify if this can be reproduced on VLV,CHV.
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	 */
	if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
		mask &= ~GEN6_PM_RP_UP_EI_EXPIRED;

	if (INTEL_INFO(dev_priv)->gen >= 8)
		mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;

	return mask;
}

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void gen6_disable_rps_interrupts(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

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	spin_lock_irq(&dev_priv->irq_lock);
	dev_priv->rps.interrupts_enabled = false;
	spin_unlock_irq(&dev_priv->irq_lock);

	cancel_work_sync(&dev_priv->rps.work);

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	spin_lock_irq(&dev_priv->irq_lock);

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	I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0));
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	__gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
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	I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
				~dev_priv->pm_rps_events);
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	spin_unlock_irq(&dev_priv->irq_lock);

	synchronize_irq(dev->irq);
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}

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/**
 * ibx_display_interrupt_update - update SDEIMR
 * @dev_priv: driver private
 * @interrupt_mask: mask of interrupt bits to update
 * @enabled_irq_mask: mask of interrupt bits to enable
 */
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void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
				  uint32_t interrupt_mask,
				  uint32_t enabled_irq_mask)
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{
	uint32_t sdeimr = I915_READ(SDEIMR);
	sdeimr &= ~interrupt_mask;
	sdeimr |= (~enabled_irq_mask & interrupt_mask);

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	WARN_ON(enabled_irq_mask & ~interrupt_mask);

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	assert_spin_locked(&dev_priv->irq_lock);

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	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
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		return;

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	I915_WRITE(SDEIMR, sdeimr);
	POSTING_READ(SDEIMR);
}
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static void
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__i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		       u32 enable_mask, u32 status_mask)
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{
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	u32 reg = PIPESTAT(pipe);
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	u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
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	assert_spin_locked(&dev_priv->irq_lock);
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	WARN_ON(!intel_irqs_enabled(dev_priv));
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	if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
		      status_mask & ~PIPESTAT_INT_STATUS_MASK,
		      "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
		      pipe_name(pipe), enable_mask, status_mask))
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		return;

	if ((pipestat & enable_mask) == enable_mask)
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		return;

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	dev_priv->pipestat_irq_mask[pipe] |= status_mask;

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	/* Enable the interrupt, clear any pending status */
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	pipestat |= enable_mask | status_mask;
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	I915_WRITE(reg, pipestat);
	POSTING_READ(reg);
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}

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static void
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__i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		        u32 enable_mask, u32 status_mask)
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{
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	u32 reg = PIPESTAT(pipe);
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	u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
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	assert_spin_locked(&dev_priv->irq_lock);
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	WARN_ON(!intel_irqs_enabled(dev_priv));
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	if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
		      status_mask & ~PIPESTAT_INT_STATUS_MASK,
		      "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
		      pipe_name(pipe), enable_mask, status_mask))
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		return;

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	if ((pipestat & enable_mask) == 0)
		return;

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	dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;

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	pipestat &= ~enable_mask;
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	I915_WRITE(reg, pipestat);
	POSTING_READ(reg);
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}

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static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
{
	u32 enable_mask = status_mask << 16;

	/*
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	 * On pipe A we don't support the PSR interrupt yet,
	 * on pipe B and C the same bit MBZ.
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	 */
	if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
		return 0;
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	/*
	 * On pipe B and C we don't support the PSR interrupt yet, on pipe
	 * A the same bit is for perf counters which we don't use either.
	 */
	if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
		return 0;
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	enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
			 SPRITE0_FLIP_DONE_INT_EN_VLV |
			 SPRITE1_FLIP_DONE_INT_EN_VLV);
	if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
		enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
	if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
		enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;

	return enable_mask;
}

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void
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		     u32 status_mask)
{
	u32 enable_mask;

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	if (IS_VALLEYVIEW(dev_priv->dev))
		enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
							   status_mask);
	else
		enable_mask = status_mask << 16;
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	__i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
}

void
i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		      u32 status_mask)
{
	u32 enable_mask;

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	if (IS_VALLEYVIEW(dev_priv->dev))
		enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
							   status_mask);
	else
		enable_mask = status_mask << 16;
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	__i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
}

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/**
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 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
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 */
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static void i915_enable_asle_pipestat(struct drm_device *dev)
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{
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	struct drm_i915_private *dev_priv = dev->dev_private;
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	if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
		return;

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	spin_lock_irq(&dev_priv->irq_lock);
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	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
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	if (INTEL_INFO(dev)->gen >= 4)
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		i915_enable_pipestat(dev_priv, PIPE_A,
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				     PIPE_LEGACY_BLC_EVENT_STATUS);
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	spin_unlock_irq(&dev_priv->irq_lock);
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}

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/*
 * This timing diagram depicts the video signal in and
 * around the vertical blanking period.
 *
 * Assumptions about the fictitious mode used in this example:
 *  vblank_start >= 3
 *  vsync_start = vblank_start + 1
 *  vsync_end = vblank_start + 2
 *  vtotal = vblank_start + 3
 *
 *           start of vblank:
 *           latch double buffered registers
 *           increment frame counter (ctg+)
 *           generate start of vblank interrupt (gen4+)
 *           |
 *           |          frame start:
 *           |          generate frame start interrupt (aka. vblank interrupt) (gmch)
 *           |          may be shifted forward 1-3 extra lines via PIPECONF
 *           |          |
 *           |          |  start of vsync:
 *           |          |  generate vsync interrupt
 *           |          |  |
 * ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx
 *       .   \hs/   .      \hs/          \hs/          \hs/   .      \hs/
 * ----va---> <-----------------vb--------------------> <--------va-------------
 *       |          |       <----vs----->                     |
 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
 *       |          |                                         |
 *       last visible pixel                                   first visible pixel
 *                  |                                         increment frame counter (gen3/4)
 *                  pixel counter = vblank_start * htotal     pixel counter = 0 (gen3/4)
 *
 * x  = horizontal active
 * _  = horizontal blanking
 * hs = horizontal sync
 * va = vertical active
 * vb = vertical blanking
 * vs = vertical sync
 * vbs = vblank_start (number)
 *
 * Summary:
 * - most events happen at the start of horizontal sync
 * - frame start happens at the start of horizontal blank, 1-4 lines
 *   (depending on PIPECONF settings) after the start of vblank
 * - gen3/4 pixel and frame counter are synchronized with the start
 *   of horizontal active on the first line of vertical active
 */

550 551 552 553 554 555
static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
{
	/* Gen2 doesn't have a hardware frame counter */
	return 0;
}

556 557 558
/* Called from drm generic code, passed a 'crtc', which
 * we use as a pipe index
 */
559
static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
560
{
561
	struct drm_i915_private *dev_priv = dev->dev_private;
562 563
	unsigned long high_frame;
	unsigned long low_frame;
564
	u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
565 566 567 568
	struct intel_crtc *intel_crtc =
		to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
	const struct drm_display_mode *mode =
		&intel_crtc->config->base.adjusted_mode;
569

570 571 572 573 574
	htotal = mode->crtc_htotal;
	hsync_start = mode->crtc_hsync_start;
	vbl_start = mode->crtc_vblank_start;
	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
		vbl_start = DIV_ROUND_UP(vbl_start, 2);
575

576 577 578 579 580 581
	/* Convert to pixel count */
	vbl_start *= htotal;

	/* Start of vblank event occurs at start of hsync */
	vbl_start -= htotal - hsync_start;

582 583
	high_frame = PIPEFRAME(pipe);
	low_frame = PIPEFRAMEPIXEL(pipe);
584

585 586 587 588 589 590
	/*
	 * High & low register fields aren't synchronized, so make sure
	 * we get a low value that's stable across two reads of the high
	 * register.
	 */
	do {
591
		high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
592
		low   = I915_READ(low_frame);
593
		high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
594 595
	} while (high1 != high2);

596
	high1 >>= PIPE_FRAME_HIGH_SHIFT;
597
	pixel = low & PIPE_PIXEL_MASK;
598
	low >>= PIPE_FRAME_LOW_SHIFT;
599 600 601 602 603 604

	/*
	 * The frame counter increments at beginning of active.
	 * Cook up a vblank counter by also checking the pixel
	 * counter against vblank start.
	 */
605
	return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
606 607
}

608
static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
609
{
610
	struct drm_i915_private *dev_priv = dev->dev_private;
611
	int reg = PIPE_FRMCOUNT_GM45(pipe);
612 613 614 615

	return I915_READ(reg);
}

616 617 618
/* raw reads, only for fast reads of display block, no need for forcewake etc. */
#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))

619 620 621 622
static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
623
	const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
624
	enum pipe pipe = crtc->pipe;
625
	int position, vtotal;
626

627
	vtotal = mode->crtc_vtotal;
628 629 630 631 632 633 634 635 636
	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
		vtotal /= 2;

	if (IS_GEN2(dev))
		position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
	else
		position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;

	/*
637 638
	 * See update_scanline_offset() for the details on the
	 * scanline_offset adjustment.
639
	 */
640
	return (position + crtc->scanline_offset) % vtotal;
641 642
}

643
static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
644 645
				    unsigned int flags, int *vpos, int *hpos,
				    ktime_t *stime, ktime_t *etime)
646
{
647 648 649
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
650
	const struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
651
	int position;
652
	int vbl_start, vbl_end, hsync_start, htotal, vtotal;
653 654
	bool in_vbl = true;
	int ret = 0;
655
	unsigned long irqflags;
656

657
	if (!intel_crtc->active) {
658
		DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
659
				 "pipe %c\n", pipe_name(pipe));
660 661 662
		return 0;
	}

663
	htotal = mode->crtc_htotal;
664
	hsync_start = mode->crtc_hsync_start;
665 666 667
	vtotal = mode->crtc_vtotal;
	vbl_start = mode->crtc_vblank_start;
	vbl_end = mode->crtc_vblank_end;
668

669 670 671 672 673 674
	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
		vbl_start = DIV_ROUND_UP(vbl_start, 2);
		vbl_end /= 2;
		vtotal /= 2;
	}

675 676
	ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;

677 678 679 680 681 682
	/*
	 * Lock uncore.lock, as we will do multiple timing critical raw
	 * register reads, potentially with preemption disabled, so the
	 * following code must not block on uncore.lock.
	 */
	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
683

684 685 686 687 688 689
	/* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */

	/* Get optional system timestamp before query. */
	if (stime)
		*stime = ktime_get();

690
	if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
691 692 693
		/* No obvious pixelcount register. Only query vertical
		 * scanout position from Display scan line register.
		 */
694
		position = __intel_get_crtc_scanline(intel_crtc);
695 696 697 698 699
	} else {
		/* Have access to pixelcount since start of frame.
		 * We can split this into vertical and horizontal
		 * scanout position.
		 */
700
		position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
701

702 703 704 705
		/* convert to pixel counts */
		vbl_start *= htotal;
		vbl_end *= htotal;
		vtotal *= htotal;
706

707 708 709 710 711 712 713 714 715 716 717 718
		/*
		 * In interlaced modes, the pixel counter counts all pixels,
		 * so one field will have htotal more pixels. In order to avoid
		 * the reported position from jumping backwards when the pixel
		 * counter is beyond the length of the shorter field, just
		 * clamp the position the length of the shorter field. This
		 * matches how the scanline counter based position works since
		 * the scanline counter doesn't count the two half lines.
		 */
		if (position >= vtotal)
			position = vtotal - 1;

719 720 721 722 723 724 725 726 727 728
		/*
		 * Start of vblank interrupt is triggered at start of hsync,
		 * just prior to the first active line of vblank. However we
		 * consider lines to start at the leading edge of horizontal
		 * active. So, should we get here before we've crossed into
		 * the horizontal active of the first line in vblank, we would
		 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
		 * always add htotal-hsync_start to the current pixel position.
		 */
		position = (position + htotal - hsync_start) % vtotal;
729 730
	}

731 732 733 734 735 736 737 738
	/* Get optional system timestamp after query. */
	if (etime)
		*etime = ktime_get();

	/* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */

	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

739 740 741 742 743 744 745 746 747 748 749 750
	in_vbl = position >= vbl_start && position < vbl_end;

	/*
	 * While in vblank, position will be negative
	 * counting up towards 0 at vbl_end. And outside
	 * vblank, position will be positive counting
	 * up since vbl_end.
	 */
	if (position >= vbl_start)
		position -= vbl_end;
	else
		position += vtotal - vbl_end;
751

752
	if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
753 754 755 756 757 758
		*vpos = position;
		*hpos = 0;
	} else {
		*vpos = position / htotal;
		*hpos = position - (*vpos * htotal);
	}
759 760 761

	/* In vblank? */
	if (in_vbl)
762
		ret |= DRM_SCANOUTPOS_IN_VBLANK;
763 764 765 766

	return ret;
}

767 768 769 770 771 772 773 774 775 776 777 778 779
int intel_get_crtc_scanline(struct intel_crtc *crtc)
{
	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
	unsigned long irqflags;
	int position;

	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
	position = __intel_get_crtc_scanline(crtc);
	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

	return position;
}

780
static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
781 782 783 784
			      int *max_error,
			      struct timeval *vblank_time,
			      unsigned flags)
{
785
	struct drm_crtc *crtc;
786

787
	if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
788
		DRM_ERROR("Invalid crtc %d\n", pipe);
789 790 791 792
		return -EINVAL;
	}

	/* Get drm_crtc to timestamp: */
793 794 795 796 797 798
	crtc = intel_get_crtc_for_pipe(dev, pipe);
	if (crtc == NULL) {
		DRM_ERROR("Invalid crtc %d\n", pipe);
		return -EINVAL;
	}

799
	if (!crtc->state->enable) {
800 801 802
		DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
		return -EBUSY;
	}
803 804

	/* Helper routine in DRM core does all the work: */
805 806
	return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
						     vblank_time, flags,
807
						     crtc,
808
						     &to_intel_crtc(crtc)->config->base.adjusted_mode);
809 810
}

811 812
static bool intel_hpd_irq_event(struct drm_device *dev,
				struct drm_connector *connector)
813 814 815 816 817 818 819
{
	enum drm_connector_status old_status;

	WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
	old_status = connector->status;

	connector->status = connector->funcs->detect(connector, false);
820 821 822 823
	if (old_status == connector->status)
		return false;

	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
824
		      connector->base.id,
825
		      connector->name,
826 827 828 829
		      drm_get_connector_status_name(old_status),
		      drm_get_connector_status_name(connector->status));

	return true;
830 831
}

832 833 834 835 836 837
static void i915_digport_work_func(struct work_struct *work)
{
	struct drm_i915_private *dev_priv =
		container_of(work, struct drm_i915_private, dig_port_work);
	u32 long_port_mask, short_port_mask;
	struct intel_digital_port *intel_dig_port;
838
	int i;
839 840
	u32 old_bits = 0;

841
	spin_lock_irq(&dev_priv->irq_lock);
842 843 844 845
	long_port_mask = dev_priv->long_hpd_port_mask;
	dev_priv->long_hpd_port_mask = 0;
	short_port_mask = dev_priv->short_hpd_port_mask;
	dev_priv->short_hpd_port_mask = 0;
846
	spin_unlock_irq(&dev_priv->irq_lock);
847 848 849 850 851 852 853 854 855 856 857 858 859 860 861

	for (i = 0; i < I915_MAX_PORTS; i++) {
		bool valid = false;
		bool long_hpd = false;
		intel_dig_port = dev_priv->hpd_irq_port[i];
		if (!intel_dig_port || !intel_dig_port->hpd_pulse)
			continue;

		if (long_port_mask & (1 << i))  {
			valid = true;
			long_hpd = true;
		} else if (short_port_mask & (1 << i))
			valid = true;

		if (valid) {
862 863
			enum irqreturn ret;

864
			ret = intel_dig_port->hpd_pulse(intel_dig_port, long_hpd);
865 866
			if (ret == IRQ_NONE) {
				/* fall back to old school hpd */
867 868 869 870 871 872
				old_bits |= (1 << intel_dig_port->base.hpd_pin);
			}
		}
	}

	if (old_bits) {
873
		spin_lock_irq(&dev_priv->irq_lock);
874
		dev_priv->hpd_event_bits |= old_bits;
875
		spin_unlock_irq(&dev_priv->irq_lock);
876 877 878 879
		schedule_work(&dev_priv->hotplug_work);
	}
}

880 881 882
/*
 * Handle hotplug events outside the interrupt handler proper.
 */
883 884
#define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)

885 886
static void i915_hotplug_work_func(struct work_struct *work)
{
887 888
	struct drm_i915_private *dev_priv =
		container_of(work, struct drm_i915_private, hotplug_work);
889
	struct drm_device *dev = dev_priv->dev;
890
	struct drm_mode_config *mode_config = &dev->mode_config;
891 892 893 894
	struct intel_connector *intel_connector;
	struct intel_encoder *intel_encoder;
	struct drm_connector *connector;
	bool hpd_disabled = false;
895
	bool changed = false;
896
	u32 hpd_event_bits;
897

898
	mutex_lock(&mode_config->mutex);
899 900
	DRM_DEBUG_KMS("running encoder hotplug functions\n");

901
	spin_lock_irq(&dev_priv->irq_lock);
902 903 904

	hpd_event_bits = dev_priv->hpd_event_bits;
	dev_priv->hpd_event_bits = 0;
905 906
	list_for_each_entry(connector, &mode_config->connector_list, head) {
		intel_connector = to_intel_connector(connector);
907 908
		if (!intel_connector->encoder)
			continue;
909 910 911 912 913 914
		intel_encoder = intel_connector->encoder;
		if (intel_encoder->hpd_pin > HPD_NONE &&
		    dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
		    connector->polled == DRM_CONNECTOR_POLL_HPD) {
			DRM_INFO("HPD interrupt storm detected on connector %s: "
				 "switching from hotplug detection to polling\n",
915
				connector->name);
916 917 918 919 920
			dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
			connector->polled = DRM_CONNECTOR_POLL_CONNECT
				| DRM_CONNECTOR_POLL_DISCONNECT;
			hpd_disabled = true;
		}
921 922
		if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
			DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
923
				      connector->name, intel_encoder->hpd_pin);
924
		}
925 926 927 928
	}
	 /* if there were no outputs to poll, poll was disabled,
	  * therefore make sure it's enabled when disabling HPD on
	  * some connectors */
929
	if (hpd_disabled) {
930
		drm_kms_helper_poll_enable(dev);
931 932
		mod_delayed_work(system_wq, &dev_priv->hotplug_reenable_work,
				 msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
933
	}
934

935
	spin_unlock_irq(&dev_priv->irq_lock);
936

937 938
	list_for_each_entry(connector, &mode_config->connector_list, head) {
		intel_connector = to_intel_connector(connector);
939 940
		if (!intel_connector->encoder)
			continue;
941 942 943 944 945 946 947 948
		intel_encoder = intel_connector->encoder;
		if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
			if (intel_encoder->hot_plug)
				intel_encoder->hot_plug(intel_encoder);
			if (intel_hpd_irq_event(dev, connector))
				changed = true;
		}
	}
949 950
	mutex_unlock(&mode_config->mutex);

951 952
	if (changed)
		drm_kms_helper_hotplug_event(dev);
953 954
}

955
static void ironlake_rps_change_irq_handler(struct drm_device *dev)
956
{
957
	struct drm_i915_private *dev_priv = dev->dev_private;
958
	u32 busy_up, busy_down, max_avg, min_avg;
959 960
	u8 new_delay;

961
	spin_lock(&mchdev_lock);
962

963 964
	I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));

965
	new_delay = dev_priv->ips.cur_delay;
966

967
	I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
968 969
	busy_up = I915_READ(RCPREVBSYTUPAVG);
	busy_down = I915_READ(RCPREVBSYTDNAVG);
970 971 972 973
	max_avg = I915_READ(RCBMAXAVG);
	min_avg = I915_READ(RCBMINAVG);

	/* Handle RCS change request from hw */
974
	if (busy_up > max_avg) {
975 976 977 978
		if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
			new_delay = dev_priv->ips.cur_delay - 1;
		if (new_delay < dev_priv->ips.max_delay)
			new_delay = dev_priv->ips.max_delay;
979
	} else if (busy_down < min_avg) {
980 981 982 983
		if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
			new_delay = dev_priv->ips.cur_delay + 1;
		if (new_delay > dev_priv->ips.min_delay)
			new_delay = dev_priv->ips.min_delay;
984 985
	}

986
	if (ironlake_set_drps(dev, new_delay))
987
		dev_priv->ips.cur_delay = new_delay;
988

989
	spin_unlock(&mchdev_lock);
990

991 992 993
	return;
}

C
Chris Wilson 已提交
994
static void notify_ring(struct intel_engine_cs *ring)
995
{
996
	if (!intel_ring_initialized(ring))
997 998
		return;

999
	trace_i915_gem_request_notify(ring);
1000

1001 1002 1003
	wake_up_all(&ring->irq_queue);
}

1004 1005
static void vlv_c0_read(struct drm_i915_private *dev_priv,
			struct intel_rps_ei *ei)
1006
{
1007 1008 1009 1010
	ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
	ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
	ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
}
1011

1012 1013 1014 1015 1016 1017
static bool vlv_c0_above(struct drm_i915_private *dev_priv,
			 const struct intel_rps_ei *old,
			 const struct intel_rps_ei *now,
			 int threshold)
{
	u64 time, c0;
1018

1019 1020
	if (old->cz_clock == 0)
		return false;
1021

1022 1023
	time = now->cz_clock - old->cz_clock;
	time *= threshold * dev_priv->mem_freq;
1024

1025 1026 1027
	/* Workload can be split between render + media, e.g. SwapBuffers
	 * being blitted in X after being rendered in mesa. To account for
	 * this we need to combine both engines into our activity counter.
1028
	 */
1029 1030 1031
	c0 = now->render_c0 - old->render_c0;
	c0 += now->media_c0 - old->media_c0;
	c0 *= 100 * VLV_CZ_CLOCK_TO_MILLI_SEC * 4 / 1000;
1032

1033
	return c0 >= time;
1034 1035
}

1036
void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1037
{
1038 1039 1040
	vlv_c0_read(dev_priv, &dev_priv->rps.down_ei);
	dev_priv->rps.up_ei = dev_priv->rps.down_ei;
}
1041

1042 1043 1044 1045
static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
{
	struct intel_rps_ei now;
	u32 events = 0;
1046

1047
	if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0)
1048
		return 0;
1049

1050 1051 1052
	vlv_c0_read(dev_priv, &now);
	if (now.cz_clock == 0)
		return 0;
1053

1054 1055 1056
	if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
		if (!vlv_c0_above(dev_priv,
				  &dev_priv->rps.down_ei, &now,
1057
				  dev_priv->rps.down_threshold))
1058 1059 1060
			events |= GEN6_PM_RP_DOWN_THRESHOLD;
		dev_priv->rps.down_ei = now;
	}
1061

1062 1063 1064
	if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
		if (vlv_c0_above(dev_priv,
				 &dev_priv->rps.up_ei, &now,
1065
				 dev_priv->rps.up_threshold))
1066 1067
			events |= GEN6_PM_RP_UP_THRESHOLD;
		dev_priv->rps.up_ei = now;
1068 1069
	}

1070
	return events;
1071 1072
}

1073
static void gen6_pm_rps_work(struct work_struct *work)
1074
{
1075 1076
	struct drm_i915_private *dev_priv =
		container_of(work, struct drm_i915_private, rps.work);
P
Paulo Zanoni 已提交
1077
	u32 pm_iir;
1078
	int new_delay, adj;
1079

1080
	spin_lock_irq(&dev_priv->irq_lock);
I
Imre Deak 已提交
1081 1082 1083 1084 1085
	/* Speed up work cancelation during disabling rps interrupts. */
	if (!dev_priv->rps.interrupts_enabled) {
		spin_unlock_irq(&dev_priv->irq_lock);
		return;
	}
1086 1087
	pm_iir = dev_priv->rps.pm_iir;
	dev_priv->rps.pm_iir = 0;
1088 1089
	/* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
	gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1090
	spin_unlock_irq(&dev_priv->irq_lock);
1091

1092
	/* Make sure we didn't queue anything we're not going to process. */
1093
	WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1094

1095
	if ((pm_iir & dev_priv->pm_rps_events) == 0)
1096 1097
		return;

1098
	mutex_lock(&dev_priv->rps.hw_lock);
1099

1100 1101
	pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);

1102
	adj = dev_priv->rps.last_adj;
1103
	new_delay = dev_priv->rps.cur_freq;
1104
	if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1105 1106
		if (adj > 0)
			adj *= 2;
1107 1108
		else /* CHV needs even encode values */
			adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1109 1110 1111 1112
		/*
		 * For better performance, jump directly
		 * to RPe if we're below it.
		 */
1113
		if (new_delay < dev_priv->rps.efficient_freq - adj) {
1114
			new_delay = dev_priv->rps.efficient_freq;
1115 1116
			adj = 0;
		}
1117
	} else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1118 1119
		if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
			new_delay = dev_priv->rps.efficient_freq;
1120
		else
1121
			new_delay = dev_priv->rps.min_freq_softlimit;
1122 1123 1124 1125
		adj = 0;
	} else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
		if (adj < 0)
			adj *= 2;
1126 1127
		else /* CHV needs even encode values */
			adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1128
	} else { /* unknown event */
1129
		adj = 0;
1130
	}
1131

1132 1133
	dev_priv->rps.last_adj = adj;

1134 1135 1136
	/* sysfs frequency interfaces may have snuck in while servicing the
	 * interrupt
	 */
1137
	new_delay += adj;
1138
	new_delay = clamp_t(int, new_delay,
1139 1140
			    dev_priv->rps.min_freq_softlimit,
			    dev_priv->rps.max_freq_softlimit);
1141

1142
	intel_set_rps(dev_priv->dev, new_delay);
1143

1144
	mutex_unlock(&dev_priv->rps.hw_lock);
1145 1146
}

1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158

/**
 * ivybridge_parity_work - Workqueue called when a parity error interrupt
 * occurred.
 * @work: workqueue struct
 *
 * Doesn't actually do anything except notify userspace. As a consequence of
 * this event, userspace should try to remap the bad rows since statistically
 * it is likely the same row is more likely to go bad again.
 */
static void ivybridge_parity_work(struct work_struct *work)
{
1159 1160
	struct drm_i915_private *dev_priv =
		container_of(work, struct drm_i915_private, l3_parity.error_work);
1161
	u32 error_status, row, bank, subbank;
1162
	char *parity_event[6];
1163
	uint32_t misccpctl;
1164
	uint8_t slice = 0;
1165 1166 1167 1168 1169 1170 1171

	/* We must turn off DOP level clock gating to access the L3 registers.
	 * In order to prevent a get/put style interface, acquire struct mutex
	 * any time we access those registers.
	 */
	mutex_lock(&dev_priv->dev->struct_mutex);

1172 1173 1174 1175
	/* If we've screwed up tracking, just let the interrupt fire again */
	if (WARN_ON(!dev_priv->l3_parity.which_slice))
		goto out;

1176 1177 1178 1179
	misccpctl = I915_READ(GEN7_MISCCPCTL);
	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
	POSTING_READ(GEN7_MISCCPCTL);

1180 1181
	while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
		u32 reg;
1182

1183 1184 1185
		slice--;
		if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
			break;
1186

1187
		dev_priv->l3_parity.which_slice &= ~(1<<slice);
1188

1189
		reg = GEN7_L3CDERRST1 + (slice * 0x200);
1190

1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205
		error_status = I915_READ(reg);
		row = GEN7_PARITY_ERROR_ROW(error_status);
		bank = GEN7_PARITY_ERROR_BANK(error_status);
		subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);

		I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
		POSTING_READ(reg);

		parity_event[0] = I915_L3_PARITY_UEVENT "=1";
		parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
		parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
		parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
		parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
		parity_event[5] = NULL;

1206
		kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1207
				   KOBJ_CHANGE, parity_event);
1208

1209 1210
		DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
			  slice, row, bank, subbank);
1211

1212 1213 1214 1215 1216
		kfree(parity_event[4]);
		kfree(parity_event[3]);
		kfree(parity_event[2]);
		kfree(parity_event[1]);
	}
1217

1218
	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1219

1220 1221
out:
	WARN_ON(dev_priv->l3_parity.which_slice);
1222
	spin_lock_irq(&dev_priv->irq_lock);
1223
	gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1224
	spin_unlock_irq(&dev_priv->irq_lock);
1225 1226

	mutex_unlock(&dev_priv->dev->struct_mutex);
1227 1228
}

1229
static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1230
{
1231
	struct drm_i915_private *dev_priv = dev->dev_private;
1232

1233
	if (!HAS_L3_DPF(dev))
1234 1235
		return;

1236
	spin_lock(&dev_priv->irq_lock);
1237
	gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1238
	spin_unlock(&dev_priv->irq_lock);
1239

1240 1241 1242 1243 1244 1245 1246
	iir &= GT_PARITY_ERROR(dev);
	if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
		dev_priv->l3_parity.which_slice |= 1 << 1;

	if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
		dev_priv->l3_parity.which_slice |= 1 << 0;

1247
	queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1248 1249
}

1250 1251 1252 1253 1254 1255
static void ilk_gt_irq_handler(struct drm_device *dev,
			       struct drm_i915_private *dev_priv,
			       u32 gt_iir)
{
	if (gt_iir &
	    (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
C
Chris Wilson 已提交
1256
		notify_ring(&dev_priv->ring[RCS]);
1257
	if (gt_iir & ILK_BSD_USER_INTERRUPT)
C
Chris Wilson 已提交
1258
		notify_ring(&dev_priv->ring[VCS]);
1259 1260
}

1261 1262 1263 1264 1265
static void snb_gt_irq_handler(struct drm_device *dev,
			       struct drm_i915_private *dev_priv,
			       u32 gt_iir)
{

1266 1267
	if (gt_iir &
	    (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
C
Chris Wilson 已提交
1268
		notify_ring(&dev_priv->ring[RCS]);
1269
	if (gt_iir & GT_BSD_USER_INTERRUPT)
C
Chris Wilson 已提交
1270
		notify_ring(&dev_priv->ring[VCS]);
1271
	if (gt_iir & GT_BLT_USER_INTERRUPT)
C
Chris Wilson 已提交
1272
		notify_ring(&dev_priv->ring[BCS]);
1273

1274 1275
	if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
		      GT_BSD_CS_ERROR_INTERRUPT |
1276 1277
		      GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
		DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1278

1279 1280
	if (gt_iir & GT_PARITY_ERROR(dev))
		ivybridge_parity_error_irq_handler(dev, gt_iir);
1281 1282
}

C
Chris Wilson 已提交
1283
static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
1284 1285 1286 1287 1288
				       u32 master_ctl)
{
	irqreturn_t ret = IRQ_NONE;

	if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
C
Chris Wilson 已提交
1289
		u32 tmp = I915_READ_FW(GEN8_GT_IIR(0));
1290
		if (tmp) {
1291
			I915_WRITE_FW(GEN8_GT_IIR(0), tmp);
1292
			ret = IRQ_HANDLED;
1293

C
Chris Wilson 已提交
1294 1295 1296 1297 1298 1299 1300 1301 1302
			if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
				intel_lrc_irq_handler(&dev_priv->ring[RCS]);
			if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
				notify_ring(&dev_priv->ring[RCS]);

			if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
				intel_lrc_irq_handler(&dev_priv->ring[BCS]);
			if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
				notify_ring(&dev_priv->ring[BCS]);
1303 1304 1305 1306
		} else
			DRM_ERROR("The master control interrupt lied (GT0)!\n");
	}

1307
	if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
C
Chris Wilson 已提交
1308
		u32 tmp = I915_READ_FW(GEN8_GT_IIR(1));
1309
		if (tmp) {
1310
			I915_WRITE_FW(GEN8_GT_IIR(1), tmp);
1311
			ret = IRQ_HANDLED;
1312

C
Chris Wilson 已提交
1313 1314 1315 1316
			if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
				intel_lrc_irq_handler(&dev_priv->ring[VCS]);
			if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
				notify_ring(&dev_priv->ring[VCS]);
1317

C
Chris Wilson 已提交
1318 1319 1320 1321
			if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
				intel_lrc_irq_handler(&dev_priv->ring[VCS2]);
			if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
				notify_ring(&dev_priv->ring[VCS2]);
1322
		} else
1323
			DRM_ERROR("The master control interrupt lied (GT1)!\n");
1324 1325
	}

1326
	if (master_ctl & GEN8_GT_VECS_IRQ) {
C
Chris Wilson 已提交
1327
		u32 tmp = I915_READ_FW(GEN8_GT_IIR(3));
1328
		if (tmp) {
C
Chris Wilson 已提交
1329
			I915_WRITE_FW(GEN8_GT_IIR(3), tmp);
1330
			ret = IRQ_HANDLED;
1331

C
Chris Wilson 已提交
1332 1333 1334 1335
			if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
				intel_lrc_irq_handler(&dev_priv->ring[VECS]);
			if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
				notify_ring(&dev_priv->ring[VECS]);
1336 1337 1338 1339
		} else
			DRM_ERROR("The master control interrupt lied (GT3)!\n");
	}

1340
	if (master_ctl & GEN8_GT_PM_IRQ) {
C
Chris Wilson 已提交
1341
		u32 tmp = I915_READ_FW(GEN8_GT_IIR(2));
1342
		if (tmp & dev_priv->pm_rps_events) {
1343 1344
			I915_WRITE_FW(GEN8_GT_IIR(2),
				      tmp & dev_priv->pm_rps_events);
1345
			ret = IRQ_HANDLED;
1346
			gen6_rps_irq_handler(dev_priv, tmp);
1347 1348 1349 1350
		} else
			DRM_ERROR("The master control interrupt lied (PM)!\n");
	}

1351 1352 1353
	return ret;
}

1354 1355 1356
#define HPD_STORM_DETECT_PERIOD 1000
#define HPD_STORM_THRESHOLD 5

1357
static int pch_port_to_hotplug_shift(enum port port)
1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372
{
	switch (port) {
	case PORT_A:
	case PORT_E:
	default:
		return -1;
	case PORT_B:
		return 0;
	case PORT_C:
		return 8;
	case PORT_D:
		return 16;
	}
}

1373
static int i915_port_to_hotplug_shift(enum port port)
1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388
{
	switch (port) {
	case PORT_A:
	case PORT_E:
	default:
		return -1;
	case PORT_B:
		return 17;
	case PORT_C:
		return 19;
	case PORT_D:
		return 21;
	}
}

1389
static enum port get_port_from_pin(enum hpd_pin pin)
1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402
{
	switch (pin) {
	case HPD_PORT_B:
		return PORT_B;
	case HPD_PORT_C:
		return PORT_C;
	case HPD_PORT_D:
		return PORT_D;
	default:
		return PORT_A; /* no hpd */
	}
}

1403 1404 1405 1406
static void intel_hpd_irq_handler(struct drm_device *dev,
				  u32 hotplug_trigger,
				  u32 dig_hotplug_reg,
				  const u32 hpd[HPD_NUM_PINS])
1407
{
1408
	struct drm_i915_private *dev_priv = dev->dev_private;
1409
	int i;
1410
	enum port port;
1411
	bool storm_detected = false;
1412 1413 1414
	bool queue_dig = false, queue_hp = false;
	u32 dig_shift;
	u32 dig_port_mask = 0;
1415

1416 1417 1418
	if (!hotplug_trigger)
		return;

1419 1420
	DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x\n",
			 hotplug_trigger, dig_hotplug_reg);
1421

1422
	spin_lock(&dev_priv->irq_lock);
1423
	for (i = 1; i < HPD_NUM_PINS; i++) {
1424 1425 1426 1427 1428 1429 1430
		if (!(hpd[i] & hotplug_trigger))
			continue;

		port = get_port_from_pin(i);
		if (port && dev_priv->hpd_irq_port[port]) {
			bool long_hpd;

1431
			if (!HAS_GMCH_DISPLAY(dev_priv)) {
1432
				dig_shift = pch_port_to_hotplug_shift(port);
1433
				long_hpd = (dig_hotplug_reg >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
1434 1435 1436
			} else {
				dig_shift = i915_port_to_hotplug_shift(port);
				long_hpd = (hotplug_trigger >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
1437 1438
			}

1439 1440 1441
			DRM_DEBUG_DRIVER("digital hpd port %c - %s\n",
					 port_name(port),
					 long_hpd ? "long" : "short");
1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454
			/* for long HPD pulses we want to have the digital queue happen,
			   but we still want HPD storm detection to function. */
			if (long_hpd) {
				dev_priv->long_hpd_port_mask |= (1 << port);
				dig_port_mask |= hpd[i];
			} else {
				/* for short HPD just trigger the digital queue */
				dev_priv->short_hpd_port_mask |= (1 << port);
				hotplug_trigger &= ~hpd[i];
			}
			queue_dig = true;
		}
	}
1455

1456
	for (i = 1; i < HPD_NUM_PINS; i++) {
1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470
		if (hpd[i] & hotplug_trigger &&
		    dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) {
			/*
			 * On GMCH platforms the interrupt mask bits only
			 * prevent irq generation, not the setting of the
			 * hotplug bits itself. So only WARN about unexpected
			 * interrupts on saner platforms.
			 */
			WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
				  "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
				  hotplug_trigger, i, hpd[i]);

			continue;
		}
1471

1472 1473 1474 1475
		if (!(hpd[i] & hotplug_trigger) ||
		    dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
			continue;

1476 1477 1478 1479 1480
		if (!(dig_port_mask & hpd[i])) {
			dev_priv->hpd_event_bits |= (1 << i);
			queue_hp = true;
		}

1481 1482 1483 1484 1485
		if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
				   dev_priv->hpd_stats[i].hpd_last_jiffies
				   + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
			dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
			dev_priv->hpd_stats[i].hpd_cnt = 0;
1486
			DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1487 1488
		} else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
			dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1489
			dev_priv->hpd_event_bits &= ~(1 << i);
1490
			DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1491
			storm_detected = true;
1492 1493
		} else {
			dev_priv->hpd_stats[i].hpd_cnt++;
1494 1495
			DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
				      dev_priv->hpd_stats[i].hpd_cnt);
1496 1497 1498
		}
	}

1499 1500
	if (storm_detected)
		dev_priv->display.hpd_irq_setup(dev);
1501
	spin_unlock(&dev_priv->irq_lock);
1502

1503 1504 1505 1506 1507 1508
	/*
	 * Our hotplug handler can grab modeset locks (by calling down into the
	 * fb helpers). Hence it must not be run on our own dev-priv->wq work
	 * queue for otherwise the flush_work in the pageflip code will
	 * deadlock.
	 */
1509
	if (queue_dig)
1510
		queue_work(dev_priv->dp_wq, &dev_priv->dig_port_work);
1511 1512
	if (queue_hp)
		schedule_work(&dev_priv->hotplug_work);
1513 1514
}

1515 1516
static void gmbus_irq_handler(struct drm_device *dev)
{
1517
	struct drm_i915_private *dev_priv = dev->dev_private;
1518 1519

	wake_up_all(&dev_priv->gmbus_wait_queue);
1520 1521
}

1522 1523
static void dp_aux_irq_handler(struct drm_device *dev)
{
1524
	struct drm_i915_private *dev_priv = dev->dev_private;
1525 1526

	wake_up_all(&dev_priv->gmbus_wait_queue);
1527 1528
}

1529
#if defined(CONFIG_DEBUG_FS)
1530 1531 1532 1533
static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
					 uint32_t crc0, uint32_t crc1,
					 uint32_t crc2, uint32_t crc3,
					 uint32_t crc4)
1534 1535 1536 1537
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
	struct intel_pipe_crc_entry *entry;
1538
	int head, tail;
1539

1540 1541
	spin_lock(&pipe_crc->lock);

1542
	if (!pipe_crc->entries) {
1543
		spin_unlock(&pipe_crc->lock);
1544
		DRM_DEBUG_KMS("spurious interrupt\n");
1545 1546 1547
		return;
	}

1548 1549
	head = pipe_crc->head;
	tail = pipe_crc->tail;
1550 1551

	if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1552
		spin_unlock(&pipe_crc->lock);
1553 1554 1555 1556 1557
		DRM_ERROR("CRC buffer overflowing\n");
		return;
	}

	entry = &pipe_crc->entries[head];
1558

1559
	entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1560 1561 1562 1563 1564
	entry->crc[0] = crc0;
	entry->crc[1] = crc1;
	entry->crc[2] = crc2;
	entry->crc[3] = crc3;
	entry->crc[4] = crc4;
1565 1566

	head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1567 1568 1569
	pipe_crc->head = head;

	spin_unlock(&pipe_crc->lock);
1570 1571

	wake_up_interruptible(&pipe_crc->wq);
1572
}
1573 1574 1575 1576 1577 1578 1579 1580
#else
static inline void
display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
			     uint32_t crc0, uint32_t crc1,
			     uint32_t crc2, uint32_t crc3,
			     uint32_t crc4) {}
#endif

1581

1582
static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
D
Daniel Vetter 已提交
1583 1584 1585
{
	struct drm_i915_private *dev_priv = dev->dev_private;

1586 1587 1588
	display_pipe_crc_irq_handler(dev, pipe,
				     I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
				     0, 0, 0, 0);
D
Daniel Vetter 已提交
1589 1590
}

1591
static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1592 1593 1594
{
	struct drm_i915_private *dev_priv = dev->dev_private;

1595 1596 1597 1598 1599 1600
	display_pipe_crc_irq_handler(dev, pipe,
				     I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
				     I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
				     I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
				     I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
				     I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1601
}
1602

1603
static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1604 1605
{
	struct drm_i915_private *dev_priv = dev->dev_private;
1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616
	uint32_t res1, res2;

	if (INTEL_INFO(dev)->gen >= 3)
		res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
	else
		res1 = 0;

	if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
		res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
	else
		res2 = 0;
1617

1618 1619 1620 1621 1622
	display_pipe_crc_irq_handler(dev, pipe,
				     I915_READ(PIPE_CRC_RES_RED(pipe)),
				     I915_READ(PIPE_CRC_RES_GREEN(pipe)),
				     I915_READ(PIPE_CRC_RES_BLUE(pipe)),
				     res1, res2);
1623
}
1624

1625 1626 1627 1628
/* The RPS events need forcewake, so we add them to a work queue and mask their
 * IMR bits until the work is done. Other interrupts can be processed without
 * the work queue. */
static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1629
{
1630
	if (pm_iir & dev_priv->pm_rps_events) {
1631
		spin_lock(&dev_priv->irq_lock);
1632
		gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
I
Imre Deak 已提交
1633 1634 1635 1636
		if (dev_priv->rps.interrupts_enabled) {
			dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
			queue_work(dev_priv->wq, &dev_priv->rps.work);
		}
1637
		spin_unlock(&dev_priv->irq_lock);
1638 1639
	}

1640 1641 1642
	if (INTEL_INFO(dev_priv)->gen >= 8)
		return;

1643 1644
	if (HAS_VEBOX(dev_priv->dev)) {
		if (pm_iir & PM_VEBOX_USER_INTERRUPT)
C
Chris Wilson 已提交
1645
			notify_ring(&dev_priv->ring[VECS]);
B
Ben Widawsky 已提交
1646

1647 1648
		if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
			DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
B
Ben Widawsky 已提交
1649
	}
1650 1651
}

1652 1653 1654 1655 1656 1657 1658 1659
static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
{
	if (!drm_handle_vblank(dev, pipe))
		return false;

	return true;
}

1660 1661 1662
static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
1663
	u32 pipe_stats[I915_MAX_PIPES] = { };
1664 1665
	int pipe;

1666
	spin_lock(&dev_priv->irq_lock);
1667
	for_each_pipe(dev_priv, pipe) {
1668
		int reg;
1669
		u32 mask, iir_bit = 0;
1670

1671 1672 1673 1674 1675 1676 1677
		/*
		 * PIPESTAT bits get signalled even when the interrupt is
		 * disabled with the mask bits, and some of the status bits do
		 * not generate interrupts at all (like the underrun bit). Hence
		 * we need to be careful that we only handle what we want to
		 * handle.
		 */
1678 1679 1680

		/* fifo underruns are filterered in the underrun handler. */
		mask = PIPE_FIFO_UNDERRUN_STATUS;
1681 1682 1683 1684 1685 1686 1687 1688

		switch (pipe) {
		case PIPE_A:
			iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
			break;
		case PIPE_B:
			iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
			break;
1689 1690 1691
		case PIPE_C:
			iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
			break;
1692 1693 1694 1695 1696
		}
		if (iir & iir_bit)
			mask |= dev_priv->pipestat_irq_mask[pipe];

		if (!mask)
1697 1698 1699
			continue;

		reg = PIPESTAT(pipe);
1700 1701
		mask |= PIPESTAT_INT_ENABLE_MASK;
		pipe_stats[pipe] = I915_READ(reg) & mask;
1702 1703 1704 1705

		/*
		 * Clear the PIPE*STAT regs before the IIR
		 */
1706 1707
		if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
					PIPESTAT_INT_STATUS_MASK))
1708 1709
			I915_WRITE(reg, pipe_stats[pipe]);
	}
1710
	spin_unlock(&dev_priv->irq_lock);
1711

1712
	for_each_pipe(dev_priv, pipe) {
1713 1714 1715
		if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
		    intel_pipe_handle_vblank(dev, pipe))
			intel_check_page_flip(dev, pipe);
1716

1717
		if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
1718 1719 1720 1721 1722 1723 1724
			intel_prepare_page_flip(dev, pipe);
			intel_finish_page_flip(dev, pipe);
		}

		if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
			i9xx_pipe_crc_irq_handler(dev, pipe);

1725 1726
		if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1727 1728 1729 1730 1731 1732
	}

	if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
		gmbus_irq_handler(dev);
}

1733 1734 1735 1736 1737
static void i9xx_hpd_irq_handler(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);

1738 1739 1740 1741 1742 1743 1744
	if (hotplug_status) {
		I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
		/*
		 * Make sure hotplug status is cleared before we clear IIR, or else we
		 * may miss hotplug events.
		 */
		POSTING_READ(PORT_HOTPLUG_STAT);
1745

1746 1747
		if (IS_G4X(dev)) {
			u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1748

1749
			intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_g4x);
1750 1751
		} else {
			u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1752

1753
			intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_i915);
1754
		}
1755

1756 1757 1758 1759
		if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) &&
		    hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
			dp_aux_irq_handler(dev);
	}
1760 1761
}

1762
static irqreturn_t valleyview_irq_handler(int irq, void *arg)
J
Jesse Barnes 已提交
1763
{
1764
	struct drm_device *dev = arg;
1765
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
1766 1767 1768
	u32 iir, gt_iir, pm_iir;
	irqreturn_t ret = IRQ_NONE;

1769 1770 1771
	if (!intel_irqs_enabled(dev_priv))
		return IRQ_NONE;

J
Jesse Barnes 已提交
1772
	while (true) {
1773 1774
		/* Find, clear, then process each source of interrupt */

J
Jesse Barnes 已提交
1775
		gt_iir = I915_READ(GTIIR);
1776 1777 1778
		if (gt_iir)
			I915_WRITE(GTIIR, gt_iir);

J
Jesse Barnes 已提交
1779
		pm_iir = I915_READ(GEN6_PMIIR);
1780 1781 1782 1783 1784 1785 1786 1787 1788 1789
		if (pm_iir)
			I915_WRITE(GEN6_PMIIR, pm_iir);

		iir = I915_READ(VLV_IIR);
		if (iir) {
			/* Consume port before clearing IIR or we'll miss events */
			if (iir & I915_DISPLAY_PORT_INTERRUPT)
				i9xx_hpd_irq_handler(dev);
			I915_WRITE(VLV_IIR, iir);
		}
J
Jesse Barnes 已提交
1790 1791 1792 1793 1794 1795

		if (gt_iir == 0 && pm_iir == 0 && iir == 0)
			goto out;

		ret = IRQ_HANDLED;

1796 1797
		if (gt_iir)
			snb_gt_irq_handler(dev, dev_priv, gt_iir);
1798
		if (pm_iir)
1799
			gen6_rps_irq_handler(dev_priv, pm_iir);
1800 1801 1802
		/* Call regardless, as some status bits might not be
		 * signalled in iir */
		valleyview_pipestat_irq_handler(dev, iir);
J
Jesse Barnes 已提交
1803 1804 1805 1806 1807 1808
	}

out:
	return ret;
}

1809 1810
static irqreturn_t cherryview_irq_handler(int irq, void *arg)
{
1811
	struct drm_device *dev = arg;
1812 1813 1814 1815
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 master_ctl, iir;
	irqreturn_t ret = IRQ_NONE;

1816 1817 1818
	if (!intel_irqs_enabled(dev_priv))
		return IRQ_NONE;

1819 1820 1821
	for (;;) {
		master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
		iir = I915_READ(VLV_IIR);
1822

1823 1824
		if (master_ctl == 0 && iir == 0)
			break;
1825

1826 1827
		ret = IRQ_HANDLED;

1828
		I915_WRITE(GEN8_MASTER_IRQ, 0);
1829

1830
		/* Find, clear, then process each source of interrupt */
1831

1832 1833 1834 1835 1836 1837
		if (iir) {
			/* Consume port before clearing IIR or we'll miss events */
			if (iir & I915_DISPLAY_PORT_INTERRUPT)
				i9xx_hpd_irq_handler(dev);
			I915_WRITE(VLV_IIR, iir);
		}
1838

C
Chris Wilson 已提交
1839
		gen8_gt_irq_handler(dev_priv, master_ctl);
1840

1841 1842 1843
		/* Call regardless, as some status bits might not be
		 * signalled in iir */
		valleyview_pipestat_irq_handler(dev, iir);
1844

1845 1846 1847
		I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
		POSTING_READ(GEN8_MASTER_IRQ);
	}
1848

1849 1850 1851
	return ret;
}

1852
static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1853
{
1854
	struct drm_i915_private *dev_priv = dev->dev_private;
1855
	int pipe;
1856
	u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1857 1858 1859 1860
	u32 dig_hotplug_reg;

	dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
	I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1861

1862
	intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_ibx);
1863

1864 1865 1866
	if (pch_iir & SDE_AUDIO_POWER_MASK) {
		int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
			       SDE_AUDIO_POWER_SHIFT);
1867
		DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1868 1869
				 port_name(port));
	}
1870

1871 1872 1873
	if (pch_iir & SDE_AUX_MASK)
		dp_aux_irq_handler(dev);

1874
	if (pch_iir & SDE_GMBUS)
1875
		gmbus_irq_handler(dev);
1876 1877 1878 1879 1880 1881 1882 1883 1884 1885

	if (pch_iir & SDE_AUDIO_HDCP_MASK)
		DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");

	if (pch_iir & SDE_AUDIO_TRANS_MASK)
		DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");

	if (pch_iir & SDE_POISON)
		DRM_ERROR("PCH poison interrupt\n");

1886
	if (pch_iir & SDE_FDI_MASK)
1887
		for_each_pipe(dev_priv, pipe)
1888 1889 1890
			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
					 pipe_name(pipe),
					 I915_READ(FDI_RX_IIR(pipe)));
1891 1892 1893 1894 1895 1896 1897 1898

	if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
		DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");

	if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
		DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");

	if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1899
		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
1900 1901

	if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1902
		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
1903 1904 1905 1906 1907 1908
}

static void ivb_err_int_handler(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 err_int = I915_READ(GEN7_ERR_INT);
D
Daniel Vetter 已提交
1909
	enum pipe pipe;
1910

1911 1912 1913
	if (err_int & ERR_INT_POISON)
		DRM_ERROR("Poison interrupt\n");

1914
	for_each_pipe(dev_priv, pipe) {
1915 1916
		if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1917

D
Daniel Vetter 已提交
1918 1919
		if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
			if (IS_IVYBRIDGE(dev))
1920
				ivb_pipe_crc_irq_handler(dev, pipe);
D
Daniel Vetter 已提交
1921
			else
1922
				hsw_pipe_crc_irq_handler(dev, pipe);
D
Daniel Vetter 已提交
1923 1924
		}
	}
1925

1926 1927 1928 1929 1930 1931 1932 1933
	I915_WRITE(GEN7_ERR_INT, err_int);
}

static void cpt_serr_int_handler(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 serr_int = I915_READ(SERR_INT);

1934 1935 1936
	if (serr_int & SERR_INT_POISON)
		DRM_ERROR("PCH poison interrupt\n");

1937
	if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1938
		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
1939 1940

	if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1941
		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
1942 1943

	if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1944
		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
1945 1946

	I915_WRITE(SERR_INT, serr_int);
1947 1948
}

1949 1950
static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
{
1951
	struct drm_i915_private *dev_priv = dev->dev_private;
1952
	int pipe;
1953
	u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1954 1955 1956 1957
	u32 dig_hotplug_reg;

	dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
	I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1958

1959
	intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_cpt);
1960

1961 1962 1963 1964 1965 1966
	if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
		int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
			       SDE_AUDIO_POWER_SHIFT_CPT);
		DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
				 port_name(port));
	}
1967 1968

	if (pch_iir & SDE_AUX_MASK_CPT)
1969
		dp_aux_irq_handler(dev);
1970 1971

	if (pch_iir & SDE_GMBUS_CPT)
1972
		gmbus_irq_handler(dev);
1973 1974 1975 1976 1977 1978 1979 1980

	if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
		DRM_DEBUG_DRIVER("Audio CP request interrupt\n");

	if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
		DRM_DEBUG_DRIVER("Audio CP change interrupt\n");

	if (pch_iir & SDE_FDI_MASK_CPT)
1981
		for_each_pipe(dev_priv, pipe)
1982 1983 1984
			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
					 pipe_name(pipe),
					 I915_READ(FDI_RX_IIR(pipe)));
1985 1986 1987

	if (pch_iir & SDE_ERROR_CPT)
		cpt_serr_int_handler(dev);
1988 1989
}

1990 1991 1992
static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
1993
	enum pipe pipe;
1994 1995 1996 1997 1998 1999 2000 2001 2002 2003

	if (de_iir & DE_AUX_CHANNEL_A)
		dp_aux_irq_handler(dev);

	if (de_iir & DE_GSE)
		intel_opregion_asle_intr(dev);

	if (de_iir & DE_POISON)
		DRM_ERROR("Poison interrupt\n");

2004
	for_each_pipe(dev_priv, pipe) {
2005 2006 2007
		if (de_iir & DE_PIPE_VBLANK(pipe) &&
		    intel_pipe_handle_vblank(dev, pipe))
			intel_check_page_flip(dev, pipe);
2008

2009
		if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2010
			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2011

2012 2013
		if (de_iir & DE_PIPE_CRC_DONE(pipe))
			i9xx_pipe_crc_irq_handler(dev, pipe);
2014

2015 2016 2017 2018 2019
		/* plane/pipes map 1:1 on ilk+ */
		if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
			intel_prepare_page_flip(dev, pipe);
			intel_finish_page_flip_plane(dev, pipe);
		}
2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038
	}

	/* check event from PCH */
	if (de_iir & DE_PCH_EVENT) {
		u32 pch_iir = I915_READ(SDEIIR);

		if (HAS_PCH_CPT(dev))
			cpt_irq_handler(dev, pch_iir);
		else
			ibx_irq_handler(dev, pch_iir);

		/* should clear PCH hotplug event before clear CPU irq */
		I915_WRITE(SDEIIR, pch_iir);
	}

	if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
		ironlake_rps_change_irq_handler(dev);
}

2039 2040 2041
static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2042
	enum pipe pipe;
2043 2044 2045 2046 2047 2048 2049 2050 2051 2052

	if (de_iir & DE_ERR_INT_IVB)
		ivb_err_int_handler(dev);

	if (de_iir & DE_AUX_CHANNEL_A_IVB)
		dp_aux_irq_handler(dev);

	if (de_iir & DE_GSE_IVB)
		intel_opregion_asle_intr(dev);

2053
	for_each_pipe(dev_priv, pipe) {
2054 2055 2056
		if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
		    intel_pipe_handle_vblank(dev, pipe))
			intel_check_page_flip(dev, pipe);
2057 2058

		/* plane/pipes map 1:1 on ilk+ */
2059 2060 2061
		if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
			intel_prepare_page_flip(dev, pipe);
			intel_finish_page_flip_plane(dev, pipe);
2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075
		}
	}

	/* check event from PCH */
	if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
		u32 pch_iir = I915_READ(SDEIIR);

		cpt_irq_handler(dev, pch_iir);

		/* clear PCH hotplug event before clear CPU irq */
		I915_WRITE(SDEIIR, pch_iir);
	}
}

2076 2077 2078 2079 2080 2081 2082 2083
/*
 * To handle irqs with the minimum potential races with fresh interrupts, we:
 * 1 - Disable Master Interrupt Control.
 * 2 - Find the source(s) of the interrupt.
 * 3 - Clear the Interrupt Identity bits (IIR).
 * 4 - Process the interrupt(s) that had bits set in the IIRs.
 * 5 - Re-enable Master Interrupt Control.
 */
2084
static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2085
{
2086
	struct drm_device *dev = arg;
2087
	struct drm_i915_private *dev_priv = dev->dev_private;
2088
	u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2089
	irqreturn_t ret = IRQ_NONE;
2090

2091 2092 2093
	if (!intel_irqs_enabled(dev_priv))
		return IRQ_NONE;

2094 2095
	/* We get interrupts on unclaimed registers, so check for this before we
	 * do any I915_{READ,WRITE}. */
2096
	intel_uncore_check_errors(dev);
2097

2098 2099 2100
	/* disable master interrupt before clearing iir  */
	de_ier = I915_READ(DEIER);
	I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2101
	POSTING_READ(DEIER);
2102

2103 2104 2105 2106 2107
	/* Disable south interrupts. We'll only write to SDEIIR once, so further
	 * interrupts will will be stored on its back queue, and then we'll be
	 * able to process them after we restore SDEIER (as soon as we restore
	 * it, we'll get an interrupt if SDEIIR still has something to process
	 * due to its back queue). */
2108 2109 2110 2111 2112
	if (!HAS_PCH_NOP(dev)) {
		sde_ier = I915_READ(SDEIER);
		I915_WRITE(SDEIER, 0);
		POSTING_READ(SDEIER);
	}
2113

2114 2115
	/* Find, clear, then process each source of interrupt */

2116
	gt_iir = I915_READ(GTIIR);
2117
	if (gt_iir) {
2118 2119
		I915_WRITE(GTIIR, gt_iir);
		ret = IRQ_HANDLED;
2120
		if (INTEL_INFO(dev)->gen >= 6)
2121
			snb_gt_irq_handler(dev, dev_priv, gt_iir);
2122 2123
		else
			ilk_gt_irq_handler(dev, dev_priv, gt_iir);
2124 2125
	}

2126 2127
	de_iir = I915_READ(DEIIR);
	if (de_iir) {
2128 2129
		I915_WRITE(DEIIR, de_iir);
		ret = IRQ_HANDLED;
2130 2131 2132 2133
		if (INTEL_INFO(dev)->gen >= 7)
			ivb_display_irq_handler(dev, de_iir);
		else
			ilk_display_irq_handler(dev, de_iir);
2134 2135
	}

2136 2137 2138 2139 2140
	if (INTEL_INFO(dev)->gen >= 6) {
		u32 pm_iir = I915_READ(GEN6_PMIIR);
		if (pm_iir) {
			I915_WRITE(GEN6_PMIIR, pm_iir);
			ret = IRQ_HANDLED;
2141
			gen6_rps_irq_handler(dev_priv, pm_iir);
2142
		}
2143
	}
2144 2145 2146

	I915_WRITE(DEIER, de_ier);
	POSTING_READ(DEIER);
2147 2148 2149 2150
	if (!HAS_PCH_NOP(dev)) {
		I915_WRITE(SDEIER, sde_ier);
		POSTING_READ(SDEIER);
	}
2151 2152 2153 2154

	return ret;
}

2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186
static void bxt_hpd_handler(struct drm_device *dev, uint32_t iir_status)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t hp_control;
	uint32_t hp_trigger;

	/* Get the status */
	hp_trigger = iir_status & BXT_DE_PORT_HOTPLUG_MASK;
	hp_control = I915_READ(BXT_HOTPLUG_CTL);

	/* Hotplug not enabled ? */
	if (!(hp_control & BXT_HOTPLUG_CTL_MASK)) {
		DRM_ERROR("Interrupt when HPD disabled\n");
		return;
	}

	DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
		hp_control & BXT_HOTPLUG_CTL_MASK);

	/* Check for HPD storm and schedule bottom half */
	intel_hpd_irq_handler(dev, hp_trigger, hp_control, hpd_bxt);

	/*
	 * FIXME: Save the hot plug status for bottom half before
	 * clearing the sticky status bits, else the status will be
	 * lost.
	 */

	/* Clear sticky bits in hpd status */
	I915_WRITE(BXT_HOTPLUG_CTL, hp_control);
}

2187 2188 2189 2190 2191 2192 2193
static irqreturn_t gen8_irq_handler(int irq, void *arg)
{
	struct drm_device *dev = arg;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 master_ctl;
	irqreturn_t ret = IRQ_NONE;
	uint32_t tmp = 0;
2194
	enum pipe pipe;
J
Jesse Barnes 已提交
2195 2196
	u32 aux_mask = GEN8_AUX_CHANNEL_A;

2197 2198 2199
	if (!intel_irqs_enabled(dev_priv))
		return IRQ_NONE;

J
Jesse Barnes 已提交
2200 2201 2202
	if (IS_GEN9(dev))
		aux_mask |=  GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
			GEN9_AUX_CHANNEL_D;
2203

2204
	master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
2205 2206 2207 2208
	master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
	if (!master_ctl)
		return IRQ_NONE;

2209
	I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
2210

2211 2212
	/* Find, clear, then process each source of interrupt */

C
Chris Wilson 已提交
2213
	ret = gen8_gt_irq_handler(dev_priv, master_ctl);
2214 2215 2216 2217 2218 2219

	if (master_ctl & GEN8_DE_MISC_IRQ) {
		tmp = I915_READ(GEN8_DE_MISC_IIR);
		if (tmp) {
			I915_WRITE(GEN8_DE_MISC_IIR, tmp);
			ret = IRQ_HANDLED;
2220 2221 2222 2223
			if (tmp & GEN8_DE_MISC_GSE)
				intel_opregion_asle_intr(dev);
			else
				DRM_ERROR("Unexpected DE Misc interrupt\n");
2224
		}
2225 2226
		else
			DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2227 2228
	}

2229 2230 2231
	if (master_ctl & GEN8_DE_PORT_IRQ) {
		tmp = I915_READ(GEN8_DE_PORT_IIR);
		if (tmp) {
2232 2233
			bool found = false;

2234 2235
			I915_WRITE(GEN8_DE_PORT_IIR, tmp);
			ret = IRQ_HANDLED;
J
Jesse Barnes 已提交
2236

2237
			if (tmp & aux_mask) {
2238
				dp_aux_irq_handler(dev);
2239 2240 2241 2242 2243 2244 2245 2246
				found = true;
			}

			if (IS_BROXTON(dev) && tmp & BXT_DE_PORT_HOTPLUG_MASK) {
				bxt_hpd_handler(dev, tmp);
				found = true;
			}

S
Shashank Sharma 已提交
2247 2248 2249 2250 2251
			if (IS_BROXTON(dev) && (tmp & BXT_DE_PORT_GMBUS)) {
				gmbus_irq_handler(dev);
				found = true;
			}

2252
			if (!found)
2253
				DRM_ERROR("Unexpected DE Port interrupt\n");
2254
		}
2255 2256
		else
			DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2257 2258
	}

2259
	for_each_pipe(dev_priv, pipe) {
2260
		uint32_t pipe_iir, flip_done = 0, fault_errors = 0;
2261

2262 2263
		if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
			continue;
2264

2265 2266 2267 2268
		pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
		if (pipe_iir) {
			ret = IRQ_HANDLED;
			I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2269

2270 2271 2272
			if (pipe_iir & GEN8_PIPE_VBLANK &&
			    intel_pipe_handle_vblank(dev, pipe))
				intel_check_page_flip(dev, pipe);
2273

2274 2275 2276 2277 2278 2279
			if (IS_GEN9(dev))
				flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE;
			else
				flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE;

			if (flip_done) {
2280 2281 2282 2283 2284 2285 2286
				intel_prepare_page_flip(dev, pipe);
				intel_finish_page_flip_plane(dev, pipe);
			}

			if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
				hsw_pipe_crc_irq_handler(dev, pipe);

2287 2288 2289
			if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN)
				intel_cpu_fifo_underrun_irq_handler(dev_priv,
								    pipe);
2290

2291 2292 2293 2294 2295 2296 2297

			if (IS_GEN9(dev))
				fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
			else
				fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS;

			if (fault_errors)
2298 2299 2300
				DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
					  pipe_name(pipe),
					  pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2301
		} else
2302 2303 2304
			DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
	}

2305 2306
	if (HAS_PCH_SPLIT(dev) && !HAS_PCH_NOP(dev) &&
	    master_ctl & GEN8_DE_PCH_IRQ) {
2307 2308 2309 2310 2311 2312 2313 2314 2315
		/*
		 * FIXME(BDW): Assume for now that the new interrupt handling
		 * scheme also closed the SDE interrupt handling race we've seen
		 * on older pch-split platforms. But this needs testing.
		 */
		u32 pch_iir = I915_READ(SDEIIR);
		if (pch_iir) {
			I915_WRITE(SDEIIR, pch_iir);
			ret = IRQ_HANDLED;
2316 2317 2318 2319
			cpt_irq_handler(dev, pch_iir);
		} else
			DRM_ERROR("The master control interrupt lied (SDE)!\n");

2320 2321
	}

2322 2323
	I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
	POSTING_READ_FW(GEN8_MASTER_IRQ);
2324 2325 2326 2327

	return ret;
}

2328 2329 2330
static void i915_error_wake_up(struct drm_i915_private *dev_priv,
			       bool reset_completed)
{
2331
	struct intel_engine_cs *ring;
2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355
	int i;

	/*
	 * Notify all waiters for GPU completion events that reset state has
	 * been changed, and that they need to restart their wait after
	 * checking for potential errors (and bail out to drop locks if there is
	 * a gpu reset pending so that i915_error_work_func can acquire them).
	 */

	/* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
	for_each_ring(ring, dev_priv, i)
		wake_up_all(&ring->irq_queue);

	/* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
	wake_up_all(&dev_priv->pending_flip_queue);

	/*
	 * Signal tasks blocked in i915_gem_wait_for_error that the pending
	 * reset state is cleared.
	 */
	if (reset_completed)
		wake_up_all(&dev_priv->gpu_error.reset_queue);
}

2356
/**
2357
 * i915_reset_and_wakeup - do process context error handling work
2358 2359 2360 2361
 *
 * Fire an error uevent so userspace can see that a hang or error
 * was detected.
 */
2362
static void i915_reset_and_wakeup(struct drm_device *dev)
2363
{
2364 2365
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct i915_gpu_error *error = &dev_priv->gpu_error;
2366 2367 2368
	char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
	char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
	char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2369
	int ret;
2370

2371
	kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2372

2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383
	/*
	 * Note that there's only one work item which does gpu resets, so we
	 * need not worry about concurrent gpu resets potentially incrementing
	 * error->reset_counter twice. We only need to take care of another
	 * racing irq/hangcheck declaring the gpu dead for a second time. A
	 * quick check for that is good enough: schedule_work ensures the
	 * correct ordering between hang detection and this work item, and since
	 * the reset in-progress bit is only ever set by code outside of this
	 * work we don't need to worry about any other races.
	 */
	if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2384
		DRM_DEBUG_DRIVER("resetting chip\n");
2385
		kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2386
				   reset_event);
2387

2388 2389 2390 2391 2392 2393 2394 2395
		/*
		 * In most cases it's guaranteed that we get here with an RPM
		 * reference held, for example because there is a pending GPU
		 * request that won't finish until the reset is done. This
		 * isn't the case at least when we get here by doing a
		 * simulated reset via debugs, so get an RPM reference.
		 */
		intel_runtime_pm_get(dev_priv);
2396 2397 2398

		intel_prepare_reset(dev);

2399 2400 2401 2402 2403 2404
		/*
		 * All state reset _must_ be completed before we update the
		 * reset counter, for otherwise waiters might miss the reset
		 * pending state and not properly drop locks, resulting in
		 * deadlocks with the reset work.
		 */
2405 2406
		ret = i915_reset(dev);

2407
		intel_finish_reset(dev);
2408

2409 2410
		intel_runtime_pm_put(dev_priv);

2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421
		if (ret == 0) {
			/*
			 * After all the gem state is reset, increment the reset
			 * counter and wake up everyone waiting for the reset to
			 * complete.
			 *
			 * Since unlock operations are a one-sided barrier only,
			 * we need to insert a barrier here to order any seqno
			 * updates before
			 * the counter increment.
			 */
2422
			smp_mb__before_atomic();
2423 2424
			atomic_inc(&dev_priv->gpu_error.reset_counter);

2425
			kobject_uevent_env(&dev->primary->kdev->kobj,
2426
					   KOBJ_CHANGE, reset_done_event);
2427
		} else {
M
Mika Kuoppala 已提交
2428
			atomic_set_mask(I915_WEDGED, &error->reset_counter);
2429
		}
2430

2431 2432 2433 2434 2435
		/*
		 * Note: The wake_up also serves as a memory barrier so that
		 * waiters see the update value of the reset counter atomic_t.
		 */
		i915_error_wake_up(dev_priv, true);
2436
	}
2437 2438
}

2439
static void i915_report_and_clear_eir(struct drm_device *dev)
2440 2441
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2442
	uint32_t instdone[I915_NUM_INSTDONE_REG];
2443
	u32 eir = I915_READ(EIR);
2444
	int pipe, i;
2445

2446 2447
	if (!eir)
		return;
2448

2449
	pr_err("render error detected, EIR: 0x%08x\n", eir);
2450

2451 2452
	i915_get_extra_instdone(dev, instdone);

2453 2454 2455 2456
	if (IS_G4X(dev)) {
		if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
			u32 ipeir = I915_READ(IPEIR_I965);

2457 2458
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2459 2460
			for (i = 0; i < ARRAY_SIZE(instdone); i++)
				pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2461 2462
			pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2463
			I915_WRITE(IPEIR_I965, ipeir);
2464
			POSTING_READ(IPEIR_I965);
2465 2466 2467
		}
		if (eir & GM45_ERROR_PAGE_TABLE) {
			u32 pgtbl_err = I915_READ(PGTBL_ER);
2468 2469
			pr_err("page table error\n");
			pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2470
			I915_WRITE(PGTBL_ER, pgtbl_err);
2471
			POSTING_READ(PGTBL_ER);
2472 2473 2474
		}
	}

2475
	if (!IS_GEN2(dev)) {
2476 2477
		if (eir & I915_ERROR_PAGE_TABLE) {
			u32 pgtbl_err = I915_READ(PGTBL_ER);
2478 2479
			pr_err("page table error\n");
			pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2480
			I915_WRITE(PGTBL_ER, pgtbl_err);
2481
			POSTING_READ(PGTBL_ER);
2482 2483 2484 2485
		}
	}

	if (eir & I915_ERROR_MEMORY_REFRESH) {
2486
		pr_err("memory refresh error:\n");
2487
		for_each_pipe(dev_priv, pipe)
2488
			pr_err("pipe %c stat: 0x%08x\n",
2489
			       pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2490 2491 2492
		/* pipestat has already been acked */
	}
	if (eir & I915_ERROR_INSTRUCTION) {
2493 2494
		pr_err("instruction error\n");
		pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
2495 2496
		for (i = 0; i < ARRAY_SIZE(instdone); i++)
			pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2497
		if (INTEL_INFO(dev)->gen < 4) {
2498 2499
			u32 ipeir = I915_READ(IPEIR);

2500 2501 2502
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
2503
			I915_WRITE(IPEIR, ipeir);
2504
			POSTING_READ(IPEIR);
2505 2506 2507
		} else {
			u32 ipeir = I915_READ(IPEIR_I965);

2508 2509 2510 2511
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
			pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2512
			I915_WRITE(IPEIR_I965, ipeir);
2513
			POSTING_READ(IPEIR_I965);
2514 2515 2516 2517
		}
	}

	I915_WRITE(EIR, eir);
2518
	POSTING_READ(EIR);
2519 2520 2521 2522 2523 2524 2525 2526 2527 2528
	eir = I915_READ(EIR);
	if (eir) {
		/*
		 * some errors might have become stuck,
		 * mask them.
		 */
		DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
		I915_WRITE(EMR, I915_READ(EMR) | eir);
		I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
	}
2529 2530 2531
}

/**
2532
 * i915_handle_error - handle a gpu error
2533 2534
 * @dev: drm device
 *
2535
 * Do some basic checking of regsiter state at error time and
2536 2537 2538 2539 2540
 * dump it to the syslog.  Also call i915_capture_error_state() to make
 * sure we get a record and make it available in debugfs.  Fire a uevent
 * so userspace knows something bad happened (should trigger collection
 * of a ring dump etc.).
 */
2541 2542
void i915_handle_error(struct drm_device *dev, bool wedged,
		       const char *fmt, ...)
2543 2544
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2545 2546
	va_list args;
	char error_msg[80];
2547

2548 2549 2550 2551 2552
	va_start(args, fmt);
	vscnprintf(error_msg, sizeof(error_msg), fmt, args);
	va_end(args);

	i915_capture_error_state(dev, wedged, error_msg);
2553
	i915_report_and_clear_eir(dev);
2554

2555
	if (wedged) {
2556 2557
		atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
				&dev_priv->gpu_error.reset_counter);
2558

2559
		/*
2560 2561 2562
		 * Wakeup waiting processes so that the reset function
		 * i915_reset_and_wakeup doesn't deadlock trying to grab
		 * various locks. By bumping the reset counter first, the woken
2563 2564 2565 2566 2567 2568 2569 2570
		 * processes will see a reset in progress and back off,
		 * releasing their locks and then wait for the reset completion.
		 * We must do this for _all_ gpu waiters that might hold locks
		 * that the reset work needs to acquire.
		 *
		 * Note: The wake_up serves as the required memory barrier to
		 * ensure that the waiters see the updated value of the reset
		 * counter atomic_t.
2571
		 */
2572
		i915_error_wake_up(dev_priv, false);
2573 2574
	}

2575
	i915_reset_and_wakeup(dev);
2576 2577
}

2578 2579 2580
/* Called from drm generic code, passed 'crtc' which
 * we use as a pipe index
 */
2581
static int i915_enable_vblank(struct drm_device *dev, int pipe)
2582
{
2583
	struct drm_i915_private *dev_priv = dev->dev_private;
2584
	unsigned long irqflags;
2585

2586
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2587
	if (INTEL_INFO(dev)->gen >= 4)
2588
		i915_enable_pipestat(dev_priv, pipe,
2589
				     PIPE_START_VBLANK_INTERRUPT_STATUS);
2590
	else
2591
		i915_enable_pipestat(dev_priv, pipe,
2592
				     PIPE_VBLANK_INTERRUPT_STATUS);
2593
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2594

2595 2596 2597
	return 0;
}

2598
static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2599
{
2600
	struct drm_i915_private *dev_priv = dev->dev_private;
2601
	unsigned long irqflags;
2602
	uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2603
						     DE_PIPE_VBLANK(pipe);
2604 2605

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2606
	ironlake_enable_display_irq(dev_priv, bit);
2607 2608 2609 2610 2611
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

	return 0;
}

J
Jesse Barnes 已提交
2612 2613
static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
{
2614
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
2615 2616 2617
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2618
	i915_enable_pipestat(dev_priv, pipe,
2619
			     PIPE_START_VBLANK_INTERRUPT_STATUS);
J
Jesse Barnes 已提交
2620 2621 2622 2623 2624
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

	return 0;
}

2625 2626 2627 2628 2629 2630
static int gen8_enable_vblank(struct drm_device *dev, int pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2631 2632 2633
	dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
	I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
	POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2634 2635 2636 2637
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
	return 0;
}

2638 2639 2640
/* Called from drm generic code, passed 'crtc' which
 * we use as a pipe index
 */
2641
static void i915_disable_vblank(struct drm_device *dev, int pipe)
2642
{
2643
	struct drm_i915_private *dev_priv = dev->dev_private;
2644
	unsigned long irqflags;
2645

2646
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2647
	i915_disable_pipestat(dev_priv, pipe,
2648 2649
			      PIPE_VBLANK_INTERRUPT_STATUS |
			      PIPE_START_VBLANK_INTERRUPT_STATUS);
2650 2651 2652
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

2653
static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2654
{
2655
	struct drm_i915_private *dev_priv = dev->dev_private;
2656
	unsigned long irqflags;
2657
	uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2658
						     DE_PIPE_VBLANK(pipe);
2659 2660

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2661
	ironlake_disable_display_irq(dev_priv, bit);
2662 2663 2664
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

J
Jesse Barnes 已提交
2665 2666
static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
{
2667
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
2668 2669 2670
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2671
	i915_disable_pipestat(dev_priv, pipe,
2672
			      PIPE_START_VBLANK_INTERRUPT_STATUS);
J
Jesse Barnes 已提交
2673 2674 2675
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

2676 2677 2678 2679 2680 2681
static void gen8_disable_vblank(struct drm_device *dev, int pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2682 2683 2684
	dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
	I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
	POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2685 2686 2687
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

2688 2689
static struct drm_i915_gem_request *
ring_last_request(struct intel_engine_cs *ring)
2690
{
2691
	return list_entry(ring->request_list.prev,
2692
			  struct drm_i915_gem_request, list);
2693 2694
}

2695
static bool
2696
ring_idle(struct intel_engine_cs *ring)
2697 2698
{
	return (list_empty(&ring->request_list) ||
2699
		i915_gem_request_completed(ring_last_request(ring), false));
B
Ben Gamari 已提交
2700 2701
}

2702 2703 2704 2705
static bool
ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
{
	if (INTEL_INFO(dev)->gen >= 8) {
2706
		return (ipehr >> 23) == 0x1c;
2707 2708 2709 2710 2711 2712 2713
	} else {
		ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
		return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
				 MI_SEMAPHORE_REGISTER);
	}
}

2714
static struct intel_engine_cs *
2715
semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset)
2716 2717
{
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
2718
	struct intel_engine_cs *signaller;
2719 2720 2721
	int i;

	if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
2722 2723 2724 2725 2726 2727 2728
		for_each_ring(signaller, dev_priv, i) {
			if (ring == signaller)
				continue;

			if (offset == signaller->semaphore.signal_ggtt[ring->id])
				return signaller;
		}
2729 2730 2731 2732 2733 2734 2735
	} else {
		u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;

		for_each_ring(signaller, dev_priv, i) {
			if(ring == signaller)
				continue;

2736
			if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
2737 2738 2739 2740
				return signaller;
		}
	}

2741 2742
	DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
		  ring->id, ipehr, offset);
2743 2744 2745 2746

	return NULL;
}

2747 2748
static struct intel_engine_cs *
semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
2749 2750
{
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
2751
	u32 cmd, ipehr, head;
2752 2753
	u64 offset = 0;
	int i, backwards;
2754 2755

	ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2756
	if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
2757
		return NULL;
2758

2759 2760 2761
	/*
	 * HEAD is likely pointing to the dword after the actual command,
	 * so scan backwards until we find the MBOX. But limit it to just 3
2762 2763
	 * or 4 dwords depending on the semaphore wait command size.
	 * Note that we don't care about ACTHD here since that might
2764 2765
	 * point at at batch, and semaphores are always emitted into the
	 * ringbuffer itself.
2766
	 */
2767
	head = I915_READ_HEAD(ring) & HEAD_ADDR;
2768
	backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4;
2769

2770
	for (i = backwards; i; --i) {
2771 2772 2773 2774 2775
		/*
		 * Be paranoid and presume the hw has gone off into the wild -
		 * our ring is smaller than what the hardware (and hence
		 * HEAD_ADDR) allows. Also handles wrap-around.
		 */
2776
		head &= ring->buffer->size - 1;
2777 2778

		/* This here seems to blow up */
2779
		cmd = ioread32(ring->buffer->virtual_start + head);
2780 2781 2782
		if (cmd == ipehr)
			break;

2783 2784
		head -= 4;
	}
2785

2786 2787
	if (!i)
		return NULL;
2788

2789
	*seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
2790 2791 2792 2793 2794 2795
	if (INTEL_INFO(ring->dev)->gen >= 8) {
		offset = ioread32(ring->buffer->virtual_start + head + 12);
		offset <<= 32;
		offset = ioread32(ring->buffer->virtual_start + head + 8);
	}
	return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
2796 2797
}

2798
static int semaphore_passed(struct intel_engine_cs *ring)
2799 2800
{
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
2801
	struct intel_engine_cs *signaller;
2802
	u32 seqno;
2803

2804
	ring->hangcheck.deadlock++;
2805 2806

	signaller = semaphore_waits_for(ring, &seqno);
2807 2808 2809 2810 2811
	if (signaller == NULL)
		return -1;

	/* Prevent pathological recursion due to driver bugs */
	if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
2812 2813
		return -1;

2814 2815 2816
	if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
		return 1;

2817 2818 2819
	/* cursory check for an unkickable deadlock */
	if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
	    semaphore_passed(signaller) < 0)
2820 2821 2822
		return -1;

	return 0;
2823 2824 2825 2826
}

static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
{
2827
	struct intel_engine_cs *ring;
2828 2829 2830
	int i;

	for_each_ring(ring, dev_priv, i)
2831
		ring->hangcheck.deadlock = 0;
2832 2833
}

2834
static enum intel_ring_hangcheck_action
2835
ring_stuck(struct intel_engine_cs *ring, u64 acthd)
2836 2837 2838
{
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2839 2840
	u32 tmp;

2841 2842 2843 2844 2845 2846 2847 2848
	if (acthd != ring->hangcheck.acthd) {
		if (acthd > ring->hangcheck.max_acthd) {
			ring->hangcheck.max_acthd = acthd;
			return HANGCHECK_ACTIVE;
		}

		return HANGCHECK_ACTIVE_LOOP;
	}
2849

2850
	if (IS_GEN2(dev))
2851
		return HANGCHECK_HUNG;
2852 2853 2854 2855 2856 2857 2858

	/* Is the chip hanging on a WAIT_FOR_EVENT?
	 * If so we can simply poke the RB_WAIT bit
	 * and break the hang. This should work on
	 * all but the second generation chipsets.
	 */
	tmp = I915_READ_CTL(ring);
2859
	if (tmp & RING_WAIT) {
2860 2861 2862
		i915_handle_error(dev, false,
				  "Kicking stuck wait on %s",
				  ring->name);
2863
		I915_WRITE_CTL(ring, tmp);
2864
		return HANGCHECK_KICK;
2865 2866 2867 2868 2869
	}

	if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
		switch (semaphore_passed(ring)) {
		default:
2870
			return HANGCHECK_HUNG;
2871
		case 1:
2872 2873 2874
			i915_handle_error(dev, false,
					  "Kicking stuck semaphore on %s",
					  ring->name);
2875
			I915_WRITE_CTL(ring, tmp);
2876
			return HANGCHECK_KICK;
2877
		case 0:
2878
			return HANGCHECK_WAIT;
2879
		}
2880
	}
2881

2882
	return HANGCHECK_HUNG;
2883 2884
}

2885
/*
B
Ben Gamari 已提交
2886
 * This is called when the chip hasn't reported back with completed
2887 2888 2889 2890 2891
 * batchbuffers in a long time. We keep track per ring seqno progress and
 * if there are no progress, hangcheck score for that ring is increased.
 * Further, acthd is inspected to see if the ring is stuck. On stuck case
 * we kick the ring. If we see no progress on three subsequent calls
 * we assume chip is wedged and try to fix it by resetting the chip.
B
Ben Gamari 已提交
2892
 */
2893
static void i915_hangcheck_elapsed(struct work_struct *work)
B
Ben Gamari 已提交
2894
{
2895 2896 2897 2898
	struct drm_i915_private *dev_priv =
		container_of(work, typeof(*dev_priv),
			     gpu_error.hangcheck_work.work);
	struct drm_device *dev = dev_priv->dev;
2899
	struct intel_engine_cs *ring;
2900
	int i;
2901
	int busy_count = 0, rings_hung = 0;
2902 2903 2904 2905
	bool stuck[I915_NUM_RINGS] = { 0 };
#define BUSY 1
#define KICK 5
#define HUNG 20
2906

2907
	if (!i915.enable_hangcheck)
2908 2909
		return;

2910
	for_each_ring(ring, dev_priv, i) {
2911 2912
		u64 acthd;
		u32 seqno;
2913
		bool busy = true;
2914

2915 2916
		semaphore_clear_deadlocks(dev_priv);

2917 2918
		seqno = ring->get_seqno(ring, false);
		acthd = intel_ring_get_active_head(ring);
2919

2920
		if (ring->hangcheck.seqno == seqno) {
2921
			if (ring_idle(ring)) {
2922 2923
				ring->hangcheck.action = HANGCHECK_IDLE;

2924 2925
				if (waitqueue_active(&ring->irq_queue)) {
					/* Issue a wake-up to catch stuck h/w. */
2926
					if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2927 2928 2929 2930 2931 2932
						if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
							DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
								  ring->name);
						else
							DRM_INFO("Fake missed irq on %s\n",
								 ring->name);
2933 2934 2935 2936
						wake_up_all(&ring->irq_queue);
					}
					/* Safeguard against driver failure */
					ring->hangcheck.score += BUSY;
2937 2938
				} else
					busy = false;
2939
			} else {
2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954
				/* We always increment the hangcheck score
				 * if the ring is busy and still processing
				 * the same request, so that no single request
				 * can run indefinitely (such as a chain of
				 * batches). The only time we do not increment
				 * the hangcheck score on this ring, if this
				 * ring is in a legitimate wait for another
				 * ring. In that case the waiting ring is a
				 * victim and we want to be sure we catch the
				 * right culprit. Then every time we do kick
				 * the ring, add a small increment to the
				 * score so that we can catch a batch that is
				 * being repeatedly kicked and so responsible
				 * for stalling the machine.
				 */
2955 2956 2957 2958
				ring->hangcheck.action = ring_stuck(ring,
								    acthd);

				switch (ring->hangcheck.action) {
2959
				case HANGCHECK_IDLE:
2960 2961
				case HANGCHECK_WAIT:
				case HANGCHECK_ACTIVE:
2962 2963
					break;
				case HANGCHECK_ACTIVE_LOOP:
2964
					ring->hangcheck.score += BUSY;
2965
					break;
2966
				case HANGCHECK_KICK:
2967
					ring->hangcheck.score += KICK;
2968
					break;
2969
				case HANGCHECK_HUNG:
2970
					ring->hangcheck.score += HUNG;
2971 2972 2973
					stuck[i] = true;
					break;
				}
2974
			}
2975
		} else {
2976 2977
			ring->hangcheck.action = HANGCHECK_ACTIVE;

2978 2979 2980 2981 2982
			/* Gradually reduce the count so that we catch DoS
			 * attempts across multiple batches.
			 */
			if (ring->hangcheck.score > 0)
				ring->hangcheck.score--;
2983 2984

			ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0;
2985 2986
		}

2987 2988
		ring->hangcheck.seqno = seqno;
		ring->hangcheck.acthd = acthd;
2989
		busy_count += busy;
2990
	}
2991

2992
	for_each_ring(ring, dev_priv, i) {
2993
		if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
2994 2995 2996
			DRM_INFO("%s on %s\n",
				 stuck[i] ? "stuck" : "no progress",
				 ring->name);
2997
			rings_hung++;
2998 2999 3000
		}
	}

3001
	if (rings_hung)
3002
		return i915_handle_error(dev, true, "Ring hung");
B
Ben Gamari 已提交
3003

3004 3005 3006
	if (busy_count)
		/* Reset timer case chip hangs without another request
		 * being added */
3007 3008 3009 3010 3011
		i915_queue_hangcheck(dev);
}

void i915_queue_hangcheck(struct drm_device *dev)
{
3012
	struct i915_gpu_error *e = &to_i915(dev)->gpu_error;
3013

3014
	if (!i915.enable_hangcheck)
3015 3016
		return;

3017 3018 3019 3020 3021 3022 3023
	/* Don't continually defer the hangcheck so that it is always run at
	 * least once after work has been scheduled on any ring. Otherwise,
	 * we will ignore a hung ring if a second ring is kept busy.
	 */

	queue_delayed_work(e->hangcheck_wq, &e->hangcheck_work,
			   round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES));
B
Ben Gamari 已提交
3024 3025
}

3026
static void ibx_irq_reset(struct drm_device *dev)
P
Paulo Zanoni 已提交
3027 3028 3029 3030 3031 3032
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (HAS_PCH_NOP(dev))
		return;

3033
	GEN5_IRQ_RESET(SDE);
3034 3035 3036

	if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
		I915_WRITE(SERR_INT, 0xffffffff);
P
Paulo Zanoni 已提交
3037
}
3038

P
Paulo Zanoni 已提交
3039 3040 3041 3042 3043 3044 3045 3046 3047 3048 3049 3050 3051 3052 3053 3054
/*
 * SDEIER is also touched by the interrupt handler to work around missed PCH
 * interrupts. Hence we can't update it after the interrupt handler is enabled -
 * instead we unconditionally enable all PCH interrupt sources here, but then
 * only unmask them as needed with SDEIMR.
 *
 * This function needs to be called before interrupts are enabled.
 */
static void ibx_irq_pre_postinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (HAS_PCH_NOP(dev))
		return;

	WARN_ON(I915_READ(SDEIER) != 0);
P
Paulo Zanoni 已提交
3055 3056 3057 3058
	I915_WRITE(SDEIER, 0xffffffff);
	POSTING_READ(SDEIER);
}

3059
static void gen5_gt_irq_reset(struct drm_device *dev)
3060 3061 3062
{
	struct drm_i915_private *dev_priv = dev->dev_private;

3063
	GEN5_IRQ_RESET(GT);
P
Paulo Zanoni 已提交
3064
	if (INTEL_INFO(dev)->gen >= 6)
3065
		GEN5_IRQ_RESET(GEN6_PM);
3066 3067
}

L
Linus Torvalds 已提交
3068 3069
/* drm_dma.h hooks
*/
P
Paulo Zanoni 已提交
3070
static void ironlake_irq_reset(struct drm_device *dev)
3071
{
3072
	struct drm_i915_private *dev_priv = dev->dev_private;
3073

3074
	I915_WRITE(HWSTAM, 0xffffffff);
3075

3076
	GEN5_IRQ_RESET(DE);
3077 3078
	if (IS_GEN7(dev))
		I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3079

3080
	gen5_gt_irq_reset(dev);
3081

3082
	ibx_irq_reset(dev);
3083
}
3084

3085 3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097
static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
{
	enum pipe pipe;

	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));

	for_each_pipe(dev_priv, pipe)
		I915_WRITE(PIPESTAT(pipe), 0xffff);

	GEN5_IRQ_RESET(VLV_);
}

J
Jesse Barnes 已提交
3098 3099
static void valleyview_irq_preinstall(struct drm_device *dev)
{
3100
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
3101 3102 3103 3104 3105 3106 3107

	/* VLV magic */
	I915_WRITE(VLV_IMR, 0);
	I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
	I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
	I915_WRITE(RING_IMR(BLT_RING_BASE), 0);

3108
	gen5_gt_irq_reset(dev);
J
Jesse Barnes 已提交
3109

3110
	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
J
Jesse Barnes 已提交
3111

3112
	vlv_display_irq_reset(dev_priv);
J
Jesse Barnes 已提交
3113 3114
}

3115 3116 3117 3118 3119 3120 3121 3122
static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
{
	GEN8_IRQ_RESET_NDX(GT, 0);
	GEN8_IRQ_RESET_NDX(GT, 1);
	GEN8_IRQ_RESET_NDX(GT, 2);
	GEN8_IRQ_RESET_NDX(GT, 3);
}

P
Paulo Zanoni 已提交
3123
static void gen8_irq_reset(struct drm_device *dev)
3124 3125 3126 3127 3128 3129 3130
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int pipe;

	I915_WRITE(GEN8_MASTER_IRQ, 0);
	POSTING_READ(GEN8_MASTER_IRQ);

3131
	gen8_gt_irq_reset(dev_priv);
3132

3133
	for_each_pipe(dev_priv, pipe)
3134 3135
		if (intel_display_power_is_enabled(dev_priv,
						   POWER_DOMAIN_PIPE(pipe)))
3136
			GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3137

3138 3139 3140
	GEN5_IRQ_RESET(GEN8_DE_PORT_);
	GEN5_IRQ_RESET(GEN8_DE_MISC_);
	GEN5_IRQ_RESET(GEN8_PCU_);
3141

3142 3143
	if (HAS_PCH_SPLIT(dev))
		ibx_irq_reset(dev);
3144
}
3145

3146 3147
void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
				     unsigned int pipe_mask)
3148
{
3149
	uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3150

3151
	spin_lock_irq(&dev_priv->irq_lock);
3152 3153 3154 3155
	if (pipe_mask & 1 << PIPE_A)
		GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_A,
				  dev_priv->de_irq_mask[PIPE_A],
				  ~dev_priv->de_irq_mask[PIPE_A] | extra_ier);
3156 3157 3158 3159 3160 3161 3162 3163
	if (pipe_mask & 1 << PIPE_B)
		GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B,
				  dev_priv->de_irq_mask[PIPE_B],
				  ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
	if (pipe_mask & 1 << PIPE_C)
		GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C,
				  dev_priv->de_irq_mask[PIPE_C],
				  ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
3164
	spin_unlock_irq(&dev_priv->irq_lock);
3165 3166
}

3167 3168 3169 3170 3171 3172 3173
static void cherryview_irq_preinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	I915_WRITE(GEN8_MASTER_IRQ, 0);
	POSTING_READ(GEN8_MASTER_IRQ);

3174
	gen8_gt_irq_reset(dev_priv);
3175 3176 3177 3178 3179

	GEN5_IRQ_RESET(GEN8_PCU_);

	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);

3180
	vlv_display_irq_reset(dev_priv);
3181 3182
}

3183
static void ibx_hpd_irq_setup(struct drm_device *dev)
3184
{
3185
	struct drm_i915_private *dev_priv = dev->dev_private;
3186
	struct intel_encoder *intel_encoder;
3187
	u32 hotplug_irqs, hotplug, enabled_irqs = 0;
3188 3189

	if (HAS_PCH_IBX(dev)) {
3190
		hotplug_irqs = SDE_HOTPLUG_MASK;
3191
		for_each_intel_encoder(dev, intel_encoder)
3192
			if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3193
				enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
3194
	} else {
3195
		hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3196
		for_each_intel_encoder(dev, intel_encoder)
3197
			if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3198
				enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
3199
	}
3200

3201
	ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3202 3203 3204 3205 3206 3207 3208

	/*
	 * Enable digital hotplug on the PCH, and configure the DP short pulse
	 * duration to 2ms (which is the minimum in the Display Port spec)
	 *
	 * This register is the same on all known PCH chips.
	 */
3209 3210 3211 3212 3213 3214 3215 3216
	hotplug = I915_READ(PCH_PORT_HOTPLUG);
	hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
	hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
	hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
	hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
}

3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247 3248 3249 3250 3251 3252
static void bxt_hpd_irq_setup(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_encoder *intel_encoder;
	u32 hotplug_port = 0;
	u32 hotplug_ctrl;

	/* Now, enable HPD */
	for_each_intel_encoder(dev, intel_encoder) {
		if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark
				== HPD_ENABLED)
			hotplug_port |= hpd_bxt[intel_encoder->hpd_pin];
	}

	/* Mask all HPD control bits */
	hotplug_ctrl = I915_READ(BXT_HOTPLUG_CTL) & ~BXT_HOTPLUG_CTL_MASK;

	/* Enable requested port in hotplug control */
	/* TODO: implement (short) HPD support on port A */
	WARN_ON_ONCE(hotplug_port & BXT_DE_PORT_HP_DDIA);
	if (hotplug_port & BXT_DE_PORT_HP_DDIB)
		hotplug_ctrl |= BXT_DDIB_HPD_ENABLE;
	if (hotplug_port & BXT_DE_PORT_HP_DDIC)
		hotplug_ctrl |= BXT_DDIC_HPD_ENABLE;
	I915_WRITE(BXT_HOTPLUG_CTL, hotplug_ctrl);

	/* Unmask DDI hotplug in IMR */
	hotplug_ctrl = I915_READ(GEN8_DE_PORT_IMR) & ~hotplug_port;
	I915_WRITE(GEN8_DE_PORT_IMR, hotplug_ctrl);

	/* Enable DDI hotplug in IER */
	hotplug_ctrl = I915_READ(GEN8_DE_PORT_IER) | hotplug_port;
	I915_WRITE(GEN8_DE_PORT_IER, hotplug_ctrl);
	POSTING_READ(GEN8_DE_PORT_IER);
}

P
Paulo Zanoni 已提交
3253 3254
static void ibx_irq_postinstall(struct drm_device *dev)
{
3255
	struct drm_i915_private *dev_priv = dev->dev_private;
3256
	u32 mask;
3257

D
Daniel Vetter 已提交
3258 3259 3260
	if (HAS_PCH_NOP(dev))
		return;

3261
	if (HAS_PCH_IBX(dev))
3262
		mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3263
	else
3264
		mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3265

3266
	GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
P
Paulo Zanoni 已提交
3267 3268 3269
	I915_WRITE(SDEIMR, ~mask);
}

3270 3271 3272 3273 3274 3275 3276 3277
static void gen5_gt_irq_postinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pm_irqs, gt_irqs;

	pm_irqs = gt_irqs = 0;

	dev_priv->gt_irq_mask = ~0;
3278
	if (HAS_L3_DPF(dev)) {
3279
		/* L3 parity interrupt is always unmasked. */
3280 3281
		dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
		gt_irqs |= GT_PARITY_ERROR(dev);
3282 3283 3284 3285 3286 3287 3288 3289 3290 3291
	}

	gt_irqs |= GT_RENDER_USER_INTERRUPT;
	if (IS_GEN5(dev)) {
		gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
			   ILK_BSD_USER_INTERRUPT;
	} else {
		gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
	}

P
Paulo Zanoni 已提交
3292
	GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3293 3294

	if (INTEL_INFO(dev)->gen >= 6) {
3295 3296 3297 3298
		/*
		 * RPS interrupts will get enabled/disabled on demand when RPS
		 * itself is enabled/disabled.
		 */
3299 3300 3301
		if (HAS_VEBOX(dev))
			pm_irqs |= PM_VEBOX_USER_INTERRUPT;

3302
		dev_priv->pm_irq_mask = 0xffffffff;
P
Paulo Zanoni 已提交
3303
		GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3304 3305 3306
	}
}

3307
static int ironlake_irq_postinstall(struct drm_device *dev)
3308
{
3309
	struct drm_i915_private *dev_priv = dev->dev_private;
3310 3311 3312 3313 3314 3315
	u32 display_mask, extra_mask;

	if (INTEL_INFO(dev)->gen >= 7) {
		display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
				DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
				DE_PLANEB_FLIP_DONE_IVB |
3316
				DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3317
		extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3318
			      DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
3319 3320 3321
	} else {
		display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
				DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3322 3323 3324
				DE_AUX_CHANNEL_A |
				DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
				DE_POISON);
3325 3326
		extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
				DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
3327
	}
3328

3329
	dev_priv->irq_mask = ~display_mask;
3330

3331 3332
	I915_WRITE(HWSTAM, 0xeffe);

P
Paulo Zanoni 已提交
3333 3334
	ibx_irq_pre_postinstall(dev);

P
Paulo Zanoni 已提交
3335
	GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3336

3337
	gen5_gt_irq_postinstall(dev);
3338

P
Paulo Zanoni 已提交
3339
	ibx_irq_postinstall(dev);
3340

3341
	if (IS_IRONLAKE_M(dev)) {
3342 3343 3344
		/* Enable PCU event interrupts
		 *
		 * spinlocking not required here for correctness since interrupt
3345 3346
		 * setup is guaranteed to run in single-threaded context. But we
		 * need it to make the assert_spin_locked happy. */
3347
		spin_lock_irq(&dev_priv->irq_lock);
3348
		ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
3349
		spin_unlock_irq(&dev_priv->irq_lock);
3350 3351
	}

3352 3353 3354
	return 0;
}

3355 3356 3357 3358
static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
{
	u32 pipestat_mask;
	u32 iir_mask;
3359
	enum pipe pipe;
3360 3361 3362 3363

	pipestat_mask = PIPESTAT_INT_STATUS_MASK |
			PIPE_FIFO_UNDERRUN_STATUS;

3364 3365
	for_each_pipe(dev_priv, pipe)
		I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3366 3367 3368 3369 3370
	POSTING_READ(PIPESTAT(PIPE_A));

	pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
			PIPE_CRC_DONE_INTERRUPT_STATUS;

3371 3372 3373
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
	for_each_pipe(dev_priv, pipe)
		      i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3374 3375 3376 3377

	iir_mask = I915_DISPLAY_PORT_INTERRUPT |
		   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3378 3379
	if (IS_CHERRYVIEW(dev_priv))
		iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3380 3381 3382 3383 3384
	dev_priv->irq_mask &= ~iir_mask;

	I915_WRITE(VLV_IIR, iir_mask);
	I915_WRITE(VLV_IIR, iir_mask);
	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3385 3386
	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
	POSTING_READ(VLV_IMR);
3387 3388 3389 3390 3391 3392
}

static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
{
	u32 pipestat_mask;
	u32 iir_mask;
3393
	enum pipe pipe;
3394 3395 3396

	iir_mask = I915_DISPLAY_PORT_INTERRUPT |
		   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3397
		   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3398 3399
	if (IS_CHERRYVIEW(dev_priv))
		iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3400 3401 3402

	dev_priv->irq_mask |= iir_mask;
	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3403
	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3404 3405 3406 3407 3408 3409 3410
	I915_WRITE(VLV_IIR, iir_mask);
	I915_WRITE(VLV_IIR, iir_mask);
	POSTING_READ(VLV_IIR);

	pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
			PIPE_CRC_DONE_INTERRUPT_STATUS;

3411 3412 3413
	i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
	for_each_pipe(dev_priv, pipe)
		i915_disable_pipestat(dev_priv, pipe, pipestat_mask);
3414 3415 3416

	pipestat_mask = PIPESTAT_INT_STATUS_MASK |
			PIPE_FIFO_UNDERRUN_STATUS;
3417 3418 3419

	for_each_pipe(dev_priv, pipe)
		I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3420 3421 3422 3423 3424 3425 3426 3427 3428 3429 3430 3431
	POSTING_READ(PIPESTAT(PIPE_A));
}

void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
{
	assert_spin_locked(&dev_priv->irq_lock);

	if (dev_priv->display_irqs_enabled)
		return;

	dev_priv->display_irqs_enabled = true;

3432
	if (intel_irqs_enabled(dev_priv))
3433 3434 3435 3436 3437 3438 3439 3440 3441 3442 3443 3444
		valleyview_display_irqs_install(dev_priv);
}

void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
{
	assert_spin_locked(&dev_priv->irq_lock);

	if (!dev_priv->display_irqs_enabled)
		return;

	dev_priv->display_irqs_enabled = false;

3445
	if (intel_irqs_enabled(dev_priv))
3446 3447 3448
		valleyview_display_irqs_uninstall(dev_priv);
}

3449
static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
J
Jesse Barnes 已提交
3450
{
3451
	dev_priv->irq_mask = ~0;
J
Jesse Barnes 已提交
3452

3453 3454 3455
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	POSTING_READ(PORT_HOTPLUG_EN);

J
Jesse Barnes 已提交
3456
	I915_WRITE(VLV_IIR, 0xffffffff);
3457 3458 3459 3460
	I915_WRITE(VLV_IIR, 0xffffffff);
	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
	POSTING_READ(VLV_IMR);
J
Jesse Barnes 已提交
3461

3462 3463
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
3464
	spin_lock_irq(&dev_priv->irq_lock);
3465 3466
	if (dev_priv->display_irqs_enabled)
		valleyview_display_irqs_install(dev_priv);
3467
	spin_unlock_irq(&dev_priv->irq_lock);
3468 3469 3470 3471 3472 3473 3474
}

static int valleyview_irq_postinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	vlv_display_irq_postinstall(dev_priv);
J
Jesse Barnes 已提交
3475

3476
	gen5_gt_irq_postinstall(dev);
J
Jesse Barnes 已提交
3477 3478 3479 3480 3481 3482 3483 3484

	/* ack & enable invalid PTE error interrupts */
#if 0 /* FIXME: add support to irq handler for checking these bits */
	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
	I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
#endif

	I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3485 3486 3487 3488

	return 0;
}

3489 3490 3491 3492 3493
static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
{
	/* These are interrupts we'll toggle with the ring mask register */
	uint32_t gt_interrupts[] = {
		GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3494
			GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3495
			GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
3496 3497
			GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
			GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3498
		GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3499 3500 3501
			GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
			GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
			GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3502
		0,
3503 3504
		GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
			GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3505 3506
		};

3507
	dev_priv->pm_irq_mask = 0xffffffff;
3508 3509
	GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
	GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3510 3511 3512 3513 3514
	/*
	 * RPS interrupts will get enabled/disabled on demand when RPS itself
	 * is enabled/disabled.
	 */
	GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
3515
	GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3516 3517 3518 3519
}

static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
{
3520 3521
	uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
	uint32_t de_pipe_enables;
3522
	int pipe;
S
Shashank Sharma 已提交
3523
	u32 de_port_en = GEN8_AUX_CHANNEL_A;
3524

J
Jesse Barnes 已提交
3525
	if (IS_GEN9(dev_priv)) {
3526 3527
		de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
				  GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
S
Shashank Sharma 已提交
3528
		de_port_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
J
Jesse Barnes 已提交
3529
			GEN9_AUX_CHANNEL_D;
S
Shashank Sharma 已提交
3530 3531 3532

		if (IS_BROXTON(dev_priv))
			de_port_en |= BXT_DE_PORT_GMBUS;
J
Jesse Barnes 已提交
3533
	} else
3534 3535 3536 3537 3538 3539
		de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
				  GEN8_DE_PIPE_IRQ_FAULT_ERRORS;

	de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
					   GEN8_PIPE_FIFO_UNDERRUN;

3540 3541 3542
	dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
	dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
	dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3543

3544
	for_each_pipe(dev_priv, pipe)
3545
		if (intel_display_power_is_enabled(dev_priv,
3546 3547 3548 3549
				POWER_DOMAIN_PIPE(pipe)))
			GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
					  dev_priv->de_irq_mask[pipe],
					  de_pipe_enables);
3550

S
Shashank Sharma 已提交
3551
	GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_en, de_port_en);
3552 3553 3554 3555 3556 3557
}

static int gen8_irq_postinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

3558 3559
	if (HAS_PCH_SPLIT(dev))
		ibx_irq_pre_postinstall(dev);
P
Paulo Zanoni 已提交
3560

3561 3562 3563
	gen8_gt_irq_postinstall(dev_priv);
	gen8_de_irq_postinstall(dev_priv);

3564 3565
	if (HAS_PCH_SPLIT(dev))
		ibx_irq_postinstall(dev);
3566 3567 3568 3569 3570 3571 3572

	I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
	POSTING_READ(GEN8_MASTER_IRQ);

	return 0;
}

3573 3574 3575 3576
static int cherryview_irq_postinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

3577
	vlv_display_irq_postinstall(dev_priv);
3578 3579 3580 3581 3582 3583 3584 3585 3586

	gen8_gt_irq_postinstall(dev_priv);

	I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
	POSTING_READ(GEN8_MASTER_IRQ);

	return 0;
}

3587 3588 3589 3590 3591 3592 3593
static void gen8_irq_uninstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (!dev_priv)
		return;

P
Paulo Zanoni 已提交
3594
	gen8_irq_reset(dev);
3595 3596
}

3597 3598 3599 3600 3601 3602 3603 3604 3605 3606 3607
static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv)
{
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
	spin_lock_irq(&dev_priv->irq_lock);
	if (dev_priv->display_irqs_enabled)
		valleyview_display_irqs_uninstall(dev_priv);
	spin_unlock_irq(&dev_priv->irq_lock);

	vlv_display_irq_reset(dev_priv);

3608
	dev_priv->irq_mask = ~0;
3609 3610
}

J
Jesse Barnes 已提交
3611 3612
static void valleyview_irq_uninstall(struct drm_device *dev)
{
3613
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
3614 3615 3616 3617

	if (!dev_priv)
		return;

3618 3619
	I915_WRITE(VLV_MASTER_IER, 0);

3620 3621
	gen5_gt_irq_reset(dev);

J
Jesse Barnes 已提交
3622
	I915_WRITE(HWSTAM, 0xffffffff);
3623

3624
	vlv_display_irq_uninstall(dev_priv);
J
Jesse Barnes 已提交
3625 3626
}

3627 3628 3629 3630 3631 3632 3633 3634 3635 3636
static void cherryview_irq_uninstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (!dev_priv)
		return;

	I915_WRITE(GEN8_MASTER_IRQ, 0);
	POSTING_READ(GEN8_MASTER_IRQ);

3637
	gen8_gt_irq_reset(dev_priv);
3638

3639
	GEN5_IRQ_RESET(GEN8_PCU_);
3640

3641
	vlv_display_irq_uninstall(dev_priv);
3642 3643
}

3644
static void ironlake_irq_uninstall(struct drm_device *dev)
3645
{
3646
	struct drm_i915_private *dev_priv = dev->dev_private;
3647 3648 3649 3650

	if (!dev_priv)
		return;

P
Paulo Zanoni 已提交
3651
	ironlake_irq_reset(dev);
3652 3653
}

3654
static void i8xx_irq_preinstall(struct drm_device * dev)
L
Linus Torvalds 已提交
3655
{
3656
	struct drm_i915_private *dev_priv = dev->dev_private;
3657
	int pipe;
3658

3659
	for_each_pipe(dev_priv, pipe)
3660
		I915_WRITE(PIPESTAT(pipe), 0);
3661 3662 3663
	I915_WRITE16(IMR, 0xffff);
	I915_WRITE16(IER, 0x0);
	POSTING_READ16(IER);
C
Chris Wilson 已提交
3664 3665 3666 3667
}

static int i8xx_irq_postinstall(struct drm_device *dev)
{
3668
	struct drm_i915_private *dev_priv = dev->dev_private;
C
Chris Wilson 已提交
3669 3670 3671 3672 3673 3674 3675 3676 3677

	I915_WRITE16(EMR,
		     ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));

	/* Unmask the interrupts that we always want on. */
	dev_priv->irq_mask =
		~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3678
		  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
C
Chris Wilson 已提交
3679 3680 3681 3682 3683 3684 3685 3686
	I915_WRITE16(IMR, dev_priv->irq_mask);

	I915_WRITE16(IER,
		     I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		     I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		     I915_USER_INTERRUPT);
	POSTING_READ16(IER);

3687 3688
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
3689
	spin_lock_irq(&dev_priv->irq_lock);
3690 3691
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3692
	spin_unlock_irq(&dev_priv->irq_lock);
3693

C
Chris Wilson 已提交
3694 3695 3696
	return 0;
}

3697 3698 3699 3700
/*
 * Returns true when a page flip has completed.
 */
static bool i8xx_handle_vblank(struct drm_device *dev,
3701
			       int plane, int pipe, u32 iir)
3702
{
3703
	struct drm_i915_private *dev_priv = dev->dev_private;
3704
	u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3705

3706
	if (!intel_pipe_handle_vblank(dev, pipe))
3707 3708 3709
		return false;

	if ((iir & flip_pending) == 0)
3710
		goto check_page_flip;
3711 3712 3713 3714 3715 3716 3717 3718

	/* We detect FlipDone by looking for the change in PendingFlip from '1'
	 * to '0' on the following vblank, i.e. IIR has the Pendingflip
	 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
	 * the flip is completed (no longer pending). Since this doesn't raise
	 * an interrupt per se, we watch for the change at vblank.
	 */
	if (I915_READ16(ISR) & flip_pending)
3719
		goto check_page_flip;
3720

3721
	intel_prepare_page_flip(dev, plane);
3722 3723
	intel_finish_page_flip(dev, pipe);
	return true;
3724 3725 3726 3727

check_page_flip:
	intel_check_page_flip(dev, pipe);
	return false;
3728 3729
}

3730
static irqreturn_t i8xx_irq_handler(int irq, void *arg)
C
Chris Wilson 已提交
3731
{
3732
	struct drm_device *dev = arg;
3733
	struct drm_i915_private *dev_priv = dev->dev_private;
C
Chris Wilson 已提交
3734 3735 3736 3737 3738 3739 3740
	u16 iir, new_iir;
	u32 pipe_stats[2];
	int pipe;
	u16 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;

3741 3742 3743
	if (!intel_irqs_enabled(dev_priv))
		return IRQ_NONE;

C
Chris Wilson 已提交
3744 3745 3746 3747 3748 3749 3750 3751 3752 3753
	iir = I915_READ16(IIR);
	if (iir == 0)
		return IRQ_NONE;

	while (iir & ~flip_mask) {
		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
3754
		spin_lock(&dev_priv->irq_lock);
C
Chris Wilson 已提交
3755
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3756
			DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
C
Chris Wilson 已提交
3757

3758
		for_each_pipe(dev_priv, pipe) {
C
Chris Wilson 已提交
3759 3760 3761 3762 3763 3764
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);

			/*
			 * Clear the PIPE*STAT regs before the IIR
			 */
3765
			if (pipe_stats[pipe] & 0x8000ffff)
C
Chris Wilson 已提交
3766 3767
				I915_WRITE(reg, pipe_stats[pipe]);
		}
3768
		spin_unlock(&dev_priv->irq_lock);
C
Chris Wilson 已提交
3769 3770 3771 3772 3773

		I915_WRITE16(IIR, iir & ~flip_mask);
		new_iir = I915_READ16(IIR); /* Flush posted writes */

		if (iir & I915_USER_INTERRUPT)
C
Chris Wilson 已提交
3774
			notify_ring(&dev_priv->ring[RCS]);
C
Chris Wilson 已提交
3775

3776
		for_each_pipe(dev_priv, pipe) {
3777
			int plane = pipe;
3778
			if (HAS_FBC(dev))
3779 3780
				plane = !plane;

3781
			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3782 3783
			    i8xx_handle_vblank(dev, plane, pipe, iir))
				flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
C
Chris Wilson 已提交
3784

3785
			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3786
				i9xx_pipe_crc_irq_handler(dev, pipe);
3787

3788 3789 3790
			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
				intel_cpu_fifo_underrun_irq_handler(dev_priv,
								    pipe);
3791
		}
C
Chris Wilson 已提交
3792 3793 3794 3795 3796 3797 3798 3799 3800

		iir = new_iir;
	}

	return IRQ_HANDLED;
}

static void i8xx_irq_uninstall(struct drm_device * dev)
{
3801
	struct drm_i915_private *dev_priv = dev->dev_private;
C
Chris Wilson 已提交
3802 3803
	int pipe;

3804
	for_each_pipe(dev_priv, pipe) {
C
Chris Wilson 已提交
3805 3806 3807 3808 3809 3810 3811 3812 3813
		/* Clear enable bits; then clear status bits */
		I915_WRITE(PIPESTAT(pipe), 0);
		I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
	}
	I915_WRITE16(IMR, 0xffff);
	I915_WRITE16(IER, 0x0);
	I915_WRITE16(IIR, I915_READ16(IIR));
}

3814 3815
static void i915_irq_preinstall(struct drm_device * dev)
{
3816
	struct drm_i915_private *dev_priv = dev->dev_private;
3817 3818 3819 3820 3821 3822 3823
	int pipe;

	if (I915_HAS_HOTPLUG(dev)) {
		I915_WRITE(PORT_HOTPLUG_EN, 0);
		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	}

3824
	I915_WRITE16(HWSTAM, 0xeffe);
3825
	for_each_pipe(dev_priv, pipe)
3826 3827 3828 3829 3830 3831 3832 3833
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);
	POSTING_READ(IER);
}

static int i915_irq_postinstall(struct drm_device *dev)
{
3834
	struct drm_i915_private *dev_priv = dev->dev_private;
3835
	u32 enable_mask;
3836

3837 3838 3839 3840 3841 3842 3843 3844
	I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));

	/* Unmask the interrupts that we always want on. */
	dev_priv->irq_mask =
		~(I915_ASLE_INTERRUPT |
		  I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3845
		  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3846 3847 3848 3849 3850 3851 3852

	enable_mask =
		I915_ASLE_INTERRUPT |
		I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		I915_USER_INTERRUPT;

3853
	if (I915_HAS_HOTPLUG(dev)) {
3854 3855 3856
		I915_WRITE(PORT_HOTPLUG_EN, 0);
		POSTING_READ(PORT_HOTPLUG_EN);

3857 3858 3859 3860 3861 3862 3863 3864 3865 3866
		/* Enable in IER... */
		enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
		/* and unmask in IMR */
		dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
	}

	I915_WRITE(IMR, dev_priv->irq_mask);
	I915_WRITE(IER, enable_mask);
	POSTING_READ(IER);

3867
	i915_enable_asle_pipestat(dev);
3868

3869 3870
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
3871
	spin_lock_irq(&dev_priv->irq_lock);
3872 3873
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3874
	spin_unlock_irq(&dev_priv->irq_lock);
3875

3876 3877 3878
	return 0;
}

3879 3880 3881 3882 3883 3884
/*
 * Returns true when a page flip has completed.
 */
static bool i915_handle_vblank(struct drm_device *dev,
			       int plane, int pipe, u32 iir)
{
3885
	struct drm_i915_private *dev_priv = dev->dev_private;
3886 3887
	u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);

3888
	if (!intel_pipe_handle_vblank(dev, pipe))
3889 3890 3891
		return false;

	if ((iir & flip_pending) == 0)
3892
		goto check_page_flip;
3893 3894 3895 3896 3897 3898 3899 3900

	/* We detect FlipDone by looking for the change in PendingFlip from '1'
	 * to '0' on the following vblank, i.e. IIR has the Pendingflip
	 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
	 * the flip is completed (no longer pending). Since this doesn't raise
	 * an interrupt per se, we watch for the change at vblank.
	 */
	if (I915_READ(ISR) & flip_pending)
3901
		goto check_page_flip;
3902

3903
	intel_prepare_page_flip(dev, plane);
3904 3905
	intel_finish_page_flip(dev, pipe);
	return true;
3906 3907 3908 3909

check_page_flip:
	intel_check_page_flip(dev, pipe);
	return false;
3910 3911
}

3912
static irqreturn_t i915_irq_handler(int irq, void *arg)
3913
{
3914
	struct drm_device *dev = arg;
3915
	struct drm_i915_private *dev_priv = dev->dev_private;
3916
	u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3917 3918 3919 3920
	u32 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
	int pipe, ret = IRQ_NONE;
3921

3922 3923 3924
	if (!intel_irqs_enabled(dev_priv))
		return IRQ_NONE;

3925
	iir = I915_READ(IIR);
3926 3927
	do {
		bool irq_received = (iir & ~flip_mask) != 0;
3928
		bool blc_event = false;
3929 3930 3931 3932 3933 3934

		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
3935
		spin_lock(&dev_priv->irq_lock);
3936
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3937
			DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3938

3939
		for_each_pipe(dev_priv, pipe) {
3940 3941 3942
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);

3943
			/* Clear the PIPE*STAT regs before the IIR */
3944 3945
			if (pipe_stats[pipe] & 0x8000ffff) {
				I915_WRITE(reg, pipe_stats[pipe]);
3946
				irq_received = true;
3947 3948
			}
		}
3949
		spin_unlock(&dev_priv->irq_lock);
3950 3951 3952 3953 3954

		if (!irq_received)
			break;

		/* Consume port.  Then clear IIR or we'll miss events */
3955 3956 3957
		if (I915_HAS_HOTPLUG(dev) &&
		    iir & I915_DISPLAY_PORT_INTERRUPT)
			i9xx_hpd_irq_handler(dev);
3958

3959
		I915_WRITE(IIR, iir & ~flip_mask);
3960 3961 3962
		new_iir = I915_READ(IIR); /* Flush posted writes */

		if (iir & I915_USER_INTERRUPT)
C
Chris Wilson 已提交
3963
			notify_ring(&dev_priv->ring[RCS]);
3964

3965
		for_each_pipe(dev_priv, pipe) {
3966
			int plane = pipe;
3967
			if (HAS_FBC(dev))
3968
				plane = !plane;
3969

3970
			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3971 3972
			    i915_handle_vblank(dev, plane, pipe, iir))
				flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3973 3974 3975

			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
				blc_event = true;
3976 3977

			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3978
				i9xx_pipe_crc_irq_handler(dev, pipe);
3979

3980 3981 3982
			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
				intel_cpu_fifo_underrun_irq_handler(dev_priv,
								    pipe);
3983 3984 3985 3986 3987 3988 3989 3990 3991 3992 3993 3994 3995 3996 3997 3998 3999 4000 4001 4002
		}

		if (blc_event || (iir & I915_ASLE_INTERRUPT))
			intel_opregion_asle_intr(dev);

		/* With MSI, interrupts are only generated when iir
		 * transitions from zero to nonzero.  If another bit got
		 * set while we were handling the existing iir bits, then
		 * we would never get another interrupt.
		 *
		 * This is fine on non-MSI as well, as if we hit this path
		 * we avoid exiting the interrupt handler only to generate
		 * another one.
		 *
		 * Note that for MSI this could cause a stray interrupt report
		 * if an interrupt landed in the time between writing IIR and
		 * the posting read.  This should be rare enough to never
		 * trigger the 99% of 100,000 interrupts test for disabling
		 * stray interrupts.
		 */
4003
		ret = IRQ_HANDLED;
4004
		iir = new_iir;
4005
	} while (iir & ~flip_mask);
4006 4007 4008 4009 4010 4011

	return ret;
}

static void i915_irq_uninstall(struct drm_device * dev)
{
4012
	struct drm_i915_private *dev_priv = dev->dev_private;
4013 4014 4015 4016 4017 4018 4019
	int pipe;

	if (I915_HAS_HOTPLUG(dev)) {
		I915_WRITE(PORT_HOTPLUG_EN, 0);
		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	}

4020
	I915_WRITE16(HWSTAM, 0xffff);
4021
	for_each_pipe(dev_priv, pipe) {
4022
		/* Clear enable bits; then clear status bits */
4023
		I915_WRITE(PIPESTAT(pipe), 0);
4024 4025
		I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
	}
4026 4027 4028 4029 4030 4031 4032 4033
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);

	I915_WRITE(IIR, I915_READ(IIR));
}

static void i965_irq_preinstall(struct drm_device * dev)
{
4034
	struct drm_i915_private *dev_priv = dev->dev_private;
4035 4036
	int pipe;

4037 4038
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4039 4040

	I915_WRITE(HWSTAM, 0xeffe);
4041
	for_each_pipe(dev_priv, pipe)
4042 4043 4044 4045 4046 4047 4048 4049
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);
	POSTING_READ(IER);
}

static int i965_irq_postinstall(struct drm_device *dev)
{
4050
	struct drm_i915_private *dev_priv = dev->dev_private;
4051
	u32 enable_mask;
4052 4053 4054
	u32 error_mask;

	/* Unmask the interrupts that we always want on. */
4055
	dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4056
			       I915_DISPLAY_PORT_INTERRUPT |
4057 4058 4059 4060 4061 4062 4063
			       I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
			       I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
			       I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
			       I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
			       I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);

	enable_mask = ~dev_priv->irq_mask;
4064 4065
	enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
			 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4066 4067 4068 4069
	enable_mask |= I915_USER_INTERRUPT;

	if (IS_G4X(dev))
		enable_mask |= I915_BSD_USER_INTERRUPT;
4070

4071 4072
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
4073
	spin_lock_irq(&dev_priv->irq_lock);
4074 4075 4076
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4077
	spin_unlock_irq(&dev_priv->irq_lock);
4078 4079 4080 4081 4082 4083 4084 4085 4086 4087 4088 4089 4090 4091 4092 4093 4094 4095 4096 4097

	/*
	 * Enable some error detection, note the instruction error mask
	 * bit is reserved, so we leave it masked.
	 */
	if (IS_G4X(dev)) {
		error_mask = ~(GM45_ERROR_PAGE_TABLE |
			       GM45_ERROR_MEM_PRIV |
			       GM45_ERROR_CP_PRIV |
			       I915_ERROR_MEMORY_REFRESH);
	} else {
		error_mask = ~(I915_ERROR_PAGE_TABLE |
			       I915_ERROR_MEMORY_REFRESH);
	}
	I915_WRITE(EMR, error_mask);

	I915_WRITE(IMR, dev_priv->irq_mask);
	I915_WRITE(IER, enable_mask);
	POSTING_READ(IER);

4098 4099 4100
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	POSTING_READ(PORT_HOTPLUG_EN);

4101
	i915_enable_asle_pipestat(dev);
4102 4103 4104 4105

	return 0;
}

4106
static void i915_hpd_irq_setup(struct drm_device *dev)
4107
{
4108
	struct drm_i915_private *dev_priv = dev->dev_private;
4109
	struct intel_encoder *intel_encoder;
4110 4111
	u32 hotplug_en;

4112 4113
	assert_spin_locked(&dev_priv->irq_lock);

4114 4115 4116 4117 4118 4119 4120 4121 4122 4123 4124 4125 4126 4127 4128 4129 4130 4131
	hotplug_en = I915_READ(PORT_HOTPLUG_EN);
	hotplug_en &= ~HOTPLUG_INT_EN_MASK;
	/* Note HDMI and DP share hotplug bits */
	/* enable bits are the same for all generations */
	for_each_intel_encoder(dev, intel_encoder)
		if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
			hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
	/* Programming the CRT detection parameters tends
	   to generate a spurious hotplug event about three
	   seconds later.  So just do it once.
	*/
	if (IS_G4X(dev))
		hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
	hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
	hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;

	/* Ignore TV since it's buggy */
	I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
4132 4133
}

4134
static irqreturn_t i965_irq_handler(int irq, void *arg)
4135
{
4136
	struct drm_device *dev = arg;
4137
	struct drm_i915_private *dev_priv = dev->dev_private;
4138 4139 4140
	u32 iir, new_iir;
	u32 pipe_stats[I915_MAX_PIPES];
	int ret = IRQ_NONE, pipe;
4141 4142 4143
	u32 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4144

4145 4146 4147
	if (!intel_irqs_enabled(dev_priv))
		return IRQ_NONE;

4148 4149 4150
	iir = I915_READ(IIR);

	for (;;) {
4151
		bool irq_received = (iir & ~flip_mask) != 0;
4152 4153
		bool blc_event = false;

4154 4155 4156 4157 4158
		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
4159
		spin_lock(&dev_priv->irq_lock);
4160
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4161
			DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4162

4163
		for_each_pipe(dev_priv, pipe) {
4164 4165 4166 4167 4168 4169 4170 4171
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);

			/*
			 * Clear the PIPE*STAT regs before the IIR
			 */
			if (pipe_stats[pipe] & 0x8000ffff) {
				I915_WRITE(reg, pipe_stats[pipe]);
4172
				irq_received = true;
4173 4174
			}
		}
4175
		spin_unlock(&dev_priv->irq_lock);
4176 4177 4178 4179 4180 4181 4182

		if (!irq_received)
			break;

		ret = IRQ_HANDLED;

		/* Consume port.  Then clear IIR or we'll miss events */
4183 4184
		if (iir & I915_DISPLAY_PORT_INTERRUPT)
			i9xx_hpd_irq_handler(dev);
4185

4186
		I915_WRITE(IIR, iir & ~flip_mask);
4187 4188 4189
		new_iir = I915_READ(IIR); /* Flush posted writes */

		if (iir & I915_USER_INTERRUPT)
C
Chris Wilson 已提交
4190
			notify_ring(&dev_priv->ring[RCS]);
4191
		if (iir & I915_BSD_USER_INTERRUPT)
C
Chris Wilson 已提交
4192
			notify_ring(&dev_priv->ring[VCS]);
4193

4194
		for_each_pipe(dev_priv, pipe) {
4195
			if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4196 4197
			    i915_handle_vblank(dev, pipe, pipe, iir))
				flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4198 4199 4200

			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
				blc_event = true;
4201 4202

			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4203
				i9xx_pipe_crc_irq_handler(dev, pipe);
4204

4205 4206
			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
				intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4207
		}
4208 4209 4210 4211

		if (blc_event || (iir & I915_ASLE_INTERRUPT))
			intel_opregion_asle_intr(dev);

4212 4213 4214
		if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
			gmbus_irq_handler(dev);

4215 4216 4217 4218 4219 4220 4221 4222 4223 4224 4225 4226 4227 4228 4229 4230 4231 4232 4233 4234 4235 4236 4237
		/* With MSI, interrupts are only generated when iir
		 * transitions from zero to nonzero.  If another bit got
		 * set while we were handling the existing iir bits, then
		 * we would never get another interrupt.
		 *
		 * This is fine on non-MSI as well, as if we hit this path
		 * we avoid exiting the interrupt handler only to generate
		 * another one.
		 *
		 * Note that for MSI this could cause a stray interrupt report
		 * if an interrupt landed in the time between writing IIR and
		 * the posting read.  This should be rare enough to never
		 * trigger the 99% of 100,000 interrupts test for disabling
		 * stray interrupts.
		 */
		iir = new_iir;
	}

	return ret;
}

static void i965_irq_uninstall(struct drm_device * dev)
{
4238
	struct drm_i915_private *dev_priv = dev->dev_private;
4239 4240 4241 4242 4243
	int pipe;

	if (!dev_priv)
		return;

4244 4245
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4246 4247

	I915_WRITE(HWSTAM, 0xffffffff);
4248
	for_each_pipe(dev_priv, pipe)
4249 4250 4251 4252
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);

4253
	for_each_pipe(dev_priv, pipe)
4254 4255 4256 4257 4258
		I915_WRITE(PIPESTAT(pipe),
			   I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
	I915_WRITE(IIR, I915_READ(IIR));
}

4259
static void intel_hpd_irq_reenable_work(struct work_struct *work)
4260
{
4261 4262 4263
	struct drm_i915_private *dev_priv =
		container_of(work, typeof(*dev_priv),
			     hotplug_reenable_work.work);
4264 4265 4266 4267
	struct drm_device *dev = dev_priv->dev;
	struct drm_mode_config *mode_config = &dev->mode_config;
	int i;

4268 4269
	intel_runtime_pm_get(dev_priv);

4270
	spin_lock_irq(&dev_priv->irq_lock);
4271 4272 4273 4274 4275 4276 4277 4278 4279 4280 4281 4282 4283 4284
	for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
		struct drm_connector *connector;

		if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
			continue;

		dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;

		list_for_each_entry(connector, &mode_config->connector_list, head) {
			struct intel_connector *intel_connector = to_intel_connector(connector);

			if (intel_connector->encoder->hpd_pin == i) {
				if (connector->polled != intel_connector->polled)
					DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
4285
							 connector->name);
4286 4287 4288 4289 4290 4291 4292 4293
				connector->polled = intel_connector->polled;
				if (!connector->polled)
					connector->polled = DRM_CONNECTOR_POLL_HPD;
			}
		}
	}
	if (dev_priv->display.hpd_irq_setup)
		dev_priv->display.hpd_irq_setup(dev);
4294
	spin_unlock_irq(&dev_priv->irq_lock);
4295 4296

	intel_runtime_pm_put(dev_priv);
4297 4298
}

4299 4300 4301 4302 4303 4304 4305
/**
 * intel_irq_init - initializes irq support
 * @dev_priv: i915 device instance
 *
 * This function initializes all the irq support including work items, timers
 * and all the vtables. It does not setup the interrupt itself though.
 */
4306
void intel_irq_init(struct drm_i915_private *dev_priv)
4307
{
4308
	struct drm_device *dev = dev_priv->dev;
4309 4310

	INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
4311
	INIT_WORK(&dev_priv->dig_port_work, i915_digport_work_func);
4312
	INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4313
	INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4314

4315
	/* Let's track the enabled rps events */
4316
	if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
4317
		/* WaGsvRC0ResidencyMethod:vlv */
4318
		dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
4319 4320
	else
		dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4321

4322 4323
	INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
			  i915_hangcheck_elapsed);
4324
	INIT_DELAYED_WORK(&dev_priv->hotplug_reenable_work,
4325
			  intel_hpd_irq_reenable_work);
4326

4327
	pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4328

4329
	if (IS_GEN2(dev_priv)) {
4330 4331
		dev->max_vblank_count = 0;
		dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4332
	} else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4333 4334
		dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
		dev->driver->get_vblank_counter = gm45_get_vblank_counter;
4335 4336 4337
	} else {
		dev->driver->get_vblank_counter = i915_get_vblank_counter;
		dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4338 4339
	}

4340 4341 4342 4343 4344
	/*
	 * Opt out of the vblank disable timer on everything except gen2.
	 * Gen2 doesn't have a hardware frame counter and so depends on
	 * vblank interrupts to produce sane vblank seuquence numbers.
	 */
4345
	if (!IS_GEN2(dev_priv))
4346 4347
		dev->vblank_disable_immediate = true;

4348 4349
	dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
	dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4350

4351
	if (IS_CHERRYVIEW(dev_priv)) {
4352 4353 4354 4355 4356 4357 4358
		dev->driver->irq_handler = cherryview_irq_handler;
		dev->driver->irq_preinstall = cherryview_irq_preinstall;
		dev->driver->irq_postinstall = cherryview_irq_postinstall;
		dev->driver->irq_uninstall = cherryview_irq_uninstall;
		dev->driver->enable_vblank = valleyview_enable_vblank;
		dev->driver->disable_vblank = valleyview_disable_vblank;
		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4359
	} else if (IS_VALLEYVIEW(dev_priv)) {
J
Jesse Barnes 已提交
4360 4361 4362 4363 4364 4365
		dev->driver->irq_handler = valleyview_irq_handler;
		dev->driver->irq_preinstall = valleyview_irq_preinstall;
		dev->driver->irq_postinstall = valleyview_irq_postinstall;
		dev->driver->irq_uninstall = valleyview_irq_uninstall;
		dev->driver->enable_vblank = valleyview_enable_vblank;
		dev->driver->disable_vblank = valleyview_disable_vblank;
4366
		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4367
	} else if (INTEL_INFO(dev_priv)->gen >= 8) {
4368
		dev->driver->irq_handler = gen8_irq_handler;
4369
		dev->driver->irq_preinstall = gen8_irq_reset;
4370 4371 4372 4373
		dev->driver->irq_postinstall = gen8_irq_postinstall;
		dev->driver->irq_uninstall = gen8_irq_uninstall;
		dev->driver->enable_vblank = gen8_enable_vblank;
		dev->driver->disable_vblank = gen8_disable_vblank;
4374 4375 4376 4377
		if (HAS_PCH_SPLIT(dev))
			dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
		else
			dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4378 4379
	} else if (HAS_PCH_SPLIT(dev)) {
		dev->driver->irq_handler = ironlake_irq_handler;
4380
		dev->driver->irq_preinstall = ironlake_irq_reset;
4381 4382 4383 4384
		dev->driver->irq_postinstall = ironlake_irq_postinstall;
		dev->driver->irq_uninstall = ironlake_irq_uninstall;
		dev->driver->enable_vblank = ironlake_enable_vblank;
		dev->driver->disable_vblank = ironlake_disable_vblank;
4385
		dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4386
	} else {
4387
		if (INTEL_INFO(dev_priv)->gen == 2) {
C
Chris Wilson 已提交
4388 4389 4390 4391
			dev->driver->irq_preinstall = i8xx_irq_preinstall;
			dev->driver->irq_postinstall = i8xx_irq_postinstall;
			dev->driver->irq_handler = i8xx_irq_handler;
			dev->driver->irq_uninstall = i8xx_irq_uninstall;
4392
		} else if (INTEL_INFO(dev_priv)->gen == 3) {
4393 4394 4395 4396
			dev->driver->irq_preinstall = i915_irq_preinstall;
			dev->driver->irq_postinstall = i915_irq_postinstall;
			dev->driver->irq_uninstall = i915_irq_uninstall;
			dev->driver->irq_handler = i915_irq_handler;
C
Chris Wilson 已提交
4397
		} else {
4398 4399 4400 4401
			dev->driver->irq_preinstall = i965_irq_preinstall;
			dev->driver->irq_postinstall = i965_irq_postinstall;
			dev->driver->irq_uninstall = i965_irq_uninstall;
			dev->driver->irq_handler = i965_irq_handler;
C
Chris Wilson 已提交
4402
		}
4403 4404
		if (I915_HAS_HOTPLUG(dev_priv))
			dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4405 4406 4407 4408
		dev->driver->enable_vblank = i915_enable_vblank;
		dev->driver->disable_vblank = i915_disable_vblank;
	}
}
4409

4410 4411 4412 4413 4414 4415 4416 4417 4418 4419 4420 4421
/**
 * intel_hpd_init - initializes and enables hpd support
 * @dev_priv: i915 device instance
 *
 * This function enables the hotplug support. It requires that interrupts have
 * already been enabled with intel_irq_init_hw(). From this point on hotplug and
 * poll request can run concurrently to other code, so locking rules must be
 * obeyed.
 *
 * This is a separate step from interrupt enabling to simplify the locking rules
 * in the driver load and resume code.
 */
4422
void intel_hpd_init(struct drm_i915_private *dev_priv)
4423
{
4424
	struct drm_device *dev = dev_priv->dev;
4425 4426 4427
	struct drm_mode_config *mode_config = &dev->mode_config;
	struct drm_connector *connector;
	int i;
4428

4429 4430 4431 4432 4433 4434 4435
	for (i = 1; i < HPD_NUM_PINS; i++) {
		dev_priv->hpd_stats[i].hpd_cnt = 0;
		dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
	}
	list_for_each_entry(connector, &mode_config->connector_list, head) {
		struct intel_connector *intel_connector = to_intel_connector(connector);
		connector->polled = intel_connector->polled;
4436 4437 4438
		if (connector->encoder && !connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
			connector->polled = DRM_CONNECTOR_POLL_HPD;
		if (intel_connector->mst_port)
4439 4440
			connector->polled = DRM_CONNECTOR_POLL_HPD;
	}
4441 4442 4443

	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked checks happy. */
4444
	spin_lock_irq(&dev_priv->irq_lock);
4445 4446
	if (dev_priv->display.hpd_irq_setup)
		dev_priv->display.hpd_irq_setup(dev);
4447
	spin_unlock_irq(&dev_priv->irq_lock);
4448
}
4449

4450 4451 4452 4453 4454 4455 4456 4457 4458 4459 4460
/**
 * intel_irq_install - enables the hardware interrupt
 * @dev_priv: i915 device instance
 *
 * This function enables the hardware interrupt handling, but leaves the hotplug
 * handling still disabled. It is called after intel_irq_init().
 *
 * In the driver load and resume code we need working interrupts in a few places
 * but don't want to deal with the hassle of concurrent probe and hotplug
 * workers. Hence the split into this two-stage approach.
 */
4461 4462 4463 4464 4465 4466 4467 4468 4469 4470 4471 4472
int intel_irq_install(struct drm_i915_private *dev_priv)
{
	/*
	 * We enable some interrupt sources in our postinstall hooks, so mark
	 * interrupts as enabled _before_ actually enabling them to avoid
	 * special cases in our ordering checks.
	 */
	dev_priv->pm.irqs_enabled = true;

	return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
}

4473 4474 4475 4476 4477 4478 4479
/**
 * intel_irq_uninstall - finilizes all irq handling
 * @dev_priv: i915 device instance
 *
 * This stops interrupt and hotplug handling and unregisters and frees all
 * resources acquired in the init functions.
 */
4480 4481 4482 4483 4484 4485 4486
void intel_irq_uninstall(struct drm_i915_private *dev_priv)
{
	drm_irq_uninstall(dev_priv->dev);
	intel_hpd_cancel_work(dev_priv);
	dev_priv->pm.irqs_enabled = false;
}

4487 4488 4489 4490 4491 4492 4493
/**
 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
 * @dev_priv: i915 device instance
 *
 * This function is used to disable interrupts at runtime, both in the runtime
 * pm and the system suspend/resume code.
 */
4494
void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4495
{
4496
	dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
4497
	dev_priv->pm.irqs_enabled = false;
4498
	synchronize_irq(dev_priv->dev->irq);
4499 4500
}

4501 4502 4503 4504 4505 4506 4507
/**
 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
 * @dev_priv: i915 device instance
 *
 * This function is used to enable interrupts at runtime, both in the runtime
 * pm and the system suspend/resume code.
 */
4508
void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4509
{
4510
	dev_priv->pm.irqs_enabled = true;
4511 4512
	dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
	dev_priv->dev->driver->irq_postinstall(dev_priv->dev);
4513
}