i915_irq.c 118.7 KB
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/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
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 */
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/*
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

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#include <linux/sysrq.h>
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#include <linux/slab.h>
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#include <linux/circ_buf.h>
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#include <drm/drmP.h>
#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#include "i915_trace.h"
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#include "intel_drv.h"
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static const u32 hpd_ibx[] = {
	[HPD_CRT] = SDE_CRT_HOTPLUG,
	[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
	[HPD_PORT_B] = SDE_PORTB_HOTPLUG,
	[HPD_PORT_C] = SDE_PORTC_HOTPLUG,
	[HPD_PORT_D] = SDE_PORTD_HOTPLUG
};

static const u32 hpd_cpt[] = {
	[HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
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	[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
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	[HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
	[HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
	[HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
};

static const u32 hpd_mask_i915[] = {
	[HPD_CRT] = CRT_HOTPLUG_INT_EN,
	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
	[HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
	[HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
	[HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
};

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static const u32 hpd_status_g4x[] = {
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	[HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
	[HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
	[HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
	[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
};

static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
	[HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
	[HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
	[HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
	[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
};

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#define GEN5_IRQ_INIT(type) do { \
	I915_WRITE(type##IMR, 0xffffffff); \
	I915_WRITE(type##IER, 0); \
	POSTING_READ(type##IER); \
} while (0)

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/* For display hotplug interrupt */
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static void
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ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
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{
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	assert_spin_locked(&dev_priv->irq_lock);

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	if (dev_priv->pm.irqs_disabled) {
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		WARN(1, "IRQs disabled\n");
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		dev_priv->pm.regsave.deimr &= ~mask;
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		return;
	}

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	if ((dev_priv->irq_mask & mask) != 0) {
		dev_priv->irq_mask &= ~mask;
		I915_WRITE(DEIMR, dev_priv->irq_mask);
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		POSTING_READ(DEIMR);
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	}
}

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static void
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ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
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{
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	assert_spin_locked(&dev_priv->irq_lock);

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	if (dev_priv->pm.irqs_disabled) {
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		WARN(1, "IRQs disabled\n");
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		dev_priv->pm.regsave.deimr |= mask;
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		return;
	}

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	if ((dev_priv->irq_mask & mask) != mask) {
		dev_priv->irq_mask |= mask;
		I915_WRITE(DEIMR, dev_priv->irq_mask);
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		POSTING_READ(DEIMR);
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	}
}

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/**
 * ilk_update_gt_irq - update GTIMR
 * @dev_priv: driver private
 * @interrupt_mask: mask of interrupt bits to update
 * @enabled_irq_mask: mask of interrupt bits to enable
 */
static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
			      uint32_t interrupt_mask,
			      uint32_t enabled_irq_mask)
{
	assert_spin_locked(&dev_priv->irq_lock);

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	if (dev_priv->pm.irqs_disabled) {
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		WARN(1, "IRQs disabled\n");
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		dev_priv->pm.regsave.gtimr &= ~interrupt_mask;
		dev_priv->pm.regsave.gtimr |= (~enabled_irq_mask &
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						interrupt_mask);
		return;
	}

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	dev_priv->gt_irq_mask &= ~interrupt_mask;
	dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
	POSTING_READ(GTIMR);
}

void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
{
	ilk_update_gt_irq(dev_priv, mask, mask);
}

void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
{
	ilk_update_gt_irq(dev_priv, mask, 0);
}

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/**
  * snb_update_pm_irq - update GEN6_PMIMR
  * @dev_priv: driver private
  * @interrupt_mask: mask of interrupt bits to update
  * @enabled_irq_mask: mask of interrupt bits to enable
  */
static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
			      uint32_t interrupt_mask,
			      uint32_t enabled_irq_mask)
{
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	uint32_t new_val;
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	assert_spin_locked(&dev_priv->irq_lock);

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	if (dev_priv->pm.irqs_disabled) {
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		WARN(1, "IRQs disabled\n");
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		dev_priv->pm.regsave.gen6_pmimr &= ~interrupt_mask;
		dev_priv->pm.regsave.gen6_pmimr |= (~enabled_irq_mask &
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						     interrupt_mask);
		return;
	}

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	new_val = dev_priv->pm_irq_mask;
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	new_val &= ~interrupt_mask;
	new_val |= (~enabled_irq_mask & interrupt_mask);

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	if (new_val != dev_priv->pm_irq_mask) {
		dev_priv->pm_irq_mask = new_val;
		I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
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		POSTING_READ(GEN6_PMIMR);
	}
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}

void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
{
	snb_update_pm_irq(dev_priv, mask, mask);
}

void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
{
	snb_update_pm_irq(dev_priv, mask, 0);
}

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static bool ivb_can_enable_err_int(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *crtc;
	enum pipe pipe;

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	assert_spin_locked(&dev_priv->irq_lock);

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	for_each_pipe(pipe) {
		crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);

		if (crtc->cpu_fifo_underrun_disabled)
			return false;
	}

	return true;
}

static bool cpt_can_enable_serr_int(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum pipe pipe;
	struct intel_crtc *crtc;

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	assert_spin_locked(&dev_priv->irq_lock);

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	for_each_pipe(pipe) {
		crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);

		if (crtc->pch_fifo_underrun_disabled)
			return false;
	}

	return true;
}

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static void i9xx_clear_fifo_underrun(struct drm_device *dev, enum pipe pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 reg = PIPESTAT(pipe);
	u32 pipestat = I915_READ(reg) & 0x7fff0000;

	assert_spin_locked(&dev_priv->irq_lock);

	I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
	POSTING_READ(reg);
}

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static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
						 enum pipe pipe, bool enable)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
					  DE_PIPEB_FIFO_UNDERRUN;

	if (enable)
		ironlake_enable_display_irq(dev_priv, bit);
	else
		ironlake_disable_display_irq(dev_priv, bit);
}

static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
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						  enum pipe pipe, bool enable)
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{
	struct drm_i915_private *dev_priv = dev->dev_private;
	if (enable) {
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		I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));

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		if (!ivb_can_enable_err_int(dev))
			return;

		ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
	} else {
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		bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);

		/* Change the state _after_ we've read out the current one. */
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		ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
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		if (!was_enabled &&
		    (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
			DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
				      pipe_name(pipe));
		}
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	}
}

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static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
						  enum pipe pipe, bool enable)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	assert_spin_locked(&dev_priv->irq_lock);

	if (enable)
		dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;
	else
		dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;
	I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
	POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
}

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/**
 * ibx_display_interrupt_update - update SDEIMR
 * @dev_priv: driver private
 * @interrupt_mask: mask of interrupt bits to update
 * @enabled_irq_mask: mask of interrupt bits to enable
 */
static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
					 uint32_t interrupt_mask,
					 uint32_t enabled_irq_mask)
{
	uint32_t sdeimr = I915_READ(SDEIMR);
	sdeimr &= ~interrupt_mask;
	sdeimr |= (~enabled_irq_mask & interrupt_mask);

	assert_spin_locked(&dev_priv->irq_lock);

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	if (dev_priv->pm.irqs_disabled &&
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	    (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) {
		WARN(1, "IRQs disabled\n");
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		dev_priv->pm.regsave.sdeimr &= ~interrupt_mask;
		dev_priv->pm.regsave.sdeimr |= (~enabled_irq_mask &
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						 interrupt_mask);
		return;
	}

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	I915_WRITE(SDEIMR, sdeimr);
	POSTING_READ(SDEIMR);
}
#define ibx_enable_display_interrupt(dev_priv, bits) \
	ibx_display_interrupt_update((dev_priv), (bits), (bits))
#define ibx_disable_display_interrupt(dev_priv, bits) \
	ibx_display_interrupt_update((dev_priv), (bits), 0)

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static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
					    enum transcoder pch_transcoder,
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					    bool enable)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
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	uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
		       SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
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	if (enable)
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		ibx_enable_display_interrupt(dev_priv, bit);
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	else
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		ibx_disable_display_interrupt(dev_priv, bit);
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}

static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
					    enum transcoder pch_transcoder,
					    bool enable)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (enable) {
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		I915_WRITE(SERR_INT,
			   SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));

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		if (!cpt_can_enable_serr_int(dev))
			return;

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		ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
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	} else {
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		uint32_t tmp = I915_READ(SERR_INT);
		bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);

		/* Change the state _after_ we've read out the current one. */
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		ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
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		if (!was_enabled &&
		    (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
			DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
				      transcoder_name(pch_transcoder));
		}
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	}
}

/**
 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
 * @dev: drm device
 * @pipe: pipe
 * @enable: true if we want to report FIFO underrun errors, false otherwise
 *
 * This function makes us disable or enable CPU fifo underruns for a specific
 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
 * reporting for one pipe may also disable all the other CPU error interruts for
 * the other pipes, due to the fact that there's just one interrupt mask/enable
 * bit for all the pipes.
 *
 * Returns the previous state of underrun reporting.
 */
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bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
					     enum pipe pipe, bool enable)
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{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	bool ret;

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	assert_spin_locked(&dev_priv->irq_lock);

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	ret = !intel_crtc->cpu_fifo_underrun_disabled;

	if (enable == ret)
		goto done;

	intel_crtc->cpu_fifo_underrun_disabled = !enable;

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	if (enable && (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)))
		i9xx_clear_fifo_underrun(dev, pipe);
	else if (IS_GEN5(dev) || IS_GEN6(dev))
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		ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
	else if (IS_GEN7(dev))
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		ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
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	else if (IS_GEN8(dev))
		broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
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done:
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	return ret;
}

bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
					   enum pipe pipe, bool enable)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long flags;
	bool ret;

	spin_lock_irqsave(&dev_priv->irq_lock, flags);
	ret = __intel_set_cpu_fifo_underrun_reporting(dev, pipe, enable);
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	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
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	return ret;
}

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static bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev,
						  enum pipe pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	return !intel_crtc->cpu_fifo_underrun_disabled;
}

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/**
 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
 * @dev: drm device
 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
 * @enable: true if we want to report FIFO underrun errors, false otherwise
 *
 * This function makes us disable or enable PCH fifo underruns for a specific
 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
 * underrun reporting for one transcoder may also disable all the other PCH
 * error interruts for the other transcoders, due to the fact that there's just
 * one interrupt mask/enable bit for all the transcoders.
 *
 * Returns the previous state of underrun reporting.
 */
bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
					   enum transcoder pch_transcoder,
					   bool enable)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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	unsigned long flags;
	bool ret;

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	/*
	 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
	 * has only one pch transcoder A that all pipes can use. To avoid racy
	 * pch transcoder -> pipe lookups from interrupt code simply store the
	 * underrun statistics in crtc A. Since we never expose this anywhere
	 * nor use it outside of the fifo underrun code here using the "wrong"
	 * crtc on LPT won't cause issues.
	 */
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	spin_lock_irqsave(&dev_priv->irq_lock, flags);

	ret = !intel_crtc->pch_fifo_underrun_disabled;

	if (enable == ret)
		goto done;

	intel_crtc->pch_fifo_underrun_disabled = !enable;

	if (HAS_PCH_IBX(dev))
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		ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
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	else
		cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);

done:
	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
	return ret;
}


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static void
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__i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		       u32 enable_mask, u32 status_mask)
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{
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	u32 reg = PIPESTAT(pipe);
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	u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
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	assert_spin_locked(&dev_priv->irq_lock);

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	if (WARN_ON_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
	                 status_mask & ~PIPESTAT_INT_STATUS_MASK))
		return;

	if ((pipestat & enable_mask) == enable_mask)
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		return;

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	dev_priv->pipestat_irq_mask[pipe] |= status_mask;

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	/* Enable the interrupt, clear any pending status */
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	pipestat |= enable_mask | status_mask;
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	I915_WRITE(reg, pipestat);
	POSTING_READ(reg);
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}

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static void
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__i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		        u32 enable_mask, u32 status_mask)
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{
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	u32 reg = PIPESTAT(pipe);
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	u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
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	assert_spin_locked(&dev_priv->irq_lock);

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	if (WARN_ON_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
	                 status_mask & ~PIPESTAT_INT_STATUS_MASK))
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		return;

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	if ((pipestat & enable_mask) == 0)
		return;

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	dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;

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	pipestat &= ~enable_mask;
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	I915_WRITE(reg, pipestat);
	POSTING_READ(reg);
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}

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static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
{
	u32 enable_mask = status_mask << 16;

	/*
	 * On pipe A we don't support the PSR interrupt yet, on pipe B the
	 * same bit MBZ.
	 */
	if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
		return 0;

	enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
			 SPRITE0_FLIP_DONE_INT_EN_VLV |
			 SPRITE1_FLIP_DONE_INT_EN_VLV);
	if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
		enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
	if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
		enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;

	return enable_mask;
}

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void
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		     u32 status_mask)
{
	u32 enable_mask;

578 579 580 581 582
	if (IS_VALLEYVIEW(dev_priv->dev))
		enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
							   status_mask);
	else
		enable_mask = status_mask << 16;
583 584 585 586 587 588 589 590 591
	__i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
}

void
i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		      u32 status_mask)
{
	u32 enable_mask;

592 593 594 595 596
	if (IS_VALLEYVIEW(dev_priv->dev))
		enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
							   status_mask);
	else
		enable_mask = status_mask << 16;
597 598 599
	__i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
}

600
/**
601
 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
602
 */
603
static void i915_enable_asle_pipestat(struct drm_device *dev)
604
{
605
	struct drm_i915_private *dev_priv = dev->dev_private;
606 607
	unsigned long irqflags;

608 609 610
	if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
		return;

611
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
612

613
	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
614
	if (INTEL_INFO(dev)->gen >= 4)
615
		i915_enable_pipestat(dev_priv, PIPE_A,
616
				     PIPE_LEGACY_BLC_EVENT_STATUS);
617 618

	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
619 620
}

621 622 623 624 625 626 627 628 629 630 631 632
/**
 * i915_pipe_enabled - check if a pipe is enabled
 * @dev: DRM device
 * @pipe: pipe to check
 *
 * Reading certain registers when the pipe is disabled can hang the chip.
 * Use this routine to make sure the PLL is running and the pipe is active
 * before reading such registers if unsure.
 */
static int
i915_pipe_enabled(struct drm_device *dev, int pipe)
{
633
	struct drm_i915_private *dev_priv = dev->dev_private;
634

635 636 637 638
	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
		/* Locking is horribly broken here, but whatever. */
		struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
639

640 641 642 643
		return intel_crtc->active;
	} else {
		return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
	}
644 645
}

646 647 648 649 650 651
static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
{
	/* Gen2 doesn't have a hardware frame counter */
	return 0;
}

652 653 654
/* Called from drm generic code, passed a 'crtc', which
 * we use as a pipe index
 */
655
static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
656
{
657
	struct drm_i915_private *dev_priv = dev->dev_private;
658 659
	unsigned long high_frame;
	unsigned long low_frame;
660
	u32 high1, high2, low, pixel, vbl_start;
661 662

	if (!i915_pipe_enabled(dev, pipe)) {
663
		DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
664
				"pipe %c\n", pipe_name(pipe));
665 666 667
		return 0;
	}

668 669 670 671 672 673 674 675
	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
		struct intel_crtc *intel_crtc =
			to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
		const struct drm_display_mode *mode =
			&intel_crtc->config.adjusted_mode;

		vbl_start = mode->crtc_vblank_start * mode->crtc_htotal;
	} else {
676
		enum transcoder cpu_transcoder = (enum transcoder) pipe;
677 678 679 680 681 682 683 684
		u32 htotal;

		htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
		vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;

		vbl_start *= htotal;
	}

685 686
	high_frame = PIPEFRAME(pipe);
	low_frame = PIPEFRAMEPIXEL(pipe);
687

688 689 690 691 692 693
	/*
	 * High & low register fields aren't synchronized, so make sure
	 * we get a low value that's stable across two reads of the high
	 * register.
	 */
	do {
694
		high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
695
		low   = I915_READ(low_frame);
696
		high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
697 698
	} while (high1 != high2);

699
	high1 >>= PIPE_FRAME_HIGH_SHIFT;
700
	pixel = low & PIPE_PIXEL_MASK;
701
	low >>= PIPE_FRAME_LOW_SHIFT;
702 703 704 705 706 707

	/*
	 * The frame counter increments at beginning of active.
	 * Cook up a vblank counter by also checking the pixel
	 * counter against vblank start.
	 */
708
	return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
709 710
}

711
static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
712
{
713
	struct drm_i915_private *dev_priv = dev->dev_private;
714
	int reg = PIPE_FRMCOUNT_GM45(pipe);
715 716

	if (!i915_pipe_enabled(dev, pipe)) {
717
		DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
718
				 "pipe %c\n", pipe_name(pipe));
719 720 721 722 723 724
		return 0;
	}

	return I915_READ(reg);
}

725 726 727
/* raw reads, only for fast reads of display block, no need for forcewake etc. */
#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))

728
static bool ilk_pipe_in_vblank_locked(struct drm_device *dev, enum pipe pipe)
729 730 731
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t status;
732 733 734 735 736 737 738 739
	int reg;

	if (INTEL_INFO(dev)->gen >= 8) {
		status = GEN8_PIPE_VBLANK;
		reg = GEN8_DE_PIPE_ISR(pipe);
	} else if (INTEL_INFO(dev)->gen >= 7) {
		status = DE_PIPE_VBLANK_IVB(pipe);
		reg = DEISR;
740
	} else {
741 742
		status = DE_PIPE_VBLANK(pipe);
		reg = DEISR;
743
	}
744

745
	return __raw_i915_read32(dev_priv, reg) & status;
746 747
}

748
static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
749 750
				    unsigned int flags, int *vpos, int *hpos,
				    ktime_t *stime, ktime_t *etime)
751
{
752 753 754 755
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
756
	int position;
757 758 759
	int vbl_start, vbl_end, htotal, vtotal;
	bool in_vbl = true;
	int ret = 0;
760
	unsigned long irqflags;
761

762
	if (!intel_crtc->active) {
763
		DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
764
				 "pipe %c\n", pipe_name(pipe));
765 766 767
		return 0;
	}

768 769 770 771
	htotal = mode->crtc_htotal;
	vtotal = mode->crtc_vtotal;
	vbl_start = mode->crtc_vblank_start;
	vbl_end = mode->crtc_vblank_end;
772

773 774 775 776 777 778
	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
		vbl_start = DIV_ROUND_UP(vbl_start, 2);
		vbl_end /= 2;
		vtotal /= 2;
	}

779 780
	ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;

781 782 783 784 785 786 787 788 789 790 791 792 793
	/*
	 * Lock uncore.lock, as we will do multiple timing critical raw
	 * register reads, potentially with preemption disabled, so the
	 * following code must not block on uncore.lock.
	 */
	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
	
	/* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */

	/* Get optional system timestamp before query. */
	if (stime)
		*stime = ktime_get();

794
	if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
795 796 797
		/* No obvious pixelcount register. Only query vertical
		 * scanout position from Display scan line register.
		 */
798
		if (IS_GEN2(dev))
799
			position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
800
		else
801
			position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
802

803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824
		if (HAS_DDI(dev)) {
			/*
			 * On HSW HDMI outputs there seems to be a 2 line
			 * difference, whereas eDP has the normal 1 line
			 * difference that earlier platforms have. External
			 * DP is unknown. For now just check for the 2 line
			 * difference case on all output types on HSW+.
			 *
			 * This might misinterpret the scanline counter being
			 * one line too far along on eDP, but that's less
			 * dangerous than the alternative since that would lead
			 * the vblank timestamp code astray when it sees a
			 * scanline count before vblank_start during a vblank
			 * interrupt.
			 */
			in_vbl = ilk_pipe_in_vblank_locked(dev, pipe);
			if ((in_vbl && (position == vbl_start - 2 ||
					position == vbl_start - 1)) ||
			    (!in_vbl && (position == vbl_end - 2 ||
					 position == vbl_end - 1)))
				position = (position + 2) % vtotal;
		} else if (HAS_PCH_SPLIT(dev)) {
825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859
			/*
			 * The scanline counter increments at the leading edge
			 * of hsync, ie. it completely misses the active portion
			 * of the line. Fix up the counter at both edges of vblank
			 * to get a more accurate picture whether we're in vblank
			 * or not.
			 */
			in_vbl = ilk_pipe_in_vblank_locked(dev, pipe);
			if ((in_vbl && position == vbl_start - 1) ||
			    (!in_vbl && position == vbl_end - 1))
				position = (position + 1) % vtotal;
		} else {
			/*
			 * ISR vblank status bits don't work the way we'd want
			 * them to work on non-PCH platforms (for
			 * ilk_pipe_in_vblank_locked()), and there doesn't
			 * appear any other way to determine if we're currently
			 * in vblank.
			 *
			 * Instead let's assume that we're already in vblank if
			 * we got called from the vblank interrupt and the
			 * scanline counter value indicates that we're on the
			 * line just prior to vblank start. This should result
			 * in the correct answer, unless the vblank interrupt
			 * delivery really got delayed for almost exactly one
			 * full frame/field.
			 */
			if (flags & DRM_CALLED_FROM_VBLIRQ &&
			    position == vbl_start - 1) {
				position = (position + 1) % vtotal;

				/* Signal this correction as "applied". */
				ret |= 0x8;
			}
		}
860 861 862 863 864
	} else {
		/* Have access to pixelcount since start of frame.
		 * We can split this into vertical and horizontal
		 * scanout position.
		 */
865
		position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
866

867 868 869 870
		/* convert to pixel counts */
		vbl_start *= htotal;
		vbl_end *= htotal;
		vtotal *= htotal;
871 872
	}

873 874 875 876 877 878 879 880
	/* Get optional system timestamp after query. */
	if (etime)
		*etime = ktime_get();

	/* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */

	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

881 882 883 884 885 886 887 888 889 890 891 892
	in_vbl = position >= vbl_start && position < vbl_end;

	/*
	 * While in vblank, position will be negative
	 * counting up towards 0 at vbl_end. And outside
	 * vblank, position will be positive counting
	 * up since vbl_end.
	 */
	if (position >= vbl_start)
		position -= vbl_end;
	else
		position += vtotal - vbl_end;
893

894
	if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
895 896 897 898 899 900
		*vpos = position;
		*hpos = 0;
	} else {
		*vpos = position / htotal;
		*hpos = position - (*vpos * htotal);
	}
901 902 903 904 905 906 907 908

	/* In vblank? */
	if (in_vbl)
		ret |= DRM_SCANOUTPOS_INVBL;

	return ret;
}

909
static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
910 911 912 913
			      int *max_error,
			      struct timeval *vblank_time,
			      unsigned flags)
{
914
	struct drm_crtc *crtc;
915

916
	if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
917
		DRM_ERROR("Invalid crtc %d\n", pipe);
918 919 920 921
		return -EINVAL;
	}

	/* Get drm_crtc to timestamp: */
922 923 924 925 926 927 928 929 930 931
	crtc = intel_get_crtc_for_pipe(dev, pipe);
	if (crtc == NULL) {
		DRM_ERROR("Invalid crtc %d\n", pipe);
		return -EINVAL;
	}

	if (!crtc->enabled) {
		DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
		return -EBUSY;
	}
932 933

	/* Helper routine in DRM core does all the work: */
934 935
	return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
						     vblank_time, flags,
936 937
						     crtc,
						     &to_intel_crtc(crtc)->config.adjusted_mode);
938 939
}

940 941
static bool intel_hpd_irq_event(struct drm_device *dev,
				struct drm_connector *connector)
942 943 944 945 946 947 948
{
	enum drm_connector_status old_status;

	WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
	old_status = connector->status;

	connector->status = connector->funcs->detect(connector, false);
949 950 951 952
	if (old_status == connector->status)
		return false;

	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
953 954
		      connector->base.id,
		      drm_get_connector_name(connector),
955 956 957 958
		      drm_get_connector_status_name(old_status),
		      drm_get_connector_status_name(connector->status));

	return true;
959 960
}

961 962 963
/*
 * Handle hotplug events outside the interrupt handler proper.
 */
964 965
#define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)

966 967
static void i915_hotplug_work_func(struct work_struct *work)
{
968 969
	struct drm_i915_private *dev_priv =
		container_of(work, struct drm_i915_private, hotplug_work);
970
	struct drm_device *dev = dev_priv->dev;
971
	struct drm_mode_config *mode_config = &dev->mode_config;
972 973 974 975 976
	struct intel_connector *intel_connector;
	struct intel_encoder *intel_encoder;
	struct drm_connector *connector;
	unsigned long irqflags;
	bool hpd_disabled = false;
977
	bool changed = false;
978
	u32 hpd_event_bits;
979

980 981 982 983
	/* HPD irq before everything is fully set up. */
	if (!dev_priv->enable_hotplug_processing)
		return;

984
	mutex_lock(&mode_config->mutex);
985 986
	DRM_DEBUG_KMS("running encoder hotplug functions\n");

987
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
988 989 990

	hpd_event_bits = dev_priv->hpd_event_bits;
	dev_priv->hpd_event_bits = 0;
991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004
	list_for_each_entry(connector, &mode_config->connector_list, head) {
		intel_connector = to_intel_connector(connector);
		intel_encoder = intel_connector->encoder;
		if (intel_encoder->hpd_pin > HPD_NONE &&
		    dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
		    connector->polled == DRM_CONNECTOR_POLL_HPD) {
			DRM_INFO("HPD interrupt storm detected on connector %s: "
				 "switching from hotplug detection to polling\n",
				drm_get_connector_name(connector));
			dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
			connector->polled = DRM_CONNECTOR_POLL_CONNECT
				| DRM_CONNECTOR_POLL_DISCONNECT;
			hpd_disabled = true;
		}
1005 1006 1007 1008
		if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
			DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
				      drm_get_connector_name(connector), intel_encoder->hpd_pin);
		}
1009 1010 1011 1012
	}
	 /* if there were no outputs to poll, poll was disabled,
	  * therefore make sure it's enabled when disabling HPD on
	  * some connectors */
1013
	if (hpd_disabled) {
1014
		drm_kms_helper_poll_enable(dev);
1015 1016 1017
		mod_timer(&dev_priv->hotplug_reenable_timer,
			  jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
	}
1018 1019 1020

	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

1021 1022 1023 1024 1025 1026 1027 1028 1029 1030
	list_for_each_entry(connector, &mode_config->connector_list, head) {
		intel_connector = to_intel_connector(connector);
		intel_encoder = intel_connector->encoder;
		if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
			if (intel_encoder->hot_plug)
				intel_encoder->hot_plug(intel_encoder);
			if (intel_hpd_irq_event(dev, connector))
				changed = true;
		}
	}
1031 1032
	mutex_unlock(&mode_config->mutex);

1033 1034
	if (changed)
		drm_kms_helper_hotplug_event(dev);
1035 1036
}

1037 1038 1039 1040 1041
static void intel_hpd_irq_uninstall(struct drm_i915_private *dev_priv)
{
	del_timer_sync(&dev_priv->hotplug_reenable_timer);
}

1042
static void ironlake_rps_change_irq_handler(struct drm_device *dev)
1043
{
1044
	struct drm_i915_private *dev_priv = dev->dev_private;
1045
	u32 busy_up, busy_down, max_avg, min_avg;
1046 1047
	u8 new_delay;

1048
	spin_lock(&mchdev_lock);
1049

1050 1051
	I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));

1052
	new_delay = dev_priv->ips.cur_delay;
1053

1054
	I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
1055 1056
	busy_up = I915_READ(RCPREVBSYTUPAVG);
	busy_down = I915_READ(RCPREVBSYTDNAVG);
1057 1058 1059 1060
	max_avg = I915_READ(RCBMAXAVG);
	min_avg = I915_READ(RCBMINAVG);

	/* Handle RCS change request from hw */
1061
	if (busy_up > max_avg) {
1062 1063 1064 1065
		if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
			new_delay = dev_priv->ips.cur_delay - 1;
		if (new_delay < dev_priv->ips.max_delay)
			new_delay = dev_priv->ips.max_delay;
1066
	} else if (busy_down < min_avg) {
1067 1068 1069 1070
		if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
			new_delay = dev_priv->ips.cur_delay + 1;
		if (new_delay > dev_priv->ips.min_delay)
			new_delay = dev_priv->ips.min_delay;
1071 1072
	}

1073
	if (ironlake_set_drps(dev, new_delay))
1074
		dev_priv->ips.cur_delay = new_delay;
1075

1076
	spin_unlock(&mchdev_lock);
1077

1078 1079 1080
	return;
}

1081 1082 1083
static void notify_ring(struct drm_device *dev,
			struct intel_ring_buffer *ring)
{
1084 1085 1086
	if (ring->obj == NULL)
		return;

1087
	trace_i915_gem_request_complete(ring);
1088

1089
	wake_up_all(&ring->irq_queue);
1090
	i915_queue_hangcheck(dev);
1091 1092
}

1093
static void gen6_pm_rps_work(struct work_struct *work)
1094
{
1095 1096
	struct drm_i915_private *dev_priv =
		container_of(work, struct drm_i915_private, rps.work);
P
Paulo Zanoni 已提交
1097
	u32 pm_iir;
1098
	int new_delay, adj;
1099

1100
	spin_lock_irq(&dev_priv->irq_lock);
1101 1102
	pm_iir = dev_priv->rps.pm_iir;
	dev_priv->rps.pm_iir = 0;
1103
	/* Make sure not to corrupt PMIMR state used by ringbuffer code */
1104
	snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1105
	spin_unlock_irq(&dev_priv->irq_lock);
1106

1107
	/* Make sure we didn't queue anything we're not going to process. */
1108
	WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1109

1110
	if ((pm_iir & dev_priv->pm_rps_events) == 0)
1111 1112
		return;

1113
	mutex_lock(&dev_priv->rps.hw_lock);
1114

1115
	adj = dev_priv->rps.last_adj;
1116
	if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1117 1118 1119 1120
		if (adj > 0)
			adj *= 2;
		else
			adj = 1;
1121
		new_delay = dev_priv->rps.cur_freq + adj;
1122 1123 1124 1125 1126

		/*
		 * For better performance, jump directly
		 * to RPe if we're below it.
		 */
1127 1128
		if (new_delay < dev_priv->rps.efficient_freq)
			new_delay = dev_priv->rps.efficient_freq;
1129
	} else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1130 1131
		if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
			new_delay = dev_priv->rps.efficient_freq;
1132
		else
1133
			new_delay = dev_priv->rps.min_freq_softlimit;
1134 1135 1136 1137 1138 1139
		adj = 0;
	} else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
		if (adj < 0)
			adj *= 2;
		else
			adj = -1;
1140
		new_delay = dev_priv->rps.cur_freq + adj;
1141
	} else { /* unknown event */
1142
		new_delay = dev_priv->rps.cur_freq;
1143
	}
1144

1145 1146 1147
	/* sysfs frequency interfaces may have snuck in while servicing the
	 * interrupt
	 */
1148
	new_delay = clamp_t(int, new_delay,
1149 1150
			    dev_priv->rps.min_freq_softlimit,
			    dev_priv->rps.max_freq_softlimit);
1151

1152
	dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq;
1153 1154 1155 1156 1157

	if (IS_VALLEYVIEW(dev_priv->dev))
		valleyview_set_rps(dev_priv->dev, new_delay);
	else
		gen6_set_rps(dev_priv->dev, new_delay);
1158

1159
	mutex_unlock(&dev_priv->rps.hw_lock);
1160 1161
}

1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173

/**
 * ivybridge_parity_work - Workqueue called when a parity error interrupt
 * occurred.
 * @work: workqueue struct
 *
 * Doesn't actually do anything except notify userspace. As a consequence of
 * this event, userspace should try to remap the bad rows since statistically
 * it is likely the same row is more likely to go bad again.
 */
static void ivybridge_parity_work(struct work_struct *work)
{
1174 1175
	struct drm_i915_private *dev_priv =
		container_of(work, struct drm_i915_private, l3_parity.error_work);
1176
	u32 error_status, row, bank, subbank;
1177
	char *parity_event[6];
1178 1179
	uint32_t misccpctl;
	unsigned long flags;
1180
	uint8_t slice = 0;
1181 1182 1183 1184 1185 1186 1187

	/* We must turn off DOP level clock gating to access the L3 registers.
	 * In order to prevent a get/put style interface, acquire struct mutex
	 * any time we access those registers.
	 */
	mutex_lock(&dev_priv->dev->struct_mutex);

1188 1189 1190 1191
	/* If we've screwed up tracking, just let the interrupt fire again */
	if (WARN_ON(!dev_priv->l3_parity.which_slice))
		goto out;

1192 1193 1194 1195
	misccpctl = I915_READ(GEN7_MISCCPCTL);
	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
	POSTING_READ(GEN7_MISCCPCTL);

1196 1197
	while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
		u32 reg;
1198

1199 1200 1201
		slice--;
		if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
			break;
1202

1203
		dev_priv->l3_parity.which_slice &= ~(1<<slice);
1204

1205
		reg = GEN7_L3CDERRST1 + (slice * 0x200);
1206

1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221
		error_status = I915_READ(reg);
		row = GEN7_PARITY_ERROR_ROW(error_status);
		bank = GEN7_PARITY_ERROR_BANK(error_status);
		subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);

		I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
		POSTING_READ(reg);

		parity_event[0] = I915_L3_PARITY_UEVENT "=1";
		parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
		parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
		parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
		parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
		parity_event[5] = NULL;

1222
		kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1223
				   KOBJ_CHANGE, parity_event);
1224

1225 1226
		DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
			  slice, row, bank, subbank);
1227

1228 1229 1230 1231 1232
		kfree(parity_event[4]);
		kfree(parity_event[3]);
		kfree(parity_event[2]);
		kfree(parity_event[1]);
	}
1233

1234
	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1235

1236 1237 1238 1239 1240 1241 1242
out:
	WARN_ON(dev_priv->l3_parity.which_slice);
	spin_lock_irqsave(&dev_priv->irq_lock, flags);
	ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);

	mutex_unlock(&dev_priv->dev->struct_mutex);
1243 1244
}

1245
static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1246
{
1247
	struct drm_i915_private *dev_priv = dev->dev_private;
1248

1249
	if (!HAS_L3_DPF(dev))
1250 1251
		return;

1252
	spin_lock(&dev_priv->irq_lock);
1253
	ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1254
	spin_unlock(&dev_priv->irq_lock);
1255

1256 1257 1258 1259 1260 1261 1262
	iir &= GT_PARITY_ERROR(dev);
	if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
		dev_priv->l3_parity.which_slice |= 1 << 1;

	if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
		dev_priv->l3_parity.which_slice |= 1 << 0;

1263
	queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1264 1265
}

1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276
static void ilk_gt_irq_handler(struct drm_device *dev,
			       struct drm_i915_private *dev_priv,
			       u32 gt_iir)
{
	if (gt_iir &
	    (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
		notify_ring(dev, &dev_priv->ring[RCS]);
	if (gt_iir & ILK_BSD_USER_INTERRUPT)
		notify_ring(dev, &dev_priv->ring[VCS]);
}

1277 1278 1279 1280 1281
static void snb_gt_irq_handler(struct drm_device *dev,
			       struct drm_i915_private *dev_priv,
			       u32 gt_iir)
{

1282 1283
	if (gt_iir &
	    (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1284
		notify_ring(dev, &dev_priv->ring[RCS]);
1285
	if (gt_iir & GT_BSD_USER_INTERRUPT)
1286
		notify_ring(dev, &dev_priv->ring[VCS]);
1287
	if (gt_iir & GT_BLT_USER_INTERRUPT)
1288 1289
		notify_ring(dev, &dev_priv->ring[BCS]);

1290 1291 1292
	if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
		      GT_BSD_CS_ERROR_INTERRUPT |
		      GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
1293 1294
		i915_handle_error(dev, false, "GT error interrupt 0x%08x",
				  gt_iir);
1295
	}
1296

1297 1298
	if (gt_iir & GT_PARITY_ERROR(dev))
		ivybridge_parity_error_irq_handler(dev, gt_iir);
1299 1300
}

1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350
static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
				       struct drm_i915_private *dev_priv,
				       u32 master_ctl)
{
	u32 rcs, bcs, vcs;
	uint32_t tmp = 0;
	irqreturn_t ret = IRQ_NONE;

	if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
		tmp = I915_READ(GEN8_GT_IIR(0));
		if (tmp) {
			ret = IRQ_HANDLED;
			rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
			bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
			if (rcs & GT_RENDER_USER_INTERRUPT)
				notify_ring(dev, &dev_priv->ring[RCS]);
			if (bcs & GT_RENDER_USER_INTERRUPT)
				notify_ring(dev, &dev_priv->ring[BCS]);
			I915_WRITE(GEN8_GT_IIR(0), tmp);
		} else
			DRM_ERROR("The master control interrupt lied (GT0)!\n");
	}

	if (master_ctl & GEN8_GT_VCS1_IRQ) {
		tmp = I915_READ(GEN8_GT_IIR(1));
		if (tmp) {
			ret = IRQ_HANDLED;
			vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
			if (vcs & GT_RENDER_USER_INTERRUPT)
				notify_ring(dev, &dev_priv->ring[VCS]);
			I915_WRITE(GEN8_GT_IIR(1), tmp);
		} else
			DRM_ERROR("The master control interrupt lied (GT1)!\n");
	}

	if (master_ctl & GEN8_GT_VECS_IRQ) {
		tmp = I915_READ(GEN8_GT_IIR(3));
		if (tmp) {
			ret = IRQ_HANDLED;
			vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
			if (vcs & GT_RENDER_USER_INTERRUPT)
				notify_ring(dev, &dev_priv->ring[VECS]);
			I915_WRITE(GEN8_GT_IIR(3), tmp);
		} else
			DRM_ERROR("The master control interrupt lied (GT3)!\n");
	}

	return ret;
}

1351 1352 1353
#define HPD_STORM_DETECT_PERIOD 1000
#define HPD_STORM_THRESHOLD 5

1354
static inline void intel_hpd_irq_handler(struct drm_device *dev,
1355 1356
					 u32 hotplug_trigger,
					 const u32 *hpd)
1357
{
1358
	struct drm_i915_private *dev_priv = dev->dev_private;
1359
	int i;
1360
	bool storm_detected = false;
1361

1362 1363 1364
	if (!hotplug_trigger)
		return;

1365 1366 1367
	DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
			  hotplug_trigger);

1368
	spin_lock(&dev_priv->irq_lock);
1369
	for (i = 1; i < HPD_NUM_PINS; i++) {
1370

1371
		WARN_ONCE(hpd[i] & hotplug_trigger &&
1372
			  dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED,
1373 1374
			  "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
			  hotplug_trigger, i, hpd[i]);
1375

1376 1377 1378 1379
		if (!(hpd[i] & hotplug_trigger) ||
		    dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
			continue;

1380
		dev_priv->hpd_event_bits |= (1 << i);
1381 1382 1383 1384 1385
		if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
				   dev_priv->hpd_stats[i].hpd_last_jiffies
				   + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
			dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
			dev_priv->hpd_stats[i].hpd_cnt = 0;
1386
			DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1387 1388
		} else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
			dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1389
			dev_priv->hpd_event_bits &= ~(1 << i);
1390
			DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1391
			storm_detected = true;
1392 1393
		} else {
			dev_priv->hpd_stats[i].hpd_cnt++;
1394 1395
			DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
				      dev_priv->hpd_stats[i].hpd_cnt);
1396 1397 1398
		}
	}

1399 1400
	if (storm_detected)
		dev_priv->display.hpd_irq_setup(dev);
1401
	spin_unlock(&dev_priv->irq_lock);
1402

1403 1404 1405 1406 1407 1408 1409
	/*
	 * Our hotplug handler can grab modeset locks (by calling down into the
	 * fb helpers). Hence it must not be run on our own dev-priv->wq work
	 * queue for otherwise the flush_work in the pageflip code will
	 * deadlock.
	 */
	schedule_work(&dev_priv->hotplug_work);
1410 1411
}

1412 1413
static void gmbus_irq_handler(struct drm_device *dev)
{
1414
	struct drm_i915_private *dev_priv = dev->dev_private;
1415 1416

	wake_up_all(&dev_priv->gmbus_wait_queue);
1417 1418
}

1419 1420
static void dp_aux_irq_handler(struct drm_device *dev)
{
1421
	struct drm_i915_private *dev_priv = dev->dev_private;
1422 1423

	wake_up_all(&dev_priv->gmbus_wait_queue);
1424 1425
}

1426
#if defined(CONFIG_DEBUG_FS)
1427 1428 1429 1430
static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
					 uint32_t crc0, uint32_t crc1,
					 uint32_t crc2, uint32_t crc3,
					 uint32_t crc4)
1431 1432 1433 1434
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
	struct intel_pipe_crc_entry *entry;
1435
	int head, tail;
1436

1437 1438
	spin_lock(&pipe_crc->lock);

1439
	if (!pipe_crc->entries) {
1440
		spin_unlock(&pipe_crc->lock);
1441 1442 1443 1444
		DRM_ERROR("spurious interrupt\n");
		return;
	}

1445 1446
	head = pipe_crc->head;
	tail = pipe_crc->tail;
1447 1448

	if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1449
		spin_unlock(&pipe_crc->lock);
1450 1451 1452 1453 1454
		DRM_ERROR("CRC buffer overflowing\n");
		return;
	}

	entry = &pipe_crc->entries[head];
1455

1456
	entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1457 1458 1459 1460 1461
	entry->crc[0] = crc0;
	entry->crc[1] = crc1;
	entry->crc[2] = crc2;
	entry->crc[3] = crc3;
	entry->crc[4] = crc4;
1462 1463

	head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1464 1465 1466
	pipe_crc->head = head;

	spin_unlock(&pipe_crc->lock);
1467 1468

	wake_up_interruptible(&pipe_crc->wq);
1469
}
1470 1471 1472 1473 1474 1475 1476 1477
#else
static inline void
display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
			     uint32_t crc0, uint32_t crc1,
			     uint32_t crc2, uint32_t crc3,
			     uint32_t crc4) {}
#endif

1478

1479
static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
D
Daniel Vetter 已提交
1480 1481 1482
{
	struct drm_i915_private *dev_priv = dev->dev_private;

1483 1484 1485
	display_pipe_crc_irq_handler(dev, pipe,
				     I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
				     0, 0, 0, 0);
D
Daniel Vetter 已提交
1486 1487
}

1488
static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1489 1490 1491
{
	struct drm_i915_private *dev_priv = dev->dev_private;

1492 1493 1494 1495 1496 1497
	display_pipe_crc_irq_handler(dev, pipe,
				     I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
				     I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
				     I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
				     I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
				     I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1498
}
1499

1500
static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1501 1502
{
	struct drm_i915_private *dev_priv = dev->dev_private;
1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513
	uint32_t res1, res2;

	if (INTEL_INFO(dev)->gen >= 3)
		res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
	else
		res1 = 0;

	if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
		res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
	else
		res2 = 0;
1514

1515 1516 1517 1518 1519
	display_pipe_crc_irq_handler(dev, pipe,
				     I915_READ(PIPE_CRC_RES_RED(pipe)),
				     I915_READ(PIPE_CRC_RES_GREEN(pipe)),
				     I915_READ(PIPE_CRC_RES_BLUE(pipe)),
				     res1, res2);
1520
}
1521

1522 1523 1524 1525
/* The RPS events need forcewake, so we add them to a work queue and mask their
 * IMR bits until the work is done. Other interrupts can be processed without
 * the work queue. */
static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1526
{
1527
	if (pm_iir & dev_priv->pm_rps_events) {
1528
		spin_lock(&dev_priv->irq_lock);
1529 1530
		dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
		snb_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1531
		spin_unlock(&dev_priv->irq_lock);
1532 1533

		queue_work(dev_priv->wq, &dev_priv->rps.work);
1534 1535
	}

1536 1537 1538
	if (HAS_VEBOX(dev_priv->dev)) {
		if (pm_iir & PM_VEBOX_USER_INTERRUPT)
			notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
B
Ben Widawsky 已提交
1539

1540
		if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1541 1542 1543
			i915_handle_error(dev_priv->dev, false,
					  "VEBOX CS error interrupt 0x%08x",
					  pm_iir);
1544
		}
B
Ben Widawsky 已提交
1545
	}
1546 1547
}

1548 1549 1550
static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
1551
	u32 pipe_stats[I915_MAX_PIPES] = { };
1552 1553
	int pipe;

1554
	spin_lock(&dev_priv->irq_lock);
1555
	for_each_pipe(pipe) {
1556
		int reg;
1557
		u32 mask, iir_bit = 0;
1558

1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581
		/*
		 * PIPESTAT bits get signalled even when the interrupt is
		 * disabled with the mask bits, and some of the status bits do
		 * not generate interrupts at all (like the underrun bit). Hence
		 * we need to be careful that we only handle what we want to
		 * handle.
		 */
		mask = 0;
		if (__cpu_fifo_underrun_reporting_enabled(dev, pipe))
			mask |= PIPE_FIFO_UNDERRUN_STATUS;

		switch (pipe) {
		case PIPE_A:
			iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
			break;
		case PIPE_B:
			iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
			break;
		}
		if (iir & iir_bit)
			mask |= dev_priv->pipestat_irq_mask[pipe];

		if (!mask)
1582 1583 1584
			continue;

		reg = PIPESTAT(pipe);
1585 1586
		mask |= PIPESTAT_INT_ENABLE_MASK;
		pipe_stats[pipe] = I915_READ(reg) & mask;
1587 1588 1589 1590

		/*
		 * Clear the PIPE*STAT regs before the IIR
		 */
1591 1592
		if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
					PIPESTAT_INT_STATUS_MASK))
1593 1594
			I915_WRITE(reg, pipe_stats[pipe]);
	}
1595
	spin_unlock(&dev_priv->irq_lock);
1596 1597 1598 1599 1600

	for_each_pipe(pipe) {
		if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
			drm_handle_vblank(dev, pipe);

1601
		if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617
			intel_prepare_page_flip(dev, pipe);
			intel_finish_page_flip(dev, pipe);
		}

		if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
			i9xx_pipe_crc_irq_handler(dev, pipe);

		if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
		    intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
			DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
	}

	if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
		gmbus_irq_handler(dev);
}

1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644
static void i9xx_hpd_irq_handler(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);

	if (IS_G4X(dev)) {
		u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;

		intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_g4x);
	} else {
		u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;

		intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
	}

	if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) &&
	    hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
		dp_aux_irq_handler(dev);

	I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
	/*
	 * Make sure hotplug status is cleared before we clear IIR, or else we
	 * may miss hotplug events.
	 */
	POSTING_READ(PORT_HOTPLUG_STAT);
}

1645
static irqreturn_t valleyview_irq_handler(int irq, void *arg)
J
Jesse Barnes 已提交
1646 1647
{
	struct drm_device *dev = (struct drm_device *) arg;
1648
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661
	u32 iir, gt_iir, pm_iir;
	irqreturn_t ret = IRQ_NONE;

	while (true) {
		iir = I915_READ(VLV_IIR);
		gt_iir = I915_READ(GTIIR);
		pm_iir = I915_READ(GEN6_PMIIR);

		if (gt_iir == 0 && pm_iir == 0 && iir == 0)
			goto out;

		ret = IRQ_HANDLED;

1662
		snb_gt_irq_handler(dev, dev_priv, gt_iir);
J
Jesse Barnes 已提交
1663

1664
		valleyview_pipestat_irq_handler(dev, iir);
1665

J
Jesse Barnes 已提交
1666
		/* Consume port.  Then clear IIR or we'll miss events */
1667 1668
		if (iir & I915_DISPLAY_PORT_INTERRUPT)
			i9xx_hpd_irq_handler(dev);
J
Jesse Barnes 已提交
1669

1670
		if (pm_iir)
1671
			gen6_rps_irq_handler(dev_priv, pm_iir);
J
Jesse Barnes 已提交
1672 1673 1674 1675 1676 1677 1678 1679 1680 1681

		I915_WRITE(GTIIR, gt_iir);
		I915_WRITE(GEN6_PMIIR, pm_iir);
		I915_WRITE(VLV_IIR, iir);
	}

out:
	return ret;
}

1682
static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1683
{
1684
	struct drm_i915_private *dev_priv = dev->dev_private;
1685
	int pipe;
1686
	u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1687

1688 1689
	intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);

1690 1691 1692
	if (pch_iir & SDE_AUDIO_POWER_MASK) {
		int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
			       SDE_AUDIO_POWER_SHIFT);
1693
		DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1694 1695
				 port_name(port));
	}
1696

1697 1698 1699
	if (pch_iir & SDE_AUX_MASK)
		dp_aux_irq_handler(dev);

1700
	if (pch_iir & SDE_GMBUS)
1701
		gmbus_irq_handler(dev);
1702 1703 1704 1705 1706 1707 1708 1709 1710 1711

	if (pch_iir & SDE_AUDIO_HDCP_MASK)
		DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");

	if (pch_iir & SDE_AUDIO_TRANS_MASK)
		DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");

	if (pch_iir & SDE_POISON)
		DRM_ERROR("PCH poison interrupt\n");

1712 1713 1714 1715 1716
	if (pch_iir & SDE_FDI_MASK)
		for_each_pipe(pipe)
			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
					 pipe_name(pipe),
					 I915_READ(FDI_RX_IIR(pipe)));
1717 1718 1719 1720 1721 1722 1723 1724

	if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
		DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");

	if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
		DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");

	if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1725 1726
		if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
							  false))
1727
			DRM_ERROR("PCH transcoder A FIFO underrun\n");
1728 1729 1730 1731

	if (pch_iir & SDE_TRANSB_FIFO_UNDER)
		if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
							  false))
1732
			DRM_ERROR("PCH transcoder B FIFO underrun\n");
1733 1734 1735 1736 1737 1738
}

static void ivb_err_int_handler(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 err_int = I915_READ(GEN7_ERR_INT);
D
Daniel Vetter 已提交
1739
	enum pipe pipe;
1740

1741 1742 1743
	if (err_int & ERR_INT_POISON)
		DRM_ERROR("Poison interrupt\n");

D
Daniel Vetter 已提交
1744 1745 1746 1747
	for_each_pipe(pipe) {
		if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
			if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
								  false))
1748 1749
				DRM_ERROR("Pipe %c FIFO underrun\n",
					  pipe_name(pipe));
D
Daniel Vetter 已提交
1750
		}
1751

D
Daniel Vetter 已提交
1752 1753
		if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
			if (IS_IVYBRIDGE(dev))
1754
				ivb_pipe_crc_irq_handler(dev, pipe);
D
Daniel Vetter 已提交
1755
			else
1756
				hsw_pipe_crc_irq_handler(dev, pipe);
D
Daniel Vetter 已提交
1757 1758
		}
	}
1759

1760 1761 1762 1763 1764 1765 1766 1767
	I915_WRITE(GEN7_ERR_INT, err_int);
}

static void cpt_serr_int_handler(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 serr_int = I915_READ(SERR_INT);

1768 1769 1770
	if (serr_int & SERR_INT_POISON)
		DRM_ERROR("PCH poison interrupt\n");

1771 1772 1773
	if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
		if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
							  false))
1774
			DRM_ERROR("PCH transcoder A FIFO underrun\n");
1775 1776 1777 1778

	if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
		if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
							  false))
1779
			DRM_ERROR("PCH transcoder B FIFO underrun\n");
1780 1781 1782 1783

	if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
		if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
							  false))
1784
			DRM_ERROR("PCH transcoder C FIFO underrun\n");
1785 1786

	I915_WRITE(SERR_INT, serr_int);
1787 1788
}

1789 1790
static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
{
1791
	struct drm_i915_private *dev_priv = dev->dev_private;
1792
	int pipe;
1793
	u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1794

1795 1796
	intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);

1797 1798 1799 1800 1801 1802
	if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
		int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
			       SDE_AUDIO_POWER_SHIFT_CPT);
		DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
				 port_name(port));
	}
1803 1804

	if (pch_iir & SDE_AUX_MASK_CPT)
1805
		dp_aux_irq_handler(dev);
1806 1807

	if (pch_iir & SDE_GMBUS_CPT)
1808
		gmbus_irq_handler(dev);
1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820

	if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
		DRM_DEBUG_DRIVER("Audio CP request interrupt\n");

	if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
		DRM_DEBUG_DRIVER("Audio CP change interrupt\n");

	if (pch_iir & SDE_FDI_MASK_CPT)
		for_each_pipe(pipe)
			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
					 pipe_name(pipe),
					 I915_READ(FDI_RX_IIR(pipe)));
1821 1822 1823

	if (pch_iir & SDE_ERROR_CPT)
		cpt_serr_int_handler(dev);
1824 1825
}

1826 1827 1828
static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
1829
	enum pipe pipe;
1830 1831 1832 1833 1834 1835 1836 1837 1838 1839

	if (de_iir & DE_AUX_CHANNEL_A)
		dp_aux_irq_handler(dev);

	if (de_iir & DE_GSE)
		intel_opregion_asle_intr(dev);

	if (de_iir & DE_POISON)
		DRM_ERROR("Poison interrupt\n");

1840 1841 1842
	for_each_pipe(pipe) {
		if (de_iir & DE_PIPE_VBLANK(pipe))
			drm_handle_vblank(dev, pipe);
1843

1844 1845
		if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
			if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1846 1847
				DRM_ERROR("Pipe %c FIFO underrun\n",
					  pipe_name(pipe));
1848

1849 1850
		if (de_iir & DE_PIPE_CRC_DONE(pipe))
			i9xx_pipe_crc_irq_handler(dev, pipe);
1851

1852 1853 1854 1855 1856
		/* plane/pipes map 1:1 on ilk+ */
		if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
			intel_prepare_page_flip(dev, pipe);
			intel_finish_page_flip_plane(dev, pipe);
		}
1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875
	}

	/* check event from PCH */
	if (de_iir & DE_PCH_EVENT) {
		u32 pch_iir = I915_READ(SDEIIR);

		if (HAS_PCH_CPT(dev))
			cpt_irq_handler(dev, pch_iir);
		else
			ibx_irq_handler(dev, pch_iir);

		/* should clear PCH hotplug event before clear CPU irq */
		I915_WRITE(SDEIIR, pch_iir);
	}

	if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
		ironlake_rps_change_irq_handler(dev);
}

1876 1877 1878
static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
1879
	enum pipe pipe;
1880 1881 1882 1883 1884 1885 1886 1887 1888 1889

	if (de_iir & DE_ERR_INT_IVB)
		ivb_err_int_handler(dev);

	if (de_iir & DE_AUX_CHANNEL_A_IVB)
		dp_aux_irq_handler(dev);

	if (de_iir & DE_GSE_IVB)
		intel_opregion_asle_intr(dev);

1890 1891 1892
	for_each_pipe(pipe) {
		if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
			drm_handle_vblank(dev, pipe);
1893 1894

		/* plane/pipes map 1:1 on ilk+ */
1895 1896 1897
		if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
			intel_prepare_page_flip(dev, pipe);
			intel_finish_page_flip_plane(dev, pipe);
1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911
		}
	}

	/* check event from PCH */
	if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
		u32 pch_iir = I915_READ(SDEIIR);

		cpt_irq_handler(dev, pch_iir);

		/* clear PCH hotplug event before clear CPU irq */
		I915_WRITE(SDEIIR, pch_iir);
	}
}

1912
static irqreturn_t ironlake_irq_handler(int irq, void *arg)
1913 1914
{
	struct drm_device *dev = (struct drm_device *) arg;
1915
	struct drm_i915_private *dev_priv = dev->dev_private;
1916
	u32 de_iir, gt_iir, de_ier, sde_ier = 0;
1917
	irqreturn_t ret = IRQ_NONE;
1918

1919 1920
	/* We get interrupts on unclaimed registers, so check for this before we
	 * do any I915_{READ,WRITE}. */
1921
	intel_uncore_check_errors(dev);
1922

1923 1924 1925
	/* disable master interrupt before clearing iir  */
	de_ier = I915_READ(DEIER);
	I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
1926
	POSTING_READ(DEIER);
1927

1928 1929 1930 1931 1932
	/* Disable south interrupts. We'll only write to SDEIIR once, so further
	 * interrupts will will be stored on its back queue, and then we'll be
	 * able to process them after we restore SDEIER (as soon as we restore
	 * it, we'll get an interrupt if SDEIIR still has something to process
	 * due to its back queue). */
1933 1934 1935 1936 1937
	if (!HAS_PCH_NOP(dev)) {
		sde_ier = I915_READ(SDEIER);
		I915_WRITE(SDEIER, 0);
		POSTING_READ(SDEIER);
	}
1938

1939
	gt_iir = I915_READ(GTIIR);
1940
	if (gt_iir) {
1941
		if (INTEL_INFO(dev)->gen >= 6)
1942
			snb_gt_irq_handler(dev, dev_priv, gt_iir);
1943 1944
		else
			ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1945 1946
		I915_WRITE(GTIIR, gt_iir);
		ret = IRQ_HANDLED;
1947 1948
	}

1949 1950
	de_iir = I915_READ(DEIIR);
	if (de_iir) {
1951 1952 1953 1954
		if (INTEL_INFO(dev)->gen >= 7)
			ivb_display_irq_handler(dev, de_iir);
		else
			ilk_display_irq_handler(dev, de_iir);
1955 1956
		I915_WRITE(DEIIR, de_iir);
		ret = IRQ_HANDLED;
1957 1958
	}

1959 1960 1961
	if (INTEL_INFO(dev)->gen >= 6) {
		u32 pm_iir = I915_READ(GEN6_PMIIR);
		if (pm_iir) {
1962
			gen6_rps_irq_handler(dev_priv, pm_iir);
1963 1964 1965
			I915_WRITE(GEN6_PMIIR, pm_iir);
			ret = IRQ_HANDLED;
		}
1966
	}
1967 1968 1969

	I915_WRITE(DEIER, de_ier);
	POSTING_READ(DEIER);
1970 1971 1972 1973
	if (!HAS_PCH_NOP(dev)) {
		I915_WRITE(SDEIER, sde_ier);
		POSTING_READ(SDEIER);
	}
1974 1975 1976 1977

	return ret;
}

1978 1979 1980 1981 1982 1983 1984
static irqreturn_t gen8_irq_handler(int irq, void *arg)
{
	struct drm_device *dev = arg;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 master_ctl;
	irqreturn_t ret = IRQ_NONE;
	uint32_t tmp = 0;
1985
	enum pipe pipe;
1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011

	master_ctl = I915_READ(GEN8_MASTER_IRQ);
	master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
	if (!master_ctl)
		return IRQ_NONE;

	I915_WRITE(GEN8_MASTER_IRQ, 0);
	POSTING_READ(GEN8_MASTER_IRQ);

	ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);

	if (master_ctl & GEN8_DE_MISC_IRQ) {
		tmp = I915_READ(GEN8_DE_MISC_IIR);
		if (tmp & GEN8_DE_MISC_GSE)
			intel_opregion_asle_intr(dev);
		else if (tmp)
			DRM_ERROR("Unexpected DE Misc interrupt\n");
		else
			DRM_ERROR("The master control interrupt lied (DE MISC)!\n");

		if (tmp) {
			I915_WRITE(GEN8_DE_MISC_IIR, tmp);
			ret = IRQ_HANDLED;
		}
	}

2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026
	if (master_ctl & GEN8_DE_PORT_IRQ) {
		tmp = I915_READ(GEN8_DE_PORT_IIR);
		if (tmp & GEN8_AUX_CHANNEL_A)
			dp_aux_irq_handler(dev);
		else if (tmp)
			DRM_ERROR("Unexpected DE Port interrupt\n");
		else
			DRM_ERROR("The master control interrupt lied (DE PORT)!\n");

		if (tmp) {
			I915_WRITE(GEN8_DE_PORT_IIR, tmp);
			ret = IRQ_HANDLED;
		}
	}

2027 2028
	for_each_pipe(pipe) {
		uint32_t pipe_iir;
2029

2030 2031
		if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
			continue;
2032

2033 2034 2035
		pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
		if (pipe_iir & GEN8_PIPE_VBLANK)
			drm_handle_vblank(dev, pipe);
2036

2037 2038 2039
		if (pipe_iir & GEN8_PIPE_FLIP_DONE) {
			intel_prepare_page_flip(dev, pipe);
			intel_finish_page_flip_plane(dev, pipe);
2040
		}
2041

2042 2043 2044
		if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
			hsw_pipe_crc_irq_handler(dev, pipe);

2045 2046 2047
		if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
			if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
								  false))
2048 2049
				DRM_ERROR("Pipe %c FIFO underrun\n",
					  pipe_name(pipe));
2050 2051
		}

2052 2053 2054 2055 2056
		if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) {
			DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
				  pipe_name(pipe),
				  pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
		}
2057 2058 2059 2060 2061

		if (pipe_iir) {
			ret = IRQ_HANDLED;
			I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
		} else
2062 2063 2064
			DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
	}

2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080
	if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
		/*
		 * FIXME(BDW): Assume for now that the new interrupt handling
		 * scheme also closed the SDE interrupt handling race we've seen
		 * on older pch-split platforms. But this needs testing.
		 */
		u32 pch_iir = I915_READ(SDEIIR);

		cpt_irq_handler(dev, pch_iir);

		if (pch_iir) {
			I915_WRITE(SDEIIR, pch_iir);
			ret = IRQ_HANDLED;
		}
	}

2081 2082 2083 2084 2085 2086
	I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
	POSTING_READ(GEN8_MASTER_IRQ);

	return ret;
}

2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114
static void i915_error_wake_up(struct drm_i915_private *dev_priv,
			       bool reset_completed)
{
	struct intel_ring_buffer *ring;
	int i;

	/*
	 * Notify all waiters for GPU completion events that reset state has
	 * been changed, and that they need to restart their wait after
	 * checking for potential errors (and bail out to drop locks if there is
	 * a gpu reset pending so that i915_error_work_func can acquire them).
	 */

	/* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
	for_each_ring(ring, dev_priv, i)
		wake_up_all(&ring->irq_queue);

	/* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
	wake_up_all(&dev_priv->pending_flip_queue);

	/*
	 * Signal tasks blocked in i915_gem_wait_for_error that the pending
	 * reset state is cleared.
	 */
	if (reset_completed)
		wake_up_all(&dev_priv->gpu_error.reset_queue);
}

2115 2116 2117 2118 2119 2120 2121 2122 2123
/**
 * i915_error_work_func - do process context error handling work
 * @work: work struct
 *
 * Fire an error uevent so userspace can see that a hang or error
 * was detected.
 */
static void i915_error_work_func(struct work_struct *work)
{
2124 2125
	struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
						    work);
2126 2127
	struct drm_i915_private *dev_priv =
		container_of(error, struct drm_i915_private, gpu_error);
2128
	struct drm_device *dev = dev_priv->dev;
2129 2130 2131
	char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
	char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
	char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2132
	int ret;
2133

2134
	kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2135

2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146
	/*
	 * Note that there's only one work item which does gpu resets, so we
	 * need not worry about concurrent gpu resets potentially incrementing
	 * error->reset_counter twice. We only need to take care of another
	 * racing irq/hangcheck declaring the gpu dead for a second time. A
	 * quick check for that is good enough: schedule_work ensures the
	 * correct ordering between hang detection and this work item, and since
	 * the reset in-progress bit is only ever set by code outside of this
	 * work we don't need to worry about any other races.
	 */
	if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2147
		DRM_DEBUG_DRIVER("resetting chip\n");
2148
		kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2149
				   reset_event);
2150

2151 2152 2153 2154 2155 2156
		/*
		 * All state reset _must_ be completed before we update the
		 * reset counter, for otherwise waiters might miss the reset
		 * pending state and not properly drop locks, resulting in
		 * deadlocks with the reset work.
		 */
2157 2158
		ret = i915_reset(dev);

2159 2160
		intel_display_handle_reset(dev);

2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174
		if (ret == 0) {
			/*
			 * After all the gem state is reset, increment the reset
			 * counter and wake up everyone waiting for the reset to
			 * complete.
			 *
			 * Since unlock operations are a one-sided barrier only,
			 * we need to insert a barrier here to order any seqno
			 * updates before
			 * the counter increment.
			 */
			smp_mb__before_atomic_inc();
			atomic_inc(&dev_priv->gpu_error.reset_counter);

2175
			kobject_uevent_env(&dev->primary->kdev->kobj,
2176
					   KOBJ_CHANGE, reset_done_event);
2177
		} else {
M
Mika Kuoppala 已提交
2178
			atomic_set_mask(I915_WEDGED, &error->reset_counter);
2179
		}
2180

2181 2182 2183 2184 2185
		/*
		 * Note: The wake_up also serves as a memory barrier so that
		 * waiters see the update value of the reset counter atomic_t.
		 */
		i915_error_wake_up(dev_priv, true);
2186
	}
2187 2188
}

2189
static void i915_report_and_clear_eir(struct drm_device *dev)
2190 2191
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2192
	uint32_t instdone[I915_NUM_INSTDONE_REG];
2193
	u32 eir = I915_READ(EIR);
2194
	int pipe, i;
2195

2196 2197
	if (!eir)
		return;
2198

2199
	pr_err("render error detected, EIR: 0x%08x\n", eir);
2200

2201 2202
	i915_get_extra_instdone(dev, instdone);

2203 2204 2205 2206
	if (IS_G4X(dev)) {
		if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
			u32 ipeir = I915_READ(IPEIR_I965);

2207 2208
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2209 2210
			for (i = 0; i < ARRAY_SIZE(instdone); i++)
				pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2211 2212
			pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2213
			I915_WRITE(IPEIR_I965, ipeir);
2214
			POSTING_READ(IPEIR_I965);
2215 2216 2217
		}
		if (eir & GM45_ERROR_PAGE_TABLE) {
			u32 pgtbl_err = I915_READ(PGTBL_ER);
2218 2219
			pr_err("page table error\n");
			pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2220
			I915_WRITE(PGTBL_ER, pgtbl_err);
2221
			POSTING_READ(PGTBL_ER);
2222 2223 2224
		}
	}

2225
	if (!IS_GEN2(dev)) {
2226 2227
		if (eir & I915_ERROR_PAGE_TABLE) {
			u32 pgtbl_err = I915_READ(PGTBL_ER);
2228 2229
			pr_err("page table error\n");
			pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2230
			I915_WRITE(PGTBL_ER, pgtbl_err);
2231
			POSTING_READ(PGTBL_ER);
2232 2233 2234 2235
		}
	}

	if (eir & I915_ERROR_MEMORY_REFRESH) {
2236
		pr_err("memory refresh error:\n");
2237
		for_each_pipe(pipe)
2238
			pr_err("pipe %c stat: 0x%08x\n",
2239
			       pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2240 2241 2242
		/* pipestat has already been acked */
	}
	if (eir & I915_ERROR_INSTRUCTION) {
2243 2244
		pr_err("instruction error\n");
		pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
2245 2246
		for (i = 0; i < ARRAY_SIZE(instdone); i++)
			pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2247
		if (INTEL_INFO(dev)->gen < 4) {
2248 2249
			u32 ipeir = I915_READ(IPEIR);

2250 2251 2252
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
2253
			I915_WRITE(IPEIR, ipeir);
2254
			POSTING_READ(IPEIR);
2255 2256 2257
		} else {
			u32 ipeir = I915_READ(IPEIR_I965);

2258 2259 2260 2261
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
			pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2262
			I915_WRITE(IPEIR_I965, ipeir);
2263
			POSTING_READ(IPEIR_I965);
2264 2265 2266 2267
		}
	}

	I915_WRITE(EIR, eir);
2268
	POSTING_READ(EIR);
2269 2270 2271 2272 2273 2274 2275 2276 2277 2278
	eir = I915_READ(EIR);
	if (eir) {
		/*
		 * some errors might have become stuck,
		 * mask them.
		 */
		DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
		I915_WRITE(EMR, I915_READ(EMR) | eir);
		I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
	}
2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290
}

/**
 * i915_handle_error - handle an error interrupt
 * @dev: drm device
 *
 * Do some basic checking of regsiter state at error interrupt time and
 * dump it to the syslog.  Also call i915_capture_error_state() to make
 * sure we get a record and make it available in debugfs.  Fire a uevent
 * so userspace knows something bad happened (should trigger collection
 * of a ring dump etc.).
 */
2291 2292
void i915_handle_error(struct drm_device *dev, bool wedged,
		       const char *fmt, ...)
2293 2294
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2295 2296
	va_list args;
	char error_msg[80];
2297

2298 2299 2300 2301 2302
	va_start(args, fmt);
	vscnprintf(error_msg, sizeof(error_msg), fmt, args);
	va_end(args);

	i915_capture_error_state(dev, wedged, error_msg);
2303
	i915_report_and_clear_eir(dev);
2304

2305
	if (wedged) {
2306 2307
		atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
				&dev_priv->gpu_error.reset_counter);
2308

2309
		/*
2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320
		 * Wakeup waiting processes so that the reset work function
		 * i915_error_work_func doesn't deadlock trying to grab various
		 * locks. By bumping the reset counter first, the woken
		 * processes will see a reset in progress and back off,
		 * releasing their locks and then wait for the reset completion.
		 * We must do this for _all_ gpu waiters that might hold locks
		 * that the reset work needs to acquire.
		 *
		 * Note: The wake_up serves as the required memory barrier to
		 * ensure that the waiters see the updated value of the reset
		 * counter atomic_t.
2321
		 */
2322
		i915_error_wake_up(dev_priv, false);
2323 2324
	}

2325 2326 2327 2328 2329 2330 2331
	/*
	 * Our reset work can grab modeset locks (since it needs to reset the
	 * state of outstanding pagelips). Hence it must not be run on our own
	 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
	 * code will deadlock.
	 */
	schedule_work(&dev_priv->gpu_error.work);
2332 2333
}

2334
static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
2335
{
2336
	struct drm_i915_private *dev_priv = dev->dev_private;
2337 2338
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2339
	struct drm_i915_gem_object *obj;
2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350
	struct intel_unpin_work *work;
	unsigned long flags;
	bool stall_detected;

	/* Ignore early vblank irqs */
	if (intel_crtc == NULL)
		return;

	spin_lock_irqsave(&dev->event_lock, flags);
	work = intel_crtc->unpin_work;

2351 2352 2353
	if (work == NULL ||
	    atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
	    !work->enable_stall_check) {
2354 2355 2356 2357 2358 2359
		/* Either the pending flip IRQ arrived, or we're too early. Don't check */
		spin_unlock_irqrestore(&dev->event_lock, flags);
		return;
	}

	/* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2360
	obj = work->pending_flip_obj;
2361
	if (INTEL_INFO(dev)->gen >= 4) {
2362
		int dspsurf = DSPSURF(intel_crtc->plane);
2363
		stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
2364
					i915_gem_obj_ggtt_offset(obj);
2365
	} else {
2366
		int dspaddr = DSPADDR(intel_crtc->plane);
2367
		stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
2368
							crtc->y * crtc->fb->pitches[0] +
2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379
							crtc->x * crtc->fb->bits_per_pixel/8);
	}

	spin_unlock_irqrestore(&dev->event_lock, flags);

	if (stall_detected) {
		DRM_DEBUG_DRIVER("Pageflip stall detected\n");
		intel_prepare_page_flip(dev, intel_crtc->plane);
	}
}

2380 2381 2382
/* Called from drm generic code, passed 'crtc' which
 * we use as a pipe index
 */
2383
static int i915_enable_vblank(struct drm_device *dev, int pipe)
2384
{
2385
	struct drm_i915_private *dev_priv = dev->dev_private;
2386
	unsigned long irqflags;
2387

2388
	if (!i915_pipe_enabled(dev, pipe))
2389
		return -EINVAL;
2390

2391
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2392
	if (INTEL_INFO(dev)->gen >= 4)
2393
		i915_enable_pipestat(dev_priv, pipe,
2394
				     PIPE_START_VBLANK_INTERRUPT_STATUS);
2395
	else
2396
		i915_enable_pipestat(dev_priv, pipe,
2397
				     PIPE_VBLANK_INTERRUPT_STATUS);
2398 2399

	/* maintain vblank delivery even in deep C-states */
2400
	if (INTEL_INFO(dev)->gen == 3)
2401
		I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
2402
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2403

2404 2405 2406
	return 0;
}

2407
static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2408
{
2409
	struct drm_i915_private *dev_priv = dev->dev_private;
2410
	unsigned long irqflags;
2411
	uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2412
						     DE_PIPE_VBLANK(pipe);
2413 2414 2415 2416 2417

	if (!i915_pipe_enabled(dev, pipe))
		return -EINVAL;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2418
	ironlake_enable_display_irq(dev_priv, bit);
2419 2420 2421 2422 2423
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

	return 0;
}

J
Jesse Barnes 已提交
2424 2425
static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
{
2426
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
2427 2428 2429 2430 2431 2432
	unsigned long irqflags;

	if (!i915_pipe_enabled(dev, pipe))
		return -EINVAL;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2433
	i915_enable_pipestat(dev_priv, pipe,
2434
			     PIPE_START_VBLANK_INTERRUPT_STATUS);
J
Jesse Barnes 已提交
2435 2436 2437 2438 2439
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

	return 0;
}

2440 2441 2442 2443 2444 2445 2446 2447 2448
static int gen8_enable_vblank(struct drm_device *dev, int pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long irqflags;

	if (!i915_pipe_enabled(dev, pipe))
		return -EINVAL;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2449 2450 2451
	dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
	I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
	POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2452 2453 2454 2455
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
	return 0;
}

2456 2457 2458
/* Called from drm generic code, passed 'crtc' which
 * we use as a pipe index
 */
2459
static void i915_disable_vblank(struct drm_device *dev, int pipe)
2460
{
2461
	struct drm_i915_private *dev_priv = dev->dev_private;
2462
	unsigned long irqflags;
2463

2464
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2465
	if (INTEL_INFO(dev)->gen == 3)
2466
		I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
2467

2468
	i915_disable_pipestat(dev_priv, pipe,
2469 2470
			      PIPE_VBLANK_INTERRUPT_STATUS |
			      PIPE_START_VBLANK_INTERRUPT_STATUS);
2471 2472 2473
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

2474
static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2475
{
2476
	struct drm_i915_private *dev_priv = dev->dev_private;
2477
	unsigned long irqflags;
2478
	uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2479
						     DE_PIPE_VBLANK(pipe);
2480 2481

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2482
	ironlake_disable_display_irq(dev_priv, bit);
2483 2484 2485
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

J
Jesse Barnes 已提交
2486 2487
static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
{
2488
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
2489 2490 2491
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2492
	i915_disable_pipestat(dev_priv, pipe,
2493
			      PIPE_START_VBLANK_INTERRUPT_STATUS);
J
Jesse Barnes 已提交
2494 2495 2496
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

2497 2498 2499 2500 2501 2502 2503 2504 2505
static void gen8_disable_vblank(struct drm_device *dev, int pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long irqflags;

	if (!i915_pipe_enabled(dev, pipe))
		return;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2506 2507 2508
	dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
	I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
	POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2509 2510 2511
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

2512 2513
static u32
ring_last_seqno(struct intel_ring_buffer *ring)
2514
{
2515 2516 2517 2518
	return list_entry(ring->request_list.prev,
			  struct drm_i915_gem_request, list)->seqno;
}

2519 2520 2521 2522 2523
static bool
ring_idle(struct intel_ring_buffer *ring, u32 seqno)
{
	return (list_empty(&ring->request_list) ||
		i915_seqno_passed(seqno, ring_last_seqno(ring)));
B
Ben Gamari 已提交
2524 2525
}

2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542
static bool
ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
{
	if (INTEL_INFO(dev)->gen >= 8) {
		/*
		 * FIXME: gen8 semaphore support - currently we don't emit
		 * semaphores on bdw anyway, but this needs to be addressed when
		 * we merge that code.
		 */
		return false;
	} else {
		ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
		return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
				 MI_SEMAPHORE_REGISTER);
	}
}

2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575
static struct intel_ring_buffer *
semaphore_wait_to_signaller_ring(struct intel_ring_buffer *ring, u32 ipehr)
{
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
	struct intel_ring_buffer *signaller;
	int i;

	if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
		/*
		 * FIXME: gen8 semaphore support - currently we don't emit
		 * semaphores on bdw anyway, but this needs to be addressed when
		 * we merge that code.
		 */
		return NULL;
	} else {
		u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;

		for_each_ring(signaller, dev_priv, i) {
			if(ring == signaller)
				continue;

			if (sync_bits ==
			    signaller->semaphore_register[ring->id])
				return signaller;
		}
	}

	DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x\n",
		  ring->id, ipehr);

	return NULL;
}

2576 2577
static struct intel_ring_buffer *
semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
2578 2579
{
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
2580 2581
	u32 cmd, ipehr, head;
	int i;
2582 2583

	ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2584
	if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
2585
		return NULL;
2586

2587 2588 2589 2590 2591 2592
	/*
	 * HEAD is likely pointing to the dword after the actual command,
	 * so scan backwards until we find the MBOX. But limit it to just 3
	 * dwords. Note that we don't care about ACTHD here since that might
	 * point at at batch, and semaphores are always emitted into the
	 * ringbuffer itself.
2593
	 */
2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605
	head = I915_READ_HEAD(ring) & HEAD_ADDR;

	for (i = 4; i; --i) {
		/*
		 * Be paranoid and presume the hw has gone off into the wild -
		 * our ring is smaller than what the hardware (and hence
		 * HEAD_ADDR) allows. Also handles wrap-around.
		 */
		head &= ring->size - 1;

		/* This here seems to blow up */
		cmd = ioread32(ring->virtual_start + head);
2606 2607 2608
		if (cmd == ipehr)
			break;

2609 2610 2611 2612 2613
		head -= 4;
	}

	if (!i)
		return NULL;
2614

2615
	*seqno = ioread32(ring->virtual_start + head + 4) + 1;
2616
	return semaphore_wait_to_signaller_ring(ring, ipehr);
2617 2618
}

2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647
static int semaphore_passed(struct intel_ring_buffer *ring)
{
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
	struct intel_ring_buffer *signaller;
	u32 seqno, ctl;

	ring->hangcheck.deadlock = true;

	signaller = semaphore_waits_for(ring, &seqno);
	if (signaller == NULL || signaller->hangcheck.deadlock)
		return -1;

	/* cursory check for an unkickable deadlock */
	ctl = I915_READ_CTL(signaller);
	if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
		return -1;

	return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
}

static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
{
	struct intel_ring_buffer *ring;
	int i;

	for_each_ring(ring, dev_priv, i)
		ring->hangcheck.deadlock = false;
}

2648
static enum intel_ring_hangcheck_action
2649
ring_stuck(struct intel_ring_buffer *ring, u64 acthd)
2650 2651 2652
{
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2653 2654
	u32 tmp;

2655
	if (ring->hangcheck.acthd != acthd)
2656
		return HANGCHECK_ACTIVE;
2657

2658
	if (IS_GEN2(dev))
2659
		return HANGCHECK_HUNG;
2660 2661 2662 2663 2664 2665 2666

	/* Is the chip hanging on a WAIT_FOR_EVENT?
	 * If so we can simply poke the RB_WAIT bit
	 * and break the hang. This should work on
	 * all but the second generation chipsets.
	 */
	tmp = I915_READ_CTL(ring);
2667
	if (tmp & RING_WAIT) {
2668 2669 2670
		i915_handle_error(dev, false,
				  "Kicking stuck wait on %s",
				  ring->name);
2671
		I915_WRITE_CTL(ring, tmp);
2672
		return HANGCHECK_KICK;
2673 2674 2675 2676 2677
	}

	if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
		switch (semaphore_passed(ring)) {
		default:
2678
			return HANGCHECK_HUNG;
2679
		case 1:
2680 2681 2682
			i915_handle_error(dev, false,
					  "Kicking stuck semaphore on %s",
					  ring->name);
2683
			I915_WRITE_CTL(ring, tmp);
2684
			return HANGCHECK_KICK;
2685
		case 0:
2686
			return HANGCHECK_WAIT;
2687
		}
2688
	}
2689

2690
	return HANGCHECK_HUNG;
2691 2692
}

B
Ben Gamari 已提交
2693 2694
/**
 * This is called when the chip hasn't reported back with completed
2695 2696 2697 2698 2699
 * batchbuffers in a long time. We keep track per ring seqno progress and
 * if there are no progress, hangcheck score for that ring is increased.
 * Further, acthd is inspected to see if the ring is stuck. On stuck case
 * we kick the ring. If we see no progress on three subsequent calls
 * we assume chip is wedged and try to fix it by resetting the chip.
B
Ben Gamari 已提交
2700
 */
2701
static void i915_hangcheck_elapsed(unsigned long data)
B
Ben Gamari 已提交
2702 2703
{
	struct drm_device *dev = (struct drm_device *)data;
2704
	struct drm_i915_private *dev_priv = dev->dev_private;
2705 2706
	struct intel_ring_buffer *ring;
	int i;
2707
	int busy_count = 0, rings_hung = 0;
2708 2709 2710 2711
	bool stuck[I915_NUM_RINGS] = { 0 };
#define BUSY 1
#define KICK 5
#define HUNG 20
2712

2713
	if (!i915.enable_hangcheck)
2714 2715
		return;

2716
	for_each_ring(ring, dev_priv, i) {
2717 2718
		u64 acthd;
		u32 seqno;
2719
		bool busy = true;
2720

2721 2722
		semaphore_clear_deadlocks(dev_priv);

2723 2724
		seqno = ring->get_seqno(ring, false);
		acthd = intel_ring_get_active_head(ring);
2725

2726 2727
		if (ring->hangcheck.seqno == seqno) {
			if (ring_idle(ring, seqno)) {
2728 2729
				ring->hangcheck.action = HANGCHECK_IDLE;

2730 2731
				if (waitqueue_active(&ring->irq_queue)) {
					/* Issue a wake-up to catch stuck h/w. */
2732
					if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2733 2734 2735 2736 2737 2738
						if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
							DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
								  ring->name);
						else
							DRM_INFO("Fake missed irq on %s\n",
								 ring->name);
2739 2740 2741 2742
						wake_up_all(&ring->irq_queue);
					}
					/* Safeguard against driver failure */
					ring->hangcheck.score += BUSY;
2743 2744
				} else
					busy = false;
2745
			} else {
2746 2747 2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758 2759 2760
				/* We always increment the hangcheck score
				 * if the ring is busy and still processing
				 * the same request, so that no single request
				 * can run indefinitely (such as a chain of
				 * batches). The only time we do not increment
				 * the hangcheck score on this ring, if this
				 * ring is in a legitimate wait for another
				 * ring. In that case the waiting ring is a
				 * victim and we want to be sure we catch the
				 * right culprit. Then every time we do kick
				 * the ring, add a small increment to the
				 * score so that we can catch a batch that is
				 * being repeatedly kicked and so responsible
				 * for stalling the machine.
				 */
2761 2762 2763 2764
				ring->hangcheck.action = ring_stuck(ring,
								    acthd);

				switch (ring->hangcheck.action) {
2765
				case HANGCHECK_IDLE:
2766
				case HANGCHECK_WAIT:
2767
					break;
2768
				case HANGCHECK_ACTIVE:
2769
					ring->hangcheck.score += BUSY;
2770
					break;
2771
				case HANGCHECK_KICK:
2772
					ring->hangcheck.score += KICK;
2773
					break;
2774
				case HANGCHECK_HUNG:
2775
					ring->hangcheck.score += HUNG;
2776 2777 2778
					stuck[i] = true;
					break;
				}
2779
			}
2780
		} else {
2781 2782
			ring->hangcheck.action = HANGCHECK_ACTIVE;

2783 2784 2785 2786 2787
			/* Gradually reduce the count so that we catch DoS
			 * attempts across multiple batches.
			 */
			if (ring->hangcheck.score > 0)
				ring->hangcheck.score--;
2788 2789
		}

2790 2791
		ring->hangcheck.seqno = seqno;
		ring->hangcheck.acthd = acthd;
2792
		busy_count += busy;
2793
	}
2794

2795
	for_each_ring(ring, dev_priv, i) {
2796
		if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
2797 2798 2799
			DRM_INFO("%s on %s\n",
				 stuck[i] ? "stuck" : "no progress",
				 ring->name);
2800
			rings_hung++;
2801 2802 2803
		}
	}

2804
	if (rings_hung)
2805
		return i915_handle_error(dev, true, "Ring hung");
B
Ben Gamari 已提交
2806

2807 2808 2809
	if (busy_count)
		/* Reset timer case chip hangs without another request
		 * being added */
2810 2811 2812 2813 2814 2815
		i915_queue_hangcheck(dev);
}

void i915_queue_hangcheck(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2816
	if (!i915.enable_hangcheck)
2817 2818 2819 2820
		return;

	mod_timer(&dev_priv->gpu_error.hangcheck_timer,
		  round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
B
Ben Gamari 已提交
2821 2822
}

P
Paulo Zanoni 已提交
2823 2824 2825 2826 2827 2828 2829
static void ibx_irq_preinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (HAS_PCH_NOP(dev))
		return;

2830
	GEN5_IRQ_INIT(SDE);
P
Paulo Zanoni 已提交
2831 2832 2833 2834 2835 2836 2837 2838 2839 2840
	/*
	 * SDEIER is also touched by the interrupt handler to work around missed
	 * PCH interrupts. Hence we can't update it after the interrupt handler
	 * is enabled - instead we unconditionally enable all PCH interrupt
	 * sources here, but then only unmask them as needed with SDEIMR.
	 */
	I915_WRITE(SDEIER, 0xffffffff);
	POSTING_READ(SDEIER);
}

2841 2842 2843 2844
static void gen5_gt_irq_preinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

P
Paulo Zanoni 已提交
2845 2846 2847
	GEN5_IRQ_INIT(GT);
	if (INTEL_INFO(dev)->gen >= 6)
		GEN5_IRQ_INIT(GEN6_PM);
2848 2849
}

L
Linus Torvalds 已提交
2850 2851
/* drm_dma.h hooks
*/
2852
static void ironlake_irq_preinstall(struct drm_device *dev)
2853
{
2854
	struct drm_i915_private *dev_priv = dev->dev_private;
2855 2856

	I915_WRITE(HWSTAM, 0xeffe);
2857

P
Paulo Zanoni 已提交
2858
	GEN5_IRQ_INIT(DE);
2859

2860
	gen5_gt_irq_preinstall(dev);
2861

P
Paulo Zanoni 已提交
2862
	ibx_irq_preinstall(dev);
2863 2864
}

J
Jesse Barnes 已提交
2865 2866
static void valleyview_irq_preinstall(struct drm_device *dev)
{
2867
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
2868 2869 2870 2871 2872 2873 2874 2875 2876 2877 2878
	int pipe;

	/* VLV magic */
	I915_WRITE(VLV_IMR, 0);
	I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
	I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
	I915_WRITE(RING_IMR(BLT_RING_BASE), 0);

	/* and GT */
	I915_WRITE(GTIIR, I915_READ(GTIIR));
	I915_WRITE(GTIIR, I915_READ(GTIIR));
2879 2880

	gen5_gt_irq_preinstall(dev);
J
Jesse Barnes 已提交
2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893

	I915_WRITE(DPINVGTT, 0xff);

	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0xffff);
	I915_WRITE(VLV_IIR, 0xffffffff);
	I915_WRITE(VLV_IMR, 0xffffffff);
	I915_WRITE(VLV_IER, 0x0);
	POSTING_READ(VLV_IER);
}

2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931 2932 2933 2934 2935 2936
static void gen8_irq_preinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int pipe;

	I915_WRITE(GEN8_MASTER_IRQ, 0);
	POSTING_READ(GEN8_MASTER_IRQ);

	/* IIR can theoretically queue up two events. Be paranoid */
#define GEN8_IRQ_INIT_NDX(type, which) do { \
		I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
		POSTING_READ(GEN8_##type##_IMR(which)); \
		I915_WRITE(GEN8_##type##_IER(which), 0); \
		I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
		POSTING_READ(GEN8_##type##_IIR(which)); \
		I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
	} while (0)

#define GEN8_IRQ_INIT(type) do { \
		I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
		POSTING_READ(GEN8_##type##_IMR); \
		I915_WRITE(GEN8_##type##_IER, 0); \
		I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
		POSTING_READ(GEN8_##type##_IIR); \
		I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
	} while (0)

	GEN8_IRQ_INIT_NDX(GT, 0);
	GEN8_IRQ_INIT_NDX(GT, 1);
	GEN8_IRQ_INIT_NDX(GT, 2);
	GEN8_IRQ_INIT_NDX(GT, 3);

	for_each_pipe(pipe) {
		GEN8_IRQ_INIT_NDX(DE_PIPE, pipe);
	}

	GEN8_IRQ_INIT(DE_PORT);
	GEN8_IRQ_INIT(DE_MISC);
	GEN8_IRQ_INIT(PCU);
#undef GEN8_IRQ_INIT
#undef GEN8_IRQ_INIT_NDX

	POSTING_READ(GEN8_PCU_IIR);
2937 2938

	ibx_irq_preinstall(dev);
2939 2940
}

2941
static void ibx_hpd_irq_setup(struct drm_device *dev)
2942
{
2943
	struct drm_i915_private *dev_priv = dev->dev_private;
2944 2945
	struct drm_mode_config *mode_config = &dev->mode_config;
	struct intel_encoder *intel_encoder;
2946
	u32 hotplug_irqs, hotplug, enabled_irqs = 0;
2947 2948

	if (HAS_PCH_IBX(dev)) {
2949
		hotplug_irqs = SDE_HOTPLUG_MASK;
2950
		list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2951
			if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2952
				enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
2953
	} else {
2954
		hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
2955
		list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2956
			if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2957
				enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
2958
	}
2959

2960
	ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
2961 2962 2963 2964 2965 2966 2967

	/*
	 * Enable digital hotplug on the PCH, and configure the DP short pulse
	 * duration to 2ms (which is the minimum in the Display Port spec)
	 *
	 * This register is the same on all known PCH chips.
	 */
2968 2969 2970 2971 2972 2973 2974 2975
	hotplug = I915_READ(PCH_PORT_HOTPLUG);
	hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
	hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
	hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
	hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
}

P
Paulo Zanoni 已提交
2976 2977
static void ibx_irq_postinstall(struct drm_device *dev)
{
2978
	struct drm_i915_private *dev_priv = dev->dev_private;
2979
	u32 mask;
2980

D
Daniel Vetter 已提交
2981 2982 2983
	if (HAS_PCH_NOP(dev))
		return;

2984
	if (HAS_PCH_IBX(dev)) {
2985
		mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
2986
	} else {
2987
		mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
2988 2989 2990

		I915_WRITE(SERR_INT, I915_READ(SERR_INT));
	}
2991

P
Paulo Zanoni 已提交
2992 2993 2994 2995
	I915_WRITE(SDEIIR, I915_READ(SDEIIR));
	I915_WRITE(SDEIMR, ~mask);
}

2996 2997 2998 2999 3000 3001 3002 3003
static void gen5_gt_irq_postinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pm_irqs, gt_irqs;

	pm_irqs = gt_irqs = 0;

	dev_priv->gt_irq_mask = ~0;
3004
	if (HAS_L3_DPF(dev)) {
3005
		/* L3 parity interrupt is always unmasked. */
3006 3007
		dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
		gt_irqs |= GT_PARITY_ERROR(dev);
3008 3009 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023
	}

	gt_irqs |= GT_RENDER_USER_INTERRUPT;
	if (IS_GEN5(dev)) {
		gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
			   ILK_BSD_USER_INTERRUPT;
	} else {
		gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
	}

	I915_WRITE(GTIIR, I915_READ(GTIIR));
	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
	I915_WRITE(GTIER, gt_irqs);
	POSTING_READ(GTIER);

	if (INTEL_INFO(dev)->gen >= 6) {
3024
		pm_irqs |= dev_priv->pm_rps_events;
3025 3026 3027 3028

		if (HAS_VEBOX(dev))
			pm_irqs |= PM_VEBOX_USER_INTERRUPT;

3029
		dev_priv->pm_irq_mask = 0xffffffff;
3030
		I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
3031
		I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
3032 3033 3034 3035 3036
		I915_WRITE(GEN6_PMIER, pm_irqs);
		POSTING_READ(GEN6_PMIER);
	}
}

3037
static int ironlake_irq_postinstall(struct drm_device *dev)
3038
{
3039
	unsigned long irqflags;
3040
	struct drm_i915_private *dev_priv = dev->dev_private;
3041 3042 3043 3044 3045 3046
	u32 display_mask, extra_mask;

	if (INTEL_INFO(dev)->gen >= 7) {
		display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
				DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
				DE_PLANEB_FLIP_DONE_IVB |
3047
				DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3048
		extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3049
			      DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
3050 3051 3052 3053 3054

		I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
	} else {
		display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
				DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3055 3056 3057
				DE_AUX_CHANNEL_A |
				DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
				DE_POISON);
3058 3059
		extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
				DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
3060
	}
3061

3062
	dev_priv->irq_mask = ~display_mask;
3063 3064 3065

	/* should always can generate irq */
	I915_WRITE(DEIIR, I915_READ(DEIIR));
3066
	I915_WRITE(DEIMR, dev_priv->irq_mask);
3067
	I915_WRITE(DEIER, display_mask | extra_mask);
3068
	POSTING_READ(DEIER);
3069

3070
	gen5_gt_irq_postinstall(dev);
3071

P
Paulo Zanoni 已提交
3072
	ibx_irq_postinstall(dev);
3073

3074
	if (IS_IRONLAKE_M(dev)) {
3075 3076 3077
		/* Enable PCU event interrupts
		 *
		 * spinlocking not required here for correctness since interrupt
3078 3079 3080
		 * setup is guaranteed to run in single-threaded context. But we
		 * need it to make the assert_spin_locked happy. */
		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3081
		ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
3082
		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3083 3084
	}

3085 3086 3087
	return 0;
}

3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111 3112 3113 3114 3115 3116 3117 3118 3119 3120 3121 3122 3123 3124 3125
static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
{
	u32 pipestat_mask;
	u32 iir_mask;

	pipestat_mask = PIPESTAT_INT_STATUS_MASK |
			PIPE_FIFO_UNDERRUN_STATUS;

	I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
	I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
	POSTING_READ(PIPESTAT(PIPE_A));

	pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
			PIPE_CRC_DONE_INTERRUPT_STATUS;

	i915_enable_pipestat(dev_priv, PIPE_A, pipestat_mask |
					       PIPE_GMBUS_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_B, pipestat_mask);

	iir_mask = I915_DISPLAY_PORT_INTERRUPT |
		   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
	dev_priv->irq_mask &= ~iir_mask;

	I915_WRITE(VLV_IIR, iir_mask);
	I915_WRITE(VLV_IIR, iir_mask);
	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
	POSTING_READ(VLV_IER);
}

static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
{
	u32 pipestat_mask;
	u32 iir_mask;

	iir_mask = I915_DISPLAY_PORT_INTERRUPT |
		   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3126
		   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3127 3128 3129 3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167 3168 3169 3170 3171 3172 3173 3174

	dev_priv->irq_mask |= iir_mask;
	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
	I915_WRITE(VLV_IIR, iir_mask);
	I915_WRITE(VLV_IIR, iir_mask);
	POSTING_READ(VLV_IIR);

	pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
			PIPE_CRC_DONE_INTERRUPT_STATUS;

	i915_disable_pipestat(dev_priv, PIPE_A, pipestat_mask |
					        PIPE_GMBUS_INTERRUPT_STATUS);
	i915_disable_pipestat(dev_priv, PIPE_B, pipestat_mask);

	pipestat_mask = PIPESTAT_INT_STATUS_MASK |
			PIPE_FIFO_UNDERRUN_STATUS;
	I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
	I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
	POSTING_READ(PIPESTAT(PIPE_A));
}

void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
{
	assert_spin_locked(&dev_priv->irq_lock);

	if (dev_priv->display_irqs_enabled)
		return;

	dev_priv->display_irqs_enabled = true;

	if (dev_priv->dev->irq_enabled)
		valleyview_display_irqs_install(dev_priv);
}

void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
{
	assert_spin_locked(&dev_priv->irq_lock);

	if (!dev_priv->display_irqs_enabled)
		return;

	dev_priv->display_irqs_enabled = false;

	if (dev_priv->dev->irq_enabled)
		valleyview_display_irqs_uninstall(dev_priv);
}

J
Jesse Barnes 已提交
3175 3176
static int valleyview_irq_postinstall(struct drm_device *dev)
{
3177
	struct drm_i915_private *dev_priv = dev->dev_private;
3178
	unsigned long irqflags;
J
Jesse Barnes 已提交
3179

3180
	dev_priv->irq_mask = ~0;
J
Jesse Barnes 已提交
3181

3182 3183 3184
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	POSTING_READ(PORT_HOTPLUG_EN);

J
Jesse Barnes 已提交
3185
	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3186
	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
J
Jesse Barnes 已提交
3187 3188 3189
	I915_WRITE(VLV_IIR, 0xffffffff);
	POSTING_READ(VLV_IER);

3190 3191 3192
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3193 3194
	if (dev_priv->display_irqs_enabled)
		valleyview_display_irqs_install(dev_priv);
3195
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3196

J
Jesse Barnes 已提交
3197 3198 3199
	I915_WRITE(VLV_IIR, 0xffffffff);
	I915_WRITE(VLV_IIR, 0xffffffff);

3200
	gen5_gt_irq_postinstall(dev);
J
Jesse Barnes 已提交
3201 3202 3203 3204 3205 3206 3207 3208

	/* ack & enable invalid PTE error interrupts */
#if 0 /* FIXME: add support to irq handler for checking these bits */
	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
	I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
#endif

	I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3209 3210 3211 3212

	return 0;
}

3213 3214 3215 3216 3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238 3239 3240 3241
static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
{
	int i;

	/* These are interrupts we'll toggle with the ring mask register */
	uint32_t gt_interrupts[] = {
		GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
			GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
			GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
		GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
			GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
		0,
		GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT
		};

	for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) {
		u32 tmp = I915_READ(GEN8_GT_IIR(i));
		if (tmp)
			DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
				  i, tmp);
		I915_WRITE(GEN8_GT_IMR(i), ~gt_interrupts[i]);
		I915_WRITE(GEN8_GT_IER(i), gt_interrupts[i]);
	}
	POSTING_READ(GEN8_GT_IER(0));
}

static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
{
	struct drm_device *dev = dev_priv->dev;
3242 3243 3244
	uint32_t de_pipe_masked = GEN8_PIPE_FLIP_DONE |
		GEN8_PIPE_CDCLK_CRC_DONE |
		GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3245 3246
	uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
		GEN8_PIPE_FIFO_UNDERRUN;
3247
	int pipe;
3248 3249 3250
	dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
	dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
	dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3251 3252 3253 3254 3255 3256 3257 3258 3259 3260 3261

	for_each_pipe(pipe) {
		u32 tmp = I915_READ(GEN8_DE_PIPE_IIR(pipe));
		if (tmp)
			DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
				  pipe, tmp);
		I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
		I915_WRITE(GEN8_DE_PIPE_IER(pipe), de_pipe_enables);
	}
	POSTING_READ(GEN8_DE_PIPE_ISR(0));

3262 3263
	I915_WRITE(GEN8_DE_PORT_IMR, ~GEN8_AUX_CHANNEL_A);
	I915_WRITE(GEN8_DE_PORT_IER, GEN8_AUX_CHANNEL_A);
3264 3265 3266 3267 3268 3269 3270 3271 3272 3273 3274 3275 3276 3277 3278 3279 3280 3281 3282 3283 3284 3285 3286 3287 3288 3289 3290 3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305 3306 3307 3308 3309 3310 3311 3312 3313 3314 3315 3316 3317 3318 3319 3320 3321
	POSTING_READ(GEN8_DE_PORT_IER);
}

static int gen8_irq_postinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	gen8_gt_irq_postinstall(dev_priv);
	gen8_de_irq_postinstall(dev_priv);

	ibx_irq_postinstall(dev);

	I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
	POSTING_READ(GEN8_MASTER_IRQ);

	return 0;
}

static void gen8_irq_uninstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int pipe;

	if (!dev_priv)
		return;

	I915_WRITE(GEN8_MASTER_IRQ, 0);

#define GEN8_IRQ_FINI_NDX(type, which) do { \
		I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
		I915_WRITE(GEN8_##type##_IER(which), 0); \
		I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
	} while (0)

#define GEN8_IRQ_FINI(type) do { \
		I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
		I915_WRITE(GEN8_##type##_IER, 0); \
		I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
	} while (0)

	GEN8_IRQ_FINI_NDX(GT, 0);
	GEN8_IRQ_FINI_NDX(GT, 1);
	GEN8_IRQ_FINI_NDX(GT, 2);
	GEN8_IRQ_FINI_NDX(GT, 3);

	for_each_pipe(pipe) {
		GEN8_IRQ_FINI_NDX(DE_PIPE, pipe);
	}

	GEN8_IRQ_FINI(DE_PORT);
	GEN8_IRQ_FINI(DE_MISC);
	GEN8_IRQ_FINI(PCU);
#undef GEN8_IRQ_FINI
#undef GEN8_IRQ_FINI_NDX

	POSTING_READ(GEN8_PCU_IIR);
}

J
Jesse Barnes 已提交
3322 3323
static void valleyview_irq_uninstall(struct drm_device *dev)
{
3324
	struct drm_i915_private *dev_priv = dev->dev_private;
3325
	unsigned long irqflags;
J
Jesse Barnes 已提交
3326 3327 3328 3329 3330
	int pipe;

	if (!dev_priv)
		return;

3331
	intel_hpd_irq_uninstall(dev_priv);
3332

J
Jesse Barnes 已提交
3333 3334 3335 3336 3337 3338
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0xffff);

	I915_WRITE(HWSTAM, 0xffffffff);
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3339 3340 3341 3342 3343 3344 3345 3346

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
	if (dev_priv->display_irqs_enabled)
		valleyview_display_irqs_uninstall(dev_priv);
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

	dev_priv->irq_mask = 0;

J
Jesse Barnes 已提交
3347 3348 3349 3350 3351 3352
	I915_WRITE(VLV_IIR, 0xffffffff);
	I915_WRITE(VLV_IMR, 0xffffffff);
	I915_WRITE(VLV_IER, 0x0);
	POSTING_READ(VLV_IER);
}

3353
static void ironlake_irq_uninstall(struct drm_device *dev)
3354
{
3355
	struct drm_i915_private *dev_priv = dev->dev_private;
3356 3357 3358 3359

	if (!dev_priv)
		return;

3360
	intel_hpd_irq_uninstall(dev_priv);
3361

3362 3363 3364 3365 3366
	I915_WRITE(HWSTAM, 0xffffffff);

	I915_WRITE(DEIMR, 0xffffffff);
	I915_WRITE(DEIER, 0x0);
	I915_WRITE(DEIIR, I915_READ(DEIIR));
3367 3368
	if (IS_GEN7(dev))
		I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
3369 3370 3371 3372

	I915_WRITE(GTIMR, 0xffffffff);
	I915_WRITE(GTIER, 0x0);
	I915_WRITE(GTIIR, I915_READ(GTIIR));
3373

3374 3375 3376
	if (HAS_PCH_NOP(dev))
		return;

3377 3378 3379
	I915_WRITE(SDEIMR, 0xffffffff);
	I915_WRITE(SDEIER, 0x0);
	I915_WRITE(SDEIIR, I915_READ(SDEIIR));
3380 3381
	if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
		I915_WRITE(SERR_INT, I915_READ(SERR_INT));
3382 3383
}

3384
static void i8xx_irq_preinstall(struct drm_device * dev)
L
Linus Torvalds 已提交
3385
{
3386
	struct drm_i915_private *dev_priv = dev->dev_private;
3387
	int pipe;
3388

3389 3390
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0);
3391 3392 3393
	I915_WRITE16(IMR, 0xffff);
	I915_WRITE16(IER, 0x0);
	POSTING_READ16(IER);
C
Chris Wilson 已提交
3394 3395 3396 3397
}

static int i8xx_irq_postinstall(struct drm_device *dev)
{
3398
	struct drm_i915_private *dev_priv = dev->dev_private;
3399
	unsigned long irqflags;
C
Chris Wilson 已提交
3400 3401 3402 3403 3404 3405 3406 3407 3408 3409 3410 3411 3412 3413 3414 3415 3416 3417 3418 3419

	I915_WRITE16(EMR,
		     ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));

	/* Unmask the interrupts that we always want on. */
	dev_priv->irq_mask =
		~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
		  I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
	I915_WRITE16(IMR, dev_priv->irq_mask);

	I915_WRITE16(IER,
		     I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		     I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		     I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
		     I915_USER_INTERRUPT);
	POSTING_READ16(IER);

3420 3421 3422
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3423 3424
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3425 3426
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

C
Chris Wilson 已提交
3427 3428 3429
	return 0;
}

3430 3431 3432 3433
/*
 * Returns true when a page flip has completed.
 */
static bool i8xx_handle_vblank(struct drm_device *dev,
3434
			       int plane, int pipe, u32 iir)
3435
{
3436
	struct drm_i915_private *dev_priv = dev->dev_private;
3437
	u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3438 3439 3440 3441 3442 3443 3444

	if (!drm_handle_vblank(dev, pipe))
		return false;

	if ((iir & flip_pending) == 0)
		return false;

3445
	intel_prepare_page_flip(dev, plane);
3446 3447 3448 3449 3450 3451 3452 3453 3454 3455 3456 3457 3458 3459 3460

	/* We detect FlipDone by looking for the change in PendingFlip from '1'
	 * to '0' on the following vblank, i.e. IIR has the Pendingflip
	 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
	 * the flip is completed (no longer pending). Since this doesn't raise
	 * an interrupt per se, we watch for the change at vblank.
	 */
	if (I915_READ16(ISR) & flip_pending)
		return false;

	intel_finish_page_flip(dev, pipe);

	return true;
}

3461
static irqreturn_t i8xx_irq_handler(int irq, void *arg)
C
Chris Wilson 已提交
3462 3463
{
	struct drm_device *dev = (struct drm_device *) arg;
3464
	struct drm_i915_private *dev_priv = dev->dev_private;
C
Chris Wilson 已提交
3465 3466 3467 3468 3469 3470 3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481 3482 3483 3484
	u16 iir, new_iir;
	u32 pipe_stats[2];
	unsigned long irqflags;
	int pipe;
	u16 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;

	iir = I915_READ16(IIR);
	if (iir == 0)
		return IRQ_NONE;

	while (iir & ~flip_mask) {
		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3485 3486 3487
			i915_handle_error(dev, false,
					  "Command parser error, iir 0x%08x",
					  iir);
C
Chris Wilson 已提交
3488 3489 3490 3491 3492 3493 3494 3495

		for_each_pipe(pipe) {
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);

			/*
			 * Clear the PIPE*STAT regs before the IIR
			 */
3496
			if (pipe_stats[pipe] & 0x8000ffff)
C
Chris Wilson 已提交
3497 3498 3499 3500 3501 3502 3503
				I915_WRITE(reg, pipe_stats[pipe]);
		}
		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

		I915_WRITE16(IIR, iir & ~flip_mask);
		new_iir = I915_READ16(IIR); /* Flush posted writes */

3504
		i915_update_dri1_breadcrumb(dev);
C
Chris Wilson 已提交
3505 3506 3507 3508

		if (iir & I915_USER_INTERRUPT)
			notify_ring(dev, &dev_priv->ring[RCS]);

3509
		for_each_pipe(pipe) {
3510
			int plane = pipe;
3511
			if (HAS_FBC(dev))
3512 3513
				plane = !plane;

3514
			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3515 3516
			    i8xx_handle_vblank(dev, plane, pipe, iir))
				flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
C
Chris Wilson 已提交
3517

3518
			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3519
				i9xx_pipe_crc_irq_handler(dev, pipe);
3520 3521 3522

			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
			    intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3523
				DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3524
		}
C
Chris Wilson 已提交
3525 3526 3527 3528 3529 3530 3531 3532 3533

		iir = new_iir;
	}

	return IRQ_HANDLED;
}

static void i8xx_irq_uninstall(struct drm_device * dev)
{
3534
	struct drm_i915_private *dev_priv = dev->dev_private;
C
Chris Wilson 已提交
3535 3536 3537 3538 3539 3540 3541 3542 3543 3544 3545 3546
	int pipe;

	for_each_pipe(pipe) {
		/* Clear enable bits; then clear status bits */
		I915_WRITE(PIPESTAT(pipe), 0);
		I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
	}
	I915_WRITE16(IMR, 0xffff);
	I915_WRITE16(IER, 0x0);
	I915_WRITE16(IIR, I915_READ16(IIR));
}

3547 3548
static void i915_irq_preinstall(struct drm_device * dev)
{
3549
	struct drm_i915_private *dev_priv = dev->dev_private;
3550 3551 3552 3553 3554 3555 3556
	int pipe;

	if (I915_HAS_HOTPLUG(dev)) {
		I915_WRITE(PORT_HOTPLUG_EN, 0);
		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	}

3557
	I915_WRITE16(HWSTAM, 0xeffe);
3558 3559 3560 3561 3562 3563 3564 3565 3566
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);
	POSTING_READ(IER);
}

static int i915_irq_postinstall(struct drm_device *dev)
{
3567
	struct drm_i915_private *dev_priv = dev->dev_private;
3568
	u32 enable_mask;
3569
	unsigned long irqflags;
3570

3571 3572 3573 3574 3575 3576 3577 3578 3579 3580 3581 3582 3583 3584 3585 3586 3587 3588
	I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));

	/* Unmask the interrupts that we always want on. */
	dev_priv->irq_mask =
		~(I915_ASLE_INTERRUPT |
		  I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
		  I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);

	enable_mask =
		I915_ASLE_INTERRUPT |
		I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
		I915_USER_INTERRUPT;

3589
	if (I915_HAS_HOTPLUG(dev)) {
3590 3591 3592
		I915_WRITE(PORT_HOTPLUG_EN, 0);
		POSTING_READ(PORT_HOTPLUG_EN);

3593 3594 3595 3596 3597 3598 3599 3600 3601 3602
		/* Enable in IER... */
		enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
		/* and unmask in IMR */
		dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
	}

	I915_WRITE(IMR, dev_priv->irq_mask);
	I915_WRITE(IER, enable_mask);
	POSTING_READ(IER);

3603
	i915_enable_asle_pipestat(dev);
3604

3605 3606 3607
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3608 3609
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3610 3611
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

3612 3613 3614
	return 0;
}

3615 3616 3617 3618 3619 3620
/*
 * Returns true when a page flip has completed.
 */
static bool i915_handle_vblank(struct drm_device *dev,
			       int plane, int pipe, u32 iir)
{
3621
	struct drm_i915_private *dev_priv = dev->dev_private;
3622 3623 3624 3625 3626 3627 3628 3629 3630 3631 3632 3633 3634 3635 3636 3637 3638 3639 3640 3641 3642 3643 3644 3645
	u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);

	if (!drm_handle_vblank(dev, pipe))
		return false;

	if ((iir & flip_pending) == 0)
		return false;

	intel_prepare_page_flip(dev, plane);

	/* We detect FlipDone by looking for the change in PendingFlip from '1'
	 * to '0' on the following vblank, i.e. IIR has the Pendingflip
	 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
	 * the flip is completed (no longer pending). Since this doesn't raise
	 * an interrupt per se, we watch for the change at vblank.
	 */
	if (I915_READ(ISR) & flip_pending)
		return false;

	intel_finish_page_flip(dev, pipe);

	return true;
}

3646
static irqreturn_t i915_irq_handler(int irq, void *arg)
3647 3648
{
	struct drm_device *dev = (struct drm_device *) arg;
3649
	struct drm_i915_private *dev_priv = dev->dev_private;
3650
	u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3651
	unsigned long irqflags;
3652 3653 3654 3655
	u32 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
	int pipe, ret = IRQ_NONE;
3656 3657

	iir = I915_READ(IIR);
3658 3659
	do {
		bool irq_received = (iir & ~flip_mask) != 0;
3660
		bool blc_event = false;
3661 3662 3663 3664 3665 3666 3667 3668

		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3669 3670 3671
			i915_handle_error(dev, false,
					  "Command parser error, iir 0x%08x",
					  iir);
3672 3673 3674 3675 3676

		for_each_pipe(pipe) {
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);

3677
			/* Clear the PIPE*STAT regs before the IIR */
3678 3679
			if (pipe_stats[pipe] & 0x8000ffff) {
				I915_WRITE(reg, pipe_stats[pipe]);
3680
				irq_received = true;
3681 3682 3683 3684 3685 3686 3687 3688
			}
		}
		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

		if (!irq_received)
			break;

		/* Consume port.  Then clear IIR or we'll miss events */
3689 3690 3691
		if (I915_HAS_HOTPLUG(dev) &&
		    iir & I915_DISPLAY_PORT_INTERRUPT)
			i9xx_hpd_irq_handler(dev);
3692

3693
		I915_WRITE(IIR, iir & ~flip_mask);
3694 3695 3696 3697 3698 3699
		new_iir = I915_READ(IIR); /* Flush posted writes */

		if (iir & I915_USER_INTERRUPT)
			notify_ring(dev, &dev_priv->ring[RCS]);

		for_each_pipe(pipe) {
3700
			int plane = pipe;
3701
			if (HAS_FBC(dev))
3702
				plane = !plane;
3703

3704
			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3705 3706
			    i915_handle_vblank(dev, plane, pipe, iir))
				flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3707 3708 3709

			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
				blc_event = true;
3710 3711

			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3712
				i9xx_pipe_crc_irq_handler(dev, pipe);
3713 3714 3715

			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
			    intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3716
				DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3717 3718 3719 3720 3721 3722 3723 3724 3725 3726 3727 3728 3729 3730 3731 3732 3733 3734 3735 3736
		}

		if (blc_event || (iir & I915_ASLE_INTERRUPT))
			intel_opregion_asle_intr(dev);

		/* With MSI, interrupts are only generated when iir
		 * transitions from zero to nonzero.  If another bit got
		 * set while we were handling the existing iir bits, then
		 * we would never get another interrupt.
		 *
		 * This is fine on non-MSI as well, as if we hit this path
		 * we avoid exiting the interrupt handler only to generate
		 * another one.
		 *
		 * Note that for MSI this could cause a stray interrupt report
		 * if an interrupt landed in the time between writing IIR and
		 * the posting read.  This should be rare enough to never
		 * trigger the 99% of 100,000 interrupts test for disabling
		 * stray interrupts.
		 */
3737
		ret = IRQ_HANDLED;
3738
		iir = new_iir;
3739
	} while (iir & ~flip_mask);
3740

3741
	i915_update_dri1_breadcrumb(dev);
3742

3743 3744 3745 3746 3747
	return ret;
}

static void i915_irq_uninstall(struct drm_device * dev)
{
3748
	struct drm_i915_private *dev_priv = dev->dev_private;
3749 3750
	int pipe;

3751
	intel_hpd_irq_uninstall(dev_priv);
3752

3753 3754 3755 3756 3757
	if (I915_HAS_HOTPLUG(dev)) {
		I915_WRITE(PORT_HOTPLUG_EN, 0);
		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	}

3758
	I915_WRITE16(HWSTAM, 0xffff);
3759 3760
	for_each_pipe(pipe) {
		/* Clear enable bits; then clear status bits */
3761
		I915_WRITE(PIPESTAT(pipe), 0);
3762 3763
		I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
	}
3764 3765 3766 3767 3768 3769 3770 3771
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);

	I915_WRITE(IIR, I915_READ(IIR));
}

static void i965_irq_preinstall(struct drm_device * dev)
{
3772
	struct drm_i915_private *dev_priv = dev->dev_private;
3773 3774
	int pipe;

3775 3776
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3777 3778 3779 3780 3781 3782 3783 3784 3785 3786 3787

	I915_WRITE(HWSTAM, 0xeffe);
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);
	POSTING_READ(IER);
}

static int i965_irq_postinstall(struct drm_device *dev)
{
3788
	struct drm_i915_private *dev_priv = dev->dev_private;
3789
	u32 enable_mask;
3790
	u32 error_mask;
3791
	unsigned long irqflags;
3792 3793

	/* Unmask the interrupts that we always want on. */
3794
	dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
3795
			       I915_DISPLAY_PORT_INTERRUPT |
3796 3797 3798 3799 3800 3801 3802
			       I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
			       I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
			       I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
			       I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
			       I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);

	enable_mask = ~dev_priv->irq_mask;
3803 3804
	enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
			 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3805 3806 3807 3808
	enable_mask |= I915_USER_INTERRUPT;

	if (IS_G4X(dev))
		enable_mask |= I915_BSD_USER_INTERRUPT;
3809

3810 3811 3812
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3813 3814 3815
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3816
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3817 3818 3819 3820 3821 3822 3823 3824 3825 3826 3827 3828 3829 3830 3831 3832 3833 3834 3835 3836

	/*
	 * Enable some error detection, note the instruction error mask
	 * bit is reserved, so we leave it masked.
	 */
	if (IS_G4X(dev)) {
		error_mask = ~(GM45_ERROR_PAGE_TABLE |
			       GM45_ERROR_MEM_PRIV |
			       GM45_ERROR_CP_PRIV |
			       I915_ERROR_MEMORY_REFRESH);
	} else {
		error_mask = ~(I915_ERROR_PAGE_TABLE |
			       I915_ERROR_MEMORY_REFRESH);
	}
	I915_WRITE(EMR, error_mask);

	I915_WRITE(IMR, dev_priv->irq_mask);
	I915_WRITE(IER, enable_mask);
	POSTING_READ(IER);

3837 3838 3839
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	POSTING_READ(PORT_HOTPLUG_EN);

3840
	i915_enable_asle_pipestat(dev);
3841 3842 3843 3844

	return 0;
}

3845
static void i915_hpd_irq_setup(struct drm_device *dev)
3846
{
3847
	struct drm_i915_private *dev_priv = dev->dev_private;
3848
	struct drm_mode_config *mode_config = &dev->mode_config;
3849
	struct intel_encoder *intel_encoder;
3850 3851
	u32 hotplug_en;

3852 3853
	assert_spin_locked(&dev_priv->irq_lock);

3854 3855 3856 3857
	if (I915_HAS_HOTPLUG(dev)) {
		hotplug_en = I915_READ(PORT_HOTPLUG_EN);
		hotplug_en &= ~HOTPLUG_INT_EN_MASK;
		/* Note HDMI and DP share hotplug bits */
3858
		/* enable bits are the same for all generations */
3859 3860 3861
		list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
			if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
				hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
3862 3863 3864 3865 3866 3867
		/* Programming the CRT detection parameters tends
		   to generate a spurious hotplug event about three
		   seconds later.  So just do it once.
		*/
		if (IS_G4X(dev))
			hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
3868
		hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
3869
		hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
3870

3871 3872 3873
		/* Ignore TV since it's buggy */
		I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
	}
3874 3875
}

3876
static irqreturn_t i965_irq_handler(int irq, void *arg)
3877 3878
{
	struct drm_device *dev = (struct drm_device *) arg;
3879
	struct drm_i915_private *dev_priv = dev->dev_private;
3880 3881 3882 3883
	u32 iir, new_iir;
	u32 pipe_stats[I915_MAX_PIPES];
	unsigned long irqflags;
	int ret = IRQ_NONE, pipe;
3884 3885 3886
	u32 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3887 3888 3889 3890

	iir = I915_READ(IIR);

	for (;;) {
3891
		bool irq_received = (iir & ~flip_mask) != 0;
3892 3893
		bool blc_event = false;

3894 3895 3896 3897 3898 3899 3900
		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3901 3902 3903
			i915_handle_error(dev, false,
					  "Command parser error, iir 0x%08x",
					  iir);
3904 3905 3906 3907 3908 3909 3910 3911 3912 3913

		for_each_pipe(pipe) {
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);

			/*
			 * Clear the PIPE*STAT regs before the IIR
			 */
			if (pipe_stats[pipe] & 0x8000ffff) {
				I915_WRITE(reg, pipe_stats[pipe]);
3914
				irq_received = true;
3915 3916 3917 3918 3919 3920 3921 3922 3923 3924
			}
		}
		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

		if (!irq_received)
			break;

		ret = IRQ_HANDLED;

		/* Consume port.  Then clear IIR or we'll miss events */
3925 3926
		if (iir & I915_DISPLAY_PORT_INTERRUPT)
			i9xx_hpd_irq_handler(dev);
3927

3928
		I915_WRITE(IIR, iir & ~flip_mask);
3929 3930 3931 3932 3933 3934 3935 3936
		new_iir = I915_READ(IIR); /* Flush posted writes */

		if (iir & I915_USER_INTERRUPT)
			notify_ring(dev, &dev_priv->ring[RCS]);
		if (iir & I915_BSD_USER_INTERRUPT)
			notify_ring(dev, &dev_priv->ring[VCS]);

		for_each_pipe(pipe) {
3937
			if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
3938 3939
			    i915_handle_vblank(dev, pipe, pipe, iir))
				flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
3940 3941 3942

			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
				blc_event = true;
3943 3944

			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3945
				i9xx_pipe_crc_irq_handler(dev, pipe);
3946

3947 3948
			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
			    intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3949
				DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3950
		}
3951 3952 3953 3954

		if (blc_event || (iir & I915_ASLE_INTERRUPT))
			intel_opregion_asle_intr(dev);

3955 3956 3957
		if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
			gmbus_irq_handler(dev);

3958 3959 3960 3961 3962 3963 3964 3965 3966 3967 3968 3969 3970 3971 3972 3973 3974 3975
		/* With MSI, interrupts are only generated when iir
		 * transitions from zero to nonzero.  If another bit got
		 * set while we were handling the existing iir bits, then
		 * we would never get another interrupt.
		 *
		 * This is fine on non-MSI as well, as if we hit this path
		 * we avoid exiting the interrupt handler only to generate
		 * another one.
		 *
		 * Note that for MSI this could cause a stray interrupt report
		 * if an interrupt landed in the time between writing IIR and
		 * the posting read.  This should be rare enough to never
		 * trigger the 99% of 100,000 interrupts test for disabling
		 * stray interrupts.
		 */
		iir = new_iir;
	}

3976
	i915_update_dri1_breadcrumb(dev);
3977

3978 3979 3980 3981 3982
	return ret;
}

static void i965_irq_uninstall(struct drm_device * dev)
{
3983
	struct drm_i915_private *dev_priv = dev->dev_private;
3984 3985 3986 3987 3988
	int pipe;

	if (!dev_priv)
		return;

3989
	intel_hpd_irq_uninstall(dev_priv);
3990

3991 3992
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3993 3994 3995 3996 3997 3998 3999 4000 4001 4002 4003 4004 4005

	I915_WRITE(HWSTAM, 0xffffffff);
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);

	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe),
			   I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
	I915_WRITE(IIR, I915_READ(IIR));
}

4006
static void intel_hpd_irq_reenable(unsigned long data)
4007
{
4008
	struct drm_i915_private *dev_priv = (struct drm_i915_private *)data;
4009 4010 4011 4012 4013 4014 4015 4016 4017 4018 4019 4020 4021 4022 4023 4024 4025 4026 4027 4028 4029 4030 4031 4032 4033 4034 4035 4036 4037 4038 4039 4040
	struct drm_device *dev = dev_priv->dev;
	struct drm_mode_config *mode_config = &dev->mode_config;
	unsigned long irqflags;
	int i;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
	for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
		struct drm_connector *connector;

		if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
			continue;

		dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;

		list_for_each_entry(connector, &mode_config->connector_list, head) {
			struct intel_connector *intel_connector = to_intel_connector(connector);

			if (intel_connector->encoder->hpd_pin == i) {
				if (connector->polled != intel_connector->polled)
					DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
							 drm_get_connector_name(connector));
				connector->polled = intel_connector->polled;
				if (!connector->polled)
					connector->polled = DRM_CONNECTOR_POLL_HPD;
			}
		}
	}
	if (dev_priv->display.hpd_irq_setup)
		dev_priv->display.hpd_irq_setup(dev);
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

4041 4042
void intel_irq_init(struct drm_device *dev)
{
4043 4044 4045
	struct drm_i915_private *dev_priv = dev->dev_private;

	INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
4046
	INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
4047
	INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4048
	INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4049

4050 4051 4052
	/* Let's track the enabled rps events */
	dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;

4053 4054
	setup_timer(&dev_priv->gpu_error.hangcheck_timer,
		    i915_hangcheck_elapsed,
4055
		    (unsigned long) dev);
4056
	setup_timer(&dev_priv->hotplug_reenable_timer, intel_hpd_irq_reenable,
4057
		    (unsigned long) dev_priv);
4058

4059
	pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4060

4061 4062 4063 4064
	if (IS_GEN2(dev)) {
		dev->max_vblank_count = 0;
		dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
	} else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
4065 4066
		dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
		dev->driver->get_vblank_counter = gm45_get_vblank_counter;
4067 4068 4069
	} else {
		dev->driver->get_vblank_counter = i915_get_vblank_counter;
		dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4070 4071
	}

4072
	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
4073
		dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4074 4075
		dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
	}
4076

J
Jesse Barnes 已提交
4077 4078 4079 4080 4081 4082 4083
	if (IS_VALLEYVIEW(dev)) {
		dev->driver->irq_handler = valleyview_irq_handler;
		dev->driver->irq_preinstall = valleyview_irq_preinstall;
		dev->driver->irq_postinstall = valleyview_irq_postinstall;
		dev->driver->irq_uninstall = valleyview_irq_uninstall;
		dev->driver->enable_vblank = valleyview_enable_vblank;
		dev->driver->disable_vblank = valleyview_disable_vblank;
4084
		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4085 4086 4087 4088 4089 4090 4091 4092
	} else if (IS_GEN8(dev)) {
		dev->driver->irq_handler = gen8_irq_handler;
		dev->driver->irq_preinstall = gen8_irq_preinstall;
		dev->driver->irq_postinstall = gen8_irq_postinstall;
		dev->driver->irq_uninstall = gen8_irq_uninstall;
		dev->driver->enable_vblank = gen8_enable_vblank;
		dev->driver->disable_vblank = gen8_disable_vblank;
		dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4093 4094 4095 4096 4097 4098 4099
	} else if (HAS_PCH_SPLIT(dev)) {
		dev->driver->irq_handler = ironlake_irq_handler;
		dev->driver->irq_preinstall = ironlake_irq_preinstall;
		dev->driver->irq_postinstall = ironlake_irq_postinstall;
		dev->driver->irq_uninstall = ironlake_irq_uninstall;
		dev->driver->enable_vblank = ironlake_enable_vblank;
		dev->driver->disable_vblank = ironlake_disable_vblank;
4100
		dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4101
	} else {
C
Chris Wilson 已提交
4102 4103 4104 4105 4106
		if (INTEL_INFO(dev)->gen == 2) {
			dev->driver->irq_preinstall = i8xx_irq_preinstall;
			dev->driver->irq_postinstall = i8xx_irq_postinstall;
			dev->driver->irq_handler = i8xx_irq_handler;
			dev->driver->irq_uninstall = i8xx_irq_uninstall;
4107 4108 4109 4110 4111
		} else if (INTEL_INFO(dev)->gen == 3) {
			dev->driver->irq_preinstall = i915_irq_preinstall;
			dev->driver->irq_postinstall = i915_irq_postinstall;
			dev->driver->irq_uninstall = i915_irq_uninstall;
			dev->driver->irq_handler = i915_irq_handler;
4112
			dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
C
Chris Wilson 已提交
4113
		} else {
4114 4115 4116 4117
			dev->driver->irq_preinstall = i965_irq_preinstall;
			dev->driver->irq_postinstall = i965_irq_postinstall;
			dev->driver->irq_uninstall = i965_irq_uninstall;
			dev->driver->irq_handler = i965_irq_handler;
4118
			dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
C
Chris Wilson 已提交
4119
		}
4120 4121 4122 4123
		dev->driver->enable_vblank = i915_enable_vblank;
		dev->driver->disable_vblank = i915_disable_vblank;
	}
}
4124 4125 4126 4127

void intel_hpd_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
4128 4129
	struct drm_mode_config *mode_config = &dev->mode_config;
	struct drm_connector *connector;
4130
	unsigned long irqflags;
4131
	int i;
4132

4133 4134 4135 4136 4137 4138 4139 4140 4141 4142
	for (i = 1; i < HPD_NUM_PINS; i++) {
		dev_priv->hpd_stats[i].hpd_cnt = 0;
		dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
	}
	list_for_each_entry(connector, &mode_config->connector_list, head) {
		struct intel_connector *intel_connector = to_intel_connector(connector);
		connector->polled = intel_connector->polled;
		if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
			connector->polled = DRM_CONNECTOR_POLL_HPD;
	}
4143 4144 4145 4146

	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked checks happy. */
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4147 4148
	if (dev_priv->display.hpd_irq_setup)
		dev_priv->display.hpd_irq_setup(dev);
4149
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4150
}
4151

4152 4153
/* Disable interrupts so we can allow runtime PM. */
void hsw_runtime_pm_disable_interrupts(struct drm_device *dev)
4154 4155 4156 4157 4158 4159
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);

4160 4161 4162 4163 4164
	dev_priv->pm.regsave.deimr = I915_READ(DEIMR);
	dev_priv->pm.regsave.sdeimr = I915_READ(SDEIMR);
	dev_priv->pm.regsave.gtimr = I915_READ(GTIMR);
	dev_priv->pm.regsave.gtier = I915_READ(GTIER);
	dev_priv->pm.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR);
4165

4166 4167
	ironlake_disable_display_irq(dev_priv, 0xffffffff);
	ibx_disable_display_interrupt(dev_priv, 0xffffffff);
4168 4169 4170
	ilk_disable_gt_irq(dev_priv, 0xffffffff);
	snb_disable_pm_irq(dev_priv, 0xffffffff);

4171
	dev_priv->pm.irqs_disabled = true;
4172 4173 4174 4175

	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

4176 4177
/* Restore interrupts so we can recover from runtime PM. */
void hsw_runtime_pm_restore_interrupts(struct drm_device *dev)
4178 4179 4180
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long irqflags;
4181
	uint32_t val;
4182 4183 4184 4185

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);

	val = I915_READ(DEIMR);
4186
	WARN(val != 0xffffffff, "DEIMR is 0x%08x\n", val);
4187

4188 4189
	val = I915_READ(SDEIMR);
	WARN(val != 0xffffffff, "SDEIMR is 0x%08x\n", val);
4190 4191

	val = I915_READ(GTIMR);
4192
	WARN(val != 0xffffffff, "GTIMR is 0x%08x\n", val);
4193 4194

	val = I915_READ(GEN6_PMIMR);
4195
	WARN(val != 0xffffffff, "GEN6_PMIMR is 0x%08x\n", val);
4196

4197
	dev_priv->pm.irqs_disabled = false;
4198

4199 4200 4201 4202 4203
	ironlake_enable_display_irq(dev_priv, ~dev_priv->pm.regsave.deimr);
	ibx_enable_display_interrupt(dev_priv, ~dev_priv->pm.regsave.sdeimr);
	ilk_enable_gt_irq(dev_priv, ~dev_priv->pm.regsave.gtimr);
	snb_enable_pm_irq(dev_priv, ~dev_priv->pm.regsave.gen6_pmimr);
	I915_WRITE(GTIER, dev_priv->pm.regsave.gtier);
4204 4205 4206

	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}