i915_irq.c 83.1 KB
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/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
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 */
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/*
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

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#include <linux/sysrq.h>
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#include <linux/slab.h>
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#include <drm/drmP.h>
#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#include "i915_trace.h"
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#include "intel_drv.h"
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static const u32 hpd_ibx[] = {
	[HPD_CRT] = SDE_CRT_HOTPLUG,
	[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
	[HPD_PORT_B] = SDE_PORTB_HOTPLUG,
	[HPD_PORT_C] = SDE_PORTC_HOTPLUG,
	[HPD_PORT_D] = SDE_PORTD_HOTPLUG
};

static const u32 hpd_cpt[] = {
	[HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
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	[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
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	[HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
	[HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
	[HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
};

static const u32 hpd_mask_i915[] = {
	[HPD_CRT] = CRT_HOTPLUG_INT_EN,
	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
	[HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
	[HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
	[HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
};

static const u32 hpd_status_gen4[] = {
	[HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
	[HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
	[HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
	[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
};

static const u32 hpd_status_i965[] = {
	 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
	 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I965,
	 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I965,
	 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
	 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
	 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
};

static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
	[HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
	[HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
	[HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
	[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
};



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/* For display hotplug interrupt */
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static void
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ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
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{
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	if ((dev_priv->irq_mask & mask) != 0) {
		dev_priv->irq_mask &= ~mask;
		I915_WRITE(DEIMR, dev_priv->irq_mask);
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		POSTING_READ(DEIMR);
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	}
}

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static void
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ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
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{
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	if ((dev_priv->irq_mask & mask) != mask) {
		dev_priv->irq_mask |= mask;
		I915_WRITE(DEIMR, dev_priv->irq_mask);
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		POSTING_READ(DEIMR);
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	}
}

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void
i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
{
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	u32 reg = PIPESTAT(pipe);
	u32 pipestat = I915_READ(reg) & 0x7fff0000;
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	if ((pipestat & mask) == mask)
		return;

	/* Enable the interrupt, clear any pending status */
	pipestat |= mask | (mask >> 16);
	I915_WRITE(reg, pipestat);
	POSTING_READ(reg);
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}

void
i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
{
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	u32 reg = PIPESTAT(pipe);
	u32 pipestat = I915_READ(reg) & 0x7fff0000;
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	if ((pipestat & mask) == 0)
		return;

	pipestat &= ~mask;
	I915_WRITE(reg, pipestat);
	POSTING_READ(reg);
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}

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/**
 * intel_enable_asle - enable ASLE interrupt for OpRegion
 */
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void intel_enable_asle(struct drm_device *dev)
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{
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	drm_i915_private_t *dev_priv = dev->dev_private;
	unsigned long irqflags;

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	/* FIXME: opregion/asle for VLV */
	if (IS_VALLEYVIEW(dev))
		return;

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	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
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	if (HAS_PCH_SPLIT(dev))
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		ironlake_enable_display_irq(dev_priv, DE_GSE);
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	else {
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		i915_enable_pipestat(dev_priv, 1,
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				     PIPE_LEGACY_BLC_EVENT_ENABLE);
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		if (INTEL_INFO(dev)->gen >= 4)
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			i915_enable_pipestat(dev_priv, 0,
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					     PIPE_LEGACY_BLC_EVENT_ENABLE);
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	}
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	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
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}

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/**
 * i915_pipe_enabled - check if a pipe is enabled
 * @dev: DRM device
 * @pipe: pipe to check
 *
 * Reading certain registers when the pipe is disabled can hang the chip.
 * Use this routine to make sure the PLL is running and the pipe is active
 * before reading such registers if unsure.
 */
static int
i915_pipe_enabled(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
								      pipe);

	return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
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}

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/* Called from drm generic code, passed a 'crtc', which
 * we use as a pipe index
 */
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static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
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{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long high_frame;
	unsigned long low_frame;
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	u32 high1, high2, low;
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	if (!i915_pipe_enabled(dev, pipe)) {
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		DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
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				"pipe %c\n", pipe_name(pipe));
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		return 0;
	}

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	high_frame = PIPEFRAME(pipe);
	low_frame = PIPEFRAMEPIXEL(pipe);
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	/*
	 * High & low register fields aren't synchronized, so make sure
	 * we get a low value that's stable across two reads of the high
	 * register.
	 */
	do {
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		high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
		low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
		high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
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	} while (high1 != high2);

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	high1 >>= PIPE_FRAME_HIGH_SHIFT;
	low >>= PIPE_FRAME_LOW_SHIFT;
	return (high1 << 8) | low;
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}

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static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
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{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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	int reg = PIPE_FRMCOUNT_GM45(pipe);
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	if (!i915_pipe_enabled(dev, pipe)) {
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		DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
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				 "pipe %c\n", pipe_name(pipe));
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		return 0;
	}

	return I915_READ(reg);
}

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static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
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			     int *vpos, int *hpos)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u32 vbl = 0, position = 0;
	int vbl_start, vbl_end, htotal, vtotal;
	bool in_vbl = true;
	int ret = 0;
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	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
								      pipe);
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	if (!i915_pipe_enabled(dev, pipe)) {
		DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
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				 "pipe %c\n", pipe_name(pipe));
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		return 0;
	}

	/* Get vtotal. */
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	vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
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	if (INTEL_INFO(dev)->gen >= 4) {
		/* No obvious pixelcount register. Only query vertical
		 * scanout position from Display scan line register.
		 */
		position = I915_READ(PIPEDSL(pipe));

		/* Decode into vertical scanout position. Don't have
		 * horizontal scanout position.
		 */
		*vpos = position & 0x1fff;
		*hpos = 0;
	} else {
		/* Have access to pixelcount since start of frame.
		 * We can split this into vertical and horizontal
		 * scanout position.
		 */
		position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;

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		htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
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		*vpos = position / htotal;
		*hpos = position - (*vpos * htotal);
	}

	/* Query vblank area. */
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	vbl = I915_READ(VBLANK(cpu_transcoder));
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	/* Test position against vblank region. */
	vbl_start = vbl & 0x1fff;
	vbl_end = (vbl >> 16) & 0x1fff;

	if ((*vpos < vbl_start) || (*vpos > vbl_end))
		in_vbl = false;

	/* Inside "upper part" of vblank area? Apply corrective offset: */
	if (in_vbl && (*vpos >= vbl_start))
		*vpos = *vpos - vtotal;

	/* Readouts valid? */
	if (vbl > 0)
		ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;

	/* In vblank? */
	if (in_vbl)
		ret |= DRM_SCANOUTPOS_INVBL;

	return ret;
}

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static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
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			      int *max_error,
			      struct timeval *vblank_time,
			      unsigned flags)
{
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	struct drm_crtc *crtc;
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	if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
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		DRM_ERROR("Invalid crtc %d\n", pipe);
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		return -EINVAL;
	}

	/* Get drm_crtc to timestamp: */
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	crtc = intel_get_crtc_for_pipe(dev, pipe);
	if (crtc == NULL) {
		DRM_ERROR("Invalid crtc %d\n", pipe);
		return -EINVAL;
	}

	if (!crtc->enabled) {
		DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
		return -EBUSY;
	}
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	/* Helper routine in DRM core does all the work: */
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	return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
						     vblank_time, flags,
						     crtc);
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}

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/*
 * Handle hotplug events outside the interrupt handler proper.
 */
static void i915_hotplug_work_func(struct work_struct *work)
{
	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
						    hotplug_work);
	struct drm_device *dev = dev_priv->dev;
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	struct drm_mode_config *mode_config = &dev->mode_config;
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	struct intel_encoder *encoder;

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	/* HPD irq before everything is fully set up. */
	if (!dev_priv->enable_hotplug_processing)
		return;

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	mutex_lock(&mode_config->mutex);
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	DRM_DEBUG_KMS("running encoder hotplug functions\n");

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	list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
		if (encoder->hot_plug)
			encoder->hot_plug(encoder);

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	mutex_unlock(&mode_config->mutex);

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	/* Just fire off a uevent and let userspace tell us what to do */
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	drm_helper_hpd_irq_event(dev);
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}

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static void ironlake_handle_rps_change(struct drm_device *dev)
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{
	drm_i915_private_t *dev_priv = dev->dev_private;
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	u32 busy_up, busy_down, max_avg, min_avg;
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	u8 new_delay;
	unsigned long flags;

	spin_lock_irqsave(&mchdev_lock, flags);
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	I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));

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	new_delay = dev_priv->ips.cur_delay;
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	I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
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	busy_up = I915_READ(RCPREVBSYTUPAVG);
	busy_down = I915_READ(RCPREVBSYTDNAVG);
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	max_avg = I915_READ(RCBMAXAVG);
	min_avg = I915_READ(RCBMINAVG);

	/* Handle RCS change request from hw */
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	if (busy_up > max_avg) {
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		if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
			new_delay = dev_priv->ips.cur_delay - 1;
		if (new_delay < dev_priv->ips.max_delay)
			new_delay = dev_priv->ips.max_delay;
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	} else if (busy_down < min_avg) {
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		if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
			new_delay = dev_priv->ips.cur_delay + 1;
		if (new_delay > dev_priv->ips.min_delay)
			new_delay = dev_priv->ips.min_delay;
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	}

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	if (ironlake_set_drps(dev, new_delay))
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		dev_priv->ips.cur_delay = new_delay;
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	spin_unlock_irqrestore(&mchdev_lock, flags);

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	return;
}

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static void notify_ring(struct drm_device *dev,
			struct intel_ring_buffer *ring)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
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	if (ring->obj == NULL)
		return;

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	trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
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	wake_up_all(&ring->irq_queue);
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	if (i915_enable_hangcheck) {
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		dev_priv->gpu_error.hangcheck_count = 0;
		mod_timer(&dev_priv->gpu_error.hangcheck_timer,
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			  round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
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	}
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}

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static void gen6_pm_rps_work(struct work_struct *work)
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{
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	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
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						    rps.work);
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	u32 pm_iir, pm_imr;
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	u8 new_delay;
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	spin_lock_irq(&dev_priv->rps.lock);
	pm_iir = dev_priv->rps.pm_iir;
	dev_priv->rps.pm_iir = 0;
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	pm_imr = I915_READ(GEN6_PMIMR);
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	I915_WRITE(GEN6_PMIMR, 0);
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	spin_unlock_irq(&dev_priv->rps.lock);
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	if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
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		return;

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	mutex_lock(&dev_priv->rps.hw_lock);
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	if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
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		new_delay = dev_priv->rps.cur_delay + 1;
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	else
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		new_delay = dev_priv->rps.cur_delay - 1;
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	/* sysfs frequency interfaces may have snuck in while servicing the
	 * interrupt
	 */
	if (!(new_delay > dev_priv->rps.max_delay ||
	      new_delay < dev_priv->rps.min_delay)) {
		gen6_set_rps(dev_priv->dev, new_delay);
	}
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	mutex_unlock(&dev_priv->rps.hw_lock);
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}

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/**
 * ivybridge_parity_work - Workqueue called when a parity error interrupt
 * occurred.
 * @work: workqueue struct
 *
 * Doesn't actually do anything except notify userspace. As a consequence of
 * this event, userspace should try to remap the bad rows since statistically
 * it is likely the same row is more likely to go bad again.
 */
static void ivybridge_parity_work(struct work_struct *work)
{
	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
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						    l3_parity.error_work);
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	u32 error_status, row, bank, subbank;
	char *parity_event[5];
	uint32_t misccpctl;
	unsigned long flags;

	/* We must turn off DOP level clock gating to access the L3 registers.
	 * In order to prevent a get/put style interface, acquire struct mutex
	 * any time we access those registers.
	 */
	mutex_lock(&dev_priv->dev->struct_mutex);

	misccpctl = I915_READ(GEN7_MISCCPCTL);
	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
	POSTING_READ(GEN7_MISCCPCTL);

	error_status = I915_READ(GEN7_L3CDERRST1);
	row = GEN7_PARITY_ERROR_ROW(error_status);
	bank = GEN7_PARITY_ERROR_BANK(error_status);
	subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);

	I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
				    GEN7_L3CDERRST1_ENABLE);
	POSTING_READ(GEN7_L3CDERRST1);

	I915_WRITE(GEN7_MISCCPCTL, misccpctl);

	spin_lock_irqsave(&dev_priv->irq_lock, flags);
	dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);

	mutex_unlock(&dev_priv->dev->struct_mutex);

	parity_event[0] = "L3_PARITY_ERROR=1";
	parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
	parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
	parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
	parity_event[4] = NULL;

	kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
			   KOBJ_CHANGE, parity_event);

	DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
		  row, bank, subbank);

	kfree(parity_event[3]);
	kfree(parity_event[2]);
	kfree(parity_event[1]);
}

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static void ivybridge_handle_parity_error(struct drm_device *dev)
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{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long flags;

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	if (!HAS_L3_GPU_CACHE(dev))
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		return;

	spin_lock_irqsave(&dev_priv->irq_lock, flags);
	dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);

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	queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
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}

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static void snb_gt_irq_handler(struct drm_device *dev,
			       struct drm_i915_private *dev_priv,
			       u32 gt_iir)
{

	if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
		      GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
		notify_ring(dev, &dev_priv->ring[RCS]);
	if (gt_iir & GEN6_BSD_USER_INTERRUPT)
		notify_ring(dev, &dev_priv->ring[VCS]);
	if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
		notify_ring(dev, &dev_priv->ring[BCS]);

	if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
		      GT_GEN6_BSD_CS_ERROR_INTERRUPT |
		      GT_RENDER_CS_ERROR_INTERRUPT)) {
		DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
		i915_handle_error(dev, false);
	}
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	if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
		ivybridge_handle_parity_error(dev);
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}

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static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
				u32 pm_iir)
{
	unsigned long flags;

	/*
	 * IIR bits should never already be set because IMR should
	 * prevent an interrupt from being shown in IIR. The warning
	 * displays a case where we've unsafely cleared
570
	 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
571 572
	 * type is not a problem, it displays a problem in the logic.
	 *
573
	 * The mask bit in IMR is cleared by dev_priv->rps.work.
574 575
	 */

576 577 578
	spin_lock_irqsave(&dev_priv->rps.lock, flags);
	dev_priv->rps.pm_iir |= pm_iir;
	I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
579
	POSTING_READ(GEN6_PMIMR);
580
	spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
581

582
	queue_work(dev_priv->wq, &dev_priv->rps.work);
583 584
}

585 586
static void gmbus_irq_handler(struct drm_device *dev)
{
587 588 589
	struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;

	wake_up_all(&dev_priv->gmbus_wait_queue);
590 591
}

592 593
static void dp_aux_irq_handler(struct drm_device *dev)
{
594 595 596
	struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;

	wake_up_all(&dev_priv->gmbus_wait_queue);
597 598
}

599
static irqreturn_t valleyview_irq_handler(int irq, void *arg)
J
Jesse Barnes 已提交
600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620
{
	struct drm_device *dev = (struct drm_device *) arg;
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u32 iir, gt_iir, pm_iir;
	irqreturn_t ret = IRQ_NONE;
	unsigned long irqflags;
	int pipe;
	u32 pipe_stats[I915_MAX_PIPES];

	atomic_inc(&dev_priv->irq_received);

	while (true) {
		iir = I915_READ(VLV_IIR);
		gt_iir = I915_READ(GTIIR);
		pm_iir = I915_READ(GEN6_PMIIR);

		if (gt_iir == 0 && pm_iir == 0 && iir == 0)
			goto out;

		ret = IRQ_HANDLED;

621
		snb_gt_irq_handler(dev, dev_priv, gt_iir);
J
Jesse Barnes 已提交
622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639

		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
		for_each_pipe(pipe) {
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);

			/*
			 * Clear the PIPE*STAT regs before the IIR
			 */
			if (pipe_stats[pipe] & 0x8000ffff) {
				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
					DRM_DEBUG_DRIVER("pipe %c underrun\n",
							 pipe_name(pipe));
				I915_WRITE(reg, pipe_stats[pipe]);
			}
		}
		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

640 641 642 643 644 645 646 647 648 649
		for_each_pipe(pipe) {
			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
				drm_handle_vblank(dev, pipe);

			if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
				intel_prepare_page_flip(dev, pipe);
				intel_finish_page_flip(dev, pipe);
			}
		}

J
Jesse Barnes 已提交
650 651 652 653 654 655
		/* Consume port.  Then clear IIR or we'll miss events */
		if (iir & I915_DISPLAY_PORT_INTERRUPT) {
			u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);

			DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
					 hotplug_status);
656
			if (hotplug_status & HOTPLUG_INT_STATUS_I915)
J
Jesse Barnes 已提交
657 658 659 660 661 662 663
				queue_work(dev_priv->wq,
					   &dev_priv->hotplug_work);

			I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
			I915_READ(PORT_HOTPLUG_STAT);
		}

664 665
		if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
			gmbus_irq_handler(dev);
J
Jesse Barnes 已提交
666

667 668
		if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
			gen6_queue_rps_work(dev_priv, pm_iir);
J
Jesse Barnes 已提交
669 670 671 672 673 674 675 676 677 678

		I915_WRITE(GTIIR, gt_iir);
		I915_WRITE(GEN6_PMIIR, pm_iir);
		I915_WRITE(VLV_IIR, iir);
	}

out:
	return ret;
}

679
static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
680 681
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
682
	int pipe;
683

684 685 686
	if (pch_iir & SDE_HOTPLUG_MASK)
		queue_work(dev_priv->wq, &dev_priv->hotplug_work);

687 688 689 690 691
	if (pch_iir & SDE_AUDIO_POWER_MASK)
		DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
				 (pch_iir & SDE_AUDIO_POWER_MASK) >>
				 SDE_AUDIO_POWER_SHIFT);

692 693 694
	if (pch_iir & SDE_AUX_MASK)
		dp_aux_irq_handler(dev);

695
	if (pch_iir & SDE_GMBUS)
696
		gmbus_irq_handler(dev);
697 698 699 700 701 702 703 704 705 706

	if (pch_iir & SDE_AUDIO_HDCP_MASK)
		DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");

	if (pch_iir & SDE_AUDIO_TRANS_MASK)
		DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");

	if (pch_iir & SDE_POISON)
		DRM_ERROR("PCH poison interrupt\n");

707 708 709 710 711
	if (pch_iir & SDE_FDI_MASK)
		for_each_pipe(pipe)
			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
					 pipe_name(pipe),
					 I915_READ(FDI_RX_IIR(pipe)));
712 713 714 715 716 717 718 719 720 721 722 723 724

	if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
		DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");

	if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
		DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");

	if (pch_iir & SDE_TRANSB_FIFO_UNDER)
		DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
	if (pch_iir & SDE_TRANSA_FIFO_UNDER)
		DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
}

725 726 727 728 729
static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;

730 731 732
	if (pch_iir & SDE_HOTPLUG_MASK_CPT)
		queue_work(dev_priv->wq, &dev_priv->hotplug_work);

733 734 735 736 737 738
	if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
		DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
				 (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
				 SDE_AUDIO_POWER_SHIFT_CPT);

	if (pch_iir & SDE_AUX_MASK_CPT)
739
		dp_aux_irq_handler(dev);
740 741

	if (pch_iir & SDE_GMBUS_CPT)
742
		gmbus_irq_handler(dev);
743 744 745 746 747 748 749 750 751 752 753 754 755 756

	if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
		DRM_DEBUG_DRIVER("Audio CP request interrupt\n");

	if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
		DRM_DEBUG_DRIVER("Audio CP change interrupt\n");

	if (pch_iir & SDE_FDI_MASK_CPT)
		for_each_pipe(pipe)
			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
					 pipe_name(pipe),
					 I915_READ(FDI_RX_IIR(pipe)));
}

757
static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
758 759 760
{
	struct drm_device *dev = (struct drm_device *) arg;
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
761
	u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier = 0;
762 763
	irqreturn_t ret = IRQ_NONE;
	int i;
764 765 766 767 768 769 770

	atomic_inc(&dev_priv->irq_received);

	/* disable master interrupt before clearing iir  */
	de_ier = I915_READ(DEIER);
	I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);

771 772 773 774 775
	/* Disable south interrupts. We'll only write to SDEIIR once, so further
	 * interrupts will will be stored on its back queue, and then we'll be
	 * able to process them after we restore SDEIER (as soon as we restore
	 * it, we'll get an interrupt if SDEIIR still has something to process
	 * due to its back queue). */
776 777 778 779 780
	if (!HAS_PCH_NOP(dev)) {
		sde_ier = I915_READ(SDEIER);
		I915_WRITE(SDEIER, 0);
		POSTING_READ(SDEIER);
	}
781

782
	gt_iir = I915_READ(GTIIR);
783 784 785 786
	if (gt_iir) {
		snb_gt_irq_handler(dev, dev_priv, gt_iir);
		I915_WRITE(GTIIR, gt_iir);
		ret = IRQ_HANDLED;
787 788
	}

789 790
	de_iir = I915_READ(DEIIR);
	if (de_iir) {
791 792 793
		if (de_iir & DE_AUX_CHANNEL_A_IVB)
			dp_aux_irq_handler(dev);

794 795 796 797
		if (de_iir & DE_GSE_IVB)
			intel_opregion_gse_intr(dev);

		for (i = 0; i < 3; i++) {
798 799
			if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
				drm_handle_vblank(dev, i);
800 801 802 803 804
			if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
				intel_prepare_page_flip(dev, i);
				intel_finish_page_flip_plane(dev, i);
			}
		}
805

806
		/* check event from PCH */
807
		if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
808
			u32 pch_iir = I915_READ(SDEIIR);
809

810
			cpt_irq_handler(dev, pch_iir);
811

812 813 814
			/* clear PCH hotplug event before clear CPU irq */
			I915_WRITE(SDEIIR, pch_iir);
		}
815

816 817
		I915_WRITE(DEIIR, de_iir);
		ret = IRQ_HANDLED;
818 819
	}

820 821 822 823 824 825 826
	pm_iir = I915_READ(GEN6_PMIIR);
	if (pm_iir) {
		if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
			gen6_queue_rps_work(dev_priv, pm_iir);
		I915_WRITE(GEN6_PMIIR, pm_iir);
		ret = IRQ_HANDLED;
	}
827 828 829

	I915_WRITE(DEIER, de_ier);
	POSTING_READ(DEIER);
830 831 832 833
	if (!HAS_PCH_NOP(dev)) {
		I915_WRITE(SDEIER, sde_ier);
		POSTING_READ(SDEIER);
	}
834 835 836 837

	return ret;
}

838 839 840 841 842 843 844 845 846 847
static void ilk_gt_irq_handler(struct drm_device *dev,
			       struct drm_i915_private *dev_priv,
			       u32 gt_iir)
{
	if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
		notify_ring(dev, &dev_priv->ring[RCS]);
	if (gt_iir & GT_BSD_USER_INTERRUPT)
		notify_ring(dev, &dev_priv->ring[VCS]);
}

848
static irqreturn_t ironlake_irq_handler(int irq, void *arg)
849
{
850
	struct drm_device *dev = (struct drm_device *) arg;
851 852
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int ret = IRQ_NONE;
853
	u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
854

855 856
	atomic_inc(&dev_priv->irq_received);

857 858 859
	/* disable master interrupt before clearing iir  */
	de_ier = I915_READ(DEIER);
	I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
860
	POSTING_READ(DEIER);
861

862 863 864 865 866 867 868 869 870
	/* Disable south interrupts. We'll only write to SDEIIR once, so further
	 * interrupts will will be stored on its back queue, and then we'll be
	 * able to process them after we restore SDEIER (as soon as we restore
	 * it, we'll get an interrupt if SDEIIR still has something to process
	 * due to its back queue). */
	sde_ier = I915_READ(SDEIER);
	I915_WRITE(SDEIER, 0);
	POSTING_READ(SDEIER);

871 872
	de_iir = I915_READ(DEIIR);
	gt_iir = I915_READ(GTIIR);
873
	pm_iir = I915_READ(GEN6_PMIIR);
874

875
	if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
876
		goto done;
877

878
	ret = IRQ_HANDLED;
879

880 881 882 883
	if (IS_GEN5(dev))
		ilk_gt_irq_handler(dev, dev_priv, gt_iir);
	else
		snb_gt_irq_handler(dev, dev_priv, gt_iir);
884

885 886 887
	if (de_iir & DE_AUX_CHANNEL_A)
		dp_aux_irq_handler(dev);

888
	if (de_iir & DE_GSE)
889
		intel_opregion_gse_intr(dev);
890

891 892 893 894 895 896
	if (de_iir & DE_PIPEA_VBLANK)
		drm_handle_vblank(dev, 0);

	if (de_iir & DE_PIPEB_VBLANK)
		drm_handle_vblank(dev, 1);

897
	if (de_iir & DE_PLANEA_FLIP_DONE) {
898
		intel_prepare_page_flip(dev, 0);
899
		intel_finish_page_flip_plane(dev, 0);
900
	}
901

902
	if (de_iir & DE_PLANEB_FLIP_DONE) {
903
		intel_prepare_page_flip(dev, 1);
904
		intel_finish_page_flip_plane(dev, 1);
905
	}
906

907
	/* check event from PCH */
908
	if (de_iir & DE_PCH_EVENT) {
909 910
		u32 pch_iir = I915_READ(SDEIIR);

911 912 913 914
		if (HAS_PCH_CPT(dev))
			cpt_irq_handler(dev, pch_iir);
		else
			ibx_irq_handler(dev, pch_iir);
915 916 917

		/* should clear PCH hotplug event before clear CPU irq */
		I915_WRITE(SDEIIR, pch_iir);
918
	}
919

920 921
	if (IS_GEN5(dev) &&  de_iir & DE_PCU_EVENT)
		ironlake_handle_rps_change(dev);
922

923 924
	if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
		gen6_queue_rps_work(dev_priv, pm_iir);
925

926 927
	I915_WRITE(GTIIR, gt_iir);
	I915_WRITE(DEIIR, de_iir);
928
	I915_WRITE(GEN6_PMIIR, pm_iir);
929 930

done:
931
	I915_WRITE(DEIER, de_ier);
932
	POSTING_READ(DEIER);
933 934
	I915_WRITE(SDEIER, sde_ier);
	POSTING_READ(SDEIER);
935

936 937 938
	return ret;
}

939 940 941 942 943 944 945 946 947
/**
 * i915_error_work_func - do process context error handling work
 * @work: work struct
 *
 * Fire an error uevent so userspace can see that a hang or error
 * was detected.
 */
static void i915_error_work_func(struct work_struct *work)
{
948 949 950 951
	struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
						    work);
	drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
						    gpu_error);
952
	struct drm_device *dev = dev_priv->dev;
953
	struct intel_ring_buffer *ring;
954 955 956
	char *error_event[] = { "ERROR=1", NULL };
	char *reset_event[] = { "RESET=1", NULL };
	char *reset_done_event[] = { "ERROR=0", NULL };
957
	int i, ret;
958

959 960
	kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);

961 962 963 964 965 966 967 968 969 970 971
	/*
	 * Note that there's only one work item which does gpu resets, so we
	 * need not worry about concurrent gpu resets potentially incrementing
	 * error->reset_counter twice. We only need to take care of another
	 * racing irq/hangcheck declaring the gpu dead for a second time. A
	 * quick check for that is good enough: schedule_work ensures the
	 * correct ordering between hang detection and this work item, and since
	 * the reset in-progress bit is only ever set by code outside of this
	 * work we don't need to worry about any other races.
	 */
	if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
972
		DRM_DEBUG_DRIVER("resetting chip\n");
973 974
		kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
				   reset_event);
975

976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993
		ret = i915_reset(dev);

		if (ret == 0) {
			/*
			 * After all the gem state is reset, increment the reset
			 * counter and wake up everyone waiting for the reset to
			 * complete.
			 *
			 * Since unlock operations are a one-sided barrier only,
			 * we need to insert a barrier here to order any seqno
			 * updates before
			 * the counter increment.
			 */
			smp_mb__before_atomic_inc();
			atomic_inc(&dev_priv->gpu_error.reset_counter);

			kobject_uevent_env(&dev->primary->kdev.kobj,
					   KOBJ_CHANGE, reset_done_event);
994 995
		} else {
			atomic_set(&error->reset_counter, I915_WEDGED);
996
		}
997

998 999 1000
		for_each_ring(ring, dev_priv, i)
			wake_up_all(&ring->irq_queue);

1001 1002
		intel_display_handle_reset(dev);

1003
		wake_up_all(&dev_priv->gpu_error.reset_queue);
1004
	}
1005 1006
}

1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035
/* NB: please notice the memset */
static void i915_get_extra_instdone(struct drm_device *dev,
				    uint32_t *instdone)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);

	switch(INTEL_INFO(dev)->gen) {
	case 2:
	case 3:
		instdone[0] = I915_READ(INSTDONE);
		break;
	case 4:
	case 5:
	case 6:
		instdone[0] = I915_READ(INSTDONE_I965);
		instdone[1] = I915_READ(INSTDONE1);
		break;
	default:
		WARN_ONCE(1, "Unsupported platform\n");
	case 7:
		instdone[0] = I915_READ(GEN7_INSTDONE_1);
		instdone[1] = I915_READ(GEN7_SC_INSTDONE);
		instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
		instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
		break;
	}
}

1036
#ifdef CONFIG_DEBUG_FS
1037
static struct drm_i915_error_object *
1038 1039 1040
i915_error_object_create_sized(struct drm_i915_private *dev_priv,
			       struct drm_i915_gem_object *src,
			       const int num_pages)
1041 1042
{
	struct drm_i915_error_object *dst;
1043
	int i;
1044
	u32 reloc_offset;
1045

1046
	if (src == NULL || src->pages == NULL)
1047 1048
		return NULL;

1049
	dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
1050 1051 1052
	if (dst == NULL)
		return NULL;

1053
	reloc_offset = src->gtt_offset;
1054
	for (i = 0; i < num_pages; i++) {
1055
		unsigned long flags;
1056
		void *d;
1057

1058
		d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
1059 1060
		if (d == NULL)
			goto unwind;
1061

1062
		local_irq_save(flags);
B
Ben Widawsky 已提交
1063
		if (reloc_offset < dev_priv->gtt.mappable_end &&
1064
		    src->has_global_gtt_mapping) {
1065 1066 1067 1068 1069 1070 1071
			void __iomem *s;

			/* Simply ignore tiling or any overlapping fence.
			 * It's part of the error state, and this hopefully
			 * captures what the GPU read.
			 */

B
Ben Widawsky 已提交
1072
			s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
1073 1074 1075
						     reloc_offset);
			memcpy_fromio(d, s, PAGE_SIZE);
			io_mapping_unmap_atomic(s);
1076 1077 1078 1079 1080 1081 1082
		} else if (src->stolen) {
			unsigned long offset;

			offset = dev_priv->mm.stolen_base;
			offset += src->stolen->start;
			offset += i << PAGE_SHIFT;

D
Daniel Vetter 已提交
1083
			memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
1084
		} else {
1085
			struct page *page;
1086 1087
			void *s;

1088
			page = i915_gem_object_get_page(src, i);
1089

1090 1091 1092
			drm_clflush_pages(&page, 1);

			s = kmap_atomic(page);
1093 1094 1095
			memcpy(d, s, PAGE_SIZE);
			kunmap_atomic(s);

1096
			drm_clflush_pages(&page, 1);
1097
		}
1098
		local_irq_restore(flags);
1099

1100
		dst->pages[i] = d;
1101 1102

		reloc_offset += PAGE_SIZE;
1103
	}
1104
	dst->page_count = num_pages;
1105
	dst->gtt_offset = src->gtt_offset;
1106 1107 1108 1109

	return dst;

unwind:
1110 1111
	while (i--)
		kfree(dst->pages[i]);
1112 1113 1114
	kfree(dst);
	return NULL;
}
1115 1116 1117
#define i915_error_object_create(dev_priv, src) \
	i915_error_object_create_sized((dev_priv), (src), \
				       (src)->base.size>>PAGE_SHIFT)
1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132

static void
i915_error_object_free(struct drm_i915_error_object *obj)
{
	int page;

	if (obj == NULL)
		return;

	for (page = 0; page < obj->page_count; page++)
		kfree(obj->pages[page]);

	kfree(obj);
}

1133 1134
void
i915_error_state_free(struct kref *error_ref)
1135
{
1136 1137
	struct drm_i915_error_state *error = container_of(error_ref,
							  typeof(*error), ref);
1138 1139
	int i;

1140 1141 1142 1143 1144
	for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
		i915_error_object_free(error->ring[i].batchbuffer);
		i915_error_object_free(error->ring[i].ringbuffer);
		kfree(error->ring[i].requests);
	}
1145

1146
	kfree(error->active_bo);
1147
	kfree(error->overlay);
1148 1149
	kfree(error);
}
1150 1151 1152 1153 1154
static void capture_bo(struct drm_i915_error_buffer *err,
		       struct drm_i915_gem_object *obj)
{
	err->size = obj->base.size;
	err->name = obj->base.name;
1155 1156
	err->rseqno = obj->last_read_seqno;
	err->wseqno = obj->last_write_seqno;
1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171
	err->gtt_offset = obj->gtt_offset;
	err->read_domains = obj->base.read_domains;
	err->write_domain = obj->base.write_domain;
	err->fence_reg = obj->fence_reg;
	err->pinned = 0;
	if (obj->pin_count > 0)
		err->pinned = 1;
	if (obj->user_pin_count > 0)
		err->pinned = -1;
	err->tiling = obj->tiling_mode;
	err->dirty = obj->dirty;
	err->purgeable = obj->madv != I915_MADV_WILLNEED;
	err->ring = obj->ring ? obj->ring->id : -1;
	err->cache_level = obj->cache_level;
}
1172

1173 1174
static u32 capture_active_bo(struct drm_i915_error_buffer *err,
			     int count, struct list_head *head)
1175 1176 1177 1178 1179
{
	struct drm_i915_gem_object *obj;
	int i = 0;

	list_for_each_entry(obj, head, mm_list) {
1180
		capture_bo(err++, obj);
1181 1182
		if (++i == count)
			break;
1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196
	}

	return i;
}

static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
			     int count, struct list_head *head)
{
	struct drm_i915_gem_object *obj;
	int i = 0;

	list_for_each_entry(obj, head, gtt_list) {
		if (obj->pin_count == 0)
			continue;
1197

1198 1199 1200
		capture_bo(err++, obj);
		if (++i == count)
			break;
1201 1202 1203 1204 1205
	}

	return i;
}

1206 1207 1208 1209 1210 1211 1212 1213
static void i915_gem_record_fences(struct drm_device *dev,
				   struct drm_i915_error_state *error)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;

	/* Fences */
	switch (INTEL_INFO(dev)->gen) {
1214
	case 7:
1215
	case 6:
1216
		for (i = 0; i < dev_priv->num_fence_regs; i++)
1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232
			error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
		break;
	case 5:
	case 4:
		for (i = 0; i < 16; i++)
			error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
		break;
	case 3:
		if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
			for (i = 0; i < 8; i++)
				error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
	case 2:
		for (i = 0; i < 8; i++)
			error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
		break;

1233 1234
	default:
		BUG();
1235 1236 1237
	}
}

1238 1239 1240 1241 1242 1243 1244 1245 1246 1247
static struct drm_i915_error_object *
i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
			     struct intel_ring_buffer *ring)
{
	struct drm_i915_gem_object *obj;
	u32 seqno;

	if (!ring->get_seqno)
		return NULL;

1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259
	if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
		u32 acthd = I915_READ(ACTHD);

		if (WARN_ON(ring->id != RCS))
			return NULL;

		obj = ring->private;
		if (acthd >= obj->gtt_offset &&
		    acthd < obj->gtt_offset + obj->base.size)
			return i915_error_object_create(dev_priv, obj);
	}

1260
	seqno = ring->get_seqno(ring, false);
1261 1262 1263 1264
	list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
		if (obj->ring != ring)
			continue;

1265
		if (i915_seqno_passed(seqno, obj->last_read_seqno))
1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279
			continue;

		if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
			continue;

		/* We need to copy these to an anonymous buffer as the simplest
		 * method to avoid being overwritten by userspace.
		 */
		return i915_error_object_create(dev_priv, obj);
	}

	return NULL;
}

1280 1281 1282 1283 1284 1285
static void i915_record_ring_state(struct drm_device *dev,
				   struct drm_i915_error_state *error,
				   struct intel_ring_buffer *ring)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

1286
	if (INTEL_INFO(dev)->gen >= 6) {
1287
		error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
1288
		error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
1289 1290 1291 1292
		error->semaphore_mboxes[ring->id][0]
			= I915_READ(RING_SYNC_0(ring->mmio_base));
		error->semaphore_mboxes[ring->id][1]
			= I915_READ(RING_SYNC_1(ring->mmio_base));
1293 1294
		error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
		error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
1295
	}
1296

1297
	if (INTEL_INFO(dev)->gen >= 4) {
1298
		error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
1299 1300 1301
		error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
		error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
		error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
1302
		error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
1303
		if (ring->id == RCS)
1304 1305
			error->bbaddr = I915_READ64(BB_ADDR);
	} else {
1306
		error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
1307 1308 1309 1310 1311
		error->ipeir[ring->id] = I915_READ(IPEIR);
		error->ipehr[ring->id] = I915_READ(IPEHR);
		error->instdone[ring->id] = I915_READ(INSTDONE);
	}

B
Ben Widawsky 已提交
1312
	error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
1313
	error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
1314
	error->seqno[ring->id] = ring->get_seqno(ring, false);
1315
	error->acthd[ring->id] = intel_ring_get_active_head(ring);
1316 1317
	error->head[ring->id] = I915_READ_HEAD(ring);
	error->tail[ring->id] = I915_READ_TAIL(ring);
1318
	error->ctl[ring->id] = I915_READ_CTL(ring);
1319 1320 1321

	error->cpu_ring_head[ring->id] = ring->head;
	error->cpu_ring_tail[ring->id] = ring->tail;
1322 1323
}

1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343

static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
					   struct drm_i915_error_state *error,
					   struct drm_i915_error_ring *ering)
{
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
	struct drm_i915_gem_object *obj;

	/* Currently render ring is the only HW context user */
	if (ring->id != RCS || !error->ccid)
		return;

	list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
		if ((error->ccid & PAGE_MASK) == obj->gtt_offset) {
			ering->ctx = i915_error_object_create_sized(dev_priv,
								    obj, 1);
		}
	}
}

1344 1345 1346 1347
static void i915_gem_record_rings(struct drm_device *dev,
				  struct drm_i915_error_state *error)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
1348
	struct intel_ring_buffer *ring;
1349 1350 1351
	struct drm_i915_gem_request *request;
	int i, count;

1352
	for_each_ring(ring, dev_priv, i) {
1353 1354 1355 1356 1357 1358 1359 1360
		i915_record_ring_state(dev, error, ring);

		error->ring[i].batchbuffer =
			i915_error_first_batchbuffer(dev_priv, ring);

		error->ring[i].ringbuffer =
			i915_error_object_create(dev_priv, ring->obj);

1361 1362 1363

		i915_gem_record_active_context(ring, error, &error->ring[i]);

1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383
		count = 0;
		list_for_each_entry(request, &ring->request_list, list)
			count++;

		error->ring[i].num_requests = count;
		error->ring[i].requests =
			kmalloc(count*sizeof(struct drm_i915_error_request),
				GFP_ATOMIC);
		if (error->ring[i].requests == NULL) {
			error->ring[i].num_requests = 0;
			continue;
		}

		count = 0;
		list_for_each_entry(request, &ring->request_list, list) {
			struct drm_i915_error_request *erq;

			erq = &error->ring[i].requests[count++];
			erq->seqno = request->seqno;
			erq->jiffies = request->emitted_jiffies;
1384
			erq->tail = request->tail;
1385 1386 1387 1388
		}
	}
}

1389 1390 1391 1392 1393 1394 1395 1396 1397
/**
 * i915_capture_error_state - capture an error record for later analysis
 * @dev: drm device
 *
 * Should be called when an error is detected (either a hang or an error
 * interrupt) to capture error state from the time of the error.  Fills
 * out a structure which becomes available in debugfs for user level tools
 * to pick up.
 */
1398 1399 1400
static void i915_capture_error_state(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
1401
	struct drm_i915_gem_object *obj;
1402 1403
	struct drm_i915_error_state *error;
	unsigned long flags;
1404
	int i, pipe;
1405

1406 1407 1408
	spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
	error = dev_priv->gpu_error.first_error;
	spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1409 1410
	if (error)
		return;
1411

1412
	/* Account for pipe specific data like PIPE*STAT */
1413
	error = kzalloc(sizeof(*error), GFP_ATOMIC);
1414
	if (!error) {
1415 1416
		DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
		return;
1417 1418
	}

1419
	DRM_INFO("capturing error event; look for more information in "
1420
		 "/sys/kernel/debug/dri/%d/i915_error_state\n",
1421
		 dev->primary->index);
1422

1423
	kref_init(&error->ref);
1424 1425
	error->eir = I915_READ(EIR);
	error->pgtbl_er = I915_READ(PGTBL_ER);
1426 1427
	if (HAS_HW_CONTEXTS(dev))
		error->ccid = I915_READ(CCID);
1428 1429 1430 1431 1432 1433 1434 1435 1436 1437

	if (HAS_PCH_SPLIT(dev))
		error->ier = I915_READ(DEIER) | I915_READ(GTIER);
	else if (IS_VALLEYVIEW(dev))
		error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
	else if (IS_GEN2(dev))
		error->ier = I915_READ16(IER);
	else
		error->ier = I915_READ(IER);

1438 1439 1440 1441 1442 1443 1444 1445 1446 1447
	if (INTEL_INFO(dev)->gen >= 6)
		error->derrmr = I915_READ(DERRMR);

	if (IS_VALLEYVIEW(dev))
		error->forcewake = I915_READ(FORCEWAKE_VLV);
	else if (INTEL_INFO(dev)->gen >= 7)
		error->forcewake = I915_READ(FORCEWAKE_MT);
	else if (INTEL_INFO(dev)->gen == 6)
		error->forcewake = I915_READ(FORCEWAKE);

1448 1449 1450
	if (!HAS_PCH_SPLIT(dev))
		for_each_pipe(pipe)
			error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1451

1452
	if (INTEL_INFO(dev)->gen >= 6) {
1453
		error->error = I915_READ(ERROR_GEN6);
1454 1455
		error->done_reg = I915_READ(DONE_REG);
	}
1456

1457 1458 1459
	if (INTEL_INFO(dev)->gen == 7)
		error->err_int = I915_READ(GEN7_ERR_INT);

1460 1461
	i915_get_extra_instdone(dev, error->extra_instdone);

1462
	i915_gem_record_fences(dev, error);
1463
	i915_gem_record_rings(dev, error);
1464

1465
	/* Record buffers on the active and pinned lists. */
1466
	error->active_bo = NULL;
1467
	error->pinned_bo = NULL;
1468

1469 1470 1471 1472
	i = 0;
	list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
		i++;
	error->active_bo_count = i;
C
Chris Wilson 已提交
1473
	list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
1474 1475
		if (obj->pin_count)
			i++;
1476
	error->pinned_bo_count = i - error->active_bo_count;
1477

1478 1479
	error->active_bo = NULL;
	error->pinned_bo = NULL;
1480 1481
	if (i) {
		error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
1482
					   GFP_ATOMIC);
1483 1484 1485
		if (error->active_bo)
			error->pinned_bo =
				error->active_bo + error->active_bo_count;
1486 1487
	}

1488 1489
	if (error->active_bo)
		error->active_bo_count =
1490 1491 1492
			capture_active_bo(error->active_bo,
					  error->active_bo_count,
					  &dev_priv->mm.active_list);
1493 1494 1495

	if (error->pinned_bo)
		error->pinned_bo_count =
1496 1497
			capture_pinned_bo(error->pinned_bo,
					  error->pinned_bo_count,
C
Chris Wilson 已提交
1498
					  &dev_priv->mm.bound_list);
1499

1500 1501
	do_gettimeofday(&error->time);

1502
	error->overlay = intel_overlay_capture_error_state(dev);
1503
	error->display = intel_display_capture_error_state(dev);
1504

1505 1506 1507
	spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
	if (dev_priv->gpu_error.first_error == NULL) {
		dev_priv->gpu_error.first_error = error;
1508 1509
		error = NULL;
	}
1510
	spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1511 1512

	if (error)
1513
		i915_error_state_free(&error->ref);
1514 1515 1516 1517 1518 1519
}

void i915_destroy_error_state(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_error_state *error;
1520
	unsigned long flags;
1521

1522 1523 1524 1525
	spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
	error = dev_priv->gpu_error.first_error;
	dev_priv->gpu_error.first_error = NULL;
	spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1526 1527

	if (error)
1528
		kref_put(&error->ref, i915_error_state_free);
1529
}
1530 1531 1532
#else
#define i915_capture_error_state(x)
#endif
1533

1534
static void i915_report_and_clear_eir(struct drm_device *dev)
1535 1536
{
	struct drm_i915_private *dev_priv = dev->dev_private;
1537
	uint32_t instdone[I915_NUM_INSTDONE_REG];
1538
	u32 eir = I915_READ(EIR);
1539
	int pipe, i;
1540

1541 1542
	if (!eir)
		return;
1543

1544
	pr_err("render error detected, EIR: 0x%08x\n", eir);
1545

1546 1547
	i915_get_extra_instdone(dev, instdone);

1548 1549 1550 1551
	if (IS_G4X(dev)) {
		if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
			u32 ipeir = I915_READ(IPEIR_I965);

1552 1553
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1554 1555
			for (i = 0; i < ARRAY_SIZE(instdone); i++)
				pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1556 1557
			pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1558
			I915_WRITE(IPEIR_I965, ipeir);
1559
			POSTING_READ(IPEIR_I965);
1560 1561 1562
		}
		if (eir & GM45_ERROR_PAGE_TABLE) {
			u32 pgtbl_err = I915_READ(PGTBL_ER);
1563 1564
			pr_err("page table error\n");
			pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1565
			I915_WRITE(PGTBL_ER, pgtbl_err);
1566
			POSTING_READ(PGTBL_ER);
1567 1568 1569
		}
	}

1570
	if (!IS_GEN2(dev)) {
1571 1572
		if (eir & I915_ERROR_PAGE_TABLE) {
			u32 pgtbl_err = I915_READ(PGTBL_ER);
1573 1574
			pr_err("page table error\n");
			pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1575
			I915_WRITE(PGTBL_ER, pgtbl_err);
1576
			POSTING_READ(PGTBL_ER);
1577 1578 1579 1580
		}
	}

	if (eir & I915_ERROR_MEMORY_REFRESH) {
1581
		pr_err("memory refresh error:\n");
1582
		for_each_pipe(pipe)
1583
			pr_err("pipe %c stat: 0x%08x\n",
1584
			       pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1585 1586 1587
		/* pipestat has already been acked */
	}
	if (eir & I915_ERROR_INSTRUCTION) {
1588 1589
		pr_err("instruction error\n");
		pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
1590 1591
		for (i = 0; i < ARRAY_SIZE(instdone); i++)
			pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1592
		if (INTEL_INFO(dev)->gen < 4) {
1593 1594
			u32 ipeir = I915_READ(IPEIR);

1595 1596 1597
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
1598
			I915_WRITE(IPEIR, ipeir);
1599
			POSTING_READ(IPEIR);
1600 1601 1602
		} else {
			u32 ipeir = I915_READ(IPEIR_I965);

1603 1604 1605 1606
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
			pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1607
			I915_WRITE(IPEIR_I965, ipeir);
1608
			POSTING_READ(IPEIR_I965);
1609 1610 1611 1612
		}
	}

	I915_WRITE(EIR, eir);
1613
	POSTING_READ(EIR);
1614 1615 1616 1617 1618 1619 1620 1621 1622 1623
	eir = I915_READ(EIR);
	if (eir) {
		/*
		 * some errors might have become stuck,
		 * mask them.
		 */
		DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
		I915_WRITE(EMR, I915_READ(EMR) | eir);
		I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
	}
1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635
}

/**
 * i915_handle_error - handle an error interrupt
 * @dev: drm device
 *
 * Do some basic checking of regsiter state at error interrupt time and
 * dump it to the syslog.  Also call i915_capture_error_state() to make
 * sure we get a record and make it available in debugfs.  Fire a uevent
 * so userspace knows something bad happened (should trigger collection
 * of a ring dump etc.).
 */
1636
void i915_handle_error(struct drm_device *dev, bool wedged)
1637 1638
{
	struct drm_i915_private *dev_priv = dev->dev_private;
1639 1640
	struct intel_ring_buffer *ring;
	int i;
1641 1642 1643

	i915_capture_error_state(dev);
	i915_report_and_clear_eir(dev);
1644

1645
	if (wedged) {
1646 1647
		atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
				&dev_priv->gpu_error.reset_counter);
1648

1649
		/*
1650 1651
		 * Wakeup waiting processes so that the reset work item
		 * doesn't deadlock trying to grab various locks.
1652
		 */
1653 1654
		for_each_ring(ring, dev_priv, i)
			wake_up_all(&ring->irq_queue);
1655 1656
	}

1657
	queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
1658 1659
}

1660
static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1661 1662 1663 1664
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1665
	struct drm_i915_gem_object *obj;
1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676
	struct intel_unpin_work *work;
	unsigned long flags;
	bool stall_detected;

	/* Ignore early vblank irqs */
	if (intel_crtc == NULL)
		return;

	spin_lock_irqsave(&dev->event_lock, flags);
	work = intel_crtc->unpin_work;

1677 1678 1679
	if (work == NULL ||
	    atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
	    !work->enable_stall_check) {
1680 1681 1682 1683 1684 1685
		/* Either the pending flip IRQ arrived, or we're too early. Don't check */
		spin_unlock_irqrestore(&dev->event_lock, flags);
		return;
	}

	/* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1686
	obj = work->pending_flip_obj;
1687
	if (INTEL_INFO(dev)->gen >= 4) {
1688
		int dspsurf = DSPSURF(intel_crtc->plane);
1689 1690
		stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
					obj->gtt_offset;
1691
	} else {
1692
		int dspaddr = DSPADDR(intel_crtc->plane);
1693
		stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1694
							crtc->y * crtc->fb->pitches[0] +
1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705
							crtc->x * crtc->fb->bits_per_pixel/8);
	}

	spin_unlock_irqrestore(&dev->event_lock, flags);

	if (stall_detected) {
		DRM_DEBUG_DRIVER("Pageflip stall detected\n");
		intel_prepare_page_flip(dev, intel_crtc->plane);
	}
}

1706 1707 1708
/* Called from drm generic code, passed 'crtc' which
 * we use as a pipe index
 */
1709
static int i915_enable_vblank(struct drm_device *dev, int pipe)
1710 1711
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1712
	unsigned long irqflags;
1713

1714
	if (!i915_pipe_enabled(dev, pipe))
1715
		return -EINVAL;
1716

1717
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1718
	if (INTEL_INFO(dev)->gen >= 4)
1719 1720
		i915_enable_pipestat(dev_priv, pipe,
				     PIPE_START_VBLANK_INTERRUPT_ENABLE);
1721
	else
1722 1723
		i915_enable_pipestat(dev_priv, pipe,
				     PIPE_VBLANK_INTERRUPT_ENABLE);
1724 1725 1726

	/* maintain vblank delivery even in deep C-states */
	if (dev_priv->info->gen == 3)
1727
		I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1728
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1729

1730 1731 1732
	return 0;
}

1733
static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1734 1735 1736 1737 1738 1739 1740 1741 1742
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;

	if (!i915_pipe_enabled(dev, pipe))
		return -EINVAL;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
	ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1743
				    DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1744 1745 1746 1747 1748
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

	return 0;
}

1749
static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1750 1751 1752 1753 1754 1755 1756 1757
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;

	if (!i915_pipe_enabled(dev, pipe))
		return -EINVAL;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1758 1759
	ironlake_enable_display_irq(dev_priv,
				    DE_PIPEA_VBLANK_IVB << (5 * pipe));
1760 1761 1762 1763 1764
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

	return 0;
}

J
Jesse Barnes 已提交
1765 1766 1767 1768
static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;
1769
	u32 imr;
J
Jesse Barnes 已提交
1770 1771 1772 1773 1774 1775

	if (!i915_pipe_enabled(dev, pipe))
		return -EINVAL;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
	imr = I915_READ(VLV_IMR);
1776
	if (pipe == 0)
J
Jesse Barnes 已提交
1777
		imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1778
	else
J
Jesse Barnes 已提交
1779 1780
		imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
	I915_WRITE(VLV_IMR, imr);
1781 1782
	i915_enable_pipestat(dev_priv, pipe,
			     PIPE_START_VBLANK_INTERRUPT_ENABLE);
J
Jesse Barnes 已提交
1783 1784 1785 1786 1787
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

	return 0;
}

1788 1789 1790
/* Called from drm generic code, passed 'crtc' which
 * we use as a pipe index
 */
1791
static void i915_disable_vblank(struct drm_device *dev, int pipe)
1792 1793
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1794
	unsigned long irqflags;
1795

1796
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1797
	if (dev_priv->info->gen == 3)
1798
		I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
1799

1800 1801 1802 1803 1804 1805
	i915_disable_pipestat(dev_priv, pipe,
			      PIPE_VBLANK_INTERRUPT_ENABLE |
			      PIPE_START_VBLANK_INTERRUPT_ENABLE);
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

1806
static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1807 1808 1809 1810 1811 1812
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
	ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1813
				     DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1814
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1815 1816
}

1817
static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1818 1819 1820 1821 1822
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1823 1824
	ironlake_disable_display_irq(dev_priv,
				     DE_PIPEA_VBLANK_IVB << (pipe * 5));
1825 1826 1827
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

J
Jesse Barnes 已提交
1828 1829 1830 1831
static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;
1832
	u32 imr;
J
Jesse Barnes 已提交
1833 1834

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1835 1836
	i915_disable_pipestat(dev_priv, pipe,
			      PIPE_START_VBLANK_INTERRUPT_ENABLE);
J
Jesse Barnes 已提交
1837
	imr = I915_READ(VLV_IMR);
1838
	if (pipe == 0)
J
Jesse Barnes 已提交
1839
		imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1840
	else
J
Jesse Barnes 已提交
1841 1842 1843 1844 1845
		imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
	I915_WRITE(VLV_IMR, imr);
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

1846 1847
static u32
ring_last_seqno(struct intel_ring_buffer *ring)
1848
{
1849 1850 1851 1852 1853 1854 1855
	return list_entry(ring->request_list.prev,
			  struct drm_i915_gem_request, list)->seqno;
}

static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
{
	if (list_empty(&ring->request_list) ||
1856 1857
	    i915_seqno_passed(ring->get_seqno(ring, false),
			      ring_last_seqno(ring))) {
1858
		/* Issue a wake-up to catch stuck h/w. */
B
Ben Widawsky 已提交
1859 1860 1861
		if (waitqueue_active(&ring->irq_queue)) {
			DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
				  ring->name);
1862 1863 1864 1865 1866 1867
			wake_up_all(&ring->irq_queue);
			*err = true;
		}
		return true;
	}
	return false;
B
Ben Gamari 已提交
1868 1869
}

1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900
static bool semaphore_passed(struct intel_ring_buffer *ring)
{
	struct drm_i915_private *dev_priv = ring->dev->dev_private;
	u32 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
	struct intel_ring_buffer *signaller;
	u32 cmd, ipehr, acthd_min;

	ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
	if ((ipehr & ~(0x3 << 16)) !=
	    (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
		return false;

	/* ACTHD is likely pointing to the dword after the actual command,
	 * so scan backwards until we find the MBOX.
	 */
	acthd_min = max((int)acthd - 3 * 4, 0);
	do {
		cmd = ioread32(ring->virtual_start + acthd);
		if (cmd == ipehr)
			break;

		acthd -= 4;
		if (acthd < acthd_min)
			return false;
	} while (1);

	signaller = &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
	return i915_seqno_passed(signaller->get_seqno(signaller, false),
				 ioread32(ring->virtual_start+acthd+4)+1);
}

1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911
static bool kick_ring(struct intel_ring_buffer *ring)
{
	struct drm_device *dev = ring->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 tmp = I915_READ_CTL(ring);
	if (tmp & RING_WAIT) {
		DRM_ERROR("Kicking stuck wait on %s\n",
			  ring->name);
		I915_WRITE_CTL(ring, tmp);
		return true;
	}
1912 1913 1914 1915 1916 1917 1918 1919 1920

	if (INTEL_INFO(dev)->gen >= 6 &&
	    tmp & RING_WAIT_SEMAPHORE &&
	    semaphore_passed(ring)) {
		DRM_ERROR("Kicking stuck semaphore on %s\n",
			  ring->name);
		I915_WRITE_CTL(ring, tmp);
		return true;
	}
1921 1922 1923
	return false;
}

1924 1925 1926 1927
static bool i915_hangcheck_hung(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;

1928
	if (dev_priv->gpu_error.hangcheck_count++ > 1) {
1929 1930
		bool hung = true;

1931 1932 1933 1934
		DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
		i915_handle_error(dev, true);

		if (!IS_GEN2(dev)) {
1935 1936 1937
			struct intel_ring_buffer *ring;
			int i;

1938 1939 1940 1941 1942
			/* Is the chip hanging on a WAIT_FOR_EVENT?
			 * If so we can simply poke the RB_WAIT bit
			 * and break the hang. This should work on
			 * all but the second generation chipsets.
			 */
1943 1944
			for_each_ring(ring, dev_priv, i)
				hung &= !kick_ring(ring);
1945 1946
		}

1947
		return hung;
1948 1949 1950 1951 1952
	}

	return false;
}

B
Ben Gamari 已提交
1953 1954 1955 1956 1957 1958 1959 1960 1961 1962
/**
 * This is called when the chip hasn't reported back with completed
 * batchbuffers in a long time. The first time this is called we simply record
 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
 * again, we assume the chip is wedged and try to fix it.
 */
void i915_hangcheck_elapsed(unsigned long data)
{
	struct drm_device *dev = (struct drm_device *)data;
	drm_i915_private_t *dev_priv = dev->dev_private;
1963
	uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG];
1964 1965 1966
	struct intel_ring_buffer *ring;
	bool err = false, idle;
	int i;
1967

1968 1969 1970
	if (!i915_enable_hangcheck)
		return;

1971 1972 1973 1974 1975 1976 1977
	memset(acthd, 0, sizeof(acthd));
	idle = true;
	for_each_ring(ring, dev_priv, i) {
	    idle &= i915_hangcheck_ring_idle(ring, &err);
	    acthd[i] = intel_ring_get_active_head(ring);
	}

1978
	/* If all work is done then ACTHD clearly hasn't advanced. */
1979
	if (idle) {
1980 1981 1982 1983
		if (err) {
			if (i915_hangcheck_hung(dev))
				return;

1984
			goto repeat;
1985 1986
		}

1987
		dev_priv->gpu_error.hangcheck_count = 0;
1988 1989
		return;
	}
1990

1991
	i915_get_extra_instdone(dev, instdone);
1992 1993 1994 1995
	if (memcmp(dev_priv->gpu_error.last_acthd, acthd,
		   sizeof(acthd)) == 0 &&
	    memcmp(dev_priv->gpu_error.prev_instdone, instdone,
		   sizeof(instdone)) == 0) {
1996
		if (i915_hangcheck_hung(dev))
1997 1998
			return;
	} else {
1999
		dev_priv->gpu_error.hangcheck_count = 0;
2000

2001 2002 2003 2004
		memcpy(dev_priv->gpu_error.last_acthd, acthd,
		       sizeof(acthd));
		memcpy(dev_priv->gpu_error.prev_instdone, instdone,
		       sizeof(instdone));
2005
	}
B
Ben Gamari 已提交
2006

2007
repeat:
B
Ben Gamari 已提交
2008
	/* Reset timer case chip hangs without another request being added */
2009
	mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2010
		  round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
B
Ben Gamari 已提交
2011 2012
}

L
Linus Torvalds 已提交
2013 2014
/* drm_dma.h hooks
*/
2015
static void ironlake_irq_preinstall(struct drm_device *dev)
2016 2017 2018
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;

2019 2020
	atomic_set(&dev_priv->irq_received, 0);

2021
	I915_WRITE(HWSTAM, 0xeffe);
2022

2023 2024 2025 2026
	/* XXX hotplug from PCH */

	I915_WRITE(DEIMR, 0xffffffff);
	I915_WRITE(DEIER, 0x0);
2027
	POSTING_READ(DEIER);
2028 2029 2030 2031

	/* and GT */
	I915_WRITE(GTIMR, 0xffffffff);
	I915_WRITE(GTIER, 0x0);
2032
	POSTING_READ(GTIER);
2033

2034 2035 2036
	if (HAS_PCH_NOP(dev))
		return;

2037 2038
	/* south display irq */
	I915_WRITE(SDEIMR, 0xffffffff);
2039 2040 2041 2042 2043 2044 2045
	/*
	 * SDEIER is also touched by the interrupt handler to work around missed
	 * PCH interrupts. Hence we can't update it after the interrupt handler
	 * is enabled - instead we unconditionally enable all PCH interrupt
	 * sources here, but then only unmask them as needed with SDEIMR.
	 */
	I915_WRITE(SDEIER, 0xffffffff);
2046
	POSTING_READ(SDEIER);
2047 2048
}

J
Jesse Barnes 已提交
2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080
static void valleyview_irq_preinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;

	atomic_set(&dev_priv->irq_received, 0);

	/* VLV magic */
	I915_WRITE(VLV_IMR, 0);
	I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
	I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
	I915_WRITE(RING_IMR(BLT_RING_BASE), 0);

	/* and GT */
	I915_WRITE(GTIIR, I915_READ(GTIIR));
	I915_WRITE(GTIIR, I915_READ(GTIIR));
	I915_WRITE(GTIMR, 0xffffffff);
	I915_WRITE(GTIER, 0x0);
	POSTING_READ(GTIER);

	I915_WRITE(DPINVGTT, 0xff);

	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0xffff);
	I915_WRITE(VLV_IIR, 0xffffffff);
	I915_WRITE(VLV_IMR, 0xffffffff);
	I915_WRITE(VLV_IER, 0x0);
	POSTING_READ(VLV_IER);
}

2081
static void ibx_hpd_irq_setup(struct drm_device *dev)
2082 2083
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095
	struct drm_mode_config *mode_config = &dev->mode_config;
	struct intel_encoder *intel_encoder;
	u32 mask = ~I915_READ(SDEIMR);
	u32 hotplug;

	if (HAS_PCH_IBX(dev)) {
		list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
			mask |= hpd_ibx[intel_encoder->hpd_pin];
	} else {
		list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
			mask |= hpd_cpt[intel_encoder->hpd_pin];
	}
2096

2097 2098 2099 2100 2101 2102 2103 2104
	I915_WRITE(SDEIMR, ~mask);

	/*
	 * Enable digital hotplug on the PCH, and configure the DP short pulse
	 * duration to 2ms (which is the minimum in the Display Port spec)
	 *
	 * This register is the same on all known PCH chips.
	 */
2105 2106 2107 2108 2109 2110 2111 2112
	hotplug = I915_READ(PCH_PORT_HOTPLUG);
	hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
	hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
	hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
	hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
}

P
Paulo Zanoni 已提交
2113 2114 2115
static void ibx_irq_postinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2116
	u32 mask;
2117

2118 2119 2120 2121
	if (HAS_PCH_IBX(dev))
		mask = SDE_GMBUS | SDE_AUX_MASK;
	else
		mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
2122 2123 2124 2125

	if (HAS_PCH_NOP(dev))
		return;

P
Paulo Zanoni 已提交
2126 2127 2128 2129
	I915_WRITE(SDEIIR, I915_READ(SDEIIR));
	I915_WRITE(SDEIMR, ~mask);
}

2130
static int ironlake_irq_postinstall(struct drm_device *dev)
2131 2132 2133
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	/* enable kind of interrupts always enabled */
2134
	u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2135 2136
			   DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
			   DE_AUX_CHANNEL_A;
2137
	u32 render_irqs;
2138

2139
	dev_priv->irq_mask = ~display_mask;
2140 2141 2142

	/* should always can generate irq */
	I915_WRITE(DEIIR, I915_READ(DEIIR));
2143 2144
	I915_WRITE(DEIMR, dev_priv->irq_mask);
	I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
2145
	POSTING_READ(DEIER);
2146

2147
	dev_priv->gt_irq_mask = ~0;
2148 2149

	I915_WRITE(GTIIR, I915_READ(GTIIR));
2150
	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2151

2152 2153 2154
	if (IS_GEN6(dev))
		render_irqs =
			GT_USER_INTERRUPT |
B
Ben Widawsky 已提交
2155 2156
			GEN6_BSD_USER_INTERRUPT |
			GEN6_BLITTER_USER_INTERRUPT;
2157 2158
	else
		render_irqs =
2159
			GT_USER_INTERRUPT |
2160
			GT_PIPE_NOTIFY |
2161 2162
			GT_BSD_USER_INTERRUPT;
	I915_WRITE(GTIER, render_irqs);
2163
	POSTING_READ(GTIER);
2164

P
Paulo Zanoni 已提交
2165
	ibx_irq_postinstall(dev);
2166

2167 2168 2169 2170 2171 2172 2173
	if (IS_IRONLAKE_M(dev)) {
		/* Clear & enable PCU event interrupts */
		I915_WRITE(DEIIR, DE_PCU_EVENT);
		I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
		ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
	}

2174 2175 2176
	return 0;
}

2177
static int ivybridge_irq_postinstall(struct drm_device *dev)
2178 2179 2180
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	/* enable kind of interrupts always enabled */
2181 2182 2183 2184
	u32 display_mask =
		DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
		DE_PLANEC_FLIP_DONE_IVB |
		DE_PLANEB_FLIP_DONE_IVB |
2185 2186
		DE_PLANEA_FLIP_DONE_IVB |
		DE_AUX_CHANNEL_A_IVB;
2187 2188 2189 2190 2191 2192 2193
	u32 render_irqs;

	dev_priv->irq_mask = ~display_mask;

	/* should always can generate irq */
	I915_WRITE(DEIIR, I915_READ(DEIIR));
	I915_WRITE(DEIMR, dev_priv->irq_mask);
2194 2195 2196 2197 2198
	I915_WRITE(DEIER,
		   display_mask |
		   DE_PIPEC_VBLANK_IVB |
		   DE_PIPEB_VBLANK_IVB |
		   DE_PIPEA_VBLANK_IVB);
2199 2200
	POSTING_READ(DEIER);

2201
	dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
2202 2203 2204 2205

	I915_WRITE(GTIIR, I915_READ(GTIIR));
	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);

B
Ben Widawsky 已提交
2206
	render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2207
		GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
2208 2209 2210
	I915_WRITE(GTIER, render_irqs);
	POSTING_READ(GTIER);

P
Paulo Zanoni 已提交
2211
	ibx_irq_postinstall(dev);
2212

2213 2214 2215
	return 0;
}

J
Jesse Barnes 已提交
2216 2217 2218 2219
static int valleyview_irq_postinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u32 enable_mask;
2220
	u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
2221
	u32 render_irqs;
J
Jesse Barnes 已提交
2222 2223 2224
	u16 msid;

	enable_mask = I915_DISPLAY_PORT_INTERRUPT;
2225 2226 2227
	enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
J
Jesse Barnes 已提交
2228 2229
		I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;

2230 2231 2232 2233 2234 2235 2236
	/*
	 *Leave vblank interrupts masked initially.  enable/disable will
	 * toggle them based on usage.
	 */
	dev_priv->irq_mask = (~enable_mask) |
		I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
		I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
J
Jesse Barnes 已提交
2237 2238 2239 2240 2241 2242 2243 2244

	/* Hack for broken MSIs on VLV */
	pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
	pci_read_config_word(dev->pdev, 0x98, &msid);
	msid &= 0xff; /* mask out delivery bits */
	msid |= (1<<14);
	pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);

2245 2246 2247
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	POSTING_READ(PORT_HOTPLUG_EN);

J
Jesse Barnes 已提交
2248 2249 2250 2251 2252 2253 2254
	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
	I915_WRITE(VLV_IER, enable_mask);
	I915_WRITE(VLV_IIR, 0xffffffff);
	I915_WRITE(PIPESTAT(0), 0xffff);
	I915_WRITE(PIPESTAT(1), 0xffff);
	POSTING_READ(VLV_IER);

2255
	i915_enable_pipestat(dev_priv, 0, pipestat_enable);
2256
	i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
2257 2258
	i915_enable_pipestat(dev_priv, 1, pipestat_enable);

J
Jesse Barnes 已提交
2259 2260 2261 2262
	I915_WRITE(VLV_IIR, 0xffffffff);
	I915_WRITE(VLV_IIR, 0xffffffff);

	I915_WRITE(GTIIR, I915_READ(GTIIR));
2263
	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2264 2265 2266 2267

	render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
		GEN6_BLITTER_USER_INTERRUPT;
	I915_WRITE(GTIER, render_irqs);
J
Jesse Barnes 已提交
2268 2269 2270 2271 2272 2273 2274 2275 2276
	POSTING_READ(GTIER);

	/* ack & enable invalid PTE error interrupts */
#if 0 /* FIXME: add support to irq handler for checking these bits */
	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
	I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
#endif

	I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2277 2278 2279 2280

	return 0;
}

J
Jesse Barnes 已提交
2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302
static void valleyview_irq_uninstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;

	if (!dev_priv)
		return;

	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0xffff);

	I915_WRITE(HWSTAM, 0xffffffff);
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0xffff);
	I915_WRITE(VLV_IIR, 0xffffffff);
	I915_WRITE(VLV_IMR, 0xffffffff);
	I915_WRITE(VLV_IER, 0x0);
	POSTING_READ(VLV_IER);
}

2303
static void ironlake_irq_uninstall(struct drm_device *dev)
2304 2305
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2306 2307 2308 2309

	if (!dev_priv)
		return;

2310 2311 2312 2313 2314 2315 2316 2317 2318
	I915_WRITE(HWSTAM, 0xffffffff);

	I915_WRITE(DEIMR, 0xffffffff);
	I915_WRITE(DEIER, 0x0);
	I915_WRITE(DEIIR, I915_READ(DEIIR));

	I915_WRITE(GTIMR, 0xffffffff);
	I915_WRITE(GTIER, 0x0);
	I915_WRITE(GTIIR, I915_READ(GTIIR));
2319

2320 2321 2322
	if (HAS_PCH_NOP(dev))
		return;

2323 2324 2325
	I915_WRITE(SDEIMR, 0xffffffff);
	I915_WRITE(SDEIER, 0x0);
	I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2326 2327
}

2328
static void i8xx_irq_preinstall(struct drm_device * dev)
L
Linus Torvalds 已提交
2329 2330
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2331
	int pipe;
2332

2333
	atomic_set(&dev_priv->irq_received, 0);
2334

2335 2336
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0);
2337 2338 2339
	I915_WRITE16(IMR, 0xffff);
	I915_WRITE16(IER, 0x0);
	POSTING_READ16(IER);
C
Chris Wilson 已提交
2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367
}

static int i8xx_irq_postinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;

	I915_WRITE16(EMR,
		     ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));

	/* Unmask the interrupts that we always want on. */
	dev_priv->irq_mask =
		~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
		  I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
	I915_WRITE16(IMR, dev_priv->irq_mask);

	I915_WRITE16(IER,
		     I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		     I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		     I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
		     I915_USER_INTERRUPT);
	POSTING_READ16(IER);

	return 0;
}

2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398
/*
 * Returns true when a page flip has completed.
 */
static bool i8xx_handle_vblank(struct drm_device *dev,
			       int pipe, u16 iir)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);

	if (!drm_handle_vblank(dev, pipe))
		return false;

	if ((iir & flip_pending) == 0)
		return false;

	intel_prepare_page_flip(dev, pipe);

	/* We detect FlipDone by looking for the change in PendingFlip from '1'
	 * to '0' on the following vblank, i.e. IIR has the Pendingflip
	 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
	 * the flip is completed (no longer pending). Since this doesn't raise
	 * an interrupt per se, we watch for the change at vblank.
	 */
	if (I915_READ16(ISR) & flip_pending)
		return false;

	intel_finish_page_flip(dev, pipe);

	return true;
}

2399
static irqreturn_t i8xx_irq_handler(int irq, void *arg)
C
Chris Wilson 已提交
2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447
{
	struct drm_device *dev = (struct drm_device *) arg;
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u16 iir, new_iir;
	u32 pipe_stats[2];
	unsigned long irqflags;
	int irq_received;
	int pipe;
	u16 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;

	atomic_inc(&dev_priv->irq_received);

	iir = I915_READ16(IIR);
	if (iir == 0)
		return IRQ_NONE;

	while (iir & ~flip_mask) {
		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
			i915_handle_error(dev, false);

		for_each_pipe(pipe) {
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);

			/*
			 * Clear the PIPE*STAT regs before the IIR
			 */
			if (pipe_stats[pipe] & 0x8000ffff) {
				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
					DRM_DEBUG_DRIVER("pipe %c underrun\n",
							 pipe_name(pipe));
				I915_WRITE(reg, pipe_stats[pipe]);
				irq_received = 1;
			}
		}
		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

		I915_WRITE16(IIR, iir & ~flip_mask);
		new_iir = I915_READ16(IIR); /* Flush posted writes */

2448
		i915_update_dri1_breadcrumb(dev);
C
Chris Wilson 已提交
2449 2450 2451 2452 2453

		if (iir & I915_USER_INTERRUPT)
			notify_ring(dev, &dev_priv->ring[RCS]);

		if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2454 2455
		    i8xx_handle_vblank(dev, 0, iir))
			flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
C
Chris Wilson 已提交
2456 2457

		if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2458 2459
		    i8xx_handle_vblank(dev, 1, iir))
			flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
C
Chris Wilson 已提交
2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481

		iir = new_iir;
	}

	return IRQ_HANDLED;
}

static void i8xx_irq_uninstall(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;

	for_each_pipe(pipe) {
		/* Clear enable bits; then clear status bits */
		I915_WRITE(PIPESTAT(pipe), 0);
		I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
	}
	I915_WRITE16(IMR, 0xffff);
	I915_WRITE16(IER, 0x0);
	I915_WRITE16(IIR, I915_READ16(IIR));
}

2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493
static void i915_irq_preinstall(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;

	atomic_set(&dev_priv->irq_received, 0);

	if (I915_HAS_HOTPLUG(dev)) {
		I915_WRITE(PORT_HOTPLUG_EN, 0);
		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	}

2494
	I915_WRITE16(HWSTAM, 0xeffe);
2495 2496 2497 2498 2499 2500 2501 2502 2503 2504
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);
	POSTING_READ(IER);
}

static int i915_irq_postinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2505
	u32 enable_mask;
2506

2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524
	I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));

	/* Unmask the interrupts that we always want on. */
	dev_priv->irq_mask =
		~(I915_ASLE_INTERRUPT |
		  I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
		  I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);

	enable_mask =
		I915_ASLE_INTERRUPT |
		I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
		I915_USER_INTERRUPT;

2525
	if (I915_HAS_HOTPLUG(dev)) {
2526 2527 2528
		I915_WRITE(PORT_HOTPLUG_EN, 0);
		POSTING_READ(PORT_HOTPLUG_EN);

2529 2530 2531 2532 2533 2534 2535 2536 2537 2538
		/* Enable in IER... */
		enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
		/* and unmask in IMR */
		dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
	}

	I915_WRITE(IMR, dev_priv->irq_mask);
	I915_WRITE(IER, enable_mask);
	POSTING_READ(IER);

2539 2540 2541 2542 2543
	intel_opregion_enable_asle(dev);

	return 0;
}

2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574
/*
 * Returns true when a page flip has completed.
 */
static bool i915_handle_vblank(struct drm_device *dev,
			       int plane, int pipe, u32 iir)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);

	if (!drm_handle_vblank(dev, pipe))
		return false;

	if ((iir & flip_pending) == 0)
		return false;

	intel_prepare_page_flip(dev, plane);

	/* We detect FlipDone by looking for the change in PendingFlip from '1'
	 * to '0' on the following vblank, i.e. IIR has the Pendingflip
	 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
	 * the flip is completed (no longer pending). Since this doesn't raise
	 * an interrupt per se, we watch for the change at vblank.
	 */
	if (I915_READ(ISR) & flip_pending)
		return false;

	intel_finish_page_flip(dev, pipe);

	return true;
}

2575
static irqreturn_t i915_irq_handler(int irq, void *arg)
2576 2577 2578
{
	struct drm_device *dev = (struct drm_device *) arg;
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2579
	u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
2580
	unsigned long irqflags;
2581 2582 2583 2584
	u32 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
	int pipe, ret = IRQ_NONE;
2585 2586 2587 2588

	atomic_inc(&dev_priv->irq_received);

	iir = I915_READ(IIR);
2589 2590
	do {
		bool irq_received = (iir & ~flip_mask) != 0;
2591
		bool blc_event = false;
2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605

		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
			i915_handle_error(dev, false);

		for_each_pipe(pipe) {
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);

2606
			/* Clear the PIPE*STAT regs before the IIR */
2607 2608 2609 2610 2611
			if (pipe_stats[pipe] & 0x8000ffff) {
				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
					DRM_DEBUG_DRIVER("pipe %c underrun\n",
							 pipe_name(pipe));
				I915_WRITE(reg, pipe_stats[pipe]);
2612
				irq_received = true;
2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626
			}
		}
		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

		if (!irq_received)
			break;

		/* Consume port.  Then clear IIR or we'll miss events */
		if ((I915_HAS_HOTPLUG(dev)) &&
		    (iir & I915_DISPLAY_PORT_INTERRUPT)) {
			u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);

			DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
				  hotplug_status);
2627
			if (hotplug_status & HOTPLUG_INT_STATUS_I915)
2628 2629 2630 2631
				queue_work(dev_priv->wq,
					   &dev_priv->hotplug_work);

			I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2632
			POSTING_READ(PORT_HOTPLUG_STAT);
2633 2634
		}

2635
		I915_WRITE(IIR, iir & ~flip_mask);
2636 2637 2638 2639 2640 2641
		new_iir = I915_READ(IIR); /* Flush posted writes */

		if (iir & I915_USER_INTERRUPT)
			notify_ring(dev, &dev_priv->ring[RCS]);

		for_each_pipe(pipe) {
2642 2643 2644
			int plane = pipe;
			if (IS_MOBILE(dev))
				plane = !plane;
2645

2646
			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
2647 2648
			    i915_handle_vblank(dev, plane, pipe, iir))
				flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671

			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
				blc_event = true;
		}

		if (blc_event || (iir & I915_ASLE_INTERRUPT))
			intel_opregion_asle_intr(dev);

		/* With MSI, interrupts are only generated when iir
		 * transitions from zero to nonzero.  If another bit got
		 * set while we were handling the existing iir bits, then
		 * we would never get another interrupt.
		 *
		 * This is fine on non-MSI as well, as if we hit this path
		 * we avoid exiting the interrupt handler only to generate
		 * another one.
		 *
		 * Note that for MSI this could cause a stray interrupt report
		 * if an interrupt landed in the time between writing IIR and
		 * the posting read.  This should be rare enough to never
		 * trigger the 99% of 100,000 interrupts test for disabling
		 * stray interrupts.
		 */
2672
		ret = IRQ_HANDLED;
2673
		iir = new_iir;
2674
	} while (iir & ~flip_mask);
2675

2676
	i915_update_dri1_breadcrumb(dev);
2677

2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690
	return ret;
}

static void i915_irq_uninstall(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;

	if (I915_HAS_HOTPLUG(dev)) {
		I915_WRITE(PORT_HOTPLUG_EN, 0);
		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	}

2691
	I915_WRITE16(HWSTAM, 0xffff);
2692 2693
	for_each_pipe(pipe) {
		/* Clear enable bits; then clear status bits */
2694
		I915_WRITE(PIPESTAT(pipe), 0);
2695 2696
		I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
	}
2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);

	I915_WRITE(IIR, I915_READ(IIR));
}

static void i965_irq_preinstall(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;

	atomic_set(&dev_priv->irq_received, 0);

2710 2711
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723

	I915_WRITE(HWSTAM, 0xeffe);
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);
	POSTING_READ(IER);
}

static int i965_irq_postinstall(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2724
	u32 enable_mask;
2725 2726 2727
	u32 error_mask;

	/* Unmask the interrupts that we always want on. */
2728
	dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
2729
			       I915_DISPLAY_PORT_INTERRUPT |
2730 2731 2732 2733 2734 2735 2736
			       I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
			       I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
			       I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
			       I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
			       I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);

	enable_mask = ~dev_priv->irq_mask;
2737 2738
	enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
			 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
2739 2740 2741 2742
	enable_mask |= I915_USER_INTERRUPT;

	if (IS_G4X(dev))
		enable_mask |= I915_BSD_USER_INTERRUPT;
2743

2744
	i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764

	/*
	 * Enable some error detection, note the instruction error mask
	 * bit is reserved, so we leave it masked.
	 */
	if (IS_G4X(dev)) {
		error_mask = ~(GM45_ERROR_PAGE_TABLE |
			       GM45_ERROR_MEM_PRIV |
			       GM45_ERROR_CP_PRIV |
			       I915_ERROR_MEMORY_REFRESH);
	} else {
		error_mask = ~(I915_ERROR_PAGE_TABLE |
			       I915_ERROR_MEMORY_REFRESH);
	}
	I915_WRITE(EMR, error_mask);

	I915_WRITE(IMR, dev_priv->irq_mask);
	I915_WRITE(IER, enable_mask);
	POSTING_READ(IER);

2765 2766 2767 2768 2769 2770 2771 2772
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	POSTING_READ(PORT_HOTPLUG_EN);

	intel_opregion_enable_asle(dev);

	return 0;
}

2773
static void i915_hpd_irq_setup(struct drm_device *dev)
2774 2775
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2776 2777
	struct drm_mode_config *mode_config = &dev->mode_config;
	struct intel_encoder *encoder;
2778 2779
	u32 hotplug_en;

2780 2781 2782 2783
	if (I915_HAS_HOTPLUG(dev)) {
		hotplug_en = I915_READ(PORT_HOTPLUG_EN);
		hotplug_en &= ~HOTPLUG_INT_EN_MASK;
		/* Note HDMI and DP share hotplug bits */
2784
		/* enable bits are the same for all generations */
2785 2786 2787 2788 2789 2790 2791 2792
		list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
			hotplug_en |= hpd_mask_i915[encoder->hpd_pin];
		/* Programming the CRT detection parameters tends
		   to generate a spurious hotplug event about three
		   seconds later.  So just do it once.
		*/
		if (IS_G4X(dev))
			hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2793
		hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
2794
		hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2795

2796 2797 2798
		/* Ignore TV since it's buggy */
		I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
	}
2799 2800
}

2801
static irqreturn_t i965_irq_handler(int irq, void *arg)
2802 2803 2804 2805 2806 2807 2808 2809
{
	struct drm_device *dev = (struct drm_device *) arg;
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	u32 iir, new_iir;
	u32 pipe_stats[I915_MAX_PIPES];
	unsigned long irqflags;
	int irq_received;
	int ret = IRQ_NONE, pipe;
2810 2811 2812
	u32 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2813 2814 2815 2816 2817 2818

	atomic_inc(&dev_priv->irq_received);

	iir = I915_READ(IIR);

	for (;;) {
2819 2820
		bool blc_event = false;

2821
		irq_received = (iir & ~flip_mask) != 0;
2822 2823 2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854

		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
			i915_handle_error(dev, false);

		for_each_pipe(pipe) {
			int reg = PIPESTAT(pipe);
			pipe_stats[pipe] = I915_READ(reg);

			/*
			 * Clear the PIPE*STAT regs before the IIR
			 */
			if (pipe_stats[pipe] & 0x8000ffff) {
				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
					DRM_DEBUG_DRIVER("pipe %c underrun\n",
							 pipe_name(pipe));
				I915_WRITE(reg, pipe_stats[pipe]);
				irq_received = 1;
			}
		}
		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

		if (!irq_received)
			break;

		ret = IRQ_HANDLED;

		/* Consume port.  Then clear IIR or we'll miss events */
2855
		if (iir & I915_DISPLAY_PORT_INTERRUPT) {
2856 2857 2858 2859
			u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);

			DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
				  hotplug_status);
2860 2861 2862
			if (hotplug_status & (IS_G4X(dev) ?
					      HOTPLUG_INT_STATUS_G4X :
					      HOTPLUG_INT_STATUS_I965))
2863 2864 2865 2866 2867 2868 2869
				queue_work(dev_priv->wq,
					   &dev_priv->hotplug_work);

			I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
			I915_READ(PORT_HOTPLUG_STAT);
		}

2870
		I915_WRITE(IIR, iir & ~flip_mask);
2871 2872 2873 2874 2875 2876 2877 2878
		new_iir = I915_READ(IIR); /* Flush posted writes */

		if (iir & I915_USER_INTERRUPT)
			notify_ring(dev, &dev_priv->ring[RCS]);
		if (iir & I915_BSD_USER_INTERRUPT)
			notify_ring(dev, &dev_priv->ring[VCS]);

		for_each_pipe(pipe) {
2879
			if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
2880 2881
			    i915_handle_vblank(dev, pipe, pipe, iir))
				flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
2882 2883 2884 2885 2886 2887 2888 2889 2890

			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
				blc_event = true;
		}


		if (blc_event || (iir & I915_ASLE_INTERRUPT))
			intel_opregion_asle_intr(dev);

2891 2892 2893
		if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
			gmbus_irq_handler(dev);

2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911
		/* With MSI, interrupts are only generated when iir
		 * transitions from zero to nonzero.  If another bit got
		 * set while we were handling the existing iir bits, then
		 * we would never get another interrupt.
		 *
		 * This is fine on non-MSI as well, as if we hit this path
		 * we avoid exiting the interrupt handler only to generate
		 * another one.
		 *
		 * Note that for MSI this could cause a stray interrupt report
		 * if an interrupt landed in the time between writing IIR and
		 * the posting read.  This should be rare enough to never
		 * trigger the 99% of 100,000 interrupts test for disabling
		 * stray interrupts.
		 */
		iir = new_iir;
	}

2912
	i915_update_dri1_breadcrumb(dev);
2913

2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924
	return ret;
}

static void i965_irq_uninstall(struct drm_device * dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	int pipe;

	if (!dev_priv)
		return;

2925 2926
	I915_WRITE(PORT_HOTPLUG_EN, 0);
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2927 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939

	I915_WRITE(HWSTAM, 0xffffffff);
	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);

	for_each_pipe(pipe)
		I915_WRITE(PIPESTAT(pipe),
			   I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
	I915_WRITE(IIR, I915_READ(IIR));
}

2940 2941
void intel_irq_init(struct drm_device *dev)
{
2942 2943 2944
	struct drm_i915_private *dev_priv = dev->dev_private;

	INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2945
	INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
2946
	INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
2947
	INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
2948

2949 2950
	setup_timer(&dev_priv->gpu_error.hangcheck_timer,
		    i915_hangcheck_elapsed,
2951 2952
		    (unsigned long) dev);

2953
	pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
2954

2955 2956
	dev->driver->get_vblank_counter = i915_get_vblank_counter;
	dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2957
	if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
2958 2959 2960 2961
		dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
		dev->driver->get_vblank_counter = gm45_get_vblank_counter;
	}

2962 2963 2964 2965
	if (drm_core_check_feature(dev, DRIVER_MODESET))
		dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
	else
		dev->driver->get_vblank_timestamp = NULL;
2966 2967
	dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;

J
Jesse Barnes 已提交
2968 2969 2970 2971 2972 2973 2974
	if (IS_VALLEYVIEW(dev)) {
		dev->driver->irq_handler = valleyview_irq_handler;
		dev->driver->irq_preinstall = valleyview_irq_preinstall;
		dev->driver->irq_postinstall = valleyview_irq_postinstall;
		dev->driver->irq_uninstall = valleyview_irq_uninstall;
		dev->driver->enable_vblank = valleyview_enable_vblank;
		dev->driver->disable_vblank = valleyview_disable_vblank;
2975
		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
2976
	} else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2977 2978 2979 2980 2981 2982 2983
		/* Share pre & uninstall handlers with ILK/SNB */
		dev->driver->irq_handler = ivybridge_irq_handler;
		dev->driver->irq_preinstall = ironlake_irq_preinstall;
		dev->driver->irq_postinstall = ivybridge_irq_postinstall;
		dev->driver->irq_uninstall = ironlake_irq_uninstall;
		dev->driver->enable_vblank = ivybridge_enable_vblank;
		dev->driver->disable_vblank = ivybridge_disable_vblank;
2984
		dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
2985 2986 2987 2988 2989 2990 2991
	} else if (HAS_PCH_SPLIT(dev)) {
		dev->driver->irq_handler = ironlake_irq_handler;
		dev->driver->irq_preinstall = ironlake_irq_preinstall;
		dev->driver->irq_postinstall = ironlake_irq_postinstall;
		dev->driver->irq_uninstall = ironlake_irq_uninstall;
		dev->driver->enable_vblank = ironlake_enable_vblank;
		dev->driver->disable_vblank = ironlake_disable_vblank;
2992
		dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
2993
	} else {
C
Chris Wilson 已提交
2994 2995 2996 2997 2998
		if (INTEL_INFO(dev)->gen == 2) {
			dev->driver->irq_preinstall = i8xx_irq_preinstall;
			dev->driver->irq_postinstall = i8xx_irq_postinstall;
			dev->driver->irq_handler = i8xx_irq_handler;
			dev->driver->irq_uninstall = i8xx_irq_uninstall;
2999 3000 3001 3002 3003
		} else if (INTEL_INFO(dev)->gen == 3) {
			dev->driver->irq_preinstall = i915_irq_preinstall;
			dev->driver->irq_postinstall = i915_irq_postinstall;
			dev->driver->irq_uninstall = i915_irq_uninstall;
			dev->driver->irq_handler = i915_irq_handler;
3004
			dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
C
Chris Wilson 已提交
3005
		} else {
3006 3007 3008 3009
			dev->driver->irq_preinstall = i965_irq_preinstall;
			dev->driver->irq_postinstall = i965_irq_postinstall;
			dev->driver->irq_uninstall = i965_irq_uninstall;
			dev->driver->irq_handler = i965_irq_handler;
3010
			dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
C
Chris Wilson 已提交
3011
		}
3012 3013 3014 3015
		dev->driver->enable_vblank = i915_enable_vblank;
		dev->driver->disable_vblank = i915_disable_vblank;
	}
}
3016 3017 3018 3019 3020 3021 3022 3023

void intel_hpd_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (dev_priv->display.hpd_irq_setup)
		dev_priv->display.hpd_irq_setup(dev);
}