i915_irq.c 130.3 KB
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/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
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 */
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/*
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

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#include <linux/sysrq.h>
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#include <linux/slab.h>
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#include <linux/circ_buf.h>
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#include <drm/drmP.h>
#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#include "i915_trace.h"
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#include "intel_drv.h"
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/**
 * DOC: interrupt handling
 *
 * These functions provide the basic support for enabling and disabling the
 * interrupt handling support. There's a lot more functionality in i915_irq.c
 * and related files, but that will be described in separate chapters.
 */

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static const u32 hpd_ilk[HPD_NUM_PINS] = {
	[HPD_PORT_A] = DE_DP_A_HOTPLUG,
};

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static const u32 hpd_ivb[HPD_NUM_PINS] = {
	[HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
};

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static const u32 hpd_bdw[HPD_NUM_PINS] = {
	[HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
};

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static const u32 hpd_ibx[HPD_NUM_PINS] = {
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	[HPD_CRT] = SDE_CRT_HOTPLUG,
	[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
	[HPD_PORT_B] = SDE_PORTB_HOTPLUG,
	[HPD_PORT_C] = SDE_PORTC_HOTPLUG,
	[HPD_PORT_D] = SDE_PORTD_HOTPLUG
};

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static const u32 hpd_cpt[HPD_NUM_PINS] = {
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	[HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
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	[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
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	[HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
	[HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
	[HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
};

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static const u32 hpd_spt[HPD_NUM_PINS] = {
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	[HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
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	[HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
	[HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
	[HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
	[HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
};

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static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
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	[HPD_CRT] = CRT_HOTPLUG_INT_EN,
	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
	[HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
	[HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
	[HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
};

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static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
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	[HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
	[HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
	[HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
	[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
};

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static const u32 hpd_status_i915[HPD_NUM_PINS] = {
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	[HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
	[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
	[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
	[HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
	[HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
	[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
};

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/* BXT hpd list */
static const u32 hpd_bxt[HPD_NUM_PINS] = {
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	[HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
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	[HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
	[HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
};

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/* IIR can theoretically queue up two events. Be paranoid. */
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#define GEN8_IRQ_RESET_NDX(type, which) do { \
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	I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
	POSTING_READ(GEN8_##type##_IMR(which)); \
	I915_WRITE(GEN8_##type##_IER(which), 0); \
	I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
	POSTING_READ(GEN8_##type##_IIR(which)); \
	I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
	POSTING_READ(GEN8_##type##_IIR(which)); \
} while (0)

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#define GEN5_IRQ_RESET(type) do { \
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	I915_WRITE(type##IMR, 0xffffffff); \
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	POSTING_READ(type##IMR); \
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	I915_WRITE(type##IER, 0); \
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	I915_WRITE(type##IIR, 0xffffffff); \
	POSTING_READ(type##IIR); \
	I915_WRITE(type##IIR, 0xffffffff); \
	POSTING_READ(type##IIR); \
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} while (0)

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/*
 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
 */
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static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv,
				    i915_reg_t reg)
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{
	u32 val = I915_READ(reg);

	if (val == 0)
		return;

	WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
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	     i915_mmio_reg_offset(reg), val);
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	I915_WRITE(reg, 0xffffffff);
	POSTING_READ(reg);
	I915_WRITE(reg, 0xffffffff);
	POSTING_READ(reg);
}
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#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
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	gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
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	I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
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	I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
	POSTING_READ(GEN8_##type##_IMR(which)); \
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} while (0)

#define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
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	gen5_assert_iir_is_zero(dev_priv, type##IIR); \
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	I915_WRITE(type##IER, (ier_val)); \
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	I915_WRITE(type##IMR, (imr_val)); \
	POSTING_READ(type##IMR); \
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} while (0)

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static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);

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/* For display hotplug interrupt */
static inline void
i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
				     uint32_t mask,
				     uint32_t bits)
{
	uint32_t val;

	assert_spin_locked(&dev_priv->irq_lock);
	WARN_ON(bits & ~mask);

	val = I915_READ(PORT_HOTPLUG_EN);
	val &= ~mask;
	val |= bits;
	I915_WRITE(PORT_HOTPLUG_EN, val);
}

/**
 * i915_hotplug_interrupt_update - update hotplug interrupt enable
 * @dev_priv: driver private
 * @mask: bits to update
 * @bits: bits to enable
 * NOTE: the HPD enable bits are modified both inside and outside
 * of an interrupt context. To avoid that read-modify-write cycles
 * interfer, these bits are protected by a spinlock. Since this
 * function is usually not called from a context where the lock is
 * held already, this function acquires the lock itself. A non-locking
 * version is also available.
 */
void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
				   uint32_t mask,
				   uint32_t bits)
{
	spin_lock_irq(&dev_priv->irq_lock);
	i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
	spin_unlock_irq(&dev_priv->irq_lock);
}

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/**
 * ilk_update_display_irq - update DEIMR
 * @dev_priv: driver private
 * @interrupt_mask: mask of interrupt bits to update
 * @enabled_irq_mask: mask of interrupt bits to enable
 */
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void ilk_update_display_irq(struct drm_i915_private *dev_priv,
			    uint32_t interrupt_mask,
			    uint32_t enabled_irq_mask)
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{
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	uint32_t new_val;

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	assert_spin_locked(&dev_priv->irq_lock);

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	WARN_ON(enabled_irq_mask & ~interrupt_mask);

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	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
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		return;

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	new_val = dev_priv->irq_mask;
	new_val &= ~interrupt_mask;
	new_val |= (~enabled_irq_mask & interrupt_mask);

	if (new_val != dev_priv->irq_mask) {
		dev_priv->irq_mask = new_val;
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		I915_WRITE(DEIMR, dev_priv->irq_mask);
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		POSTING_READ(DEIMR);
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	}
}

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/**
 * ilk_update_gt_irq - update GTIMR
 * @dev_priv: driver private
 * @interrupt_mask: mask of interrupt bits to update
 * @enabled_irq_mask: mask of interrupt bits to enable
 */
static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
			      uint32_t interrupt_mask,
			      uint32_t enabled_irq_mask)
{
	assert_spin_locked(&dev_priv->irq_lock);

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	WARN_ON(enabled_irq_mask & ~interrupt_mask);

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	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
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		return;

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	dev_priv->gt_irq_mask &= ~interrupt_mask;
	dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
}

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void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
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{
	ilk_update_gt_irq(dev_priv, mask, mask);
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	POSTING_READ_FW(GTIMR);
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}

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void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
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{
	ilk_update_gt_irq(dev_priv, mask, 0);
}

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static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
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{
	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
}

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static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
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{
	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
}

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static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
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{
	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
}

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/**
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 * snb_update_pm_irq - update GEN6_PMIMR
 * @dev_priv: driver private
 * @interrupt_mask: mask of interrupt bits to update
 * @enabled_irq_mask: mask of interrupt bits to enable
 */
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static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
			      uint32_t interrupt_mask,
			      uint32_t enabled_irq_mask)
{
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	uint32_t new_val;
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	WARN_ON(enabled_irq_mask & ~interrupt_mask);

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	assert_spin_locked(&dev_priv->irq_lock);

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	new_val = dev_priv->pm_irq_mask;
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	new_val &= ~interrupt_mask;
	new_val |= (~enabled_irq_mask & interrupt_mask);

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	if (new_val != dev_priv->pm_irq_mask) {
		dev_priv->pm_irq_mask = new_val;
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		I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
		POSTING_READ(gen6_pm_imr(dev_priv));
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	}
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}

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void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
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{
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	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
		return;

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	snb_update_pm_irq(dev_priv, mask, mask);
}

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static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
				  uint32_t mask)
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{
	snb_update_pm_irq(dev_priv, mask, 0);
}

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void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
{
	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
		return;

	__gen6_disable_pm_irq(dev_priv, mask);
}

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void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
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{
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	i915_reg_t reg = gen6_pm_iir(dev_priv);
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	spin_lock_irq(&dev_priv->irq_lock);
	I915_WRITE(reg, dev_priv->pm_rps_events);
	I915_WRITE(reg, dev_priv->pm_rps_events);
	POSTING_READ(reg);
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	dev_priv->rps.pm_iir = 0;
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	spin_unlock_irq(&dev_priv->irq_lock);
}

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void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
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{
	spin_lock_irq(&dev_priv->irq_lock);
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	WARN_ON_ONCE(dev_priv->rps.pm_iir);
	WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
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	dev_priv->rps.interrupts_enabled = true;
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	I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
				dev_priv->pm_rps_events);
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	gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
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	spin_unlock_irq(&dev_priv->irq_lock);
}

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u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
{
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	return (mask & ~dev_priv->rps.pm_intr_keep);
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}

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void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
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{
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	spin_lock_irq(&dev_priv->irq_lock);
	dev_priv->rps.interrupts_enabled = false;
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	I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0));
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	__gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
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	I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
				~dev_priv->pm_rps_events);
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	spin_unlock_irq(&dev_priv->irq_lock);
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	synchronize_irq(dev_priv->dev->irq);
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	/* Now that we will not be generating any more work, flush any
	 * outsanding tasks. As we are called on the RPS idle path,
	 * we will reset the GPU to minimum frequencies, so the current
	 * state of the worker can be discarded.
	 */
	cancel_work_sync(&dev_priv->rps.work);
	gen6_reset_rps_interrupts(dev_priv);
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}

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/**
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 * bdw_update_port_irq - update DE port interrupt
 * @dev_priv: driver private
 * @interrupt_mask: mask of interrupt bits to update
 * @enabled_irq_mask: mask of interrupt bits to enable
 */
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static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
				uint32_t interrupt_mask,
				uint32_t enabled_irq_mask)
{
	uint32_t new_val;
	uint32_t old_val;

	assert_spin_locked(&dev_priv->irq_lock);

	WARN_ON(enabled_irq_mask & ~interrupt_mask);

	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
		return;

	old_val = I915_READ(GEN8_DE_PORT_IMR);

	new_val = old_val;
	new_val &= ~interrupt_mask;
	new_val |= (~enabled_irq_mask & interrupt_mask);

	if (new_val != old_val) {
		I915_WRITE(GEN8_DE_PORT_IMR, new_val);
		POSTING_READ(GEN8_DE_PORT_IMR);
	}
}

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/**
 * bdw_update_pipe_irq - update DE pipe interrupt
 * @dev_priv: driver private
 * @pipe: pipe whose interrupt to update
 * @interrupt_mask: mask of interrupt bits to update
 * @enabled_irq_mask: mask of interrupt bits to enable
 */
void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
			 enum pipe pipe,
			 uint32_t interrupt_mask,
			 uint32_t enabled_irq_mask)
{
	uint32_t new_val;

	assert_spin_locked(&dev_priv->irq_lock);

	WARN_ON(enabled_irq_mask & ~interrupt_mask);

	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
		return;

	new_val = dev_priv->de_irq_mask[pipe];
	new_val &= ~interrupt_mask;
	new_val |= (~enabled_irq_mask & interrupt_mask);

	if (new_val != dev_priv->de_irq_mask[pipe]) {
		dev_priv->de_irq_mask[pipe] = new_val;
		I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
		POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
	}
}

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/**
 * ibx_display_interrupt_update - update SDEIMR
 * @dev_priv: driver private
 * @interrupt_mask: mask of interrupt bits to update
 * @enabled_irq_mask: mask of interrupt bits to enable
 */
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void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
				  uint32_t interrupt_mask,
				  uint32_t enabled_irq_mask)
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{
	uint32_t sdeimr = I915_READ(SDEIMR);
	sdeimr &= ~interrupt_mask;
	sdeimr |= (~enabled_irq_mask & interrupt_mask);

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	WARN_ON(enabled_irq_mask & ~interrupt_mask);

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	assert_spin_locked(&dev_priv->irq_lock);

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	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
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		return;

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	I915_WRITE(SDEIMR, sdeimr);
	POSTING_READ(SDEIMR);
}
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static void
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__i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		       u32 enable_mask, u32 status_mask)
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{
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	i915_reg_t reg = PIPESTAT(pipe);
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	u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
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	assert_spin_locked(&dev_priv->irq_lock);
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	WARN_ON(!intel_irqs_enabled(dev_priv));
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	if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
		      status_mask & ~PIPESTAT_INT_STATUS_MASK,
		      "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
		      pipe_name(pipe), enable_mask, status_mask))
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		return;

	if ((pipestat & enable_mask) == enable_mask)
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		return;

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	dev_priv->pipestat_irq_mask[pipe] |= status_mask;

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	/* Enable the interrupt, clear any pending status */
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	pipestat |= enable_mask | status_mask;
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	I915_WRITE(reg, pipestat);
	POSTING_READ(reg);
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}

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static void
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__i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		        u32 enable_mask, u32 status_mask)
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{
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	i915_reg_t reg = PIPESTAT(pipe);
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	u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
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	assert_spin_locked(&dev_priv->irq_lock);
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	WARN_ON(!intel_irqs_enabled(dev_priv));
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	if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
		      status_mask & ~PIPESTAT_INT_STATUS_MASK,
		      "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
		      pipe_name(pipe), enable_mask, status_mask))
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		return;

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	if ((pipestat & enable_mask) == 0)
		return;

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	dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;

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	pipestat &= ~enable_mask;
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	I915_WRITE(reg, pipestat);
	POSTING_READ(reg);
532 533
}

534 535 536 537 538
static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
{
	u32 enable_mask = status_mask << 16;

	/*
539 540
	 * On pipe A we don't support the PSR interrupt yet,
	 * on pipe B and C the same bit MBZ.
541 542 543
	 */
	if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
		return 0;
544 545 546 547 548 549
	/*
	 * On pipe B and C we don't support the PSR interrupt yet, on pipe
	 * A the same bit is for perf counters which we don't use either.
	 */
	if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
		return 0;
550 551 552 553 554 555 556 557 558 559 560 561

	enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
			 SPRITE0_FLIP_DONE_INT_EN_VLV |
			 SPRITE1_FLIP_DONE_INT_EN_VLV);
	if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
		enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
	if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
		enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;

	return enable_mask;
}

562 563 564 565 566 567
void
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		     u32 status_mask)
{
	u32 enable_mask;

568
	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
569 570 571 572
		enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
							   status_mask);
	else
		enable_mask = status_mask << 16;
573 574 575 576 577 578 579 580 581
	__i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
}

void
i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
		      u32 status_mask)
{
	u32 enable_mask;

582
	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
583 584 585 586
		enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
							   status_mask);
	else
		enable_mask = status_mask << 16;
587 588 589
	__i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
}

590
/**
591
 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
592
 * @dev_priv: i915 device private
593
 */
594
static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
595
{
596
	if (!dev_priv->opregion.asle || !IS_MOBILE(dev_priv))
597 598
		return;

599
	spin_lock_irq(&dev_priv->irq_lock);
600

601
	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
602
	if (INTEL_GEN(dev_priv) >= 4)
603
		i915_enable_pipestat(dev_priv, PIPE_A,
604
				     PIPE_LEGACY_BLC_EVENT_STATUS);
605

606
	spin_unlock_irq(&dev_priv->irq_lock);
607 608
}

609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658
/*
 * This timing diagram depicts the video signal in and
 * around the vertical blanking period.
 *
 * Assumptions about the fictitious mode used in this example:
 *  vblank_start >= 3
 *  vsync_start = vblank_start + 1
 *  vsync_end = vblank_start + 2
 *  vtotal = vblank_start + 3
 *
 *           start of vblank:
 *           latch double buffered registers
 *           increment frame counter (ctg+)
 *           generate start of vblank interrupt (gen4+)
 *           |
 *           |          frame start:
 *           |          generate frame start interrupt (aka. vblank interrupt) (gmch)
 *           |          may be shifted forward 1-3 extra lines via PIPECONF
 *           |          |
 *           |          |  start of vsync:
 *           |          |  generate vsync interrupt
 *           |          |  |
 * ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx
 *       .   \hs/   .      \hs/          \hs/          \hs/   .      \hs/
 * ----va---> <-----------------vb--------------------> <--------va-------------
 *       |          |       <----vs----->                     |
 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
 *       |          |                                         |
 *       last visible pixel                                   first visible pixel
 *                  |                                         increment frame counter (gen3/4)
 *                  pixel counter = vblank_start * htotal     pixel counter = 0 (gen3/4)
 *
 * x  = horizontal active
 * _  = horizontal blanking
 * hs = horizontal sync
 * va = vertical active
 * vb = vertical blanking
 * vs = vertical sync
 * vbs = vblank_start (number)
 *
 * Summary:
 * - most events happen at the start of horizontal sync
 * - frame start happens at the start of horizontal blank, 1-4 lines
 *   (depending on PIPECONF settings) after the start of vblank
 * - gen3/4 pixel and frame counter are synchronized with the start
 *   of horizontal active on the first line of vertical active
 */

659
static u32 i8xx_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
660 661 662 663 664
{
	/* Gen2 doesn't have a hardware frame counter */
	return 0;
}

665 666 667
/* Called from drm generic code, passed a 'crtc', which
 * we use as a pipe index
 */
668
static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
669
{
670
	struct drm_i915_private *dev_priv = dev->dev_private;
671
	i915_reg_t high_frame, low_frame;
672
	u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
673 674
	struct intel_crtc *intel_crtc =
		to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
675
	const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
676

677 678 679 680 681
	htotal = mode->crtc_htotal;
	hsync_start = mode->crtc_hsync_start;
	vbl_start = mode->crtc_vblank_start;
	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
		vbl_start = DIV_ROUND_UP(vbl_start, 2);
682

683 684 685 686 687 688
	/* Convert to pixel count */
	vbl_start *= htotal;

	/* Start of vblank event occurs at start of hsync */
	vbl_start -= htotal - hsync_start;

689 690
	high_frame = PIPEFRAME(pipe);
	low_frame = PIPEFRAMEPIXEL(pipe);
691

692 693 694 695 696 697
	/*
	 * High & low register fields aren't synchronized, so make sure
	 * we get a low value that's stable across two reads of the high
	 * register.
	 */
	do {
698
		high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
699
		low   = I915_READ(low_frame);
700
		high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
701 702
	} while (high1 != high2);

703
	high1 >>= PIPE_FRAME_HIGH_SHIFT;
704
	pixel = low & PIPE_PIXEL_MASK;
705
	low >>= PIPE_FRAME_LOW_SHIFT;
706 707 708 709 710 711

	/*
	 * The frame counter increments at beginning of active.
	 * Cook up a vblank counter by also checking the pixel
	 * counter against vblank start.
	 */
712
	return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
713 714
}

715
static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
716
{
717
	struct drm_i915_private *dev_priv = dev->dev_private;
718

719
	return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
720 721
}

722
/* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
723 724 725 726
static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
727
	const struct drm_display_mode *mode = &crtc->base.hwmode;
728
	enum pipe pipe = crtc->pipe;
729
	int position, vtotal;
730

731
	vtotal = mode->crtc_vtotal;
732 733 734
	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
		vtotal /= 2;

735
	if (IS_GEN2(dev_priv))
736
		position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
737
	else
738
		position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
739

740 741 742 743 744 745 746 747 748 749 750 751
	/*
	 * On HSW, the DSL reg (0x70000) appears to return 0 if we
	 * read it just before the start of vblank.  So try it again
	 * so we don't accidentally end up spanning a vblank frame
	 * increment, causing the pipe_update_end() code to squak at us.
	 *
	 * The nature of this problem means we can't simply check the ISR
	 * bit and return the vblank start value; nor can we use the scanline
	 * debug register in the transcoder as it appears to have the same
	 * problem.  We may need to extend this to include other platforms,
	 * but so far testing only shows the problem on HSW.
	 */
752
	if (HAS_DDI(dev_priv) && !position) {
753 754 755 756 757 758 759 760 761 762 763 764 765
		int i, temp;

		for (i = 0; i < 100; i++) {
			udelay(1);
			temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) &
				DSL_LINEMASK_GEN3;
			if (temp != position) {
				position = temp;
				break;
			}
		}
	}

766
	/*
767 768
	 * See update_scanline_offset() for the details on the
	 * scanline_offset adjustment.
769
	 */
770
	return (position + crtc->scanline_offset) % vtotal;
771 772
}

773
static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
774
				    unsigned int flags, int *vpos, int *hpos,
775 776
				    ktime_t *stime, ktime_t *etime,
				    const struct drm_display_mode *mode)
777
{
778 779 780
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
781
	int position;
782
	int vbl_start, vbl_end, hsync_start, htotal, vtotal;
783 784
	bool in_vbl = true;
	int ret = 0;
785
	unsigned long irqflags;
786

787
	if (WARN_ON(!mode->crtc_clock)) {
788
		DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
789
				 "pipe %c\n", pipe_name(pipe));
790 791 792
		return 0;
	}

793
	htotal = mode->crtc_htotal;
794
	hsync_start = mode->crtc_hsync_start;
795 796 797
	vtotal = mode->crtc_vtotal;
	vbl_start = mode->crtc_vblank_start;
	vbl_end = mode->crtc_vblank_end;
798

799 800 801 802 803 804
	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
		vbl_start = DIV_ROUND_UP(vbl_start, 2);
		vbl_end /= 2;
		vtotal /= 2;
	}

805 806
	ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;

807 808 809 810 811 812
	/*
	 * Lock uncore.lock, as we will do multiple timing critical raw
	 * register reads, potentially with preemption disabled, so the
	 * following code must not block on uncore.lock.
	 */
	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
813

814 815 816 817 818 819
	/* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */

	/* Get optional system timestamp before query. */
	if (stime)
		*stime = ktime_get();

820
	if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
821 822 823
		/* No obvious pixelcount register. Only query vertical
		 * scanout position from Display scan line register.
		 */
824
		position = __intel_get_crtc_scanline(intel_crtc);
825 826 827 828 829
	} else {
		/* Have access to pixelcount since start of frame.
		 * We can split this into vertical and horizontal
		 * scanout position.
		 */
830
		position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
831

832 833 834 835
		/* convert to pixel counts */
		vbl_start *= htotal;
		vbl_end *= htotal;
		vtotal *= htotal;
836

837 838 839 840 841 842 843 844 845 846 847 848
		/*
		 * In interlaced modes, the pixel counter counts all pixels,
		 * so one field will have htotal more pixels. In order to avoid
		 * the reported position from jumping backwards when the pixel
		 * counter is beyond the length of the shorter field, just
		 * clamp the position the length of the shorter field. This
		 * matches how the scanline counter based position works since
		 * the scanline counter doesn't count the two half lines.
		 */
		if (position >= vtotal)
			position = vtotal - 1;

849 850 851 852 853 854 855 856 857 858
		/*
		 * Start of vblank interrupt is triggered at start of hsync,
		 * just prior to the first active line of vblank. However we
		 * consider lines to start at the leading edge of horizontal
		 * active. So, should we get here before we've crossed into
		 * the horizontal active of the first line in vblank, we would
		 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
		 * always add htotal-hsync_start to the current pixel position.
		 */
		position = (position + htotal - hsync_start) % vtotal;
859 860
	}

861 862 863 864 865 866 867 868
	/* Get optional system timestamp after query. */
	if (etime)
		*etime = ktime_get();

	/* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */

	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

869 870 871 872 873 874 875 876 877 878 879 880
	in_vbl = position >= vbl_start && position < vbl_end;

	/*
	 * While in vblank, position will be negative
	 * counting up towards 0 at vbl_end. And outside
	 * vblank, position will be positive counting
	 * up since vbl_end.
	 */
	if (position >= vbl_start)
		position -= vbl_end;
	else
		position += vtotal - vbl_end;
881

882
	if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
883 884 885 886 887 888
		*vpos = position;
		*hpos = 0;
	} else {
		*vpos = position / htotal;
		*hpos = position - (*vpos * htotal);
	}
889 890 891

	/* In vblank? */
	if (in_vbl)
892
		ret |= DRM_SCANOUTPOS_IN_VBLANK;
893 894 895 896

	return ret;
}

897 898 899 900 901 902 903 904 905 906 907 908 909
int intel_get_crtc_scanline(struct intel_crtc *crtc)
{
	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
	unsigned long irqflags;
	int position;

	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
	position = __intel_get_crtc_scanline(crtc);
	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);

	return position;
}

910
static int i915_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe,
911 912 913 914
			      int *max_error,
			      struct timeval *vblank_time,
			      unsigned flags)
{
915
	struct drm_crtc *crtc;
916

917 918
	if (pipe >= INTEL_INFO(dev)->num_pipes) {
		DRM_ERROR("Invalid crtc %u\n", pipe);
919 920 921 922
		return -EINVAL;
	}

	/* Get drm_crtc to timestamp: */
923 924
	crtc = intel_get_crtc_for_pipe(dev, pipe);
	if (crtc == NULL) {
925
		DRM_ERROR("Invalid crtc %u\n", pipe);
926 927 928
		return -EINVAL;
	}

929
	if (!crtc->hwmode.crtc_clock) {
930
		DRM_DEBUG_KMS("crtc %u is disabled\n", pipe);
931 932
		return -EBUSY;
	}
933 934

	/* Helper routine in DRM core does all the work: */
935 936
	return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
						     vblank_time, flags,
937
						     &crtc->hwmode);
938 939
}

940
static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv)
941
{
942
	u32 busy_up, busy_down, max_avg, min_avg;
943 944
	u8 new_delay;

945
	spin_lock(&mchdev_lock);
946

947 948
	I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));

949
	new_delay = dev_priv->ips.cur_delay;
950

951
	I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
952 953
	busy_up = I915_READ(RCPREVBSYTUPAVG);
	busy_down = I915_READ(RCPREVBSYTDNAVG);
954 955 956 957
	max_avg = I915_READ(RCBMAXAVG);
	min_avg = I915_READ(RCBMINAVG);

	/* Handle RCS change request from hw */
958
	if (busy_up > max_avg) {
959 960 961 962
		if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
			new_delay = dev_priv->ips.cur_delay - 1;
		if (new_delay < dev_priv->ips.max_delay)
			new_delay = dev_priv->ips.max_delay;
963
	} else if (busy_down < min_avg) {
964 965 966 967
		if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
			new_delay = dev_priv->ips.cur_delay + 1;
		if (new_delay > dev_priv->ips.min_delay)
			new_delay = dev_priv->ips.min_delay;
968 969
	}

970
	if (ironlake_set_drps(dev_priv, new_delay))
971
		dev_priv->ips.cur_delay = new_delay;
972

973
	spin_unlock(&mchdev_lock);
974

975 976 977
	return;
}

978
static void notify_ring(struct intel_engine_cs *engine)
979
{
980
	smp_store_mb(engine->irq_posted, true);
981 982 983 984
	if (intel_engine_wakeup(engine)) {
		trace_i915_gem_request_notify(engine);
		engine->user_interrupts++;
	}
985 986
}

987 988
static void vlv_c0_read(struct drm_i915_private *dev_priv,
			struct intel_rps_ei *ei)
989
{
990 991 992 993
	ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
	ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
	ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
}
994

995 996 997 998 999 1000
static bool vlv_c0_above(struct drm_i915_private *dev_priv,
			 const struct intel_rps_ei *old,
			 const struct intel_rps_ei *now,
			 int threshold)
{
	u64 time, c0;
1001
	unsigned int mul = 100;
1002

1003 1004
	if (old->cz_clock == 0)
		return false;
1005

1006 1007 1008
	if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
		mul <<= 8;

1009
	time = now->cz_clock - old->cz_clock;
1010
	time *= threshold * dev_priv->czclk_freq;
1011

1012 1013 1014
	/* Workload can be split between render + media, e.g. SwapBuffers
	 * being blitted in X after being rendered in mesa. To account for
	 * this we need to combine both engines into our activity counter.
1015
	 */
1016 1017
	c0 = now->render_c0 - old->render_c0;
	c0 += now->media_c0 - old->media_c0;
1018
	c0 *= mul * VLV_CZ_CLOCK_TO_MILLI_SEC;
1019

1020
	return c0 >= time;
1021 1022
}

1023
void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1024
{
1025 1026 1027
	vlv_c0_read(dev_priv, &dev_priv->rps.down_ei);
	dev_priv->rps.up_ei = dev_priv->rps.down_ei;
}
1028

1029 1030 1031 1032
static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
{
	struct intel_rps_ei now;
	u32 events = 0;
1033

1034
	if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0)
1035
		return 0;
1036

1037 1038 1039
	vlv_c0_read(dev_priv, &now);
	if (now.cz_clock == 0)
		return 0;
1040

1041 1042 1043
	if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
		if (!vlv_c0_above(dev_priv,
				  &dev_priv->rps.down_ei, &now,
1044
				  dev_priv->rps.down_threshold))
1045 1046 1047
			events |= GEN6_PM_RP_DOWN_THRESHOLD;
		dev_priv->rps.down_ei = now;
	}
1048

1049 1050 1051
	if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
		if (vlv_c0_above(dev_priv,
				 &dev_priv->rps.up_ei, &now,
1052
				 dev_priv->rps.up_threshold))
1053 1054
			events |= GEN6_PM_RP_UP_THRESHOLD;
		dev_priv->rps.up_ei = now;
1055 1056
	}

1057
	return events;
1058 1059
}

1060 1061
static bool any_waiters(struct drm_i915_private *dev_priv)
{
1062
	struct intel_engine_cs *engine;
1063

1064
	for_each_engine(engine, dev_priv)
1065
		if (intel_engine_has_waiter(engine))
1066 1067 1068 1069 1070
			return true;

	return false;
}

1071
static void gen6_pm_rps_work(struct work_struct *work)
1072
{
1073 1074
	struct drm_i915_private *dev_priv =
		container_of(work, struct drm_i915_private, rps.work);
1075 1076
	bool client_boost;
	int new_delay, adj, min, max;
P
Paulo Zanoni 已提交
1077
	u32 pm_iir;
1078

1079
	spin_lock_irq(&dev_priv->irq_lock);
I
Imre Deak 已提交
1080 1081 1082 1083 1084
	/* Speed up work cancelation during disabling rps interrupts. */
	if (!dev_priv->rps.interrupts_enabled) {
		spin_unlock_irq(&dev_priv->irq_lock);
		return;
	}
1085

1086 1087
	pm_iir = dev_priv->rps.pm_iir;
	dev_priv->rps.pm_iir = 0;
1088 1089
	/* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
	gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1090 1091
	client_boost = dev_priv->rps.client_boost;
	dev_priv->rps.client_boost = false;
1092
	spin_unlock_irq(&dev_priv->irq_lock);
1093

1094
	/* Make sure we didn't queue anything we're not going to process. */
1095
	WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1096

1097
	if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1098
		return;
1099

1100
	mutex_lock(&dev_priv->rps.hw_lock);
1101

1102 1103
	pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);

1104
	adj = dev_priv->rps.last_adj;
1105
	new_delay = dev_priv->rps.cur_freq;
1106 1107 1108 1109 1110 1111 1112
	min = dev_priv->rps.min_freq_softlimit;
	max = dev_priv->rps.max_freq_softlimit;

	if (client_boost) {
		new_delay = dev_priv->rps.max_freq_softlimit;
		adj = 0;
	} else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1113 1114
		if (adj > 0)
			adj *= 2;
1115 1116
		else /* CHV needs even encode values */
			adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1117 1118 1119 1120
		/*
		 * For better performance, jump directly
		 * to RPe if we're below it.
		 */
1121
		if (new_delay < dev_priv->rps.efficient_freq - adj) {
1122
			new_delay = dev_priv->rps.efficient_freq;
1123 1124
			adj = 0;
		}
1125 1126
	} else if (any_waiters(dev_priv)) {
		adj = 0;
1127
	} else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1128 1129
		if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
			new_delay = dev_priv->rps.efficient_freq;
1130
		else
1131
			new_delay = dev_priv->rps.min_freq_softlimit;
1132 1133 1134 1135
		adj = 0;
	} else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
		if (adj < 0)
			adj *= 2;
1136 1137
		else /* CHV needs even encode values */
			adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1138
	} else { /* unknown event */
1139
		adj = 0;
1140
	}
1141

1142 1143
	dev_priv->rps.last_adj = adj;

1144 1145 1146
	/* sysfs frequency interfaces may have snuck in while servicing the
	 * interrupt
	 */
1147
	new_delay += adj;
1148
	new_delay = clamp_t(int, new_delay, min, max);
1149

1150
	intel_set_rps(dev_priv, new_delay);
1151

1152
	mutex_unlock(&dev_priv->rps.hw_lock);
1153 1154
}

1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166

/**
 * ivybridge_parity_work - Workqueue called when a parity error interrupt
 * occurred.
 * @work: workqueue struct
 *
 * Doesn't actually do anything except notify userspace. As a consequence of
 * this event, userspace should try to remap the bad rows since statistically
 * it is likely the same row is more likely to go bad again.
 */
static void ivybridge_parity_work(struct work_struct *work)
{
1167 1168
	struct drm_i915_private *dev_priv =
		container_of(work, struct drm_i915_private, l3_parity.error_work);
1169
	u32 error_status, row, bank, subbank;
1170
	char *parity_event[6];
1171
	uint32_t misccpctl;
1172
	uint8_t slice = 0;
1173 1174 1175 1176 1177 1178 1179

	/* We must turn off DOP level clock gating to access the L3 registers.
	 * In order to prevent a get/put style interface, acquire struct mutex
	 * any time we access those registers.
	 */
	mutex_lock(&dev_priv->dev->struct_mutex);

1180 1181 1182 1183
	/* If we've screwed up tracking, just let the interrupt fire again */
	if (WARN_ON(!dev_priv->l3_parity.which_slice))
		goto out;

1184 1185 1186 1187
	misccpctl = I915_READ(GEN7_MISCCPCTL);
	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
	POSTING_READ(GEN7_MISCCPCTL);

1188
	while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1189
		i915_reg_t reg;
1190

1191
		slice--;
1192
		if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv)))
1193
			break;
1194

1195
		dev_priv->l3_parity.which_slice &= ~(1<<slice);
1196

1197
		reg = GEN7_L3CDERRST1(slice);
1198

1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213
		error_status = I915_READ(reg);
		row = GEN7_PARITY_ERROR_ROW(error_status);
		bank = GEN7_PARITY_ERROR_BANK(error_status);
		subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);

		I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
		POSTING_READ(reg);

		parity_event[0] = I915_L3_PARITY_UEVENT "=1";
		parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
		parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
		parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
		parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
		parity_event[5] = NULL;

1214
		kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1215
				   KOBJ_CHANGE, parity_event);
1216

1217 1218
		DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
			  slice, row, bank, subbank);
1219

1220 1221 1222 1223 1224
		kfree(parity_event[4]);
		kfree(parity_event[3]);
		kfree(parity_event[2]);
		kfree(parity_event[1]);
	}
1225

1226
	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1227

1228 1229
out:
	WARN_ON(dev_priv->l3_parity.which_slice);
1230
	spin_lock_irq(&dev_priv->irq_lock);
1231
	gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1232
	spin_unlock_irq(&dev_priv->irq_lock);
1233 1234

	mutex_unlock(&dev_priv->dev->struct_mutex);
1235 1236
}

1237 1238
static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv,
					       u32 iir)
1239
{
1240
	if (!HAS_L3_DPF(dev_priv))
1241 1242
		return;

1243
	spin_lock(&dev_priv->irq_lock);
1244
	gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1245
	spin_unlock(&dev_priv->irq_lock);
1246

1247
	iir &= GT_PARITY_ERROR(dev_priv);
1248 1249 1250 1251 1252 1253
	if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
		dev_priv->l3_parity.which_slice |= 1 << 1;

	if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
		dev_priv->l3_parity.which_slice |= 1 << 0;

1254
	queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1255 1256
}

1257
static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv,
1258 1259
			       u32 gt_iir)
{
1260
	if (gt_iir & GT_RENDER_USER_INTERRUPT)
1261
		notify_ring(&dev_priv->engine[RCS]);
1262
	if (gt_iir & ILK_BSD_USER_INTERRUPT)
1263
		notify_ring(&dev_priv->engine[VCS]);
1264 1265
}

1266
static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
1267 1268
			       u32 gt_iir)
{
1269
	if (gt_iir & GT_RENDER_USER_INTERRUPT)
1270
		notify_ring(&dev_priv->engine[RCS]);
1271
	if (gt_iir & GT_BSD_USER_INTERRUPT)
1272
		notify_ring(&dev_priv->engine[VCS]);
1273
	if (gt_iir & GT_BLT_USER_INTERRUPT)
1274
		notify_ring(&dev_priv->engine[BCS]);
1275

1276 1277
	if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
		      GT_BSD_CS_ERROR_INTERRUPT |
1278 1279
		      GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
		DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1280

1281 1282
	if (gt_iir & GT_PARITY_ERROR(dev_priv))
		ivybridge_parity_error_irq_handler(dev_priv, gt_iir);
1283 1284
}

1285
static __always_inline void
1286
gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
1287 1288
{
	if (iir & (GT_RENDER_USER_INTERRUPT << test_shift))
1289
		notify_ring(engine);
1290
	if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift))
1291
		tasklet_schedule(&engine->irq_tasklet);
1292 1293
}

1294 1295 1296
static irqreturn_t gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
				   u32 master_ctl,
				   u32 gt_iir[4])
1297 1298 1299 1300
{
	irqreturn_t ret = IRQ_NONE;

	if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1301 1302 1303
		gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0));
		if (gt_iir[0]) {
			I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir[0]);
1304 1305 1306 1307 1308
			ret = IRQ_HANDLED;
		} else
			DRM_ERROR("The master control interrupt lied (GT0)!\n");
	}

1309
	if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1310 1311 1312
		gt_iir[1] = I915_READ_FW(GEN8_GT_IIR(1));
		if (gt_iir[1]) {
			I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir[1]);
1313
			ret = IRQ_HANDLED;
1314
		} else
1315
			DRM_ERROR("The master control interrupt lied (GT1)!\n");
1316 1317
	}

1318
	if (master_ctl & GEN8_GT_VECS_IRQ) {
1319 1320 1321
		gt_iir[3] = I915_READ_FW(GEN8_GT_IIR(3));
		if (gt_iir[3]) {
			I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir[3]);
1322 1323 1324 1325 1326
			ret = IRQ_HANDLED;
		} else
			DRM_ERROR("The master control interrupt lied (GT3)!\n");
	}

1327
	if (master_ctl & GEN8_GT_PM_IRQ) {
1328 1329
		gt_iir[2] = I915_READ_FW(GEN8_GT_IIR(2));
		if (gt_iir[2] & dev_priv->pm_rps_events) {
1330
			I915_WRITE_FW(GEN8_GT_IIR(2),
1331
				      gt_iir[2] & dev_priv->pm_rps_events);
1332
			ret = IRQ_HANDLED;
1333 1334 1335 1336
		} else
			DRM_ERROR("The master control interrupt lied (PM)!\n");
	}

1337 1338 1339
	return ret;
}

1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364
static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
				u32 gt_iir[4])
{
	if (gt_iir[0]) {
		gen8_cs_irq_handler(&dev_priv->engine[RCS],
				    gt_iir[0], GEN8_RCS_IRQ_SHIFT);
		gen8_cs_irq_handler(&dev_priv->engine[BCS],
				    gt_iir[0], GEN8_BCS_IRQ_SHIFT);
	}

	if (gt_iir[1]) {
		gen8_cs_irq_handler(&dev_priv->engine[VCS],
				    gt_iir[1], GEN8_VCS1_IRQ_SHIFT);
		gen8_cs_irq_handler(&dev_priv->engine[VCS2],
				    gt_iir[1], GEN8_VCS2_IRQ_SHIFT);
	}

	if (gt_iir[3])
		gen8_cs_irq_handler(&dev_priv->engine[VECS],
				    gt_iir[3], GEN8_VECS_IRQ_SHIFT);

	if (gt_iir[2] & dev_priv->pm_rps_events)
		gen6_rps_irq_handler(dev_priv, gt_iir[2]);
}

1365 1366 1367 1368
static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
{
	switch (port) {
	case PORT_A:
1369
		return val & PORTA_HOTPLUG_LONG_DETECT;
1370 1371 1372 1373 1374 1375 1376 1377 1378
	case PORT_B:
		return val & PORTB_HOTPLUG_LONG_DETECT;
	case PORT_C:
		return val & PORTC_HOTPLUG_LONG_DETECT;
	default:
		return false;
	}
}

1379 1380 1381 1382 1383 1384 1385 1386 1387 1388
static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
{
	switch (port) {
	case PORT_E:
		return val & PORTE_HOTPLUG_LONG_DETECT;
	default:
		return false;
	}
}

1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404
static bool spt_port_hotplug_long_detect(enum port port, u32 val)
{
	switch (port) {
	case PORT_A:
		return val & PORTA_HOTPLUG_LONG_DETECT;
	case PORT_B:
		return val & PORTB_HOTPLUG_LONG_DETECT;
	case PORT_C:
		return val & PORTC_HOTPLUG_LONG_DETECT;
	case PORT_D:
		return val & PORTD_HOTPLUG_LONG_DETECT;
	default:
		return false;
	}
}

1405 1406 1407 1408 1409 1410 1411 1412 1413 1414
static bool ilk_port_hotplug_long_detect(enum port port, u32 val)
{
	switch (port) {
	case PORT_A:
		return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
	default:
		return false;
	}
}

1415
static bool pch_port_hotplug_long_detect(enum port port, u32 val)
1416 1417 1418
{
	switch (port) {
	case PORT_B:
1419
		return val & PORTB_HOTPLUG_LONG_DETECT;
1420
	case PORT_C:
1421
		return val & PORTC_HOTPLUG_LONG_DETECT;
1422
	case PORT_D:
1423 1424 1425
		return val & PORTD_HOTPLUG_LONG_DETECT;
	default:
		return false;
1426 1427 1428
	}
}

1429
static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
1430 1431 1432
{
	switch (port) {
	case PORT_B:
1433
		return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1434
	case PORT_C:
1435
		return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1436
	case PORT_D:
1437 1438 1439
		return val & PORTD_HOTPLUG_INT_LONG_PULSE;
	default:
		return false;
1440 1441 1442
	}
}

1443 1444 1445 1446 1447 1448 1449
/*
 * Get a bit mask of pins that have triggered, and which ones may be long.
 * This can be called multiple times with the same masks to accumulate
 * hotplug detection results from several registers.
 *
 * Note that the caller is expected to zero out the masks initially.
 */
1450
static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
1451
			     u32 hotplug_trigger, u32 dig_hotplug_reg,
1452 1453
			     const u32 hpd[HPD_NUM_PINS],
			     bool long_pulse_detect(enum port port, u32 val))
1454
{
1455
	enum port port;
1456 1457 1458
	int i;

	for_each_hpd_pin(i) {
1459 1460
		if ((hpd[i] & hotplug_trigger) == 0)
			continue;
1461

1462 1463
		*pin_mask |= BIT(i);

1464 1465 1466
		if (!intel_hpd_pin_to_port(i, &port))
			continue;

1467
		if (long_pulse_detect(port, dig_hotplug_reg))
1468
			*long_mask |= BIT(i);
1469 1470 1471 1472 1473 1474 1475
	}

	DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
			 hotplug_trigger, dig_hotplug_reg, *pin_mask);

}

1476
static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1477
{
1478
	wake_up_all(&dev_priv->gmbus_wait_queue);
1479 1480
}

1481
static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1482
{
1483
	wake_up_all(&dev_priv->gmbus_wait_queue);
1484 1485
}

1486
#if defined(CONFIG_DEBUG_FS)
1487 1488
static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
					 enum pipe pipe,
1489 1490 1491
					 uint32_t crc0, uint32_t crc1,
					 uint32_t crc2, uint32_t crc3,
					 uint32_t crc4)
1492 1493 1494
{
	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
	struct intel_pipe_crc_entry *entry;
1495
	int head, tail;
1496

1497 1498
	spin_lock(&pipe_crc->lock);

1499
	if (!pipe_crc->entries) {
1500
		spin_unlock(&pipe_crc->lock);
1501
		DRM_DEBUG_KMS("spurious interrupt\n");
1502 1503 1504
		return;
	}

1505 1506
	head = pipe_crc->head;
	tail = pipe_crc->tail;
1507 1508

	if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1509
		spin_unlock(&pipe_crc->lock);
1510 1511 1512 1513 1514
		DRM_ERROR("CRC buffer overflowing\n");
		return;
	}

	entry = &pipe_crc->entries[head];
1515

1516 1517
	entry->frame = dev_priv->dev->driver->get_vblank_counter(dev_priv->dev,
								 pipe);
1518 1519 1520 1521 1522
	entry->crc[0] = crc0;
	entry->crc[1] = crc1;
	entry->crc[2] = crc2;
	entry->crc[3] = crc3;
	entry->crc[4] = crc4;
1523 1524

	head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1525 1526 1527
	pipe_crc->head = head;

	spin_unlock(&pipe_crc->lock);
1528 1529

	wake_up_interruptible(&pipe_crc->wq);
1530
}
1531 1532
#else
static inline void
1533 1534
display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
			     enum pipe pipe,
1535 1536 1537 1538 1539
			     uint32_t crc0, uint32_t crc1,
			     uint32_t crc2, uint32_t crc3,
			     uint32_t crc4) {}
#endif

1540

1541 1542
static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
				     enum pipe pipe)
D
Daniel Vetter 已提交
1543
{
1544
	display_pipe_crc_irq_handler(dev_priv, pipe,
1545 1546
				     I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
				     0, 0, 0, 0);
D
Daniel Vetter 已提交
1547 1548
}

1549 1550
static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
				     enum pipe pipe)
1551
{
1552
	display_pipe_crc_irq_handler(dev_priv, pipe,
1553 1554 1555 1556 1557
				     I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
				     I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
				     I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
				     I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
				     I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1558
}
1559

1560 1561
static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
				      enum pipe pipe)
1562
{
1563 1564
	uint32_t res1, res2;

1565
	if (INTEL_GEN(dev_priv) >= 3)
1566 1567 1568 1569
		res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
	else
		res1 = 0;

1570
	if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1571 1572 1573
		res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
	else
		res2 = 0;
1574

1575
	display_pipe_crc_irq_handler(dev_priv, pipe,
1576 1577 1578 1579
				     I915_READ(PIPE_CRC_RES_RED(pipe)),
				     I915_READ(PIPE_CRC_RES_GREEN(pipe)),
				     I915_READ(PIPE_CRC_RES_BLUE(pipe)),
				     res1, res2);
1580
}
1581

1582 1583 1584 1585
/* The RPS events need forcewake, so we add them to a work queue and mask their
 * IMR bits until the work is done. Other interrupts can be processed without
 * the work queue. */
static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1586
{
1587
	if (pm_iir & dev_priv->pm_rps_events) {
1588
		spin_lock(&dev_priv->irq_lock);
1589
		gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
I
Imre Deak 已提交
1590 1591
		if (dev_priv->rps.interrupts_enabled) {
			dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1592
			schedule_work(&dev_priv->rps.work);
I
Imre Deak 已提交
1593
		}
1594
		spin_unlock(&dev_priv->irq_lock);
1595 1596
	}

1597 1598 1599
	if (INTEL_INFO(dev_priv)->gen >= 8)
		return;

1600
	if (HAS_VEBOX(dev_priv)) {
1601
		if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1602
			notify_ring(&dev_priv->engine[VECS]);
B
Ben Widawsky 已提交
1603

1604 1605
		if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
			DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
B
Ben Widawsky 已提交
1606
	}
1607 1608
}

1609
static bool intel_pipe_handle_vblank(struct drm_i915_private *dev_priv,
1610
				     enum pipe pipe)
1611
{
1612 1613 1614 1615
	bool ret;

	ret = drm_handle_vblank(dev_priv->dev, pipe);
	if (ret)
1616
		intel_finish_page_flip_mmio(dev_priv, pipe);
1617 1618

	return ret;
1619 1620
}

1621 1622
static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
					u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1623 1624 1625
{
	int pipe;

1626
	spin_lock(&dev_priv->irq_lock);
1627 1628 1629 1630 1631 1632

	if (!dev_priv->display_irqs_enabled) {
		spin_unlock(&dev_priv->irq_lock);
		return;
	}

1633
	for_each_pipe(dev_priv, pipe) {
1634
		i915_reg_t reg;
1635
		u32 mask, iir_bit = 0;
1636

1637 1638 1639 1640 1641 1642 1643
		/*
		 * PIPESTAT bits get signalled even when the interrupt is
		 * disabled with the mask bits, and some of the status bits do
		 * not generate interrupts at all (like the underrun bit). Hence
		 * we need to be careful that we only handle what we want to
		 * handle.
		 */
1644 1645 1646

		/* fifo underruns are filterered in the underrun handler. */
		mask = PIPE_FIFO_UNDERRUN_STATUS;
1647 1648 1649 1650 1651 1652 1653 1654

		switch (pipe) {
		case PIPE_A:
			iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
			break;
		case PIPE_B:
			iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
			break;
1655 1656 1657
		case PIPE_C:
			iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
			break;
1658 1659 1660 1661 1662
		}
		if (iir & iir_bit)
			mask |= dev_priv->pipestat_irq_mask[pipe];

		if (!mask)
1663 1664 1665
			continue;

		reg = PIPESTAT(pipe);
1666 1667
		mask |= PIPESTAT_INT_ENABLE_MASK;
		pipe_stats[pipe] = I915_READ(reg) & mask;
1668 1669 1670 1671

		/*
		 * Clear the PIPE*STAT regs before the IIR
		 */
1672 1673
		if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
					PIPESTAT_INT_STATUS_MASK))
1674 1675
			I915_WRITE(reg, pipe_stats[pipe]);
	}
1676
	spin_unlock(&dev_priv->irq_lock);
1677 1678
}

1679
static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1680 1681 1682
					    u32 pipe_stats[I915_MAX_PIPES])
{
	enum pipe pipe;
1683

1684
	for_each_pipe(dev_priv, pipe) {
1685 1686 1687
		if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
		    intel_pipe_handle_vblank(dev_priv, pipe))
			intel_check_page_flip(dev_priv, pipe);
1688

1689
		if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)
1690
			intel_finish_page_flip_cs(dev_priv, pipe);
1691 1692

		if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1693
			i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1694

1695 1696
		if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1697 1698 1699
	}

	if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1700
		gmbus_irq_handler(dev_priv);
1701 1702
}

1703
static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
1704 1705 1706
{
	u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);

1707 1708
	if (hotplug_status)
		I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1709

1710 1711 1712
	return hotplug_status;
}

1713
static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1714 1715 1716
				 u32 hotplug_status)
{
	u32 pin_mask = 0, long_mask = 0;
1717

1718 1719
	if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
	    IS_CHERRYVIEW(dev_priv)) {
1720
		u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1721

1722 1723 1724 1725 1726
		if (hotplug_trigger) {
			intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
					   hotplug_trigger, hpd_status_g4x,
					   i9xx_port_hotplug_long_detect);

1727
			intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1728
		}
1729 1730

		if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1731
			dp_aux_irq_handler(dev_priv);
1732 1733
	} else {
		u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1734

1735 1736
		if (hotplug_trigger) {
			intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1737
					   hotplug_trigger, hpd_status_i915,
1738
					   i9xx_port_hotplug_long_detect);
1739
			intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1740
		}
1741
	}
1742 1743
}

1744
static irqreturn_t valleyview_irq_handler(int irq, void *arg)
J
Jesse Barnes 已提交
1745
{
1746
	struct drm_device *dev = arg;
1747
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
1748 1749
	irqreturn_t ret = IRQ_NONE;

1750 1751 1752
	if (!intel_irqs_enabled(dev_priv))
		return IRQ_NONE;

1753 1754 1755
	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
	disable_rpm_wakeref_asserts(dev_priv);

1756
	do {
1757
		u32 iir, gt_iir, pm_iir;
1758
		u32 pipe_stats[I915_MAX_PIPES] = {};
1759
		u32 hotplug_status = 0;
1760
		u32 ier = 0;
1761

J
Jesse Barnes 已提交
1762 1763
		gt_iir = I915_READ(GTIIR);
		pm_iir = I915_READ(GEN6_PMIIR);
1764
		iir = I915_READ(VLV_IIR);
J
Jesse Barnes 已提交
1765 1766

		if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1767
			break;
J
Jesse Barnes 已提交
1768 1769 1770

		ret = IRQ_HANDLED;

1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783
		/*
		 * Theory on interrupt generation, based on empirical evidence:
		 *
		 * x = ((VLV_IIR & VLV_IER) ||
		 *      (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
		 *       (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
		 *
		 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
		 * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
		 * guarantee the CPU interrupt will be raised again even if we
		 * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
		 * bits this time around.
		 */
1784
		I915_WRITE(VLV_MASTER_IER, 0);
1785 1786
		ier = I915_READ(VLV_IER);
		I915_WRITE(VLV_IER, 0);
1787 1788 1789 1790 1791 1792

		if (gt_iir)
			I915_WRITE(GTIIR, gt_iir);
		if (pm_iir)
			I915_WRITE(GEN6_PMIIR, pm_iir);

1793
		if (iir & I915_DISPLAY_PORT_INTERRUPT)
1794
			hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1795

1796 1797
		/* Call regardless, as some status bits might not be
		 * signalled in iir */
1798
		valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1799 1800 1801 1802 1803 1804 1805

		/*
		 * VLV_IIR is single buffered, and reflects the level
		 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
		 */
		if (iir)
			I915_WRITE(VLV_IIR, iir);
1806

1807
		I915_WRITE(VLV_IER, ier);
1808 1809
		I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
		POSTING_READ(VLV_MASTER_IER);
1810

1811
		if (gt_iir)
1812
			snb_gt_irq_handler(dev_priv, gt_iir);
1813 1814 1815
		if (pm_iir)
			gen6_rps_irq_handler(dev_priv, pm_iir);

1816
		if (hotplug_status)
1817
			i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1818

1819
		valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1820
	} while (0);
J
Jesse Barnes 已提交
1821

1822 1823
	enable_rpm_wakeref_asserts(dev_priv);

J
Jesse Barnes 已提交
1824 1825 1826
	return ret;
}

1827 1828
static irqreturn_t cherryview_irq_handler(int irq, void *arg)
{
1829
	struct drm_device *dev = arg;
1830 1831 1832
	struct drm_i915_private *dev_priv = dev->dev_private;
	irqreturn_t ret = IRQ_NONE;

1833 1834 1835
	if (!intel_irqs_enabled(dev_priv))
		return IRQ_NONE;

1836 1837 1838
	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
	disable_rpm_wakeref_asserts(dev_priv);

1839
	do {
1840
		u32 master_ctl, iir;
1841
		u32 gt_iir[4] = {};
1842
		u32 pipe_stats[I915_MAX_PIPES] = {};
1843
		u32 hotplug_status = 0;
1844 1845
		u32 ier = 0;

1846 1847
		master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
		iir = I915_READ(VLV_IIR);
1848

1849 1850
		if (master_ctl == 0 && iir == 0)
			break;
1851

1852 1853
		ret = IRQ_HANDLED;

1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866
		/*
		 * Theory on interrupt generation, based on empirical evidence:
		 *
		 * x = ((VLV_IIR & VLV_IER) ||
		 *      ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
		 *       (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
		 *
		 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
		 * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
		 * guarantee the CPU interrupt will be raised again even if we
		 * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
		 * bits this time around.
		 */
1867
		I915_WRITE(GEN8_MASTER_IRQ, 0);
1868 1869
		ier = I915_READ(VLV_IER);
		I915_WRITE(VLV_IER, 0);
1870

1871
		gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
1872

1873
		if (iir & I915_DISPLAY_PORT_INTERRUPT)
1874
			hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1875

1876 1877
		/* Call regardless, as some status bits might not be
		 * signalled in iir */
1878
		valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1879

1880 1881 1882 1883 1884 1885 1886
		/*
		 * VLV_IIR is single buffered, and reflects the level
		 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
		 */
		if (iir)
			I915_WRITE(VLV_IIR, iir);

1887
		I915_WRITE(VLV_IER, ier);
1888
		I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
1889
		POSTING_READ(GEN8_MASTER_IRQ);
1890

1891 1892
		gen8_gt_irq_handler(dev_priv, gt_iir);

1893
		if (hotplug_status)
1894
			i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1895

1896
		valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1897
	} while (0);
1898

1899 1900
	enable_rpm_wakeref_asserts(dev_priv);

1901 1902 1903
	return ret;
}

1904 1905
static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
				u32 hotplug_trigger,
1906 1907 1908 1909
				const u32 hpd[HPD_NUM_PINS])
{
	u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;

1910 1911 1912 1913 1914 1915
	/*
	 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
	 * unless we touch the hotplug register, even if hotplug_trigger is
	 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
	 * errors.
	 */
1916
	dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1917 1918 1919 1920 1921 1922 1923 1924
	if (!hotplug_trigger) {
		u32 mask = PORTA_HOTPLUG_STATUS_MASK |
			PORTD_HOTPLUG_STATUS_MASK |
			PORTC_HOTPLUG_STATUS_MASK |
			PORTB_HOTPLUG_STATUS_MASK;
		dig_hotplug_reg &= ~mask;
	}

1925
	I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1926 1927
	if (!hotplug_trigger)
		return;
1928 1929 1930 1931 1932

	intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
			   dig_hotplug_reg, hpd,
			   pch_port_hotplug_long_detect);

1933
	intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1934 1935
}

1936
static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1937
{
1938
	int pipe;
1939
	u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1940

1941
	ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx);
1942

1943 1944 1945
	if (pch_iir & SDE_AUDIO_POWER_MASK) {
		int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
			       SDE_AUDIO_POWER_SHIFT);
1946
		DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1947 1948
				 port_name(port));
	}
1949

1950
	if (pch_iir & SDE_AUX_MASK)
1951
		dp_aux_irq_handler(dev_priv);
1952

1953
	if (pch_iir & SDE_GMBUS)
1954
		gmbus_irq_handler(dev_priv);
1955 1956 1957 1958 1959 1960 1961 1962 1963 1964

	if (pch_iir & SDE_AUDIO_HDCP_MASK)
		DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");

	if (pch_iir & SDE_AUDIO_TRANS_MASK)
		DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");

	if (pch_iir & SDE_POISON)
		DRM_ERROR("PCH poison interrupt\n");

1965
	if (pch_iir & SDE_FDI_MASK)
1966
		for_each_pipe(dev_priv, pipe)
1967 1968 1969
			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
					 pipe_name(pipe),
					 I915_READ(FDI_RX_IIR(pipe)));
1970 1971 1972 1973 1974 1975 1976 1977

	if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
		DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");

	if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
		DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");

	if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1978
		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
1979 1980

	if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1981
		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
1982 1983
}

1984
static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
1985 1986
{
	u32 err_int = I915_READ(GEN7_ERR_INT);
D
Daniel Vetter 已提交
1987
	enum pipe pipe;
1988

1989 1990 1991
	if (err_int & ERR_INT_POISON)
		DRM_ERROR("Poison interrupt\n");

1992
	for_each_pipe(dev_priv, pipe) {
1993 1994
		if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1995

D
Daniel Vetter 已提交
1996
		if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1997 1998
			if (IS_IVYBRIDGE(dev_priv))
				ivb_pipe_crc_irq_handler(dev_priv, pipe);
D
Daniel Vetter 已提交
1999
			else
2000
				hsw_pipe_crc_irq_handler(dev_priv, pipe);
D
Daniel Vetter 已提交
2001 2002
		}
	}
2003

2004 2005 2006
	I915_WRITE(GEN7_ERR_INT, err_int);
}

2007
static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
2008 2009 2010
{
	u32 serr_int = I915_READ(SERR_INT);

2011 2012 2013
	if (serr_int & SERR_INT_POISON)
		DRM_ERROR("PCH poison interrupt\n");

2014
	if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2015
		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2016 2017

	if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2018
		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2019 2020

	if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2021
		intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
2022 2023

	I915_WRITE(SERR_INT, serr_int);
2024 2025
}

2026
static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2027 2028
{
	int pipe;
2029
	u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2030

2031
	ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt);
2032

2033 2034 2035 2036 2037 2038
	if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
		int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
			       SDE_AUDIO_POWER_SHIFT_CPT);
		DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
				 port_name(port));
	}
2039 2040

	if (pch_iir & SDE_AUX_MASK_CPT)
2041
		dp_aux_irq_handler(dev_priv);
2042 2043

	if (pch_iir & SDE_GMBUS_CPT)
2044
		gmbus_irq_handler(dev_priv);
2045 2046 2047 2048 2049 2050 2051 2052

	if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
		DRM_DEBUG_DRIVER("Audio CP request interrupt\n");

	if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
		DRM_DEBUG_DRIVER("Audio CP change interrupt\n");

	if (pch_iir & SDE_FDI_MASK_CPT)
2053
		for_each_pipe(dev_priv, pipe)
2054 2055 2056
			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
					 pipe_name(pipe),
					 I915_READ(FDI_RX_IIR(pipe)));
2057 2058

	if (pch_iir & SDE_ERROR_CPT)
2059
		cpt_serr_int_handler(dev_priv);
2060 2061
}

2062
static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076
{
	u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
		~SDE_PORTE_HOTPLUG_SPT;
	u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
	u32 pin_mask = 0, long_mask = 0;

	if (hotplug_trigger) {
		u32 dig_hotplug_reg;

		dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
		I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);

		intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
				   dig_hotplug_reg, hpd_spt,
2077
				   spt_port_hotplug_long_detect);
2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091
	}

	if (hotplug2_trigger) {
		u32 dig_hotplug_reg;

		dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
		I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);

		intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger,
				   dig_hotplug_reg, hpd_spt,
				   spt_port_hotplug2_long_detect);
	}

	if (pin_mask)
2092
		intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2093 2094

	if (pch_iir & SDE_GMBUS_CPT)
2095
		gmbus_irq_handler(dev_priv);
2096 2097
}

2098 2099
static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
				u32 hotplug_trigger,
2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110
				const u32 hpd[HPD_NUM_PINS])
{
	u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;

	dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
	I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);

	intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
			   dig_hotplug_reg, hpd,
			   ilk_port_hotplug_long_detect);

2111
	intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2112 2113
}

2114 2115
static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
				    u32 de_iir)
2116
{
2117
	enum pipe pipe;
2118 2119
	u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;

2120
	if (hotplug_trigger)
2121
		ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk);
2122 2123

	if (de_iir & DE_AUX_CHANNEL_A)
2124
		dp_aux_irq_handler(dev_priv);
2125 2126

	if (de_iir & DE_GSE)
2127
		intel_opregion_asle_intr(dev_priv);
2128 2129 2130 2131

	if (de_iir & DE_POISON)
		DRM_ERROR("Poison interrupt\n");

2132
	for_each_pipe(dev_priv, pipe) {
2133 2134 2135
		if (de_iir & DE_PIPE_VBLANK(pipe) &&
		    intel_pipe_handle_vblank(dev_priv, pipe))
			intel_check_page_flip(dev_priv, pipe);
2136

2137
		if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2138
			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2139

2140
		if (de_iir & DE_PIPE_CRC_DONE(pipe))
2141
			i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2142

2143
		/* plane/pipes map 1:1 on ilk+ */
2144
		if (de_iir & DE_PLANE_FLIP_DONE(pipe))
2145
			intel_finish_page_flip_cs(dev_priv, pipe);
2146 2147 2148 2149 2150 2151
	}

	/* check event from PCH */
	if (de_iir & DE_PCH_EVENT) {
		u32 pch_iir = I915_READ(SDEIIR);

2152 2153
		if (HAS_PCH_CPT(dev_priv))
			cpt_irq_handler(dev_priv, pch_iir);
2154
		else
2155
			ibx_irq_handler(dev_priv, pch_iir);
2156 2157 2158 2159 2160

		/* should clear PCH hotplug event before clear CPU irq */
		I915_WRITE(SDEIIR, pch_iir);
	}

2161 2162
	if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT)
		ironlake_rps_change_irq_handler(dev_priv);
2163 2164
}

2165 2166
static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
				    u32 de_iir)
2167
{
2168
	enum pipe pipe;
2169 2170
	u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;

2171
	if (hotplug_trigger)
2172
		ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb);
2173 2174

	if (de_iir & DE_ERR_INT_IVB)
2175
		ivb_err_int_handler(dev_priv);
2176 2177

	if (de_iir & DE_AUX_CHANNEL_A_IVB)
2178
		dp_aux_irq_handler(dev_priv);
2179 2180

	if (de_iir & DE_GSE_IVB)
2181
		intel_opregion_asle_intr(dev_priv);
2182

2183
	for_each_pipe(dev_priv, pipe) {
2184 2185 2186
		if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
		    intel_pipe_handle_vblank(dev_priv, pipe))
			intel_check_page_flip(dev_priv, pipe);
2187 2188

		/* plane/pipes map 1:1 on ilk+ */
2189
		if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe))
2190
			intel_finish_page_flip_cs(dev_priv, pipe);
2191 2192 2193
	}

	/* check event from PCH */
2194
	if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2195 2196
		u32 pch_iir = I915_READ(SDEIIR);

2197
		cpt_irq_handler(dev_priv, pch_iir);
2198 2199 2200 2201 2202 2203

		/* clear PCH hotplug event before clear CPU irq */
		I915_WRITE(SDEIIR, pch_iir);
	}
}

2204 2205 2206 2207 2208 2209 2210 2211
/*
 * To handle irqs with the minimum potential races with fresh interrupts, we:
 * 1 - Disable Master Interrupt Control.
 * 2 - Find the source(s) of the interrupt.
 * 3 - Clear the Interrupt Identity bits (IIR).
 * 4 - Process the interrupt(s) that had bits set in the IIRs.
 * 5 - Re-enable Master Interrupt Control.
 */
2212
static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2213
{
2214
	struct drm_device *dev = arg;
2215
	struct drm_i915_private *dev_priv = dev->dev_private;
2216
	u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2217
	irqreturn_t ret = IRQ_NONE;
2218

2219 2220 2221
	if (!intel_irqs_enabled(dev_priv))
		return IRQ_NONE;

2222 2223 2224
	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
	disable_rpm_wakeref_asserts(dev_priv);

2225 2226 2227
	/* disable master interrupt before clearing iir  */
	de_ier = I915_READ(DEIER);
	I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2228
	POSTING_READ(DEIER);
2229

2230 2231 2232 2233 2234
	/* Disable south interrupts. We'll only write to SDEIIR once, so further
	 * interrupts will will be stored on its back queue, and then we'll be
	 * able to process them after we restore SDEIER (as soon as we restore
	 * it, we'll get an interrupt if SDEIIR still has something to process
	 * due to its back queue). */
2235
	if (!HAS_PCH_NOP(dev_priv)) {
2236 2237 2238 2239
		sde_ier = I915_READ(SDEIER);
		I915_WRITE(SDEIER, 0);
		POSTING_READ(SDEIER);
	}
2240

2241 2242
	/* Find, clear, then process each source of interrupt */

2243
	gt_iir = I915_READ(GTIIR);
2244
	if (gt_iir) {
2245 2246
		I915_WRITE(GTIIR, gt_iir);
		ret = IRQ_HANDLED;
2247
		if (INTEL_GEN(dev_priv) >= 6)
2248
			snb_gt_irq_handler(dev_priv, gt_iir);
2249
		else
2250
			ilk_gt_irq_handler(dev_priv, gt_iir);
2251 2252
	}

2253 2254
	de_iir = I915_READ(DEIIR);
	if (de_iir) {
2255 2256
		I915_WRITE(DEIIR, de_iir);
		ret = IRQ_HANDLED;
2257 2258
		if (INTEL_GEN(dev_priv) >= 7)
			ivb_display_irq_handler(dev_priv, de_iir);
2259
		else
2260
			ilk_display_irq_handler(dev_priv, de_iir);
2261 2262
	}

2263
	if (INTEL_GEN(dev_priv) >= 6) {
2264 2265 2266 2267
		u32 pm_iir = I915_READ(GEN6_PMIIR);
		if (pm_iir) {
			I915_WRITE(GEN6_PMIIR, pm_iir);
			ret = IRQ_HANDLED;
2268
			gen6_rps_irq_handler(dev_priv, pm_iir);
2269
		}
2270
	}
2271 2272 2273

	I915_WRITE(DEIER, de_ier);
	POSTING_READ(DEIER);
2274
	if (!HAS_PCH_NOP(dev_priv)) {
2275 2276 2277
		I915_WRITE(SDEIER, sde_ier);
		POSTING_READ(SDEIER);
	}
2278

2279 2280 2281
	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
	enable_rpm_wakeref_asserts(dev_priv);

2282 2283 2284
	return ret;
}

2285 2286
static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
				u32 hotplug_trigger,
2287
				const u32 hpd[HPD_NUM_PINS])
2288
{
2289
	u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2290

2291 2292
	dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
	I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2293

2294
	intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2295
			   dig_hotplug_reg, hpd,
2296
			   bxt_port_hotplug_long_detect);
2297

2298
	intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2299 2300
}

2301 2302
static irqreturn_t
gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2303 2304
{
	irqreturn_t ret = IRQ_NONE;
2305
	u32 iir;
2306
	enum pipe pipe;
J
Jesse Barnes 已提交
2307

2308
	if (master_ctl & GEN8_DE_MISC_IRQ) {
2309 2310 2311
		iir = I915_READ(GEN8_DE_MISC_IIR);
		if (iir) {
			I915_WRITE(GEN8_DE_MISC_IIR, iir);
2312
			ret = IRQ_HANDLED;
2313
			if (iir & GEN8_DE_MISC_GSE)
2314
				intel_opregion_asle_intr(dev_priv);
2315 2316
			else
				DRM_ERROR("Unexpected DE Misc interrupt\n");
2317
		}
2318 2319
		else
			DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2320 2321
	}

2322
	if (master_ctl & GEN8_DE_PORT_IRQ) {
2323 2324 2325
		iir = I915_READ(GEN8_DE_PORT_IIR);
		if (iir) {
			u32 tmp_mask;
2326
			bool found = false;
2327

2328
			I915_WRITE(GEN8_DE_PORT_IIR, iir);
2329
			ret = IRQ_HANDLED;
J
Jesse Barnes 已提交
2330

2331 2332 2333 2334 2335 2336 2337
			tmp_mask = GEN8_AUX_CHANNEL_A;
			if (INTEL_INFO(dev_priv)->gen >= 9)
				tmp_mask |= GEN9_AUX_CHANNEL_B |
					    GEN9_AUX_CHANNEL_C |
					    GEN9_AUX_CHANNEL_D;

			if (iir & tmp_mask) {
2338
				dp_aux_irq_handler(dev_priv);
2339 2340 2341
				found = true;
			}

2342 2343 2344
			if (IS_BROXTON(dev_priv)) {
				tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
				if (tmp_mask) {
2345 2346
					bxt_hpd_irq_handler(dev_priv, tmp_mask,
							    hpd_bxt);
2347 2348 2349 2350 2351
					found = true;
				}
			} else if (IS_BROADWELL(dev_priv)) {
				tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
				if (tmp_mask) {
2352 2353
					ilk_hpd_irq_handler(dev_priv,
							    tmp_mask, hpd_bdw);
2354 2355
					found = true;
				}
2356 2357
			}

2358 2359
			if (IS_BROXTON(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
				gmbus_irq_handler(dev_priv);
S
Shashank Sharma 已提交
2360 2361 2362
				found = true;
			}

2363
			if (!found)
2364
				DRM_ERROR("Unexpected DE Port interrupt\n");
2365
		}
2366 2367
		else
			DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2368 2369
	}

2370
	for_each_pipe(dev_priv, pipe) {
2371
		u32 flip_done, fault_errors;
2372

2373 2374
		if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
			continue;
2375

2376 2377 2378 2379 2380
		iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
		if (!iir) {
			DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
			continue;
		}
2381

2382 2383
		ret = IRQ_HANDLED;
		I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2384

2385 2386 2387
		if (iir & GEN8_PIPE_VBLANK &&
		    intel_pipe_handle_vblank(dev_priv, pipe))
			intel_check_page_flip(dev_priv, pipe);
2388

2389 2390 2391 2392 2393
		flip_done = iir;
		if (INTEL_INFO(dev_priv)->gen >= 9)
			flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE;
		else
			flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE;
2394

2395
		if (flip_done)
2396
			intel_finish_page_flip_cs(dev_priv, pipe);
2397

2398
		if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2399
			hsw_pipe_crc_irq_handler(dev_priv, pipe);
2400

2401 2402
		if (iir & GEN8_PIPE_FIFO_UNDERRUN)
			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2403

2404 2405 2406 2407 2408
		fault_errors = iir;
		if (INTEL_INFO(dev_priv)->gen >= 9)
			fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
		else
			fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2409

2410 2411 2412 2413
		if (fault_errors)
			DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
				  pipe_name(pipe),
				  fault_errors);
2414 2415
	}

2416
	if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2417
	    master_ctl & GEN8_DE_PCH_IRQ) {
2418 2419 2420 2421 2422
		/*
		 * FIXME(BDW): Assume for now that the new interrupt handling
		 * scheme also closed the SDE interrupt handling race we've seen
		 * on older pch-split platforms. But this needs testing.
		 */
2423 2424 2425
		iir = I915_READ(SDEIIR);
		if (iir) {
			I915_WRITE(SDEIIR, iir);
2426
			ret = IRQ_HANDLED;
2427 2428

			if (HAS_PCH_SPT(dev_priv))
2429
				spt_irq_handler(dev_priv, iir);
2430
			else
2431
				cpt_irq_handler(dev_priv, iir);
2432 2433 2434 2435 2436 2437 2438
		} else {
			/*
			 * Like on previous PCH there seems to be something
			 * fishy going on with forwarding PCH interrupts.
			 */
			DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
		}
2439 2440
	}

2441 2442 2443 2444 2445 2446 2447 2448
	return ret;
}

static irqreturn_t gen8_irq_handler(int irq, void *arg)
{
	struct drm_device *dev = arg;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 master_ctl;
2449
	u32 gt_iir[4] = {};
2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465
	irqreturn_t ret;

	if (!intel_irqs_enabled(dev_priv))
		return IRQ_NONE;

	master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
	master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
	if (!master_ctl)
		return IRQ_NONE;

	I915_WRITE_FW(GEN8_MASTER_IRQ, 0);

	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
	disable_rpm_wakeref_asserts(dev_priv);

	/* Find, clear, then process each source of interrupt */
2466 2467
	ret = gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
	gen8_gt_irq_handler(dev_priv, gt_iir);
2468 2469
	ret |= gen8_de_irq_handler(dev_priv, master_ctl);

2470 2471
	I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
	POSTING_READ_FW(GEN8_MASTER_IRQ);
2472

2473 2474
	enable_rpm_wakeref_asserts(dev_priv);

2475 2476 2477
	return ret;
}

2478
static void i915_error_wake_up(struct drm_i915_private *dev_priv)
2479 2480 2481 2482 2483 2484 2485 2486 2487
{
	/*
	 * Notify all waiters for GPU completion events that reset state has
	 * been changed, and that they need to restart their wait after
	 * checking for potential errors (and bail out to drop locks if there is
	 * a gpu reset pending so that i915_error_work_func can acquire them).
	 */

	/* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2488
	wake_up_all(&dev_priv->gpu_error.wait_queue);
2489 2490 2491 2492 2493

	/* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
	wake_up_all(&dev_priv->pending_flip_queue);
}

2494
/**
2495
 * i915_reset_and_wakeup - do process context error handling work
2496
 * @dev_priv: i915 device private
2497 2498 2499 2500
 *
 * Fire an error uevent so userspace can see that a hang or error
 * was detected.
 */
2501
static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
2502
{
2503
	struct kobject *kobj = &dev_priv->dev->primary->kdev->kobj;
2504 2505 2506
	char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
	char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
	char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2507
	int ret;
2508

2509
	kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
2510

2511 2512 2513 2514 2515 2516 2517 2518 2519 2520
	/*
	 * Note that there's only one work item which does gpu resets, so we
	 * need not worry about concurrent gpu resets potentially incrementing
	 * error->reset_counter twice. We only need to take care of another
	 * racing irq/hangcheck declaring the gpu dead for a second time. A
	 * quick check for that is good enough: schedule_work ensures the
	 * correct ordering between hang detection and this work item, and since
	 * the reset in-progress bit is only ever set by code outside of this
	 * work we don't need to worry about any other races.
	 */
2521
	if (i915_reset_in_progress(&dev_priv->gpu_error)) {
2522
		DRM_DEBUG_DRIVER("resetting chip\n");
2523
		kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
2524

2525 2526 2527 2528 2529 2530 2531 2532
		/*
		 * In most cases it's guaranteed that we get here with an RPM
		 * reference held, for example because there is a pending GPU
		 * request that won't finish until the reset is done. This
		 * isn't the case at least when we get here by doing a
		 * simulated reset via debugs, so get an RPM reference.
		 */
		intel_runtime_pm_get(dev_priv);
2533

2534
		intel_prepare_reset(dev_priv);
2535

2536 2537 2538 2539 2540 2541
		/*
		 * All state reset _must_ be completed before we update the
		 * reset counter, for otherwise waiters might miss the reset
		 * pending state and not properly drop locks, resulting in
		 * deadlocks with the reset work.
		 */
2542
		ret = i915_reset(dev_priv);
2543

2544
		intel_finish_reset(dev_priv);
2545

2546 2547
		intel_runtime_pm_put(dev_priv);

2548
		if (ret == 0)
2549
			kobject_uevent_env(kobj,
2550
					   KOBJ_CHANGE, reset_done_event);
2551

2552 2553 2554 2555
		/*
		 * Note: The wake_up also serves as a memory barrier so that
		 * waiters see the update value of the reset counter atomic_t.
		 */
2556
		wake_up_all(&dev_priv->gpu_error.reset_queue);
2557
	}
2558 2559
}

2560
static void i915_report_and_clear_eir(struct drm_i915_private *dev_priv)
2561
{
2562
	uint32_t instdone[I915_NUM_INSTDONE_REG];
2563
	u32 eir = I915_READ(EIR);
2564
	int pipe, i;
2565

2566 2567
	if (!eir)
		return;
2568

2569
	pr_err("render error detected, EIR: 0x%08x\n", eir);
2570

2571
	i915_get_extra_instdone(dev_priv, instdone);
2572

2573
	if (IS_G4X(dev_priv)) {
2574 2575 2576
		if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
			u32 ipeir = I915_READ(IPEIR_I965);

2577 2578
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2579 2580
			for (i = 0; i < ARRAY_SIZE(instdone); i++)
				pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2581 2582
			pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2583
			I915_WRITE(IPEIR_I965, ipeir);
2584
			POSTING_READ(IPEIR_I965);
2585 2586 2587
		}
		if (eir & GM45_ERROR_PAGE_TABLE) {
			u32 pgtbl_err = I915_READ(PGTBL_ER);
2588 2589
			pr_err("page table error\n");
			pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2590
			I915_WRITE(PGTBL_ER, pgtbl_err);
2591
			POSTING_READ(PGTBL_ER);
2592 2593 2594
		}
	}

2595
	if (!IS_GEN2(dev_priv)) {
2596 2597
		if (eir & I915_ERROR_PAGE_TABLE) {
			u32 pgtbl_err = I915_READ(PGTBL_ER);
2598 2599
			pr_err("page table error\n");
			pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2600
			I915_WRITE(PGTBL_ER, pgtbl_err);
2601
			POSTING_READ(PGTBL_ER);
2602 2603 2604 2605
		}
	}

	if (eir & I915_ERROR_MEMORY_REFRESH) {
2606
		pr_err("memory refresh error:\n");
2607
		for_each_pipe(dev_priv, pipe)
2608
			pr_err("pipe %c stat: 0x%08x\n",
2609
			       pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2610 2611 2612
		/* pipestat has already been acked */
	}
	if (eir & I915_ERROR_INSTRUCTION) {
2613 2614
		pr_err("instruction error\n");
		pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
2615 2616
		for (i = 0; i < ARRAY_SIZE(instdone); i++)
			pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2617
		if (INTEL_GEN(dev_priv) < 4) {
2618 2619
			u32 ipeir = I915_READ(IPEIR);

2620 2621 2622
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
2623
			I915_WRITE(IPEIR, ipeir);
2624
			POSTING_READ(IPEIR);
2625 2626 2627
		} else {
			u32 ipeir = I915_READ(IPEIR_I965);

2628 2629 2630 2631
			pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
			pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
			pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
			pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2632
			I915_WRITE(IPEIR_I965, ipeir);
2633
			POSTING_READ(IPEIR_I965);
2634 2635 2636 2637
		}
	}

	I915_WRITE(EIR, eir);
2638
	POSTING_READ(EIR);
2639 2640 2641 2642 2643 2644 2645 2646 2647 2648
	eir = I915_READ(EIR);
	if (eir) {
		/*
		 * some errors might have become stuck,
		 * mask them.
		 */
		DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
		I915_WRITE(EMR, I915_READ(EMR) | eir);
		I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
	}
2649 2650 2651
}

/**
2652
 * i915_handle_error - handle a gpu error
2653
 * @dev_priv: i915 device private
2654
 * @engine_mask: mask representing engines that are hung
2655
 * Do some basic checking of register state at error time and
2656 2657 2658 2659
 * dump it to the syslog.  Also call i915_capture_error_state() to make
 * sure we get a record and make it available in debugfs.  Fire a uevent
 * so userspace knows something bad happened (should trigger collection
 * of a ring dump etc.).
2660
 * @fmt: Error message format string
2661
 */
2662 2663
void i915_handle_error(struct drm_i915_private *dev_priv,
		       u32 engine_mask,
2664
		       const char *fmt, ...)
2665
{
2666 2667
	va_list args;
	char error_msg[80];
2668

2669 2670 2671 2672
	va_start(args, fmt);
	vscnprintf(error_msg, sizeof(error_msg), fmt, args);
	va_end(args);

2673 2674
	i915_capture_error_state(dev_priv, engine_mask, error_msg);
	i915_report_and_clear_eir(dev_priv);
2675

2676
	if (engine_mask) {
2677
		atomic_or(I915_RESET_IN_PROGRESS_FLAG,
2678
				&dev_priv->gpu_error.reset_counter);
2679

2680
		/*
2681 2682 2683
		 * Wakeup waiting processes so that the reset function
		 * i915_reset_and_wakeup doesn't deadlock trying to grab
		 * various locks. By bumping the reset counter first, the woken
2684 2685 2686 2687 2688 2689 2690 2691
		 * processes will see a reset in progress and back off,
		 * releasing their locks and then wait for the reset completion.
		 * We must do this for _all_ gpu waiters that might hold locks
		 * that the reset work needs to acquire.
		 *
		 * Note: The wake_up serves as the required memory barrier to
		 * ensure that the waiters see the updated value of the reset
		 * counter atomic_t.
2692
		 */
2693
		i915_error_wake_up(dev_priv);
2694 2695
	}

2696
	i915_reset_and_wakeup(dev_priv);
2697 2698
}

2699 2700 2701
/* Called from drm generic code, passed 'crtc' which
 * we use as a pipe index
 */
2702
static int i915_enable_vblank(struct drm_device *dev, unsigned int pipe)
2703
{
2704
	struct drm_i915_private *dev_priv = dev->dev_private;
2705
	unsigned long irqflags;
2706

2707
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2708
	if (INTEL_INFO(dev)->gen >= 4)
2709
		i915_enable_pipestat(dev_priv, pipe,
2710
				     PIPE_START_VBLANK_INTERRUPT_STATUS);
2711
	else
2712
		i915_enable_pipestat(dev_priv, pipe,
2713
				     PIPE_VBLANK_INTERRUPT_STATUS);
2714
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2715

2716 2717 2718
	return 0;
}

2719
static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
2720
{
2721
	struct drm_i915_private *dev_priv = dev->dev_private;
2722
	unsigned long irqflags;
2723
	uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2724
						     DE_PIPE_VBLANK(pipe);
2725 2726

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2727
	ilk_enable_display_irq(dev_priv, bit);
2728 2729 2730 2731 2732
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

	return 0;
}

2733
static int valleyview_enable_vblank(struct drm_device *dev, unsigned int pipe)
J
Jesse Barnes 已提交
2734
{
2735
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
2736 2737 2738
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2739
	i915_enable_pipestat(dev_priv, pipe,
2740
			     PIPE_START_VBLANK_INTERRUPT_STATUS);
J
Jesse Barnes 已提交
2741 2742 2743 2744 2745
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

	return 0;
}

2746
static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
2747 2748 2749 2750 2751
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2752
	bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2753
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2754

2755 2756 2757
	return 0;
}

2758 2759 2760
/* Called from drm generic code, passed 'crtc' which
 * we use as a pipe index
 */
2761
static void i915_disable_vblank(struct drm_device *dev, unsigned int pipe)
2762
{
2763
	struct drm_i915_private *dev_priv = dev->dev_private;
2764
	unsigned long irqflags;
2765

2766
	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2767
	i915_disable_pipestat(dev_priv, pipe,
2768 2769
			      PIPE_VBLANK_INTERRUPT_STATUS |
			      PIPE_START_VBLANK_INTERRUPT_STATUS);
2770 2771 2772
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

2773
static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
2774
{
2775
	struct drm_i915_private *dev_priv = dev->dev_private;
2776
	unsigned long irqflags;
2777
	uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2778
						     DE_PIPE_VBLANK(pipe);
2779 2780

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2781
	ilk_disable_display_irq(dev_priv, bit);
2782 2783 2784
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

2785
static void valleyview_disable_vblank(struct drm_device *dev, unsigned int pipe)
J
Jesse Barnes 已提交
2786
{
2787
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
2788 2789 2790
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2791
	i915_disable_pipestat(dev_priv, pipe,
2792
			      PIPE_START_VBLANK_INTERRUPT_STATUS);
J
Jesse Barnes 已提交
2793 2794 2795
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

2796
static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
2797 2798 2799 2800 2801
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2802
	bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2803 2804 2805
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}

2806
static bool
2807
ring_idle(struct intel_engine_cs *engine, u32 seqno)
2808
{
2809 2810
	return i915_seqno_passed(seqno,
				 READ_ONCE(engine->last_submitted_seqno));
B
Ben Gamari 已提交
2811 2812
}

2813
static bool
2814
ipehr_is_semaphore_wait(struct intel_engine_cs *engine, u32 ipehr)
2815
{
2816
	if (INTEL_GEN(engine->i915) >= 8) {
2817
		return (ipehr >> 23) == 0x1c;
2818 2819 2820 2821 2822 2823 2824
	} else {
		ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
		return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
				 MI_SEMAPHORE_REGISTER);
	}
}

2825
static struct intel_engine_cs *
2826 2827
semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr,
				 u64 offset)
2828
{
2829
	struct drm_i915_private *dev_priv = engine->i915;
2830
	struct intel_engine_cs *signaller;
2831

2832
	if (INTEL_GEN(dev_priv) >= 8) {
2833
		for_each_engine(signaller, dev_priv) {
2834
			if (engine == signaller)
2835 2836
				continue;

2837
			if (offset == signaller->semaphore.signal_ggtt[engine->id])
2838 2839
				return signaller;
		}
2840 2841 2842
	} else {
		u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;

2843
		for_each_engine(signaller, dev_priv) {
2844
			if(engine == signaller)
2845 2846
				continue;

2847
			if (sync_bits == signaller->semaphore.mbox.wait[engine->id])
2848 2849 2850 2851
				return signaller;
		}
	}

2852
	DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2853
		  engine->id, ipehr, offset);
2854 2855 2856 2857

	return NULL;
}

2858
static struct intel_engine_cs *
2859
semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
2860
{
2861
	struct drm_i915_private *dev_priv = engine->i915;
2862
	u32 cmd, ipehr, head;
2863 2864
	u64 offset = 0;
	int i, backwards;
2865

2866 2867 2868 2869 2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882
	/*
	 * This function does not support execlist mode - any attempt to
	 * proceed further into this function will result in a kernel panic
	 * when dereferencing ring->buffer, which is not set up in execlist
	 * mode.
	 *
	 * The correct way of doing it would be to derive the currently
	 * executing ring buffer from the current context, which is derived
	 * from the currently running request. Unfortunately, to get the
	 * current request we would have to grab the struct_mutex before doing
	 * anything else, which would be ill-advised since some other thread
	 * might have grabbed it already and managed to hang itself, causing
	 * the hang checker to deadlock.
	 *
	 * Therefore, this function does not support execlist mode in its
	 * current form. Just return NULL and move on.
	 */
2883
	if (engine->buffer == NULL)
2884 2885
		return NULL;

2886
	ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
2887
	if (!ipehr_is_semaphore_wait(engine, ipehr))
2888
		return NULL;
2889

2890 2891 2892
	/*
	 * HEAD is likely pointing to the dword after the actual command,
	 * so scan backwards until we find the MBOX. But limit it to just 3
2893 2894
	 * or 4 dwords depending on the semaphore wait command size.
	 * Note that we don't care about ACTHD here since that might
2895 2896
	 * point at at batch, and semaphores are always emitted into the
	 * ringbuffer itself.
2897
	 */
2898
	head = I915_READ_HEAD(engine) & HEAD_ADDR;
2899
	backwards = (INTEL_GEN(dev_priv) >= 8) ? 5 : 4;
2900

2901
	for (i = backwards; i; --i) {
2902 2903 2904 2905 2906
		/*
		 * Be paranoid and presume the hw has gone off into the wild -
		 * our ring is smaller than what the hardware (and hence
		 * HEAD_ADDR) allows. Also handles wrap-around.
		 */
2907
		head &= engine->buffer->size - 1;
2908 2909

		/* This here seems to blow up */
2910
		cmd = ioread32(engine->buffer->virtual_start + head);
2911 2912 2913
		if (cmd == ipehr)
			break;

2914 2915
		head -= 4;
	}
2916

2917 2918
	if (!i)
		return NULL;
2919

2920
	*seqno = ioread32(engine->buffer->virtual_start + head + 4) + 1;
2921
	if (INTEL_GEN(dev_priv) >= 8) {
2922
		offset = ioread32(engine->buffer->virtual_start + head + 12);
2923
		offset <<= 32;
2924
		offset = ioread32(engine->buffer->virtual_start + head + 8);
2925
	}
2926
	return semaphore_wait_to_signaller_ring(engine, ipehr, offset);
2927 2928
}

2929
static int semaphore_passed(struct intel_engine_cs *engine)
2930
{
2931
	struct drm_i915_private *dev_priv = engine->i915;
2932
	struct intel_engine_cs *signaller;
2933
	u32 seqno;
2934

2935
	engine->hangcheck.deadlock++;
2936

2937
	signaller = semaphore_waits_for(engine, &seqno);
2938 2939 2940 2941
	if (signaller == NULL)
		return -1;

	/* Prevent pathological recursion due to driver bugs */
2942
	if (signaller->hangcheck.deadlock >= I915_NUM_ENGINES)
2943 2944
		return -1;

2945
	if (i915_seqno_passed(intel_engine_get_seqno(signaller), seqno))
2946 2947
		return 1;

2948 2949 2950
	/* cursory check for an unkickable deadlock */
	if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
	    semaphore_passed(signaller) < 0)
2951 2952 2953
		return -1;

	return 0;
2954 2955 2956 2957
}

static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
{
2958
	struct intel_engine_cs *engine;
2959

2960
	for_each_engine(engine, dev_priv)
2961
		engine->hangcheck.deadlock = 0;
2962 2963
}

2964
static bool subunits_stuck(struct intel_engine_cs *engine)
2965
{
2966 2967 2968 2969
	u32 instdone[I915_NUM_INSTDONE_REG];
	bool stuck;
	int i;

2970
	if (engine->id != RCS)
2971 2972
		return true;

2973
	i915_get_extra_instdone(engine->i915, instdone);
2974

2975 2976 2977 2978 2979 2980 2981
	/* There might be unstable subunit states even when
	 * actual head is not moving. Filter out the unstable ones by
	 * accumulating the undone -> done transitions and only
	 * consider those as progress.
	 */
	stuck = true;
	for (i = 0; i < I915_NUM_INSTDONE_REG; i++) {
2982
		const u32 tmp = instdone[i] | engine->hangcheck.instdone[i];
2983

2984
		if (tmp != engine->hangcheck.instdone[i])
2985 2986
			stuck = false;

2987
		engine->hangcheck.instdone[i] |= tmp;
2988 2989 2990 2991 2992 2993
	}

	return stuck;
}

static enum intel_ring_hangcheck_action
2994
head_stuck(struct intel_engine_cs *engine, u64 acthd)
2995
{
2996
	if (acthd != engine->hangcheck.acthd) {
2997 2998

		/* Clear subunit states on head movement */
2999 3000
		memset(engine->hangcheck.instdone, 0,
		       sizeof(engine->hangcheck.instdone));
3001

3002
		return HANGCHECK_ACTIVE;
3003
	}
3004

3005
	if (!subunits_stuck(engine))
3006 3007 3008 3009 3010 3011
		return HANGCHECK_ACTIVE;

	return HANGCHECK_HUNG;
}

static enum intel_ring_hangcheck_action
3012
ring_stuck(struct intel_engine_cs *engine, u64 acthd)
3013
{
3014
	struct drm_i915_private *dev_priv = engine->i915;
3015 3016 3017
	enum intel_ring_hangcheck_action ha;
	u32 tmp;

3018
	ha = head_stuck(engine, acthd);
3019 3020 3021
	if (ha != HANGCHECK_HUNG)
		return ha;

3022
	if (IS_GEN2(dev_priv))
3023
		return HANGCHECK_HUNG;
3024 3025 3026 3027 3028 3029

	/* Is the chip hanging on a WAIT_FOR_EVENT?
	 * If so we can simply poke the RB_WAIT bit
	 * and break the hang. This should work on
	 * all but the second generation chipsets.
	 */
3030
	tmp = I915_READ_CTL(engine);
3031
	if (tmp & RING_WAIT) {
3032
		i915_handle_error(dev_priv, 0,
3033
				  "Kicking stuck wait on %s",
3034 3035
				  engine->name);
		I915_WRITE_CTL(engine, tmp);
3036
		return HANGCHECK_KICK;
3037 3038
	}

3039
	if (INTEL_GEN(dev_priv) >= 6 && tmp & RING_WAIT_SEMAPHORE) {
3040
		switch (semaphore_passed(engine)) {
3041
		default:
3042
			return HANGCHECK_HUNG;
3043
		case 1:
3044
			i915_handle_error(dev_priv, 0,
3045
					  "Kicking stuck semaphore on %s",
3046 3047
					  engine->name);
			I915_WRITE_CTL(engine, tmp);
3048
			return HANGCHECK_KICK;
3049
		case 0:
3050
			return HANGCHECK_WAIT;
3051
		}
3052
	}
3053

3054
	return HANGCHECK_HUNG;
3055 3056
}

3057 3058
static unsigned kick_waiters(struct intel_engine_cs *engine)
{
3059
	struct drm_i915_private *i915 = engine->i915;
3060 3061 3062 3063
	unsigned user_interrupts = READ_ONCE(engine->user_interrupts);

	if (engine->hangcheck.user_interrupts == user_interrupts &&
	    !test_and_set_bit(engine->id, &i915->gpu_error.missed_irq_rings)) {
3064
		if (!test_bit(engine->id, &i915->gpu_error.test_irq_rings))
3065 3066
			DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
				  engine->name);
3067 3068

		intel_engine_enable_fake_irq(engine);
3069 3070 3071 3072
	}

	return user_interrupts;
}
3073
/*
B
Ben Gamari 已提交
3074
 * This is called when the chip hasn't reported back with completed
3075 3076 3077 3078 3079
 * batchbuffers in a long time. We keep track per ring seqno progress and
 * if there are no progress, hangcheck score for that ring is increased.
 * Further, acthd is inspected to see if the ring is stuck. On stuck case
 * we kick the ring. If we see no progress on three subsequent calls
 * we assume chip is wedged and try to fix it by resetting the chip.
B
Ben Gamari 已提交
3080
 */
3081
static void i915_hangcheck_elapsed(struct work_struct *work)
B
Ben Gamari 已提交
3082
{
3083 3084 3085
	struct drm_i915_private *dev_priv =
		container_of(work, typeof(*dev_priv),
			     gpu_error.hangcheck_work.work);
3086
	struct intel_engine_cs *engine;
3087
	enum intel_engine_id id;
3088
	int busy_count = 0, rings_hung = 0;
3089
	bool stuck[I915_NUM_ENGINES] = { 0 };
3090 3091 3092
#define BUSY 1
#define KICK 5
#define HUNG 20
3093
#define ACTIVE_DECAY 15
3094

3095
	if (!i915.enable_hangcheck)
3096 3097
		return;

3098 3099
	if (!lockless_dereference(dev_priv->gt.awake))
		return;
3100

3101 3102 3103 3104 3105 3106
	/* As enabling the GPU requires fairly extensive mmio access,
	 * periodically arm the mmio checker to see if we are triggering
	 * any invalid access.
	 */
	intel_uncore_arm_unclaimed_mmio_detection(dev_priv);

3107
	for_each_engine_id(engine, dev_priv, id) {
3108
		bool busy = intel_engine_has_waiter(engine);
3109 3110
		u64 acthd;
		u32 seqno;
3111
		unsigned user_interrupts;
3112

3113 3114
		semaphore_clear_deadlocks(dev_priv);

3115 3116 3117 3118 3119 3120 3121 3122 3123 3124
		/* We don't strictly need an irq-barrier here, as we are not
		 * serving an interrupt request, be paranoid in case the
		 * barrier has side-effects (such as preventing a broken
		 * cacheline snoop) and so be sure that we can see the seqno
		 * advance. If the seqno should stick, due to a stale
		 * cacheline, we would erroneously declare the GPU hung.
		 */
		if (engine->irq_seqno_barrier)
			engine->irq_seqno_barrier(engine);

3125
		acthd = intel_ring_get_active_head(engine);
3126
		seqno = intel_engine_get_seqno(engine);
3127

3128 3129 3130
		/* Reset stuck interrupts between batch advances */
		user_interrupts = 0;

3131 3132 3133
		if (engine->hangcheck.seqno == seqno) {
			if (ring_idle(engine, seqno)) {
				engine->hangcheck.action = HANGCHECK_IDLE;
3134
				if (busy) {
3135
					/* Safeguard against driver failure */
3136
					user_interrupts = kick_waiters(engine);
3137
					engine->hangcheck.score += BUSY;
3138
				}
3139
			} else {
3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152 3153 3154
				/* We always increment the hangcheck score
				 * if the ring is busy and still processing
				 * the same request, so that no single request
				 * can run indefinitely (such as a chain of
				 * batches). The only time we do not increment
				 * the hangcheck score on this ring, if this
				 * ring is in a legitimate wait for another
				 * ring. In that case the waiting ring is a
				 * victim and we want to be sure we catch the
				 * right culprit. Then every time we do kick
				 * the ring, add a small increment to the
				 * score so that we can catch a batch that is
				 * being repeatedly kicked and so responsible
				 * for stalling the machine.
				 */
3155 3156
				engine->hangcheck.action = ring_stuck(engine,
								      acthd);
3157

3158
				switch (engine->hangcheck.action) {
3159
				case HANGCHECK_IDLE:
3160
				case HANGCHECK_WAIT:
3161
					break;
3162
				case HANGCHECK_ACTIVE:
3163
					engine->hangcheck.score += BUSY;
3164
					break;
3165
				case HANGCHECK_KICK:
3166
					engine->hangcheck.score += KICK;
3167
					break;
3168
				case HANGCHECK_HUNG:
3169
					engine->hangcheck.score += HUNG;
3170
					stuck[id] = true;
3171 3172
					break;
				}
3173
			}
3174
		} else {
3175
			engine->hangcheck.action = HANGCHECK_ACTIVE;
3176

3177 3178 3179
			/* Gradually reduce the count so that we catch DoS
			 * attempts across multiple batches.
			 */
3180 3181 3182 3183
			if (engine->hangcheck.score > 0)
				engine->hangcheck.score -= ACTIVE_DECAY;
			if (engine->hangcheck.score < 0)
				engine->hangcheck.score = 0;
3184

3185
			/* Clear head and subunit states on seqno movement */
3186
			acthd = 0;
3187

3188 3189
			memset(engine->hangcheck.instdone, 0,
			       sizeof(engine->hangcheck.instdone));
3190 3191
		}

3192 3193
		engine->hangcheck.seqno = seqno;
		engine->hangcheck.acthd = acthd;
3194
		engine->hangcheck.user_interrupts = user_interrupts;
3195
		busy_count += busy;
3196
	}
3197

3198
	for_each_engine_id(engine, dev_priv, id) {
3199
		if (engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3200
			DRM_INFO("%s on %s\n",
3201
				 stuck[id] ? "stuck" : "no progress",
3202
				 engine->name);
3203
			rings_hung |= intel_engine_flag(engine);
3204 3205 3206
		}
	}

3207
	if (rings_hung)
3208
		i915_handle_error(dev_priv, rings_hung, "Engine(s) hung");
B
Ben Gamari 已提交
3209

3210
	/* Reset timer in case GPU hangs without another request being added */
3211
	if (busy_count)
3212
		i915_queue_hangcheck(dev_priv);
3213 3214
}

3215
static void ibx_irq_reset(struct drm_device *dev)
P
Paulo Zanoni 已提交
3216 3217 3218 3219 3220 3221
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (HAS_PCH_NOP(dev))
		return;

3222
	GEN5_IRQ_RESET(SDE);
3223 3224 3225

	if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
		I915_WRITE(SERR_INT, 0xffffffff);
P
Paulo Zanoni 已提交
3226
}
3227

P
Paulo Zanoni 已提交
3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238 3239 3240 3241 3242 3243
/*
 * SDEIER is also touched by the interrupt handler to work around missed PCH
 * interrupts. Hence we can't update it after the interrupt handler is enabled -
 * instead we unconditionally enable all PCH interrupt sources here, but then
 * only unmask them as needed with SDEIMR.
 *
 * This function needs to be called before interrupts are enabled.
 */
static void ibx_irq_pre_postinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (HAS_PCH_NOP(dev))
		return;

	WARN_ON(I915_READ(SDEIER) != 0);
P
Paulo Zanoni 已提交
3244 3245 3246 3247
	I915_WRITE(SDEIER, 0xffffffff);
	POSTING_READ(SDEIER);
}

3248
static void gen5_gt_irq_reset(struct drm_device *dev)
3249 3250 3251
{
	struct drm_i915_private *dev_priv = dev->dev_private;

3252
	GEN5_IRQ_RESET(GT);
P
Paulo Zanoni 已提交
3253
	if (INTEL_INFO(dev)->gen >= 6)
3254
		GEN5_IRQ_RESET(GEN6_PM);
3255 3256
}

3257 3258 3259 3260
static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
{
	enum pipe pipe;

3261 3262 3263 3264 3265
	if (IS_CHERRYVIEW(dev_priv))
		I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
	else
		I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);

3266
	i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
3267 3268
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));

3269 3270 3271 3272 3273 3274
	for_each_pipe(dev_priv, pipe) {
		I915_WRITE(PIPESTAT(pipe),
			   PIPE_FIFO_UNDERRUN_STATUS |
			   PIPESTAT_INT_STATUS_MASK);
		dev_priv->pipestat_irq_mask[pipe] = 0;
	}
3275 3276

	GEN5_IRQ_RESET(VLV_);
3277
	dev_priv->irq_mask = ~0;
3278 3279
}

3280 3281 3282
static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
{
	u32 pipestat_mask;
3283
	u32 enable_mask;
3284 3285 3286 3287 3288 3289 3290 3291 3292
	enum pipe pipe;

	pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
			PIPE_CRC_DONE_INTERRUPT_STATUS;

	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
	for_each_pipe(dev_priv, pipe)
		i915_enable_pipestat(dev_priv, pipe, pipestat_mask);

3293 3294 3295
	enable_mask = I915_DISPLAY_PORT_INTERRUPT |
		I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3296
	if (IS_CHERRYVIEW(dev_priv))
3297
		enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3298 3299 3300

	WARN_ON(dev_priv->irq_mask != ~0);

3301 3302 3303
	dev_priv->irq_mask = ~enable_mask;

	GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);
3304 3305 3306 3307 3308 3309 3310 3311 3312 3313 3314 3315 3316 3317 3318 3319 3320 3321 3322
}

/* drm_dma.h hooks
*/
static void ironlake_irq_reset(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	I915_WRITE(HWSTAM, 0xffffffff);

	GEN5_IRQ_RESET(DE);
	if (IS_GEN7(dev))
		I915_WRITE(GEN7_ERR_INT, 0xffffffff);

	gen5_gt_irq_reset(dev);

	ibx_irq_reset(dev);
}

J
Jesse Barnes 已提交
3323 3324
static void valleyview_irq_preinstall(struct drm_device *dev)
{
3325
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
3326

3327 3328 3329
	I915_WRITE(VLV_MASTER_IER, 0);
	POSTING_READ(VLV_MASTER_IER);

3330
	gen5_gt_irq_reset(dev);
J
Jesse Barnes 已提交
3331

3332
	spin_lock_irq(&dev_priv->irq_lock);
3333 3334
	if (dev_priv->display_irqs_enabled)
		vlv_display_irq_reset(dev_priv);
3335
	spin_unlock_irq(&dev_priv->irq_lock);
J
Jesse Barnes 已提交
3336 3337
}

3338 3339 3340 3341 3342 3343 3344 3345
static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
{
	GEN8_IRQ_RESET_NDX(GT, 0);
	GEN8_IRQ_RESET_NDX(GT, 1);
	GEN8_IRQ_RESET_NDX(GT, 2);
	GEN8_IRQ_RESET_NDX(GT, 3);
}

P
Paulo Zanoni 已提交
3346
static void gen8_irq_reset(struct drm_device *dev)
3347 3348 3349 3350 3351 3352 3353
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int pipe;

	I915_WRITE(GEN8_MASTER_IRQ, 0);
	POSTING_READ(GEN8_MASTER_IRQ);

3354
	gen8_gt_irq_reset(dev_priv);
3355

3356
	for_each_pipe(dev_priv, pipe)
3357 3358
		if (intel_display_power_is_enabled(dev_priv,
						   POWER_DOMAIN_PIPE(pipe)))
3359
			GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3360

3361 3362 3363
	GEN5_IRQ_RESET(GEN8_DE_PORT_);
	GEN5_IRQ_RESET(GEN8_DE_MISC_);
	GEN5_IRQ_RESET(GEN8_PCU_);
3364

3365 3366
	if (HAS_PCH_SPLIT(dev))
		ibx_irq_reset(dev);
3367
}
3368

3369 3370
void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
				     unsigned int pipe_mask)
3371
{
3372
	uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3373
	enum pipe pipe;
3374

3375
	spin_lock_irq(&dev_priv->irq_lock);
3376 3377 3378 3379
	for_each_pipe_masked(dev_priv, pipe, pipe_mask)
		GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
				  dev_priv->de_irq_mask[pipe],
				  ~dev_priv->de_irq_mask[pipe] | extra_ier);
3380
	spin_unlock_irq(&dev_priv->irq_lock);
3381 3382
}

3383 3384 3385
void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
				     unsigned int pipe_mask)
{
3386 3387
	enum pipe pipe;

3388
	spin_lock_irq(&dev_priv->irq_lock);
3389 3390
	for_each_pipe_masked(dev_priv, pipe, pipe_mask)
		GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3391 3392 3393 3394 3395 3396
	spin_unlock_irq(&dev_priv->irq_lock);

	/* make sure we're done processing display irqs */
	synchronize_irq(dev_priv->dev->irq);
}

3397 3398 3399 3400 3401 3402 3403
static void cherryview_irq_preinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	I915_WRITE(GEN8_MASTER_IRQ, 0);
	POSTING_READ(GEN8_MASTER_IRQ);

3404
	gen8_gt_irq_reset(dev_priv);
3405 3406 3407

	GEN5_IRQ_RESET(GEN8_PCU_);

3408
	spin_lock_irq(&dev_priv->irq_lock);
3409 3410
	if (dev_priv->display_irqs_enabled)
		vlv_display_irq_reset(dev_priv);
3411
	spin_unlock_irq(&dev_priv->irq_lock);
3412 3413
}

3414
static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
3415 3416 3417 3418 3419
				  const u32 hpd[HPD_NUM_PINS])
{
	struct intel_encoder *encoder;
	u32 enabled_irqs = 0;

3420
	for_each_intel_encoder(dev_priv->dev, encoder)
3421 3422 3423 3424 3425 3426
		if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
			enabled_irqs |= hpd[encoder->hpd_pin];

	return enabled_irqs;
}

3427
static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
3428
{
3429
	u32 hotplug_irqs, hotplug, enabled_irqs;
3430

3431
	if (HAS_PCH_IBX(dev_priv)) {
3432
		hotplug_irqs = SDE_HOTPLUG_MASK;
3433
		enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx);
3434
	} else {
3435
		hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3436
		enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt);
3437
	}
3438

3439
	ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3440 3441 3442

	/*
	 * Enable digital hotplug on the PCH, and configure the DP short pulse
3443 3444
	 * duration to 2ms (which is the minimum in the Display Port spec).
	 * The pulse duration bits are reserved on LPT+.
3445
	 */
3446 3447 3448 3449 3450
	hotplug = I915_READ(PCH_PORT_HOTPLUG);
	hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
	hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
	hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
	hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3451 3452 3453 3454
	/*
	 * When CPU and PCH are on the same package, port A
	 * HPD must be enabled in both north and south.
	 */
3455
	if (HAS_PCH_LPT_LP(dev_priv))
3456
		hotplug |= PORTA_HOTPLUG_ENABLE;
3457
	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3458
}
X
Xiong Zhang 已提交
3459

3460
static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3461 3462 3463 3464
{
	u32 hotplug_irqs, hotplug, enabled_irqs;

	hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3465
	enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt);
3466 3467 3468 3469 3470 3471

	ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);

	/* Enable digital hotplug on the PCH */
	hotplug = I915_READ(PCH_PORT_HOTPLUG);
	hotplug |= PORTD_HOTPLUG_ENABLE | PORTC_HOTPLUG_ENABLE |
3472
		PORTB_HOTPLUG_ENABLE | PORTA_HOTPLUG_ENABLE;
3473 3474 3475 3476 3477
	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);

	hotplug = I915_READ(PCH_PORT_HOTPLUG2);
	hotplug |= PORTE_HOTPLUG_ENABLE;
	I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3478 3479
}

3480
static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
3481 3482 3483
{
	u32 hotplug_irqs, hotplug, enabled_irqs;

3484
	if (INTEL_GEN(dev_priv) >= 8) {
3485
		hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3486
		enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw);
3487 3488

		bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3489
	} else if (INTEL_GEN(dev_priv) >= 7) {
3490
		hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3491
		enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb);
3492 3493

		ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3494 3495
	} else {
		hotplug_irqs = DE_DP_A_HOTPLUG;
3496
		enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk);
3497

3498 3499
		ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
	}
3500 3501 3502 3503

	/*
	 * Enable digital hotplug on the CPU, and configure the DP short pulse
	 * duration to 2ms (which is the minimum in the Display Port spec)
3504
	 * The pulse duration bits are reserved on HSW+.
3505 3506 3507 3508 3509 3510
	 */
	hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
	hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
	hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | DIGITAL_PORTA_PULSE_DURATION_2ms;
	I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);

3511
	ibx_hpd_irq_setup(dev_priv);
3512 3513
}

3514
static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3515
{
3516
	u32 hotplug_irqs, hotplug, enabled_irqs;
3517

3518
	enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt);
3519
	hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
3520

3521
	bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3522

3523 3524 3525
	hotplug = I915_READ(PCH_PORT_HOTPLUG);
	hotplug |= PORTC_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |
		PORTA_HOTPLUG_ENABLE;
3526 3527 3528 3529 3530 3531 3532 3533 3534 3535 3536 3537 3538 3539 3540 3541 3542 3543 3544 3545

	DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n",
		      hotplug, enabled_irqs);
	hotplug &= ~BXT_DDI_HPD_INVERT_MASK;

	/*
	 * For BXT invert bit has to be set based on AOB design
	 * for HPD detection logic, update it based on VBT fields.
	 */

	if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
	    intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
		hotplug |= BXT_DDIA_HPD_INVERT;
	if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
	    intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
		hotplug |= BXT_DDIB_HPD_INVERT;
	if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
	    intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
		hotplug |= BXT_DDIC_HPD_INVERT;

3546
	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3547 3548
}

P
Paulo Zanoni 已提交
3549 3550
static void ibx_irq_postinstall(struct drm_device *dev)
{
3551
	struct drm_i915_private *dev_priv = dev->dev_private;
3552
	u32 mask;
3553

D
Daniel Vetter 已提交
3554 3555 3556
	if (HAS_PCH_NOP(dev))
		return;

3557
	if (HAS_PCH_IBX(dev))
3558
		mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3559
	else
3560
		mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3561

3562
	gen5_assert_iir_is_zero(dev_priv, SDEIIR);
P
Paulo Zanoni 已提交
3563 3564 3565
	I915_WRITE(SDEIMR, ~mask);
}

3566 3567 3568 3569 3570 3571 3572 3573
static void gen5_gt_irq_postinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pm_irqs, gt_irqs;

	pm_irqs = gt_irqs = 0;

	dev_priv->gt_irq_mask = ~0;
3574
	if (HAS_L3_DPF(dev)) {
3575
		/* L3 parity interrupt is always unmasked. */
3576 3577
		dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
		gt_irqs |= GT_PARITY_ERROR(dev);
3578 3579 3580 3581
	}

	gt_irqs |= GT_RENDER_USER_INTERRUPT;
	if (IS_GEN5(dev)) {
3582
		gt_irqs |= ILK_BSD_USER_INTERRUPT;
3583 3584 3585 3586
	} else {
		gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
	}

P
Paulo Zanoni 已提交
3587
	GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3588 3589

	if (INTEL_INFO(dev)->gen >= 6) {
3590 3591 3592 3593
		/*
		 * RPS interrupts will get enabled/disabled on demand when RPS
		 * itself is enabled/disabled.
		 */
3594 3595 3596
		if (HAS_VEBOX(dev))
			pm_irqs |= PM_VEBOX_USER_INTERRUPT;

3597
		dev_priv->pm_irq_mask = 0xffffffff;
P
Paulo Zanoni 已提交
3598
		GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3599 3600 3601
	}
}

3602
static int ironlake_irq_postinstall(struct drm_device *dev)
3603
{
3604
	struct drm_i915_private *dev_priv = dev->dev_private;
3605 3606 3607 3608 3609 3610
	u32 display_mask, extra_mask;

	if (INTEL_INFO(dev)->gen >= 7) {
		display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
				DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
				DE_PLANEB_FLIP_DONE_IVB |
3611
				DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3612
		extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3613 3614
			      DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
			      DE_DP_A_HOTPLUG_IVB);
3615 3616 3617
	} else {
		display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
				DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3618 3619 3620
				DE_AUX_CHANNEL_A |
				DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
				DE_POISON);
3621 3622 3623
		extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
			      DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
			      DE_DP_A_HOTPLUG);
3624
	}
3625

3626
	dev_priv->irq_mask = ~display_mask;
3627

3628 3629
	I915_WRITE(HWSTAM, 0xeffe);

P
Paulo Zanoni 已提交
3630 3631
	ibx_irq_pre_postinstall(dev);

P
Paulo Zanoni 已提交
3632
	GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3633

3634
	gen5_gt_irq_postinstall(dev);
3635

P
Paulo Zanoni 已提交
3636
	ibx_irq_postinstall(dev);
3637

3638
	if (IS_IRONLAKE_M(dev)) {
3639 3640 3641
		/* Enable PCU event interrupts
		 *
		 * spinlocking not required here for correctness since interrupt
3642 3643
		 * setup is guaranteed to run in single-threaded context. But we
		 * need it to make the assert_spin_locked happy. */
3644
		spin_lock_irq(&dev_priv->irq_lock);
3645
		ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
3646
		spin_unlock_irq(&dev_priv->irq_lock);
3647 3648
	}

3649 3650 3651
	return 0;
}

3652 3653 3654 3655 3656 3657 3658 3659 3660
void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
{
	assert_spin_locked(&dev_priv->irq_lock);

	if (dev_priv->display_irqs_enabled)
		return;

	dev_priv->display_irqs_enabled = true;

3661 3662
	if (intel_irqs_enabled(dev_priv)) {
		vlv_display_irq_reset(dev_priv);
3663
		vlv_display_irq_postinstall(dev_priv);
3664
	}
3665 3666 3667 3668 3669 3670 3671 3672 3673 3674 3675
}

void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
{
	assert_spin_locked(&dev_priv->irq_lock);

	if (!dev_priv->display_irqs_enabled)
		return;

	dev_priv->display_irqs_enabled = false;

3676
	if (intel_irqs_enabled(dev_priv))
3677
		vlv_display_irq_reset(dev_priv);
3678 3679
}

3680 3681 3682 3683 3684

static int valleyview_irq_postinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

3685
	gen5_gt_irq_postinstall(dev);
J
Jesse Barnes 已提交
3686

3687
	spin_lock_irq(&dev_priv->irq_lock);
3688 3689
	if (dev_priv->display_irqs_enabled)
		vlv_display_irq_postinstall(dev_priv);
3690 3691
	spin_unlock_irq(&dev_priv->irq_lock);

J
Jesse Barnes 已提交
3692
	I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3693
	POSTING_READ(VLV_MASTER_IER);
3694 3695 3696 3697

	return 0;
}

3698 3699 3700 3701 3702
static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
{
	/* These are interrupts we'll toggle with the ring mask register */
	uint32_t gt_interrupts[] = {
		GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3703 3704 3705
			GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
			GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
			GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3706
		GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3707 3708 3709
			GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
			GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
			GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3710
		0,
3711 3712
		GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
			GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3713 3714
		};

3715 3716 3717
	if (HAS_L3_DPF(dev_priv))
		gt_interrupts[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;

3718
	dev_priv->pm_irq_mask = 0xffffffff;
3719 3720
	GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
	GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3721 3722 3723 3724 3725
	/*
	 * RPS interrupts will get enabled/disabled on demand when RPS itself
	 * is enabled/disabled.
	 */
	GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
3726
	GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3727 3728 3729 3730
}

static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
{
3731 3732
	uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
	uint32_t de_pipe_enables;
3733 3734
	u32 de_port_masked = GEN8_AUX_CHANNEL_A;
	u32 de_port_enables;
3735
	u32 de_misc_masked = GEN8_DE_MISC_GSE;
3736
	enum pipe pipe;
3737

3738
	if (INTEL_INFO(dev_priv)->gen >= 9) {
3739 3740
		de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
				  GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3741 3742
		de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
				  GEN9_AUX_CHANNEL_D;
S
Shashank Sharma 已提交
3743
		if (IS_BROXTON(dev_priv))
3744 3745
			de_port_masked |= BXT_DE_PORT_GMBUS;
	} else {
3746 3747
		de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
				  GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3748
	}
3749 3750 3751 3752

	de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
					   GEN8_PIPE_FIFO_UNDERRUN;

3753
	de_port_enables = de_port_masked;
3754 3755 3756
	if (IS_BROXTON(dev_priv))
		de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
	else if (IS_BROADWELL(dev_priv))
3757 3758
		de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;

3759 3760 3761
	dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
	dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
	dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3762

3763
	for_each_pipe(dev_priv, pipe)
3764
		if (intel_display_power_is_enabled(dev_priv,
3765 3766 3767 3768
				POWER_DOMAIN_PIPE(pipe)))
			GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
					  dev_priv->de_irq_mask[pipe],
					  de_pipe_enables);
3769

3770
	GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3771
	GEN5_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
3772 3773 3774 3775 3776 3777
}

static int gen8_irq_postinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

3778 3779
	if (HAS_PCH_SPLIT(dev))
		ibx_irq_pre_postinstall(dev);
P
Paulo Zanoni 已提交
3780

3781 3782 3783
	gen8_gt_irq_postinstall(dev_priv);
	gen8_de_irq_postinstall(dev_priv);

3784 3785
	if (HAS_PCH_SPLIT(dev))
		ibx_irq_postinstall(dev);
3786

3787
	I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3788 3789 3790 3791 3792
	POSTING_READ(GEN8_MASTER_IRQ);

	return 0;
}

3793 3794 3795 3796 3797 3798
static int cherryview_irq_postinstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	gen8_gt_irq_postinstall(dev_priv);

3799
	spin_lock_irq(&dev_priv->irq_lock);
3800 3801
	if (dev_priv->display_irqs_enabled)
		vlv_display_irq_postinstall(dev_priv);
3802 3803
	spin_unlock_irq(&dev_priv->irq_lock);

3804
	I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3805 3806 3807 3808 3809
	POSTING_READ(GEN8_MASTER_IRQ);

	return 0;
}

3810 3811 3812 3813 3814 3815 3816
static void gen8_irq_uninstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (!dev_priv)
		return;

P
Paulo Zanoni 已提交
3817
	gen8_irq_reset(dev);
3818 3819
}

J
Jesse Barnes 已提交
3820 3821
static void valleyview_irq_uninstall(struct drm_device *dev)
{
3822
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
3823 3824 3825 3826

	if (!dev_priv)
		return;

3827
	I915_WRITE(VLV_MASTER_IER, 0);
3828
	POSTING_READ(VLV_MASTER_IER);
3829

3830 3831
	gen5_gt_irq_reset(dev);

J
Jesse Barnes 已提交
3832
	I915_WRITE(HWSTAM, 0xffffffff);
3833

3834
	spin_lock_irq(&dev_priv->irq_lock);
3835 3836
	if (dev_priv->display_irqs_enabled)
		vlv_display_irq_reset(dev_priv);
3837
	spin_unlock_irq(&dev_priv->irq_lock);
J
Jesse Barnes 已提交
3838 3839
}

3840 3841 3842 3843 3844 3845 3846 3847 3848 3849
static void cherryview_irq_uninstall(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (!dev_priv)
		return;

	I915_WRITE(GEN8_MASTER_IRQ, 0);
	POSTING_READ(GEN8_MASTER_IRQ);

3850
	gen8_gt_irq_reset(dev_priv);
3851

3852
	GEN5_IRQ_RESET(GEN8_PCU_);
3853

3854
	spin_lock_irq(&dev_priv->irq_lock);
3855 3856
	if (dev_priv->display_irqs_enabled)
		vlv_display_irq_reset(dev_priv);
3857
	spin_unlock_irq(&dev_priv->irq_lock);
3858 3859
}

3860
static void ironlake_irq_uninstall(struct drm_device *dev)
3861
{
3862
	struct drm_i915_private *dev_priv = dev->dev_private;
3863 3864 3865 3866

	if (!dev_priv)
		return;

P
Paulo Zanoni 已提交
3867
	ironlake_irq_reset(dev);
3868 3869
}

3870
static void i8xx_irq_preinstall(struct drm_device * dev)
L
Linus Torvalds 已提交
3871
{
3872
	struct drm_i915_private *dev_priv = dev->dev_private;
3873
	int pipe;
3874

3875
	for_each_pipe(dev_priv, pipe)
3876
		I915_WRITE(PIPESTAT(pipe), 0);
3877 3878 3879
	I915_WRITE16(IMR, 0xffff);
	I915_WRITE16(IER, 0x0);
	POSTING_READ16(IER);
C
Chris Wilson 已提交
3880 3881 3882 3883
}

static int i8xx_irq_postinstall(struct drm_device *dev)
{
3884
	struct drm_i915_private *dev_priv = dev->dev_private;
C
Chris Wilson 已提交
3885 3886 3887 3888 3889 3890 3891 3892 3893

	I915_WRITE16(EMR,
		     ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));

	/* Unmask the interrupts that we always want on. */
	dev_priv->irq_mask =
		~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3894
		  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
C
Chris Wilson 已提交
3895 3896 3897 3898 3899 3900 3901 3902
	I915_WRITE16(IMR, dev_priv->irq_mask);

	I915_WRITE16(IER,
		     I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		     I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		     I915_USER_INTERRUPT);
	POSTING_READ16(IER);

3903 3904
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
3905
	spin_lock_irq(&dev_priv->irq_lock);
3906 3907
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3908
	spin_unlock_irq(&dev_priv->irq_lock);
3909

C
Chris Wilson 已提交
3910 3911 3912
	return 0;
}

3913 3914 3915 3916 3917 3918 3919 3920 3921 3922 3923 3924 3925 3926 3927 3928 3929 3930 3931 3932 3933 3934 3935 3936 3937 3938 3939 3940 3941 3942 3943
/*
 * Returns true when a page flip has completed.
 */
static bool i8xx_handle_vblank(struct drm_i915_private *dev_priv,
			       int plane, int pipe, u32 iir)
{
	u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);

	if (!intel_pipe_handle_vblank(dev_priv, pipe))
		return false;

	if ((iir & flip_pending) == 0)
		goto check_page_flip;

	/* We detect FlipDone by looking for the change in PendingFlip from '1'
	 * to '0' on the following vblank, i.e. IIR has the Pendingflip
	 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
	 * the flip is completed (no longer pending). Since this doesn't raise
	 * an interrupt per se, we watch for the change at vblank.
	 */
	if (I915_READ16(ISR) & flip_pending)
		goto check_page_flip;

	intel_finish_page_flip_cs(dev_priv, pipe);
	return true;

check_page_flip:
	intel_check_page_flip(dev_priv, pipe);
	return false;
}

3944
static irqreturn_t i8xx_irq_handler(int irq, void *arg)
C
Chris Wilson 已提交
3945
{
3946
	struct drm_device *dev = arg;
3947
	struct drm_i915_private *dev_priv = dev->dev_private;
C
Chris Wilson 已提交
3948 3949 3950 3951 3952 3953
	u16 iir, new_iir;
	u32 pipe_stats[2];
	int pipe;
	u16 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3954
	irqreturn_t ret;
C
Chris Wilson 已提交
3955

3956 3957 3958
	if (!intel_irqs_enabled(dev_priv))
		return IRQ_NONE;

3959 3960 3961 3962
	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
	disable_rpm_wakeref_asserts(dev_priv);

	ret = IRQ_NONE;
C
Chris Wilson 已提交
3963 3964
	iir = I915_READ16(IIR);
	if (iir == 0)
3965
		goto out;
C
Chris Wilson 已提交
3966 3967 3968 3969 3970 3971 3972

	while (iir & ~flip_mask) {
		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
3973
		spin_lock(&dev_priv->irq_lock);
C
Chris Wilson 已提交
3974
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3975
			DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
C
Chris Wilson 已提交
3976

3977
		for_each_pipe(dev_priv, pipe) {
3978
			i915_reg_t reg = PIPESTAT(pipe);
C
Chris Wilson 已提交
3979 3980 3981 3982 3983
			pipe_stats[pipe] = I915_READ(reg);

			/*
			 * Clear the PIPE*STAT regs before the IIR
			 */
3984
			if (pipe_stats[pipe] & 0x8000ffff)
C
Chris Wilson 已提交
3985 3986
				I915_WRITE(reg, pipe_stats[pipe]);
		}
3987
		spin_unlock(&dev_priv->irq_lock);
C
Chris Wilson 已提交
3988 3989 3990 3991 3992

		I915_WRITE16(IIR, iir & ~flip_mask);
		new_iir = I915_READ16(IIR); /* Flush posted writes */

		if (iir & I915_USER_INTERRUPT)
3993
			notify_ring(&dev_priv->engine[RCS]);
C
Chris Wilson 已提交
3994

3995
		for_each_pipe(dev_priv, pipe) {
3996 3997 3998 3999 4000 4001 4002
			int plane = pipe;
			if (HAS_FBC(dev_priv))
				plane = !plane;

			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
			    i8xx_handle_vblank(dev_priv, plane, pipe, iir))
				flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
C
Chris Wilson 已提交
4003

4004
			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4005
				i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4006

4007 4008 4009
			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
				intel_cpu_fifo_underrun_irq_handler(dev_priv,
								    pipe);
4010
		}
C
Chris Wilson 已提交
4011 4012 4013

		iir = new_iir;
	}
4014 4015 4016 4017
	ret = IRQ_HANDLED;

out:
	enable_rpm_wakeref_asserts(dev_priv);
C
Chris Wilson 已提交
4018

4019
	return ret;
C
Chris Wilson 已提交
4020 4021 4022 4023
}

static void i8xx_irq_uninstall(struct drm_device * dev)
{
4024
	struct drm_i915_private *dev_priv = dev->dev_private;
C
Chris Wilson 已提交
4025 4026
	int pipe;

4027
	for_each_pipe(dev_priv, pipe) {
C
Chris Wilson 已提交
4028 4029 4030 4031 4032 4033 4034 4035 4036
		/* Clear enable bits; then clear status bits */
		I915_WRITE(PIPESTAT(pipe), 0);
		I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
	}
	I915_WRITE16(IMR, 0xffff);
	I915_WRITE16(IER, 0x0);
	I915_WRITE16(IIR, I915_READ16(IIR));
}

4037 4038
static void i915_irq_preinstall(struct drm_device * dev)
{
4039
	struct drm_i915_private *dev_priv = dev->dev_private;
4040 4041 4042
	int pipe;

	if (I915_HAS_HOTPLUG(dev)) {
4043
		i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4044 4045 4046
		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	}

4047
	I915_WRITE16(HWSTAM, 0xeffe);
4048
	for_each_pipe(dev_priv, pipe)
4049 4050 4051 4052 4053 4054 4055 4056
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);
	POSTING_READ(IER);
}

static int i915_irq_postinstall(struct drm_device *dev)
{
4057
	struct drm_i915_private *dev_priv = dev->dev_private;
4058
	u32 enable_mask;
4059

4060 4061 4062 4063 4064 4065 4066 4067
	I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));

	/* Unmask the interrupts that we always want on. */
	dev_priv->irq_mask =
		~(I915_ASLE_INTERRUPT |
		  I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		  I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4068
		  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4069 4070 4071 4072 4073 4074 4075

	enable_mask =
		I915_ASLE_INTERRUPT |
		I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
		I915_USER_INTERRUPT;

4076
	if (I915_HAS_HOTPLUG(dev)) {
4077
		i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4078 4079
		POSTING_READ(PORT_HOTPLUG_EN);

4080 4081 4082 4083 4084 4085 4086 4087 4088 4089
		/* Enable in IER... */
		enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
		/* and unmask in IMR */
		dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
	}

	I915_WRITE(IMR, dev_priv->irq_mask);
	I915_WRITE(IER, enable_mask);
	POSTING_READ(IER);

4090
	i915_enable_asle_pipestat(dev_priv);
4091

4092 4093
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
4094
	spin_lock_irq(&dev_priv->irq_lock);
4095 4096
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4097
	spin_unlock_irq(&dev_priv->irq_lock);
4098

4099 4100 4101
	return 0;
}

4102 4103 4104 4105 4106 4107 4108 4109 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 4120 4121 4122 4123 4124 4125 4126 4127 4128 4129 4130 4131 4132
/*
 * Returns true when a page flip has completed.
 */
static bool i915_handle_vblank(struct drm_i915_private *dev_priv,
			       int plane, int pipe, u32 iir)
{
	u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);

	if (!intel_pipe_handle_vblank(dev_priv, pipe))
		return false;

	if ((iir & flip_pending) == 0)
		goto check_page_flip;

	/* We detect FlipDone by looking for the change in PendingFlip from '1'
	 * to '0' on the following vblank, i.e. IIR has the Pendingflip
	 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
	 * the flip is completed (no longer pending). Since this doesn't raise
	 * an interrupt per se, we watch for the change at vblank.
	 */
	if (I915_READ(ISR) & flip_pending)
		goto check_page_flip;

	intel_finish_page_flip_cs(dev_priv, pipe);
	return true;

check_page_flip:
	intel_check_page_flip(dev_priv, pipe);
	return false;
}

4133
static irqreturn_t i915_irq_handler(int irq, void *arg)
4134
{
4135
	struct drm_device *dev = arg;
4136
	struct drm_i915_private *dev_priv = dev->dev_private;
4137
	u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
4138 4139 4140 4141
	u32 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
	int pipe, ret = IRQ_NONE;
4142

4143 4144 4145
	if (!intel_irqs_enabled(dev_priv))
		return IRQ_NONE;

4146 4147 4148
	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
	disable_rpm_wakeref_asserts(dev_priv);

4149
	iir = I915_READ(IIR);
4150 4151
	do {
		bool irq_received = (iir & ~flip_mask) != 0;
4152
		bool blc_event = false;
4153 4154 4155 4156 4157 4158

		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
4159
		spin_lock(&dev_priv->irq_lock);
4160
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4161
			DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4162

4163
		for_each_pipe(dev_priv, pipe) {
4164
			i915_reg_t reg = PIPESTAT(pipe);
4165 4166
			pipe_stats[pipe] = I915_READ(reg);

4167
			/* Clear the PIPE*STAT regs before the IIR */
4168 4169
			if (pipe_stats[pipe] & 0x8000ffff) {
				I915_WRITE(reg, pipe_stats[pipe]);
4170
				irq_received = true;
4171 4172
			}
		}
4173
		spin_unlock(&dev_priv->irq_lock);
4174 4175 4176 4177 4178

		if (!irq_received)
			break;

		/* Consume port.  Then clear IIR or we'll miss events */
4179
		if (I915_HAS_HOTPLUG(dev_priv) &&
4180 4181 4182
		    iir & I915_DISPLAY_PORT_INTERRUPT) {
			u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
			if (hotplug_status)
4183
				i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4184
		}
4185

4186
		I915_WRITE(IIR, iir & ~flip_mask);
4187 4188 4189
		new_iir = I915_READ(IIR); /* Flush posted writes */

		if (iir & I915_USER_INTERRUPT)
4190
			notify_ring(&dev_priv->engine[RCS]);
4191

4192
		for_each_pipe(dev_priv, pipe) {
4193 4194 4195 4196 4197 4198 4199
			int plane = pipe;
			if (HAS_FBC(dev_priv))
				plane = !plane;

			if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
			    i915_handle_vblank(dev_priv, plane, pipe, iir))
				flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4200 4201 4202

			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
				blc_event = true;
4203 4204

			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4205
				i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4206

4207 4208 4209
			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
				intel_cpu_fifo_underrun_irq_handler(dev_priv,
								    pipe);
4210 4211 4212
		}

		if (blc_event || (iir & I915_ASLE_INTERRUPT))
4213
			intel_opregion_asle_intr(dev_priv);
4214 4215 4216 4217 4218 4219 4220 4221 4222 4223 4224 4225 4226 4227 4228 4229

		/* With MSI, interrupts are only generated when iir
		 * transitions from zero to nonzero.  If another bit got
		 * set while we were handling the existing iir bits, then
		 * we would never get another interrupt.
		 *
		 * This is fine on non-MSI as well, as if we hit this path
		 * we avoid exiting the interrupt handler only to generate
		 * another one.
		 *
		 * Note that for MSI this could cause a stray interrupt report
		 * if an interrupt landed in the time between writing IIR and
		 * the posting read.  This should be rare enough to never
		 * trigger the 99% of 100,000 interrupts test for disabling
		 * stray interrupts.
		 */
4230
		ret = IRQ_HANDLED;
4231
		iir = new_iir;
4232
	} while (iir & ~flip_mask);
4233

4234 4235
	enable_rpm_wakeref_asserts(dev_priv);

4236 4237 4238 4239 4240
	return ret;
}

static void i915_irq_uninstall(struct drm_device * dev)
{
4241
	struct drm_i915_private *dev_priv = dev->dev_private;
4242 4243 4244
	int pipe;

	if (I915_HAS_HOTPLUG(dev)) {
4245
		i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4246 4247 4248
		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
	}

4249
	I915_WRITE16(HWSTAM, 0xffff);
4250
	for_each_pipe(dev_priv, pipe) {
4251
		/* Clear enable bits; then clear status bits */
4252
		I915_WRITE(PIPESTAT(pipe), 0);
4253 4254
		I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
	}
4255 4256 4257 4258 4259 4260 4261 4262
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);

	I915_WRITE(IIR, I915_READ(IIR));
}

static void i965_irq_preinstall(struct drm_device * dev)
{
4263
	struct drm_i915_private *dev_priv = dev->dev_private;
4264 4265
	int pipe;

4266
	i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4267
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4268 4269

	I915_WRITE(HWSTAM, 0xeffe);
4270
	for_each_pipe(dev_priv, pipe)
4271 4272 4273 4274 4275 4276 4277 4278
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);
	POSTING_READ(IER);
}

static int i965_irq_postinstall(struct drm_device *dev)
{
4279
	struct drm_i915_private *dev_priv = dev->dev_private;
4280
	u32 enable_mask;
4281 4282 4283
	u32 error_mask;

	/* Unmask the interrupts that we always want on. */
4284
	dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4285
			       I915_DISPLAY_PORT_INTERRUPT |
4286 4287 4288 4289 4290 4291 4292
			       I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
			       I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
			       I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
			       I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
			       I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);

	enable_mask = ~dev_priv->irq_mask;
4293 4294
	enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
			 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4295 4296
	enable_mask |= I915_USER_INTERRUPT;

4297
	if (IS_G4X(dev_priv))
4298
		enable_mask |= I915_BSD_USER_INTERRUPT;
4299

4300 4301
	/* Interrupt setup is already guaranteed to be single-threaded, this is
	 * just to make the assert_spin_locked check happy. */
4302
	spin_lock_irq(&dev_priv->irq_lock);
4303 4304 4305
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4306
	spin_unlock_irq(&dev_priv->irq_lock);
4307 4308 4309 4310 4311

	/*
	 * Enable some error detection, note the instruction error mask
	 * bit is reserved, so we leave it masked.
	 */
4312
	if (IS_G4X(dev_priv)) {
4313 4314 4315 4316 4317 4318 4319 4320 4321 4322 4323 4324 4325 4326
		error_mask = ~(GM45_ERROR_PAGE_TABLE |
			       GM45_ERROR_MEM_PRIV |
			       GM45_ERROR_CP_PRIV |
			       I915_ERROR_MEMORY_REFRESH);
	} else {
		error_mask = ~(I915_ERROR_PAGE_TABLE |
			       I915_ERROR_MEMORY_REFRESH);
	}
	I915_WRITE(EMR, error_mask);

	I915_WRITE(IMR, dev_priv->irq_mask);
	I915_WRITE(IER, enable_mask);
	POSTING_READ(IER);

4327
	i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4328 4329
	POSTING_READ(PORT_HOTPLUG_EN);

4330
	i915_enable_asle_pipestat(dev_priv);
4331 4332 4333 4334

	return 0;
}

4335
static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
4336 4337 4338
{
	u32 hotplug_en;

4339 4340
	assert_spin_locked(&dev_priv->irq_lock);

4341 4342
	/* Note HDMI and DP share hotplug bits */
	/* enable bits are the same for all generations */
4343
	hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
4344 4345 4346 4347
	/* Programming the CRT detection parameters tends
	   to generate a spurious hotplug event about three
	   seconds later.  So just do it once.
	*/
4348
	if (IS_G4X(dev_priv))
4349 4350 4351 4352
		hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
	hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;

	/* Ignore TV since it's buggy */
4353
	i915_hotplug_interrupt_update_locked(dev_priv,
4354 4355 4356 4357
					     HOTPLUG_INT_EN_MASK |
					     CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
					     CRT_HOTPLUG_ACTIVATION_PERIOD_64,
					     hotplug_en);
4358 4359
}

4360
static irqreturn_t i965_irq_handler(int irq, void *arg)
4361
{
4362
	struct drm_device *dev = arg;
4363
	struct drm_i915_private *dev_priv = dev->dev_private;
4364 4365 4366
	u32 iir, new_iir;
	u32 pipe_stats[I915_MAX_PIPES];
	int ret = IRQ_NONE, pipe;
4367 4368 4369
	u32 flip_mask =
		I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
		I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4370

4371 4372 4373
	if (!intel_irqs_enabled(dev_priv))
		return IRQ_NONE;

4374 4375 4376
	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
	disable_rpm_wakeref_asserts(dev_priv);

4377 4378 4379
	iir = I915_READ(IIR);

	for (;;) {
4380
		bool irq_received = (iir & ~flip_mask) != 0;
4381 4382
		bool blc_event = false;

4383 4384 4385 4386 4387
		/* Can't rely on pipestat interrupt bit in iir as it might
		 * have been cleared after the pipestat interrupt was received.
		 * It doesn't set the bit in iir again, but it still produces
		 * interrupts (for non-MSI).
		 */
4388
		spin_lock(&dev_priv->irq_lock);
4389
		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4390
			DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4391

4392
		for_each_pipe(dev_priv, pipe) {
4393
			i915_reg_t reg = PIPESTAT(pipe);
4394 4395 4396 4397 4398 4399 4400
			pipe_stats[pipe] = I915_READ(reg);

			/*
			 * Clear the PIPE*STAT regs before the IIR
			 */
			if (pipe_stats[pipe] & 0x8000ffff) {
				I915_WRITE(reg, pipe_stats[pipe]);
4401
				irq_received = true;
4402 4403
			}
		}
4404
		spin_unlock(&dev_priv->irq_lock);
4405 4406 4407 4408 4409 4410 4411

		if (!irq_received)
			break;

		ret = IRQ_HANDLED;

		/* Consume port.  Then clear IIR or we'll miss events */
4412 4413 4414
		if (iir & I915_DISPLAY_PORT_INTERRUPT) {
			u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
			if (hotplug_status)
4415
				i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4416
		}
4417

4418
		I915_WRITE(IIR, iir & ~flip_mask);
4419 4420 4421
		new_iir = I915_READ(IIR); /* Flush posted writes */

		if (iir & I915_USER_INTERRUPT)
4422
			notify_ring(&dev_priv->engine[RCS]);
4423
		if (iir & I915_BSD_USER_INTERRUPT)
4424
			notify_ring(&dev_priv->engine[VCS]);
4425

4426
		for_each_pipe(dev_priv, pipe) {
4427 4428 4429
			if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
			    i915_handle_vblank(dev_priv, pipe, pipe, iir))
				flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4430 4431 4432

			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
				blc_event = true;
4433 4434

			if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4435
				i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4436

4437 4438
			if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
				intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4439
		}
4440 4441

		if (blc_event || (iir & I915_ASLE_INTERRUPT))
4442
			intel_opregion_asle_intr(dev_priv);
4443

4444
		if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4445
			gmbus_irq_handler(dev_priv);
4446

4447 4448 4449 4450 4451 4452 4453 4454 4455 4456 4457 4458 4459 4460 4461 4462 4463 4464
		/* With MSI, interrupts are only generated when iir
		 * transitions from zero to nonzero.  If another bit got
		 * set while we were handling the existing iir bits, then
		 * we would never get another interrupt.
		 *
		 * This is fine on non-MSI as well, as if we hit this path
		 * we avoid exiting the interrupt handler only to generate
		 * another one.
		 *
		 * Note that for MSI this could cause a stray interrupt report
		 * if an interrupt landed in the time between writing IIR and
		 * the posting read.  This should be rare enough to never
		 * trigger the 99% of 100,000 interrupts test for disabling
		 * stray interrupts.
		 */
		iir = new_iir;
	}

4465 4466
	enable_rpm_wakeref_asserts(dev_priv);

4467 4468 4469 4470 4471
	return ret;
}

static void i965_irq_uninstall(struct drm_device * dev)
{
4472
	struct drm_i915_private *dev_priv = dev->dev_private;
4473 4474 4475 4476 4477
	int pipe;

	if (!dev_priv)
		return;

4478
	i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4479
	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4480 4481

	I915_WRITE(HWSTAM, 0xffffffff);
4482
	for_each_pipe(dev_priv, pipe)
4483 4484 4485 4486
		I915_WRITE(PIPESTAT(pipe), 0);
	I915_WRITE(IMR, 0xffffffff);
	I915_WRITE(IER, 0x0);

4487
	for_each_pipe(dev_priv, pipe)
4488 4489 4490 4491 4492
		I915_WRITE(PIPESTAT(pipe),
			   I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
	I915_WRITE(IIR, I915_READ(IIR));
}

4493 4494 4495 4496 4497 4498 4499
/**
 * intel_irq_init - initializes irq support
 * @dev_priv: i915 device instance
 *
 * This function initializes all the irq support including work items, timers
 * and all the vtables. It does not setup the interrupt itself though.
 */
4500
void intel_irq_init(struct drm_i915_private *dev_priv)
4501
{
4502
	struct drm_device *dev = dev_priv->dev;
4503

4504 4505
	intel_hpd_init_work(dev_priv);

4506
	INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4507
	INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4508

4509
	/* Let's track the enabled rps events */
4510
	if (IS_VALLEYVIEW(dev_priv))
4511
		/* WaGsvRC0ResidencyMethod:vlv */
4512
		dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
4513 4514
	else
		dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4515

4516 4517 4518 4519 4520 4521 4522 4523 4524 4525 4526 4527 4528 4529
	dev_priv->rps.pm_intr_keep = 0;

	/*
	 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
	 * if GEN6_PM_UP_EI_EXPIRED is masked.
	 *
	 * TODO: verify if this can be reproduced on VLV,CHV.
	 */
	if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
		dev_priv->rps.pm_intr_keep |= GEN6_PM_RP_UP_EI_EXPIRED;

	if (INTEL_INFO(dev_priv)->gen >= 8)
		dev_priv->rps.pm_intr_keep |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;

4530 4531
	INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
			  i915_hangcheck_elapsed);
4532

4533
	if (IS_GEN2(dev_priv)) {
4534 4535
		dev->max_vblank_count = 0;
		dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4536
	} else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4537
		dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4538
		dev->driver->get_vblank_counter = g4x_get_vblank_counter;
4539 4540 4541
	} else {
		dev->driver->get_vblank_counter = i915_get_vblank_counter;
		dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4542 4543
	}

4544 4545 4546 4547 4548
	/*
	 * Opt out of the vblank disable timer on everything except gen2.
	 * Gen2 doesn't have a hardware frame counter and so depends on
	 * vblank interrupts to produce sane vblank seuquence numbers.
	 */
4549
	if (!IS_GEN2(dev_priv))
4550 4551
		dev->vblank_disable_immediate = true;

4552 4553
	dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
	dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4554

4555
	if (IS_CHERRYVIEW(dev_priv)) {
4556 4557 4558 4559 4560 4561 4562
		dev->driver->irq_handler = cherryview_irq_handler;
		dev->driver->irq_preinstall = cherryview_irq_preinstall;
		dev->driver->irq_postinstall = cherryview_irq_postinstall;
		dev->driver->irq_uninstall = cherryview_irq_uninstall;
		dev->driver->enable_vblank = valleyview_enable_vblank;
		dev->driver->disable_vblank = valleyview_disable_vblank;
		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4563
	} else if (IS_VALLEYVIEW(dev_priv)) {
J
Jesse Barnes 已提交
4564 4565 4566 4567 4568 4569
		dev->driver->irq_handler = valleyview_irq_handler;
		dev->driver->irq_preinstall = valleyview_irq_preinstall;
		dev->driver->irq_postinstall = valleyview_irq_postinstall;
		dev->driver->irq_uninstall = valleyview_irq_uninstall;
		dev->driver->enable_vblank = valleyview_enable_vblank;
		dev->driver->disable_vblank = valleyview_disable_vblank;
4570
		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4571
	} else if (INTEL_INFO(dev_priv)->gen >= 8) {
4572
		dev->driver->irq_handler = gen8_irq_handler;
4573
		dev->driver->irq_preinstall = gen8_irq_reset;
4574 4575 4576 4577
		dev->driver->irq_postinstall = gen8_irq_postinstall;
		dev->driver->irq_uninstall = gen8_irq_uninstall;
		dev->driver->enable_vblank = gen8_enable_vblank;
		dev->driver->disable_vblank = gen8_disable_vblank;
4578
		if (IS_BROXTON(dev))
4579
			dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4580 4581 4582
		else if (HAS_PCH_SPT(dev))
			dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
		else
4583
			dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4584 4585
	} else if (HAS_PCH_SPLIT(dev)) {
		dev->driver->irq_handler = ironlake_irq_handler;
4586
		dev->driver->irq_preinstall = ironlake_irq_reset;
4587 4588 4589 4590
		dev->driver->irq_postinstall = ironlake_irq_postinstall;
		dev->driver->irq_uninstall = ironlake_irq_uninstall;
		dev->driver->enable_vblank = ironlake_enable_vblank;
		dev->driver->disable_vblank = ironlake_disable_vblank;
4591
		dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4592
	} else {
4593
		if (IS_GEN2(dev_priv)) {
C
Chris Wilson 已提交
4594 4595 4596 4597
			dev->driver->irq_preinstall = i8xx_irq_preinstall;
			dev->driver->irq_postinstall = i8xx_irq_postinstall;
			dev->driver->irq_handler = i8xx_irq_handler;
			dev->driver->irq_uninstall = i8xx_irq_uninstall;
4598
		} else if (IS_GEN3(dev_priv)) {
4599 4600 4601 4602
			dev->driver->irq_preinstall = i915_irq_preinstall;
			dev->driver->irq_postinstall = i915_irq_postinstall;
			dev->driver->irq_uninstall = i915_irq_uninstall;
			dev->driver->irq_handler = i915_irq_handler;
C
Chris Wilson 已提交
4603
		} else {
4604 4605 4606 4607
			dev->driver->irq_preinstall = i965_irq_preinstall;
			dev->driver->irq_postinstall = i965_irq_postinstall;
			dev->driver->irq_uninstall = i965_irq_uninstall;
			dev->driver->irq_handler = i965_irq_handler;
C
Chris Wilson 已提交
4608
		}
4609 4610
		if (I915_HAS_HOTPLUG(dev_priv))
			dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4611 4612 4613 4614
		dev->driver->enable_vblank = i915_enable_vblank;
		dev->driver->disable_vblank = i915_disable_vblank;
	}
}
4615

4616 4617 4618 4619 4620 4621 4622 4623 4624 4625 4626
/**
 * intel_irq_install - enables the hardware interrupt
 * @dev_priv: i915 device instance
 *
 * This function enables the hardware interrupt handling, but leaves the hotplug
 * handling still disabled. It is called after intel_irq_init().
 *
 * In the driver load and resume code we need working interrupts in a few places
 * but don't want to deal with the hassle of concurrent probe and hotplug
 * workers. Hence the split into this two-stage approach.
 */
4627 4628 4629 4630 4631 4632 4633 4634 4635 4636 4637 4638
int intel_irq_install(struct drm_i915_private *dev_priv)
{
	/*
	 * We enable some interrupt sources in our postinstall hooks, so mark
	 * interrupts as enabled _before_ actually enabling them to avoid
	 * special cases in our ordering checks.
	 */
	dev_priv->pm.irqs_enabled = true;

	return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
}

4639 4640 4641 4642 4643 4644 4645
/**
 * intel_irq_uninstall - finilizes all irq handling
 * @dev_priv: i915 device instance
 *
 * This stops interrupt and hotplug handling and unregisters and frees all
 * resources acquired in the init functions.
 */
4646 4647 4648 4649 4650 4651 4652
void intel_irq_uninstall(struct drm_i915_private *dev_priv)
{
	drm_irq_uninstall(dev_priv->dev);
	intel_hpd_cancel_work(dev_priv);
	dev_priv->pm.irqs_enabled = false;
}

4653 4654 4655 4656 4657 4658 4659
/**
 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
 * @dev_priv: i915 device instance
 *
 * This function is used to disable interrupts at runtime, both in the runtime
 * pm and the system suspend/resume code.
 */
4660
void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4661
{
4662
	dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
4663
	dev_priv->pm.irqs_enabled = false;
4664
	synchronize_irq(dev_priv->dev->irq);
4665 4666
}

4667 4668 4669 4670 4671 4672 4673
/**
 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
 * @dev_priv: i915 device instance
 *
 * This function is used to enable interrupts at runtime, both in the runtime
 * pm and the system suspend/resume code.
 */
4674
void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4675
{
4676
	dev_priv->pm.irqs_enabled = true;
4677 4678
	dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
	dev_priv->dev->driver->irq_postinstall(dev_priv->dev);
4679
}