spi-imx.c 45.5 KB
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// SPDX-License-Identifier: GPL-2.0+
// Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
// Copyright (C) 2008 Juergen Beisert
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#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/delay.h>
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#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
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#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/module.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>
#include <linux/types.h>
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#include <linux/of.h>
#include <linux/of_device.h>
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#include <linux/property.h>
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#include <linux/platform_data/dma-imx.h>
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#define DRIVER_NAME "spi_imx"

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static bool use_dma = true;
module_param(use_dma, bool, 0644);
MODULE_PARM_DESC(use_dma, "Enable usage of DMA when available (default)");

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#define MXC_RPM_TIMEOUT		2000 /* 2000ms */

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#define MXC_CSPIRXDATA		0x00
#define MXC_CSPITXDATA		0x04
#define MXC_CSPICTRL		0x08
#define MXC_CSPIINT		0x0c
#define MXC_RESET		0x1c

/* generic defines to abstract from the different register layouts */
#define MXC_INT_RR	(1 << 0) /* Receive data ready interrupt */
#define MXC_INT_TE	(1 << 1) /* Transmit FIFO empty interrupt */
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#define MXC_INT_RDR	BIT(4) /* Receive date threshold interrupt */
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/* The maximum bytes that a sdma BD can transfer. */
#define MAX_SDMA_BD_BYTES (1 << 15)
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#define MX51_ECSPI_CTRL_MAX_BURST	512
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/* The maximum bytes that IMX53_ECSPI can transfer in slave mode.*/
#define MX53_MAX_TRANSFER_BYTES		512
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enum spi_imx_devtype {
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	IMX1_CSPI,
	IMX21_CSPI,
	IMX27_CSPI,
	IMX31_CSPI,
	IMX35_CSPI,	/* CSPI on all i.mx except above */
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	IMX51_ECSPI,	/* ECSPI on i.mx51 */
	IMX53_ECSPI,	/* ECSPI on i.mx53 and later */
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};

struct spi_imx_data;

struct spi_imx_devtype_data {
	void (*intctrl)(struct spi_imx_data *, int);
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	int (*prepare_message)(struct spi_imx_data *, struct spi_message *);
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	int (*prepare_transfer)(struct spi_imx_data *, struct spi_device *);
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	void (*trigger)(struct spi_imx_data *);
	int (*rx_available)(struct spi_imx_data *);
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	void (*reset)(struct spi_imx_data *);
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	void (*setup_wml)(struct spi_imx_data *);
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	void (*disable)(struct spi_imx_data *);
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	void (*disable_dma)(struct spi_imx_data *);
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	bool has_dmamode;
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	bool has_slavemode;
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	unsigned int fifo_size;
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	bool dynamic_burst;
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	enum spi_imx_devtype devtype;
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};

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struct spi_imx_data {
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	struct spi_bitbang bitbang;
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	struct device *dev;
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	struct completion xfer_done;
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	void __iomem *base;
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	unsigned long base_phys;

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	struct clk *clk_per;
	struct clk *clk_ipg;
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	unsigned long spi_clk;
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	unsigned int spi_bus_clk;
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	unsigned int bits_per_word;
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	unsigned int spi_drctl;
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	unsigned int count, remainder;
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	void (*tx)(struct spi_imx_data *);
	void (*rx)(struct spi_imx_data *);
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	void *rx_buf;
	const void *tx_buf;
	unsigned int txfifo; /* number of words pushed in tx FIFO */
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	unsigned int dynamic_burst;
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	/* Slave mode */
	bool slave_mode;
	bool slave_aborted;
	unsigned int slave_burst;

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	/* DMA */
	bool usedma;
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	u32 wml;
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	struct completion dma_rx_completion;
	struct completion dma_tx_completion;

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	const struct spi_imx_devtype_data *devtype_data;
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};

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static inline int is_imx27_cspi(struct spi_imx_data *d)
{
	return d->devtype_data->devtype == IMX27_CSPI;
}

static inline int is_imx35_cspi(struct spi_imx_data *d)
{
	return d->devtype_data->devtype == IMX35_CSPI;
}

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static inline int is_imx51_ecspi(struct spi_imx_data *d)
{
	return d->devtype_data->devtype == IMX51_ECSPI;
}

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static inline int is_imx53_ecspi(struct spi_imx_data *d)
{
	return d->devtype_data->devtype == IMX53_ECSPI;
}

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#define MXC_SPI_BUF_RX(type)						\
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static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx)		\
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{									\
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	unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);	\
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									\
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	if (spi_imx->rx_buf) {						\
		*(type *)spi_imx->rx_buf = val;				\
		spi_imx->rx_buf += sizeof(type);			\
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	}								\
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									\
	spi_imx->remainder -= sizeof(type);				\
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}

#define MXC_SPI_BUF_TX(type)						\
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static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx)		\
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{									\
	type val = 0;							\
									\
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	if (spi_imx->tx_buf) {						\
		val = *(type *)spi_imx->tx_buf;				\
		spi_imx->tx_buf += sizeof(type);			\
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	}								\
									\
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	spi_imx->count -= sizeof(type);					\
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									\
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	writel(val, spi_imx->base + MXC_CSPITXDATA);			\
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}

MXC_SPI_BUF_RX(u8)
MXC_SPI_BUF_TX(u8)
MXC_SPI_BUF_RX(u16)
MXC_SPI_BUF_TX(u16)
MXC_SPI_BUF_RX(u32)
MXC_SPI_BUF_TX(u32)

/* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
 * (which is currently not the case in this driver)
 */
static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
	256, 384, 512, 768, 1024};

/* MX21, MX27 */
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static unsigned int spi_imx_clkdiv_1(unsigned int fin,
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		unsigned int fspi, unsigned int max, unsigned int *fres)
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{
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	int i;
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	for (i = 2; i < max; i++)
		if (fspi * mxc_clkdivs[i] >= fin)
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			break;
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	*fres = fin / mxc_clkdivs[i];
	return i;
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}

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/* MX1, MX31, MX35, MX51 CSPI */
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static unsigned int spi_imx_clkdiv_2(unsigned int fin,
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		unsigned int fspi, unsigned int *fres)
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{
	int i, div = 4;

	for (i = 0; i < 7; i++) {
		if (fspi * div >= fin)
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			goto out;
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		div <<= 1;
	}

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out:
	*fres = fin / div;
	return i;
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}

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static int spi_imx_bytes_per_word(const int bits_per_word)
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{
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	if (bits_per_word <= 8)
		return 1;
	else if (bits_per_word <= 16)
		return 2;
	else
		return 4;
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}

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static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
			 struct spi_transfer *transfer)
{
	struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
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	if (!use_dma || master->fallback)
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		return false;

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	if (!master->dma_rx)
		return false;

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	if (spi_imx->slave_mode)
		return false;

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	if (transfer->len < spi_imx->devtype_data->fifo_size)
		return false;

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	spi_imx->dynamic_burst = 0;
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	return true;
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}

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#define MX51_ECSPI_CTRL		0x08
#define MX51_ECSPI_CTRL_ENABLE		(1 <<  0)
#define MX51_ECSPI_CTRL_XCH		(1 <<  2)
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#define MX51_ECSPI_CTRL_SMC		(1 << 3)
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#define MX51_ECSPI_CTRL_MODE_MASK	(0xf << 4)
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#define MX51_ECSPI_CTRL_DRCTL(drctl)	((drctl) << 16)
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#define MX51_ECSPI_CTRL_POSTDIV_OFFSET	8
#define MX51_ECSPI_CTRL_PREDIV_OFFSET	12
#define MX51_ECSPI_CTRL_CS(cs)		((cs) << 18)
#define MX51_ECSPI_CTRL_BL_OFFSET	20
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#define MX51_ECSPI_CTRL_BL_MASK		(0xfff << 20)
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#define MX51_ECSPI_CONFIG	0x0c
#define MX51_ECSPI_CONFIG_SCLKPHA(cs)	(1 << ((cs) +  0))
#define MX51_ECSPI_CONFIG_SCLKPOL(cs)	(1 << ((cs) +  4))
#define MX51_ECSPI_CONFIG_SBBCTRL(cs)	(1 << ((cs) +  8))
#define MX51_ECSPI_CONFIG_SSBPOL(cs)	(1 << ((cs) + 12))
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#define MX51_ECSPI_CONFIG_SCLKCTL(cs)	(1 << ((cs) + 20))
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#define MX51_ECSPI_INT		0x10
#define MX51_ECSPI_INT_TEEN		(1 <<  0)
#define MX51_ECSPI_INT_RREN		(1 <<  3)
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#define MX51_ECSPI_INT_RDREN		(1 <<  4)
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#define MX51_ECSPI_DMA		0x14
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#define MX51_ECSPI_DMA_TX_WML(wml)	((wml) & 0x3f)
#define MX51_ECSPI_DMA_RX_WML(wml)	(((wml) & 0x3f) << 16)
#define MX51_ECSPI_DMA_RXT_WML(wml)	(((wml) & 0x3f) << 24)
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#define MX51_ECSPI_DMA_TEDEN		(1 << 7)
#define MX51_ECSPI_DMA_RXDEN		(1 << 23)
#define MX51_ECSPI_DMA_RXTDEN		(1 << 31)
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#define MX51_ECSPI_STAT		0x18
#define MX51_ECSPI_STAT_RR		(1 <<  3)
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#define MX51_ECSPI_TESTREG	0x20
#define MX51_ECSPI_TESTREG_LBC	BIT(31)

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static void spi_imx_buf_rx_swap_u32(struct spi_imx_data *spi_imx)
{
	unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);
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#ifdef __LITTLE_ENDIAN
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	unsigned int bytes_per_word;
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#endif
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	if (spi_imx->rx_buf) {
#ifdef __LITTLE_ENDIAN
		bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
		if (bytes_per_word == 1)
			val = cpu_to_be32(val);
		else if (bytes_per_word == 2)
			val = (val << 16) | (val >> 16);
#endif
		*(u32 *)spi_imx->rx_buf = val;
		spi_imx->rx_buf += sizeof(u32);
	}
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	spi_imx->remainder -= sizeof(u32);
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}

static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx)
{
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	int unaligned;
	u32 val;
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	unaligned = spi_imx->remainder % 4;

	if (!unaligned) {
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		spi_imx_buf_rx_swap_u32(spi_imx);
		return;
	}

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	if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
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		spi_imx_buf_rx_u16(spi_imx);
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		return;
	}

	val = readl(spi_imx->base + MXC_CSPIRXDATA);

	while (unaligned--) {
		if (spi_imx->rx_buf) {
			*(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff;
			spi_imx->rx_buf++;
		}
		spi_imx->remainder--;
	}
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}

static void spi_imx_buf_tx_swap_u32(struct spi_imx_data *spi_imx)
{
	u32 val = 0;
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#ifdef __LITTLE_ENDIAN
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	unsigned int bytes_per_word;
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#endif
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	if (spi_imx->tx_buf) {
		val = *(u32 *)spi_imx->tx_buf;
		spi_imx->tx_buf += sizeof(u32);
	}

	spi_imx->count -= sizeof(u32);
#ifdef __LITTLE_ENDIAN
	bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);

	if (bytes_per_word == 1)
		val = cpu_to_be32(val);
	else if (bytes_per_word == 2)
		val = (val << 16) | (val >> 16);
#endif
	writel(val, spi_imx->base + MXC_CSPITXDATA);
}

static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx)
{
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	int unaligned;
	u32 val = 0;
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	unaligned = spi_imx->count % 4;
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	if (!unaligned) {
		spi_imx_buf_tx_swap_u32(spi_imx);
		return;
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	}

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	if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
		spi_imx_buf_tx_u16(spi_imx);
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		return;
	}

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	while (unaligned--) {
		if (spi_imx->tx_buf) {
			val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned);
			spi_imx->tx_buf++;
		}
		spi_imx->count--;
	}
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	writel(val, spi_imx->base + MXC_CSPITXDATA);
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}

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static void mx53_ecspi_rx_slave(struct spi_imx_data *spi_imx)
{
	u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA));

	if (spi_imx->rx_buf) {
		int n_bytes = spi_imx->slave_burst % sizeof(val);

		if (!n_bytes)
			n_bytes = sizeof(val);

		memcpy(spi_imx->rx_buf,
		       ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes);

		spi_imx->rx_buf += n_bytes;
		spi_imx->slave_burst -= n_bytes;
	}
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	spi_imx->remainder -= sizeof(u32);
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}

static void mx53_ecspi_tx_slave(struct spi_imx_data *spi_imx)
{
	u32 val = 0;
	int n_bytes = spi_imx->count % sizeof(val);

	if (!n_bytes)
		n_bytes = sizeof(val);

	if (spi_imx->tx_buf) {
		memcpy(((u8 *)&val) + sizeof(val) - n_bytes,
		       spi_imx->tx_buf, n_bytes);
		val = cpu_to_be32(val);
		spi_imx->tx_buf += n_bytes;
	}

	spi_imx->count -= n_bytes;

	writel(val, spi_imx->base + MXC_CSPITXDATA);
}

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/* MX51 eCSPI */
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static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx,
				      unsigned int fspi, unsigned int *fres)
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{
	/*
	 * there are two 4-bit dividers, the pre-divider divides by
	 * $pre, the post-divider by 2^$post
	 */
	unsigned int pre, post;
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	unsigned int fin = spi_imx->spi_clk;
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	if (unlikely(fspi > fin))
		return 0;

	post = fls(fin) - fls(fspi);
	if (fin > fspi << post)
		post++;

	/* now we have: (fin <= fspi << post) with post being minimal */

	post = max(4U, post) - 4;
	if (unlikely(post > 0xf)) {
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		dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n",
				fspi, fin);
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		return 0xff;
	}

	pre = DIV_ROUND_UP(fin, fspi << post) - 1;

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	dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
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			__func__, fin, fspi, post, pre);
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	/* Resulting frequency for the SCLK line. */
	*fres = (fin / (pre + 1)) >> post;

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	return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
		(post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
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}

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static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
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{
	unsigned val = 0;

	if (enable & MXC_INT_TE)
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		val |= MX51_ECSPI_INT_TEEN;
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	if (enable & MXC_INT_RR)
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		val |= MX51_ECSPI_INT_RREN;
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	if (enable & MXC_INT_RDR)
		val |= MX51_ECSPI_INT_RDREN;

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	writel(val, spi_imx->base + MX51_ECSPI_INT);
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}

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static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
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{
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	u32 reg;
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	reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
	reg |= MX51_ECSPI_CTRL_XCH;
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	writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
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}

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static void mx51_disable_dma(struct spi_imx_data *spi_imx)
{
	writel(0, spi_imx->base + MX51_ECSPI_DMA);
}

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static void mx51_ecspi_disable(struct spi_imx_data *spi_imx)
{
	u32 ctrl;

	ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
	ctrl &= ~MX51_ECSPI_CTRL_ENABLE;
	writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
}

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static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx,
				      struct spi_message *msg)
{
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	struct spi_device *spi = msg->spi;
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	u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
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	u32 testreg, delay;
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	u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
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	/* set Master or Slave mode */
	if (spi_imx->slave_mode)
		ctrl &= ~MX51_ECSPI_CTRL_MODE_MASK;
	else
		ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
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	/*
	 * Enable SPI_RDY handling (falling edge/level triggered).
	 */
	if (spi->mode & SPI_READY)
		ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl);

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	/* set chip select to use */
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	ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select);
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	/*
	 * The ctrl register must be written first, with the EN bit set other
	 * registers must not be written to.
	 */
	writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);

	testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
	if (spi->mode & SPI_LOOP)
		testreg |= MX51_ECSPI_TESTREG_LBC;
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	else
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		testreg &= ~MX51_ECSPI_TESTREG_LBC;
	writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG);
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	/*
	 * eCSPI burst completion by Chip Select signal in Slave mode
	 * is not functional for imx53 Soc, config SPI burst completed when
	 * BURST_LENGTH + 1 bits are received
	 */
	if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
		cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
	else
		cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
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	if (spi->mode & SPI_CPHA)
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		cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
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	else
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		cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
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	if (spi->mode & SPI_CPOL) {
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		cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
		cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
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	} else {
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		cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
		cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
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	}
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	if (spi->mode & SPI_CS_HIGH)
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		cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
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	else
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		cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
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	writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
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	/*
	 * Wait until the changes in the configuration register CONFIGREG
	 * propagate into the hardware. It takes exactly one tick of the
	 * SCLK clock, but we will wait two SCLK clock just to be sure. The
	 * effect of the delay it takes for the hardware to apply changes
	 * is noticable if the SCLK clock run very slow. In such a case, if
	 * the polarity of SCLK should be inverted, the GPIO ChipSelect might
	 * be asserted before the SCLK polarity changes, which would disrupt
	 * the SPI communication as the device on the other end would consider
	 * the change of SCLK polarity as a clock tick already.
	 */
	delay = (2 * 1000000) / spi_imx->spi_bus_clk;
	if (likely(delay < 10))	/* SCLK is faster than 100 kHz */
		udelay(delay);
	else			/* SCLK is _very_ slow */
		usleep_range(delay, delay + 10);

587 588
	return 0;
}
589

590
static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
591
				       struct spi_device *spi)
592 593
{
	u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
594
	u32 clk;
595 596 597 598 599 600

	/* Clear BL field and set the right value */
	ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
	if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
		ctrl |= (spi_imx->slave_burst * 8 - 1)
			<< MX51_ECSPI_CTRL_BL_OFFSET;
601
	else
602 603
		ctrl |= (spi_imx->bits_per_word - 1)
			<< MX51_ECSPI_CTRL_BL_OFFSET;
604

605 606 607
	/* set clock speed */
	ctrl &= ~(0xf << MX51_ECSPI_CTRL_POSTDIV_OFFSET |
		  0xf << MX51_ECSPI_CTRL_PREDIV_OFFSET);
608
	ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->spi_bus_clk, &clk);
609 610 611 612 613 614
	spi_imx->spi_bus_clk = clk;

	if (spi_imx->usedma)
		ctrl |= MX51_ECSPI_CTRL_SMC;

	writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
615

616 617 618 619 620
	return 0;
}

static void mx51_setup_wml(struct spi_imx_data *spi_imx)
{
R
Robin Gong 已提交
621 622 623 624
	/*
	 * Configure the DMA register: setup the watermark
	 * and enable DMA request.
	 */
625
	writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
626 627
		MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
		MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
628 629
		MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
		MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
630 631
}

632
static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
633
{
634
	return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
635 636
}

637
static void mx51_ecspi_reset(struct spi_imx_data *spi_imx)
638 639
{
	/* drain receive buffer */
640
	while (mx51_ecspi_rx_available(spi_imx))
641 642 643
		readl(spi_imx->base + MXC_CSPIRXDATA);
}

644 645 646 647 648 649
#define MX31_INTREG_TEEN	(1 << 0)
#define MX31_INTREG_RREN	(1 << 3)

#define MX31_CSPICTRL_ENABLE	(1 << 0)
#define MX31_CSPICTRL_MASTER	(1 << 1)
#define MX31_CSPICTRL_XCH	(1 << 2)
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#define MX31_CSPICTRL_SMC	(1 << 3)
651 652 653 654 655 656 657 658 659 660
#define MX31_CSPICTRL_POL	(1 << 4)
#define MX31_CSPICTRL_PHA	(1 << 5)
#define MX31_CSPICTRL_SSCTL	(1 << 6)
#define MX31_CSPICTRL_SSPOL	(1 << 7)
#define MX31_CSPICTRL_BC_SHIFT	8
#define MX35_CSPICTRL_BL_SHIFT	20
#define MX31_CSPICTRL_CS_SHIFT	24
#define MX35_CSPICTRL_CS_SHIFT	12
#define MX31_CSPICTRL_DR_SHIFT	16

M
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661 662 663 664
#define MX31_CSPI_DMAREG	0x10
#define MX31_DMAREG_RH_DEN	(1<<4)
#define MX31_DMAREG_TH_DEN	(1<<1)

665 666 667
#define MX31_CSPISTATUS		0x14
#define MX31_STATUS_RR		(1 << 3)

668 669 670
#define MX31_CSPI_TESTREG	0x1C
#define MX31_TEST_LBC		(1 << 14)

671 672 673 674
/* These functions also work for the i.MX35, but be aware that
 * the i.MX35 has a slightly different register layout for bits
 * we do not use here.
 */
675
static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
676 677 678 679 680 681 682 683
{
	unsigned int val = 0;

	if (enable & MXC_INT_TE)
		val |= MX31_INTREG_TEEN;
	if (enable & MXC_INT_RR)
		val |= MX31_INTREG_RREN;

684
	writel(val, spi_imx->base + MXC_CSPIINT);
685 686
}

687
static void mx31_trigger(struct spi_imx_data *spi_imx)
688 689 690
{
	unsigned int reg;

691
	reg = readl(spi_imx->base + MXC_CSPICTRL);
692
	reg |= MX31_CSPICTRL_XCH;
693
	writel(reg, spi_imx->base + MXC_CSPICTRL);
694 695
}

696 697 698 699 700 701
static int mx31_prepare_message(struct spi_imx_data *spi_imx,
				struct spi_message *msg)
{
	return 0;
}

702
static int mx31_prepare_transfer(struct spi_imx_data *spi_imx,
703
				 struct spi_device *spi)
704 705
{
	unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
706
	unsigned int clk;
707

708
	reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) <<
709
		MX31_CSPICTRL_DR_SHIFT;
710
	spi_imx->spi_bus_clk = clk;
711

712
	if (is_imx35_cspi(spi_imx)) {
713
		reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT;
714 715
		reg |= MX31_CSPICTRL_SSCTL;
	} else {
716
		reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT;
717
	}
718

719
	if (spi->mode & SPI_CPHA)
720
		reg |= MX31_CSPICTRL_PHA;
721
	if (spi->mode & SPI_CPOL)
722
		reg |= MX31_CSPICTRL_POL;
723
	if (spi->mode & SPI_CS_HIGH)
724
		reg |= MX31_CSPICTRL_SSPOL;
725
	if (!spi->cs_gpiod)
726
		reg |= (spi->chip_select) <<
727 728
			(is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
						  MX31_CSPICTRL_CS_SHIFT);
729

M
Martin Kaiser 已提交
730 731 732
	if (spi_imx->usedma)
		reg |= MX31_CSPICTRL_SMC;

733 734
	writel(reg, spi_imx->base + MXC_CSPICTRL);

735 736 737 738 739 740 741
	reg = readl(spi_imx->base + MX31_CSPI_TESTREG);
	if (spi->mode & SPI_LOOP)
		reg |= MX31_TEST_LBC;
	else
		reg &= ~MX31_TEST_LBC;
	writel(reg, spi_imx->base + MX31_CSPI_TESTREG);

M
Martin Kaiser 已提交
742
	if (spi_imx->usedma) {
U
Uwe Kleine-König 已提交
743 744 745 746
		/*
		 * configure DMA requests when RXFIFO is half full and
		 * when TXFIFO is half empty
		 */
M
Martin Kaiser 已提交
747 748 749 750
		writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN,
			spi_imx->base + MX31_CSPI_DMAREG);
	}

751 752 753
	return 0;
}

754
static int mx31_rx_available(struct spi_imx_data *spi_imx)
755
{
756
	return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
757 758
}

759
static void mx31_reset(struct spi_imx_data *spi_imx)
760 761
{
	/* drain receive buffer */
762
	while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
763 764 765
		readl(spi_imx->base + MXC_CSPIRXDATA);
}

766 767 768 769 770 771 772 773 774 775 776 777 778
#define MX21_INTREG_RR		(1 << 4)
#define MX21_INTREG_TEEN	(1 << 9)
#define MX21_INTREG_RREN	(1 << 13)

#define MX21_CSPICTRL_POL	(1 << 5)
#define MX21_CSPICTRL_PHA	(1 << 6)
#define MX21_CSPICTRL_SSPOL	(1 << 8)
#define MX21_CSPICTRL_XCH	(1 << 9)
#define MX21_CSPICTRL_ENABLE	(1 << 10)
#define MX21_CSPICTRL_MASTER	(1 << 11)
#define MX21_CSPICTRL_DR_SHIFT	14
#define MX21_CSPICTRL_CS_SHIFT	19

779
static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
780 781 782 783
{
	unsigned int val = 0;

	if (enable & MXC_INT_TE)
784
		val |= MX21_INTREG_TEEN;
785
	if (enable & MXC_INT_RR)
786
		val |= MX21_INTREG_RREN;
787

788
	writel(val, spi_imx->base + MXC_CSPIINT);
789 790
}

791
static void mx21_trigger(struct spi_imx_data *spi_imx)
792 793 794
{
	unsigned int reg;

795
	reg = readl(spi_imx->base + MXC_CSPICTRL);
796
	reg |= MX21_CSPICTRL_XCH;
797
	writel(reg, spi_imx->base + MXC_CSPICTRL);
798 799
}

800 801 802 803 804 805
static int mx21_prepare_message(struct spi_imx_data *spi_imx,
				struct spi_message *msg)
{
	return 0;
}

806
static int mx21_prepare_transfer(struct spi_imx_data *spi_imx,
807
				 struct spi_device *spi)
808
{
809
	unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
810
	unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
811 812
	unsigned int clk;

813
	reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, spi_imx->spi_bus_clk, max, &clk)
814 815
		<< MX21_CSPICTRL_DR_SHIFT;
	spi_imx->spi_bus_clk = clk;
816

817
	reg |= spi_imx->bits_per_word - 1;
818

819
	if (spi->mode & SPI_CPHA)
820
		reg |= MX21_CSPICTRL_PHA;
821
	if (spi->mode & SPI_CPOL)
822
		reg |= MX21_CSPICTRL_POL;
823
	if (spi->mode & SPI_CS_HIGH)
824
		reg |= MX21_CSPICTRL_SSPOL;
825
	if (!spi->cs_gpiod)
826
		reg |= spi->chip_select << MX21_CSPICTRL_CS_SHIFT;
827

828
	writel(reg, spi_imx->base + MXC_CSPICTRL);
829 830 831 832

	return 0;
}

833
static int mx21_rx_available(struct spi_imx_data *spi_imx)
834
{
835
	return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
836 837
}

838
static void mx21_reset(struct spi_imx_data *spi_imx)
839 840 841 842
{
	writel(1, spi_imx->base + MXC_RESET);
}

843 844 845 846 847 848 849 850 851 852 853
#define MX1_INTREG_RR		(1 << 3)
#define MX1_INTREG_TEEN		(1 << 8)
#define MX1_INTREG_RREN		(1 << 11)

#define MX1_CSPICTRL_POL	(1 << 4)
#define MX1_CSPICTRL_PHA	(1 << 5)
#define MX1_CSPICTRL_XCH	(1 << 8)
#define MX1_CSPICTRL_ENABLE	(1 << 9)
#define MX1_CSPICTRL_MASTER	(1 << 10)
#define MX1_CSPICTRL_DR_SHIFT	13

854
static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
855 856 857 858 859 860 861 862
{
	unsigned int val = 0;

	if (enable & MXC_INT_TE)
		val |= MX1_INTREG_TEEN;
	if (enable & MXC_INT_RR)
		val |= MX1_INTREG_RREN;

863
	writel(val, spi_imx->base + MXC_CSPIINT);
864 865
}

866
static void mx1_trigger(struct spi_imx_data *spi_imx)
867 868 869
{
	unsigned int reg;

870
	reg = readl(spi_imx->base + MXC_CSPICTRL);
871
	reg |= MX1_CSPICTRL_XCH;
872
	writel(reg, spi_imx->base + MXC_CSPICTRL);
873 874
}

875 876 877 878 879 880
static int mx1_prepare_message(struct spi_imx_data *spi_imx,
			       struct spi_message *msg)
{
	return 0;
}

881
static int mx1_prepare_transfer(struct spi_imx_data *spi_imx,
882
				struct spi_device *spi)
883 884
{
	unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
885
	unsigned int clk;
886

887
	reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) <<
888
		MX1_CSPICTRL_DR_SHIFT;
889 890
	spi_imx->spi_bus_clk = clk;

891
	reg |= spi_imx->bits_per_word - 1;
892

893
	if (spi->mode & SPI_CPHA)
894
		reg |= MX1_CSPICTRL_PHA;
895
	if (spi->mode & SPI_CPOL)
896 897
		reg |= MX1_CSPICTRL_POL;

898
	writel(reg, spi_imx->base + MXC_CSPICTRL);
899 900 901 902

	return 0;
}

903
static int mx1_rx_available(struct spi_imx_data *spi_imx)
904
{
905
	return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
906 907
}

908
static void mx1_reset(struct spi_imx_data *spi_imx)
909 910 911 912
{
	writel(1, spi_imx->base + MXC_RESET);
}

913 914
static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
	.intctrl = mx1_intctrl,
915
	.prepare_message = mx1_prepare_message,
916
	.prepare_transfer = mx1_prepare_transfer,
917 918 919
	.trigger = mx1_trigger,
	.rx_available = mx1_rx_available,
	.reset = mx1_reset,
920 921
	.fifo_size = 8,
	.has_dmamode = false,
922
	.dynamic_burst = false,
923
	.has_slavemode = false,
924 925 926 927 928
	.devtype = IMX1_CSPI,
};

static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
	.intctrl = mx21_intctrl,
929
	.prepare_message = mx21_prepare_message,
930
	.prepare_transfer = mx21_prepare_transfer,
931 932 933
	.trigger = mx21_trigger,
	.rx_available = mx21_rx_available,
	.reset = mx21_reset,
934 935
	.fifo_size = 8,
	.has_dmamode = false,
936
	.dynamic_burst = false,
937
	.has_slavemode = false,
938 939 940 941 942 943
	.devtype = IMX21_CSPI,
};

static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
	/* i.mx27 cspi shares the functions with i.mx21 one */
	.intctrl = mx21_intctrl,
944
	.prepare_message = mx21_prepare_message,
945
	.prepare_transfer = mx21_prepare_transfer,
946 947 948
	.trigger = mx21_trigger,
	.rx_available = mx21_rx_available,
	.reset = mx21_reset,
949 950
	.fifo_size = 8,
	.has_dmamode = false,
951
	.dynamic_burst = false,
952
	.has_slavemode = false,
953 954 955 956 957
	.devtype = IMX27_CSPI,
};

static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
	.intctrl = mx31_intctrl,
958
	.prepare_message = mx31_prepare_message,
959
	.prepare_transfer = mx31_prepare_transfer,
960 961 962
	.trigger = mx31_trigger,
	.rx_available = mx31_rx_available,
	.reset = mx31_reset,
963 964
	.fifo_size = 8,
	.has_dmamode = false,
965
	.dynamic_burst = false,
966
	.has_slavemode = false,
967 968 969 970 971 972
	.devtype = IMX31_CSPI,
};

static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
	/* i.mx35 and later cspi shares the functions with i.mx31 one */
	.intctrl = mx31_intctrl,
973
	.prepare_message = mx31_prepare_message,
974
	.prepare_transfer = mx31_prepare_transfer,
975 976 977
	.trigger = mx31_trigger,
	.rx_available = mx31_rx_available,
	.reset = mx31_reset,
978 979
	.fifo_size = 8,
	.has_dmamode = true,
980
	.dynamic_burst = false,
981
	.has_slavemode = false,
982 983 984 985 986
	.devtype = IMX35_CSPI,
};

static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
	.intctrl = mx51_ecspi_intctrl,
987
	.prepare_message = mx51_ecspi_prepare_message,
988
	.prepare_transfer = mx51_ecspi_prepare_transfer,
989 990 991
	.trigger = mx51_ecspi_trigger,
	.rx_available = mx51_ecspi_rx_available,
	.reset = mx51_ecspi_reset,
992
	.setup_wml = mx51_setup_wml,
993
	.disable_dma = mx51_disable_dma,
994 995
	.fifo_size = 64,
	.has_dmamode = true,
996
	.dynamic_burst = true,
997 998
	.has_slavemode = true,
	.disable = mx51_ecspi_disable,
999 1000 1001
	.devtype = IMX51_ECSPI,
};

1002 1003
static struct spi_imx_devtype_data imx53_ecspi_devtype_data = {
	.intctrl = mx51_ecspi_intctrl,
1004
	.prepare_message = mx51_ecspi_prepare_message,
1005
	.prepare_transfer = mx51_ecspi_prepare_transfer,
1006 1007
	.trigger = mx51_ecspi_trigger,
	.rx_available = mx51_ecspi_rx_available,
1008
	.disable_dma = mx51_disable_dma,
1009 1010 1011
	.reset = mx51_ecspi_reset,
	.fifo_size = 64,
	.has_dmamode = true,
1012 1013
	.has_slavemode = true,
	.disable = mx51_ecspi_disable,
1014 1015 1016
	.devtype = IMX53_ECSPI,
};

1017 1018 1019 1020 1021 1022 1023
static const struct of_device_id spi_imx_dt_ids[] = {
	{ .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
	{ .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
	{ .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
	{ .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
	{ .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
	{ .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
1024
	{ .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, },
1025 1026
	{ /* sentinel */ }
};
1027
MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
1028

1029 1030 1031 1032 1033 1034 1035 1036 1037 1038
static void spi_imx_set_burst_len(struct spi_imx_data *spi_imx, int n_bits)
{
	u32 ctrl;

	ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
	ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
	ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET);
	writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
}

1039
static void spi_imx_push(struct spi_imx_data *spi_imx)
1040
{
1041
	unsigned int burst_len;
1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060

	/*
	 * Reload the FIFO when the remaining bytes to be transferred in the
	 * current burst is 0. This only applies when bits_per_word is a
	 * multiple of 8.
	 */
	if (!spi_imx->remainder) {
		if (spi_imx->dynamic_burst) {

			/* We need to deal unaligned data first */
			burst_len = spi_imx->count % MX51_ECSPI_CTRL_MAX_BURST;

			if (!burst_len)
				burst_len = MX51_ECSPI_CTRL_MAX_BURST;

			spi_imx_set_burst_len(spi_imx, burst_len * 8);

			spi_imx->remainder = burst_len;
		} else {
1061
			spi_imx->remainder = spi_imx_bytes_per_word(spi_imx->bits_per_word);
1062 1063 1064
		}
	}

1065
	while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) {
1066
		if (!spi_imx->count)
1067
			break;
1068
		if (spi_imx->dynamic_burst &&
1069
		    spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder, 4))
1070
			break;
1071 1072
		spi_imx->tx(spi_imx);
		spi_imx->txfifo++;
1073 1074
	}

1075 1076
	if (!spi_imx->slave_mode)
		spi_imx->devtype_data->trigger(spi_imx);
1077 1078
}

1079
static irqreturn_t spi_imx_isr(int irq, void *dev_id)
1080
{
1081
	struct spi_imx_data *spi_imx = dev_id;
1082

1083 1084
	while (spi_imx->txfifo &&
	       spi_imx->devtype_data->rx_available(spi_imx)) {
1085 1086
		spi_imx->rx(spi_imx);
		spi_imx->txfifo--;
1087 1088
	}

1089 1090
	if (spi_imx->count) {
		spi_imx_push(spi_imx);
1091 1092 1093
		return IRQ_HANDLED;
	}

1094
	if (spi_imx->txfifo) {
1095 1096 1097
		/* No data left to push, but still waiting for rx data,
		 * enable receive data available interrupt.
		 */
1098
		spi_imx->devtype_data->intctrl(
1099
				spi_imx, MXC_INT_RR);
1100 1101 1102
		return IRQ_HANDLED;
	}

1103
	spi_imx->devtype_data->intctrl(spi_imx, 0);
1104
	complete(&spi_imx->xfer_done);
1105 1106 1107 1108

	return IRQ_HANDLED;
}

1109
static int spi_imx_dma_configure(struct spi_master *master)
1110 1111 1112 1113 1114 1115
{
	int ret;
	enum dma_slave_buswidth buswidth;
	struct dma_slave_config rx = {}, tx = {};
	struct spi_imx_data *spi_imx = spi_master_get_devdata(master);

1116
	switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) {
1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152
	case 4:
		buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
		break;
	case 2:
		buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
		break;
	case 1:
		buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
		break;
	default:
		return -EINVAL;
	}

	tx.direction = DMA_MEM_TO_DEV;
	tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
	tx.dst_addr_width = buswidth;
	tx.dst_maxburst = spi_imx->wml;
	ret = dmaengine_slave_config(master->dma_tx, &tx);
	if (ret) {
		dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret);
		return ret;
	}

	rx.direction = DMA_DEV_TO_MEM;
	rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA;
	rx.src_addr_width = buswidth;
	rx.src_maxburst = spi_imx->wml;
	ret = dmaengine_slave_config(master->dma_rx, &rx);
	if (ret) {
		dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret);
		return ret;
	}

	return 0;
}

1153
static int spi_imx_setupxfer(struct spi_device *spi,
1154 1155
				 struct spi_transfer *t)
{
1156
	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1157

1158 1159 1160
	if (!t)
		return 0;

1161 1162 1163 1164 1165 1166 1167 1168 1169 1170
	if (!t->speed_hz) {
		if (!spi->max_speed_hz) {
			dev_err(&spi->dev, "no speed_hz provided!\n");
			return -EINVAL;
		}
		dev_dbg(&spi->dev, "using spi->max_speed_hz!\n");
		spi_imx->spi_bus_clk = spi->max_speed_hz;
	} else
		spi_imx->spi_bus_clk = t->speed_hz;

1171
	spi_imx->bits_per_word = t->bits_per_word;
1172

1173 1174 1175 1176 1177 1178 1179 1180 1181
	/*
	 * Initialize the functions for transfer. To transfer non byte-aligned
	 * words, we have to use multiple word-size bursts, we can't use
	 * dynamic_burst in that case.
	 */
	if (spi_imx->devtype_data->dynamic_burst && !spi_imx->slave_mode &&
	    (spi_imx->bits_per_word == 8 ||
	    spi_imx->bits_per_word == 16 ||
	    spi_imx->bits_per_word == 32)) {
1182 1183 1184 1185 1186

		spi_imx->rx = spi_imx_buf_rx_swap;
		spi_imx->tx = spi_imx_buf_tx_swap;
		spi_imx->dynamic_burst = 1;

1187
	} else {
1188 1189 1190 1191 1192 1193 1194 1195 1196 1197
		if (spi_imx->bits_per_word <= 8) {
			spi_imx->rx = spi_imx_buf_rx_u8;
			spi_imx->tx = spi_imx_buf_tx_u8;
		} else if (spi_imx->bits_per_word <= 16) {
			spi_imx->rx = spi_imx_buf_rx_u16;
			spi_imx->tx = spi_imx_buf_tx_u16;
		} else {
			spi_imx->rx = spi_imx_buf_rx_u32;
			spi_imx->tx = spi_imx_buf_tx_u32;
		}
1198
		spi_imx->dynamic_burst = 0;
1199
	}
1200

1201
	if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t))
1202
		spi_imx->usedma = true;
1203
	else
1204
		spi_imx->usedma = false;
1205

1206 1207 1208 1209 1210 1211
	if (is_imx53_ecspi(spi_imx) && spi_imx->slave_mode) {
		spi_imx->rx = mx53_ecspi_rx_slave;
		spi_imx->tx = mx53_ecspi_tx_slave;
		spi_imx->slave_burst = t->len;
	}

1212
	spi_imx->devtype_data->prepare_transfer(spi_imx, spi);
1213 1214 1215 1216

	return 0;
}

R
Robin Gong 已提交
1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232
static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
{
	struct spi_master *master = spi_imx->bitbang.master;

	if (master->dma_rx) {
		dma_release_channel(master->dma_rx);
		master->dma_rx = NULL;
	}

	if (master->dma_tx) {
		dma_release_channel(master->dma_tx);
		master->dma_tx = NULL;
	}
}

static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
1233
			     struct spi_master *master)
R
Robin Gong 已提交
1234 1235 1236
{
	int ret;

R
Robin Gong 已提交
1237 1238 1239 1240
	/* use pio mode for i.mx6dl chip TKT238285 */
	if (of_machine_is_compatible("fsl,imx6dl"))
		return 0;

1241
	spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
1242

R
Robin Gong 已提交
1243
	/* Prepare for TX DMA: */
1244
	master->dma_tx = dma_request_chan(dev, "tx");
1245 1246 1247 1248
	if (IS_ERR(master->dma_tx)) {
		ret = PTR_ERR(master->dma_tx);
		dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
		master->dma_tx = NULL;
R
Robin Gong 已提交
1249 1250 1251 1252
		goto err;
	}

	/* Prepare for RX : */
1253
	master->dma_rx = dma_request_chan(dev, "rx");
1254 1255 1256 1257
	if (IS_ERR(master->dma_rx)) {
		ret = PTR_ERR(master->dma_rx);
		dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
		master->dma_rx = NULL;
R
Robin Gong 已提交
1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287
		goto err;
	}

	init_completion(&spi_imx->dma_rx_completion);
	init_completion(&spi_imx->dma_tx_completion);
	master->can_dma = spi_imx_can_dma;
	master->max_dma_len = MAX_SDMA_BD_BYTES;
	spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX |
					 SPI_MASTER_MUST_TX;

	return 0;
err:
	spi_imx_sdma_exit(spi_imx);
	return ret;
}

static void spi_imx_dma_rx_callback(void *cookie)
{
	struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;

	complete(&spi_imx->dma_rx_completion);
}

static void spi_imx_dma_tx_callback(void *cookie)
{
	struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;

	complete(&spi_imx->dma_tx_completion);
}

1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301
static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size)
{
	unsigned long timeout = 0;

	/* Time with actual data transfer and CS change delay related to HW */
	timeout = (8 + 4) * size / spi_imx->spi_bus_clk;

	/* Add extra second for scheduler related activities */
	timeout += 1;

	/* Double calculated timeout */
	return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
}

R
Robin Gong 已提交
1302 1303 1304
static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
				struct spi_transfer *transfer)
{
1305
	struct dma_async_tx_descriptor *desc_tx, *desc_rx;
1306
	unsigned long transfer_timeout;
1307
	unsigned long timeout;
R
Robin Gong 已提交
1308 1309
	struct spi_master *master = spi_imx->bitbang.master;
	struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
1310 1311
	struct scatterlist *last_sg = sg_last(rx->sgl, rx->nents);
	unsigned int bytes_per_word, i;
1312 1313
	int ret;

1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325
	/* Get the right burst length from the last sg to ensure no tail data */
	bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word);
	for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) {
		if (!(sg_dma_len(last_sg) % (i * bytes_per_word)))
			break;
	}
	/* Use 1 as wml in case no available burst length got */
	if (i == 0)
		i = 1;

	spi_imx->wml =  i;

1326 1327
	ret = spi_imx_dma_configure(master);
	if (ret)
R
Robin Gong 已提交
1328
		goto dma_failure_no_start;
1329

1330 1331
	if (!spi_imx->devtype_data->setup_wml) {
		dev_err(spi_imx->dev, "No setup_wml()?\n");
R
Robin Gong 已提交
1332 1333
		ret = -EINVAL;
		goto dma_failure_no_start;
1334
	}
1335
	spi_imx->devtype_data->setup_wml(spi_imx);
R
Robin Gong 已提交
1336

1337 1338 1339 1340 1341 1342 1343
	/*
	 * The TX DMA setup starts the transfer, so make sure RX is configured
	 * before TX.
	 */
	desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
				rx->sgl, rx->nents, DMA_DEV_TO_MEM,
				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
R
Robin Gong 已提交
1344 1345 1346 1347
	if (!desc_rx) {
		ret = -EINVAL;
		goto dma_failure_no_start;
	}
R
Robin Gong 已提交
1348

1349 1350 1351 1352 1353
	desc_rx->callback = spi_imx_dma_rx_callback;
	desc_rx->callback_param = (void *)spi_imx;
	dmaengine_submit(desc_rx);
	reinit_completion(&spi_imx->dma_rx_completion);
	dma_async_issue_pending(master->dma_rx);
R
Robin Gong 已提交
1354

1355 1356 1357 1358 1359
	desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
				tx->sgl, tx->nents, DMA_MEM_TO_DEV,
				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
	if (!desc_tx) {
		dmaengine_terminate_all(master->dma_tx);
1360
		dmaengine_terminate_all(master->dma_rx);
1361
		return -EINVAL;
R
Robin Gong 已提交
1362 1363
	}

1364 1365 1366
	desc_tx->callback = spi_imx_dma_tx_callback;
	desc_tx->callback_param = (void *)spi_imx;
	dmaengine_submit(desc_tx);
R
Robin Gong 已提交
1367
	reinit_completion(&spi_imx->dma_tx_completion);
1368
	dma_async_issue_pending(master->dma_tx);
R
Robin Gong 已提交
1369

1370 1371
	transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);

R
Robin Gong 已提交
1372
	/* Wait SDMA to finish the data transfer.*/
1373
	timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
1374
						transfer_timeout);
1375
	if (!timeout) {
1376
		dev_err(spi_imx->dev, "I/O Error in DMA TX\n");
R
Robin Gong 已提交
1377
		dmaengine_terminate_all(master->dma_tx);
1378
		dmaengine_terminate_all(master->dma_rx);
1379
		return -ETIMEDOUT;
R
Robin Gong 已提交
1380 1381
	}

1382 1383 1384 1385 1386 1387 1388 1389
	timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion,
					      transfer_timeout);
	if (!timeout) {
		dev_err(&master->dev, "I/O Error in DMA RX\n");
		spi_imx->devtype_data->reset(spi_imx);
		dmaengine_terminate_all(master->dma_rx);
		return -ETIMEDOUT;
	}
R
Robin Gong 已提交
1390

1391
	return transfer->len;
R
Robin Gong 已提交
1392 1393 1394 1395
/* fallback to pio */
dma_failure_no_start:
	transfer->error |= SPI_TRANS_FAIL_NO_START;
	return ret;
R
Robin Gong 已提交
1396 1397 1398
}

static int spi_imx_pio_transfer(struct spi_device *spi,
1399 1400
				struct spi_transfer *transfer)
{
1401
	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1402 1403
	unsigned long transfer_timeout;
	unsigned long timeout;
1404

1405 1406 1407 1408
	spi_imx->tx_buf = transfer->tx_buf;
	spi_imx->rx_buf = transfer->rx_buf;
	spi_imx->count = transfer->len;
	spi_imx->txfifo = 0;
1409
	spi_imx->remainder = 0;
1410

1411
	reinit_completion(&spi_imx->xfer_done);
1412

1413
	spi_imx_push(spi_imx);
1414

1415
	spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
1416

1417 1418 1419 1420 1421 1422 1423 1424 1425
	transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);

	timeout = wait_for_completion_timeout(&spi_imx->xfer_done,
					      transfer_timeout);
	if (!timeout) {
		dev_err(&spi->dev, "I/O Error in PIO\n");
		spi_imx->devtype_data->reset(spi_imx);
		return -ETIMEDOUT;
	}
1426 1427 1428 1429

	return transfer->len;
}

1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446
static int spi_imx_pio_transfer_slave(struct spi_device *spi,
				      struct spi_transfer *transfer)
{
	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
	int ret = transfer->len;

	if (is_imx53_ecspi(spi_imx) &&
	    transfer->len > MX53_MAX_TRANSFER_BYTES) {
		dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n",
			MX53_MAX_TRANSFER_BYTES);
		return -EMSGSIZE;
	}

	spi_imx->tx_buf = transfer->tx_buf;
	spi_imx->rx_buf = transfer->rx_buf;
	spi_imx->count = transfer->len;
	spi_imx->txfifo = 0;
1447
	spi_imx->remainder = 0;
1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473

	reinit_completion(&spi_imx->xfer_done);
	spi_imx->slave_aborted = false;

	spi_imx_push(spi_imx);

	spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR);

	if (wait_for_completion_interruptible(&spi_imx->xfer_done) ||
	    spi_imx->slave_aborted) {
		dev_dbg(&spi->dev, "interrupted\n");
		ret = -EINTR;
	}

	/* ecspi has a HW issue when works in Slave mode,
	 * after 64 words writtern to TXFIFO, even TXFIFO becomes empty,
	 * ECSPI_TXDATA keeps shift out the last word data,
	 * so we have to disable ECSPI when in slave mode after the
	 * transfer completes
	 */
	if (spi_imx->devtype_data->disable)
		spi_imx->devtype_data->disable(spi_imx);

	return ret;
}

R
Robin Gong 已提交
1474 1475 1476 1477 1478
static int spi_imx_transfer(struct spi_device *spi,
				struct spi_transfer *transfer)
{
	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);

1479 1480
	transfer->effective_speed_hz = spi_imx->spi_bus_clk;

1481 1482
	/* flush rxfifo before transfer */
	while (spi_imx->devtype_data->rx_available(spi_imx))
1483
		readl(spi_imx->base + MXC_CSPIRXDATA);
1484 1485 1486 1487

	if (spi_imx->slave_mode)
		return spi_imx_pio_transfer_slave(spi, transfer);

R
Robin Gong 已提交
1488 1489
	if (spi_imx->usedma)
		return spi_imx_dma_transfer(spi_imx, transfer);
1490 1491

	return spi_imx_pio_transfer(spi, transfer);
R
Robin Gong 已提交
1492 1493
}

1494
static int spi_imx_setup(struct spi_device *spi)
1495
{
1496
	dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
1497 1498 1499 1500 1501
		 spi->mode, spi->bits_per_word, spi->max_speed_hz);

	return 0;
}

1502
static void spi_imx_cleanup(struct spi_device *spi)
1503 1504 1505
{
}

1506 1507 1508 1509 1510 1511
static int
spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg)
{
	struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
	int ret;

C
Clark Wang 已提交
1512 1513
	ret = pm_runtime_get_sync(spi_imx->dev);
	if (ret < 0) {
1514
		pm_runtime_put_noidle(spi_imx->dev);
C
Clark Wang 已提交
1515
		dev_err(spi_imx->dev, "failed to enable clock\n");
1516 1517 1518
		return ret;
	}

1519 1520
	ret = spi_imx->devtype_data->prepare_message(spi_imx, msg);
	if (ret) {
C
Clark Wang 已提交
1521 1522
		pm_runtime_mark_last_busy(spi_imx->dev);
		pm_runtime_put_autosuspend(spi_imx->dev);
1523 1524 1525
	}

	return ret;
1526 1527 1528 1529 1530 1531 1532
}

static int
spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
{
	struct spi_imx_data *spi_imx = spi_master_get_devdata(master);

C
Clark Wang 已提交
1533 1534
	pm_runtime_mark_last_busy(spi_imx->dev);
	pm_runtime_put_autosuspend(spi_imx->dev);
1535 1536 1537
	return 0;
}

1538 1539 1540 1541 1542 1543 1544 1545 1546 1547
static int spi_imx_slave_abort(struct spi_master *master)
{
	struct spi_imx_data *spi_imx = spi_master_get_devdata(master);

	spi_imx->slave_aborted = true;
	complete(&spi_imx->xfer_done);

	return 0;
}

1548
static int spi_imx_probe(struct platform_device *pdev)
1549
{
1550
	struct device_node *np = pdev->dev.of_node;
1551
	struct spi_master *master;
1552
	struct spi_imx_data *spi_imx;
1553
	struct resource *res;
1554
	int ret, irq, spi_drctl;
1555 1556
	const struct spi_imx_devtype_data *devtype_data =
			of_device_get_match_data(&pdev->dev);
1557
	bool slave_mode;
1558
	u32 val;
1559

1560 1561 1562 1563 1564 1565 1566 1567
	slave_mode = devtype_data->has_slavemode &&
			of_property_read_bool(np, "spi-slave");
	if (slave_mode)
		master = spi_alloc_slave(&pdev->dev,
					 sizeof(struct spi_imx_data));
	else
		master = spi_alloc_master(&pdev->dev,
					  sizeof(struct spi_imx_data));
1568 1569 1570
	if (!master)
		return -ENOMEM;

1571 1572 1573 1574 1575 1576
	ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl);
	if ((ret < 0) || (spi_drctl >= 0x3)) {
		/* '11' is reserved */
		spi_drctl = 0;
	}

1577 1578
	platform_set_drvdata(pdev, master);

1579
	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
1580
	master->bus_num = np ? -1 : pdev->id;
1581
	master->use_gpio_descriptors = true;
1582

1583
	spi_imx = spi_master_get_devdata(master);
1584
	spi_imx->bitbang.master = master;
1585
	spi_imx->dev = &pdev->dev;
1586
	spi_imx->slave_mode = slave_mode;
1587

1588
	spi_imx->devtype_data = devtype_data;
1589

1590 1591 1592 1593 1594 1595 1596 1597 1598 1599
	/*
	 * Get number of chip selects from device properties. This can be
	 * coming from device tree or boardfiles, if it is not defined,
	 * a default value of 3 chip selects will be used, as all the legacy
	 * board files have <= 3 chip selects.
	 */
	if (!device_property_read_u32(&pdev->dev, "num-cs", &val))
		master->num_chipselect = val;
	else
		master->num_chipselect = 3;
1600

1601 1602 1603 1604
	spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
	spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
	spi_imx->bitbang.master->setup = spi_imx_setup;
	spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
1605 1606
	spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
	spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
1607
	spi_imx->bitbang.master->slave_abort = spi_imx_slave_abort;
O
Oleksij Rempel 已提交
1608 1609
	spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
					     | SPI_NO_CS;
1610 1611
	if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) ||
	    is_imx53_ecspi(spi_imx))
1612 1613 1614
		spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY;

	spi_imx->spi_drctl = spi_drctl;
1615

1616
	init_completion(&spi_imx->xfer_done);
1617 1618

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
F
Fabio Estevam 已提交
1619 1620 1621 1622
	spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(spi_imx->base)) {
		ret = PTR_ERR(spi_imx->base);
		goto out_master_put;
1623
	}
1624
	spi_imx->base_phys = res->start;
1625

1626 1627 1628
	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		ret = irq;
F
Fabio Estevam 已提交
1629
		goto out_master_put;
1630 1631
	}

1632
	ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
1633
			       dev_name(&pdev->dev), spi_imx);
1634
	if (ret) {
1635
		dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
F
Fabio Estevam 已提交
1636
		goto out_master_put;
1637 1638
	}

1639 1640 1641
	spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
	if (IS_ERR(spi_imx->clk_ipg)) {
		ret = PTR_ERR(spi_imx->clk_ipg);
F
Fabio Estevam 已提交
1642
		goto out_master_put;
1643 1644
	}

1645 1646 1647
	spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
	if (IS_ERR(spi_imx->clk_per)) {
		ret = PTR_ERR(spi_imx->clk_per);
F
Fabio Estevam 已提交
1648
		goto out_master_put;
1649 1650
	}

1651 1652 1653 1654 1655 1656 1657 1658
	ret = clk_prepare_enable(spi_imx->clk_per);
	if (ret)
		goto out_master_put;

	ret = clk_prepare_enable(spi_imx->clk_ipg);
	if (ret)
		goto out_put_per;

C
Clark Wang 已提交
1659 1660
	pm_runtime_set_autosuspend_delay(spi_imx->dev, MXC_RPM_TIMEOUT);
	pm_runtime_use_autosuspend(spi_imx->dev);
1661
	pm_runtime_get_noresume(spi_imx->dev);
1662 1663
	pm_runtime_set_active(spi_imx->dev);
	pm_runtime_enable(spi_imx->dev);
1664 1665

	spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
R
Robin Gong 已提交
1666
	/*
M
Martin Kaiser 已提交
1667 1668
	 * Only validated on i.mx35 and i.mx6 now, can remove the constraint
	 * if validated on other chips.
R
Robin Gong 已提交
1669
	 */
1670
	if (spi_imx->devtype_data->has_dmamode) {
1671
		ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master);
1672
		if (ret == -EPROBE_DEFER)
C
Clark Wang 已提交
1673
			goto out_runtime_pm_put;
1674

1675
		if (ret < 0)
1676
			dev_dbg(&pdev->dev, "dma setup error %d, use pio\n",
1677 1678
				ret);
	}
1679

1680
	spi_imx->devtype_data->reset(spi_imx);
1681

1682
	spi_imx->devtype_data->intctrl(spi_imx, 0);
1683

1684
	master->dev.of_node = pdev->dev.of_node;
1685 1686
	ret = spi_bitbang_start(&spi_imx->bitbang);
	if (ret) {
1687
		dev_err_probe(&pdev->dev, ret, "bitbang start failed\n");
1688
		goto out_bitbang_start;
1689
	}
1690

C
Clark Wang 已提交
1691 1692 1693
	pm_runtime_mark_last_busy(spi_imx->dev);
	pm_runtime_put_autosuspend(spi_imx->dev);

1694 1695
	return ret;

1696 1697 1698
out_bitbang_start:
	if (spi_imx->devtype_data->has_dmamode)
		spi_imx_sdma_exit(spi_imx);
C
Clark Wang 已提交
1699 1700
out_runtime_pm_put:
	pm_runtime_dont_use_autosuspend(spi_imx->dev);
1701
	pm_runtime_set_suspended(&pdev->dev);
C
Clark Wang 已提交
1702
	pm_runtime_disable(spi_imx->dev);
1703 1704 1705 1706

	clk_disable_unprepare(spi_imx->clk_ipg);
out_put_per:
	clk_disable_unprepare(spi_imx->clk_per);
F
Fabio Estevam 已提交
1707
out_master_put:
1708
	spi_master_put(master);
F
Fabio Estevam 已提交
1709

1710 1711 1712
	return ret;
}

1713
static int spi_imx_remove(struct platform_device *pdev)
1714 1715
{
	struct spi_master *master = platform_get_drvdata(pdev);
1716
	struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1717
	int ret;
1718

1719
	spi_bitbang_stop(&spi_imx->bitbang);
1720

C
Clark Wang 已提交
1721 1722
	ret = pm_runtime_get_sync(spi_imx->dev);
	if (ret < 0) {
1723
		pm_runtime_put_noidle(spi_imx->dev);
C
Clark Wang 已提交
1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748
		dev_err(spi_imx->dev, "failed to enable clock\n");
		return ret;
	}

	writel(0, spi_imx->base + MXC_CSPICTRL);

	pm_runtime_dont_use_autosuspend(spi_imx->dev);
	pm_runtime_put_sync(spi_imx->dev);
	pm_runtime_disable(spi_imx->dev);

	spi_imx_sdma_exit(spi_imx);
	spi_master_put(master);

	return 0;
}

static int __maybe_unused spi_imx_runtime_resume(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct spi_imx_data *spi_imx;
	int ret;

	spi_imx = spi_master_get_devdata(master);

	ret = clk_prepare_enable(spi_imx->clk_per);
1749 1750 1751
	if (ret)
		return ret;

C
Clark Wang 已提交
1752
	ret = clk_prepare_enable(spi_imx->clk_ipg);
1753
	if (ret) {
C
Clark Wang 已提交
1754
		clk_disable_unprepare(spi_imx->clk_per);
1755 1756 1757
		return ret;
	}

C
Clark Wang 已提交
1758 1759 1760 1761 1762 1763 1764 1765 1766 1767
	return 0;
}

static int __maybe_unused spi_imx_runtime_suspend(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct spi_imx_data *spi_imx;

	spi_imx = spi_master_get_devdata(master);

1768
	clk_disable_unprepare(spi_imx->clk_per);
C
Clark Wang 已提交
1769 1770 1771 1772
	clk_disable_unprepare(spi_imx->clk_ipg);

	return 0;
}
1773

C
Clark Wang 已提交
1774 1775 1776
static int __maybe_unused spi_imx_suspend(struct device *dev)
{
	pinctrl_pm_select_sleep_state(dev);
1777 1778 1779
	return 0;
}

C
Clark Wang 已提交
1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791
static int __maybe_unused spi_imx_resume(struct device *dev)
{
	pinctrl_pm_select_default_state(dev);
	return 0;
}

static const struct dev_pm_ops imx_spi_pm = {
	SET_RUNTIME_PM_OPS(spi_imx_runtime_suspend,
				spi_imx_runtime_resume, NULL)
	SET_SYSTEM_SLEEP_PM_OPS(spi_imx_suspend, spi_imx_resume)
};

1792
static struct platform_driver spi_imx_driver = {
1793 1794
	.driver = {
		   .name = DRIVER_NAME,
1795
		   .of_match_table = spi_imx_dt_ids,
C
Clark Wang 已提交
1796 1797
		   .pm = &imx_spi_pm,
	},
1798
	.probe = spi_imx_probe,
1799
	.remove = spi_imx_remove,
1800
};
1801
module_platform_driver(spi_imx_driver);
1802

1803
MODULE_DESCRIPTION("i.MX SPI Controller driver");
1804 1805
MODULE_AUTHOR("Sascha Hauer, Pengutronix");
MODULE_LICENSE("GPL");
F
Fabio Estevam 已提交
1806
MODULE_ALIAS("platform:" DRIVER_NAME);