i915_gem.c 122.3 KB
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/*
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 * Copyright © 2008-2015 Intel Corporation
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eric Anholt <eric@anholt.net>
 *
 */

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#include <drm/drmP.h>
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#include <drm/drm_vma_manager.h>
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#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#include "i915_gem_dmabuf.h"
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#include "i915_vgpu.h"
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#include "i915_trace.h"
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#include "intel_drv.h"
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#include "intel_mocs.h"
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#include <linux/reservation.h>
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#include <linux/shmem_fs.h>
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#include <linux/slab.h>
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#include <linux/swap.h>
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#include <linux/pci.h>
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#include <linux/dma-buf.h>
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static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
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static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
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static bool cpu_cache_is_coherent(struct drm_device *dev,
				  enum i915_cache_level level)
{
	return HAS_LLC(dev) || level != I915_CACHE_NONE;
}

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static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
{
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	if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
		return false;

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	if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
		return true;

	return obj->pin_display;
}

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static int
insert_mappable_node(struct drm_i915_private *i915,
                     struct drm_mm_node *node, u32 size)
{
	memset(node, 0, sizeof(*node));
	return drm_mm_insert_node_in_range_generic(&i915->ggtt.base.mm, node,
						   size, 0, 0, 0,
						   i915->ggtt.mappable_end,
						   DRM_MM_SEARCH_DEFAULT,
						   DRM_MM_CREATE_DEFAULT);
}

static void
remove_mappable_node(struct drm_mm_node *node)
{
	drm_mm_remove_node(node);
}

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/* some bookkeeping */
static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
				  size_t size)
{
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	spin_lock(&dev_priv->mm.object_stat_lock);
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	dev_priv->mm.object_count++;
	dev_priv->mm.object_memory += size;
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	spin_unlock(&dev_priv->mm.object_stat_lock);
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}

static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
				     size_t size)
{
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	spin_lock(&dev_priv->mm.object_stat_lock);
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	dev_priv->mm.object_count--;
	dev_priv->mm.object_memory -= size;
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	spin_unlock(&dev_priv->mm.object_stat_lock);
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}

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static int
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i915_gem_wait_for_error(struct i915_gpu_error *error)
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{
	int ret;

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	if (!i915_reset_in_progress(error))
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		return 0;

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	/*
	 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
	 * userspace. If it takes that long something really bad is going on and
	 * we should simply try to bail out and fail as gracefully as possible.
	 */
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	ret = wait_event_interruptible_timeout(error->reset_queue,
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					       !i915_reset_in_progress(error),
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					       10*HZ);
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	if (ret == 0) {
		DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
		return -EIO;
	} else if (ret < 0) {
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		return ret;
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	} else {
		return 0;
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	}
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}

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int i915_mutex_lock_interruptible(struct drm_device *dev)
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{
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	struct drm_i915_private *dev_priv = to_i915(dev);
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	int ret;

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	ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
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	if (ret)
		return ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

	return 0;
}
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int
i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
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			    struct drm_file *file)
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{
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	struct drm_i915_private *dev_priv = to_i915(dev);
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	struct i915_ggtt *ggtt = &dev_priv->ggtt;
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	struct drm_i915_gem_get_aperture *args = data;
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	struct i915_vma *vma;
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	size_t pinned;
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	pinned = 0;
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	mutex_lock(&dev->struct_mutex);
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	list_for_each_entry(vma, &ggtt->base.active_list, vm_link)
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		if (vma->pin_count)
			pinned += vma->node.size;
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	list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link)
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		if (vma->pin_count)
			pinned += vma->node.size;
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	mutex_unlock(&dev->struct_mutex);
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	args->aper_size = ggtt->base.total;
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	args->aper_available_size = args->aper_size - pinned;
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	return 0;
}

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static int
i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
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{
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	struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
	char *vaddr = obj->phys_handle->vaddr;
	struct sg_table *st;
	struct scatterlist *sg;
	int i;
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	if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
		return -EINVAL;

	for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
		struct page *page;
		char *src;

		page = shmem_read_mapping_page(mapping, i);
		if (IS_ERR(page))
			return PTR_ERR(page);

		src = kmap_atomic(page);
		memcpy(vaddr, src, PAGE_SIZE);
		drm_clflush_virt_range(vaddr, PAGE_SIZE);
		kunmap_atomic(src);

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		put_page(page);
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		vaddr += PAGE_SIZE;
	}

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	i915_gem_chipset_flush(to_i915(obj->base.dev));
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	st = kmalloc(sizeof(*st), GFP_KERNEL);
	if (st == NULL)
		return -ENOMEM;

	if (sg_alloc_table(st, 1, GFP_KERNEL)) {
		kfree(st);
		return -ENOMEM;
	}

	sg = st->sgl;
	sg->offset = 0;
	sg->length = obj->base.size;
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	sg_dma_address(sg) = obj->phys_handle->busaddr;
	sg_dma_len(sg) = obj->base.size;

	obj->pages = st;
	return 0;
}

static void
i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj)
{
	int ret;

	BUG_ON(obj->madv == __I915_MADV_PURGED);
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	ret = i915_gem_object_set_to_cpu_domain(obj, true);
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	if (WARN_ON(ret)) {
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		/* In the event of a disaster, abandon all caches and
		 * hope for the best.
		 */
		obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
	}

	if (obj->madv == I915_MADV_DONTNEED)
		obj->dirty = 0;

	if (obj->dirty) {
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		struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
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		char *vaddr = obj->phys_handle->vaddr;
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		int i;

		for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
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			struct page *page;
			char *dst;

			page = shmem_read_mapping_page(mapping, i);
			if (IS_ERR(page))
				continue;

			dst = kmap_atomic(page);
			drm_clflush_virt_range(vaddr, PAGE_SIZE);
			memcpy(dst, vaddr, PAGE_SIZE);
			kunmap_atomic(dst);

			set_page_dirty(page);
			if (obj->madv == I915_MADV_WILLNEED)
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				mark_page_accessed(page);
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			put_page(page);
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			vaddr += PAGE_SIZE;
		}
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		obj->dirty = 0;
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	}

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	sg_free_table(obj->pages);
	kfree(obj->pages);
}

static void
i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
{
	drm_pci_free(obj->base.dev, obj->phys_handle);
}

static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
	.get_pages = i915_gem_object_get_pages_phys,
	.put_pages = i915_gem_object_put_pages_phys,
	.release = i915_gem_object_release_phys,
};

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int
i915_gem_object_unbind(struct drm_i915_gem_object *obj)
{
	struct i915_vma *vma;
	LIST_HEAD(still_in_list);
	int ret;

	/* The vma will only be freed if it is marked as closed, and if we wait
	 * upon rendering to the vma, we may unbind anything in the list.
	 */
	while ((vma = list_first_entry_or_null(&obj->vma_list,
					       struct i915_vma,
					       obj_link))) {
		list_move_tail(&vma->obj_link, &still_in_list);
		ret = i915_vma_unbind(vma);
		if (ret)
			break;
	}
	list_splice(&still_in_list, &obj->vma_list);

	return ret;
}

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int
i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
			    int align)
{
	drm_dma_handle_t *phys;
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	int ret;
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	if (obj->phys_handle) {
		if ((unsigned long)obj->phys_handle->vaddr & (align -1))
			return -EBUSY;

		return 0;
	}

	if (obj->madv != I915_MADV_WILLNEED)
		return -EFAULT;

	if (obj->base.filp == NULL)
		return -EINVAL;

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	ret = i915_gem_object_unbind(obj);
	if (ret)
		return ret;

	ret = i915_gem_object_put_pages(obj);
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	if (ret)
		return ret;

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	/* create a new object */
	phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
	if (!phys)
		return -ENOMEM;

	obj->phys_handle = phys;
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	obj->ops = &i915_gem_phys_ops;

	return i915_gem_object_get_pages(obj);
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}

static int
i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
		     struct drm_i915_gem_pwrite *args,
		     struct drm_file *file_priv)
{
	struct drm_device *dev = obj->base.dev;
	void *vaddr = obj->phys_handle->vaddr + args->offset;
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	char __user *user_data = u64_to_user_ptr(args->data_ptr);
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	int ret = 0;
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	/* We manually control the domain here and pretend that it
	 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
	 */
	ret = i915_gem_object_wait_rendering(obj, false);
	if (ret)
		return ret;
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	intel_fb_obj_invalidate(obj, ORIGIN_CPU);
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	if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
		unsigned long unwritten;

		/* The physical object once assigned is fixed for the lifetime
		 * of the obj, so we can safely drop the lock and continue
		 * to access vaddr.
		 */
		mutex_unlock(&dev->struct_mutex);
		unwritten = copy_from_user(vaddr, user_data, args->size);
		mutex_lock(&dev->struct_mutex);
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		if (unwritten) {
			ret = -EFAULT;
			goto out;
		}
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	}

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	drm_clflush_virt_range(vaddr, args->size);
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	i915_gem_chipset_flush(to_i915(dev));
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out:
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	intel_fb_obj_flush(obj, false, ORIGIN_CPU);
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	return ret;
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}

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void *i915_gem_object_alloc(struct drm_device *dev)
{
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	struct drm_i915_private *dev_priv = to_i915(dev);
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	return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL);
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}

void i915_gem_object_free(struct drm_i915_gem_object *obj)
{
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	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
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	kmem_cache_free(dev_priv->objects, obj);
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}

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static int
i915_gem_create(struct drm_file *file,
		struct drm_device *dev,
		uint64_t size,
		uint32_t *handle_p)
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{
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	struct drm_i915_gem_object *obj;
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	int ret;
	u32 handle;
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	size = roundup(size, PAGE_SIZE);
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	if (size == 0)
		return -EINVAL;
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	/* Allocate the new object */
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	obj = i915_gem_object_create(dev, size);
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	if (IS_ERR(obj))
		return PTR_ERR(obj);
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	ret = drm_gem_handle_create(file, &obj->base, &handle);
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	/* drop reference from allocate - handle holds it now */
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	i915_gem_object_put_unlocked(obj);
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	if (ret)
		return ret;
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	*handle_p = handle;
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	return 0;
}

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int
i915_gem_dumb_create(struct drm_file *file,
		     struct drm_device *dev,
		     struct drm_mode_create_dumb *args)
{
	/* have to work out size/pitch and return them */
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	args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
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	args->size = args->pitch * args->height;
	return i915_gem_create(file, dev,
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			       args->size, &args->handle);
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}

/**
 * Creates a new mm object and returns a handle to it.
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 * @dev: drm device pointer
 * @data: ioctl data blob
 * @file: drm file pointer
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 */
int
i915_gem_create_ioctl(struct drm_device *dev, void *data,
		      struct drm_file *file)
{
	struct drm_i915_gem_create *args = data;
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	return i915_gem_create(file, dev,
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			       args->size, &args->handle);
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}

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static inline int
__copy_to_user_swizzled(char __user *cpu_vaddr,
			const char *gpu_vaddr, int gpu_offset,
			int length)
{
	int ret, cpu_offset = 0;

	while (length > 0) {
		int cacheline_end = ALIGN(gpu_offset + 1, 64);
		int this_length = min(cacheline_end - gpu_offset, length);
		int swizzled_gpu_offset = gpu_offset ^ 64;

		ret = __copy_to_user(cpu_vaddr + cpu_offset,
				     gpu_vaddr + swizzled_gpu_offset,
				     this_length);
		if (ret)
			return ret + length;

		cpu_offset += this_length;
		gpu_offset += this_length;
		length -= this_length;
	}

	return 0;
}

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static inline int
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__copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
			  const char __user *cpu_vaddr,
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			  int length)
{
	int ret, cpu_offset = 0;

	while (length > 0) {
		int cacheline_end = ALIGN(gpu_offset + 1, 64);
		int this_length = min(cacheline_end - gpu_offset, length);
		int swizzled_gpu_offset = gpu_offset ^ 64;

		ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
				       cpu_vaddr + cpu_offset,
				       this_length);
		if (ret)
			return ret + length;

		cpu_offset += this_length;
		gpu_offset += this_length;
		length -= this_length;
	}

	return 0;
}

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/*
 * Pins the specified object's pages and synchronizes the object with
 * GPU accesses. Sets needs_clflush to non-zero if the caller should
 * flush the object from the CPU cache.
 */
int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
				    int *needs_clflush)
{
	int ret;

	*needs_clflush = 0;

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	if (WARN_ON(!i915_gem_object_has_struct_page(obj)))
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		return -EINVAL;

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	ret = i915_gem_object_wait_rendering(obj, true);
	if (ret)
		return ret;

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	if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
		/* If we're not in the cpu read domain, set ourself into the gtt
		 * read domain and manually flush cachelines (if required). This
		 * optimizes for the case when the gpu will dirty the data
		 * anyway again before the next pread happens. */
		*needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
							obj->cache_level);
	}

	ret = i915_gem_object_get_pages(obj);
	if (ret)
		return ret;

	i915_gem_object_pin_pages(obj);

	return ret;
}

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/* Per-page copy function for the shmem pread fastpath.
 * Flushes invalid cachelines before reading the target if
 * needs_clflush is set. */
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static int
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shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
		 char __user *user_data,
		 bool page_do_bit17_swizzling, bool needs_clflush)
{
	char *vaddr;
	int ret;

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	if (unlikely(page_do_bit17_swizzling))
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		return -EINVAL;

	vaddr = kmap_atomic(page);
	if (needs_clflush)
		drm_clflush_virt_range(vaddr + shmem_page_offset,
				       page_length);
	ret = __copy_to_user_inatomic(user_data,
				      vaddr + shmem_page_offset,
				      page_length);
	kunmap_atomic(vaddr);

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	return ret ? -EFAULT : 0;
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}

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static void
shmem_clflush_swizzled_range(char *addr, unsigned long length,
			     bool swizzled)
{
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	if (unlikely(swizzled)) {
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		unsigned long start = (unsigned long) addr;
		unsigned long end = (unsigned long) addr + length;

		/* For swizzling simply ensure that we always flush both
		 * channels. Lame, but simple and it works. Swizzled
		 * pwrite/pread is far from a hotpath - current userspace
		 * doesn't use it at all. */
		start = round_down(start, 128);
		end = round_up(end, 128);

		drm_clflush_virt_range((void *)start, end - start);
	} else {
		drm_clflush_virt_range(addr, length);
	}

}

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/* Only difference to the fast-path function is that this can handle bit17
 * and uses non-atomic copy and kmap functions. */
static int
shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
		 char __user *user_data,
		 bool page_do_bit17_swizzling, bool needs_clflush)
{
	char *vaddr;
	int ret;

	vaddr = kmap(page);
	if (needs_clflush)
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		shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
					     page_length,
					     page_do_bit17_swizzling);
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	if (page_do_bit17_swizzling)
		ret = __copy_to_user_swizzled(user_data,
					      vaddr, shmem_page_offset,
					      page_length);
	else
		ret = __copy_to_user(user_data,
				     vaddr + shmem_page_offset,
				     page_length);
	kunmap(page);

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	return ret ? - EFAULT : 0;
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}

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static inline unsigned long
slow_user_access(struct io_mapping *mapping,
		 uint64_t page_base, int page_offset,
		 char __user *user_data,
		 unsigned long length, bool pwrite)
{
	void __iomem *ioaddr;
	void *vaddr;
	uint64_t unwritten;

	ioaddr = io_mapping_map_wc(mapping, page_base, PAGE_SIZE);
	/* We can use the cpu mem copy function because this is X86. */
	vaddr = (void __force *)ioaddr + page_offset;
	if (pwrite)
		unwritten = __copy_from_user(vaddr, user_data, length);
	else
		unwritten = __copy_to_user(user_data, vaddr, length);

	io_mapping_unmap(ioaddr);
	return unwritten;
}

static int
i915_gem_gtt_pread(struct drm_device *dev,
		   struct drm_i915_gem_object *obj, uint64_t size,
		   uint64_t data_offset, uint64_t data_ptr)
{
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	struct drm_i915_private *dev_priv = to_i915(dev);
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	struct i915_ggtt *ggtt = &dev_priv->ggtt;
	struct drm_mm_node node;
	char __user *user_data;
	uint64_t remain;
	uint64_t offset;
	int ret;

	ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
	if (ret) {
		ret = insert_mappable_node(dev_priv, &node, PAGE_SIZE);
		if (ret)
			goto out;

		ret = i915_gem_object_get_pages(obj);
		if (ret) {
			remove_mappable_node(&node);
			goto out;
		}

		i915_gem_object_pin_pages(obj);
	} else {
		node.start = i915_gem_obj_ggtt_offset(obj);
		node.allocated = false;
		ret = i915_gem_object_put_fence(obj);
		if (ret)
			goto out_unpin;
	}

	ret = i915_gem_object_set_to_gtt_domain(obj, false);
	if (ret)
		goto out_unpin;

	user_data = u64_to_user_ptr(data_ptr);
	remain = size;
	offset = data_offset;

	mutex_unlock(&dev->struct_mutex);
	if (likely(!i915.prefault_disable)) {
		ret = fault_in_multipages_writeable(user_data, remain);
		if (ret) {
			mutex_lock(&dev->struct_mutex);
			goto out_unpin;
		}
	}

	while (remain > 0) {
		/* Operation in this page
		 *
		 * page_base = page offset within aperture
		 * page_offset = offset within page
		 * page_length = bytes to copy for this page
		 */
		u32 page_base = node.start;
		unsigned page_offset = offset_in_page(offset);
		unsigned page_length = PAGE_SIZE - page_offset;
		page_length = remain < page_length ? remain : page_length;
		if (node.allocated) {
			wmb();
			ggtt->base.insert_page(&ggtt->base,
					       i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
					       node.start,
					       I915_CACHE_NONE, 0);
			wmb();
		} else {
			page_base += offset & PAGE_MASK;
		}
		/* This is a slow read/write as it tries to read from
		 * and write to user memory which may result into page
		 * faults, and so we cannot perform this under struct_mutex.
		 */
		if (slow_user_access(ggtt->mappable, page_base,
				     page_offset, user_data,
				     page_length, false)) {
			ret = -EFAULT;
			break;
		}

		remain -= page_length;
		user_data += page_length;
		offset += page_length;
	}

	mutex_lock(&dev->struct_mutex);
	if (ret == 0 && (obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) {
		/* The user has modified the object whilst we tried
		 * reading from it, and we now have no idea what domain
		 * the pages should be in. As we have just been touching
		 * them directly, flush everything back to the GTT
		 * domain.
		 */
		ret = i915_gem_object_set_to_gtt_domain(obj, false);
	}

out_unpin:
	if (node.allocated) {
		wmb();
		ggtt->base.clear_range(&ggtt->base,
				       node.start, node.size,
				       true);
		i915_gem_object_unpin_pages(obj);
		remove_mappable_node(&node);
	} else {
		i915_gem_object_ggtt_unpin(obj);
	}
out:
	return ret;
}

756
static int
757 758 759 760
i915_gem_shmem_pread(struct drm_device *dev,
		     struct drm_i915_gem_object *obj,
		     struct drm_i915_gem_pread *args,
		     struct drm_file *file)
761
{
762
	char __user *user_data;
763
	ssize_t remain;
764
	loff_t offset;
765
	int shmem_page_offset, page_length, ret = 0;
766
	int obj_do_bit17_swizzling, page_do_bit17_swizzling;
767
	int prefaulted = 0;
768
	int needs_clflush = 0;
769
	struct sg_page_iter sg_iter;
770

771
	if (!i915_gem_object_has_struct_page(obj))
772 773
		return -ENODEV;

774
	user_data = u64_to_user_ptr(args->data_ptr);
775 776
	remain = args->size;

777
	obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
778

779
	ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
780 781 782
	if (ret)
		return ret;

783
	offset = args->offset;
784

785 786
	for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
			 offset >> PAGE_SHIFT) {
787
		struct page *page = sg_page_iter_page(&sg_iter);
788 789 790 791

		if (remain <= 0)
			break;

792 793 794 795 796
		/* Operation in this page
		 *
		 * shmem_page_offset = offset within page in shmem file
		 * page_length = bytes to copy for this page
		 */
797
		shmem_page_offset = offset_in_page(offset);
798 799 800 801
		page_length = remain;
		if ((shmem_page_offset + page_length) > PAGE_SIZE)
			page_length = PAGE_SIZE - shmem_page_offset;

802 803 804
		page_do_bit17_swizzling = obj_do_bit17_swizzling &&
			(page_to_phys(page) & (1 << 17)) != 0;

805 806 807 808 809
		ret = shmem_pread_fast(page, shmem_page_offset, page_length,
				       user_data, page_do_bit17_swizzling,
				       needs_clflush);
		if (ret == 0)
			goto next_page;
810 811 812

		mutex_unlock(&dev->struct_mutex);

813
		if (likely(!i915.prefault_disable) && !prefaulted) {
814
			ret = fault_in_multipages_writeable(user_data, remain);
815 816 817 818 819 820 821
			/* Userspace is tricking us, but we've already clobbered
			 * its pages with the prefault and promised to write the
			 * data up to the first fault. Hence ignore any errors
			 * and just continue. */
			(void)ret;
			prefaulted = 1;
		}
822

823 824 825
		ret = shmem_pread_slow(page, shmem_page_offset, page_length,
				       user_data, page_do_bit17_swizzling,
				       needs_clflush);
826

827
		mutex_lock(&dev->struct_mutex);
828 829

		if (ret)
830 831
			goto out;

832
next_page:
833
		remain -= page_length;
834
		user_data += page_length;
835 836 837
		offset += page_length;
	}

838
out:
839 840
	i915_gem_object_unpin_pages(obj);

841 842 843
	return ret;
}

844 845
/**
 * Reads data from the object referenced by handle.
846 847 848
 * @dev: drm device pointer
 * @data: ioctl data blob
 * @file: drm file pointer
849 850 851 852 853
 *
 * On error, the contents of *data are undefined.
 */
int
i915_gem_pread_ioctl(struct drm_device *dev, void *data,
854
		     struct drm_file *file)
855 856
{
	struct drm_i915_gem_pread *args = data;
857
	struct drm_i915_gem_object *obj;
858
	int ret = 0;
859

860 861 862 863
	if (args->size == 0)
		return 0;

	if (!access_ok(VERIFY_WRITE,
864
		       u64_to_user_ptr(args->data_ptr),
865 866 867
		       args->size))
		return -EFAULT;

868
	ret = i915_mutex_lock_interruptible(dev);
869
	if (ret)
870
		return ret;
871

872 873
	obj = i915_gem_object_lookup(file, args->handle);
	if (!obj) {
874 875
		ret = -ENOENT;
		goto unlock;
876
	}
877

878
	/* Bounds check source.  */
879 880
	if (args->offset > obj->base.size ||
	    args->size > obj->base.size - args->offset) {
C
Chris Wilson 已提交
881
		ret = -EINVAL;
882
		goto out;
C
Chris Wilson 已提交
883 884
	}

C
Chris Wilson 已提交
885 886
	trace_i915_gem_object_pread(obj, args->offset, args->size);

887
	ret = i915_gem_shmem_pread(dev, obj, args, file);
888

889 890 891 892 893
	/* pread for non shmem backed objects */
	if (ret == -EFAULT || ret == -ENODEV)
		ret = i915_gem_gtt_pread(dev, obj, args->size,
					args->offset, args->data_ptr);

894
out:
895
	i915_gem_object_put(obj);
896
unlock:
897
	mutex_unlock(&dev->struct_mutex);
898
	return ret;
899 900
}

901 902
/* This is the fast write path which cannot handle
 * page faults in the source data
903
 */
904 905 906 907 908 909

static inline int
fast_user_write(struct io_mapping *mapping,
		loff_t page_base, int page_offset,
		char __user *user_data,
		int length)
910
{
911 912
	void __iomem *vaddr_atomic;
	void *vaddr;
913
	unsigned long unwritten;
914

P
Peter Zijlstra 已提交
915
	vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
916 917 918
	/* We can use the cpu mem copy function because this is X86. */
	vaddr = (void __force*)vaddr_atomic + page_offset;
	unwritten = __copy_from_user_inatomic_nocache(vaddr,
919
						      user_data, length);
P
Peter Zijlstra 已提交
920
	io_mapping_unmap_atomic(vaddr_atomic);
921
	return unwritten;
922 923
}

924 925 926
/**
 * This is the fast pwrite path, where we copy the data directly from the
 * user into the GTT, uncached.
927
 * @i915: i915 device private data
928 929 930
 * @obj: i915 gem object
 * @args: pwrite arguments structure
 * @file: drm file pointer
931
 */
932
static int
933
i915_gem_gtt_pwrite_fast(struct drm_i915_private *i915,
934
			 struct drm_i915_gem_object *obj,
935
			 struct drm_i915_gem_pwrite *args,
936
			 struct drm_file *file)
937
{
938
	struct i915_ggtt *ggtt = &i915->ggtt;
939
	struct drm_device *dev = obj->base.dev;
940 941
	struct drm_mm_node node;
	uint64_t remain, offset;
942
	char __user *user_data;
943
	int ret;
944 945 946 947
	bool hit_slow_path = false;

	if (obj->tiling_mode != I915_TILING_NONE)
		return -EFAULT;
D
Daniel Vetter 已提交
948

949
	ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
950 951 952 953 954 955 956 957 958 959 960 961 962 963 964
	if (ret) {
		ret = insert_mappable_node(i915, &node, PAGE_SIZE);
		if (ret)
			goto out;

		ret = i915_gem_object_get_pages(obj);
		if (ret) {
			remove_mappable_node(&node);
			goto out;
		}

		i915_gem_object_pin_pages(obj);
	} else {
		node.start = i915_gem_obj_ggtt_offset(obj);
		node.allocated = false;
965 966 967
		ret = i915_gem_object_put_fence(obj);
		if (ret)
			goto out_unpin;
968
	}
D
Daniel Vetter 已提交
969 970 971 972 973

	ret = i915_gem_object_set_to_gtt_domain(obj, true);
	if (ret)
		goto out_unpin;

974
	intel_fb_obj_invalidate(obj, ORIGIN_GTT);
975
	obj->dirty = true;
976

977 978 979 980
	user_data = u64_to_user_ptr(args->data_ptr);
	offset = args->offset;
	remain = args->size;
	while (remain) {
981 982
		/* Operation in this page
		 *
983 984 985
		 * page_base = page offset within aperture
		 * page_offset = offset within page
		 * page_length = bytes to copy for this page
986
		 */
987 988 989 990 991 992 993 994 995 996 997 998 999
		u32 page_base = node.start;
		unsigned page_offset = offset_in_page(offset);
		unsigned page_length = PAGE_SIZE - page_offset;
		page_length = remain < page_length ? remain : page_length;
		if (node.allocated) {
			wmb(); /* flush the write before we modify the GGTT */
			ggtt->base.insert_page(&ggtt->base,
					       i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
					       node.start, I915_CACHE_NONE, 0);
			wmb(); /* flush modifications to the GGTT (insert_page) */
		} else {
			page_base += offset & PAGE_MASK;
		}
1000
		/* If we get a fault while copying data, then (presumably) our
1001 1002
		 * source page isn't available.  Return the error and we'll
		 * retry in the slow path.
1003 1004
		 * If the object is non-shmem backed, we retry again with the
		 * path that handles page fault.
1005
		 */
1006
		if (fast_user_write(ggtt->mappable, page_base,
D
Daniel Vetter 已提交
1007
				    page_offset, user_data, page_length)) {
1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019
			hit_slow_path = true;
			mutex_unlock(&dev->struct_mutex);
			if (slow_user_access(ggtt->mappable,
					     page_base,
					     page_offset, user_data,
					     page_length, true)) {
				ret = -EFAULT;
				mutex_lock(&dev->struct_mutex);
				goto out_flush;
			}

			mutex_lock(&dev->struct_mutex);
D
Daniel Vetter 已提交
1020
		}
1021

1022 1023 1024
		remain -= page_length;
		user_data += page_length;
		offset += page_length;
1025 1026
	}

1027
out_flush:
1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040
	if (hit_slow_path) {
		if (ret == 0 &&
		    (obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) {
			/* The user has modified the object whilst we tried
			 * reading from it, and we now have no idea what domain
			 * the pages should be in. As we have just been touching
			 * them directly, flush everything back to the GTT
			 * domain.
			 */
			ret = i915_gem_object_set_to_gtt_domain(obj, false);
		}
	}

1041
	intel_fb_obj_flush(obj, false, ORIGIN_GTT);
D
Daniel Vetter 已提交
1042
out_unpin:
1043 1044 1045 1046 1047 1048 1049 1050 1051 1052
	if (node.allocated) {
		wmb();
		ggtt->base.clear_range(&ggtt->base,
				       node.start, node.size,
				       true);
		i915_gem_object_unpin_pages(obj);
		remove_mappable_node(&node);
	} else {
		i915_gem_object_ggtt_unpin(obj);
	}
D
Daniel Vetter 已提交
1053
out:
1054
	return ret;
1055 1056
}

1057 1058 1059 1060
/* Per-page copy function for the shmem pwrite fastpath.
 * Flushes invalid cachelines before writing to the target if
 * needs_clflush_before is set and flushes out any written cachelines after
 * writing if needs_clflush is set. */
1061
static int
1062 1063 1064 1065 1066
shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
		  char __user *user_data,
		  bool page_do_bit17_swizzling,
		  bool needs_clflush_before,
		  bool needs_clflush_after)
1067
{
1068
	char *vaddr;
1069
	int ret;
1070

1071
	if (unlikely(page_do_bit17_swizzling))
1072
		return -EINVAL;
1073

1074 1075 1076 1077
	vaddr = kmap_atomic(page);
	if (needs_clflush_before)
		drm_clflush_virt_range(vaddr + shmem_page_offset,
				       page_length);
1078 1079
	ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
					user_data, page_length);
1080 1081 1082 1083
	if (needs_clflush_after)
		drm_clflush_virt_range(vaddr + shmem_page_offset,
				       page_length);
	kunmap_atomic(vaddr);
1084

1085
	return ret ? -EFAULT : 0;
1086 1087
}

1088 1089
/* Only difference to the fast-path function is that this can handle bit17
 * and uses non-atomic copy and kmap functions. */
1090
static int
1091 1092 1093 1094 1095
shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
		  char __user *user_data,
		  bool page_do_bit17_swizzling,
		  bool needs_clflush_before,
		  bool needs_clflush_after)
1096
{
1097 1098
	char *vaddr;
	int ret;
1099

1100
	vaddr = kmap(page);
1101
	if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
1102 1103 1104
		shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
					     page_length,
					     page_do_bit17_swizzling);
1105 1106
	if (page_do_bit17_swizzling)
		ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
1107 1108
						user_data,
						page_length);
1109 1110 1111 1112 1113
	else
		ret = __copy_from_user(vaddr + shmem_page_offset,
				       user_data,
				       page_length);
	if (needs_clflush_after)
1114 1115 1116
		shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
					     page_length,
					     page_do_bit17_swizzling);
1117
	kunmap(page);
1118

1119
	return ret ? -EFAULT : 0;
1120 1121 1122
}

static int
1123 1124 1125 1126
i915_gem_shmem_pwrite(struct drm_device *dev,
		      struct drm_i915_gem_object *obj,
		      struct drm_i915_gem_pwrite *args,
		      struct drm_file *file)
1127 1128
{
	ssize_t remain;
1129 1130
	loff_t offset;
	char __user *user_data;
1131
	int shmem_page_offset, page_length, ret = 0;
1132
	int obj_do_bit17_swizzling, page_do_bit17_swizzling;
1133
	int hit_slowpath = 0;
1134 1135
	int needs_clflush_after = 0;
	int needs_clflush_before = 0;
1136
	struct sg_page_iter sg_iter;
1137

1138
	user_data = u64_to_user_ptr(args->data_ptr);
1139 1140
	remain = args->size;

1141
	obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
1142

1143 1144 1145 1146
	ret = i915_gem_object_wait_rendering(obj, false);
	if (ret)
		return ret;

1147 1148 1149 1150 1151
	if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
		/* If we're not in the cpu write domain, set ourself into the gtt
		 * write domain and manually flush cachelines (if required). This
		 * optimizes for the case when the gpu will use the data
		 * right away and we therefore have to clflush anyway. */
1152
		needs_clflush_after = cpu_write_needs_clflush(obj);
1153
	}
1154 1155 1156 1157 1158
	/* Same trick applies to invalidate partially written cachelines read
	 * before writing. */
	if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
		needs_clflush_before =
			!cpu_cache_is_coherent(dev, obj->cache_level);
1159

1160 1161 1162 1163
	ret = i915_gem_object_get_pages(obj);
	if (ret)
		return ret;

1164
	intel_fb_obj_invalidate(obj, ORIGIN_CPU);
1165

1166 1167
	i915_gem_object_pin_pages(obj);

1168
	offset = args->offset;
1169
	obj->dirty = 1;
1170

1171 1172
	for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
			 offset >> PAGE_SHIFT) {
1173
		struct page *page = sg_page_iter_page(&sg_iter);
1174
		int partial_cacheline_write;
1175

1176 1177 1178
		if (remain <= 0)
			break;

1179 1180 1181 1182 1183
		/* Operation in this page
		 *
		 * shmem_page_offset = offset within page in shmem file
		 * page_length = bytes to copy for this page
		 */
1184
		shmem_page_offset = offset_in_page(offset);
1185 1186 1187 1188 1189

		page_length = remain;
		if ((shmem_page_offset + page_length) > PAGE_SIZE)
			page_length = PAGE_SIZE - shmem_page_offset;

1190 1191 1192 1193 1194 1195 1196
		/* If we don't overwrite a cacheline completely we need to be
		 * careful to have up-to-date data by first clflushing. Don't
		 * overcomplicate things and flush the entire patch. */
		partial_cacheline_write = needs_clflush_before &&
			((shmem_page_offset | page_length)
				& (boot_cpu_data.x86_clflush_size - 1));

1197 1198 1199
		page_do_bit17_swizzling = obj_do_bit17_swizzling &&
			(page_to_phys(page) & (1 << 17)) != 0;

1200 1201 1202 1203 1204 1205
		ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
					user_data, page_do_bit17_swizzling,
					partial_cacheline_write,
					needs_clflush_after);
		if (ret == 0)
			goto next_page;
1206 1207 1208

		hit_slowpath = 1;
		mutex_unlock(&dev->struct_mutex);
1209 1210 1211 1212
		ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
					user_data, page_do_bit17_swizzling,
					partial_cacheline_write,
					needs_clflush_after);
1213

1214
		mutex_lock(&dev->struct_mutex);
1215 1216

		if (ret)
1217 1218
			goto out;

1219
next_page:
1220
		remain -= page_length;
1221
		user_data += page_length;
1222
		offset += page_length;
1223 1224
	}

1225
out:
1226 1227
	i915_gem_object_unpin_pages(obj);

1228
	if (hit_slowpath) {
1229 1230 1231 1232 1233 1234 1235
		/*
		 * Fixup: Flush cpu caches in case we didn't flush the dirty
		 * cachelines in-line while writing and the object moved
		 * out of the cpu write domain while we've dropped the lock.
		 */
		if (!needs_clflush_after &&
		    obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1236
			if (i915_gem_clflush_object(obj, obj->pin_display))
1237
				needs_clflush_after = true;
1238
		}
1239
	}
1240

1241
	if (needs_clflush_after)
1242
		i915_gem_chipset_flush(to_i915(dev));
1243 1244
	else
		obj->cache_dirty = true;
1245

1246
	intel_fb_obj_flush(obj, false, ORIGIN_CPU);
1247
	return ret;
1248 1249 1250 1251
}

/**
 * Writes data to the object referenced by handle.
1252 1253 1254
 * @dev: drm device
 * @data: ioctl data blob
 * @file: drm file
1255 1256 1257 1258 1259
 *
 * On error, the contents of the buffer that were to be modified are undefined.
 */
int
i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1260
		      struct drm_file *file)
1261
{
1262
	struct drm_i915_private *dev_priv = to_i915(dev);
1263
	struct drm_i915_gem_pwrite *args = data;
1264
	struct drm_i915_gem_object *obj;
1265 1266 1267 1268 1269 1270
	int ret;

	if (args->size == 0)
		return 0;

	if (!access_ok(VERIFY_READ,
1271
		       u64_to_user_ptr(args->data_ptr),
1272 1273 1274
		       args->size))
		return -EFAULT;

1275
	if (likely(!i915.prefault_disable)) {
1276
		ret = fault_in_multipages_readable(u64_to_user_ptr(args->data_ptr),
1277 1278 1279 1280
						   args->size);
		if (ret)
			return -EFAULT;
	}
1281

1282 1283
	intel_runtime_pm_get(dev_priv);

1284
	ret = i915_mutex_lock_interruptible(dev);
1285
	if (ret)
1286
		goto put_rpm;
1287

1288 1289
	obj = i915_gem_object_lookup(file, args->handle);
	if (!obj) {
1290 1291
		ret = -ENOENT;
		goto unlock;
1292
	}
1293

1294
	/* Bounds check destination. */
1295 1296
	if (args->offset > obj->base.size ||
	    args->size > obj->base.size - args->offset) {
C
Chris Wilson 已提交
1297
		ret = -EINVAL;
1298
		goto out;
C
Chris Wilson 已提交
1299 1300
	}

C
Chris Wilson 已提交
1301 1302
	trace_i915_gem_object_pwrite(obj, args->offset, args->size);

D
Daniel Vetter 已提交
1303
	ret = -EFAULT;
1304 1305 1306 1307 1308 1309
	/* We can only do the GTT pwrite on untiled buffers, as otherwise
	 * it would end up going through the fenced access, and we'll get
	 * different detiling behavior between reading and writing.
	 * pread/pwrite currently are reading and writing from the CPU
	 * perspective, requiring manual detiling by the client.
	 */
1310 1311
	if (!i915_gem_object_has_struct_page(obj) ||
	    cpu_write_needs_clflush(obj)) {
1312
		ret = i915_gem_gtt_pwrite_fast(dev_priv, obj, args, file);
D
Daniel Vetter 已提交
1313 1314 1315
		/* Note that the gtt paths might fail with non-page-backed user
		 * pointers (e.g. gtt mappings when moving data between
		 * textures). Fallback to the shmem path in that case. */
1316
	}
1317

1318
	if (ret == -EFAULT || ret == -ENOSPC) {
1319 1320
		if (obj->phys_handle)
			ret = i915_gem_phys_pwrite(obj, args, file);
1321
		else if (i915_gem_object_has_struct_page(obj))
1322
			ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1323 1324
		else
			ret = -ENODEV;
1325
	}
1326

1327
out:
1328
	i915_gem_object_put(obj);
1329
unlock:
1330
	mutex_unlock(&dev->struct_mutex);
1331 1332 1333
put_rpm:
	intel_runtime_pm_put(dev_priv);

1334 1335 1336
	return ret;
}

1337 1338 1339
/**
 * Ensures that all rendering to the object has completed and the object is
 * safe to unbind from the GTT or access from the CPU.
1340 1341
 * @obj: i915 gem object
 * @readonly: waiting for read access or write
1342
 */
1343
int
1344 1345 1346
i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
			       bool readonly)
{
1347
	struct reservation_object *resv;
C
Chris Wilson 已提交
1348 1349 1350
	struct i915_gem_active *active;
	unsigned long active_mask;
	int idx, ret;
1351

C
Chris Wilson 已提交
1352 1353 1354 1355 1356
	lockdep_assert_held(&obj->base.dev->struct_mutex);

	if (!readonly) {
		active = obj->last_read;
		active_mask = obj->active;
1357
	} else {
C
Chris Wilson 已提交
1358 1359 1360
		active_mask = 1;
		active = &obj->last_write;
	}
1361

C
Chris Wilson 已提交
1362
	for_each_active(active_mask, idx) {
1363 1364
		ret = i915_gem_active_wait(&active[idx],
					   &obj->base.dev->struct_mutex);
C
Chris Wilson 已提交
1365 1366
		if (ret)
			return ret;
1367 1368
	}

1369 1370 1371 1372 1373 1374 1375 1376 1377 1378
	resv = i915_gem_object_get_dmabuf_resv(obj);
	if (resv) {
		long err;

		err = reservation_object_wait_timeout_rcu(resv, !readonly, true,
							  MAX_SCHEDULE_TIMEOUT);
		if (err < 0)
			return err;
	}

1379 1380 1381
	return 0;
}

1382 1383 1384 1385 1386
/* A nonblocking variant of the above wait. This is a highly dangerous routine
 * as the object state may change during this call.
 */
static __must_check int
i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1387
					    struct intel_rps_client *rps,
1388 1389 1390
					    bool readonly)
{
	struct drm_device *dev = obj->base.dev;
1391
	struct drm_i915_private *dev_priv = to_i915(dev);
1392
	struct drm_i915_gem_request *requests[I915_NUM_ENGINES];
C
Chris Wilson 已提交
1393 1394
	struct i915_gem_active *active;
	unsigned long active_mask;
1395
	int ret, i, n = 0;
1396 1397 1398 1399

	BUG_ON(!mutex_is_locked(&dev->struct_mutex));
	BUG_ON(!dev_priv->mm.interruptible);

C
Chris Wilson 已提交
1400 1401
	active_mask = obj->active;
	if (!active_mask)
1402 1403
		return 0;

C
Chris Wilson 已提交
1404 1405
	if (!readonly) {
		active = obj->last_read;
1406
	} else {
C
Chris Wilson 已提交
1407 1408 1409
		active_mask = 1;
		active = &obj->last_write;
	}
1410

C
Chris Wilson 已提交
1411 1412
	for_each_active(active_mask, i) {
		struct drm_i915_gem_request *req;
1413

C
Chris Wilson 已提交
1414 1415 1416
		req = i915_gem_active_get(&active[i],
					  &obj->base.dev->struct_mutex);
		if (req)
1417
			requests[n++] = req;
1418 1419
	}

1420
	mutex_unlock(&dev->struct_mutex);
1421
	ret = 0;
1422
	for (i = 0; ret == 0 && i < n; i++)
1423
		ret = i915_wait_request(requests[i], true, NULL, rps);
1424 1425
	mutex_lock(&dev->struct_mutex);

1426
	for (i = 0; i < n; i++)
1427
		i915_gem_request_put(requests[i]);
1428 1429

	return ret;
1430 1431
}

1432 1433 1434 1435 1436 1437
static struct intel_rps_client *to_rps_client(struct drm_file *file)
{
	struct drm_i915_file_private *fpriv = file->driver_priv;
	return &fpriv->rps;
}

1438 1439 1440 1441 1442 1443 1444
static enum fb_op_origin
write_origin(struct drm_i915_gem_object *obj, unsigned domain)
{
	return domain == I915_GEM_DOMAIN_GTT && !obj->has_wc_mmap ?
	       ORIGIN_GTT : ORIGIN_CPU;
}

1445
/**
1446 1447
 * Called when user space prepares to use an object with the CPU, either
 * through the mmap ioctl's mapping or a GTT mapping.
1448 1449 1450
 * @dev: drm device
 * @data: ioctl data blob
 * @file: drm file
1451 1452 1453
 */
int
i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1454
			  struct drm_file *file)
1455 1456
{
	struct drm_i915_gem_set_domain *args = data;
1457
	struct drm_i915_gem_object *obj;
1458 1459
	uint32_t read_domains = args->read_domains;
	uint32_t write_domain = args->write_domain;
1460 1461
	int ret;

1462
	/* Only handle setting domains to types used by the CPU. */
1463
	if (write_domain & I915_GEM_GPU_DOMAINS)
1464 1465
		return -EINVAL;

1466
	if (read_domains & I915_GEM_GPU_DOMAINS)
1467 1468 1469 1470 1471 1472 1473 1474
		return -EINVAL;

	/* Having something in the write domain implies it's in the read
	 * domain, and only that read domain.  Enforce that in the request.
	 */
	if (write_domain != 0 && read_domains != write_domain)
		return -EINVAL;

1475
	ret = i915_mutex_lock_interruptible(dev);
1476
	if (ret)
1477
		return ret;
1478

1479 1480
	obj = i915_gem_object_lookup(file, args->handle);
	if (!obj) {
1481 1482
		ret = -ENOENT;
		goto unlock;
1483
	}
1484

1485 1486 1487 1488
	/* Try to flush the object off the GPU without holding the lock.
	 * We will repeat the flush holding the lock in the normal manner
	 * to catch cases where we are gazumped.
	 */
1489
	ret = i915_gem_object_wait_rendering__nonblocking(obj,
1490
							  to_rps_client(file),
1491
							  !write_domain);
1492 1493 1494
	if (ret)
		goto unref;

1495
	if (read_domains & I915_GEM_DOMAIN_GTT)
1496
		ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1497
	else
1498
		ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1499

1500
	if (write_domain != 0)
1501
		intel_fb_obj_invalidate(obj, write_origin(obj, write_domain));
1502

1503
unref:
1504
	i915_gem_object_put(obj);
1505
unlock:
1506 1507 1508 1509 1510 1511
	mutex_unlock(&dev->struct_mutex);
	return ret;
}

/**
 * Called when user space has done writes to this buffer
1512 1513 1514
 * @dev: drm device
 * @data: ioctl data blob
 * @file: drm file
1515 1516 1517
 */
int
i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1518
			 struct drm_file *file)
1519 1520
{
	struct drm_i915_gem_sw_finish *args = data;
1521
	struct drm_i915_gem_object *obj;
1522 1523
	int ret = 0;

1524
	ret = i915_mutex_lock_interruptible(dev);
1525
	if (ret)
1526
		return ret;
1527

1528 1529
	obj = i915_gem_object_lookup(file, args->handle);
	if (!obj) {
1530 1531
		ret = -ENOENT;
		goto unlock;
1532 1533 1534
	}

	/* Pinned buffers may be scanout, so flush the cache */
1535
	if (obj->pin_display)
1536
		i915_gem_object_flush_cpu_write_domain(obj);
1537

1538
	i915_gem_object_put(obj);
1539
unlock:
1540 1541 1542 1543 1544
	mutex_unlock(&dev->struct_mutex);
	return ret;
}

/**
1545 1546 1547 1548 1549
 * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address
 *			 it is mapped to.
 * @dev: drm device
 * @data: ioctl data blob
 * @file: drm file
1550 1551 1552
 *
 * While the mapping holds a reference on the contents of the object, it doesn't
 * imply a ref on the object itself.
1553 1554 1555 1556 1557 1558 1559 1560 1561 1562
 *
 * IMPORTANT:
 *
 * DRM driver writers who look a this function as an example for how to do GEM
 * mmap support, please don't implement mmap support like here. The modern way
 * to implement DRM mmap support is with an mmap offset ioctl (like
 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
 * That way debug tooling like valgrind will understand what's going on, hiding
 * the mmap call in a driver private ioctl will break that. The i915 driver only
 * does cpu mmaps this way because we didn't know better.
1563 1564 1565
 */
int
i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1566
		    struct drm_file *file)
1567 1568
{
	struct drm_i915_gem_mmap *args = data;
1569
	struct drm_i915_gem_object *obj;
1570 1571
	unsigned long addr;

1572 1573 1574
	if (args->flags & ~(I915_MMAP_WC))
		return -EINVAL;

1575
	if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT))
1576 1577
		return -ENODEV;

1578 1579
	obj = i915_gem_object_lookup(file, args->handle);
	if (!obj)
1580
		return -ENOENT;
1581

1582 1583 1584
	/* prime objects have no backing filp to GEM mmap
	 * pages from.
	 */
1585
	if (!obj->base.filp) {
1586
		i915_gem_object_put_unlocked(obj);
1587 1588 1589
		return -EINVAL;
	}

1590
	addr = vm_mmap(obj->base.filp, 0, args->size,
1591 1592
		       PROT_READ | PROT_WRITE, MAP_SHARED,
		       args->offset);
1593 1594 1595 1596
	if (args->flags & I915_MMAP_WC) {
		struct mm_struct *mm = current->mm;
		struct vm_area_struct *vma;

1597
		if (down_write_killable(&mm->mmap_sem)) {
1598
			i915_gem_object_put_unlocked(obj);
1599 1600
			return -EINTR;
		}
1601 1602 1603 1604 1605 1606 1607
		vma = find_vma(mm, addr);
		if (vma)
			vma->vm_page_prot =
				pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
		else
			addr = -ENOMEM;
		up_write(&mm->mmap_sem);
1608 1609

		/* This may race, but that's ok, it only gets set */
1610
		WRITE_ONCE(obj->has_wc_mmap, true);
1611
	}
1612
	i915_gem_object_put_unlocked(obj);
1613 1614 1615 1616 1617 1618 1619 1620
	if (IS_ERR((void *)addr))
		return addr;

	args->addr_ptr = (uint64_t) addr;

	return 0;
}

1621 1622
/**
 * i915_gem_fault - fault a page into the GTT
1623 1624
 * @vma: VMA in question
 * @vmf: fault info
1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638
 *
 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
 * from userspace.  The fault handler takes care of binding the object to
 * the GTT (if needed), allocating and programming a fence register (again,
 * only if needed based on whether the old reg is still valid or the object
 * is tiled) and inserting a new PTE into the faulting process.
 *
 * Note that the faulting process may involve evicting existing objects
 * from the GTT and/or fence registers to make room.  So performance may
 * suffer if the GTT working set is large or there are few fence registers
 * left.
 */
int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
{
1639 1640
	struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
	struct drm_device *dev = obj->base.dev;
1641 1642
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct i915_ggtt *ggtt = &dev_priv->ggtt;
1643
	struct i915_ggtt_view view = i915_ggtt_view_normal;
1644 1645 1646
	pgoff_t page_offset;
	unsigned long pfn;
	int ret = 0;
1647
	bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1648

1649 1650
	intel_runtime_pm_get(dev_priv);

1651 1652 1653 1654
	/* We don't use vmf->pgoff since that has the fake offset */
	page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
		PAGE_SHIFT;

1655 1656 1657
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		goto out;
1658

C
Chris Wilson 已提交
1659 1660
	trace_i915_gem_object_fault(obj, page_offset, true, write);

1661 1662 1663 1664 1665 1666 1667 1668 1669
	/* Try to flush the object off the GPU first without holding the lock.
	 * Upon reacquiring the lock, we will perform our sanity checks and then
	 * repeat the flush holding the lock in the normal manner to catch cases
	 * where we are gazumped.
	 */
	ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
	if (ret)
		goto unlock;

1670 1671
	/* Access to snoopable pages through the GTT is incoherent. */
	if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1672
		ret = -EFAULT;
1673 1674 1675
		goto unlock;
	}

1676
	/* Use a partial view if the object is bigger than the aperture. */
1677
	if (obj->base.size >= ggtt->mappable_end &&
1678
	    obj->tiling_mode == I915_TILING_NONE) {
1679
		static const unsigned int chunk_size = 256; // 1 MiB
1680

1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692
		memset(&view, 0, sizeof(view));
		view.type = I915_GGTT_VIEW_PARTIAL;
		view.params.partial.offset = rounddown(page_offset, chunk_size);
		view.params.partial.size =
			min_t(unsigned int,
			      chunk_size,
			      (vma->vm_end - vma->vm_start)/PAGE_SIZE -
			      view.params.partial.offset);
	}

	/* Now pin it into the GTT if needed */
	ret = i915_gem_object_ggtt_pin(obj, &view, 0, PIN_MAPPABLE);
1693 1694
	if (ret)
		goto unlock;
1695

1696 1697 1698
	ret = i915_gem_object_set_to_gtt_domain(obj, write);
	if (ret)
		goto unpin;
1699

1700
	ret = i915_gem_object_get_fence(obj);
1701
	if (ret)
1702
		goto unpin;
1703

1704
	/* Finally, remap it using the new GTT offset */
1705
	pfn = ggtt->mappable_base +
1706
		i915_gem_obj_ggtt_offset_view(obj, &view);
1707
	pfn >>= PAGE_SHIFT;
1708

1709 1710 1711 1712 1713 1714 1715 1716 1717
	if (unlikely(view.type == I915_GGTT_VIEW_PARTIAL)) {
		/* Overriding existing pages in partial view does not cause
		 * us any trouble as TLBs are still valid because the fault
		 * is due to userspace losing part of the mapping or never
		 * having accessed it before (at this partials' range).
		 */
		unsigned long base = vma->vm_start +
				     (view.params.partial.offset << PAGE_SHIFT);
		unsigned int i;
1718

1719 1720
		for (i = 0; i < view.params.partial.size; i++) {
			ret = vm_insert_pfn(vma, base + i * PAGE_SIZE, pfn + i);
1721 1722 1723 1724 1725
			if (ret)
				break;
		}

		obj->fault_mappable = true;
1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746
	} else {
		if (!obj->fault_mappable) {
			unsigned long size = min_t(unsigned long,
						   vma->vm_end - vma->vm_start,
						   obj->base.size);
			int i;

			for (i = 0; i < size >> PAGE_SHIFT; i++) {
				ret = vm_insert_pfn(vma,
						    (unsigned long)vma->vm_start + i * PAGE_SIZE,
						    pfn + i);
				if (ret)
					break;
			}

			obj->fault_mappable = true;
		} else
			ret = vm_insert_pfn(vma,
					    (unsigned long)vmf->virtual_address,
					    pfn + page_offset);
	}
1747
unpin:
1748
	i915_gem_object_ggtt_unpin_view(obj, &view);
1749
unlock:
1750
	mutex_unlock(&dev->struct_mutex);
1751
out:
1752
	switch (ret) {
1753
	case -EIO:
1754 1755 1756 1757 1758 1759 1760
		/*
		 * We eat errors when the gpu is terminally wedged to avoid
		 * userspace unduly crashing (gl has no provisions for mmaps to
		 * fail). But any other -EIO isn't ours (e.g. swap in failure)
		 * and so needs to be reported.
		 */
		if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1761 1762 1763
			ret = VM_FAULT_SIGBUS;
			break;
		}
1764
	case -EAGAIN:
D
Daniel Vetter 已提交
1765 1766 1767 1768
		/*
		 * EAGAIN means the gpu is hung and we'll wait for the error
		 * handler to reset everything when re-faulting in
		 * i915_mutex_lock_interruptible.
1769
		 */
1770 1771
	case 0:
	case -ERESTARTSYS:
1772
	case -EINTR:
1773 1774 1775 1776 1777
	case -EBUSY:
		/*
		 * EBUSY is ok: this just means that another thread
		 * already did the job.
		 */
1778 1779
		ret = VM_FAULT_NOPAGE;
		break;
1780
	case -ENOMEM:
1781 1782
		ret = VM_FAULT_OOM;
		break;
1783
	case -ENOSPC:
1784
	case -EFAULT:
1785 1786
		ret = VM_FAULT_SIGBUS;
		break;
1787
	default:
1788
		WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1789 1790
		ret = VM_FAULT_SIGBUS;
		break;
1791
	}
1792 1793 1794

	intel_runtime_pm_put(dev_priv);
	return ret;
1795 1796
}

1797 1798 1799 1800
/**
 * i915_gem_release_mmap - remove physical page mappings
 * @obj: obj in question
 *
1801
 * Preserve the reservation of the mmapping with the DRM core code, but
1802 1803 1804 1805 1806 1807 1808 1809 1810
 * relinquish ownership of the pages back to the system.
 *
 * It is vital that we remove the page mapping if we have mapped a tiled
 * object through the GTT and then lose the fence register due to
 * resource pressure. Similarly if the object has been moved out of the
 * aperture, than pages mapped into userspace must be revoked. Removing the
 * mapping will then trigger a page fault on the next user access, allowing
 * fixup by i915_gem_fault().
 */
1811
void
1812
i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1813
{
1814 1815 1816 1817 1818 1819
	/* Serialisation between user GTT access and our code depends upon
	 * revoking the CPU's PTE whilst the mutex is held. The next user
	 * pagefault then has to wait until we release the mutex.
	 */
	lockdep_assert_held(&obj->base.dev->struct_mutex);

1820 1821
	if (!obj->fault_mappable)
		return;
1822

1823 1824
	drm_vma_node_unmap(&obj->base.vma_node,
			   obj->base.dev->anon_inode->i_mapping);
1825 1826 1827 1828 1829 1830 1831 1832 1833 1834

	/* Ensure that the CPU's PTE are revoked and there are not outstanding
	 * memory transactions from userspace before we return. The TLB
	 * flushing implied above by changing the PTE above *should* be
	 * sufficient, an extra barrier here just provides us with a bit
	 * of paranoid documentation about our requirement to serialise
	 * memory writes before touching registers / GSM.
	 */
	wmb();

1835
	obj->fault_mappable = false;
1836 1837
}

1838 1839 1840 1841 1842 1843 1844 1845 1846
void
i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
{
	struct drm_i915_gem_object *obj;

	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
		i915_gem_release_mmap(obj);
}

1847
uint32_t
1848
i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1849
{
1850
	uint32_t gtt_size;
1851 1852

	if (INTEL_INFO(dev)->gen >= 4 ||
1853 1854
	    tiling_mode == I915_TILING_NONE)
		return size;
1855 1856

	/* Previous chips need a power-of-two fence region when tiling */
1857
	if (IS_GEN3(dev))
1858
		gtt_size = 1024*1024;
1859
	else
1860
		gtt_size = 512*1024;
1861

1862 1863
	while (gtt_size < size)
		gtt_size <<= 1;
1864

1865
	return gtt_size;
1866 1867
}

1868 1869
/**
 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1870 1871 1872 1873
 * @dev: drm device
 * @size: object size
 * @tiling_mode: tiling mode
 * @fenced: is fenced alignemned required or not
1874 1875
 *
 * Return the required GTT alignment for an object, taking into account
1876
 * potential fence register mapping.
1877
 */
1878 1879 1880
uint32_t
i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
			   int tiling_mode, bool fenced)
1881 1882 1883 1884 1885
{
	/*
	 * Minimum alignment is 4k (GTT page size), but might be greater
	 * if a fence register is needed for the object.
	 */
1886
	if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1887
	    tiling_mode == I915_TILING_NONE)
1888 1889
		return 4096;

1890 1891 1892 1893
	/*
	 * Previous chips need to be aligned to the size of the smallest
	 * fence register that can contain the object.
	 */
1894
	return i915_gem_get_gtt_size(dev, size, tiling_mode);
1895 1896
}

1897 1898
static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
{
1899
	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
1900 1901
	int ret;

1902 1903
	dev_priv->mm.shrinker_no_lock_stealing = true;

1904 1905
	ret = drm_gem_create_mmap_offset(&obj->base);
	if (ret != -ENOSPC)
1906
		goto out;
1907 1908 1909 1910 1911 1912 1913 1914

	/* Badly fragmented mmap space? The only way we can recover
	 * space is by destroying unwanted objects. We can't randomly release
	 * mmap_offsets as userspace expects them to be persistent for the
	 * lifetime of the objects. The closest we can is to release the
	 * offsets on purgeable objects by truncating it and marking it purged,
	 * which prevents userspace from ever using that object again.
	 */
1915 1916 1917 1918 1919
	i915_gem_shrink(dev_priv,
			obj->base.size >> PAGE_SHIFT,
			I915_SHRINK_BOUND |
			I915_SHRINK_UNBOUND |
			I915_SHRINK_PURGEABLE);
1920 1921
	ret = drm_gem_create_mmap_offset(&obj->base);
	if (ret != -ENOSPC)
1922
		goto out;
1923 1924

	i915_gem_shrink_all(dev_priv);
1925 1926 1927 1928 1929
	ret = drm_gem_create_mmap_offset(&obj->base);
out:
	dev_priv->mm.shrinker_no_lock_stealing = false;

	return ret;
1930 1931 1932 1933 1934 1935 1936
}

static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
{
	drm_gem_free_mmap_offset(&obj->base);
}

1937
int
1938 1939
i915_gem_mmap_gtt(struct drm_file *file,
		  struct drm_device *dev,
1940
		  uint32_t handle,
1941
		  uint64_t *offset)
1942
{
1943
	struct drm_i915_gem_object *obj;
1944 1945
	int ret;

1946
	ret = i915_mutex_lock_interruptible(dev);
1947
	if (ret)
1948
		return ret;
1949

1950 1951
	obj = i915_gem_object_lookup(file, handle);
	if (!obj) {
1952 1953 1954
		ret = -ENOENT;
		goto unlock;
	}
1955

1956
	if (obj->madv != I915_MADV_WILLNEED) {
1957
		DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1958
		ret = -EFAULT;
1959
		goto out;
1960 1961
	}

1962 1963 1964
	ret = i915_gem_object_create_mmap_offset(obj);
	if (ret)
		goto out;
1965

1966
	*offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1967

1968
out:
1969
	i915_gem_object_put(obj);
1970
unlock:
1971
	mutex_unlock(&dev->struct_mutex);
1972
	return ret;
1973 1974
}

1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995
/**
 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
 * @dev: DRM device
 * @data: GTT mapping ioctl data
 * @file: GEM object info
 *
 * Simply returns the fake offset to userspace so it can mmap it.
 * The mmap call will end up in drm_gem_mmap(), which will set things
 * up so we can get faults in the handler above.
 *
 * The fault handler will take care of binding the object into the GTT
 * (since it may have been evicted to make room for something), allocating
 * a fence register, and mapping the appropriate aperture address into
 * userspace.
 */
int
i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file)
{
	struct drm_i915_gem_mmap_gtt *args = data;

1996
	return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1997 1998
}

D
Daniel Vetter 已提交
1999 2000 2001
/* Immediately discard the backing storage */
static void
i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2002
{
2003
	i915_gem_object_free_mmap_offset(obj);
2004

2005 2006
	if (obj->base.filp == NULL)
		return;
2007

D
Daniel Vetter 已提交
2008 2009 2010 2011 2012
	/* Our goal here is to return as much of the memory as
	 * is possible back to the system as we are called from OOM.
	 * To do this we must instruct the shmfs to drop all of its
	 * backing pages, *now*.
	 */
2013
	shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
D
Daniel Vetter 已提交
2014 2015
	obj->madv = __I915_MADV_PURGED;
}
2016

2017 2018 2019
/* Try to discard unwanted pages */
static void
i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
D
Daniel Vetter 已提交
2020
{
2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034
	struct address_space *mapping;

	switch (obj->madv) {
	case I915_MADV_DONTNEED:
		i915_gem_object_truncate(obj);
	case __I915_MADV_PURGED:
		return;
	}

	if (obj->base.filp == NULL)
		return;

	mapping = file_inode(obj->base.filp)->i_mapping,
	invalidate_mapping_pages(mapping, 0, (loff_t)-1);
2035 2036
}

2037
static void
2038
i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
2039
{
2040 2041
	struct sgt_iter sgt_iter;
	struct page *page;
2042
	int ret;
2043

2044
	BUG_ON(obj->madv == __I915_MADV_PURGED);
2045

C
Chris Wilson 已提交
2046
	ret = i915_gem_object_set_to_cpu_domain(obj, true);
2047
	if (WARN_ON(ret)) {
C
Chris Wilson 已提交
2048 2049 2050
		/* In the event of a disaster, abandon all caches and
		 * hope for the best.
		 */
2051
		i915_gem_clflush_object(obj, true);
C
Chris Wilson 已提交
2052 2053 2054
		obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
	}

I
Imre Deak 已提交
2055 2056
	i915_gem_gtt_finish_object(obj);

2057
	if (i915_gem_object_needs_bit17_swizzle(obj))
2058 2059
		i915_gem_object_save_bit_17_swizzle(obj);

2060 2061
	if (obj->madv == I915_MADV_DONTNEED)
		obj->dirty = 0;
2062

2063
	for_each_sgt_page(page, sgt_iter, obj->pages) {
2064
		if (obj->dirty)
2065
			set_page_dirty(page);
2066

2067
		if (obj->madv == I915_MADV_WILLNEED)
2068
			mark_page_accessed(page);
2069

2070
		put_page(page);
2071
	}
2072
	obj->dirty = 0;
2073

2074 2075
	sg_free_table(obj->pages);
	kfree(obj->pages);
2076
}
C
Chris Wilson 已提交
2077

2078
int
2079 2080 2081 2082
i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
{
	const struct drm_i915_gem_object_ops *ops = obj->ops;

2083
	if (obj->pages == NULL)
2084 2085
		return 0;

2086 2087 2088
	if (obj->pages_pin_count)
		return -EBUSY;

2089
	GEM_BUG_ON(obj->bind_count);
B
Ben Widawsky 已提交
2090

2091 2092 2093
	/* ->put_pages might need to allocate memory for the bit17 swizzle
	 * array, hence protect them from being reaped by removing them from gtt
	 * lists early. */
2094
	list_del(&obj->global_list);
2095

2096
	if (obj->mapping) {
2097 2098 2099 2100
		if (is_vmalloc_addr(obj->mapping))
			vunmap(obj->mapping);
		else
			kunmap(kmap_to_page(obj->mapping));
2101 2102 2103
		obj->mapping = NULL;
	}

2104
	ops->put_pages(obj);
2105
	obj->pages = NULL;
2106

2107
	i915_gem_object_invalidate(obj);
C
Chris Wilson 已提交
2108 2109 2110 2111

	return 0;
}

2112
static int
C
Chris Wilson 已提交
2113
i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2114
{
2115
	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2116 2117
	int page_count, i;
	struct address_space *mapping;
2118 2119
	struct sg_table *st;
	struct scatterlist *sg;
2120
	struct sgt_iter sgt_iter;
2121
	struct page *page;
2122
	unsigned long last_pfn = 0;	/* suppress gcc warning */
I
Imre Deak 已提交
2123
	int ret;
C
Chris Wilson 已提交
2124
	gfp_t gfp;
2125

C
Chris Wilson 已提交
2126 2127 2128 2129 2130 2131 2132
	/* Assert that the object is not currently in any GPU domain. As it
	 * wasn't in the GTT, there shouldn't be any way it could have been in
	 * a GPU cache
	 */
	BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
	BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);

2133 2134 2135 2136
	st = kmalloc(sizeof(*st), GFP_KERNEL);
	if (st == NULL)
		return -ENOMEM;

2137
	page_count = obj->base.size / PAGE_SIZE;
2138 2139
	if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
		kfree(st);
2140
		return -ENOMEM;
2141
	}
2142

2143 2144 2145 2146 2147
	/* Get the list of pages out of our struct file.  They'll be pinned
	 * at this point until we release them.
	 *
	 * Fail silently without starting the shrinker
	 */
A
Al Viro 已提交
2148
	mapping = file_inode(obj->base.filp)->i_mapping;
2149
	gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM));
2150
	gfp |= __GFP_NORETRY | __GFP_NOWARN;
2151 2152 2153
	sg = st->sgl;
	st->nents = 0;
	for (i = 0; i < page_count; i++) {
C
Chris Wilson 已提交
2154 2155
		page = shmem_read_mapping_page_gfp(mapping, i, gfp);
		if (IS_ERR(page)) {
2156 2157 2158 2159 2160
			i915_gem_shrink(dev_priv,
					page_count,
					I915_SHRINK_BOUND |
					I915_SHRINK_UNBOUND |
					I915_SHRINK_PURGEABLE);
C
Chris Wilson 已提交
2161 2162 2163 2164 2165 2166 2167 2168
			page = shmem_read_mapping_page_gfp(mapping, i, gfp);
		}
		if (IS_ERR(page)) {
			/* We've tried hard to allocate the memory by reaping
			 * our own buffer, now let the real VM do its job and
			 * go down in flames if truly OOM.
			 */
			i915_gem_shrink_all(dev_priv);
2169
			page = shmem_read_mapping_page(mapping, i);
I
Imre Deak 已提交
2170 2171
			if (IS_ERR(page)) {
				ret = PTR_ERR(page);
C
Chris Wilson 已提交
2172
				goto err_pages;
I
Imre Deak 已提交
2173
			}
C
Chris Wilson 已提交
2174
		}
2175 2176 2177 2178 2179 2180 2181 2182
#ifdef CONFIG_SWIOTLB
		if (swiotlb_nr_tbl()) {
			st->nents++;
			sg_set_page(sg, page, PAGE_SIZE, 0);
			sg = sg_next(sg);
			continue;
		}
#endif
2183 2184 2185 2186 2187 2188 2189 2190 2191
		if (!i || page_to_pfn(page) != last_pfn + 1) {
			if (i)
				sg = sg_next(sg);
			st->nents++;
			sg_set_page(sg, page, PAGE_SIZE, 0);
		} else {
			sg->length += PAGE_SIZE;
		}
		last_pfn = page_to_pfn(page);
2192 2193 2194

		/* Check that the i965g/gm workaround works. */
		WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2195
	}
2196 2197 2198 2199
#ifdef CONFIG_SWIOTLB
	if (!swiotlb_nr_tbl())
#endif
		sg_mark_end(sg);
2200 2201
	obj->pages = st;

I
Imre Deak 已提交
2202 2203 2204 2205
	ret = i915_gem_gtt_prepare_object(obj);
	if (ret)
		goto err_pages;

2206
	if (i915_gem_object_needs_bit17_swizzle(obj))
2207 2208
		i915_gem_object_do_bit_17_swizzle(obj);

2209 2210 2211 2212
	if (obj->tiling_mode != I915_TILING_NONE &&
	    dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
		i915_gem_object_pin_pages(obj);

2213 2214 2215
	return 0;

err_pages:
2216
	sg_mark_end(sg);
2217 2218
	for_each_sgt_page(page, sgt_iter, st)
		put_page(page);
2219 2220
	sg_free_table(st);
	kfree(st);
2221 2222 2223 2224 2225 2226 2227 2228 2229

	/* shmemfs first checks if there is enough memory to allocate the page
	 * and reports ENOSPC should there be insufficient, along with the usual
	 * ENOMEM for a genuine allocation failure.
	 *
	 * We use ENOSPC in our driver to mean that we have run out of aperture
	 * space and so want to translate the error from shmemfs back to our
	 * usual understanding of ENOMEM.
	 */
I
Imre Deak 已提交
2230 2231 2232 2233
	if (ret == -ENOSPC)
		ret = -ENOMEM;

	return ret;
2234 2235
}

2236 2237 2238 2239 2240 2241 2242 2243 2244 2245
/* Ensure that the associated pages are gathered from the backing storage
 * and pinned into our object. i915_gem_object_get_pages() may be called
 * multiple times before they are released by a single call to
 * i915_gem_object_put_pages() - once the pages are no longer referenced
 * either as a result of memory pressure (reaping pages under the shrinker)
 * or as the object is itself released.
 */
int
i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
{
2246
	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2247 2248 2249
	const struct drm_i915_gem_object_ops *ops = obj->ops;
	int ret;

2250
	if (obj->pages)
2251 2252
		return 0;

2253
	if (obj->madv != I915_MADV_WILLNEED) {
2254
		DRM_DEBUG("Attempting to obtain a purgeable object\n");
2255
		return -EFAULT;
2256 2257
	}

2258 2259
	BUG_ON(obj->pages_pin_count);

2260 2261 2262 2263
	ret = ops->get_pages(obj);
	if (ret)
		return ret;

2264
	list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2265 2266 2267 2268

	obj->get_page.sg = obj->pages->sgl;
	obj->get_page.last = 0;

2269
	return 0;
2270 2271
}

2272 2273 2274 2275 2276
/* The 'mapping' part of i915_gem_object_pin_map() below */
static void *i915_gem_object_map(const struct drm_i915_gem_object *obj)
{
	unsigned long n_pages = obj->base.size >> PAGE_SHIFT;
	struct sg_table *sgt = obj->pages;
2277 2278
	struct sgt_iter sgt_iter;
	struct page *page;
2279 2280
	struct page *stack_pages[32];
	struct page **pages = stack_pages;
2281 2282 2283 2284 2285 2286 2287
	unsigned long i = 0;
	void *addr;

	/* A single page can always be kmapped */
	if (n_pages == 1)
		return kmap(sg_page(sgt->sgl));

2288 2289 2290 2291 2292 2293
	if (n_pages > ARRAY_SIZE(stack_pages)) {
		/* Too big for stack -- allocate temporary array instead */
		pages = drm_malloc_gfp(n_pages, sizeof(*pages), GFP_TEMPORARY);
		if (!pages)
			return NULL;
	}
2294

2295 2296
	for_each_sgt_page(page, sgt_iter, sgt)
		pages[i++] = page;
2297 2298 2299 2300 2301 2302

	/* Check that we have the expected number of pages */
	GEM_BUG_ON(i != n_pages);

	addr = vmap(pages, n_pages, 0, PAGE_KERNEL);

2303 2304
	if (pages != stack_pages)
		drm_free_large(pages);
2305 2306 2307 2308 2309

	return addr;
}

/* get, pin, and map the pages of the object into kernel space */
2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321
void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj)
{
	int ret;

	lockdep_assert_held(&obj->base.dev->struct_mutex);

	ret = i915_gem_object_get_pages(obj);
	if (ret)
		return ERR_PTR(ret);

	i915_gem_object_pin_pages(obj);

2322 2323 2324
	if (!obj->mapping) {
		obj->mapping = i915_gem_object_map(obj);
		if (!obj->mapping) {
2325 2326 2327 2328 2329 2330 2331 2332
			i915_gem_object_unpin_pages(obj);
			return ERR_PTR(-ENOMEM);
		}
	}

	return obj->mapping;
}

2333
static void
2334 2335
i915_gem_object_retire__write(struct i915_gem_active *active,
			      struct drm_i915_gem_request *request)
B
Ben Widawsky 已提交
2336
{
2337 2338
	struct drm_i915_gem_object *obj =
		container_of(active, struct drm_i915_gem_object, last_write);
2339

2340
	intel_fb_obj_flush(obj, true, ORIGIN_CS);
B
Ben Widawsky 已提交
2341 2342
}

2343
static void
2344 2345
i915_gem_object_retire__read(struct i915_gem_active *active,
			     struct drm_i915_gem_request *request)
2346
{
2347 2348 2349
	int idx = request->engine->id;
	struct drm_i915_gem_object *obj =
		container_of(active, struct drm_i915_gem_object, last_read[idx]);
2350

2351
	GEM_BUG_ON((obj->active & (1 << idx)) == 0);
2352

2353
	obj->active &= ~(1 << idx);
2354 2355
	if (obj->active)
		return;
2356

2357 2358 2359 2360
	/* Bump our place on the bound list to keep it roughly in LRU order
	 * so that we don't steal from recently used but inactive objects
	 * (unless we are forced to ofc!)
	 */
2361 2362 2363
	if (obj->bind_count)
		list_move_tail(&obj->global_list,
			       &request->i915->mm.bound_list);
2364

2365
	i915_gem_object_put(obj);
2366 2367
}

2368
static bool i915_context_is_banned(const struct i915_gem_context *ctx)
2369
{
2370
	unsigned long elapsed;
2371

2372
	if (ctx->hang_stats.banned)
2373 2374
		return true;

2375
	elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2376 2377
	if (ctx->hang_stats.ban_period_seconds &&
	    elapsed <= ctx->hang_stats.ban_period_seconds) {
2378 2379
		DRM_DEBUG("context hanging too fast, banning!\n");
		return true;
2380 2381 2382 2383 2384
	}

	return false;
}

2385
static void i915_set_reset_status(struct i915_gem_context *ctx,
2386
				  const bool guilty)
2387
{
2388
	struct i915_ctx_hang_stats *hs = &ctx->hang_stats;
2389 2390

	if (guilty) {
2391
		hs->banned = i915_context_is_banned(ctx);
2392 2393 2394 2395
		hs->batch_active++;
		hs->guilty_ts = get_seconds();
	} else {
		hs->batch_pending++;
2396 2397 2398
	}
}

2399
struct drm_i915_gem_request *
2400
i915_gem_find_active_request(struct intel_engine_cs *engine)
2401
{
2402 2403
	struct drm_i915_gem_request *request;

2404 2405 2406 2407 2408 2409 2410 2411
	/* We are called by the error capture and reset at a random
	 * point in time. In particular, note that neither is crucially
	 * ordered with an interrupt. After a hang, the GPU is dead and we
	 * assume that no more writes can happen (we waited long enough for
	 * all writes that were in transaction to be flushed) - adding an
	 * extra delay for a recent interrupt is pointless. Hence, we do
	 * not need an engine->irq_seqno_barrier() before the seqno reads.
	 */
2412
	list_for_each_entry(request, &engine->request_list, link) {
2413
		if (i915_gem_request_completed(request))
2414
			continue;
2415

2416
		return request;
2417
	}
2418 2419 2420 2421

	return NULL;
}

2422
static void i915_gem_reset_engine_status(struct intel_engine_cs *engine)
2423 2424 2425 2426
{
	struct drm_i915_gem_request *request;
	bool ring_hung;

2427
	request = i915_gem_find_active_request(engine);
2428 2429 2430
	if (request == NULL)
		return;

2431
	ring_hung = engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2432

2433
	i915_set_reset_status(request->ctx, ring_hung);
2434
	list_for_each_entry_continue(request, &engine->request_list, link)
2435
		i915_set_reset_status(request->ctx, false);
2436
}
2437

2438
static void i915_gem_reset_engine_cleanup(struct intel_engine_cs *engine)
2439
{
2440
	struct intel_ring *ring;
2441

2442 2443 2444 2445
	/* Mark all pending requests as complete so that any concurrent
	 * (lockless) lookup doesn't try and wait upon the request as we
	 * reset it.
	 */
2446
	intel_engine_init_seqno(engine, engine->last_submitted_seqno);
2447

2448 2449 2450 2451 2452 2453
	/*
	 * Clear the execlists queue up before freeing the requests, as those
	 * are the ones that keep the context and ringbuffer backing objects
	 * pinned in place.
	 */

2454
	if (i915.enable_execlists) {
2455 2456
		/* Ensure irq handler finishes or is cancelled. */
		tasklet_kill(&engine->irq_tasklet);
2457

2458
		intel_execlists_cancel_requests(engine);
2459 2460
	}

2461 2462 2463 2464 2465 2466 2467
	/*
	 * We must free the requests after all the corresponding objects have
	 * been moved off active lists. Which is the same order as the normal
	 * retire_requests function does. This is important if object hold
	 * implicit references on things like e.g. ppgtt address spaces through
	 * the request.
	 */
2468
	if (!list_empty(&engine->request_list)) {
2469 2470
		struct drm_i915_gem_request *request;

2471 2472
		request = list_last_entry(&engine->request_list,
					  struct drm_i915_gem_request,
2473
					  link);
2474

2475
		i915_gem_request_retire_upto(request);
2476
	}
2477 2478 2479 2480 2481 2482 2483 2484

	/* Having flushed all requests from all queues, we know that all
	 * ringbuffers must now be empty. However, since we do not reclaim
	 * all space when retiring the request (to prevent HEADs colliding
	 * with rapid ringbuffer wraparound) the amount of available space
	 * upon reset is less than when we start. Do one more pass over
	 * all the ringbuffers to reset last_retired_head.
	 */
2485 2486 2487
	list_for_each_entry(ring, &engine->buffers, link) {
		ring->last_retired_head = ring->tail;
		intel_ring_update_space(ring);
2488
	}
2489

2490
	engine->i915->gt.active_engines &= ~intel_engine_flag(engine);
2491 2492
}

2493
void i915_gem_reset(struct drm_device *dev)
2494
{
2495
	struct drm_i915_private *dev_priv = to_i915(dev);
2496
	struct intel_engine_cs *engine;
2497

2498 2499 2500 2501 2502
	/*
	 * Before we free the objects from the requests, we need to inspect
	 * them for finding the guilty party. As the requests only borrow
	 * their reference to the objects, the inspection must be done first.
	 */
2503
	for_each_engine(engine, dev_priv)
2504
		i915_gem_reset_engine_status(engine);
2505

2506
	for_each_engine(engine, dev_priv)
2507
		i915_gem_reset_engine_cleanup(engine);
2508
	mod_delayed_work(dev_priv->wq, &dev_priv->gt.idle_work, 0);
2509

2510 2511
	i915_gem_context_reset(dev);

2512
	i915_gem_restore_fences(dev);
2513 2514
}

2515
static void
2516 2517
i915_gem_retire_work_handler(struct work_struct *work)
{
2518
	struct drm_i915_private *dev_priv =
2519
		container_of(work, typeof(*dev_priv), gt.retire_work.work);
2520
	struct drm_device *dev = &dev_priv->drm;
2521

2522
	/* Come back later if the device is busy... */
2523
	if (mutex_trylock(&dev->struct_mutex)) {
2524
		i915_gem_retire_requests(dev_priv);
2525
		mutex_unlock(&dev->struct_mutex);
2526
	}
2527 2528 2529 2530 2531

	/* Keep the retire handler running until we are finally idle.
	 * We do not need to do this test under locking as in the worst-case
	 * we queue the retire worker once too often.
	 */
2532 2533
	if (READ_ONCE(dev_priv->gt.awake)) {
		i915_queue_hangcheck(dev_priv);
2534 2535
		queue_delayed_work(dev_priv->wq,
				   &dev_priv->gt.retire_work,
2536
				   round_jiffies_up_relative(HZ));
2537
	}
2538
}
2539

2540 2541 2542 2543
static void
i915_gem_idle_work_handler(struct work_struct *work)
{
	struct drm_i915_private *dev_priv =
2544
		container_of(work, typeof(*dev_priv), gt.idle_work.work);
2545
	struct drm_device *dev = &dev_priv->drm;
2546
	struct intel_engine_cs *engine;
2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568
	unsigned int stuck_engines;
	bool rearm_hangcheck;

	if (!READ_ONCE(dev_priv->gt.awake))
		return;

	if (READ_ONCE(dev_priv->gt.active_engines))
		return;

	rearm_hangcheck =
		cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);

	if (!mutex_trylock(&dev->struct_mutex)) {
		/* Currently busy, come back later */
		mod_delayed_work(dev_priv->wq,
				 &dev_priv->gt.idle_work,
				 msecs_to_jiffies(50));
		goto out_rearm;
	}

	if (dev_priv->gt.active_engines)
		goto out_unlock;
2569

2570
	for_each_engine(engine, dev_priv)
2571
		i915_gem_batch_pool_fini(&engine->batch_pool);
2572

2573 2574 2575
	GEM_BUG_ON(!dev_priv->gt.awake);
	dev_priv->gt.awake = false;
	rearm_hangcheck = false;
2576

2577 2578 2579 2580
	/* As we have disabled hangcheck, we need to unstick any waiters still
	 * hanging around. However, as we may be racing against the interrupt
	 * handler or the waiters themselves, we skip enabling the fake-irq.
	 */
2581
	stuck_engines = intel_kick_waiters(dev_priv);
2582 2583 2584
	if (unlikely(stuck_engines))
		DRM_DEBUG_DRIVER("kicked stuck waiters (%x)...missed irq?\n",
				 stuck_engines);
2585

2586 2587 2588 2589 2590
	if (INTEL_GEN(dev_priv) >= 6)
		gen6_rps_idle(dev_priv);
	intel_runtime_pm_put(dev_priv);
out_unlock:
	mutex_unlock(&dev->struct_mutex);
2591

2592 2593 2594 2595
out_rearm:
	if (rearm_hangcheck) {
		GEM_BUG_ON(!dev_priv->gt.awake);
		i915_queue_hangcheck(dev_priv);
2596
	}
2597 2598
}

2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611
void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file)
{
	struct drm_i915_gem_object *obj = to_intel_bo(gem);
	struct drm_i915_file_private *fpriv = file->driver_priv;
	struct i915_vma *vma, *vn;

	mutex_lock(&obj->base.dev->struct_mutex);
	list_for_each_entry_safe(vma, vn, &obj->vma_list, obj_link)
		if (vma->vm->file == fpriv)
			i915_vma_close(vma);
	mutex_unlock(&obj->base.dev->struct_mutex);
}

2612 2613
/**
 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2614 2615 2616
 * @dev: drm device pointer
 * @data: ioctl data blob
 * @file: drm file pointer
2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640
 *
 * Returns 0 if successful, else an error is returned with the remaining time in
 * the timeout parameter.
 *  -ETIME: object is still busy after timeout
 *  -ERESTARTSYS: signal interrupted the wait
 *  -ENONENT: object doesn't exist
 * Also possible, but rare:
 *  -EAGAIN: GPU wedged
 *  -ENOMEM: damn
 *  -ENODEV: Internal IRQ fail
 *  -E?: The add request failed
 *
 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
 * non-zero timeout parameter the wait ioctl will wait for the given number of
 * nanoseconds on an object becoming unbusy. Since the wait itself does so
 * without holding struct_mutex the object may become re-busied before this
 * function completes. A similar but shorter * race condition exists in the busy
 * ioctl
 */
int
i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
{
	struct drm_i915_gem_wait *args = data;
	struct drm_i915_gem_object *obj;
2641
	struct drm_i915_gem_request *requests[I915_NUM_ENGINES];
2642 2643
	int i, n = 0;
	int ret;
2644

2645 2646 2647
	if (args->flags != 0)
		return -EINVAL;

2648 2649 2650 2651
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;

2652 2653
	obj = i915_gem_object_lookup(file, args->bo_handle);
	if (!obj) {
2654 2655 2656 2657
		mutex_unlock(&dev->struct_mutex);
		return -ENOENT;
	}

2658
	if (!obj->active)
2659
		goto out;
2660

2661
	for (i = 0; i < I915_NUM_ENGINES; i++) {
2662
		struct drm_i915_gem_request *req;
2663

2664 2665
		req = i915_gem_active_get(&obj->last_read[i],
					  &obj->base.dev->struct_mutex);
2666 2667
		if (req)
			requests[n++] = req;
2668 2669
	}

2670 2671
out:
	i915_gem_object_put(obj);
2672 2673
	mutex_unlock(&dev->struct_mutex);

2674 2675
	for (i = 0; i < n; i++) {
		if (ret == 0)
2676 2677 2678
			ret = i915_wait_request(requests[i], true,
						args->timeout_ns > 0 ? &args->timeout_ns : NULL,
						to_rps_client(file));
2679
		i915_gem_request_put(requests[i]);
2680
	}
2681
	return ret;
2682 2683
}

2684
static int
2685
__i915_gem_object_sync(struct drm_i915_gem_request *to,
2686
		       struct drm_i915_gem_request *from)
2687 2688 2689
{
	int ret;

2690
	if (to->engine == from->engine)
2691 2692
		return 0;

2693
	if (!i915.semaphores) {
2694 2695 2696 2697
		ret = i915_wait_request(from,
					from->i915->mm.interruptible,
					NULL,
					NO_WAITBOOST);
2698 2699 2700
		if (ret)
			return ret;
	} else {
2701
		int idx = intel_engine_sync_index(from->engine, to->engine);
2702
		if (from->fence.seqno <= from->engine->semaphore.sync_seqno[idx])
2703 2704
			return 0;

2705
		trace_i915_gem_ring_sync_to(to, from);
2706
		ret = to->engine->semaphore.sync_to(to, from);
2707 2708 2709
		if (ret)
			return ret;

2710
		from->engine->semaphore.sync_seqno[idx] = from->fence.seqno;
2711 2712 2713 2714 2715
	}

	return 0;
}

2716 2717 2718 2719
/**
 * i915_gem_object_sync - sync an object to a ring.
 *
 * @obj: object which may be in use on another ring.
2720
 * @to: request we are wishing to use
2721 2722
 *
 * This code is meant to abstract object synchronization with the GPU.
2723 2724 2725
 * Conceptually we serialise writes between engines inside the GPU.
 * We only allow one engine to write into a buffer at any time, but
 * multiple readers. To ensure each has a coherent view of memory, we must:
2726 2727 2728 2729 2730 2731 2732
 *
 * - If there is an outstanding write request to the object, the new
 *   request must wait for it to complete (either CPU or in hw, requests
 *   on the same ring will be naturally ordered).
 *
 * - If we are a write request (pending_write_domain is set), the new
 *   request must wait for outstanding read requests to complete.
2733 2734 2735
 *
 * Returns 0 if successful, else propagates up the lower layer error.
 */
2736 2737
int
i915_gem_object_sync(struct drm_i915_gem_object *obj,
2738
		     struct drm_i915_gem_request *to)
2739
{
C
Chris Wilson 已提交
2740 2741 2742
	struct i915_gem_active *active;
	unsigned long active_mask;
	int idx;
2743

C
Chris Wilson 已提交
2744
	lockdep_assert_held(&obj->base.dev->struct_mutex);
2745

C
Chris Wilson 已提交
2746 2747 2748
	active_mask = obj->active;
	if (!active_mask)
		return 0;
2749

C
Chris Wilson 已提交
2750 2751
	if (obj->base.pending_write_domain) {
		active = obj->last_read;
2752
	} else {
C
Chris Wilson 已提交
2753 2754
		active_mask = 1;
		active = &obj->last_write;
2755
	}
C
Chris Wilson 已提交
2756 2757 2758 2759 2760 2761 2762 2763 2764 2765

	for_each_active(active_mask, idx) {
		struct drm_i915_gem_request *request;
		int ret;

		request = i915_gem_active_peek(&active[idx],
					       &obj->base.dev->struct_mutex);
		if (!request)
			continue;

2766
		ret = __i915_gem_object_sync(to, request);
2767 2768 2769
		if (ret)
			return ret;
	}
2770

2771
	return 0;
2772 2773
}

2774 2775 2776 2777 2778 2779 2780
static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
{
	u32 old_write_domain, old_read_domains;

	/* Force a pagefault for domain tracking on next user access */
	i915_gem_release_mmap(obj);

2781 2782 2783
	if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
		return;

2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794
	old_read_domains = obj->base.read_domains;
	old_write_domain = obj->base.write_domain;

	obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
	obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;

	trace_i915_gem_object_change_domain(obj,
					    old_read_domains,
					    old_write_domain);
}

2795 2796 2797 2798 2799 2800 2801 2802 2803 2804 2805
static void __i915_vma_iounmap(struct i915_vma *vma)
{
	GEM_BUG_ON(vma->pin_count);

	if (vma->iomap == NULL)
		return;

	io_mapping_unmap(vma->iomap);
	vma->iomap = NULL;
}

2806
static int __i915_vma_unbind(struct i915_vma *vma, bool wait)
2807
{
2808
	struct drm_i915_gem_object *obj = vma->obj;
2809
	unsigned long active;
2810
	int ret;
2811

2812 2813 2814 2815 2816 2817 2818
	/* First wait upon any activity as retiring the request may
	 * have side-effects such as unpinning or even unbinding this vma.
	 */
	active = i915_vma_get_active(vma);
	if (active && wait) {
		int idx;

2819 2820 2821 2822 2823 2824 2825
		/* When a closed VMA is retired, it is unbound - eek.
		 * In order to prevent it from being recursively closed,
		 * take a pin on the vma so that the second unbind is
		 * aborted.
		 */
		vma->pin_count++;

2826 2827 2828 2829
		for_each_active(active, idx) {
			ret = i915_gem_active_retire(&vma->last_read[idx],
						   &vma->vm->dev->struct_mutex);
			if (ret)
2830
				break;
2831 2832
		}

2833 2834 2835 2836
		vma->pin_count--;
		if (ret)
			return ret;

2837 2838 2839 2840 2841 2842
		GEM_BUG_ON(i915_vma_is_active(vma));
	}

	if (vma->pin_count)
		return -EBUSY;

2843 2844
	if (!drm_mm_node_allocated(&vma->node))
		goto destroy;
2845

2846 2847
	GEM_BUG_ON(obj->bind_count == 0);
	GEM_BUG_ON(!obj->pages);
2848

2849
	if (vma->is_ggtt && vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
2850
		i915_gem_object_finish_gtt(obj);
2851

2852 2853 2854 2855
		/* release the fence reg _after_ flushing */
		ret = i915_gem_object_put_fence(obj);
		if (ret)
			return ret;
2856 2857

		__i915_vma_iounmap(vma);
2858
	}
2859

2860 2861 2862 2863
	if (likely(!vma->vm->closed)) {
		trace_i915_vma_unbind(vma);
		vma->vm->unbind_vma(vma);
	}
2864
	vma->bound = 0;
2865

2866 2867 2868
	drm_mm_remove_node(&vma->node);
	list_move_tail(&vma->vm_link, &vma->vm->unbound_list);

2869
	if (vma->is_ggtt) {
2870 2871 2872 2873 2874 2875
		if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
			obj->map_and_fenceable = false;
		} else if (vma->ggtt_view.pages) {
			sg_free_table(vma->ggtt_view.pages);
			kfree(vma->ggtt_view.pages);
		}
2876
		vma->ggtt_view.pages = NULL;
2877
	}
2878

B
Ben Widawsky 已提交
2879
	/* Since the unbound list is global, only move to that list if
2880
	 * no more VMAs exist. */
2881 2882 2883
	if (--obj->bind_count == 0)
		list_move_tail(&obj->global_list,
			       &to_i915(obj->base.dev)->mm.unbound_list);
2884

2885 2886 2887 2888 2889 2890
	/* And finally now the object is completely decoupled from this vma,
	 * we can drop its hold on the backing storage and allow it to be
	 * reaped by the shrinker.
	 */
	i915_gem_object_unpin_pages(obj);

2891 2892 2893 2894
destroy:
	if (unlikely(vma->closed))
		i915_vma_destroy(vma);

2895
	return 0;
2896 2897
}

2898 2899 2900 2901 2902 2903 2904 2905 2906 2907
int i915_vma_unbind(struct i915_vma *vma)
{
	return __i915_vma_unbind(vma, true);
}

int __i915_vma_unbind_no_wait(struct i915_vma *vma)
{
	return __i915_vma_unbind(vma, false);
}

2908
int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv)
2909
{
2910
	struct intel_engine_cs *engine;
2911
	int ret;
2912

2913
	lockdep_assert_held(&dev_priv->drm.struct_mutex);
2914

2915
	for_each_engine(engine, dev_priv) {
2916 2917 2918
		if (engine->last_context == NULL)
			continue;

2919
		ret = intel_engine_idle(engine);
2920 2921 2922
		if (ret)
			return ret;
	}
2923

2924
	return 0;
2925 2926
}

2927
static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
2928 2929
				     unsigned long cache_level)
{
2930
	struct drm_mm_node *gtt_space = &vma->node;
2931 2932
	struct drm_mm_node *other;

2933 2934 2935 2936 2937 2938
	/*
	 * On some machines we have to be careful when putting differing types
	 * of snoopable memory together to avoid the prefetcher crossing memory
	 * domains and dying. During vm initialisation, we decide whether or not
	 * these constraints apply and set the drm_mm.color_adjust
	 * appropriately.
2939
	 */
2940
	if (vma->vm->mm.color_adjust == NULL)
2941 2942
		return true;

2943
	if (!drm_mm_node_allocated(gtt_space))
2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 2956 2957 2958 2959
		return true;

	if (list_empty(&gtt_space->node_list))
		return true;

	other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
	if (other->allocated && !other->hole_follows && other->color != cache_level)
		return false;

	other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
	if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
		return false;

	return true;
}

2960
/**
2961 2962
 * Finds free space in the GTT aperture and binds the object or a view of it
 * there.
2963 2964 2965 2966 2967
 * @obj: object to bind
 * @vm: address space to bind into
 * @ggtt_view: global gtt view if applicable
 * @alignment: requested alignment
 * @flags: mask of PIN_* flags to use
2968
 */
2969
static struct i915_vma *
2970 2971
i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
			   struct i915_address_space *vm,
2972
			   const struct i915_ggtt_view *ggtt_view,
2973
			   unsigned alignment,
2974
			   uint64_t flags)
2975
{
2976
	struct drm_device *dev = obj->base.dev;
2977 2978
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct i915_ggtt *ggtt = &dev_priv->ggtt;
2979
	u32 fence_alignment, unfenced_alignment;
2980 2981
	u32 search_flag, alloc_flag;
	u64 start, end;
2982
	u64 size, fence_size;
B
Ben Widawsky 已提交
2983
	struct i915_vma *vma;
2984
	int ret;
2985

2986 2987 2988 2989 2990
	if (i915_is_ggtt(vm)) {
		u32 view_size;

		if (WARN_ON(!ggtt_view))
			return ERR_PTR(-EINVAL);
2991

2992 2993 2994 2995 2996 2997 2998 2999 3000 3001 3002 3003 3004 3005 3006 3007 3008 3009 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020
		view_size = i915_ggtt_view_size(obj, ggtt_view);

		fence_size = i915_gem_get_gtt_size(dev,
						   view_size,
						   obj->tiling_mode);
		fence_alignment = i915_gem_get_gtt_alignment(dev,
							     view_size,
							     obj->tiling_mode,
							     true);
		unfenced_alignment = i915_gem_get_gtt_alignment(dev,
								view_size,
								obj->tiling_mode,
								false);
		size = flags & PIN_MAPPABLE ? fence_size : view_size;
	} else {
		fence_size = i915_gem_get_gtt_size(dev,
						   obj->base.size,
						   obj->tiling_mode);
		fence_alignment = i915_gem_get_gtt_alignment(dev,
							     obj->base.size,
							     obj->tiling_mode,
							     true);
		unfenced_alignment =
			i915_gem_get_gtt_alignment(dev,
						   obj->base.size,
						   obj->tiling_mode,
						   false);
		size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
	}
3021

3022 3023 3024
	start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
	end = vm->total;
	if (flags & PIN_MAPPABLE)
3025
		end = min_t(u64, end, ggtt->mappable_end);
3026
	if (flags & PIN_ZONE_4G)
3027
		end = min_t(u64, end, (1ULL << 32) - PAGE_SIZE);
3028

3029
	if (alignment == 0)
3030
		alignment = flags & PIN_MAPPABLE ? fence_alignment :
3031
						unfenced_alignment;
3032
	if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3033 3034 3035
		DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n",
			  ggtt_view ? ggtt_view->type : 0,
			  alignment);
3036
		return ERR_PTR(-EINVAL);
3037 3038
	}

3039 3040 3041
	/* If binding the object/GGTT view requires more space than the entire
	 * aperture has, reject it early before evicting everything in a vain
	 * attempt to find space.
3042
	 */
3043
	if (size > end) {
3044
		DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%llu > %s aperture=%llu\n",
3045 3046
			  ggtt_view ? ggtt_view->type : 0,
			  size,
3047
			  flags & PIN_MAPPABLE ? "mappable" : "total",
3048
			  end);
3049
		return ERR_PTR(-E2BIG);
3050 3051
	}

3052
	ret = i915_gem_object_get_pages(obj);
C
Chris Wilson 已提交
3053
	if (ret)
3054
		return ERR_PTR(ret);
C
Chris Wilson 已提交
3055

3056 3057
	i915_gem_object_pin_pages(obj);

3058 3059 3060
	vma = ggtt_view ? i915_gem_obj_lookup_or_create_ggtt_vma(obj, ggtt_view) :
			  i915_gem_obj_lookup_or_create_vma(obj, vm);

3061
	if (IS_ERR(vma))
3062
		goto err_unpin;
B
Ben Widawsky 已提交
3063

3064 3065 3066 3067 3068
	if (flags & PIN_OFFSET_FIXED) {
		uint64_t offset = flags & PIN_OFFSET_MASK;

		if (offset & (alignment - 1) || offset + size > end) {
			ret = -EINVAL;
3069
			goto err_vma;
3070 3071 3072 3073 3074 3075 3076 3077 3078 3079 3080
		}
		vma->node.start = offset;
		vma->node.size = size;
		vma->node.color = obj->cache_level;
		ret = drm_mm_reserve_node(&vm->mm, &vma->node);
		if (ret) {
			ret = i915_gem_evict_for_vma(vma);
			if (ret == 0)
				ret = drm_mm_reserve_node(&vm->mm, &vma->node);
		}
		if (ret)
3081
			goto err_vma;
3082
	} else {
3083 3084 3085 3086 3087 3088 3089
		if (flags & PIN_HIGH) {
			search_flag = DRM_MM_SEARCH_BELOW;
			alloc_flag = DRM_MM_CREATE_TOP;
		} else {
			search_flag = DRM_MM_SEARCH_DEFAULT;
			alloc_flag = DRM_MM_CREATE_DEFAULT;
		}
3090

3091
search_free:
3092 3093 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103 3104
		ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
							  size, alignment,
							  obj->cache_level,
							  start, end,
							  search_flag,
							  alloc_flag);
		if (ret) {
			ret = i915_gem_evict_something(dev, vm, size, alignment,
						       obj->cache_level,
						       start, end,
						       flags);
			if (ret == 0)
				goto search_free;
3105

3106
			goto err_vma;
3107
		}
3108
	}
3109
	if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
B
Ben Widawsky 已提交
3110
		ret = -EINVAL;
3111
		goto err_remove_node;
3112 3113
	}

3114
	trace_i915_vma_bind(vma, flags);
3115
	ret = i915_vma_bind(vma, obj->cache_level, flags);
3116
	if (ret)
I
Imre Deak 已提交
3117
		goto err_remove_node;
3118

3119
	list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3120
	list_move_tail(&vma->vm_link, &vm->inactive_list);
3121
	obj->bind_count++;
3122

3123
	return vma;
B
Ben Widawsky 已提交
3124

3125
err_remove_node:
3126
	drm_mm_remove_node(&vma->node);
3127
err_vma:
3128
	vma = ERR_PTR(ret);
3129
err_unpin:
B
Ben Widawsky 已提交
3130
	i915_gem_object_unpin_pages(obj);
3131
	return vma;
3132 3133
}

3134
bool
3135 3136
i915_gem_clflush_object(struct drm_i915_gem_object *obj,
			bool force)
3137 3138 3139 3140 3141
{
	/* If we don't have a page list set up, then we're not pinned
	 * to GPU, and we can ignore the cache flush because it'll happen
	 * again at bind time.
	 */
3142
	if (obj->pages == NULL)
3143
		return false;
3144

3145 3146 3147 3148
	/*
	 * Stolen memory is always coherent with the GPU as it is explicitly
	 * marked as wc by the system, or the system is cache-coherent.
	 */
3149
	if (obj->stolen || obj->phys_handle)
3150
		return false;
3151

3152 3153 3154 3155 3156 3157 3158 3159
	/* If the GPU is snooping the contents of the CPU cache,
	 * we do not need to manually clear the CPU cache lines.  However,
	 * the caches are only snooped when the render cache is
	 * flushed/invalidated.  As we always have to emit invalidations
	 * and flushes when moving into and out of the RENDER domain, correct
	 * snooping behaviour occurs naturally as the result of our domain
	 * tracking.
	 */
3160 3161
	if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) {
		obj->cache_dirty = true;
3162
		return false;
3163
	}
3164

C
Chris Wilson 已提交
3165
	trace_i915_gem_object_clflush(obj);
3166
	drm_clflush_sg(obj->pages);
3167
	obj->cache_dirty = false;
3168 3169

	return true;
3170 3171 3172 3173
}

/** Flushes the GTT write domain for the object if it's dirty. */
static void
3174
i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3175
{
C
Chris Wilson 已提交
3176 3177
	uint32_t old_write_domain;

3178
	if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3179 3180
		return;

3181
	/* No actual flushing is required for the GTT write domain.  Writes
3182 3183
	 * to it immediately go to main memory as far as we know, so there's
	 * no chipset flush.  It also doesn't land in render cache.
3184 3185 3186 3187
	 *
	 * However, we do have to enforce the order so that all writes through
	 * the GTT land before any writes to the device, such as updates to
	 * the GATT itself.
3188
	 */
3189 3190
	wmb();

3191 3192
	old_write_domain = obj->base.write_domain;
	obj->base.write_domain = 0;
C
Chris Wilson 已提交
3193

3194
	intel_fb_obj_flush(obj, false, ORIGIN_GTT);
3195

C
Chris Wilson 已提交
3196
	trace_i915_gem_object_change_domain(obj,
3197
					    obj->base.read_domains,
C
Chris Wilson 已提交
3198
					    old_write_domain);
3199 3200 3201 3202
}

/** Flushes the CPU write domain for the object if it's dirty. */
static void
3203
i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3204
{
C
Chris Wilson 已提交
3205
	uint32_t old_write_domain;
3206

3207
	if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3208 3209
		return;

3210
	if (i915_gem_clflush_object(obj, obj->pin_display))
3211
		i915_gem_chipset_flush(to_i915(obj->base.dev));
3212

3213 3214
	old_write_domain = obj->base.write_domain;
	obj->base.write_domain = 0;
C
Chris Wilson 已提交
3215

3216
	intel_fb_obj_flush(obj, false, ORIGIN_CPU);
3217

C
Chris Wilson 已提交
3218
	trace_i915_gem_object_change_domain(obj,
3219
					    obj->base.read_domains,
C
Chris Wilson 已提交
3220
					    old_write_domain);
3221 3222
}

3223 3224
/**
 * Moves a single object to the GTT read, and possibly write domain.
3225 3226
 * @obj: object to act on
 * @write: ask for write access or read only
3227 3228 3229 3230
 *
 * This function returns when the move is complete, including waiting on
 * flushes to occur.
 */
J
Jesse Barnes 已提交
3231
int
3232
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3233
{
C
Chris Wilson 已提交
3234
	uint32_t old_write_domain, old_read_domains;
3235
	struct i915_vma *vma;
3236
	int ret;
3237

3238
	ret = i915_gem_object_wait_rendering(obj, !write);
3239 3240 3241
	if (ret)
		return ret;

3242 3243 3244
	if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
		return 0;

3245 3246 3247 3248 3249 3250 3251 3252 3253 3254 3255 3256
	/* Flush and acquire obj->pages so that we are coherent through
	 * direct access in memory with previous cached writes through
	 * shmemfs and that our cache domain tracking remains valid.
	 * For example, if the obj->filp was moved to swap without us
	 * being notified and releasing the pages, we would mistakenly
	 * continue to assume that the obj remained out of the CPU cached
	 * domain.
	 */
	ret = i915_gem_object_get_pages(obj);
	if (ret)
		return ret;

3257
	i915_gem_object_flush_cpu_write_domain(obj);
C
Chris Wilson 已提交
3258

3259 3260 3261 3262 3263 3264 3265
	/* Serialise direct access to this object with the barriers for
	 * coherent writes from the GPU, by effectively invalidating the
	 * GTT domain upon first access.
	 */
	if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
		mb();

3266 3267
	old_write_domain = obj->base.write_domain;
	old_read_domains = obj->base.read_domains;
C
Chris Wilson 已提交
3268

3269 3270 3271
	/* It should now be out of any other write domains, and we can update
	 * the domain values for our changes.
	 */
3272 3273
	BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
	obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3274
	if (write) {
3275 3276 3277
		obj->base.read_domains = I915_GEM_DOMAIN_GTT;
		obj->base.write_domain = I915_GEM_DOMAIN_GTT;
		obj->dirty = 1;
3278 3279
	}

C
Chris Wilson 已提交
3280 3281 3282 3283
	trace_i915_gem_object_change_domain(obj,
					    old_read_domains,
					    old_write_domain);

3284
	/* And bump the LRU for this access */
3285
	vma = i915_gem_obj_to_ggtt(obj);
3286 3287 3288 3289
	if (vma &&
	    drm_mm_node_allocated(&vma->node) &&
	    !i915_vma_is_active(vma))
		list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
3290

3291 3292 3293
	return 0;
}

3294 3295
/**
 * Changes the cache-level of an object across all VMA.
3296 3297
 * @obj: object to act on
 * @cache_level: new cache level to set for the object
3298 3299 3300 3301 3302 3303 3304 3305 3306 3307 3308
 *
 * After this function returns, the object will be in the new cache-level
 * across all GTT and the contents of the backing storage will be coherent,
 * with respect to the new cache-level. In order to keep the backing storage
 * coherent for all users, we only allow a single cache level to be set
 * globally on the object and prevent it from being changed whilst the
 * hardware is reading from the object. That is if the object is currently
 * on the scanout it will be set to uncached (or equivalent display
 * cache coherency) and all non-MOCS GPU access will also be uncached so
 * that all direct access to the scanout remains coherent.
 */
3309 3310 3311
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
				    enum i915_cache_level cache_level)
{
3312
	struct i915_vma *vma;
3313
	int ret = 0;
3314 3315

	if (obj->cache_level == cache_level)
3316
		goto out;
3317

3318 3319 3320 3321 3322
	/* Inspect the list of currently bound VMA and unbind any that would
	 * be invalid given the new cache-level. This is principally to
	 * catch the issue of the CS prefetch crossing page boundaries and
	 * reading an invalid PTE on older architectures.
	 */
3323 3324
restart:
	list_for_each_entry(vma, &obj->vma_list, obj_link) {
3325 3326 3327 3328 3329 3330 3331 3332
		if (!drm_mm_node_allocated(&vma->node))
			continue;

		if (vma->pin_count) {
			DRM_DEBUG("can not change the cache level of pinned objects\n");
			return -EBUSY;
		}

3333 3334 3335 3336 3337 3338 3339 3340 3341 3342 3343 3344
		if (i915_gem_valid_gtt_space(vma, cache_level))
			continue;

		ret = i915_vma_unbind(vma);
		if (ret)
			return ret;

		/* As unbinding may affect other elements in the
		 * obj->vma_list (due to side-effects from retiring
		 * an active vma), play safe and restart the iterator.
		 */
		goto restart;
3345 3346
	}

3347 3348 3349 3350 3351 3352 3353
	/* We can reuse the existing drm_mm nodes but need to change the
	 * cache-level on the PTE. We could simply unbind them all and
	 * rebind with the correct cache-level on next use. However since
	 * we already have a valid slot, dma mapping, pages etc, we may as
	 * rewrite the PTE in the belief that doing so tramples upon less
	 * state and so involves less work.
	 */
3354
	if (obj->bind_count) {
3355 3356 3357 3358
		/* Before we change the PTE, the GPU must not be accessing it.
		 * If we wait upon the object, we know that all the bound
		 * VMA are no longer active.
		 */
3359
		ret = i915_gem_object_wait_rendering(obj, false);
3360 3361 3362
		if (ret)
			return ret;

3363
		if (!HAS_LLC(obj->base.dev) && cache_level != I915_CACHE_NONE) {
3364 3365 3366 3367 3368 3369 3370 3371 3372 3373 3374 3375 3376 3377 3378 3379
			/* Access to snoopable pages through the GTT is
			 * incoherent and on some machines causes a hard
			 * lockup. Relinquish the CPU mmaping to force
			 * userspace to refault in the pages and we can
			 * then double check if the GTT mapping is still
			 * valid for that pointer access.
			 */
			i915_gem_release_mmap(obj);

			/* As we no longer need a fence for GTT access,
			 * we can relinquish it now (and so prevent having
			 * to steal a fence from someone else on the next
			 * fence request). Note GPU activity would have
			 * dropped the fence as all snoopable access is
			 * supposed to be linear.
			 */
3380 3381 3382
			ret = i915_gem_object_put_fence(obj);
			if (ret)
				return ret;
3383 3384 3385 3386 3387 3388 3389 3390
		} else {
			/* We either have incoherent backing store and
			 * so no GTT access or the architecture is fully
			 * coherent. In such cases, existing GTT mmaps
			 * ignore the cache bit in the PTE and we can
			 * rewrite it without confusing the GPU or having
			 * to force userspace to fault back in its mmaps.
			 */
3391 3392
		}

3393
		list_for_each_entry(vma, &obj->vma_list, obj_link) {
3394 3395 3396 3397 3398 3399 3400
			if (!drm_mm_node_allocated(&vma->node))
				continue;

			ret = i915_vma_bind(vma, cache_level, PIN_UPDATE);
			if (ret)
				return ret;
		}
3401 3402
	}

3403
	list_for_each_entry(vma, &obj->vma_list, obj_link)
3404 3405 3406
		vma->node.color = cache_level;
	obj->cache_level = cache_level;

3407
out:
3408 3409 3410 3411
	/* Flush the dirty CPU caches to the backing storage so that the
	 * object is now coherent at its new cache level (with respect
	 * to the access domain).
	 */
3412
	if (obj->cache_dirty && cpu_write_needs_clflush(obj)) {
3413
		if (i915_gem_clflush_object(obj, true))
3414
			i915_gem_chipset_flush(to_i915(obj->base.dev));
3415 3416 3417 3418 3419
	}

	return 0;
}

B
Ben Widawsky 已提交
3420 3421
int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file)
3422
{
B
Ben Widawsky 已提交
3423
	struct drm_i915_gem_caching *args = data;
3424 3425
	struct drm_i915_gem_object *obj;

3426 3427
	obj = i915_gem_object_lookup(file, args->handle);
	if (!obj)
3428
		return -ENOENT;
3429

3430 3431 3432 3433 3434 3435
	switch (obj->cache_level) {
	case I915_CACHE_LLC:
	case I915_CACHE_L3_LLC:
		args->caching = I915_CACHING_CACHED;
		break;

3436 3437 3438 3439
	case I915_CACHE_WT:
		args->caching = I915_CACHING_DISPLAY;
		break;

3440 3441 3442 3443
	default:
		args->caching = I915_CACHING_NONE;
		break;
	}
3444

3445
	i915_gem_object_put_unlocked(obj);
3446
	return 0;
3447 3448
}

B
Ben Widawsky 已提交
3449 3450
int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file)
3451
{
3452
	struct drm_i915_private *dev_priv = to_i915(dev);
B
Ben Widawsky 已提交
3453
	struct drm_i915_gem_caching *args = data;
3454 3455 3456 3457
	struct drm_i915_gem_object *obj;
	enum i915_cache_level level;
	int ret;

B
Ben Widawsky 已提交
3458 3459
	switch (args->caching) {
	case I915_CACHING_NONE:
3460 3461
		level = I915_CACHE_NONE;
		break;
B
Ben Widawsky 已提交
3462
	case I915_CACHING_CACHED:
3463 3464 3465 3466 3467 3468
		/*
		 * Due to a HW issue on BXT A stepping, GPU stores via a
		 * snooped mapping may leave stale data in a corresponding CPU
		 * cacheline, whereas normally such cachelines would get
		 * invalidated.
		 */
3469
		if (!HAS_LLC(dev) && !HAS_SNOOP(dev))
3470 3471
			return -ENODEV;

3472 3473
		level = I915_CACHE_LLC;
		break;
3474 3475 3476
	case I915_CACHING_DISPLAY:
		level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
		break;
3477 3478 3479 3480
	default:
		return -EINVAL;
	}

3481 3482
	intel_runtime_pm_get(dev_priv);

B
Ben Widawsky 已提交
3483 3484
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
3485
		goto rpm_put;
B
Ben Widawsky 已提交
3486

3487 3488
	obj = i915_gem_object_lookup(file, args->handle);
	if (!obj) {
3489 3490 3491 3492 3493 3494
		ret = -ENOENT;
		goto unlock;
	}

	ret = i915_gem_object_set_cache_level(obj, level);

3495
	i915_gem_object_put(obj);
3496 3497
unlock:
	mutex_unlock(&dev->struct_mutex);
3498 3499 3500
rpm_put:
	intel_runtime_pm_put(dev_priv);

3501 3502 3503
	return ret;
}

3504
/*
3505 3506 3507
 * Prepare buffer for display plane (scanout, cursors, etc).
 * Can be called from an uninterruptible phase (modesetting) and allows
 * any flushes to be pipelined (for pageflips).
3508 3509
 */
int
3510 3511
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
				     u32 alignment,
3512
				     const struct i915_ggtt_view *view)
3513
{
3514
	u32 old_read_domains, old_write_domain;
3515 3516
	int ret;

3517 3518 3519
	/* Mark the pin_display early so that we account for the
	 * display coherency whilst setting up the cache domains.
	 */
3520
	obj->pin_display++;
3521

3522 3523 3524 3525 3526 3527 3528 3529 3530
	/* The display engine is not coherent with the LLC cache on gen6.  As
	 * a result, we make sure that the pinning that is about to occur is
	 * done with uncached PTEs. This is lowest common denominator for all
	 * chipsets.
	 *
	 * However for gen6+, we could do better by using the GFDT bit instead
	 * of uncaching, which would allow us to flush all the LLC-cached data
	 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
	 */
3531 3532
	ret = i915_gem_object_set_cache_level(obj,
					      HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3533
	if (ret)
3534
		goto err_unpin_display;
3535

3536 3537 3538 3539
	/* As the user may map the buffer once pinned in the display plane
	 * (e.g. libkms for the bootup splash), we have to ensure that we
	 * always use map_and_fenceable for all scanout buffers.
	 */
3540 3541 3542
	ret = i915_gem_object_ggtt_pin(obj, view, alignment,
				       view->type == I915_GGTT_VIEW_NORMAL ?
				       PIN_MAPPABLE : 0);
3543
	if (ret)
3544
		goto err_unpin_display;
3545

3546
	i915_gem_object_flush_cpu_write_domain(obj);
3547

3548
	old_write_domain = obj->base.write_domain;
3549
	old_read_domains = obj->base.read_domains;
3550 3551 3552 3553

	/* It should now be out of any other write domains, and we can update
	 * the domain values for our changes.
	 */
3554
	obj->base.write_domain = 0;
3555
	obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3556 3557 3558

	trace_i915_gem_object_change_domain(obj,
					    old_read_domains,
3559
					    old_write_domain);
3560 3561

	return 0;
3562 3563

err_unpin_display:
3564
	obj->pin_display--;
3565 3566 3567 3568
	return ret;
}

void
3569 3570
i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
					 const struct i915_ggtt_view *view)
3571
{
3572 3573 3574
	if (WARN_ON(obj->pin_display == 0))
		return;

3575 3576
	i915_gem_object_ggtt_unpin_view(obj, view);

3577
	obj->pin_display--;
3578 3579
}

3580 3581
/**
 * Moves a single object to the CPU read, and possibly write domain.
3582 3583
 * @obj: object to act on
 * @write: requesting write or read-only access
3584 3585 3586 3587
 *
 * This function returns when the move is complete, including waiting on
 * flushes to occur.
 */
3588
int
3589
i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3590
{
C
Chris Wilson 已提交
3591
	uint32_t old_write_domain, old_read_domains;
3592 3593
	int ret;

3594
	ret = i915_gem_object_wait_rendering(obj, !write);
3595 3596 3597
	if (ret)
		return ret;

3598 3599 3600
	if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
		return 0;

3601
	i915_gem_object_flush_gtt_write_domain(obj);
3602

3603 3604
	old_write_domain = obj->base.write_domain;
	old_read_domains = obj->base.read_domains;
C
Chris Wilson 已提交
3605

3606
	/* Flush the CPU cache if it's still invalid. */
3607
	if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3608
		i915_gem_clflush_object(obj, false);
3609

3610
		obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3611 3612 3613 3614 3615
	}

	/* It should now be out of any other write domains, and we can update
	 * the domain values for our changes.
	 */
3616
	BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3617 3618 3619 3620 3621

	/* If we're writing through the CPU, then the GPU read domains will
	 * need to be invalidated at next use.
	 */
	if (write) {
3622 3623
		obj->base.read_domains = I915_GEM_DOMAIN_CPU;
		obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3624
	}
3625

C
Chris Wilson 已提交
3626 3627 3628 3629
	trace_i915_gem_object_change_domain(obj,
					    old_read_domains,
					    old_write_domain);

3630 3631 3632
	return 0;
}

3633 3634 3635
/* Throttle our rendering by waiting until the ring has completed our requests
 * emitted over 20 msec ago.
 *
3636 3637 3638 3639
 * Note that if we were to use the current jiffies each time around the loop,
 * we wouldn't escape the function with any frames outstanding if the time to
 * render a frame was over 20ms.
 *
3640 3641 3642
 * This should get us reasonable parallelism between CPU and GPU but also
 * relatively low latency when blocking on a particular request to finish.
 */
3643
static int
3644
i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3645
{
3646
	struct drm_i915_private *dev_priv = to_i915(dev);
3647
	struct drm_i915_file_private *file_priv = file->driver_priv;
3648
	unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES;
3649
	struct drm_i915_gem_request *request, *target = NULL;
3650
	int ret;
3651

3652 3653 3654 3655
	ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
	if (ret)
		return ret;

3656 3657 3658
	/* ABI: return -EIO if already wedged */
	if (i915_terminally_wedged(&dev_priv->gpu_error))
		return -EIO;
3659

3660
	spin_lock(&file_priv->mm.lock);
3661
	list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3662 3663
		if (time_after_eq(request->emitted_jiffies, recent_enough))
			break;
3664

3665 3666 3667 3668 3669 3670 3671
		/*
		 * Note that the request might not have been submitted yet.
		 * In which case emitted_jiffies will be zero.
		 */
		if (!request->emitted_jiffies)
			continue;

3672
		target = request;
3673
	}
3674
	if (target)
3675
		i915_gem_request_get(target);
3676
	spin_unlock(&file_priv->mm.lock);
3677

3678
	if (target == NULL)
3679
		return 0;
3680

3681
	ret = i915_wait_request(target, true, NULL, NULL);
3682
	i915_gem_request_put(target);
3683

3684 3685 3686
	return ret;
}

3687 3688 3689 3690 3691 3692 3693 3694 3695 3696 3697 3698 3699 3700 3701 3702
static bool
i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
{
	struct drm_i915_gem_object *obj = vma->obj;

	if (alignment &&
	    vma->node.start & (alignment - 1))
		return true;

	if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
		return true;

	if (flags & PIN_OFFSET_BIAS &&
	    vma->node.start < (flags & PIN_OFFSET_MASK))
		return true;

3703 3704 3705 3706
	if (flags & PIN_OFFSET_FIXED &&
	    vma->node.start != (flags & PIN_OFFSET_MASK))
		return true;

3707 3708 3709
	return false;
}

3710 3711 3712 3713 3714 3715 3716 3717 3718 3719 3720 3721 3722 3723 3724 3725 3726 3727
void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
{
	struct drm_i915_gem_object *obj = vma->obj;
	bool mappable, fenceable;
	u32 fence_size, fence_alignment;

	fence_size = i915_gem_get_gtt_size(obj->base.dev,
					   obj->base.size,
					   obj->tiling_mode);
	fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
						     obj->base.size,
						     obj->tiling_mode,
						     true);

	fenceable = (vma->node.size == fence_size &&
		     (vma->node.start & (fence_alignment - 1)) == 0);

	mappable = (vma->node.start + fence_size <=
3728
		    to_i915(obj->base.dev)->ggtt.mappable_end);
3729 3730 3731 3732

	obj->map_and_fenceable = mappable && fenceable;
}

3733 3734 3735 3736 3737 3738
static int
i915_gem_object_do_pin(struct drm_i915_gem_object *obj,
		       struct i915_address_space *vm,
		       const struct i915_ggtt_view *ggtt_view,
		       uint32_t alignment,
		       uint64_t flags)
3739
{
3740
	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3741
	struct i915_vma *vma;
3742
	unsigned bound;
3743 3744
	int ret;

3745 3746 3747
	if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
		return -ENODEV;

3748
	if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
3749
		return -EINVAL;
3750

3751 3752 3753
	if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
		return -EINVAL;

3754 3755 3756 3757 3758 3759
	if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
		return -EINVAL;

	vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) :
			  i915_gem_obj_to_vma(obj, vm);

3760
	if (vma) {
B
Ben Widawsky 已提交
3761 3762 3763
		if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
			return -EBUSY;

3764
		if (i915_vma_misplaced(vma, alignment, flags)) {
B
Ben Widawsky 已提交
3765
			WARN(vma->pin_count,
3766
			     "bo is already pinned in %s with incorrect alignment:"
3767
			     " offset=%08x %08x, req.alignment=%x, req.map_and_fenceable=%d,"
3768
			     " obj->map_and_fenceable=%d\n",
3769
			     ggtt_view ? "ggtt" : "ppgtt",
3770 3771
			     upper_32_bits(vma->node.start),
			     lower_32_bits(vma->node.start),
3772
			     alignment,
3773
			     !!(flags & PIN_MAPPABLE),
3774
			     obj->map_and_fenceable);
3775
			ret = i915_vma_unbind(vma);
3776 3777
			if (ret)
				return ret;
3778 3779

			vma = NULL;
3780 3781 3782
		}
	}

3783
	bound = vma ? vma->bound : 0;
3784
	if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
3785 3786
		vma = i915_gem_object_bind_to_vm(obj, vm, ggtt_view, alignment,
						 flags);
3787 3788
		if (IS_ERR(vma))
			return PTR_ERR(vma);
3789 3790
	} else {
		ret = i915_vma_bind(vma, obj->cache_level, flags);
3791 3792 3793
		if (ret)
			return ret;
	}
3794

3795 3796
	if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL &&
	    (bound ^ vma->bound) & GLOBAL_BIND) {
3797
		__i915_vma_set_map_and_fenceable(vma);
3798 3799
		WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
	}
3800

3801
	vma->pin_count++;
3802 3803 3804
	return 0;
}

3805 3806 3807 3808 3809 3810 3811 3812 3813 3814 3815 3816 3817 3818 3819 3820 3821
int
i915_gem_object_pin(struct drm_i915_gem_object *obj,
		    struct i915_address_space *vm,
		    uint32_t alignment,
		    uint64_t flags)
{
	return i915_gem_object_do_pin(obj, vm,
				      i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL,
				      alignment, flags);
}

int
i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
			 const struct i915_ggtt_view *view,
			 uint32_t alignment,
			 uint64_t flags)
{
3822 3823 3824 3825
	struct drm_device *dev = obj->base.dev;
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct i915_ggtt *ggtt = &dev_priv->ggtt;

3826
	BUG_ON(!view);
3827

3828
	return i915_gem_object_do_pin(obj, &ggtt->base, view,
3829
				      alignment, flags | PIN_GLOBAL);
3830 3831
}

3832
void
3833 3834
i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
				const struct i915_ggtt_view *view)
3835
{
3836
	struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view);
3837

3838
	WARN_ON(vma->pin_count == 0);
3839
	WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view));
B
Ben Widawsky 已提交
3840

3841
	--vma->pin_count;
3842 3843 3844 3845
}

int
i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3846
		    struct drm_file *file)
3847 3848
{
	struct drm_i915_gem_busy *args = data;
3849
	struct drm_i915_gem_object *obj;
3850 3851
	int ret;

3852
	ret = i915_mutex_lock_interruptible(dev);
3853
	if (ret)
3854
		return ret;
3855

3856 3857
	obj = i915_gem_object_lookup(file, args->handle);
	if (!obj) {
3858 3859
		ret = -ENOENT;
		goto unlock;
3860
	}
3861

3862 3863
	/* Count all active objects as busy, even if they are currently not used
	 * by the gpu. Users of this interface expect objects to eventually
3864
	 * become non-busy without any further actions.
3865
	 */
3866 3867
	args->busy = 0;
	if (obj->active) {
3868
		struct drm_i915_gem_request *req;
3869 3870
		int i;

3871
		for (i = 0; i < I915_NUM_ENGINES; i++) {
3872 3873
			req = i915_gem_active_peek(&obj->last_read[i],
						   &obj->base.dev->struct_mutex);
3874
			if (req)
3875
				args->busy |= 1 << (16 + req->engine->exec_id);
3876
		}
3877 3878
		req = i915_gem_active_peek(&obj->last_write,
					   &obj->base.dev->struct_mutex);
3879 3880
		if (req)
			args->busy |= req->engine->exec_id;
3881
	}
3882

3883
	i915_gem_object_put(obj);
3884
unlock:
3885
	mutex_unlock(&dev->struct_mutex);
3886
	return ret;
3887 3888 3889 3890 3891 3892
}

int
i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv)
{
3893
	return i915_gem_ring_throttle(dev, file_priv);
3894 3895
}

3896 3897 3898 3899
int
i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
		       struct drm_file *file_priv)
{
3900
	struct drm_i915_private *dev_priv = to_i915(dev);
3901
	struct drm_i915_gem_madvise *args = data;
3902
	struct drm_i915_gem_object *obj;
3903
	int ret;
3904 3905 3906 3907 3908 3909 3910 3911 3912

	switch (args->madv) {
	case I915_MADV_DONTNEED:
	case I915_MADV_WILLNEED:
	    break;
	default:
	    return -EINVAL;
	}

3913 3914 3915 3916
	ret = i915_mutex_lock_interruptible(dev);
	if (ret)
		return ret;

3917 3918
	obj = i915_gem_object_lookup(file_priv, args->handle);
	if (!obj) {
3919 3920
		ret = -ENOENT;
		goto unlock;
3921 3922
	}

B
Ben Widawsky 已提交
3923
	if (i915_gem_obj_is_pinned(obj)) {
3924 3925
		ret = -EINVAL;
		goto out;
3926 3927
	}

3928 3929 3930 3931 3932 3933 3934 3935 3936
	if (obj->pages &&
	    obj->tiling_mode != I915_TILING_NONE &&
	    dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
		if (obj->madv == I915_MADV_WILLNEED)
			i915_gem_object_unpin_pages(obj);
		if (args->madv == I915_MADV_WILLNEED)
			i915_gem_object_pin_pages(obj);
	}

3937 3938
	if (obj->madv != __I915_MADV_PURGED)
		obj->madv = args->madv;
3939

C
Chris Wilson 已提交
3940
	/* if the object is no longer attached, discard its backing storage */
3941
	if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL)
3942 3943
		i915_gem_object_truncate(obj);

3944
	args->retained = obj->madv != __I915_MADV_PURGED;
C
Chris Wilson 已提交
3945

3946
out:
3947
	i915_gem_object_put(obj);
3948
unlock:
3949
	mutex_unlock(&dev->struct_mutex);
3950
	return ret;
3951 3952
}

3953 3954
void i915_gem_object_init(struct drm_i915_gem_object *obj,
			  const struct drm_i915_gem_object_ops *ops)
3955
{
3956 3957
	int i;

3958
	INIT_LIST_HEAD(&obj->global_list);
3959
	for (i = 0; i < I915_NUM_ENGINES; i++)
3960 3961 3962 3963 3964
		init_request_active(&obj->last_read[i],
				    i915_gem_object_retire__read);
	init_request_active(&obj->last_write,
			    i915_gem_object_retire__write);
	init_request_active(&obj->last_fence, NULL);
3965
	INIT_LIST_HEAD(&obj->obj_exec_link);
B
Ben Widawsky 已提交
3966
	INIT_LIST_HEAD(&obj->vma_list);
3967
	INIT_LIST_HEAD(&obj->batch_pool_link);
3968

3969 3970
	obj->ops = ops;

3971 3972 3973
	obj->fence_reg = I915_FENCE_REG_NONE;
	obj->madv = I915_MADV_WILLNEED;

3974
	i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size);
3975 3976
}

3977
static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3978
	.flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE,
3979 3980 3981 3982
	.get_pages = i915_gem_object_get_pages_gtt,
	.put_pages = i915_gem_object_put_pages_gtt,
};

3983
struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev,
3984
						  size_t size)
3985
{
3986
	struct drm_i915_gem_object *obj;
3987
	struct address_space *mapping;
D
Daniel Vetter 已提交
3988
	gfp_t mask;
3989
	int ret;
3990

3991
	obj = i915_gem_object_alloc(dev);
3992
	if (obj == NULL)
3993
		return ERR_PTR(-ENOMEM);
3994

3995 3996 3997
	ret = drm_gem_object_init(dev, &obj->base, size);
	if (ret)
		goto fail;
3998

3999 4000 4001 4002 4003 4004 4005
	mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
	if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
		/* 965gm cannot relocate objects above 4GiB. */
		mask &= ~__GFP_HIGHMEM;
		mask |= __GFP_DMA32;
	}

A
Al Viro 已提交
4006
	mapping = file_inode(obj->base.filp)->i_mapping;
4007
	mapping_set_gfp_mask(mapping, mask);
4008

4009
	i915_gem_object_init(obj, &i915_gem_object_ops);
4010

4011 4012
	obj->base.write_domain = I915_GEM_DOMAIN_CPU;
	obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4013

4014 4015
	if (HAS_LLC(dev)) {
		/* On some devices, we can have the GPU use the LLC (the CPU
4016 4017 4018 4019 4020 4021 4022 4023 4024 4025 4026 4027 4028 4029 4030
		 * cache) for about a 10% performance improvement
		 * compared to uncached.  Graphics requests other than
		 * display scanout are coherent with the CPU in
		 * accessing this cache.  This means in this mode we
		 * don't need to clflush on the CPU side, and on the
		 * GPU side we only need to flush internal caches to
		 * get data visible to the CPU.
		 *
		 * However, we maintain the display planes as UC, and so
		 * need to rebind when first used as such.
		 */
		obj->cache_level = I915_CACHE_LLC;
	} else
		obj->cache_level = I915_CACHE_NONE;

4031 4032
	trace_i915_gem_object_create(obj);

4033
	return obj;
4034 4035 4036 4037 4038

fail:
	i915_gem_object_free(obj);

	return ERR_PTR(ret);
4039 4040
}

4041 4042 4043 4044 4045 4046 4047 4048 4049 4050 4051 4052 4053 4054 4055 4056 4057 4058 4059 4060 4061 4062 4063 4064
static bool discard_backing_storage(struct drm_i915_gem_object *obj)
{
	/* If we are the last user of the backing storage (be it shmemfs
	 * pages or stolen etc), we know that the pages are going to be
	 * immediately released. In this case, we can then skip copying
	 * back the contents from the GPU.
	 */

	if (obj->madv != I915_MADV_WILLNEED)
		return false;

	if (obj->base.filp == NULL)
		return true;

	/* At first glance, this looks racy, but then again so would be
	 * userspace racing mmap against close. However, the first external
	 * reference to the filp can only be obtained through the
	 * i915_gem_mmap_ioctl() which safeguards us against the user
	 * acquiring such a reference whilst we are in the middle of
	 * freeing the object.
	 */
	return atomic_long_read(&obj->base.filp->f_count) == 1;
}

4065
void i915_gem_free_object(struct drm_gem_object *gem_obj)
4066
{
4067
	struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4068
	struct drm_device *dev = obj->base.dev;
4069
	struct drm_i915_private *dev_priv = to_i915(dev);
4070
	struct i915_vma *vma, *next;
4071

4072 4073
	intel_runtime_pm_get(dev_priv);

4074 4075
	trace_i915_gem_object_destroy(obj);

4076 4077 4078 4079 4080 4081 4082
	/* All file-owned VMA should have been released by this point through
	 * i915_gem_close_object(), or earlier by i915_gem_context_close().
	 * However, the object may also be bound into the global GTT (e.g.
	 * older GPUs without per-process support, or for direct access through
	 * the GTT either for the user or for scanout). Those VMA still need to
	 * unbound now.
	 */
4083
	list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) {
4084 4085
		GEM_BUG_ON(!vma->is_ggtt);
		GEM_BUG_ON(i915_vma_is_active(vma));
B
Ben Widawsky 已提交
4086
		vma->pin_count = 0;
4087
		i915_vma_close(vma);
4088
	}
4089
	GEM_BUG_ON(obj->bind_count);
4090

B
Ben Widawsky 已提交
4091 4092 4093 4094 4095
	/* Stolen objects don't hold a ref, but do hold pin count. Fix that up
	 * before progressing. */
	if (obj->stolen)
		i915_gem_object_unpin_pages(obj);

4096 4097
	WARN_ON(obj->frontbuffer_bits);

4098 4099 4100 4101 4102
	if (obj->pages && obj->madv == I915_MADV_WILLNEED &&
	    dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES &&
	    obj->tiling_mode != I915_TILING_NONE)
		i915_gem_object_unpin_pages(obj);

B
Ben Widawsky 已提交
4103 4104
	if (WARN_ON(obj->pages_pin_count))
		obj->pages_pin_count = 0;
4105
	if (discard_backing_storage(obj))
4106
		obj->madv = I915_MADV_DONTNEED;
4107
	i915_gem_object_put_pages(obj);
4108

4109 4110
	BUG_ON(obj->pages);

4111 4112
	if (obj->base.import_attach)
		drm_prime_gem_destroy(&obj->base, NULL);
4113

4114 4115 4116
	if (obj->ops->release)
		obj->ops->release(obj);

4117 4118
	drm_gem_object_release(&obj->base);
	i915_gem_info_remove_obj(dev_priv, obj->base.size);
4119

4120
	kfree(obj->bit_17);
4121
	i915_gem_object_free(obj);
4122 4123

	intel_runtime_pm_put(dev_priv);
4124 4125
}

4126 4127
struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
				     struct i915_address_space *vm)
4128 4129
{
	struct i915_vma *vma;
4130
	list_for_each_entry(vma, &obj->vma_list, obj_link) {
4131 4132
		if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL &&
		    vma->vm == vm)
4133
			return vma;
4134 4135 4136 4137 4138 4139 4140 4141
	}
	return NULL;
}

struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
					   const struct i915_ggtt_view *view)
{
	struct i915_vma *vma;
4142

4143
	GEM_BUG_ON(!view);
4144

4145
	list_for_each_entry(vma, &obj->vma_list, obj_link)
4146
		if (vma->is_ggtt && i915_ggtt_view_equal(&vma->ggtt_view, view))
4147
			return vma;
4148 4149 4150
	return NULL;
}

4151
static void
4152
i915_gem_stop_engines(struct drm_device *dev)
4153
{
4154
	struct drm_i915_private *dev_priv = to_i915(dev);
4155
	struct intel_engine_cs *engine;
4156

4157
	for_each_engine(engine, dev_priv)
4158
		dev_priv->gt.stop_engine(engine);
4159 4160
}

4161
int
4162
i915_gem_suspend(struct drm_device *dev)
4163
{
4164
	struct drm_i915_private *dev_priv = to_i915(dev);
4165
	int ret = 0;
4166

4167 4168
	intel_suspend_gt_powersave(dev_priv);

4169
	mutex_lock(&dev->struct_mutex);
4170 4171 4172 4173 4174 4175 4176 4177 4178 4179 4180 4181 4182

	/* We have to flush all the executing contexts to main memory so
	 * that they can saved in the hibernation image. To ensure the last
	 * context image is coherent, we have to switch away from it. That
	 * leaves the dev_priv->kernel_context still active when
	 * we actually suspend, and its image in memory may not match the GPU
	 * state. Fortunately, the kernel_context is disposable and we do
	 * not rely on its state.
	 */
	ret = i915_gem_switch_to_kernel_context(dev_priv);
	if (ret)
		goto err;

4183
	ret = i915_gem_wait_for_idle(dev_priv);
4184
	if (ret)
4185
		goto err;
4186

4187
	i915_gem_retire_requests(dev_priv);
4188

4189 4190 4191 4192 4193
	/* Note that rather than stopping the engines, all we have to do
	 * is assert that every RING_HEAD == RING_TAIL (all execution complete)
	 * and similar for all logical context images (to ensure they are
	 * all ready for hibernation).
	 */
4194
	i915_gem_stop_engines(dev);
4195
	i915_gem_context_lost(dev_priv);
4196 4197
	mutex_unlock(&dev->struct_mutex);

4198
	cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4199 4200
	cancel_delayed_work_sync(&dev_priv->gt.retire_work);
	flush_delayed_work(&dev_priv->gt.idle_work);
4201

4202 4203 4204
	/* Assert that we sucessfully flushed all the work and
	 * reset the GPU back to its idle, low power state.
	 */
4205
	WARN_ON(dev_priv->gt.awake);
4206

4207
	return 0;
4208 4209 4210 4211

err:
	mutex_unlock(&dev->struct_mutex);
	return ret;
4212 4213
}

4214 4215 4216 4217 4218 4219 4220 4221 4222 4223 4224 4225 4226 4227 4228 4229 4230
void i915_gem_resume(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = to_i915(dev);

	mutex_lock(&dev->struct_mutex);
	i915_gem_restore_gtt_mappings(dev);

	/* As we didn't flush the kernel context before suspend, we cannot
	 * guarantee that the context image is complete. So let's just reset
	 * it and start again.
	 */
	if (i915.enable_execlists)
		intel_lr_context_reset(dev_priv, dev_priv->kernel_context);

	mutex_unlock(&dev->struct_mutex);
}

4231 4232
void i915_gem_init_swizzling(struct drm_device *dev)
{
4233
	struct drm_i915_private *dev_priv = to_i915(dev);
4234

4235
	if (INTEL_INFO(dev)->gen < 5 ||
4236 4237 4238 4239 4240 4241
	    dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
		return;

	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
				 DISP_TILE_SURFACE_SWIZZLING);

4242 4243 4244
	if (IS_GEN5(dev))
		return;

4245 4246
	I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
	if (IS_GEN6(dev))
4247
		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4248
	else if (IS_GEN7(dev))
4249
		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
B
Ben Widawsky 已提交
4250 4251
	else if (IS_GEN8(dev))
		I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4252 4253
	else
		BUG();
4254
}
D
Daniel Vetter 已提交
4255

4256 4257
static void init_unused_ring(struct drm_device *dev, u32 base)
{
4258
	struct drm_i915_private *dev_priv = to_i915(dev);
4259 4260 4261 4262 4263 4264 4265 4266 4267 4268 4269 4270 4271 4272 4273 4274 4275 4276 4277 4278 4279 4280 4281 4282

	I915_WRITE(RING_CTL(base), 0);
	I915_WRITE(RING_HEAD(base), 0);
	I915_WRITE(RING_TAIL(base), 0);
	I915_WRITE(RING_START(base), 0);
}

static void init_unused_rings(struct drm_device *dev)
{
	if (IS_I830(dev)) {
		init_unused_ring(dev, PRB1_BASE);
		init_unused_ring(dev, SRB0_BASE);
		init_unused_ring(dev, SRB1_BASE);
		init_unused_ring(dev, SRB2_BASE);
		init_unused_ring(dev, SRB3_BASE);
	} else if (IS_GEN2(dev)) {
		init_unused_ring(dev, SRB0_BASE);
		init_unused_ring(dev, SRB1_BASE);
	} else if (IS_GEN3(dev)) {
		init_unused_ring(dev, PRB1_BASE);
		init_unused_ring(dev, PRB2_BASE);
	}
}

4283 4284 4285
int
i915_gem_init_hw(struct drm_device *dev)
{
4286
	struct drm_i915_private *dev_priv = to_i915(dev);
4287
	struct intel_engine_cs *engine;
C
Chris Wilson 已提交
4288
	int ret;
4289

4290 4291 4292
	/* Double layer security blanket, see i915_gem_init() */
	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);

4293
	if (HAS_EDRAM(dev) && INTEL_GEN(dev_priv) < 9)
4294
		I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4295

4296 4297 4298
	if (IS_HASWELL(dev))
		I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
			   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4299

4300
	if (HAS_PCH_NOP(dev)) {
4301 4302 4303 4304 4305 4306 4307 4308 4309
		if (IS_IVYBRIDGE(dev)) {
			u32 temp = I915_READ(GEN7_MSG_CTL);
			temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
			I915_WRITE(GEN7_MSG_CTL, temp);
		} else if (INTEL_INFO(dev)->gen >= 7) {
			u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
			temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
			I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
		}
4310 4311
	}

4312 4313
	i915_gem_init_swizzling(dev);

4314 4315 4316 4317 4318 4319 4320 4321
	/*
	 * At least 830 can leave some of the unused rings
	 * "active" (ie. head != tail) after resume which
	 * will prevent c3 entry. Makes sure all unused rings
	 * are totally idle.
	 */
	init_unused_rings(dev);

4322
	BUG_ON(!dev_priv->kernel_context);
4323

4324 4325 4326 4327 4328 4329 4330
	ret = i915_ppgtt_init_hw(dev);
	if (ret) {
		DRM_ERROR("PPGTT enable HW failed %d\n", ret);
		goto out;
	}

	/* Need to do basic initialisation of all rings first: */
4331
	for_each_engine(engine, dev_priv) {
4332
		ret = engine->init_hw(engine);
D
Daniel Vetter 已提交
4333
		if (ret)
4334
			goto out;
D
Daniel Vetter 已提交
4335
	}
4336

4337 4338
	intel_mocs_init_l3cc_table(dev);

4339
	/* We can't enable contexts until all firmware is loaded */
4340 4341 4342
	ret = intel_guc_setup(dev);
	if (ret)
		goto out;
4343

4344 4345
out:
	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4346
	return ret;
4347 4348
}

4349 4350 4351 4352 4353 4354 4355 4356 4357 4358 4359 4360 4361 4362 4363 4364 4365 4366 4367 4368 4369
bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value)
{
	if (INTEL_INFO(dev_priv)->gen < 6)
		return false;

	/* TODO: make semaphores and Execlists play nicely together */
	if (i915.enable_execlists)
		return false;

	if (value >= 0)
		return value;

#ifdef CONFIG_INTEL_IOMMU
	/* Enable semaphores on SNB when IO remapping is off */
	if (INTEL_INFO(dev_priv)->gen == 6 && intel_iommu_gfx_mapped)
		return false;
#endif

	return true;
}

4370 4371
int i915_gem_init(struct drm_device *dev)
{
4372
	struct drm_i915_private *dev_priv = to_i915(dev);
4373 4374 4375
	int ret;

	mutex_lock(&dev->struct_mutex);
4376

4377
	if (!i915.enable_execlists) {
4378 4379
		dev_priv->gt.cleanup_engine = intel_engine_cleanup;
		dev_priv->gt.stop_engine = intel_engine_stop;
4380
	} else {
4381 4382
		dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup;
		dev_priv->gt.stop_engine = intel_logical_ring_stop;
4383 4384
	}

4385 4386 4387 4388 4389 4390 4391 4392
	/* This is just a security blanket to placate dragons.
	 * On some systems, we very sporadically observe that the first TLBs
	 * used by the CS may be stale, despite us poking the TLB reset. If
	 * we hold the forcewake during initialisation these problems
	 * just magically go away.
	 */
	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);

4393
	i915_gem_init_userptr(dev_priv);
4394 4395 4396 4397

	ret = i915_gem_init_ggtt(dev_priv);
	if (ret)
		goto out_unlock;
4398

4399
	ret = i915_gem_context_init(dev);
4400 4401
	if (ret)
		goto out_unlock;
4402

4403
	ret = intel_engines_init(dev);
D
Daniel Vetter 已提交
4404
	if (ret)
4405
		goto out_unlock;
4406

4407
	ret = i915_gem_init_hw(dev);
4408
	if (ret == -EIO) {
4409
		/* Allow engine initialisation to fail by marking the GPU as
4410 4411 4412 4413
		 * wedged. But we only want to do this where the GPU is angry,
		 * for all other failure, such as an allocation failure, bail.
		 */
		DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4414
		atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
4415
		ret = 0;
4416
	}
4417 4418

out_unlock:
4419
	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4420
	mutex_unlock(&dev->struct_mutex);
4421

4422
	return ret;
4423 4424
}

4425
void
4426
i915_gem_cleanup_engines(struct drm_device *dev)
4427
{
4428
	struct drm_i915_private *dev_priv = to_i915(dev);
4429
	struct intel_engine_cs *engine;
4430

4431
	for_each_engine(engine, dev_priv)
4432
		dev_priv->gt.cleanup_engine(engine);
4433 4434
}

4435
static void
4436
init_engine_lists(struct intel_engine_cs *engine)
4437
{
4438
	INIT_LIST_HEAD(&engine->request_list);
4439 4440
}

4441 4442 4443
void
i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
{
4444
	struct drm_device *dev = &dev_priv->drm;
4445 4446 4447 4448 4449 4450 4451 4452 4453 4454

	if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) &&
	    !IS_CHERRYVIEW(dev_priv))
		dev_priv->num_fence_regs = 32;
	else if (INTEL_INFO(dev_priv)->gen >= 4 || IS_I945G(dev_priv) ||
		 IS_I945GM(dev_priv) || IS_G33(dev_priv))
		dev_priv->num_fence_regs = 16;
	else
		dev_priv->num_fence_regs = 8;

4455
	if (intel_vgpu_active(dev_priv))
4456 4457 4458 4459 4460 4461 4462 4463 4464
		dev_priv->num_fence_regs =
				I915_READ(vgtif_reg(avail_rs.fence_num));

	/* Initialize fence registers to zero */
	i915_gem_restore_fences(dev);

	i915_gem_detect_bit_6_swizzle(dev);
}

4465
void
4466
i915_gem_load_init(struct drm_device *dev)
4467
{
4468
	struct drm_i915_private *dev_priv = to_i915(dev);
4469 4470
	int i;

4471
	dev_priv->objects =
4472 4473 4474 4475
		kmem_cache_create("i915_gem_object",
				  sizeof(struct drm_i915_gem_object), 0,
				  SLAB_HWCACHE_ALIGN,
				  NULL);
4476 4477 4478 4479 4480
	dev_priv->vmas =
		kmem_cache_create("i915_gem_vma",
				  sizeof(struct i915_vma), 0,
				  SLAB_HWCACHE_ALIGN,
				  NULL);
4481 4482 4483 4484 4485
	dev_priv->requests =
		kmem_cache_create("i915_gem_request",
				  sizeof(struct drm_i915_gem_request), 0,
				  SLAB_HWCACHE_ALIGN,
				  NULL);
4486

4487
	INIT_LIST_HEAD(&dev_priv->context_list);
C
Chris Wilson 已提交
4488 4489
	INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
	INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4490
	INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4491 4492
	for (i = 0; i < I915_NUM_ENGINES; i++)
		init_engine_lists(&dev_priv->engine[i]);
4493
	for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4494
		INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4495
	INIT_DELAYED_WORK(&dev_priv->gt.retire_work,
4496
			  i915_gem_retire_work_handler);
4497
	INIT_DELAYED_WORK(&dev_priv->gt.idle_work,
4498
			  i915_gem_idle_work_handler);
4499
	init_waitqueue_head(&dev_priv->gpu_error.wait_queue);
4500
	init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4501

4502 4503
	dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;

4504
	INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4505

4506
	init_waitqueue_head(&dev_priv->pending_flip_queue);
4507

4508 4509
	dev_priv->mm.interruptible = true;

4510
	mutex_init(&dev_priv->fb_tracking.lock);
4511
}
4512

4513 4514 4515 4516 4517 4518 4519 4520 4521
void i915_gem_load_cleanup(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = to_i915(dev);

	kmem_cache_destroy(dev_priv->requests);
	kmem_cache_destroy(dev_priv->vmas);
	kmem_cache_destroy(dev_priv->objects);
}

4522 4523 4524 4525 4526 4527 4528 4529 4530 4531 4532 4533 4534 4535 4536 4537 4538 4539 4540 4541 4542 4543 4544 4545 4546 4547 4548 4549
int i915_gem_freeze_late(struct drm_i915_private *dev_priv)
{
	struct drm_i915_gem_object *obj;

	/* Called just before we write the hibernation image.
	 *
	 * We need to update the domain tracking to reflect that the CPU
	 * will be accessing all the pages to create and restore from the
	 * hibernation, and so upon restoration those pages will be in the
	 * CPU domain.
	 *
	 * To make sure the hibernation image contains the latest state,
	 * we update that state just before writing out the image.
	 */

	list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
		obj->base.read_domains = I915_GEM_DOMAIN_CPU;
		obj->base.write_domain = I915_GEM_DOMAIN_CPU;
	}

	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
		obj->base.read_domains = I915_GEM_DOMAIN_CPU;
		obj->base.write_domain = I915_GEM_DOMAIN_CPU;
	}

	return 0;
}

4550
void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4551
{
4552
	struct drm_i915_file_private *file_priv = file->driver_priv;
4553
	struct drm_i915_gem_request *request;
4554 4555 4556 4557 4558

	/* Clean up our request list when the client is going away, so that
	 * later retire_requests won't dereference our soon-to-be-gone
	 * file_priv.
	 */
4559
	spin_lock(&file_priv->mm.lock);
4560
	list_for_each_entry(request, &file_priv->mm.request_list, client_list)
4561
		request->file_priv = NULL;
4562
	spin_unlock(&file_priv->mm.lock);
4563

4564
	if (!list_empty(&file_priv->rps.link)) {
4565
		spin_lock(&to_i915(dev)->rps.client_lock);
4566
		list_del(&file_priv->rps.link);
4567
		spin_unlock(&to_i915(dev)->rps.client_lock);
4568
	}
4569 4570 4571 4572 4573
}

int i915_gem_open(struct drm_device *dev, struct drm_file *file)
{
	struct drm_i915_file_private *file_priv;
4574
	int ret;
4575 4576 4577 4578 4579 4580 4581 4582

	DRM_DEBUG_DRIVER("\n");

	file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
	if (!file_priv)
		return -ENOMEM;

	file->driver_priv = file_priv;
4583
	file_priv->dev_priv = to_i915(dev);
4584
	file_priv->file = file;
4585
	INIT_LIST_HEAD(&file_priv->rps.link);
4586 4587 4588 4589

	spin_lock_init(&file_priv->mm.lock);
	INIT_LIST_HEAD(&file_priv->mm.request_list);

4590
	file_priv->bsd_engine = -1;
4591

4592 4593 4594
	ret = i915_gem_context_open(dev, file);
	if (ret)
		kfree(file_priv);
4595

4596
	return ret;
4597 4598
}

4599 4600
/**
 * i915_gem_track_fb - update frontbuffer tracking
4601 4602 4603
 * @old: current GEM buffer for the frontbuffer slots
 * @new: new GEM buffer for the frontbuffer slots
 * @frontbuffer_bits: bitmask of frontbuffer slots
4604 4605 4606 4607
 *
 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
 * from @old and setting them in @new. Both @old and @new can be NULL.
 */
4608 4609 4610 4611 4612 4613 4614 4615 4616 4617 4618 4619 4620 4621 4622 4623 4624
void i915_gem_track_fb(struct drm_i915_gem_object *old,
		       struct drm_i915_gem_object *new,
		       unsigned frontbuffer_bits)
{
	if (old) {
		WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
		WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
		old->frontbuffer_bits &= ~frontbuffer_bits;
	}

	if (new) {
		WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
		WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
		new->frontbuffer_bits |= frontbuffer_bits;
	}
}

4625
/* All the new VM stuff */
4626 4627
u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
			struct i915_address_space *vm)
4628
{
4629
	struct drm_i915_private *dev_priv = to_i915(o->base.dev);
4630 4631
	struct i915_vma *vma;

4632
	WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
4633

4634
	list_for_each_entry(vma, &o->vma_list, obj_link) {
4635
		if (vma->is_ggtt &&
4636 4637 4638
		    vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
			continue;
		if (vma->vm == vm)
4639 4640
			return vma->node.start;
	}
4641

4642 4643
	WARN(1, "%s vma for this object not found.\n",
	     i915_is_ggtt(vm) ? "global" : "ppgtt");
4644 4645 4646
	return -1;
}

4647 4648
u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
				  const struct i915_ggtt_view *view)
4649 4650 4651
{
	struct i915_vma *vma;

4652
	list_for_each_entry(vma, &o->vma_list, obj_link)
4653
		if (vma->is_ggtt && i915_ggtt_view_equal(&vma->ggtt_view, view))
4654 4655
			return vma->node.start;

4656
	WARN(1, "global vma for this object not found. (view=%u)\n", view->type);
4657 4658 4659 4660 4661 4662 4663 4664
	return -1;
}

bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
			struct i915_address_space *vm)
{
	struct i915_vma *vma;

4665
	list_for_each_entry(vma, &o->vma_list, obj_link) {
4666
		if (vma->is_ggtt &&
4667 4668 4669 4670 4671 4672 4673 4674 4675 4676
		    vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
			continue;
		if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
			return true;
	}

	return false;
}

bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
4677
				  const struct i915_ggtt_view *view)
4678 4679 4680
{
	struct i915_vma *vma;

4681
	list_for_each_entry(vma, &o->vma_list, obj_link)
4682
		if (vma->is_ggtt &&
4683
		    i915_ggtt_view_equal(&vma->ggtt_view, view) &&
4684
		    drm_mm_node_allocated(&vma->node))
4685 4686 4687 4688 4689
			return true;

	return false;
}

4690
unsigned long i915_gem_obj_ggtt_size(struct drm_i915_gem_object *o)
4691 4692 4693
{
	struct i915_vma *vma;

4694
	GEM_BUG_ON(list_empty(&o->vma_list));
4695

4696
	list_for_each_entry(vma, &o->vma_list, obj_link) {
4697
		if (vma->is_ggtt &&
4698
		    vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
4699
			return vma->node.size;
4700
	}
4701

4702 4703 4704
	return 0;
}

4705
bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj)
4706 4707
{
	struct i915_vma *vma;
4708
	list_for_each_entry(vma, &obj->vma_list, obj_link)
4709 4710
		if (vma->pin_count > 0)
			return true;
4711

4712
	return false;
4713
}
4714

4715 4716 4717 4718 4719 4720 4721
/* Like i915_gem_object_get_page(), but mark the returned page dirty */
struct page *
i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n)
{
	struct page *page;

	/* Only default objects have per-page dirty tracking */
4722
	if (WARN_ON(!i915_gem_object_has_struct_page(obj)))
4723 4724 4725 4726 4727 4728 4729
		return NULL;

	page = i915_gem_object_get_page(obj, n);
	set_page_dirty(page);
	return page;
}

4730 4731 4732 4733 4734 4735 4736 4737 4738 4739
/* Allocate a new GEM object and fill it with the supplied data */
struct drm_i915_gem_object *
i915_gem_object_create_from_data(struct drm_device *dev,
			         const void *data, size_t size)
{
	struct drm_i915_gem_object *obj;
	struct sg_table *sg;
	size_t bytes;
	int ret;

4740
	obj = i915_gem_object_create(dev, round_up(size, PAGE_SIZE));
4741
	if (IS_ERR(obj))
4742 4743 4744 4745 4746 4747 4748 4749 4750 4751 4752 4753 4754
		return obj;

	ret = i915_gem_object_set_to_cpu_domain(obj, true);
	if (ret)
		goto fail;

	ret = i915_gem_object_get_pages(obj);
	if (ret)
		goto fail;

	i915_gem_object_pin_pages(obj);
	sg = obj->pages;
	bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size);
4755
	obj->dirty = 1;		/* Backing store is now out of date */
4756 4757 4758 4759 4760 4761 4762 4763 4764 4765 4766
	i915_gem_object_unpin_pages(obj);

	if (WARN_ON(bytes != size)) {
		DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size);
		ret = -EFAULT;
		goto fail;
	}

	return obj;

fail:
4767
	i915_gem_object_put(obj);
4768 4769
	return ERR_PTR(ret);
}