i915_drv.h 116.2 KB
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/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
 */
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/*
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 *
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#ifndef _I915_DRV_H_
#define _I915_DRV_H_

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#include <uapi/drm/i915_drm.h>
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#include <uapi/drm/drm_fourcc.h>
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#include <linux/io-mapping.h>
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include <linux/backlight.h>
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#include <linux/hash.h>
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#include <linux/intel-iommu.h>
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#include <linux/kref.h>
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#include <linux/perf_event.h>
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#include <linux/pm_qos.h>
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#include <linux/reservation.h>
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#include <linux/shmem_fs.h>

#include <drm/drmP.h>
#include <drm/intel-gtt.h>
#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
#include <drm/drm_gem.h>
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#include <drm/drm_auth.h>
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#include <drm/drm_cache.h>
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#include "i915_params.h"
#include "i915_reg.h"
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#include "i915_utils.h"
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#include "intel_bios.h"
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#include "intel_device_info.h"
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#include "intel_display.h"
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#include "intel_dpll_mgr.h"
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#include "intel_lrc.h"
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#include "intel_opregion.h"
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#include "intel_ringbuffer.h"
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#include "intel_uncore.h"
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#include "intel_wopcm.h"
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#include "intel_uc.h"
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#include "i915_gem.h"
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#include "i915_gem_context.h"
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#include "i915_gem_fence_reg.h"
#include "i915_gem_object.h"
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#include "i915_gem_gtt.h"
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#include "i915_gem_timeline.h"
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#include "i915_gpu_error.h"
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#include "i915_request.h"
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#include "i915_scheduler.h"
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#include "i915_vma.h"

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#include "intel_gvt.h"

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/* General customization:
 */

#define DRIVER_NAME		"i915"
#define DRIVER_DESC		"Intel Graphics"
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#define DRIVER_DATE		"20180413"
#define DRIVER_TIMESTAMP	1523611258
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/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
 * which may not necessarily be a user visible problem.  This will either
 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
 * enable distros and users to tailor their preferred amount of i915 abrt
 * spam.
 */
#define I915_STATE_WARN(condition, format...) ({			\
	int __ret_warn_on = !!(condition);				\
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	if (unlikely(__ret_warn_on))					\
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		if (!WARN(i915_modparams.verbose_state_checks, format))	\
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			DRM_ERROR(format);				\
	unlikely(__ret_warn_on);					\
})

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#define I915_STATE_WARN_ON(x)						\
	I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
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#if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
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bool __i915_inject_load_failure(const char *func, int line);
#define i915_inject_load_failure() \
	__i915_inject_load_failure(__func__, __LINE__)
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#else
#define i915_inject_load_failure() false
#endif
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typedef struct {
	uint32_t val;
} uint_fixed_16_16_t;

#define FP_16_16_MAX ({ \
	uint_fixed_16_16_t fp; \
	fp.val = UINT_MAX; \
	fp; \
})

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static inline bool is_fixed16_zero(uint_fixed_16_16_t val)
{
	if (val.val == 0)
		return true;
	return false;
}

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static inline uint_fixed_16_16_t u32_to_fixed16(uint32_t val)
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{
	uint_fixed_16_16_t fp;

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	WARN_ON(val > U16_MAX);
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	fp.val = val << 16;
	return fp;
}

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static inline uint32_t fixed16_to_u32_round_up(uint_fixed_16_16_t fp)
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{
	return DIV_ROUND_UP(fp.val, 1 << 16);
}

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static inline uint32_t fixed16_to_u32(uint_fixed_16_16_t fp)
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{
	return fp.val >> 16;
}

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static inline uint_fixed_16_16_t min_fixed16(uint_fixed_16_16_t min1,
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						 uint_fixed_16_16_t min2)
{
	uint_fixed_16_16_t min;

	min.val = min(min1.val, min2.val);
	return min;
}

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static inline uint_fixed_16_16_t max_fixed16(uint_fixed_16_16_t max1,
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						 uint_fixed_16_16_t max2)
{
	uint_fixed_16_16_t max;

	max.val = max(max1.val, max2.val);
	return max;
}

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static inline uint_fixed_16_16_t clamp_u64_to_fixed16(uint64_t val)
{
	uint_fixed_16_16_t fp;
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	WARN_ON(val > U32_MAX);
	fp.val = (uint32_t) val;
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	return fp;
}

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static inline uint32_t div_round_up_fixed16(uint_fixed_16_16_t val,
					    uint_fixed_16_16_t d)
{
	return DIV_ROUND_UP(val.val, d.val);
}

static inline uint32_t mul_round_up_u32_fixed16(uint32_t val,
						uint_fixed_16_16_t mul)
{
	uint64_t intermediate_val;

	intermediate_val = (uint64_t) val * mul.val;
	intermediate_val = DIV_ROUND_UP_ULL(intermediate_val, 1 << 16);
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	WARN_ON(intermediate_val > U32_MAX);
	return (uint32_t) intermediate_val;
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}

static inline uint_fixed_16_16_t mul_fixed16(uint_fixed_16_16_t val,
					     uint_fixed_16_16_t mul)
{
	uint64_t intermediate_val;

	intermediate_val = (uint64_t) val.val * mul.val;
	intermediate_val = intermediate_val >> 16;
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	return clamp_u64_to_fixed16(intermediate_val);
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}

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static inline uint_fixed_16_16_t div_fixed16(uint32_t val, uint32_t d)
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{
	uint64_t interm_val;

	interm_val = (uint64_t)val << 16;
	interm_val = DIV_ROUND_UP_ULL(interm_val, d);
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	return clamp_u64_to_fixed16(interm_val);
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}

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static inline uint32_t div_round_up_u32_fixed16(uint32_t val,
						uint_fixed_16_16_t d)
{
	uint64_t interm_val;

	interm_val = (uint64_t)val << 16;
	interm_val = DIV_ROUND_UP_ULL(interm_val, d.val);
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	WARN_ON(interm_val > U32_MAX);
	return (uint32_t) interm_val;
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}

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static inline uint_fixed_16_16_t mul_u32_fixed16(uint32_t val,
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						     uint_fixed_16_16_t mul)
{
	uint64_t intermediate_val;

	intermediate_val = (uint64_t) val * mul.val;
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	return clamp_u64_to_fixed16(intermediate_val);
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}

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static inline uint_fixed_16_16_t add_fixed16(uint_fixed_16_16_t add1,
					     uint_fixed_16_16_t add2)
{
	uint64_t interm_sum;

	interm_sum = (uint64_t) add1.val + add2.val;
	return clamp_u64_to_fixed16(interm_sum);
}

static inline uint_fixed_16_16_t add_fixed16_u32(uint_fixed_16_16_t add1,
						 uint32_t add2)
{
	uint64_t interm_sum;
	uint_fixed_16_16_t interm_add2 = u32_to_fixed16(add2);

	interm_sum = (uint64_t) add1.val + interm_add2.val;
	return clamp_u64_to_fixed16(interm_sum);
}

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enum hpd_pin {
	HPD_NONE = 0,
	HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
	HPD_CRT,
	HPD_SDVO_B,
	HPD_SDVO_C,
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	HPD_PORT_A,
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	HPD_PORT_B,
	HPD_PORT_C,
	HPD_PORT_D,
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	HPD_PORT_E,
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	HPD_PORT_F,
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	HPD_NUM_PINS
};

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#define for_each_hpd_pin(__pin) \
	for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)

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#define HPD_STORM_DEFAULT_THRESHOLD 5

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struct i915_hotplug {
	struct work_struct hotplug_work;

	struct {
		unsigned long last_jiffies;
		int count;
		enum {
			HPD_ENABLED = 0,
			HPD_DISABLED = 1,
			HPD_MARK_DISABLED = 2
		} state;
	} stats[HPD_NUM_PINS];
	u32 event_bits;
	struct delayed_work reenable_work;

	struct intel_digital_port *irq_port[I915_MAX_PORTS];
	u32 long_port_mask;
	u32 short_port_mask;
	struct work_struct dig_port_work;

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	struct work_struct poll_init_work;
	bool poll_enabled;

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	unsigned int hpd_storm_threshold;

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	/*
	 * if we get a HPD irq from DP and a HPD irq from non-DP
	 * the non-DP HPD could block the workqueue on a mode config
	 * mutex getting, that userspace may have taken. However
	 * userspace is waiting on the DP workqueue to run which is
	 * blocked behind the non-DP one.
	 */
	struct workqueue_struct *dp_wq;
};

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#define I915_GEM_GPU_DOMAINS \
	(I915_GEM_DOMAIN_RENDER | \
	 I915_GEM_DOMAIN_SAMPLER | \
	 I915_GEM_DOMAIN_COMMAND | \
	 I915_GEM_DOMAIN_INSTRUCTION | \
	 I915_GEM_DOMAIN_VERTEX)
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struct drm_i915_private;
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struct i915_mm_struct;
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struct i915_mmu_object;
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struct drm_i915_file_private {
	struct drm_i915_private *dev_priv;
	struct drm_file *file;

	struct {
		spinlock_t lock;
		struct list_head request_list;
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/* 20ms is a fairly arbitrary limit (greater than the average frame time)
 * chosen to prevent the CPU getting more than a frame ahead of the GPU
 * (when using lax throttling for the frontbuffer). We also use it to
 * offer free GPU waitboosts for severely congested workloads.
 */
#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
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	} mm;
	struct idr context_idr;

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	struct intel_rps_client {
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		atomic_t boosts;
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	} rps_client;
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	unsigned int bsd_engine;
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/* Client can have a maximum of 3 contexts banned before
 * it is denied of creating new contexts. As one context
 * ban needs 4 consecutive hangs, and more if there is
 * progress in between, this is a last resort stop gap measure
 * to limit the badly behaving clients access to gpu.
 */
#define I915_MAX_CLIENT_CONTEXT_BANS 3
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	atomic_t context_bans;
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};

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/* Interface history:
 *
 * 1.1: Original.
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 * 1.2: Add Power Management
 * 1.3: Add vblank support
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 * 1.4: Fix cmdbuffer path, add heap destroy
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 * 1.5: Add vblank pipe configuration
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 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 *      - Support vertical blank on secondary display pipe
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 */
#define DRIVER_MAJOR		1
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#define DRIVER_MINOR		6
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#define DRIVER_PATCHLEVEL	0

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struct intel_overlay;
struct intel_overlay_error_state;

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struct sdvo_device_mapping {
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	u8 initialized;
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	u8 dvo_port;
	u8 slave_addr;
	u8 dvo_wiring;
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	u8 i2c_pin;
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	u8 ddc_pin;
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};

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struct intel_connector;
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struct intel_encoder;
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struct intel_atomic_state;
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struct intel_crtc_state;
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struct intel_initial_plane_config;
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struct intel_crtc;
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struct intel_limit;
struct dpll;
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struct intel_cdclk_state;
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struct drm_i915_display_funcs {
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	void (*get_cdclk)(struct drm_i915_private *dev_priv,
			  struct intel_cdclk_state *cdclk_state);
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	void (*set_cdclk)(struct drm_i915_private *dev_priv,
			  const struct intel_cdclk_state *cdclk_state);
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	int (*get_fifo_size)(struct drm_i915_private *dev_priv,
			     enum i9xx_plane_id i9xx_plane);
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	int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
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	int (*compute_intermediate_wm)(struct drm_device *dev,
				       struct intel_crtc *intel_crtc,
				       struct intel_crtc_state *newstate);
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	void (*initial_watermarks)(struct intel_atomic_state *state,
				   struct intel_crtc_state *cstate);
	void (*atomic_update_watermarks)(struct intel_atomic_state *state,
					 struct intel_crtc_state *cstate);
	void (*optimize_watermarks)(struct intel_atomic_state *state,
				    struct intel_crtc_state *cstate);
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	int (*compute_global_watermarks)(struct drm_atomic_state *state);
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	void (*update_wm)(struct intel_crtc *crtc);
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	int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
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	/* Returns the active state of the crtc, and if the crtc is active,
	 * fills out the pipe-config with the hw state. */
	bool (*get_pipe_config)(struct intel_crtc *,
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				struct intel_crtc_state *);
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	void (*get_initial_plane_config)(struct intel_crtc *,
					 struct intel_initial_plane_config *);
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	int (*crtc_compute_clock)(struct intel_crtc *crtc,
				  struct intel_crtc_state *crtc_state);
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	void (*crtc_enable)(struct intel_crtc_state *pipe_config,
			    struct drm_atomic_state *old_state);
	void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
			     struct drm_atomic_state *old_state);
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	void (*update_crtcs)(struct drm_atomic_state *state);
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	void (*audio_codec_enable)(struct intel_encoder *encoder,
				   const struct intel_crtc_state *crtc_state,
				   const struct drm_connector_state *conn_state);
	void (*audio_codec_disable)(struct intel_encoder *encoder,
				    const struct intel_crtc_state *old_crtc_state,
				    const struct drm_connector_state *old_conn_state);
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	void (*fdi_link_train)(struct intel_crtc *crtc,
			       const struct intel_crtc_state *crtc_state);
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	void (*init_clock_gating)(struct drm_i915_private *dev_priv);
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	void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
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	/* clock updates for mode set */
	/* cursor updates */
	/* render clock increase/decrease */
	/* display clock increase/decrease */
	/* pll clock increase/decrease */
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	void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
	void (*load_luts)(struct drm_crtc_state *crtc_state);
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};

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#define CSR_VERSION(major, minor)	((major) << 16 | (minor))
#define CSR_VERSION_MAJOR(version)	((version) >> 16)
#define CSR_VERSION_MINOR(version)	((version) & 0xffff)

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struct intel_csr {
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	struct work_struct work;
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	const char *fw_path;
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	uint32_t *dmc_payload;
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	uint32_t dmc_fw_size;
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	uint32_t version;
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	uint32_t mmio_count;
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	i915_reg_t mmioaddr[8];
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	uint32_t mmiodata[8];
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	uint32_t dc_state;
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	uint32_t allowed_dc_mask;
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};

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enum i915_cache_level {
	I915_CACHE_NONE = 0,
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	I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
	I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
			      caches, eg sampler/render caches, and the
			      large Last-Level-Cache. LLC is coherent with
			      the CPU, but L3 is only visible to the GPU. */
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	I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
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};

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#define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */

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enum fb_op_origin {
	ORIGIN_GTT,
	ORIGIN_CPU,
	ORIGIN_CS,
	ORIGIN_FLIP,
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	ORIGIN_DIRTYFB,
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};

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struct intel_fbc {
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	/* This is always the inner lock when overlapping with struct_mutex and
	 * it's the outer lock when overlapping with stolen_lock. */
	struct mutex lock;
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	unsigned threshold;
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	unsigned int possible_framebuffer_bits;
	unsigned int busy_bits;
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	unsigned int visible_pipes_mask;
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	struct intel_crtc *crtc;
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	struct drm_mm_node compressed_fb;
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	struct drm_mm_node *compressed_llb;

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	bool false_color;

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	bool enabled;
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	bool active;
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	bool underrun_detected;
	struct work_struct underrun_work;

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	/*
	 * Due to the atomic rules we can't access some structures without the
	 * appropriate locking, so we cache information here in order to avoid
	 * these problems.
	 */
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	struct intel_fbc_state_cache {
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		struct i915_vma *vma;
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		unsigned long flags;
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		struct {
			unsigned int mode_flags;
			uint32_t hsw_bdw_pixel_rate;
		} crtc;

		struct {
			unsigned int rotation;
			int src_w;
			int src_h;
			bool visible;
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			/*
			 * Display surface base address adjustement for
			 * pageflips. Note that on gen4+ this only adjusts up
			 * to a tile, offsets within a tile are handled in
			 * the hw itself (with the TILEOFF register).
			 */
			int adjusted_x;
			int adjusted_y;
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			int y;
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		} plane;

		struct {
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			const struct drm_format_info *format;
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			unsigned int stride;
		} fb;
	} state_cache;

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	/*
	 * This structure contains everything that's relevant to program the
	 * hardware registers. When we want to figure out if we need to disable
	 * and re-enable FBC for a new configuration we just check if there's
	 * something different in the struct. The genx_fbc_activate functions
	 * are supposed to read from it in order to program the registers.
	 */
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	struct intel_fbc_reg_params {
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		struct i915_vma *vma;
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		unsigned long flags;
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		struct {
			enum pipe pipe;
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			enum i9xx_plane_id i9xx_plane;
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			unsigned int fence_y_offset;
		} crtc;

		struct {
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			const struct drm_format_info *format;
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			unsigned int stride;
		} fb;

		int cfb_size;
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		unsigned int gen9_wa_cfb_stride;
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	} params;

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	struct intel_fbc_work {
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		bool scheduled;
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		u64 scheduled_vblank;
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		struct work_struct work;
	} work;
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	const char *no_fbc_reason;
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};

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/*
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 * HIGH_RR is the highest eDP panel refresh rate read from EDID
 * LOW_RR is the lowest eDP panel refresh rate found from EDID
 * parsing for same resolution.
 */
enum drrs_refresh_rate_type {
	DRRS_HIGH_RR,
	DRRS_LOW_RR,
	DRRS_MAX_RR, /* RR count */
};

enum drrs_support_type {
	DRRS_NOT_SUPPORTED = 0,
	STATIC_DRRS_SUPPORT = 1,
	SEAMLESS_DRRS_SUPPORT = 2
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};

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struct intel_dp;
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struct i915_drrs {
	struct mutex mutex;
	struct delayed_work work;
	struct intel_dp *dp;
	unsigned busy_frontbuffer_bits;
	enum drrs_refresh_rate_type refresh_rate_type;
	enum drrs_support_type type;
};

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struct i915_psr {
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	struct mutex lock;
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	bool sink_support;
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	struct intel_dp *enabled;
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	bool active;
	struct delayed_work work;
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	unsigned busy_frontbuffer_bits;
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	bool sink_psr2_support;
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	bool link_standby;
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	bool colorimetry_support;
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	bool alpm;
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	bool has_hw_tracking;
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	bool psr2_enabled;
612
	u8 sink_sync_latency;
613
	bool debug;
614

615 616
	void (*enable_source)(struct intel_dp *,
			      const struct intel_crtc_state *);
617 618
	void (*disable_source)(struct intel_dp *,
			       const struct intel_crtc_state *);
619
	void (*enable_sink)(struct intel_dp *);
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Rodrigo Vivi 已提交
620
	void (*activate)(struct intel_dp *);
621
	void (*setup_vsc)(struct intel_dp *, const struct intel_crtc_state *);
622
};
623

624
enum intel_pch {
625
	PCH_NONE = 0,	/* No PCH present */
626
	PCH_IBX,	/* Ibexpeak PCH */
627 628
	PCH_CPT,	/* Cougarpoint/Pantherpoint PCH */
	PCH_LPT,	/* Lynxpoint/Wildcatpoint PCH */
629
	PCH_SPT,        /* Sunrisepoint PCH */
630 631
	PCH_KBP,        /* Kaby Lake PCH */
	PCH_CNP,        /* Cannon Lake PCH */
632
	PCH_ICP,	/* Ice Lake PCH */
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Ben Widawsky 已提交
633
	PCH_NOP,
634 635
};

636 637 638 639 640
enum intel_sbi_destination {
	SBI_ICLK,
	SBI_MPHY,
};

641
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
642
#define QUIRK_INVERT_BRIGHTNESS (1<<2)
643
#define QUIRK_BACKLIGHT_PRESENT (1<<3)
644
#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
645
#define QUIRK_INCREASE_T12_DELAY (1<<6)
646

647
struct intel_fbdev;
648
struct intel_fbc_work;
649

650 651
struct intel_gmbus {
	struct i2c_adapter adapter;
652
#define GMBUS_FORCE_BIT_RETRY (1U << 31)
653
	u32 force_bit;
654
	u32 reg0;
655
	i915_reg_t gpio_reg;
656
	struct i2c_algo_bit_data bit_algo;
657 658 659
	struct drm_i915_private *dev_priv;
};

660
struct i915_suspend_saved_registers {
661
	u32 saveDSPARB;
J
Jesse Barnes 已提交
662
	u32 saveFBC_CONTROL;
663 664
	u32 saveCACHE_MODE_0;
	u32 saveMI_ARB_STATE;
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Jesse Barnes 已提交
665 666
	u32 saveSWF0[16];
	u32 saveSWF1[16];
667
	u32 saveSWF3[3];
668
	uint64_t saveFENCE[I915_MAX_NUM_FENCES];
669
	u32 savePCH_PORT_HOTPLUG;
670
	u16 saveGCDGMBUS;
671
};
672

673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730
struct vlv_s0ix_state {
	/* GAM */
	u32 wr_watermark;
	u32 gfx_prio_ctrl;
	u32 arb_mode;
	u32 gfx_pend_tlb0;
	u32 gfx_pend_tlb1;
	u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
	u32 media_max_req_count;
	u32 gfx_max_req_count;
	u32 render_hwsp;
	u32 ecochk;
	u32 bsd_hwsp;
	u32 blt_hwsp;
	u32 tlb_rd_addr;

	/* MBC */
	u32 g3dctl;
	u32 gsckgctl;
	u32 mbctl;

	/* GCP */
	u32 ucgctl1;
	u32 ucgctl3;
	u32 rcgctl1;
	u32 rcgctl2;
	u32 rstctl;
	u32 misccpctl;

	/* GPM */
	u32 gfxpause;
	u32 rpdeuhwtc;
	u32 rpdeuc;
	u32 ecobus;
	u32 pwrdwnupctl;
	u32 rp_down_timeout;
	u32 rp_deucsw;
	u32 rcubmabdtmr;
	u32 rcedata;
	u32 spare2gh;

	/* Display 1 CZ domain */
	u32 gt_imr;
	u32 gt_ier;
	u32 pm_imr;
	u32 pm_ier;
	u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];

	/* GT SA CZ domain */
	u32 tilectl;
	u32 gt_fifoctl;
	u32 gtlc_wake_ctrl;
	u32 gtlc_survive;
	u32 pmwgicz;

	/* Display 2 CZ domain */
	u32 gu_ctl0;
	u32 gu_ctl1;
731
	u32 pcbr;
732 733 734
	u32 clock_gate_dis2;
};

735
struct intel_rps_ei {
736
	ktime_t ktime;
737 738
	u32 render_c0;
	u32 media_c0;
739 740
};

741
struct intel_rps {
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Imre Deak 已提交
742 743 744 745
	/*
	 * work, interrupts_enabled and pm_iir are protected by
	 * dev_priv->irq_lock
	 */
746
	struct work_struct work;
I
Imre Deak 已提交
747
	bool interrupts_enabled;
748
	u32 pm_iir;
749

750
	/* PM interrupt bits that should never be masked */
751
	u32 pm_intrmsk_mbz;
752

753 754 755 756 757 758 759 760 761 762 763 764 765 766 767
	/* Frequencies are stored in potentially platform dependent multiples.
	 * In other words, *_freq needs to be multiplied by X to be interesting.
	 * Soft limits are those which are used for the dynamic reclocking done
	 * by the driver (raise frequencies under heavy loads, and lower for
	 * lighter loads). Hard limits are those imposed by the hardware.
	 *
	 * A distinction is made for overclocking, which is never enabled by
	 * default, and is considered to be above the hard limit if it's
	 * possible at all.
	 */
	u8 cur_freq;		/* Current frequency (cached, may not == HW) */
	u8 min_freq_softlimit;	/* Minimum frequency permitted by the driver */
	u8 max_freq_softlimit;	/* Max frequency permitted by the driver */
	u8 max_freq;		/* Maximum frequency, RP0 if not overclocking */
	u8 min_freq;		/* AKA RPn. Minimum frequency */
768
	u8 boost_freq;		/* Frequency to request when wait boosting */
769
	u8 idle_freq;		/* Frequency to request when we are idle */
770 771 772
	u8 efficient_freq;	/* AKA RPe. Pre-determined balanced frequency */
	u8 rp1_freq;		/* "less than" RP0 power/freqency */
	u8 rp0_freq;		/* Non-overclocked max frequency. */
773
	u16 gpll_ref_freq;	/* vlv/chv GPLL reference frequency */
774

775 776 777
	u8 up_threshold; /* Current %busy required to uplock */
	u8 down_threshold; /* Current %busy required to downclock */

778 779 780
	int last_adj;
	enum { LOW_POWER, BETWEEN, HIGH_POWER } power;

781
	bool enabled;
782 783
	atomic_t num_waiters;
	atomic_t boosts;
784

785
	/* manual wa residency calculations */
786
	struct intel_rps_ei ei;
787 788
};

789 790
struct intel_rc6 {
	bool enabled;
791 792
	u64 prev_hw_residency[4];
	u64 cur_residency[4];
793 794 795 796 797 798
};

struct intel_llc_pstate {
	bool enabled;
};

799 800
struct intel_gen6_power_mgmt {
	struct intel_rps rps;
801 802
	struct intel_rc6 rc6;
	struct intel_llc_pstate llc_pstate;
803 804
};

D
Daniel Vetter 已提交
805 806 807
/* defined intel_pm.c */
extern spinlock_t mchdev_lock;

808 809 810 811 812 813 814 815 816 817 818
struct intel_ilk_power_mgmt {
	u8 cur_delay;
	u8 min_delay;
	u8 max_delay;
	u8 fmax;
	u8 fstart;

	u64 last_count1;
	unsigned long last_time1;
	unsigned long chipset_power;
	u64 last_count2;
819
	u64 last_time2;
820 821 822 823 824 825 826
	unsigned long gfx_power;
	u8 corr;

	int c_m;
	int r_t;
};

827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856
struct drm_i915_private;
struct i915_power_well;

struct i915_power_well_ops {
	/*
	 * Synchronize the well's hw state to match the current sw state, for
	 * example enable/disable it based on the current refcount. Called
	 * during driver init and resume time, possibly after first calling
	 * the enable/disable handlers.
	 */
	void (*sync_hw)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/*
	 * Enable the well and resources that depend on it (for example
	 * interrupts located on the well). Called after the 0->1 refcount
	 * transition.
	 */
	void (*enable)(struct drm_i915_private *dev_priv,
		       struct i915_power_well *power_well);
	/*
	 * Disable the well and resources that depend on it. Called after
	 * the 1->0 refcount transition.
	 */
	void (*disable)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/* Returns the hw enabled state. */
	bool (*is_enabled)(struct drm_i915_private *dev_priv,
			   struct i915_power_well *power_well);
};

857 858
/* Power well structure for haswell */
struct i915_power_well {
859
	const char *name;
860
	bool always_on;
861 862
	/* power well enable/disable usage count */
	int count;
863 864
	/* cached hw enabled state */
	bool hw_enabled;
865
	u64 domains;
866
	/* unique identifier for this power well */
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Imre Deak 已提交
867
	enum i915_power_well_id id;
868 869 870 871
	/*
	 * Arbitraty data associated with this power well. Platform and power
	 * well specific.
	 */
872 873 874 875
	union {
		struct {
			enum dpio_phy phy;
		} bxt;
876 877 878 879 880
		struct {
			/* Mask of pipes whose IRQ logic is backed by the pw */
			u8 irq_pipe_mask;
			/* The pw is backing the VGA functionality */
			bool has_vga:1;
881
			bool has_fuses:1;
882
		} hsw;
883
	};
884
	const struct i915_power_well_ops *ops;
885 886
};

887
struct i915_power_domains {
888 889 890 891 892
	/*
	 * Power wells needed for initialization at driver init and suspend
	 * time are on. They are kept on until after the first modeset.
	 */
	bool init_power_on;
893
	bool initializing;
894
	int power_well_count;
895

896
	struct mutex lock;
897
	int domain_use_count[POWER_DOMAIN_NUM];
898
	struct i915_power_well *power_wells;
899 900
};

901
#define MAX_L3_SLICES 2
902
struct intel_l3_parity {
903
	u32 *remap_info[MAX_L3_SLICES];
904
	struct work_struct error_work;
905
	int which_slice;
906 907
};

908 909 910
struct i915_gem_mm {
	/** Memory allocator for GTT stolen memory */
	struct drm_mm stolen;
911 912 913 914
	/** Protects the usage of the GTT stolen memory allocator. This is
	 * always the inner lock when overlapping with struct_mutex. */
	struct mutex stolen_lock;

915 916 917
	/* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
	spinlock_t obj_lock;

918 919 920 921 922
	/** List of all objects in gtt_space. Used to restore gtt
	 * mappings on resume */
	struct list_head bound_list;
	/**
	 * List of objects which are not bound to the GTT (thus
923 924
	 * are idle and not used by the GPU). These objects may or may
	 * not actually have any pages attached.
925 926 927
	 */
	struct list_head unbound_list;

928 929 930 931 932
	/** List of all objects in gtt_space, currently mmaped by userspace.
	 * All objects within this list must also be on bound_list.
	 */
	struct list_head userfault_list;

933 934 935 936 937
	/**
	 * List of objects which are pending destruction.
	 */
	struct llist_head free_list;
	struct work_struct free_work;
938
	spinlock_t free_lock;
939 940 941 942 943
	/**
	 * Count of objects pending destructions. Used to skip needlessly
	 * waiting on an RCU barrier if no objects are waiting to be freed.
	 */
	atomic_t free_count;
944

945 946 947 948 949
	/**
	 * Small stash of WC pages
	 */
	struct pagevec wc_stash;

M
Matthew Auld 已提交
950 951 952 953 954
	/**
	 * tmpfs instance used for shmem backed objects
	 */
	struct vfsmount *gemfs;

955 956 957
	/** PPGTT used for aliasing the PPGTT with the GTT */
	struct i915_hw_ppgtt *aliasing_ppgtt;

958
	struct notifier_block oom_notifier;
959
	struct notifier_block vmap_notifier;
960
	struct shrinker shrinker;
961 962 963 964

	/** LRU list of objects with fence regs on them. */
	struct list_head fence_list;

965 966 967 968 969 970 971
	/**
	 * Workqueue to fault in userptr pages, flushed by the execbuf
	 * when required but otherwise left to userspace to try again
	 * on EAGAIN.
	 */
	struct workqueue_struct *userptr_wq;

972 973
	u64 unordered_timeline;

974
	/* the indicator for dispatch video commands on two BSD rings */
975
	atomic_t bsd_engine_dispatch_index;
976

977 978 979 980 981 982
	/** Bit 6 swizzling required for X tiling */
	uint32_t bit_6_swizzle_x;
	/** Bit 6 swizzling required for Y tiling */
	uint32_t bit_6_swizzle_y;

	/* accounting, useful for userland debugging */
983
	spinlock_t object_stat_lock;
984
	u64 object_memory;
985 986 987
	u32 object_count;
};

988 989
#define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */

990 991 992
#define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
#define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */

993 994 995
#define I915_ENGINE_DEAD_TIMEOUT  (4 * HZ)  /* Seqno, head and subunits dead */
#define I915_SEQNO_DEAD_TIMEOUT   (12 * HZ) /* Seqno dead with active head */

996 997 998 999 1000 1001
enum modeset_restore {
	MODESET_ON_LID_OPEN,
	MODESET_DONE,
	MODESET_SUSPENDED,
};

1002 1003 1004 1005
#define DP_AUX_A 0x40
#define DP_AUX_B 0x10
#define DP_AUX_C 0x20
#define DP_AUX_D 0x30
R
Rodrigo Vivi 已提交
1006
#define DP_AUX_F 0x60
1007

X
Xiong Zhang 已提交
1008 1009 1010 1011
#define DDC_PIN_B  0x05
#define DDC_PIN_C  0x04
#define DDC_PIN_D  0x06

1012
struct ddi_vbt_port_info {
1013 1014
	int max_tmds_clock;

1015 1016 1017 1018 1019 1020
	/*
	 * This is an index in the HDMI/DVI DDI buffer translation table.
	 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
	 * populate this field.
	 */
#define HDMI_LEVEL_SHIFT_UNKNOWN	0xff
1021
	uint8_t hdmi_level_shift;
1022 1023 1024 1025

	uint8_t supports_dvi:1;
	uint8_t supports_hdmi:1;
	uint8_t supports_dp:1;
1026
	uint8_t supports_edp:1;
1027 1028

	uint8_t alternate_aux_channel;
X
Xiong Zhang 已提交
1029
	uint8_t alternate_ddc_pin;
1030 1031 1032

	uint8_t dp_boost_level;
	uint8_t hdmi_boost_level;
1033
	int dp_max_link_rate;		/* 0 for not limited by VBT */
1034 1035
};

R
Rodrigo Vivi 已提交
1036 1037 1038 1039 1040
enum psr_lines_to_wait {
	PSR_0_LINES_TO_WAIT = 0,
	PSR_1_LINE_TO_WAIT,
	PSR_4_LINES_TO_WAIT,
	PSR_8_LINES_TO_WAIT
1041 1042
};

1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054
struct intel_vbt_data {
	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */

	/* Feature bits */
	unsigned int int_tv_support:1;
	unsigned int lvds_dither:1;
	unsigned int lvds_vbt:1;
	unsigned int int_crt_support:1;
	unsigned int lvds_use_ssc:1;
	unsigned int display_clock_mode:1;
	unsigned int fdi_rx_polarity_inverted:1;
1055
	unsigned int panel_type:4;
1056 1057 1058
	int lvds_ssc_freq;
	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */

1059 1060
	enum drrs_support_type drrs_type;

1061 1062 1063 1064 1065
	struct {
		int rate;
		int lanes;
		int preemphasis;
		int vswing;
1066
		bool low_vswing;
1067 1068 1069 1070 1071
		bool initialized;
		bool support;
		int bpp;
		struct edp_power_seq pps;
	} edp;
1072

R
Rodrigo Vivi 已提交
1073 1074 1075 1076 1077 1078 1079 1080 1081
	struct {
		bool full_link;
		bool require_aux_wakeup;
		int idle_frames;
		enum psr_lines_to_wait lines_to_wait;
		int tp1_wakeup_time;
		int tp2_tp3_wakeup_time;
	} psr;

1082 1083
	struct {
		u16 pwm_freq_hz;
1084
		bool present;
1085
		bool active_low_pwm;
1086
		u8 min_brightness;	/* min_brightness/255 of max */
1087
		u8 controller;		/* brightness controller number */
1088
		enum intel_backlight_type type;
1089 1090
	} backlight;

1091 1092 1093
	/* MIPI DSI */
	struct {
		u16 panel_id;
1094 1095
		struct mipi_config *config;
		struct mipi_pps_data *pps;
1096 1097
		u16 bl_ports;
		u16 cabc_ports;
1098 1099 1100
		u8 seq_version;
		u32 size;
		u8 *data;
1101
		const u8 *sequence[MIPI_SEQ_MAX];
1102
		u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
1103 1104
	} dsi;

1105 1106 1107
	int crt_ddc_pin;

	int child_dev_num;
1108
	struct child_device_config *child_dev;
1109 1110

	struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1111
	struct sdvo_device_mapping sdvo_mappings[2];
1112 1113
};

1114 1115 1116 1117 1118
enum intel_ddb_partitioning {
	INTEL_DDB_PART_1_2,
	INTEL_DDB_PART_5_6, /* IVB+ */
};

1119 1120 1121 1122 1123 1124 1125 1126
struct intel_wm_level {
	bool enable;
	uint32_t pri_val;
	uint32_t spr_val;
	uint32_t cur_val;
	uint32_t fbc_val;
};

1127
struct ilk_wm_values {
1128 1129 1130 1131 1132 1133 1134 1135
	uint32_t wm_pipe[3];
	uint32_t wm_lp[3];
	uint32_t wm_lp_spr[3];
	uint32_t wm_linetime[3];
	bool enable_fbc_wm;
	enum intel_ddb_partitioning partitioning;
};

1136
struct g4x_pipe_wm {
1137
	uint16_t plane[I915_MAX_PLANES];
1138
	uint16_t fbc;
1139
};
1140

1141
struct g4x_sr_wm {
1142
	uint16_t plane;
1143
	uint16_t cursor;
1144
	uint16_t fbc;
1145 1146 1147 1148
};

struct vlv_wm_ddl_values {
	uint8_t plane[I915_MAX_PLANES];
1149
};
1150

1151
struct vlv_wm_values {
1152 1153
	struct g4x_pipe_wm pipe[3];
	struct g4x_sr_wm sr;
1154
	struct vlv_wm_ddl_values ddl[3];
1155 1156
	uint8_t level;
	bool cxsr;
1157 1158
};

1159 1160 1161 1162 1163 1164 1165 1166 1167
struct g4x_wm_values {
	struct g4x_pipe_wm pipe[2];
	struct g4x_sr_wm sr;
	struct g4x_sr_wm hpll;
	bool cxsr;
	bool hpll_en;
	bool fbc_en;
};

1168
struct skl_ddb_entry {
1169
	uint16_t start, end;	/* in number of blocks, 'end' is exclusive */
1170 1171 1172 1173
};

static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
{
1174
	return entry->end - entry->start;
1175 1176
}

1177 1178 1179 1180 1181 1182 1183 1184 1185
static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
				       const struct skl_ddb_entry *e2)
{
	if (e1->start == e2->start && e1->end == e2->end)
		return true;

	return false;
}

1186
struct skl_ddb_allocation {
1187 1188 1189
	/* packed/y */
	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
	struct skl_ddb_entry uv_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1190 1191
};

1192
struct skl_ddb_values {
1193
	unsigned dirty_pipes;
1194
	struct skl_ddb_allocation ddb;
1195 1196 1197
};

struct skl_wm_level {
L
Lyude 已提交
1198 1199 1200
	bool plane_en;
	uint16_t plane_res_b;
	uint8_t plane_res_l;
1201 1202
};

1203 1204 1205 1206
/* Stores plane specific WM parameters */
struct skl_wm_params {
	bool x_tiled, y_tiled;
	bool rc_surface;
1207
	bool is_planar;
1208 1209 1210 1211 1212 1213 1214 1215
	uint32_t width;
	uint8_t cpp;
	uint32_t plane_pixel_rate;
	uint32_t y_min_scanlines;
	uint32_t plane_bytes_per_line;
	uint_fixed_16_16_t plane_blocks_per_line;
	uint_fixed_16_16_t y_tile_minimum;
	uint32_t linetime_us;
1216
	uint32_t dbuf_block_size;
1217 1218
};

1219
/*
1220 1221 1222 1223
 * This struct helps tracking the state needed for runtime PM, which puts the
 * device in PCI D3 state. Notice that when this happens, nothing on the
 * graphics device works, even register access, so we don't get interrupts nor
 * anything else.
1224
 *
1225 1226 1227
 * Every piece of our code that needs to actually touch the hardware needs to
 * either call intel_runtime_pm_get or call intel_display_power_get with the
 * appropriate power domain.
1228
 *
1229 1230
 * Our driver uses the autosuspend delay feature, which means we'll only really
 * suspend if we stay with zero refcount for a certain amount of time. The
1231
 * default value is currently very conservative (see intel_runtime_pm_enable), but
1232
 * it can be changed with the standard runtime PM files from sysfs.
1233 1234 1235 1236 1237
 *
 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
 * goes back to false exactly before we reenable the IRQs. We use this variable
 * to check if someone is trying to enable/disable IRQs while they're supposed
 * to be disabled. This shouldn't happen and we'll print some error messages in
1238
 * case it happens.
1239
 *
1240
 * For more, read the Documentation/power/runtime_pm.txt.
1241
 */
1242
struct i915_runtime_pm {
1243
	atomic_t wakeref_count;
1244
	bool suspended;
1245
	bool irqs_enabled;
1246 1247
};

1248 1249 1250 1251 1252
enum intel_pipe_crc_source {
	INTEL_PIPE_CRC_SOURCE_NONE,
	INTEL_PIPE_CRC_SOURCE_PLANE1,
	INTEL_PIPE_CRC_SOURCE_PLANE2,
	INTEL_PIPE_CRC_SOURCE_PF,
1253
	INTEL_PIPE_CRC_SOURCE_PIPE,
D
Daniel Vetter 已提交
1254 1255 1256 1257 1258
	/* TV/DP on pre-gen5/vlv can't use the pipe source. */
	INTEL_PIPE_CRC_SOURCE_TV,
	INTEL_PIPE_CRC_SOURCE_DP_B,
	INTEL_PIPE_CRC_SOURCE_DP_C,
	INTEL_PIPE_CRC_SOURCE_DP_D,
1259
	INTEL_PIPE_CRC_SOURCE_AUTO,
1260 1261 1262
	INTEL_PIPE_CRC_SOURCE_MAX,
};

1263
struct intel_pipe_crc_entry {
1264
	uint32_t frame;
1265 1266 1267
	uint32_t crc[5];
};

1268
#define INTEL_PIPE_CRC_ENTRIES_NR	128
1269
struct intel_pipe_crc {
1270 1271
	spinlock_t lock;
	bool opened;		/* exclusive access to the result file */
1272
	struct intel_pipe_crc_entry *entries;
1273
	enum intel_pipe_crc_source source;
1274
	int head, tail;
1275
	wait_queue_head_t wq;
T
Tomeu Vizoso 已提交
1276
	int skipped;
1277 1278
};

1279
struct i915_frontbuffer_tracking {
1280
	spinlock_t lock;
1281 1282 1283 1284 1285 1286 1287 1288 1289

	/*
	 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
	 * scheduled flips.
	 */
	unsigned busy_bits;
	unsigned flip_bits;
};

1290
struct i915_wa_reg {
1291
	i915_reg_t addr;
1292 1293 1294 1295 1296
	u32 value;
	/* bitmask representing WA bits */
	u32 mask;
};

1297
#define I915_MAX_WA_REGS 16
1298 1299 1300 1301 1302 1303

struct i915_workarounds {
	struct i915_wa_reg reg[I915_MAX_WA_REGS];
	u32 count;
};

1304 1305
struct i915_virtual_gpu {
	bool active;
1306
	u32 caps;
1307 1308
};

1309 1310 1311 1312 1313 1314 1315
/* used in computing the new watermarks state */
struct intel_wm_config {
	unsigned int num_pipes_active;
	bool sprites_enabled;
	bool sprites_scaled;
};

1316 1317 1318 1319 1320
struct i915_oa_format {
	u32 format;
	int size;
};

1321 1322 1323 1324 1325
struct i915_oa_reg {
	i915_reg_t addr;
	u32 value;
};

1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339
struct i915_oa_config {
	char uuid[UUID_STRING_LEN + 1];
	int id;

	const struct i915_oa_reg *mux_regs;
	u32 mux_regs_len;
	const struct i915_oa_reg *b_counter_regs;
	u32 b_counter_regs_len;
	const struct i915_oa_reg *flex_regs;
	u32 flex_regs_len;

	struct attribute_group sysfs_metric;
	struct attribute *attrs[2];
	struct device_attribute sysfs_metric_id;
1340 1341

	atomic_t ref_count;
1342 1343
};

1344 1345
struct i915_perf_stream;

1346 1347 1348
/**
 * struct i915_perf_stream_ops - the OPs to support a specific stream type
 */
1349
struct i915_perf_stream_ops {
1350 1351 1352 1353
	/**
	 * @enable: Enables the collection of HW samples, either in response to
	 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
	 * without `I915_PERF_FLAG_DISABLED`.
1354 1355 1356
	 */
	void (*enable)(struct i915_perf_stream *stream);

1357 1358 1359 1360
	/**
	 * @disable: Disables the collection of HW samples, either in response
	 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
	 * the stream.
1361 1362 1363
	 */
	void (*disable)(struct i915_perf_stream *stream);

1364 1365
	/**
	 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1366 1367 1368 1369 1370 1371
	 * once there is something ready to read() for the stream
	 */
	void (*poll_wait)(struct i915_perf_stream *stream,
			  struct file *file,
			  poll_table *wait);

1372 1373 1374
	/**
	 * @wait_unlocked: For handling a blocking read, wait until there is
	 * something to ready to read() for the stream. E.g. wait on the same
1375
	 * wait queue that would be passed to poll_wait().
1376 1377 1378
	 */
	int (*wait_unlocked)(struct i915_perf_stream *stream);

1379 1380 1381 1382 1383 1384 1385
	/**
	 * @read: Copy buffered metrics as records to userspace
	 * **buf**: the userspace, destination buffer
	 * **count**: the number of bytes to copy, requested by userspace
	 * **offset**: zero at the start of the read, updated as the read
	 * proceeds, it represents how many bytes have been copied so far and
	 * the buffer offset for copying the next record.
1386
	 *
1387 1388
	 * Copy as many buffered i915 perf samples and records for this stream
	 * to userspace as will fit in the given buffer.
1389
	 *
1390 1391
	 * Only write complete records; returning -%ENOSPC if there isn't room
	 * for a complete record.
1392
	 *
1393 1394 1395
	 * Return any error condition that results in a short read such as
	 * -%ENOSPC or -%EFAULT, even though these may be squashed before
	 * returning to userspace.
1396 1397 1398 1399 1400 1401
	 */
	int (*read)(struct i915_perf_stream *stream,
		    char __user *buf,
		    size_t count,
		    size_t *offset);

1402 1403
	/**
	 * @destroy: Cleanup any stream specific resources.
1404 1405 1406 1407 1408 1409
	 *
	 * The stream will always be disabled before this is called.
	 */
	void (*destroy)(struct i915_perf_stream *stream);
};

1410 1411 1412
/**
 * struct i915_perf_stream - state for a single open stream FD
 */
1413
struct i915_perf_stream {
1414 1415 1416
	/**
	 * @dev_priv: i915 drm device
	 */
1417 1418
	struct drm_i915_private *dev_priv;

1419 1420 1421
	/**
	 * @link: Links the stream into ``&drm_i915_private->streams``
	 */
1422 1423
	struct list_head link;

1424 1425 1426 1427 1428
	/**
	 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
	 * properties given when opening a stream, representing the contents
	 * of a single sample as read() by userspace.
	 */
1429
	u32 sample_flags;
1430 1431 1432 1433 1434 1435

	/**
	 * @sample_size: Considering the configured contents of a sample
	 * combined with the required header size, this is the total size
	 * of a single sample record.
	 */
1436
	int sample_size;
1437

1438 1439 1440 1441
	/**
	 * @ctx: %NULL if measuring system-wide across all contexts or a
	 * specific context that is being monitored.
	 */
1442
	struct i915_gem_context *ctx;
1443 1444 1445 1446 1447 1448

	/**
	 * @enabled: Whether the stream is currently enabled, considering
	 * whether the stream was opened in a disabled state and based
	 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
	 */
1449 1450
	bool enabled;

1451 1452 1453 1454
	/**
	 * @ops: The callbacks providing the implementation of this specific
	 * type of configured stream.
	 */
1455
	const struct i915_perf_stream_ops *ops;
1456 1457 1458 1459 1460

	/**
	 * @oa_config: The OA configuration used by the stream.
	 */
	struct i915_oa_config *oa_config;
1461 1462
};

1463 1464 1465
/**
 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
 */
1466
struct i915_oa_ops {
1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485
	/**
	 * @is_valid_b_counter_reg: Validates register's address for
	 * programming boolean counters for a particular platform.
	 */
	bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv,
				       u32 addr);

	/**
	 * @is_valid_mux_reg: Validates register's address for programming mux
	 * for a particular platform.
	 */
	bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr);

	/**
	 * @is_valid_flex_reg: Validates register's address for programming
	 * flex EU filtering for a particular platform.
	 */
	bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr);

1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500
	/**
	 * @init_oa_buffer: Resets the head and tail pointers of the
	 * circular buffer for periodic OA reports.
	 *
	 * Called when first opening a stream for OA metrics, but also may be
	 * called in response to an OA buffer overflow or other error
	 * condition.
	 *
	 * Note it may be necessary to clear the full OA buffer here as part of
	 * maintaining the invariable that new reports must be written to
	 * zeroed memory for us to be able to reliable detect if an expected
	 * report has not yet landed in memory.  (At least on Haswell the OA
	 * buffer tail pointer is not synchronized with reports being visible
	 * to the CPU)
	 */
1501
	void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
1502

1503 1504 1505 1506
	/**
	 * @enable_metric_set: Selects and applies any MUX configuration to set
	 * up the Boolean and Custom (B/C) counters that are part of the
	 * counter reports being sampled. May apply system constraints such as
1507 1508
	 * disabling EU clock gating as required.
	 */
1509 1510
	int (*enable_metric_set)(struct drm_i915_private *dev_priv,
				 const struct i915_oa_config *oa_config);
1511 1512 1513 1514 1515

	/**
	 * @disable_metric_set: Remove system constraints associated with using
	 * the OA unit.
	 */
1516
	void (*disable_metric_set)(struct drm_i915_private *dev_priv);
1517 1518 1519 1520

	/**
	 * @oa_enable: Enable periodic sampling
	 */
1521
	void (*oa_enable)(struct drm_i915_private *dev_priv);
1522 1523 1524 1525

	/**
	 * @oa_disable: Disable periodic sampling
	 */
1526
	void (*oa_disable)(struct drm_i915_private *dev_priv);
1527 1528 1529 1530 1531

	/**
	 * @read: Copy data from the circular OA buffer into a given userspace
	 * buffer.
	 */
1532 1533 1534 1535
	int (*read)(struct i915_perf_stream *stream,
		    char __user *buf,
		    size_t count,
		    size_t *offset);
1536 1537

	/**
1538
	 * @oa_hw_tail_read: read the OA tail pointer register
1539
	 *
1540 1541 1542
	 * In particular this enables us to share all the fiddly code for
	 * handling the OA unit tail pointer race that affects multiple
	 * generations.
1543
	 */
1544
	u32 (*oa_hw_tail_read)(struct drm_i915_private *dev_priv);
1545 1546
};

1547
struct intel_cdclk_state {
1548
	unsigned int cdclk, vco, ref, bypass;
1549
	u8 voltage_level;
1550 1551
};

1552
struct drm_i915_private {
1553 1554
	struct drm_device drm;

1555
	struct kmem_cache *objects;
1556
	struct kmem_cache *vmas;
1557
	struct kmem_cache *luts;
1558
	struct kmem_cache *requests;
1559
	struct kmem_cache *dependencies;
1560
	struct kmem_cache *priorities;
1561

1562
	const struct intel_device_info info;
1563
	struct intel_driver_caps caps;
1564

1565 1566 1567
	/**
	 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
	 * end of stolen which we can optionally use to create GEM objects
1568
	 * backed by stolen memory. Note that stolen_usable_size tells us
1569 1570 1571 1572
	 * exactly how much of this we are actually allowed to use, given that
	 * some portion of it is in fact reserved for use by hardware functions.
	 */
	struct resource dsm;
1573 1574 1575 1576
	/**
	 * Reseved portion of Data Stolen Memory
	 */
	struct resource dsm_reserved;
1577

1578 1579 1580 1581 1582 1583 1584 1585 1586
	/*
	 * Stolen memory is segmented in hardware with different portions
	 * offlimits to certain functions.
	 *
	 * The drm_mm is initialised to the total accessible range, as found
	 * from the PCI config. On Broadwell+, this is further restricted to
	 * avoid the first page! The upper end of stolen memory is reserved for
	 * hardware functions and similarly removed from the accessible range.
	 */
1587
	resource_size_t stolen_usable_size;	/* Total size minus reserved ranges */
1588

1589 1590
	void __iomem *regs;

1591
	struct intel_uncore uncore;
1592

1593 1594
	struct i915_virtual_gpu vgpu;

1595
	struct intel_gvt *gvt;
1596

1597 1598
	struct intel_wopcm wopcm;

1599
	struct intel_huc huc;
1600 1601
	struct intel_guc guc;

1602 1603
	struct intel_csr csr;

1604
	struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1605

1606 1607 1608 1609 1610 1611 1612 1613 1614
	/** gmbus_mutex protects against concurrent usage of the single hw gmbus
	 * controller on different i2c buses. */
	struct mutex gmbus_mutex;

	/**
	 * Base address of the gmbus and gpio block.
	 */
	uint32_t gpio_mmio_base;

1615 1616 1617
	/* MMIO base address for MIPI regs */
	uint32_t mipi_mmio_base;

1618 1619
	uint32_t psr_mmio_base;

1620 1621
	uint32_t pps_mmio_base;

1622 1623
	wait_queue_head_t gmbus_wait_queue;

1624
	struct pci_dev *bridge_dev;
1625
	struct intel_engine_cs *engine[I915_NUM_ENGINES];
1626 1627 1628 1629
	/* Context used internally to idle the GPU and setup initial state */
	struct i915_gem_context *kernel_context;
	/* Context only to be used for injecting preemption commands */
	struct i915_gem_context *preempt_context;
1630 1631
	struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1]
					    [MAX_ENGINE_INSTANCE + 1];
1632

1633
	struct drm_dma_handle *status_page_dmah;
1634 1635 1636 1637 1638
	struct resource mch_res;

	/* protects the irq masks */
	spinlock_t irq_lock;

1639 1640
	bool display_irqs_enabled;

1641 1642 1643
	/* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
	struct pm_qos_request pm_qos;

V
Ville Syrjälä 已提交
1644 1645
	/* Sideband mailbox protection */
	struct mutex sb_lock;
1646 1647

	/** Cached value of IMR to avoid reads in updating the bitfield */
1648 1649 1650 1651
	union {
		u32 irq_mask;
		u32 de_irq_mask[I915_MAX_PIPES];
	};
1652
	u32 gt_irq_mask;
1653 1654
	u32 pm_imr;
	u32 pm_ier;
1655
	u32 pm_rps_events;
1656
	u32 pm_guc_events;
1657
	u32 pipestat_irq_mask[I915_MAX_PIPES];
1658

1659
	struct i915_hotplug hotplug;
1660
	struct intel_fbc fbc;
1661
	struct i915_drrs drrs;
1662
	struct intel_opregion opregion;
1663
	struct intel_vbt_data vbt;
1664

1665 1666
	bool preserve_bios_swizzle;

1667 1668 1669
	/* overlay */
	struct intel_overlay *overlay;

1670
	/* backlight registers and fields in struct intel_panel */
1671
	struct mutex backlight_lock;
1672

1673 1674 1675
	/* LVDS info */
	bool no_aux_handshake;

V
Ville Syrjälä 已提交
1676 1677 1678
	/* protects panel power sequencer state */
	struct mutex pps_mutex;

1679 1680 1681 1682
	struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
	int num_fence_regs; /* 8 on pre-965, 16 otherwise */

	unsigned int fsb_freq, mem_freq, is_ddr3;
1683
	unsigned int skl_preferred_vco_freq;
1684
	unsigned int max_cdclk_freq;
1685

M
Mika Kahola 已提交
1686
	unsigned int max_dotclk_freq;
1687
	unsigned int rawclk_freq;
1688
	unsigned int hpll_freq;
1689
	unsigned int fdi_pll_freq;
1690
	unsigned int czclk_freq;
1691

1692
	struct {
1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706
		/*
		 * The current logical cdclk state.
		 * See intel_atomic_state.cdclk.logical
		 *
		 * For reading holding any crtc lock is sufficient,
		 * for writing must hold all of them.
		 */
		struct intel_cdclk_state logical;
		/*
		 * The current actual cdclk state.
		 * See intel_atomic_state.cdclk.actual
		 */
		struct intel_cdclk_state actual;
		/* The current hardware cdclk state */
1707 1708
		struct intel_cdclk_state hw;
	} cdclk;
1709

1710 1711 1712 1713 1714 1715 1716
	/**
	 * wq - Driver workqueue for GEM.
	 *
	 * NOTE: Work items scheduled here are not allowed to grab any modeset
	 * locks, for otherwise the flushing done in the pageflip code will
	 * result in deadlocks.
	 */
1717 1718
	struct workqueue_struct *wq;

1719 1720 1721
	/* ordered wq for modesets */
	struct workqueue_struct *modeset_wq;

1722 1723 1724 1725 1726
	/* Display functions */
	struct drm_i915_display_funcs display;

	/* PCH chipset type */
	enum intel_pch pch_type;
1727
	unsigned short pch_id;
1728 1729 1730

	unsigned long quirks;

1731 1732
	enum modeset_restore modeset_restore;
	struct mutex modeset_restore_lock;
1733
	struct drm_atomic_state *modeset_restore_state;
1734
	struct drm_modeset_acquire_ctx reset_ctx;
1735

1736
	struct list_head vm_list; /* Global list of all address spaces */
1737
	struct i915_ggtt ggtt; /* VM representing the global address space */
B
Ben Widawsky 已提交
1738

1739
	struct i915_gem_mm mm;
1740 1741
	DECLARE_HASHTABLE(mm_structs, 7);
	struct mutex mm_lock;
1742

1743 1744
	struct intel_ppat ppat;

1745 1746
	/* Kernel Modesetting */

1747 1748
	struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
	struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1749

1750 1751 1752 1753
#ifdef CONFIG_DEBUG_FS
	struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
#endif

1754
	/* dpll and cdclk state is protected by connection_mutex */
D
Daniel Vetter 已提交
1755 1756
	int num_shared_dpll;
	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1757
	const struct intel_dpll_mgr *dpll_mgr;
1758

1759 1760 1761 1762 1763 1764 1765
	/*
	 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
	 * Must be global rather than per dpll, because on some platforms
	 * plls share registers.
	 */
	struct mutex dpll_lock;

1766
	unsigned int active_crtcs;
1767 1768
	/* minimum acceptable cdclk for each pipe */
	int min_cdclk[I915_MAX_PIPES];
1769 1770
	/* minimum acceptable voltage level for each pipe */
	u8 min_voltage_level[I915_MAX_PIPES];
1771

1772
	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1773

1774
	struct i915_workarounds workarounds;
1775

1776 1777
	struct i915_frontbuffer_tracking fb_tracking;

1778 1779 1780 1781 1782
	struct intel_atomic_helper {
		struct llist_head free_list;
		struct work_struct free_work;
	} atomic_helper;

1783
	u16 orig_clock;
1784

1785
	bool mchbar_need_disable;
1786

1787 1788
	struct intel_l3_parity l3_parity;

B
Ben Widawsky 已提交
1789
	/* Cannot be determined by PCIID. You must always read a register. */
1790
	u32 edram_cap;
B
Ben Widawsky 已提交
1791

1792 1793 1794 1795 1796 1797 1798 1799
	/*
	 * Protects RPS/RC6 register access and PCU communication.
	 * Must be taken after struct_mutex if nested. Note that
	 * this lock may be held for long periods of time when
	 * talking to hw - so only take it when talking to hw!
	 */
	struct mutex pcu_lock;

1800 1801
	/* gen6+ GT PM state */
	struct intel_gen6_power_mgmt gt_pm;
1802

1803 1804
	/* ilk-only ips/rps state. Everything in here is protected by the global
	 * mchdev_lock in intel_pm.c */
1805
	struct intel_ilk_power_mgmt ips;
1806

1807
	struct i915_power_domains power_domains;
1808

R
Rodrigo Vivi 已提交
1809
	struct i915_psr psr;
1810

1811
	struct i915_gpu_error gpu_error;
1812

1813 1814
	struct drm_i915_gem_object *vlv_pctx;

1815 1816
	/* list of fbdev register on this device */
	struct intel_fbdev *fbdev;
1817
	struct work_struct fbdev_suspend_work;
1818 1819

	struct drm_property *broadcast_rgb_property;
1820
	struct drm_property *force_audio_property;
1821

I
Imre Deak 已提交
1822
	/* hda/i915 audio component */
1823
	struct i915_audio_component *audio_component;
I
Imre Deak 已提交
1824
	bool audio_component_registered;
1825 1826 1827 1828 1829
	/**
	 * av_mutex - mutex for audio/video sync
	 *
	 */
	struct mutex av_mutex;
I
Imre Deak 已提交
1830

1831 1832
	struct {
		struct list_head list;
1833 1834
		struct llist_head free_list;
		struct work_struct free_work;
1835 1836 1837 1838 1839 1840 1841

		/* The hw wants to have a stable context identifier for the
		 * lifetime of the context (for OA, PASID, faults, etc).
		 * This is limited in execlists to 21 bits.
		 */
		struct ida hw_ida;
#define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1842
#define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
1843
	} contexts;
1844

1845
	u32 fdi_rx_config;
1846

1847
	/* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1848
	u32 chv_phy_control;
1849 1850 1851 1852 1853 1854
	/*
	 * Shadows for CHV DPLL_MD regs to keep the state
	 * checker somewhat working in the presence hardware
	 * crappiness (can't read out DPLL_MD for pipes B & C).
	 */
	u32 chv_dpll_md[I915_MAX_PIPES];
1855
	u32 bxt_phy_grc;
1856

1857
	u32 suspend_count;
1858
	bool power_domains_suspended;
1859
	struct i915_suspend_saved_registers regfile;
1860
	struct vlv_s0ix_state vlv_s0ix_state;
1861

1862
	enum {
1863 1864 1865 1866 1867
		I915_SAGV_UNKNOWN = 0,
		I915_SAGV_DISABLED,
		I915_SAGV_ENABLED,
		I915_SAGV_NOT_CONTROLLED
	} sagv_status;
1868

1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880
	struct {
		/*
		 * Raw watermark latency values:
		 * in 0.1us units for WM0,
		 * in 0.5us units for WM1+.
		 */
		/* primary */
		uint16_t pri_latency[5];
		/* sprite */
		uint16_t spr_latency[5];
		/* cursor */
		uint16_t cur_latency[5];
1881 1882 1883 1884 1885 1886
		/*
		 * Raw watermark memory latency values
		 * for SKL for all 8 levels
		 * in 1us units.
		 */
		uint16_t skl_latency[8];
1887 1888

		/* current hardware state */
1889 1890
		union {
			struct ilk_wm_values hw;
1891
			struct skl_ddb_values skl_hw;
1892
			struct vlv_wm_values vlv;
1893
			struct g4x_wm_values g4x;
1894
		};
1895 1896

		uint8_t max_level;
1897 1898 1899 1900 1901 1902 1903

		/*
		 * Should be held around atomic WM register writing; also
		 * protects * intel_crtc->wm.active and
		 * cstate->wm.need_postvbl_update.
		 */
		struct mutex wm_mutex;
1904 1905 1906 1907 1908 1909 1910

		/*
		 * Set during HW readout of watermarks/DDB.  Some platforms
		 * need to know when we're still using BIOS-provided values
		 * (which we don't fully trust).
		 */
		bool distrust_bios_wm;
1911 1912
	} wm;

1913
	struct i915_runtime_pm runtime_pm;
1914

1915 1916
	struct {
		bool initialized;
1917

1918
		struct kobject *metrics_kobj;
1919
		struct ctl_table_header *sysctl_header;
1920

1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936
		/*
		 * Lock associated with adding/modifying/removing OA configs
		 * in dev_priv->perf.metrics_idr.
		 */
		struct mutex metrics_lock;

		/*
		 * List of dynamic configurations, you need to hold
		 * dev_priv->perf.metrics_lock to access it.
		 */
		struct idr metrics_idr;

		/*
		 * Lock associated with anything below within this structure
		 * except exclusive_stream.
		 */
1937 1938
		struct mutex lock;
		struct list_head streams;
1939 1940

		struct {
1941 1942 1943 1944 1945 1946
			/*
			 * The stream currently using the OA unit. If accessed
			 * outside a syscall associated to its file
			 * descriptor, you need to hold
			 * dev_priv->drm.struct_mutex.
			 */
1947 1948 1949 1950 1951 1952 1953 1954
			struct i915_perf_stream *exclusive_stream;

			u32 specific_ctx_id;

			struct hrtimer poll_check_timer;
			wait_queue_head_t poll_wq;
			bool pollin;

1955 1956 1957 1958 1959 1960
			/**
			 * For rate limiting any notifications of spurious
			 * invalid OA reports
			 */
			struct ratelimit_state spurious_report_rs;

1961 1962 1963
			bool periodic;
			int period_exponent;

1964
			struct i915_oa_config test_config;
1965 1966 1967 1968

			struct {
				struct i915_vma *vma;
				u8 *vaddr;
1969
				u32 last_ctx_id;
1970 1971
				int format;
				int format_size;
1972

1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025
				/**
				 * Locks reads and writes to all head/tail state
				 *
				 * Consider: the head and tail pointer state
				 * needs to be read consistently from a hrtimer
				 * callback (atomic context) and read() fop
				 * (user context) with tail pointer updates
				 * happening in atomic context and head updates
				 * in user context and the (unlikely)
				 * possibility of read() errors needing to
				 * reset all head/tail state.
				 *
				 * Note: Contention or performance aren't
				 * currently a significant concern here
				 * considering the relatively low frequency of
				 * hrtimer callbacks (5ms period) and that
				 * reads typically only happen in response to a
				 * hrtimer event and likely complete before the
				 * next callback.
				 *
				 * Note: This lock is not held *while* reading
				 * and copying data to userspace so the value
				 * of head observed in htrimer callbacks won't
				 * represent any partial consumption of data.
				 */
				spinlock_t ptr_lock;

				/**
				 * One 'aging' tail pointer and one 'aged'
				 * tail pointer ready to used for reading.
				 *
				 * Initial values of 0xffffffff are invalid
				 * and imply that an update is required
				 * (and should be ignored by an attempted
				 * read)
				 */
				struct {
					u32 offset;
				} tails[2];

				/**
				 * Index for the aged tail ready to read()
				 * data up to.
				 */
				unsigned int aged_tail_idx;

				/**
				 * A monotonic timestamp for when the current
				 * aging tail pointer was read; used to
				 * determine when it is old enough to trust.
				 */
				u64 aging_timestamp;

2026 2027 2028 2029 2030 2031 2032 2033 2034 2035
				/**
				 * Although we can always read back the head
				 * pointer register, we prefer to avoid
				 * trusting the HW state, just to avoid any
				 * risk that some hardware condition could
				 * somehow bump the head pointer unpredictably
				 * and cause us to forward the wrong OA buffer
				 * data to userspace.
				 */
				u32 head;
2036 2037 2038
			} oa_buffer;

			u32 gen7_latched_oastatus1;
2039 2040 2041 2042 2043 2044 2045 2046 2047
			u32 ctx_oactxctrl_offset;
			u32 ctx_flexeu0_offset;

			/**
			 * The RPT_ID/reason field for Gen8+ includes a bit
			 * to determine if the CTX ID in the report is valid
			 * but the specific bit differs between Gen 8 and 9
			 */
			u32 gen8_valid_ctx_bit;
2048 2049 2050

			struct i915_oa_ops ops;
			const struct i915_oa_format *oa_formats;
2051
		} oa;
2052 2053
	} perf;

2054 2055
	/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
	struct {
2056
		void (*resume)(struct drm_i915_private *);
2057
		void (*cleanup_engine)(struct intel_engine_cs *engine);
2058

2059 2060
		struct list_head timelines;
		struct i915_gem_timeline global_timeline;
2061
		u32 active_requests;
2062

2063 2064 2065 2066 2067 2068 2069 2070 2071
		/**
		 * Is the GPU currently considered idle, or busy executing
		 * userspace requests? Whilst idle, we allow runtime power
		 * management to power down the hardware and display clocks.
		 * In order to reduce the effect on performance, there
		 * is a slight delay before we do so.
		 */
		bool awake;

2072 2073 2074 2075 2076 2077
		/**
		 * The number of times we have woken up.
		 */
		unsigned int epoch;
#define I915_EPOCH_INVALID 0

2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094
		/**
		 * We leave the user IRQ off as much as possible,
		 * but this means that requests will finish and never
		 * be retired once the system goes idle. Set a timer to
		 * fire periodically while the ring is running. When it
		 * fires, go retire requests.
		 */
		struct delayed_work retire_work;

		/**
		 * When we detect an idle GPU, we want to turn on
		 * powersaving features. So once we see that there
		 * are no more requests outstanding and no more
		 * arrive within a small period of time, we fire
		 * off the idle_work.
		 */
		struct delayed_work idle_work;
2095 2096

		ktime_t last_init_time;
2097 2098
	} gt;

2099 2100 2101
	/* perform PHY state sanity checks? */
	bool chv_phy_assert[2];

M
Mahesh Kumar 已提交
2102 2103
	bool ipc_enabled;

2104 2105
	/* Used to save the pipe-to-encoder mapping for audio */
	struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2106

2107 2108 2109 2110 2111 2112
	/* necessary resource sharing with HDMI LPE audio driver. */
	struct {
		struct platform_device *platdev;
		int	irq;
	} lpe_audio;

2113 2114
	struct i915_pmu pmu;

2115 2116 2117 2118
	/*
	 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
	 * will be rejected. Instead look for a better place.
	 */
2119
};
L
Linus Torvalds 已提交
2120

2121 2122
static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
{
2123
	return container_of(dev, struct drm_i915_private, drm);
2124 2125
}

2126
static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
I
Imre Deak 已提交
2127
{
2128
	return to_i915(dev_get_drvdata(kdev));
I
Imre Deak 已提交
2129 2130
}

2131 2132 2133 2134 2135
static inline struct drm_i915_private *wopcm_to_i915(struct intel_wopcm *wopcm)
{
	return container_of(wopcm, struct drm_i915_private, wopcm);
}

2136 2137 2138 2139 2140
static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
{
	return container_of(guc, struct drm_i915_private, guc);
}

A
Arkadiusz Hiler 已提交
2141 2142 2143 2144 2145
static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
{
	return container_of(huc, struct drm_i915_private, huc);
}

2146
/* Simple iterator over all initialised engines */
2147 2148 2149 2150 2151
#define for_each_engine(engine__, dev_priv__, id__) \
	for ((id__) = 0; \
	     (id__) < I915_NUM_ENGINES; \
	     (id__)++) \
		for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2152 2153

/* Iterator over subset of engines selected by mask */
2154
#define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2155 2156 2157 2158
	for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->ring_mask; \
	     (tmp__) ? \
	     ((engine__) = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : \
	     0;)
2159

2160 2161 2162 2163 2164 2165 2166
enum hdmi_force_audio {
	HDMI_AUDIO_OFF_DVI = -2,	/* no aux data for HDMI-DVI converter */
	HDMI_AUDIO_OFF,			/* force turn off HDMI audio */
	HDMI_AUDIO_AUTO,		/* trust EDID */
	HDMI_AUDIO_ON,			/* force turn on HDMI audio */
};

2167
#define I915_GTT_OFFSET_NONE ((u32)-1)
2168

2169 2170
/*
 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2171
 * considered to be the frontbuffer for the given plane interface-wise. This
2172 2173 2174 2175 2176
 * doesn't mean that the hw necessarily already scans it out, but that any
 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
 *
 * We have one bit per pipe and per scanout plane type.
 */
2177
#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2178 2179 2180 2181 2182
#define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
	BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
	BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
	BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
})
2183
#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2184
	BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2185
#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2186 2187
	GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
		INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2188

2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214
/*
 * Optimised SGL iterator for GEM objects
 */
static __always_inline struct sgt_iter {
	struct scatterlist *sgp;
	union {
		unsigned long pfn;
		dma_addr_t dma;
	};
	unsigned int curr;
	unsigned int max;
} __sgt_iter(struct scatterlist *sgl, bool dma) {
	struct sgt_iter s = { .sgp = sgl };

	if (s.sgp) {
		s.max = s.curr = s.sgp->offset;
		s.max += s.sgp->length;
		if (dma)
			s.dma = sg_dma_address(s.sgp);
		else
			s.pfn = page_to_pfn(sg_page(s.sgp));
	}

	return s;
}

2215 2216 2217 2218 2219 2220 2221 2222
static inline struct scatterlist *____sg_next(struct scatterlist *sg)
{
	++sg;
	if (unlikely(sg_is_chain(sg)))
		sg = sg_chain_ptr(sg);
	return sg;
}

2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236
/**
 * __sg_next - return the next scatterlist entry in a list
 * @sg:		The current sg entry
 *
 * Description:
 *   If the entry is the last, return NULL; otherwise, step to the next
 *   element in the array (@sg@+1). If that's a chain pointer, follow it;
 *   otherwise just return the pointer to the current element.
 **/
static inline struct scatterlist *__sg_next(struct scatterlist *sg)
{
#ifdef CONFIG_DEBUG_SG
	BUG_ON(sg->sg_magic != SG_MAGIC);
#endif
2237
	return sg_is_last(sg) ? NULL : ____sg_next(sg);
2238 2239
}

2240 2241 2242 2243 2244 2245 2246 2247 2248
/**
 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
 * @__dmap:	DMA address (output)
 * @__iter:	'struct sgt_iter' (iterator state, internal)
 * @__sgt:	sg_table to iterate over (input)
 */
#define for_each_sgt_dma(__dmap, __iter, __sgt)				\
	for ((__iter) = __sgt_iter((__sgt)->sgl, true);			\
	     ((__dmap) = (__iter).dma + (__iter).curr);			\
2249 2250
	     (((__iter).curr += PAGE_SIZE) >= (__iter).max) ?		\
	     (__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0)
2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261

/**
 * for_each_sgt_page - iterate over the pages of the given sg_table
 * @__pp:	page pointer (output)
 * @__iter:	'struct sgt_iter' (iterator state, internal)
 * @__sgt:	sg_table to iterate over (input)
 */
#define for_each_sgt_page(__pp, __iter, __sgt)				\
	for ((__iter) = __sgt_iter((__sgt)->sgl, false);		\
	     ((__pp) = (__iter).pfn == 0 ? NULL :			\
	      pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2262 2263
	     (((__iter).curr += PAGE_SIZE) >= (__iter).max) ?		\
	     (__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0 : 0)
2264

2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279
static inline unsigned int i915_sg_page_sizes(struct scatterlist *sg)
{
	unsigned int page_sizes;

	page_sizes = 0;
	while (sg) {
		GEM_BUG_ON(sg->offset);
		GEM_BUG_ON(!IS_ALIGNED(sg->length, PAGE_SIZE));
		page_sizes |= sg->length;
		sg = __sg_next(sg);
	}

	return page_sizes;
}

2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294
static inline unsigned int i915_sg_segment_size(void)
{
	unsigned int size = swiotlb_max_segment();

	if (size == 0)
		return SCATTERLIST_MAX_SEGMENT;

	size = rounddown(size, PAGE_SIZE);
	/* swiotlb_max_segment_size can return 1 byte when it means one page. */
	if (size < PAGE_SIZE)
		size = PAGE_SIZE;

	return size;
}

2295 2296 2297 2298 2299 2300 2301
static inline const struct intel_device_info *
intel_info(const struct drm_i915_private *dev_priv)
{
	return &dev_priv->info;
}

#define INTEL_INFO(dev_priv)	intel_info((dev_priv))
2302

2303
#define INTEL_GEN(dev_priv)	((dev_priv)->info.gen)
2304
#define INTEL_DEVID(dev_priv)	((dev_priv)->info.device_id)
2305

2306
#define REVID_FOREVER		0xff
2307
#define INTEL_REVID(dev_priv)	((dev_priv)->drm.pdev->revision)
2308 2309

#define GEN_FOREVER (0)
2310 2311 2312 2313 2314 2315 2316 2317

#define INTEL_GEN_MASK(s, e) ( \
	BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
	BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
	GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \
		(s) != GEN_FOREVER ? (s) - 1 : 0) \
)

2318 2319 2320 2321 2322
/*
 * Returns true if Gen is in inclusive range [Start, End].
 *
 * Use GEN_FOREVER for unbound start and or end.
 */
2323 2324
#define IS_GEN(dev_priv, s, e) \
	(!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
2325

2326 2327 2328 2329 2330 2331 2332 2333
/*
 * Return true if revision is in range [since,until] inclusive.
 *
 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
 */
#define IS_REVID(p, since, until) \
	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))

2334
#define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
T
Tvrtko Ursulin 已提交
2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347

#define IS_I830(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I830)
#define IS_I845G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I845G)
#define IS_I85X(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I85X)
#define IS_I865G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I865G)
#define IS_I915G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915G)
#define IS_I915GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915GM)
#define IS_I945G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I945G)
#define IS_I945GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I945GM)
#define IS_I965G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I965G)
#define IS_I965GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I965GM)
#define IS_G45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G45)
#define IS_GM45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GM45)
2348
#define IS_G4X(dev_priv)	(IS_G45(dev_priv) || IS_GM45(dev_priv))
2349 2350
#define IS_PINEVIEW_G(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa001)
#define IS_PINEVIEW_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa011)
T
Tvrtko Ursulin 已提交
2351 2352
#define IS_PINEVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
#define IS_G33(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G33)
2353
#define IS_IRONLAKE_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0046)
T
Tvrtko Ursulin 已提交
2354
#define IS_IVYBRIDGE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
2355 2356
#define IS_IVB_GT1(dev_priv)	(IS_IVYBRIDGE(dev_priv) && \
				 (dev_priv)->info.gt == 1)
T
Tvrtko Ursulin 已提交
2357 2358 2359 2360 2361 2362 2363 2364 2365 2366
#define IS_VALLEYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
#define IS_CHERRYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
#define IS_HASWELL(dev_priv)	IS_PLATFORM(dev_priv, INTEL_HASWELL)
#define IS_BROADWELL(dev_priv)	IS_PLATFORM(dev_priv, INTEL_BROADWELL)
#define IS_SKYLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
#define IS_BROXTON(dev_priv)	IS_PLATFORM(dev_priv, INTEL_BROXTON)
#define IS_KABYLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
#define IS_GEMINILAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
#define IS_COFFEELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
#define IS_CANNONLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
2367
#define IS_ICELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ICELAKE)
2368
#define IS_MOBILE(dev_priv)	((dev_priv)->info.is_mobile)
2369 2370 2371 2372 2373 2374
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv)	(IS_BROADWELL(dev_priv) && \
				 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 ||	\
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xb ||	\
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
V
Ville Syrjälä 已提交
2375
/* ULX machines are also considered ULT. */
2376 2377 2378
#define IS_BDW_ULX(dev_priv)	(IS_BROADWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
#define IS_BDW_GT3(dev_priv)	(IS_BROADWELL(dev_priv) && \
2379
				 (dev_priv)->info.gt == 3)
2380 2381 2382
#define IS_HSW_ULT(dev_priv)	(IS_HASWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
#define IS_HSW_GT3(dev_priv)	(IS_HASWELL(dev_priv) && \
2383
				 (dev_priv)->info.gt == 3)
2384
/* ULX machines are also considered ULT. */
2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402
#define IS_HSW_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0A0E || \
				 INTEL_DEVID(dev_priv) == 0x0A1E)
#define IS_SKL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x1906 || \
				 INTEL_DEVID(dev_priv) == 0x1913 || \
				 INTEL_DEVID(dev_priv) == 0x1916 || \
				 INTEL_DEVID(dev_priv) == 0x1921 || \
				 INTEL_DEVID(dev_priv) == 0x1926)
#define IS_SKL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x190E || \
				 INTEL_DEVID(dev_priv) == 0x1915 || \
				 INTEL_DEVID(dev_priv) == 0x191E)
#define IS_KBL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x5906 || \
				 INTEL_DEVID(dev_priv) == 0x5913 || \
				 INTEL_DEVID(dev_priv) == 0x5916 || \
				 INTEL_DEVID(dev_priv) == 0x5921 || \
				 INTEL_DEVID(dev_priv) == 0x5926)
#define IS_KBL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x590E || \
				 INTEL_DEVID(dev_priv) == 0x5915 || \
				 INTEL_DEVID(dev_priv) == 0x591E)
2403
#define IS_SKL_GT2(dev_priv)	(IS_SKYLAKE(dev_priv) && \
2404
				 (dev_priv)->info.gt == 2)
2405
#define IS_SKL_GT3(dev_priv)	(IS_SKYLAKE(dev_priv) && \
2406
				 (dev_priv)->info.gt == 3)
2407
#define IS_SKL_GT4(dev_priv)	(IS_SKYLAKE(dev_priv) && \
2408
				 (dev_priv)->info.gt == 4)
2409
#define IS_KBL_GT2(dev_priv)	(IS_KABYLAKE(dev_priv) && \
2410
				 (dev_priv)->info.gt == 2)
2411
#define IS_KBL_GT3(dev_priv)	(IS_KABYLAKE(dev_priv) && \
2412
				 (dev_priv)->info.gt == 3)
2413 2414
#define IS_CFL_ULT(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
2415 2416
#define IS_CFL_GT2(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
				 (dev_priv)->info.gt == 2)
2417 2418
#define IS_CFL_GT3(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
				 (dev_priv)->info.gt == 3)
2419 2420
#define IS_CNL_WITH_PORT_F(dev_priv)   (IS_CANNONLAKE(dev_priv) && \
					(INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
2421

2422
#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2423

2424 2425 2426 2427 2428 2429
#define SKL_REVID_A0		0x0
#define SKL_REVID_B0		0x1
#define SKL_REVID_C0		0x2
#define SKL_REVID_D0		0x3
#define SKL_REVID_E0		0x4
#define SKL_REVID_F0		0x5
2430 2431
#define SKL_REVID_G0		0x6
#define SKL_REVID_H0		0x7
2432

2433 2434
#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))

2435
#define BXT_REVID_A0		0x0
2436
#define BXT_REVID_A1		0x1
2437
#define BXT_REVID_B0		0x3
2438
#define BXT_REVID_B_LAST	0x8
2439
#define BXT_REVID_C0		0x9
N
Nick Hoath 已提交
2440

2441 2442
#define IS_BXT_REVID(dev_priv, since, until) \
	(IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2443

M
Mika Kuoppala 已提交
2444 2445
#define KBL_REVID_A0		0x0
#define KBL_REVID_B0		0x1
2446 2447 2448
#define KBL_REVID_C0		0x2
#define KBL_REVID_D0		0x3
#define KBL_REVID_E0		0x4
M
Mika Kuoppala 已提交
2449

2450 2451
#define IS_KBL_REVID(dev_priv, since, until) \
	(IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
M
Mika Kuoppala 已提交
2452

2453 2454 2455 2456 2457 2458
#define GLK_REVID_A0		0x0
#define GLK_REVID_A1		0x1

#define IS_GLK_REVID(dev_priv, since, until) \
	(IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))

2459 2460
#define CNL_REVID_A0		0x0
#define CNL_REVID_B0		0x1
R
Rodrigo Vivi 已提交
2461
#define CNL_REVID_C0		0x2
2462 2463 2464 2465

#define IS_CNL_REVID(p, since, until) \
	(IS_CANNONLAKE(p) && IS_REVID(p, since, until))

2466 2467 2468 2469 2470 2471
/*
 * The genX designation typically refers to the render engine, so render
 * capability related checks should use IS_GEN, while display and other checks
 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
 * chips, etc.).
 */
2472 2473 2474 2475 2476 2477 2478 2479
#define IS_GEN2(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(1)))
#define IS_GEN3(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(2)))
#define IS_GEN4(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(3)))
#define IS_GEN5(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(4)))
#define IS_GEN6(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(5)))
#define IS_GEN7(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(6)))
#define IS_GEN8(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(7)))
#define IS_GEN9(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(8)))
2480
#define IS_GEN10(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(9)))
2481
#define IS_GEN11(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(10)))
2482

2483
#define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
2484 2485
#define IS_GEN9_LP(dev_priv)	(IS_GEN9(dev_priv) && IS_LP(dev_priv))
#define IS_GEN9_BC(dev_priv)	(IS_GEN9(dev_priv) && !IS_LP(dev_priv))
2486

2487 2488 2489 2490 2491 2492
#define ENGINE_MASK(id)	BIT(id)
#define RENDER_RING	ENGINE_MASK(RCS)
#define BSD_RING	ENGINE_MASK(VCS)
#define BLT_RING	ENGINE_MASK(BCS)
#define VEBOX_RING	ENGINE_MASK(VECS)
#define BSD2_RING	ENGINE_MASK(VCS2)
2493 2494 2495
#define BSD3_RING	ENGINE_MASK(VCS3)
#define BSD4_RING	ENGINE_MASK(VCS4)
#define VEBOX2_RING	ENGINE_MASK(VECS2)
2496 2497 2498
#define ALL_ENGINES	(~0)

#define HAS_ENGINE(dev_priv, id) \
2499
	(!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2500 2501 2502 2503 2504 2505

#define HAS_BSD(dev_priv)	HAS_ENGINE(dev_priv, VCS)
#define HAS_BSD2(dev_priv)	HAS_ENGINE(dev_priv, VCS2)
#define HAS_BLT(dev_priv)	HAS_ENGINE(dev_priv, BCS)
#define HAS_VEBOX(dev_priv)	HAS_ENGINE(dev_priv, VECS)

2506 2507
#define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN7(dev_priv)

2508 2509 2510
#define HAS_LLC(dev_priv)	((dev_priv)->info.has_llc)
#define HAS_SNOOP(dev_priv)	((dev_priv)->info.has_snoop)
#define HAS_EDRAM(dev_priv)	(!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2511 2512
#define HAS_WT(dev_priv)	((IS_HASWELL(dev_priv) || \
				 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2513

2514
#define HWS_NEEDS_PHYSICAL(dev_priv)	((dev_priv)->info.hws_needs_physical)
2515

2516 2517
#define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
		((dev_priv)->info.has_logical_ring_contexts)
2518 2519
#define HAS_LOGICAL_RING_ELSQ(dev_priv) \
		((dev_priv)->info.has_logical_ring_elsq)
2520 2521
#define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
		((dev_priv)->info.has_logical_ring_preemption)
2522 2523 2524

#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)

2525 2526 2527
#define USES_PPGTT(dev_priv)		(i915_modparams.enable_ppgtt)
#define USES_FULL_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt >= 2)
#define USES_FULL_48BIT_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt == 3)
2528 2529 2530 2531
#define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
	GEM_BUG_ON((sizes) == 0); \
	((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
})
2532 2533 2534 2535

#define HAS_OVERLAY(dev_priv)		 ((dev_priv)->info.has_overlay)
#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
		((dev_priv)->info.overlay_needs_physical)
2536

2537
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
2538
#define HAS_BROKEN_CS_TLB(dev_priv)	(IS_I830(dev_priv) || IS_I845G(dev_priv))
2539

2540
/* WaRsDisableCoarsePowerGating:skl,cnl */
2541
#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2542 2543
	(IS_CANNONLAKE(dev_priv) || \
	 IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2544

2545 2546 2547 2548 2549
/*
 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
 * even when in MSI mode. This results in spurious interrupt warnings if the
 * legacy irq no. is shared with another device. The kernel then disables that
 * interrupt source and so prevents the other device from working properly.
2550 2551 2552
 *
 * Since we don't enable MSI anymore on gen4, we can always use GMBUS/AUX
 * interrupts.
2553
 */
2554 2555
#define HAS_AUX_IRQ(dev_priv)   true
#define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
2556

2557 2558 2559
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 * rows, which changed the alignment requirements and fence programming.
 */
2560 2561 2562
#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
					 !(IS_I915G(dev_priv) || \
					 IS_I915GM(dev_priv)))
2563 2564
#define SUPPORTS_TV(dev_priv)		((dev_priv)->info.supports_tv)
#define I915_HAS_HOTPLUG(dev_priv)	((dev_priv)->info.has_hotplug)
2565

2566 2567
#define HAS_FW_BLC(dev_priv) 	(INTEL_GEN(dev_priv) > 2)
#define HAS_FBC(dev_priv)	((dev_priv)->info.has_fbc)
2568
#define HAS_CUR_FBC(dev_priv)	(!HAS_GMCH_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 7)
2569

2570
#define HAS_IPS(dev_priv)	(IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2571

2572
#define HAS_DP_MST(dev_priv)	((dev_priv)->info.has_dp_mst)
2573

2574 2575 2576
#define HAS_DDI(dev_priv)		 ((dev_priv)->info.has_ddi)
#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
#define HAS_PSR(dev_priv)		 ((dev_priv)->info.has_psr)
2577

2578 2579
#define HAS_RC6(dev_priv)		 ((dev_priv)->info.has_rc6)
#define HAS_RC6p(dev_priv)		 ((dev_priv)->info.has_rc6p)
2580
#define HAS_RC6pp(dev_priv)		 (false) /* HW was never validated */
P
Paulo Zanoni 已提交
2581

2582
#define HAS_CSR(dev_priv)	((dev_priv)->info.has_csr)
2583

2584
#define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2585 2586
#define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)

2587 2588
#define HAS_IPC(dev_priv)		 ((dev_priv)->info.has_ipc)

2589 2590 2591 2592 2593
/*
 * For now, anything with a GuC requires uCode loading, and then supports
 * command submission once loaded. But these are logically independent
 * properties, so we have separate macros to test them.
 */
2594
#define HAS_GUC(dev_priv)	((dev_priv)->info.has_guc)
2595
#define HAS_GUC_CT(dev_priv)	((dev_priv)->info.has_guc_ct)
2596 2597
#define HAS_GUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
#define HAS_GUC_SCHED(dev_priv)	(HAS_GUC(dev_priv))
2598 2599 2600

/* For now, anything with a GuC has also HuC */
#define HAS_HUC(dev_priv)	(HAS_GUC(dev_priv))
2601
#define HAS_HUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
2602

2603
/* Having a GuC is not the same as using a GuC */
2604 2605 2606
#define USES_GUC(dev_priv)		intel_uc_is_using_guc()
#define USES_GUC_SUBMISSION(dev_priv)	intel_uc_is_using_guc_submission()
#define USES_HUC(dev_priv)		intel_uc_is_using_huc()
2607

2608
#define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2609

2610
#define HAS_POOLED_EU(dev_priv)	((dev_priv)->info.has_pooled_eu)
2611

2612
#define INTEL_PCH_DEVICE_ID_MASK		0xff80
2613 2614 2615 2616 2617
#define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
#define INTEL_PCH_PPT_DEVICE_ID_TYPE		0x1e00
#define INTEL_PCH_LPT_DEVICE_ID_TYPE		0x8c00
#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE		0x9c00
2618 2619
#define INTEL_PCH_WPT_DEVICE_ID_TYPE		0x8c80
#define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE		0x9c80
2620 2621
#define INTEL_PCH_SPT_DEVICE_ID_TYPE		0xA100
#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE		0x9D00
2622
#define INTEL_PCH_KBP_DEVICE_ID_TYPE		0xA280
2623
#define INTEL_PCH_CNP_DEVICE_ID_TYPE		0xA300
2624
#define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE		0x9D80
2625
#define INTEL_PCH_ICP_DEVICE_ID_TYPE		0x3480
2626
#define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
2627
#define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
2628
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
2629

2630
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2631
#define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
2632
#define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
2633
#define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
2634
#define HAS_PCH_CNP_LP(dev_priv) \
2635
	(INTEL_PCH_ID(dev_priv) == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE)
2636 2637 2638
#define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2639
#define HAS_PCH_LPT_LP(dev_priv) \
2640 2641
	(INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
	 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
2642
#define HAS_PCH_LPT_H(dev_priv) \
2643 2644
	(INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
	 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE)
2645 2646 2647 2648
#define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
#define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2649

2650
#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2651

2652
#define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
2653

2654
/* DPF == dynamic parity feature */
2655
#define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2656 2657
#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
				 2 : HAS_L3_DPF(dev_priv))
2658

2659
#define GT_FREQUENCY_MULTIPLIER 50
A
Akash Goel 已提交
2660
#define GEN9_FREQ_SCALER 3
2661

2662 2663
#include "i915_trace.h"

2664
static inline bool intel_vtd_active(void)
2665 2666
{
#ifdef CONFIG_INTEL_IOMMU
2667
	if (intel_iommu_gfx_mapped)
2668 2669 2670 2671 2672
		return true;
#endif
	return false;
}

2673 2674 2675 2676 2677
static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
{
	return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
}

2678 2679 2680
static inline bool
intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
{
2681
	return IS_BROXTON(dev_priv) && intel_vtd_active();
2682 2683
}

2684
int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2685
				int enable_ppgtt);
2686

2687
/* i915_drv.c */
2688 2689 2690 2691 2692 2693 2694
void __printf(3, 4)
__i915_printk(struct drm_i915_private *dev_priv, const char *level,
	      const char *fmt, ...);

#define i915_report_error(dev_priv, fmt, ...)				   \
	__i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)

2695
#ifdef CONFIG_COMPAT
D
Dave Airlie 已提交
2696 2697
extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
			      unsigned long arg);
2698 2699
#else
#define i915_compat_ioctl NULL
2700
#endif
2701 2702 2703 2704 2705
extern const struct dev_pm_ops i915_pm_ops;

extern int i915_driver_load(struct pci_dev *pdev,
			    const struct pci_device_id *ent);
extern void i915_driver_unload(struct drm_device *dev);
2706 2707
extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2708

2709 2710 2711 2712 2713
extern void i915_reset(struct drm_i915_private *i915,
		       unsigned int stalled_mask,
		       const char *reason);
extern int i915_reset_engine(struct intel_engine_cs *engine,
			     const char *reason);
2714

2715
extern bool intel_has_reset_engine(struct drm_i915_private *dev_priv);
2716
extern int intel_reset_guc(struct drm_i915_private *dev_priv);
2717 2718
extern int intel_guc_reset_engine(struct intel_guc *guc,
				  struct intel_engine_cs *engine);
2719
extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2720
extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
2721 2722 2723 2724
extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2725
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2726

2727
int intel_engines_init_mmio(struct drm_i915_private *dev_priv);
2728 2729
int intel_engines_init(struct drm_i915_private *dev_priv);

2730
/* intel_hotplug.c */
2731 2732
void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
			   u32 pin_mask, u32 long_mask);
2733 2734 2735
void intel_hpd_init(struct drm_i915_private *dev_priv);
void intel_hpd_init_work(struct drm_i915_private *dev_priv);
void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2736 2737 2738 2739
enum port intel_hpd_pin_to_port(struct drm_i915_private *dev_priv,
				enum hpd_pin pin);
enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
				   enum port port);
2740 2741
bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2742

L
Linus Torvalds 已提交
2743
/* i915_irq.c */
2744 2745 2746 2747
static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
{
	unsigned long delay;

2748
	if (unlikely(!i915_modparams.enable_hangcheck))
2749 2750 2751 2752 2753 2754 2755 2756 2757 2758 2759 2760
		return;

	/* Don't continually defer the hangcheck so that it is always run at
	 * least once after work has been scheduled on any ring. Otherwise,
	 * we will ignore a hung ring if a second ring is kept busy.
	 */

	delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
	queue_delayed_work(system_long_wq,
			   &dev_priv->gpu_error.hangcheck_work, delay);
}

2761
__printf(4, 5)
2762 2763
void i915_handle_error(struct drm_i915_private *dev_priv,
		       u32 engine_mask,
2764
		       unsigned long flags,
2765
		       const char *fmt, ...);
2766
#define I915_ERROR_CAPTURE BIT(0)
L
Linus Torvalds 已提交
2767

2768
extern void intel_irq_init(struct drm_i915_private *dev_priv);
2769
extern void intel_irq_fini(struct drm_i915_private *dev_priv);
2770 2771
int intel_irq_install(struct drm_i915_private *dev_priv);
void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2772

2773 2774
static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
{
2775
	return dev_priv->gvt;
2776 2777
}

2778
static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2779
{
2780
	return dev_priv->vgpu.active;
2781
}
2782

2783 2784
u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
			      enum pipe pipe);
2785
void
2786
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2787
		     u32 status_mask);
2788 2789

void
2790
i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2791
		      u32 status_mask);
2792

2793 2794
void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2795 2796 2797
void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
				   uint32_t mask,
				   uint32_t bits);
2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810
void ilk_update_display_irq(struct drm_i915_private *dev_priv,
			    uint32_t interrupt_mask,
			    uint32_t enabled_irq_mask);
static inline void
ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, bits);
}
static inline void
ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, 0);
}
2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823 2824
void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
			 enum pipe pipe,
			 uint32_t interrupt_mask,
			 uint32_t enabled_irq_mask);
static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
				       enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
}
static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
					enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
}
2825 2826 2827
void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
				  uint32_t interrupt_mask,
				  uint32_t enabled_irq_mask);
2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838
static inline void
ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, bits);
}
static inline void
ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, 0);
}

2839 2840 2841 2842 2843 2844 2845 2846 2847
/* i915_gem.c */
int i915_gem_create_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2848 2849
int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2850 2851 2852 2853
int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
			     struct drm_file *file_priv);
2854 2855 2856 2857
int i915_gem_execbuffer_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file_priv);
2858 2859
int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
B
Ben Widawsky 已提交
2860 2861 2862 2863
int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
2864 2865
int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *file_priv);
2866 2867
int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
2868 2869 2870 2871
int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
2872 2873
int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
2874 2875
int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file);
2876 2877
int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
2878 2879
int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2880
void i915_gem_sanitize(struct drm_i915_private *i915);
2881 2882
int i915_gem_init_early(struct drm_i915_private *dev_priv);
void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
2883
void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
2884
int i915_gem_freeze(struct drm_i915_private *dev_priv);
2885 2886
int i915_gem_freeze_late(struct drm_i915_private *dev_priv);

2887
void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
2888
void i915_gem_object_free(struct drm_i915_gem_object *obj);
2889 2890
void i915_gem_object_init(struct drm_i915_gem_object *obj,
			 const struct drm_i915_gem_object_ops *ops);
2891 2892 2893 2894 2895
struct drm_i915_gem_object *
i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
struct drm_i915_gem_object *
i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
				 const void *data, size_t size);
2896
void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
2897
void i915_gem_free_object(struct drm_gem_object *obj);
2898

2899 2900
static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
{
2901 2902 2903
	if (!atomic_read(&i915->mm.free_count))
		return;

2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914
	/* A single pass should suffice to release all the freed objects (along
	 * most call paths) , but be a little more paranoid in that freeing
	 * the objects does take a little amount of time, during which the rcu
	 * callbacks could have added new objects into the freed list, and
	 * armed the work again.
	 */
	do {
		rcu_barrier();
	} while (flush_work(&i915->mm.free_work));
}

2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931 2932 2933 2934
static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
{
	/*
	 * Similar to objects above (see i915_gem_drain_freed-objects), in
	 * general we have workers that are armed by RCU and then rearm
	 * themselves in their callbacks. To be paranoid, we need to
	 * drain the workqueue a second time after waiting for the RCU
	 * grace period so that we catch work queued via RCU from the first
	 * pass. As neither drain_workqueue() nor flush_workqueue() report
	 * a result, we make an assumption that we only don't require more
	 * than 2 passes to catch all recursive RCU delayed work.
	 *
	 */
	int pass = 2;
	do {
		rcu_barrier();
		drain_workqueue(i915->wq);
	} while (--pass);
}

C
Chris Wilson 已提交
2935
struct i915_vma * __must_check
2936 2937
i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
			 const struct i915_ggtt_view *view,
2938
			 u64 size,
2939 2940
			 u64 alignment,
			 u64 flags);
2941

2942
int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
2943
void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2944

2945 2946
void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);

C
Chris Wilson 已提交
2947
static inline int __sg_page_count(const struct scatterlist *sg)
2948
{
2949 2950
	return sg->length >> PAGE_SHIFT;
}
2951

2952 2953 2954
struct scatterlist *
i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
		       unsigned int n, unsigned int *offset);
2955

2956 2957 2958
struct page *
i915_gem_object_get_page(struct drm_i915_gem_object *obj,
			 unsigned int n);
2959

2960 2961 2962
struct page *
i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
			       unsigned int n);
2963

2964 2965 2966
dma_addr_t
i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
				unsigned long n);
2967

2968
void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
2969
				 struct sg_table *pages,
M
Matthew Auld 已提交
2970
				 unsigned int sg_page_sizes);
C
Chris Wilson 已提交
2971 2972 2973 2974 2975
int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);

static inline int __must_check
i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
{
2976
	might_lock(&obj->mm.lock);
C
Chris Wilson 已提交
2977

2978
	if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
C
Chris Wilson 已提交
2979 2980 2981 2982 2983
		return 0;

	return __i915_gem_object_get_pages(obj);
}

2984 2985 2986 2987 2988 2989
static inline bool
i915_gem_object_has_pages(struct drm_i915_gem_object *obj)
{
	return !IS_ERR_OR_NULL(READ_ONCE(obj->mm.pages));
}

C
Chris Wilson 已提交
2990 2991
static inline void
__i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2992
{
2993
	GEM_BUG_ON(!i915_gem_object_has_pages(obj));
C
Chris Wilson 已提交
2994

2995
	atomic_inc(&obj->mm.pages_pin_count);
C
Chris Wilson 已提交
2996 2997 2998 2999 3000
}

static inline bool
i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
{
3001
	return atomic_read(&obj->mm.pages_pin_count);
C
Chris Wilson 已提交
3002 3003 3004 3005 3006
}

static inline void
__i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
{
3007
	GEM_BUG_ON(!i915_gem_object_has_pages(obj));
C
Chris Wilson 已提交
3008 3009
	GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));

3010
	atomic_dec(&obj->mm.pages_pin_count);
3011
}
3012

3013 3014
static inline void
i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3015
{
C
Chris Wilson 已提交
3016
	__i915_gem_object_unpin_pages(obj);
3017 3018
}

3019 3020 3021 3022 3023 3024 3025
enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
	I915_MM_NORMAL = 0,
	I915_MM_SHRINKER
};

void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
				 enum i915_mm_subclass subclass);
3026
void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
C
Chris Wilson 已提交
3027

3028 3029 3030
enum i915_map_type {
	I915_MAP_WB = 0,
	I915_MAP_WC,
3031 3032 3033
#define I915_MAP_OVERRIDE BIT(31)
	I915_MAP_FORCE_WB = I915_MAP_WB | I915_MAP_OVERRIDE,
	I915_MAP_FORCE_WC = I915_MAP_WC | I915_MAP_OVERRIDE,
3034 3035
};

3036 3037
/**
 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3038 3039
 * @obj: the object to map into kernel address space
 * @type: the type of mapping, used to select pgprot_t
3040 3041 3042
 *
 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
 * pages and then returns a contiguous mapping of the backing storage into
3043 3044
 * the kernel address space. Based on the @type of mapping, the PTE will be
 * set to either WriteBack or WriteCombine (via pgprot_t).
3045
 *
3046 3047
 * The caller is responsible for calling i915_gem_object_unpin_map() when the
 * mapping is no longer required.
3048
 *
3049 3050
 * Returns the pointer through which to access the mapped object, or an
 * ERR_PTR() on error.
3051
 */
3052 3053
void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
					   enum i915_map_type type);
3054 3055 3056

/**
 * i915_gem_object_unpin_map - releases an earlier mapping
3057
 * @obj: the object to unmap
3058 3059 3060 3061 3062 3063 3064 3065 3066 3067 3068
 *
 * After pinning the object and mapping its pages, once you are finished
 * with your access, call i915_gem_object_unpin_map() to release the pin
 * upon the mapping. Once the pin count reaches zero, that mapping may be
 * removed.
 */
static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
{
	i915_gem_object_unpin_pages(obj);
}

3069 3070 3071 3072
int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
				    unsigned int *needs_clflush);
int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
				     unsigned int *needs_clflush);
3073 3074 3075
#define CLFLUSH_BEFORE	BIT(0)
#define CLFLUSH_AFTER	BIT(1)
#define CLFLUSH_FLAGS	(CLFLUSH_BEFORE | CLFLUSH_AFTER)
3076 3077 3078 3079 3080 3081 3082

static inline void
i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
{
	i915_gem_object_unpin_pages(obj);
}

3083
int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
B
Ben Widawsky 已提交
3084
void i915_vma_move_to_active(struct i915_vma *vma,
3085
			     struct i915_request *rq,
3086
			     unsigned int flags);
3087 3088 3089
int i915_gem_dumb_create(struct drm_file *file_priv,
			 struct drm_device *dev,
			 struct drm_mode_create_dumb *args);
3090 3091
int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
		      uint32_t handle, uint64_t *offset);
3092
int i915_gem_mmap_gtt_version(void);
3093 3094 3095 3096 3097

void i915_gem_track_fb(struct drm_i915_gem_object *old,
		       struct drm_i915_gem_object *new,
		       unsigned frontbuffer_bits);

3098
int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3099

3100
struct i915_request *
3101
i915_gem_find_active_request(struct intel_engine_cs *engine);
3102

3103 3104 3105 3106 3107 3108
static inline bool i915_reset_backoff(struct i915_gpu_error *error)
{
	return unlikely(test_bit(I915_RESET_BACKOFF, &error->flags));
}

static inline bool i915_reset_handoff(struct i915_gpu_error *error)
3109
{
3110
	return unlikely(test_bit(I915_RESET_HANDOFF, &error->flags));
3111 3112
}

3113
static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3114
{
3115
	return unlikely(test_bit(I915_WEDGED, &error->flags));
3116 3117
}

3118
static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error *error)
3119
{
3120
	return i915_reset_backoff(error) | i915_terminally_wedged(error);
M
Mika Kuoppala 已提交
3121 3122 3123 3124
}

static inline u32 i915_reset_count(struct i915_gpu_error *error)
{
3125
	return READ_ONCE(error->reset_count);
3126
}
3127

3128 3129 3130 3131 3132 3133
static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
					  struct intel_engine_cs *engine)
{
	return READ_ONCE(error->reset_engine_count[engine->id]);
}

3134
struct i915_request *
3135
i915_gem_reset_prepare_engine(struct intel_engine_cs *engine);
3136
int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
3137 3138
void i915_gem_reset(struct drm_i915_private *dev_priv,
		    unsigned int stalled_mask);
3139
void i915_gem_reset_finish_engine(struct intel_engine_cs *engine);
3140
void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
3141
void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3142
bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
3143
void i915_gem_reset_engine(struct intel_engine_cs *engine,
3144 3145
			   struct i915_request *request,
			   bool stalled);
3146

3147
void i915_gem_init_mmio(struct drm_i915_private *i915);
3148 3149
int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3150
void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3151
void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3152 3153
int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
			   unsigned int flags);
3154 3155
int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
void i915_gem_resume(struct drm_i915_private *dev_priv);
3156
int i915_gem_fault(struct vm_fault *vmf);
3157 3158 3159 3160
int i915_gem_object_wait(struct drm_i915_gem_object *obj,
			 unsigned int flags,
			 long timeout,
			 struct intel_rps_client *rps);
3161 3162
int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
				  unsigned int flags,
3163
				  const struct i915_sched_attr *attr);
3164 3165
#define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX

3166
int __must_check
3167 3168 3169
i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write);
int __must_check
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write);
3170
int __must_check
3171
i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
C
Chris Wilson 已提交
3172
struct i915_vma * __must_check
3173 3174
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
				     u32 alignment,
3175 3176
				     const struct i915_ggtt_view *view,
				     unsigned int flags);
C
Chris Wilson 已提交
3177
void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3178
int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3179
				int align);
3180
int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
3181
void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3182

3183 3184 3185
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
				    enum i915_cache_level cache_level);

3186 3187 3188 3189 3190 3191
struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
				struct dma_buf *dma_buf);

struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
				struct drm_gem_object *gem_obj, int flags);

3192 3193 3194 3195 3196 3197
static inline struct i915_hw_ppgtt *
i915_vm_to_ppgtt(struct i915_address_space *vm)
{
	return container_of(vm, struct i915_hw_ppgtt, base);
}

J
Joonas Lahtinen 已提交
3198
/* i915_gem_fence_reg.c */
3199 3200 3201
struct drm_i915_fence_reg *
i915_reserve_fence(struct drm_i915_private *dev_priv);
void i915_unreserve_fence(struct drm_i915_fence_reg *fence);
3202

3203
void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
3204
void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3205

3206
void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3207 3208 3209 3210
void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
				       struct sg_table *pages);
void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
					 struct sg_table *pages);
3211

3212 3213 3214 3215 3216 3217
static inline struct i915_gem_context *
__i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
{
	return idr_find(&file_priv->context_idr, id);
}

3218 3219 3220 3221 3222
static inline struct i915_gem_context *
i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
{
	struct i915_gem_context *ctx;

3223 3224 3225 3226 3227
	rcu_read_lock();
	ctx = __i915_gem_context_lookup_rcu(file_priv, id);
	if (ctx && !kref_get_unless_zero(&ctx->ref))
		ctx = NULL;
	rcu_read_unlock();
3228 3229 3230 3231

	return ctx;
}

C
Chris Wilson 已提交
3232 3233 3234 3235 3236 3237 3238 3239 3240 3241
static inline struct intel_timeline *
i915_gem_context_lookup_timeline(struct i915_gem_context *ctx,
				 struct intel_engine_cs *engine)
{
	struct i915_address_space *vm;

	vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base;
	return &vm->timeline.engine[engine->id];
}

3242 3243
int i915_perf_open_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file);
3244 3245 3246 3247
int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
				  struct drm_file *file);
3248 3249 3250
void i915_oa_init_reg_state(struct intel_engine_cs *engine,
			    struct i915_gem_context *ctx,
			    uint32_t *reg_state);
3251

3252
/* i915_gem_evict.c */
3253
int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3254
					  u64 min_size, u64 alignment,
3255
					  unsigned cache_level,
3256
					  u64 start, u64 end,
3257
					  unsigned flags);
3258 3259 3260
int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
					 struct drm_mm_node *node,
					 unsigned int flags);
3261
int i915_gem_evict_vm(struct i915_address_space *vm);
3262

3263 3264
void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv);

3265
/* belongs in i915_gem_gtt.h */
3266
static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3267
{
3268
	wmb();
3269
	if (INTEL_GEN(dev_priv) < 6)
3270 3271
		intel_gtt_chipset_flush();
}
3272

3273
/* i915_gem_stolen.c */
3274 3275 3276
int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
				struct drm_mm_node *node, u64 size,
				unsigned alignment);
3277 3278 3279 3280
int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
					 struct drm_mm_node *node, u64 size,
					 unsigned alignment, u64 start,
					 u64 end);
3281 3282
void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
				 struct drm_mm_node *node);
3283
int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3284
void i915_gem_cleanup_stolen(struct drm_device *dev);
3285
struct drm_i915_gem_object *
3286 3287
i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
			      resource_size_t size);
3288
struct drm_i915_gem_object *
3289
i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3290 3291 3292
					       resource_size_t stolen_offset,
					       resource_size_t gtt_offset,
					       resource_size_t size);
3293

3294 3295 3296
/* i915_gem_internal.c */
struct drm_i915_gem_object *
i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3297
				phys_addr_t size);
3298

3299
/* i915_gem_shrinker.c */
3300
unsigned long i915_gem_shrink(struct drm_i915_private *i915,
3301
			      unsigned long target,
3302
			      unsigned long *nr_scanned,
3303 3304 3305 3306
			      unsigned flags);
#define I915_SHRINK_PURGEABLE 0x1
#define I915_SHRINK_UNBOUND 0x2
#define I915_SHRINK_BOUND 0x4
3307
#define I915_SHRINK_ACTIVE 0x8
3308
#define I915_SHRINK_VMAPS 0x10
3309 3310 3311
unsigned long i915_gem_shrink_all(struct drm_i915_private *i915);
void i915_gem_shrinker_register(struct drm_i915_private *i915);
void i915_gem_shrinker_unregister(struct drm_i915_private *i915);
3312 3313


3314
/* i915_gem_tiling.c */
3315
static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3316
{
3317
	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3318 3319

	return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3320
		i915_gem_object_is_tiled(obj);
3321 3322
}

3323 3324 3325 3326 3327
u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
			unsigned int tiling, unsigned int stride);
u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
			     unsigned int tiling, unsigned int stride);

3328
/* i915_debugfs.c */
3329
#ifdef CONFIG_DEBUG_FS
3330
int i915_debugfs_register(struct drm_i915_private *dev_priv);
J
Jani Nikula 已提交
3331
int i915_debugfs_connector_add(struct drm_connector *connector);
3332
void intel_display_crc_init(struct drm_i915_private *dev_priv);
3333
#else
3334
static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3335 3336
static inline int i915_debugfs_connector_add(struct drm_connector *connector)
{ return 0; }
3337
static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3338
#endif
3339

3340
const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3341

3342
/* i915_cmd_parser.c */
3343
int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3344
void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3345 3346 3347 3348 3349 3350 3351
void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
int intel_engine_cmd_parser(struct intel_engine_cs *engine,
			    struct drm_i915_gem_object *batch_obj,
			    struct drm_i915_gem_object *shadow_batch_obj,
			    u32 batch_start_offset,
			    u32 batch_len,
			    bool is_master);
3352

3353 3354 3355
/* i915_perf.c */
extern void i915_perf_init(struct drm_i915_private *dev_priv);
extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3356 3357
extern void i915_perf_register(struct drm_i915_private *dev_priv);
extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3358

3359
/* i915_suspend.c */
3360 3361
extern int i915_save_state(struct drm_i915_private *dev_priv);
extern int i915_restore_state(struct drm_i915_private *dev_priv);
3362

B
Ben Widawsky 已提交
3363
/* i915_sysfs.c */
D
David Weinehall 已提交
3364 3365
void i915_setup_sysfs(struct drm_i915_private *dev_priv);
void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
B
Ben Widawsky 已提交
3366

3367 3368 3369 3370
/* intel_lpe_audio.c */
int  intel_lpe_audio_init(struct drm_i915_private *dev_priv);
void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv);
void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv);
3371
void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
3372 3373
			    enum pipe pipe, enum port port,
			    const void *eld, int ls_clock, bool dp_output);
3374

3375
/* intel_i2c.c */
3376 3377
extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3378 3379
extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
				     unsigned int pin);
3380
extern int intel_gmbus_output_aksv(struct i2c_adapter *adapter);
3381

3382 3383
extern struct i2c_adapter *
intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
C
Chris Wilson 已提交
3384 3385
extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3386
static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3387 3388 3389
{
	return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
}
3390
extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3391

3392
/* intel_bios.c */
3393
void intel_bios_init(struct drm_i915_private *dev_priv);
3394
void intel_bios_cleanup(struct drm_i915_private *dev_priv);
J
Jani Nikula 已提交
3395
bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3396
bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3397
bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3398
bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3399
bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3400
bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3401
bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3402 3403
bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
				     enum port port);
3404 3405 3406
bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
				enum port port);

J
Jesse Barnes 已提交
3407 3408 3409 3410 3411 3412 3413 3414 3415
/* intel_acpi.c */
#ifdef CONFIG_ACPI
extern void intel_register_dsm_handler(void);
extern void intel_unregister_dsm_handler(void);
#else
static inline void intel_register_dsm_handler(void) { return; }
static inline void intel_unregister_dsm_handler(void) { return; }
#endif /* CONFIG_ACPI */

3416 3417 3418 3419 3420 3421 3422
/* intel_device_info.c */
static inline struct intel_device_info *
mkwrite_device_info(struct drm_i915_private *dev_priv)
{
	return (struct intel_device_info *)&dev_priv->info;
}

J
Jesse Barnes 已提交
3423
/* modesetting */
3424
extern void intel_modeset_init_hw(struct drm_device *dev);
3425
extern int intel_modeset_init(struct drm_device *dev);
J
Jesse Barnes 已提交
3426
extern void intel_modeset_cleanup(struct drm_device *dev);
3427
extern int intel_connector_register(struct drm_connector *);
3428
extern void intel_connector_unregister(struct drm_connector *);
3429 3430
extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
				       bool state);
3431
extern void intel_display_resume(struct drm_device *dev);
3432 3433
extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3434
extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3435
extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3436
extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3437
extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3438
				  bool enable);
3439

B
Ben Widawsky 已提交
3440 3441
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file);
3442

3443
/* overlay */
3444 3445
extern struct intel_overlay_error_state *
intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3446 3447
extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
					    struct intel_overlay_error_state *error);
3448

3449 3450
extern struct intel_display_error_state *
intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3451
extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3452
					    struct intel_display_error_state *error);
3453

3454
int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3455
int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv, u32 mbox,
3456 3457
				    u32 val, int fast_timeout_us,
				    int slow_timeout_ms);
3458
#define sandybridge_pcode_write(dev_priv, mbox, val)	\
3459
	sandybridge_pcode_write_timeout(dev_priv, mbox, val, 500, 0)
3460

3461 3462
int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
		      u32 reply_mask, u32 reply, int timeout_base_ms);
3463 3464

/* intel_sideband.c */
3465
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3466
int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3467
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3468 3469
u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3470 3471 3472 3473
u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3474 3475
u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3476 3477
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3478 3479 3480 3481
u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
		   enum intel_sbi_destination destination);
void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
		     enum intel_sbi_destination destination);
3482 3483
u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3484

3485
/* intel_dpio_phy.c */
3486
void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3487
			     enum dpio_phy *phy, enum dpio_channel *ch);
3488 3489 3490
void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
				  enum port port, u32 margin, u32 scale,
				  u32 enable, u32 deemphasis);
3491 3492 3493 3494 3495 3496
void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
			    enum dpio_phy phy);
bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
			      enum dpio_phy phy);
3497
uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(uint8_t lane_count);
3498 3499 3500 3501
void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
				     uint8_t lane_lat_optim_mask);
uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);

3502 3503 3504
void chv_set_phy_signal_level(struct intel_encoder *encoder,
			      u32 deemph_reg_value, u32 margin_reg_value,
			      bool uniq_trans_scale);
3505
void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3506
			      const struct intel_crtc_state *crtc_state,
3507
			      bool reset);
3508 3509 3510 3511
void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
			    const struct intel_crtc_state *crtc_state);
void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
				const struct intel_crtc_state *crtc_state);
3512
void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3513 3514
void chv_phy_post_pll_disable(struct intel_encoder *encoder,
			      const struct intel_crtc_state *old_crtc_state);
3515

3516 3517 3518
void vlv_set_phy_signal_level(struct intel_encoder *encoder,
			      u32 demph_reg_value, u32 preemph_reg_value,
			      u32 uniqtranscale_reg_value, u32 tx3_demph);
3519 3520 3521 3522 3523 3524
void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
			    const struct intel_crtc_state *crtc_state);
void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
				const struct intel_crtc_state *crtc_state);
void vlv_phy_reset_lanes(struct intel_encoder *encoder,
			 const struct intel_crtc_state *old_crtc_state);
3525

3526 3527
int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3528
u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
3529
			   const i915_reg_t reg);
3530

T
Tvrtko Ursulin 已提交
3531 3532
u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1);

3533 3534 3535 3536 3537 3538
static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
					 const i915_reg_t reg)
{
	return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(dev_priv, reg), 1000);
}

3539 3540 3541 3542 3543 3544 3545 3546 3547 3548 3549 3550 3551
#define I915_READ8(reg)		dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
#define I915_WRITE8(reg, val)	dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)

#define I915_READ16(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
#define I915_WRITE16(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
#define I915_READ16_NOTRACE(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
#define I915_WRITE16_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)

#define I915_READ(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
#define I915_WRITE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
#define I915_READ_NOTRACE(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
#define I915_WRITE_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)

3552 3553 3554 3555
/* Be very careful with read/write 64-bit values. On 32-bit machines, they
 * will be implemented using 2 32-bit writes in an arbitrary order with
 * an arbitrary delay between them. This can cause the hardware to
 * act upon the intermediate value, possibly leading to corruption and
3556 3557 3558 3559 3560 3561 3562 3563 3564
 * machine death. For this reason we do not support I915_WRITE64, or
 * dev_priv->uncore.funcs.mmio_writeq.
 *
 * When reading a 64-bit value as two 32-bit values, the delay may cause
 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
 * occasionally a 64-bit register does not actualy support a full readq
 * and must be read using two 32-bit reads.
 *
 * You have been warned.
3565
 */
3566
#define I915_READ64(reg)	dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3567

3568
#define I915_READ64_2x32(lower_reg, upper_reg) ({			\
3569 3570
	u32 upper, lower, old_upper, loop = 0;				\
	upper = I915_READ(upper_reg);					\
3571
	do {								\
3572
		old_upper = upper;					\
3573
		lower = I915_READ(lower_reg);				\
3574 3575
		upper = I915_READ(upper_reg);				\
	} while (upper != old_upper && loop++ < 2);			\
3576
	(u64)upper << 32 | lower; })
3577

3578 3579 3580
#define POSTING_READ(reg)	(void)I915_READ_NOTRACE(reg)
#define POSTING_READ16(reg)	(void)I915_READ16_NOTRACE(reg)

3581
#define __raw_read(x, s) \
3582
static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
3583
					     i915_reg_t reg) \
3584
{ \
3585
	return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3586 3587 3588
}

#define __raw_write(x, s) \
3589
static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
3590
				       i915_reg_t reg, uint##x##_t val) \
3591
{ \
3592
	write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3593 3594 3595 3596 3597 3598 3599 3600 3601 3602 3603 3604 3605 3606
}
__raw_read(8, b)
__raw_read(16, w)
__raw_read(32, l)
__raw_read(64, q)

__raw_write(8, b)
__raw_write(16, w)
__raw_write(32, l)
__raw_write(64, q)

#undef __raw_read
#undef __raw_write

3607
/* These are untraced mmio-accessors that are only valid to be used inside
3608
 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3609
 * controlled.
3610
 *
3611
 * Think twice, and think again, before using these.
3612 3613 3614 3615 3616 3617 3618 3619 3620 3621 3622 3623 3624 3625 3626 3627 3628 3629 3630 3631
 *
 * As an example, these accessors can possibly be used between:
 *
 * spin_lock_irq(&dev_priv->uncore.lock);
 * intel_uncore_forcewake_get__locked();
 *
 * and
 *
 * intel_uncore_forcewake_put__locked();
 * spin_unlock_irq(&dev_priv->uncore.lock);
 *
 *
 * Note: some registers may not need forcewake held, so
 * intel_uncore_forcewake_{get,put} can be omitted, see
 * intel_uncore_forcewake_for_reg().
 *
 * Certain architectures will die if the same cacheline is concurrently accessed
 * by different clients (e.g. on Ivybridge). Access to registers should
 * therefore generally be serialised, by either the dev_priv->uncore.lock or
 * a more localised lock guarding all access to that bank of registers.
3632
 */
3633 3634
#define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3635
#define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3636 3637
#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)

3638 3639 3640 3641
/* "Broadcast RGB" property */
#define INTEL_BROADCAST_RGB_AUTO 0
#define INTEL_BROADCAST_RGB_FULL 1
#define INTEL_BROADCAST_RGB_LIMITED 2
3642

3643
static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
3644
{
3645
	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3646
		return VLV_VGACNTRL;
3647
	else if (INTEL_GEN(dev_priv) >= 5)
3648
		return CPU_VGACNTRL;
3649 3650 3651 3652
	else
		return VGACNTRL;
}

3653 3654 3655 3656 3657 3658 3659
static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
{
	unsigned long j = msecs_to_jiffies(m);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

3660 3661
static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
{
3662 3663 3664 3665 3666
	/* nsecs_to_jiffies64() does not guard against overflow */
	if (NSEC_PER_SEC % HZ &&
	    div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ)
		return MAX_JIFFY_OFFSET;

3667 3668 3669
        return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
}

3670 3671 3672 3673 3674 3675 3676 3677
static inline unsigned long
timespec_to_jiffies_timeout(const struct timespec *value)
{
	unsigned long j = timespec_to_jiffies(value);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

3678 3679 3680 3681 3682 3683 3684 3685 3686
/*
 * If you need to wait X milliseconds between events A and B, but event B
 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
 * when event A happened, then just before event B you call this function and
 * pass the timestamp as the first argument, and X as the second argument.
 */
static inline void
wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
{
3687
	unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3688 3689 3690 3691 3692 3693 3694 3695 3696 3697

	/*
	 * Don't re-read the value of "jiffies" every time since it may change
	 * behind our back and break the math.
	 */
	tmp_jiffies = jiffies;
	target_jiffies = timestamp_jiffies +
			 msecs_to_jiffies_timeout(to_wait_ms);

	if (time_after(target_jiffies, tmp_jiffies)) {
3698 3699 3700 3701
		remaining_jiffies = target_jiffies - tmp_jiffies;
		while (remaining_jiffies)
			remaining_jiffies =
			    schedule_timeout_uninterruptible(remaining_jiffies);
3702 3703
	}
}
3704 3705

static inline bool
3706
__i915_request_irq_complete(const struct i915_request *rq)
3707
{
3708
	struct intel_engine_cs *engine = rq->engine;
3709
	u32 seqno;
3710

3711 3712 3713 3714 3715 3716
	/* Note that the engine may have wrapped around the seqno, and
	 * so our request->global_seqno will be ahead of the hardware,
	 * even though it completed the request before wrapping. We catch
	 * this by kicking all the waiters before resetting the seqno
	 * in hardware, and also signal the fence.
	 */
3717
	if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags))
3718 3719
		return true;

3720 3721 3722 3723 3724 3725
	/* The request was dequeued before we were awoken. We check after
	 * inspecting the hw to confirm that this was the same request
	 * that generated the HWS update. The memory barriers within
	 * the request execution are sufficient to ensure that a check
	 * after reading the value from hw matches this request.
	 */
3726
	seqno = i915_request_global_seqno(rq);
3727 3728 3729
	if (!seqno)
		return false;

3730 3731 3732
	/* Before we do the heavier coherent read of the seqno,
	 * check the value (hopefully) in the CPU cacheline.
	 */
3733
	if (__i915_request_completed(rq, seqno))
3734 3735
		return true;

3736 3737 3738 3739 3740 3741 3742 3743 3744 3745 3746
	/* Ensure our read of the seqno is coherent so that we
	 * do not "miss an interrupt" (i.e. if this is the last
	 * request and the seqno write from the GPU is not visible
	 * by the time the interrupt fires, we will see that the
	 * request is incomplete and go back to sleep awaiting
	 * another interrupt that will never come.)
	 *
	 * Strictly, we only need to do this once after an interrupt,
	 * but it is easier and safer to do it every time the waiter
	 * is woken.
	 */
3747
	if (engine->irq_seqno_barrier &&
3748
	    test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) {
3749
		struct intel_breadcrumbs *b = &engine->breadcrumbs;
3750

3751 3752 3753 3754 3755 3756 3757 3758 3759 3760 3761 3762
		/* The ordering of irq_posted versus applying the barrier
		 * is crucial. The clearing of the current irq_posted must
		 * be visible before we perform the barrier operation,
		 * such that if a subsequent interrupt arrives, irq_posted
		 * is reasserted and our task rewoken (which causes us to
		 * do another __i915_request_irq_complete() immediately
		 * and reapply the barrier). Conversely, if the clear
		 * occurs after the barrier, then an interrupt that arrived
		 * whilst we waited on the barrier would not trigger a
		 * barrier on the next pass, and the read may not see the
		 * seqno update.
		 */
3763
		engine->irq_seqno_barrier(engine);
3764 3765 3766 3767 3768 3769 3770

		/* If we consume the irq, but we are no longer the bottom-half,
		 * the real bottom-half may not have serialised their own
		 * seqno check with the irq-barrier (i.e. may have inspected
		 * the seqno before we believe it coherent since they see
		 * irq_posted == false but we are still running).
		 */
3771
		spin_lock_irq(&b->irq_lock);
3772
		if (b->irq_wait && b->irq_wait->tsk != current)
3773 3774 3775 3776 3777 3778
			/* Note that if the bottom-half is changed as we
			 * are sending the wake-up, the new bottom-half will
			 * be woken by whomever made the change. We only have
			 * to worry about when we steal the irq-posted for
			 * ourself.
			 */
3779
			wake_up_process(b->irq_wait->tsk);
3780
		spin_unlock_irq(&b->irq_lock);
3781

3782
		if (__i915_request_completed(rq, seqno))
3783 3784
			return true;
	}
3785 3786 3787 3788

	return false;
}

3789 3790 3791
void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);

3792 3793 3794 3795 3796 3797 3798 3799 3800 3801 3802 3803 3804 3805 3806 3807
/* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
 * perform the operation. To check beforehand, pass in the parameters to
 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
 * you only need to pass in the minor offsets, page-aligned pointers are
 * always valid.
 *
 * For just checking for SSE4.1, in the foreknowledge that the future use
 * will be correctly aligned, just use i915_has_memcpy_from_wc().
 */
#define i915_can_memcpy_from_wc(dst, src, len) \
	i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)

#define i915_has_memcpy_from_wc() \
	i915_memcpy_from_wc(NULL, NULL, 0)

3808 3809 3810 3811 3812
/* i915_mm.c */
int remap_io_mapping(struct vm_area_struct *vma,
		     unsigned long addr, unsigned long pfn, unsigned long size,
		     struct io_mapping *iomap);

3813 3814 3815 3816 3817 3818 3819 3820
static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
{
	if (INTEL_GEN(i915) >= 10)
		return CNL_HWS_CSB_WRITE_INDEX;
	else
		return I915_HWS_CSB_WRITE_INDEX;
}

L
Linus Torvalds 已提交
3821
#endif