i915_drv.h 119.7 KB
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/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
 */
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/*
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 *
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#ifndef _I915_DRV_H_
#define _I915_DRV_H_

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#include <uapi/drm/i915_drm.h>
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#include <uapi/drm/drm_fourcc.h>
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#include <linux/io-mapping.h>
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include <linux/backlight.h>
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#include <linux/hashtable.h>
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#include <linux/intel-iommu.h>
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#include <linux/kref.h>
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#include <linux/pm_qos.h>
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#include <linux/reservation.h>
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#include <linux/shmem_fs.h>

#include <drm/drmP.h>
#include <drm/intel-gtt.h>
#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
#include <drm/drm_gem.h>
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#include <drm/drm_auth.h>
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#include "i915_params.h"
#include "i915_reg.h"
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#include "i915_utils.h"
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#include "intel_bios.h"
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#include "intel_dpll_mgr.h"
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#include "intel_uc.h"
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#include "intel_lrc.h"
#include "intel_ringbuffer.h"

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#include "i915_gem.h"
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#include "i915_gem_context.h"
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#include "i915_gem_fence_reg.h"
#include "i915_gem_object.h"
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#include "i915_gem_gtt.h"
#include "i915_gem_render_state.h"
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#include "i915_gem_request.h"
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#include "i915_gem_timeline.h"
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#include "i915_vma.h"

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#include "intel_gvt.h"

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/* General customization:
 */

#define DRIVER_NAME		"i915"
#define DRIVER_DESC		"Intel Graphics"
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#define DRIVER_DATE		"20170123"
#define DRIVER_TIMESTAMP	1485156432
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#undef WARN_ON
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/* Many gcc seem to no see through this and fall over :( */
#if 0
#define WARN_ON(x) ({ \
	bool __i915_warn_cond = (x); \
	if (__builtin_constant_p(__i915_warn_cond)) \
		BUILD_BUG_ON(__i915_warn_cond); \
	WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
#else
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#define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
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#endif

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#undef WARN_ON_ONCE
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#define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
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#define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
			     (long) (x), __func__);
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/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
 * which may not necessarily be a user visible problem.  This will either
 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
 * enable distros and users to tailor their preferred amount of i915 abrt
 * spam.
 */
#define I915_STATE_WARN(condition, format...) ({			\
	int __ret_warn_on = !!(condition);				\
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	if (unlikely(__ret_warn_on))					\
		if (!WARN(i915.verbose_state_checks, format))		\
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			DRM_ERROR(format);				\
	unlikely(__ret_warn_on);					\
})

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#define I915_STATE_WARN_ON(x)						\
	I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
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bool __i915_inject_load_failure(const char *func, int line);
#define i915_inject_load_failure() \
	__i915_inject_load_failure(__func__, __LINE__)

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typedef struct {
	uint32_t val;
} uint_fixed_16_16_t;

#define FP_16_16_MAX ({ \
	uint_fixed_16_16_t fp; \
	fp.val = UINT_MAX; \
	fp; \
})

static inline uint_fixed_16_16_t u32_to_fixed_16_16(uint32_t val)
{
	uint_fixed_16_16_t fp;

	WARN_ON(val >> 16);

	fp.val = val << 16;
	return fp;
}

static inline uint32_t fixed_16_16_to_u32_round_up(uint_fixed_16_16_t fp)
{
	return DIV_ROUND_UP(fp.val, 1 << 16);
}

static inline uint32_t fixed_16_16_to_u32(uint_fixed_16_16_t fp)
{
	return fp.val >> 16;
}

static inline uint_fixed_16_16_t min_fixed_16_16(uint_fixed_16_16_t min1,
						 uint_fixed_16_16_t min2)
{
	uint_fixed_16_16_t min;

	min.val = min(min1.val, min2.val);
	return min;
}

static inline uint_fixed_16_16_t max_fixed_16_16(uint_fixed_16_16_t max1,
						 uint_fixed_16_16_t max2)
{
	uint_fixed_16_16_t max;

	max.val = max(max1.val, max2.val);
	return max;
}

static inline uint_fixed_16_16_t fixed_16_16_div_round_up(uint32_t val,
							  uint32_t d)
{
	uint_fixed_16_16_t fp, res;

	fp = u32_to_fixed_16_16(val);
	res.val = DIV_ROUND_UP(fp.val, d);
	return res;
}

static inline uint_fixed_16_16_t fixed_16_16_div_round_up_u64(uint32_t val,
							      uint32_t d)
{
	uint_fixed_16_16_t res;
	uint64_t interm_val;

	interm_val = (uint64_t)val << 16;
	interm_val = DIV_ROUND_UP_ULL(interm_val, d);
	WARN_ON(interm_val >> 32);
	res.val = (uint32_t) interm_val;

	return res;
}

static inline uint_fixed_16_16_t mul_u32_fixed_16_16(uint32_t val,
						     uint_fixed_16_16_t mul)
{
	uint64_t intermediate_val;
	uint_fixed_16_16_t fp;

	intermediate_val = (uint64_t) val * mul.val;
	WARN_ON(intermediate_val >> 32);
	fp.val = (uint32_t) intermediate_val;
	return fp;
}

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static inline const char *yesno(bool v)
{
	return v ? "yes" : "no";
}

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static inline const char *onoff(bool v)
{
	return v ? "on" : "off";
}

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static inline const char *enableddisabled(bool v)
{
	return v ? "enabled" : "disabled";
}

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enum pipe {
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	INVALID_PIPE = -1,
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	PIPE_A = 0,
	PIPE_B,
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	PIPE_C,
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	_PIPE_EDP,
	I915_MAX_PIPES = _PIPE_EDP
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};
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#define pipe_name(p) ((p) + 'A')
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enum transcoder {
	TRANSCODER_A = 0,
	TRANSCODER_B,
	TRANSCODER_C,
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	TRANSCODER_EDP,
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	TRANSCODER_DSI_A,
	TRANSCODER_DSI_C,
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	I915_MAX_TRANSCODERS
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};
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static inline const char *transcoder_name(enum transcoder transcoder)
{
	switch (transcoder) {
	case TRANSCODER_A:
		return "A";
	case TRANSCODER_B:
		return "B";
	case TRANSCODER_C:
		return "C";
	case TRANSCODER_EDP:
		return "EDP";
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	case TRANSCODER_DSI_A:
		return "DSI A";
	case TRANSCODER_DSI_C:
		return "DSI C";
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	default:
		return "<invalid>";
	}
}
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static inline bool transcoder_is_dsi(enum transcoder transcoder)
{
	return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
}

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/*
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 * Global legacy plane identifier. Valid only for primary/sprite
 * planes on pre-g4x, and only for primary planes on g4x+.
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 */
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enum plane {
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	PLANE_A,
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	PLANE_B,
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	PLANE_C,
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};
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#define plane_name(p) ((p) + 'A')
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#define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
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/*
 * Per-pipe plane identifier.
 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
 * number of planes per CRTC.  Not all platforms really have this many planes,
 * which means some arrays of size I915_MAX_PLANES may have unused entries
 * between the topmost sprite plane and the cursor plane.
 *
 * This is expected to be passed to various register macros
 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
 */
enum plane_id {
	PLANE_PRIMARY,
	PLANE_SPRITE0,
	PLANE_SPRITE1,
	PLANE_CURSOR,
	I915_MAX_PLANES,
};

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#define for_each_plane_id_on_crtc(__crtc, __p) \
	for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
		for_each_if ((__crtc)->plane_ids_mask & BIT(__p))

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enum port {
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	PORT_NONE = -1,
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	PORT_A = 0,
	PORT_B,
	PORT_C,
	PORT_D,
	PORT_E,
	I915_MAX_PORTS
};
#define port_name(p) ((p) + 'A')

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#define I915_NUM_PHYS_VLV 2
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enum dpio_channel {
	DPIO_CH0,
	DPIO_CH1
};

enum dpio_phy {
	DPIO_PHY0,
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	DPIO_PHY1,
	DPIO_PHY2,
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};

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enum intel_display_power_domain {
	POWER_DOMAIN_PIPE_A,
	POWER_DOMAIN_PIPE_B,
	POWER_DOMAIN_PIPE_C,
	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
	POWER_DOMAIN_TRANSCODER_A,
	POWER_DOMAIN_TRANSCODER_B,
	POWER_DOMAIN_TRANSCODER_C,
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	POWER_DOMAIN_TRANSCODER_EDP,
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	POWER_DOMAIN_TRANSCODER_DSI_A,
	POWER_DOMAIN_TRANSCODER_DSI_C,
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	POWER_DOMAIN_PORT_DDI_A_LANES,
	POWER_DOMAIN_PORT_DDI_B_LANES,
	POWER_DOMAIN_PORT_DDI_C_LANES,
	POWER_DOMAIN_PORT_DDI_D_LANES,
	POWER_DOMAIN_PORT_DDI_E_LANES,
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	POWER_DOMAIN_PORT_DSI,
	POWER_DOMAIN_PORT_CRT,
	POWER_DOMAIN_PORT_OTHER,
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	POWER_DOMAIN_VGA,
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	POWER_DOMAIN_AUDIO,
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	POWER_DOMAIN_PLLS,
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	POWER_DOMAIN_AUX_A,
	POWER_DOMAIN_AUX_B,
	POWER_DOMAIN_AUX_C,
	POWER_DOMAIN_AUX_D,
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	POWER_DOMAIN_GMBUS,
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	POWER_DOMAIN_MODESET,
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	POWER_DOMAIN_INIT,
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	POWER_DOMAIN_NUM,
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};

#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
		((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
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#define POWER_DOMAIN_TRANSCODER(tran) \
	((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
	 (tran) + POWER_DOMAIN_TRANSCODER_A)
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enum hpd_pin {
	HPD_NONE = 0,
	HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
	HPD_CRT,
	HPD_SDVO_B,
	HPD_SDVO_C,
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	HPD_PORT_A,
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	HPD_PORT_B,
	HPD_PORT_C,
	HPD_PORT_D,
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	HPD_PORT_E,
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	HPD_NUM_PINS
};

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#define for_each_hpd_pin(__pin) \
	for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)

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struct i915_hotplug {
	struct work_struct hotplug_work;

	struct {
		unsigned long last_jiffies;
		int count;
		enum {
			HPD_ENABLED = 0,
			HPD_DISABLED = 1,
			HPD_MARK_DISABLED = 2
		} state;
	} stats[HPD_NUM_PINS];
	u32 event_bits;
	struct delayed_work reenable_work;

	struct intel_digital_port *irq_port[I915_MAX_PORTS];
	u32 long_port_mask;
	u32 short_port_mask;
	struct work_struct dig_port_work;

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	struct work_struct poll_init_work;
	bool poll_enabled;

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	/*
	 * if we get a HPD irq from DP and a HPD irq from non-DP
	 * the non-DP HPD could block the workqueue on a mode config
	 * mutex getting, that userspace may have taken. However
	 * userspace is waiting on the DP workqueue to run which is
	 * blocked behind the non-DP one.
	 */
	struct workqueue_struct *dp_wq;
};

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#define I915_GEM_GPU_DOMAINS \
	(I915_GEM_DOMAIN_RENDER | \
	 I915_GEM_DOMAIN_SAMPLER | \
	 I915_GEM_DOMAIN_COMMAND | \
	 I915_GEM_DOMAIN_INSTRUCTION | \
	 I915_GEM_DOMAIN_VERTEX)
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#define for_each_pipe(__dev_priv, __p) \
	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
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#define for_each_pipe_masked(__dev_priv, __p, __mask) \
	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
		for_each_if ((__mask) & (1 << (__p)))
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#define for_each_universal_plane(__dev_priv, __pipe, __p)		\
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	for ((__p) = 0;							\
	     (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1;	\
	     (__p)++)
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#define for_each_sprite(__dev_priv, __p, __s)				\
	for ((__s) = 0;							\
	     (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)];	\
	     (__s)++)
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#define for_each_port_masked(__port, __ports_mask) \
	for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)	\
		for_each_if ((__ports_mask) & (1 << (__port)))

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#define for_each_crtc(dev, crtc) \
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	list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
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#define for_each_intel_plane(dev, intel_plane) \
	list_for_each_entry(intel_plane,			\
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			    &(dev)->mode_config.plane_list,	\
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			    base.head)

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#define for_each_intel_plane_mask(dev, intel_plane, plane_mask)		\
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	list_for_each_entry(intel_plane,				\
			    &(dev)->mode_config.plane_list,		\
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			    base.head)					\
		for_each_if ((plane_mask) &				\
			     (1 << drm_plane_index(&intel_plane->base)))

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#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)	\
	list_for_each_entry(intel_plane,				\
			    &(dev)->mode_config.plane_list,		\
			    base.head)					\
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		for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
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#define for_each_intel_crtc(dev, intel_crtc)				\
	list_for_each_entry(intel_crtc,					\
			    &(dev)->mode_config.crtc_list,		\
			    base.head)
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#define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask)		\
	list_for_each_entry(intel_crtc,					\
			    &(dev)->mode_config.crtc_list,		\
			    base.head)					\
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		for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))

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#define for_each_intel_encoder(dev, intel_encoder)		\
	list_for_each_entry(intel_encoder,			\
			    &(dev)->mode_config.encoder_list,	\
			    base.head)

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#define for_each_intel_connector(dev, intel_connector)		\
	list_for_each_entry(intel_connector,			\
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			    &(dev)->mode_config.connector_list,	\
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			    base.head)

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#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
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		for_each_if ((intel_encoder)->base.crtc == (__crtc))
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#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
	list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
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		for_each_if ((intel_connector)->base.encoder == (__encoder))
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#define for_each_power_domain(domain, mask)				\
	for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)	\
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		for_each_if ((1 << (domain)) & (mask))
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struct drm_i915_private;
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struct i915_mm_struct;
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struct i915_mmu_object;
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struct drm_i915_file_private {
	struct drm_i915_private *dev_priv;
	struct drm_file *file;

	struct {
		spinlock_t lock;
		struct list_head request_list;
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/* 20ms is a fairly arbitrary limit (greater than the average frame time)
 * chosen to prevent the CPU getting more than a frame ahead of the GPU
 * (when using lax throttling for the frontbuffer). We also use it to
 * offer free GPU waitboosts for severely congested workloads.
 */
#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
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	} mm;
	struct idr context_idr;

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	struct intel_rps_client {
		struct list_head link;
		unsigned boosts;
	} rps;
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	unsigned int bsd_engine;
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/* Client can have a maximum of 3 contexts banned before
 * it is denied of creating new contexts. As one context
 * ban needs 4 consecutive hangs, and more if there is
 * progress in between, this is a last resort stop gap measure
 * to limit the badly behaving clients access to gpu.
 */
#define I915_MAX_CLIENT_CONTEXT_BANS 3
	int context_bans;
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};

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/* Used by dp and fdi links */
struct intel_link_m_n {
	uint32_t	tu;
	uint32_t	gmch_m;
	uint32_t	gmch_n;
	uint32_t	link_m;
	uint32_t	link_n;
};

void intel_link_compute_m_n(int bpp, int nlanes,
			    int pixel_clock, int link_clock,
			    struct intel_link_m_n *m_n);

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/* Interface history:
 *
 * 1.1: Original.
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 * 1.2: Add Power Management
 * 1.3: Add vblank support
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 * 1.4: Fix cmdbuffer path, add heap destroy
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 * 1.5: Add vblank pipe configuration
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 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 *      - Support vertical blank on secondary display pipe
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 */
#define DRIVER_MAJOR		1
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#define DRIVER_MINOR		6
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#define DRIVER_PATCHLEVEL	0

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struct opregion_header;
struct opregion_acpi;
struct opregion_swsci;
struct opregion_asle;

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struct intel_opregion {
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	struct opregion_header *header;
	struct opregion_acpi *acpi;
	struct opregion_swsci *swsci;
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	u32 swsci_gbda_sub_functions;
	u32 swsci_sbcb_sub_functions;
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	struct opregion_asle *asle;
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	void *rvda;
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	const void *vbt;
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	u32 vbt_size;
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	u32 *lid_state;
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	struct work_struct asle_work;
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};
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#define OPREGION_SIZE            (8*1024)
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struct intel_overlay;
struct intel_overlay_error_state;

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struct sdvo_device_mapping {
C
Chris Wilson 已提交
586
	u8 initialized;
587 588 589
	u8 dvo_port;
	u8 slave_addr;
	u8 dvo_wiring;
C
Chris Wilson 已提交
590
	u8 i2c_pin;
591
	u8 ddc_pin;
592 593
};

594
struct intel_connector;
595
struct intel_encoder;
596
struct intel_atomic_state;
597
struct intel_crtc_state;
598
struct intel_initial_plane_config;
599
struct intel_crtc;
600 601
struct intel_limit;
struct dpll;
602

603
struct drm_i915_display_funcs {
604
	int (*get_display_clock_speed)(struct drm_i915_private *dev_priv);
605
	int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane);
606
	int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
607 608 609
	int (*compute_intermediate_wm)(struct drm_device *dev,
				       struct intel_crtc *intel_crtc,
				       struct intel_crtc_state *newstate);
610 611 612 613 614 615
	void (*initial_watermarks)(struct intel_atomic_state *state,
				   struct intel_crtc_state *cstate);
	void (*atomic_update_watermarks)(struct intel_atomic_state *state,
					 struct intel_crtc_state *cstate);
	void (*optimize_watermarks)(struct intel_atomic_state *state,
				    struct intel_crtc_state *cstate);
616
	int (*compute_global_watermarks)(struct drm_atomic_state *state);
617
	void (*update_wm)(struct intel_crtc *crtc);
618 619
	int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
	void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
620 621 622
	/* Returns the active state of the crtc, and if the crtc is active,
	 * fills out the pipe-config with the hw state. */
	bool (*get_pipe_config)(struct intel_crtc *,
623
				struct intel_crtc_state *);
624 625
	void (*get_initial_plane_config)(struct intel_crtc *,
					 struct intel_initial_plane_config *);
626 627
	int (*crtc_compute_clock)(struct intel_crtc *crtc,
				  struct intel_crtc_state *crtc_state);
628 629 630 631
	void (*crtc_enable)(struct intel_crtc_state *pipe_config,
			    struct drm_atomic_state *old_state);
	void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
			     struct drm_atomic_state *old_state);
632 633
	void (*update_crtcs)(struct drm_atomic_state *state,
			     unsigned int *crtc_vblank_mask);
634 635
	void (*audio_codec_enable)(struct drm_connector *connector,
				   struct intel_encoder *encoder,
636
				   const struct drm_display_mode *adjusted_mode);
637
	void (*audio_codec_disable)(struct intel_encoder *encoder);
638
	void (*fdi_link_train)(struct drm_crtc *crtc);
639
	void (*init_clock_gating)(struct drm_i915_private *dev_priv);
640 641 642 643 644
	int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
			  struct drm_framebuffer *fb,
			  struct drm_i915_gem_object *obj,
			  struct drm_i915_gem_request *req,
			  uint32_t flags);
645
	void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
646 647 648 649 650
	/* clock updates for mode set */
	/* cursor updates */
	/* render clock increase/decrease */
	/* display clock increase/decrease */
	/* pll clock increase/decrease */
651

652 653
	void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
	void (*load_luts)(struct drm_crtc_state *crtc_state);
654 655
};

656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672
enum forcewake_domain_id {
	FW_DOMAIN_ID_RENDER = 0,
	FW_DOMAIN_ID_BLITTER,
	FW_DOMAIN_ID_MEDIA,

	FW_DOMAIN_ID_COUNT
};

enum forcewake_domains {
	FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
	FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
	FORCEWAKE_MEDIA	= (1 << FW_DOMAIN_ID_MEDIA),
	FORCEWAKE_ALL = (FORCEWAKE_RENDER |
			 FORCEWAKE_BLITTER |
			 FORCEWAKE_MEDIA)
};

673 674 675
#define FW_REG_READ  (1)
#define FW_REG_WRITE (2)

676 677 678 679 680 681 682 683 684 685 686 687
enum decoupled_power_domain {
	GEN9_DECOUPLED_PD_BLITTER = 0,
	GEN9_DECOUPLED_PD_RENDER,
	GEN9_DECOUPLED_PD_MEDIA,
	GEN9_DECOUPLED_PD_ALL
};

enum decoupled_ops {
	GEN9_DECOUPLED_OP_WRITE = 0,
	GEN9_DECOUPLED_OP_READ
};

688 689 690 691
enum forcewake_domains
intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
			       i915_reg_t reg, unsigned int op);

692
struct intel_uncore_funcs {
693
	void (*force_wake_get)(struct drm_i915_private *dev_priv,
694
							enum forcewake_domains domains);
695
	void (*force_wake_put)(struct drm_i915_private *dev_priv,
696
							enum forcewake_domains domains);
697

698 699 700 701
	uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
	uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
	uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
	uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
702

703
	void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
704
				uint8_t val, bool trace);
705
	void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
706
				uint16_t val, bool trace);
707
	void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
708
				uint32_t val, bool trace);
709 710
};

711 712 713 714 715 716 717
struct intel_forcewake_range {
	u32 start;
	u32 end;

	enum forcewake_domains domains;
};

718 719 720
struct intel_uncore {
	spinlock_t lock; /** lock is also taken in irq contexts. */

721 722 723
	const struct intel_forcewake_range *fw_domains_table;
	unsigned int fw_domains_table_entries;

724 725 726
	struct intel_uncore_funcs funcs;

	unsigned fifo_count;
727

728
	enum forcewake_domains fw_domains;
729
	enum forcewake_domains fw_domains_active;
730 731 732

	struct intel_uncore_forcewake_domain {
		struct drm_i915_private *i915;
733
		enum forcewake_domain_id id;
734
		enum forcewake_domains mask;
735
		unsigned wake_count;
736
		struct hrtimer timer;
737
		i915_reg_t reg_set;
738 739
		u32 val_set;
		u32 val_clear;
740 741
		i915_reg_t reg_ack;
		i915_reg_t reg_post;
742
		u32 val_reset;
743
	} fw_domain[FW_DOMAIN_ID_COUNT];
744 745

	int unclaimed_mmio_check;
746 747 748
};

/* Iterate over initialised fw domains */
749 750 751 752 753 754 755 756
#define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
	for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
	     (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
	     (domain__)++) \
		for_each_if ((mask__) & (domain__)->mask)

#define for_each_fw_domain(domain__, dev_priv__) \
	for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
757

758 759 760 761
#define CSR_VERSION(major, minor)	((major) << 16 | (minor))
#define CSR_VERSION_MAJOR(version)	((version) >> 16)
#define CSR_VERSION_MINOR(version)	((version) & 0xffff)

762
struct intel_csr {
763
	struct work_struct work;
764
	const char *fw_path;
765
	uint32_t *dmc_payload;
766
	uint32_t dmc_fw_size;
767
	uint32_t version;
768
	uint32_t mmio_count;
769
	i915_reg_t mmioaddr[8];
770
	uint32_t mmiodata[8];
771
	uint32_t dc_state;
772
	uint32_t allowed_dc_mask;
773 774
};

775 776
#define DEV_INFO_FOR_EACH_FLAG(func) \
	func(is_mobile); \
777
	func(is_lp); \
778
	func(is_alpha_support); \
779
	/* Keep has_* in alphabetical order */ \
780
	func(has_64bit_reloc); \
781
	func(has_aliasing_ppgtt); \
782
	func(has_csr); \
783
	func(has_ddi); \
784
	func(has_decoupled_mmio); \
785
	func(has_dp_mst); \
786 787
	func(has_fbc); \
	func(has_fpga_dbg); \
788 789
	func(has_full_ppgtt); \
	func(has_full_48bit_ppgtt); \
790 791 792 793
	func(has_gmbus_irq); \
	func(has_gmch_display); \
	func(has_guc); \
	func(has_hotplug); \
794 795
	func(has_hw_contexts); \
	func(has_l3_dpf); \
796
	func(has_llc); \
797 798 799 800 801 802 803 804 805
	func(has_logical_ring_contexts); \
	func(has_overlay); \
	func(has_pipe_cxsr); \
	func(has_pooled_eu); \
	func(has_psr); \
	func(has_rc6); \
	func(has_rc6p); \
	func(has_resource_streamer); \
	func(has_runtime_pm); \
806
	func(has_snoop); \
807 808 809
	func(cursor_needs_physical); \
	func(hws_needs_physical); \
	func(overlay_needs_physical); \
810
	func(supports_tv);
D
Daniel Vetter 已提交
811

812
struct sseu_dev_info {
813
	u8 slice_mask;
814
	u8 subslice_mask;
815 816
	u8 eu_total;
	u8 eu_per_subslice;
817 818 819 820 821 822
	u8 min_eu_in_pool;
	/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
	u8 subslice_7eu[3];
	u8 has_slice_pg:1;
	u8 has_subslice_pg:1;
	u8 has_eu_pg:1;
823 824
};

825 826 827 828 829
static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
{
	return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
}

830 831 832 833 834 835 836 837 838 839 840 841 842
/* Keep in gen based order, and chronological order within a gen */
enum intel_platform {
	INTEL_PLATFORM_UNINITIALIZED = 0,
	INTEL_I830,
	INTEL_I845G,
	INTEL_I85X,
	INTEL_I865G,
	INTEL_I915G,
	INTEL_I915GM,
	INTEL_I945G,
	INTEL_I945GM,
	INTEL_G33,
	INTEL_PINEVIEW,
843 844
	INTEL_I965G,
	INTEL_I965GM,
845 846
	INTEL_G45,
	INTEL_GM45,
847 848 849 850 851 852 853 854 855 856 857 858 859
	INTEL_IRONLAKE,
	INTEL_SANDYBRIDGE,
	INTEL_IVYBRIDGE,
	INTEL_VALLEYVIEW,
	INTEL_HASWELL,
	INTEL_BROADWELL,
	INTEL_CHERRYVIEW,
	INTEL_SKYLAKE,
	INTEL_BROXTON,
	INTEL_KABYLAKE,
	INTEL_GEMINILAKE,
};

860
struct intel_device_info {
861
	u32 display_mmio_offset;
862
	u16 device_id;
863
	u8 num_pipes;
864
	u8 num_sprites[I915_MAX_PIPES];
865
	u8 num_scalers[I915_MAX_PIPES];
866
	u8 gen;
867
	u16 gen_mask;
868
	enum intel_platform platform;
869
	u8 ring_mask; /* Rings supported by the HW */
870
	u8 num_rings;
871 872 873
#define DEFINE_FLAG(name) u8 name:1
	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
#undef DEFINE_FLAG
874
	u16 ddb_size; /* in blocks */
875 876 877 878
	/* Register offsets for the various display pipes and transcoders */
	int pipe_offsets[I915_MAX_TRANSCODERS];
	int trans_offsets[I915_MAX_TRANSCODERS];
	int palette_offsets[I915_MAX_PIPES];
879
	int cursor_offsets[I915_MAX_PIPES];
880 881

	/* Slice/subslice/EU info */
882
	struct sseu_dev_info sseu;
883 884 885 886 887

	struct color_luts {
		u16 degamma_lut_size;
		u16 gamma_lut_size;
	} color;
888 889
};

890 891 892 893 894
struct intel_display_error_state;

struct drm_i915_error_state {
	struct kref ref;
	struct timeval time;
895 896
	struct timeval boottime;
	struct timeval uptime;
897

898 899
	struct drm_i915_private *i915;

900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923
	char error_msg[128];
	bool simulated;
	int iommu;
	u32 reset_count;
	u32 suspend_count;
	struct intel_device_info device_info;

	/* Generic register state */
	u32 eir;
	u32 pgtbl_er;
	u32 ier;
	u32 gtier[4];
	u32 ccid;
	u32 derrmr;
	u32 forcewake;
	u32 error; /* gen6+ */
	u32 err_int; /* gen7 */
	u32 fault_data0; /* gen8, gen9 */
	u32 fault_data1; /* gen8, gen9 */
	u32 done_reg;
	u32 gac_eco;
	u32 gam_ecochk;
	u32 gab_ctl;
	u32 gfx_mode;
924

925 926 927
	u64 fence[I915_MAX_NUM_FENCES];
	struct intel_overlay_error_state *overlay;
	struct intel_display_error_state *display;
928
	struct drm_i915_error_object *semaphore;
929
	struct drm_i915_error_object *guc_log;
930 931 932 933 934 935

	struct drm_i915_error_engine {
		int engine_id;
		/* Software tracked state */
		bool waiting;
		int num_waiters;
936 937
		unsigned long hangcheck_timestamp;
		bool hangcheck_stalled;
938 939 940 941
		enum intel_engine_hangcheck_action hangcheck_action;
		struct i915_address_space *vm;
		int num_requests;

942 943 944
		/* position of active request inside the ring */
		u32 rq_head, rq_post, rq_tail;

945 946 947 948 949 950 951 952 953 954 955
		/* our own tracking of ring head and tail */
		u32 cpu_ring_head;
		u32 cpu_ring_tail;

		u32 last_seqno;

		/* Register state */
		u32 start;
		u32 tail;
		u32 head;
		u32 ctl;
956
		u32 mode;
957 958 959 960 961 962 963 964 965 966 967 968 969
		u32 hws;
		u32 ipeir;
		u32 ipehr;
		u32 bbstate;
		u32 instpm;
		u32 instps;
		u32 seqno;
		u64 bbaddr;
		u64 acthd;
		u32 fault_reg;
		u64 faddr;
		u32 rc_psmi; /* sleep state */
		u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
970
		struct intel_instdone instdone;
971 972 973

		struct drm_i915_error_object {
			u64 gtt_offset;
974
			u64 gtt_size;
975 976
			int page_count;
			int unused;
977 978 979 980 981 982 983
			u32 *pages[0];
		} *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;

		struct drm_i915_error_object *wa_ctx;

		struct drm_i915_error_request {
			long jiffies;
984
			pid_t pid;
985
			u32 context;
986
			int ban_score;
987 988 989
			u32 seqno;
			u32 head;
			u32 tail;
990
		} *requests, execlist[2];
991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007

		struct drm_i915_error_waiter {
			char comm[TASK_COMM_LEN];
			pid_t pid;
			u32 seqno;
		} *waiters;

		struct {
			u32 gfx_mode;
			union {
				u64 pdp[4];
				u32 pp_dir_base;
			};
		} vm_info;

		pid_t pid;
		char comm[TASK_COMM_LEN];
1008
		int context_bans;
1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029
	} engine[I915_NUM_ENGINES];

	struct drm_i915_error_buffer {
		u32 size;
		u32 name;
		u32 rseqno[I915_NUM_ENGINES], wseqno;
		u64 gtt_offset;
		u32 read_domains;
		u32 write_domain;
		s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
		u32 tiling:2;
		u32 dirty:1;
		u32 purgeable:1;
		u32 userptr:1;
		s32 engine:4;
		u32 cache_level:3;
	} *active_bo[I915_NUM_ENGINES], *pinned_bo;
	u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
	struct i915_address_space *active_vm[I915_NUM_ENGINES];
};

1030 1031
enum i915_cache_level {
	I915_CACHE_NONE = 0,
1032 1033 1034 1035 1036
	I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
	I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
			      caches, eg sampler/render caches, and the
			      large Last-Level-Cache. LLC is coherent with
			      the CPU, but L3 is only visible to the GPU. */
1037
	I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
1038 1039
};

1040 1041
#define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */

1042 1043 1044 1045 1046
enum fb_op_origin {
	ORIGIN_GTT,
	ORIGIN_CPU,
	ORIGIN_CS,
	ORIGIN_FLIP,
1047
	ORIGIN_DIRTYFB,
1048 1049
};

1050
struct intel_fbc {
P
Paulo Zanoni 已提交
1051 1052 1053
	/* This is always the inner lock when overlapping with struct_mutex and
	 * it's the outer lock when overlapping with stolen_lock. */
	struct mutex lock;
B
Ben Widawsky 已提交
1054
	unsigned threshold;
1055 1056
	unsigned int possible_framebuffer_bits;
	unsigned int busy_bits;
1057
	unsigned int visible_pipes_mask;
1058
	struct intel_crtc *crtc;
1059

1060
	struct drm_mm_node compressed_fb;
1061 1062
	struct drm_mm_node *compressed_llb;

1063 1064
	bool false_color;

1065
	bool enabled;
1066
	bool active;
1067

1068 1069 1070
	bool underrun_detected;
	struct work_struct underrun_work;

1071
	struct intel_fbc_state_cache {
1072 1073
		struct i915_vma *vma;

1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086
		struct {
			unsigned int mode_flags;
			uint32_t hsw_bdw_pixel_rate;
		} crtc;

		struct {
			unsigned int rotation;
			int src_w;
			int src_h;
			bool visible;
		} plane;

		struct {
1087
			const struct drm_format_info *format;
1088 1089 1090 1091
			unsigned int stride;
		} fb;
	} state_cache;

1092
	struct intel_fbc_reg_params {
1093 1094
		struct i915_vma *vma;

1095 1096 1097 1098 1099 1100 1101
		struct {
			enum pipe pipe;
			enum plane plane;
			unsigned int fence_y_offset;
		} crtc;

		struct {
1102
			const struct drm_format_info *format;
1103 1104 1105 1106 1107 1108
			unsigned int stride;
		} fb;

		int cfb_size;
	} params;

1109
	struct intel_fbc_work {
1110
		bool scheduled;
1111
		u32 scheduled_vblank;
1112 1113
		struct work_struct work;
	} work;
1114

1115
	const char *no_fbc_reason;
1116 1117
};

1118
/*
1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132
 * HIGH_RR is the highest eDP panel refresh rate read from EDID
 * LOW_RR is the lowest eDP panel refresh rate found from EDID
 * parsing for same resolution.
 */
enum drrs_refresh_rate_type {
	DRRS_HIGH_RR,
	DRRS_LOW_RR,
	DRRS_MAX_RR, /* RR count */
};

enum drrs_support_type {
	DRRS_NOT_SUPPORTED = 0,
	STATIC_DRRS_SUPPORT = 1,
	SEAMLESS_DRRS_SUPPORT = 2
1133 1134
};

1135
struct intel_dp;
1136 1137 1138 1139 1140 1141 1142 1143 1144
struct i915_drrs {
	struct mutex mutex;
	struct delayed_work work;
	struct intel_dp *dp;
	unsigned busy_frontbuffer_bits;
	enum drrs_refresh_rate_type refresh_rate_type;
	enum drrs_support_type type;
};

R
Rodrigo Vivi 已提交
1145
struct i915_psr {
1146
	struct mutex lock;
R
Rodrigo Vivi 已提交
1147 1148
	bool sink_support;
	bool source_ok;
1149
	struct intel_dp *enabled;
1150 1151
	bool active;
	struct delayed_work work;
1152
	unsigned busy_frontbuffer_bits;
1153 1154
	bool psr2_support;
	bool aux_frame_sync;
1155
	bool link_standby;
1156 1157
	bool y_cord_support;
	bool colorimetry_support;
1158
	bool alpm;
1159
};
1160

1161
enum intel_pch {
1162
	PCH_NONE = 0,	/* No PCH present */
1163 1164
	PCH_IBX,	/* Ibexpeak PCH */
	PCH_CPT,	/* Cougarpoint PCH */
1165
	PCH_LPT,	/* Lynxpoint PCH */
1166
	PCH_SPT,        /* Sunrisepoint PCH */
1167
	PCH_KBP,        /* Kabypoint PCH */
B
Ben Widawsky 已提交
1168
	PCH_NOP,
1169 1170
};

1171 1172 1173 1174 1175
enum intel_sbi_destination {
	SBI_ICLK,
	SBI_MPHY,
};

1176
#define QUIRK_PIPEA_FORCE (1<<0)
1177
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
1178
#define QUIRK_INVERT_BRIGHTNESS (1<<2)
1179
#define QUIRK_BACKLIGHT_PRESENT (1<<3)
1180
#define QUIRK_PIPEB_FORCE (1<<4)
1181
#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1182

1183
struct intel_fbdev;
1184
struct intel_fbc_work;
1185

1186 1187
struct intel_gmbus {
	struct i2c_adapter adapter;
1188
#define GMBUS_FORCE_BIT_RETRY (1U << 31)
1189
	u32 force_bit;
1190
	u32 reg0;
1191
	i915_reg_t gpio_reg;
1192
	struct i2c_algo_bit_data bit_algo;
1193 1194 1195
	struct drm_i915_private *dev_priv;
};

1196
struct i915_suspend_saved_registers {
1197
	u32 saveDSPARB;
J
Jesse Barnes 已提交
1198
	u32 saveFBC_CONTROL;
1199 1200
	u32 saveCACHE_MODE_0;
	u32 saveMI_ARB_STATE;
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Jesse Barnes 已提交
1201 1202
	u32 saveSWF0[16];
	u32 saveSWF1[16];
1203
	u32 saveSWF3[3];
1204
	uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1205
	u32 savePCH_PORT_HOTPLUG;
1206
	u16 saveGCDGMBUS;
1207
};
1208

1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266
struct vlv_s0ix_state {
	/* GAM */
	u32 wr_watermark;
	u32 gfx_prio_ctrl;
	u32 arb_mode;
	u32 gfx_pend_tlb0;
	u32 gfx_pend_tlb1;
	u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
	u32 media_max_req_count;
	u32 gfx_max_req_count;
	u32 render_hwsp;
	u32 ecochk;
	u32 bsd_hwsp;
	u32 blt_hwsp;
	u32 tlb_rd_addr;

	/* MBC */
	u32 g3dctl;
	u32 gsckgctl;
	u32 mbctl;

	/* GCP */
	u32 ucgctl1;
	u32 ucgctl3;
	u32 rcgctl1;
	u32 rcgctl2;
	u32 rstctl;
	u32 misccpctl;

	/* GPM */
	u32 gfxpause;
	u32 rpdeuhwtc;
	u32 rpdeuc;
	u32 ecobus;
	u32 pwrdwnupctl;
	u32 rp_down_timeout;
	u32 rp_deucsw;
	u32 rcubmabdtmr;
	u32 rcedata;
	u32 spare2gh;

	/* Display 1 CZ domain */
	u32 gt_imr;
	u32 gt_ier;
	u32 pm_imr;
	u32 pm_ier;
	u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];

	/* GT SA CZ domain */
	u32 tilectl;
	u32 gt_fifoctl;
	u32 gtlc_wake_ctrl;
	u32 gtlc_survive;
	u32 pmwgicz;

	/* Display 2 CZ domain */
	u32 gu_ctl0;
	u32 gu_ctl1;
1267
	u32 pcbr;
1268 1269 1270
	u32 clock_gate_dis2;
};

1271 1272 1273 1274
struct intel_rps_ei {
	u32 cz_clock;
	u32 render_c0;
	u32 media_c0;
1275 1276
};

1277
struct intel_gen6_power_mgmt {
I
Imre Deak 已提交
1278 1279 1280 1281
	/*
	 * work, interrupts_enabled and pm_iir are protected by
	 * dev_priv->irq_lock
	 */
1282
	struct work_struct work;
I
Imre Deak 已提交
1283
	bool interrupts_enabled;
1284
	u32 pm_iir;
1285

1286
	/* PM interrupt bits that should never be masked */
1287 1288
	u32 pm_intr_keep;

1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303
	/* Frequencies are stored in potentially platform dependent multiples.
	 * In other words, *_freq needs to be multiplied by X to be interesting.
	 * Soft limits are those which are used for the dynamic reclocking done
	 * by the driver (raise frequencies under heavy loads, and lower for
	 * lighter loads). Hard limits are those imposed by the hardware.
	 *
	 * A distinction is made for overclocking, which is never enabled by
	 * default, and is considered to be above the hard limit if it's
	 * possible at all.
	 */
	u8 cur_freq;		/* Current frequency (cached, may not == HW) */
	u8 min_freq_softlimit;	/* Minimum frequency permitted by the driver */
	u8 max_freq_softlimit;	/* Max frequency permitted by the driver */
	u8 max_freq;		/* Maximum frequency, RP0 if not overclocking */
	u8 min_freq;		/* AKA RPn. Minimum frequency */
1304
	u8 boost_freq;		/* Frequency to request when wait boosting */
1305
	u8 idle_freq;		/* Frequency to request when we are idle */
1306 1307 1308
	u8 efficient_freq;	/* AKA RPe. Pre-determined balanced frequency */
	u8 rp1_freq;		/* "less than" RP0 power/freqency */
	u8 rp0_freq;		/* Non-overclocked max frequency. */
1309
	u16 gpll_ref_freq;	/* vlv/chv GPLL reference frequency */
1310

1311 1312 1313
	u8 up_threshold; /* Current %busy required to uplock */
	u8 down_threshold; /* Current %busy required to downclock */

1314 1315 1316
	int last_adj;
	enum { LOW_POWER, BETWEEN, HIGH_POWER } power;

1317 1318 1319 1320
	spinlock_t client_lock;
	struct list_head clients;
	bool client_boost;

1321
	bool enabled;
1322
	struct delayed_work autoenable_work;
1323
	unsigned boosts;
1324

1325 1326 1327
	/* manual wa residency calculations */
	struct intel_rps_ei up_ei, down_ei;

1328 1329
	/*
	 * Protects RPS/RC6 register access and PCU communication.
1330 1331 1332
	 * Must be taken after struct_mutex if nested. Note that
	 * this lock may be held for long periods of time when
	 * talking to hw - so only take it when talking to hw!
1333 1334
	 */
	struct mutex hw_lock;
1335 1336
};

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Daniel Vetter 已提交
1337 1338 1339
/* defined intel_pm.c */
extern spinlock_t mchdev_lock;

1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350
struct intel_ilk_power_mgmt {
	u8 cur_delay;
	u8 min_delay;
	u8 max_delay;
	u8 fmax;
	u8 fstart;

	u64 last_count1;
	unsigned long last_time1;
	unsigned long chipset_power;
	u64 last_count2;
1351
	u64 last_time2;
1352 1353 1354 1355 1356 1357 1358
	unsigned long gfx_power;
	u8 corr;

	int c_m;
	int r_t;
};

1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388
struct drm_i915_private;
struct i915_power_well;

struct i915_power_well_ops {
	/*
	 * Synchronize the well's hw state to match the current sw state, for
	 * example enable/disable it based on the current refcount. Called
	 * during driver init and resume time, possibly after first calling
	 * the enable/disable handlers.
	 */
	void (*sync_hw)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/*
	 * Enable the well and resources that depend on it (for example
	 * interrupts located on the well). Called after the 0->1 refcount
	 * transition.
	 */
	void (*enable)(struct drm_i915_private *dev_priv,
		       struct i915_power_well *power_well);
	/*
	 * Disable the well and resources that depend on it. Called after
	 * the 1->0 refcount transition.
	 */
	void (*disable)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/* Returns the hw enabled state. */
	bool (*is_enabled)(struct drm_i915_private *dev_priv,
			   struct i915_power_well *power_well);
};

1389 1390
/* Power well structure for haswell */
struct i915_power_well {
1391
	const char *name;
1392
	bool always_on;
1393 1394
	/* power well enable/disable usage count */
	int count;
1395 1396
	/* cached hw enabled state */
	bool hw_enabled;
1397
	unsigned long domains;
1398 1399
	/* unique identifier for this power well */
	unsigned long id;
1400 1401 1402 1403 1404
	/*
	 * Arbitraty data associated with this power well. Platform and power
	 * well specific.
	 */
	unsigned long data;
1405
	const struct i915_power_well_ops *ops;
1406 1407
};

1408
struct i915_power_domains {
1409 1410 1411 1412 1413
	/*
	 * Power wells needed for initialization at driver init and suspend
	 * time are on. They are kept on until after the first modeset.
	 */
	bool init_power_on;
1414
	bool initializing;
1415
	int power_well_count;
1416

1417
	struct mutex lock;
1418
	int domain_use_count[POWER_DOMAIN_NUM];
1419
	struct i915_power_well *power_wells;
1420 1421
};

1422
#define MAX_L3_SLICES 2
1423
struct intel_l3_parity {
1424
	u32 *remap_info[MAX_L3_SLICES];
1425
	struct work_struct error_work;
1426
	int which_slice;
1427 1428
};

1429 1430 1431
struct i915_gem_mm {
	/** Memory allocator for GTT stolen memory */
	struct drm_mm stolen;
1432 1433 1434 1435
	/** Protects the usage of the GTT stolen memory allocator. This is
	 * always the inner lock when overlapping with struct_mutex. */
	struct mutex stolen_lock;

1436 1437 1438 1439 1440
	/** List of all objects in gtt_space. Used to restore gtt
	 * mappings on resume */
	struct list_head bound_list;
	/**
	 * List of objects which are not bound to the GTT (thus
1441 1442
	 * are idle and not used by the GPU). These objects may or may
	 * not actually have any pages attached.
1443 1444 1445
	 */
	struct list_head unbound_list;

1446 1447 1448 1449 1450
	/** List of all objects in gtt_space, currently mmaped by userspace.
	 * All objects within this list must also be on bound_list.
	 */
	struct list_head userfault_list;

1451 1452 1453 1454 1455 1456
	/**
	 * List of objects which are pending destruction.
	 */
	struct llist_head free_list;
	struct work_struct free_work;

1457
	/** Usable portion of the GTT for GEM */
1458
	phys_addr_t stolen_base; /* limited to low memory (32-bit) */
1459 1460 1461 1462

	/** PPGTT used for aliasing the PPGTT with the GTT */
	struct i915_hw_ppgtt *aliasing_ppgtt;

1463
	struct notifier_block oom_notifier;
1464
	struct notifier_block vmap_notifier;
1465
	struct shrinker shrinker;
1466 1467 1468 1469 1470 1471 1472 1473 1474 1475

	/** LRU list of objects with fence regs on them. */
	struct list_head fence_list;

	/**
	 * Are we in a non-interruptible section of code like
	 * modesetting?
	 */
	bool interruptible;

1476
	/* the indicator for dispatch video commands on two BSD rings */
1477
	atomic_t bsd_engine_dispatch_index;
1478

1479 1480 1481 1482 1483 1484
	/** Bit 6 swizzling required for X tiling */
	uint32_t bit_6_swizzle_x;
	/** Bit 6 swizzling required for Y tiling */
	uint32_t bit_6_swizzle_y;

	/* accounting, useful for userland debugging */
1485
	spinlock_t object_stat_lock;
1486
	u64 object_memory;
1487 1488 1489
	u32 object_count;
};

1490
struct drm_i915_error_state_buf {
1491
	struct drm_i915_private *i915;
1492 1493 1494 1495 1496 1497 1498 1499
	unsigned bytes;
	unsigned size;
	int err;
	u8 *buf;
	loff_t start;
	loff_t pos;
};

1500
struct i915_error_state_file_priv {
1501
	struct drm_i915_private *i915;
1502 1503 1504
	struct drm_i915_error_state *error;
};

1505 1506 1507
#define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
#define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */

1508 1509 1510
#define I915_ENGINE_DEAD_TIMEOUT  (4 * HZ)  /* Seqno, head and subunits dead */
#define I915_SEQNO_DEAD_TIMEOUT   (12 * HZ) /* Seqno dead with active head */

1511 1512 1513 1514
struct i915_gpu_error {
	/* For hangcheck timer */
#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1515

1516
	struct delayed_work hangcheck_work;
1517 1518 1519 1520 1521

	/* For reset and error_state handling. */
	spinlock_t lock;
	/* Protected by the above dev->gpu_error.lock. */
	struct drm_i915_error_state *first_error;
1522 1523 1524

	unsigned long missed_irq_rings;

1525
	/**
M
Mika Kuoppala 已提交
1526
	 * State variable controlling the reset flow and count
1527
	 *
M
Mika Kuoppala 已提交
1528
	 * This is a counter which gets incremented when reset is triggered,
1529 1530 1531 1532
	 *
	 * Before the reset commences, the I915_RESET_IN_PROGRESS bit is set
	 * meaning that any waiters holding onto the struct_mutex should
	 * relinquish the lock immediately in order for the reset to start.
M
Mika Kuoppala 已提交
1533 1534 1535 1536 1537 1538 1539 1540 1541
	 *
	 * If reset is not completed succesfully, the I915_WEDGE bit is
	 * set meaning that hardware is terminally sour and there is no
	 * recovery. All waiters on the reset_queue will be woken when
	 * that happens.
	 *
	 * This counter is used by the wait_seqno code to notice that reset
	 * event happened and it needs to restart the entire ioctl (since most
	 * likely the seqno it waited for won't ever signal anytime soon).
1542 1543 1544 1545
	 *
	 * This is important for lock-free wait paths, where no contended lock
	 * naturally enforces the correct ordering between the bail-out of the
	 * waiter and the gpu reset work code.
1546
	 */
1547
	unsigned long reset_count;
1548

1549 1550 1551
	unsigned long flags;
#define I915_RESET_IN_PROGRESS	0
#define I915_WEDGED		(BITS_PER_LONG - 1)
1552

1553 1554 1555 1556 1557 1558
	/**
	 * Waitqueue to signal when a hang is detected. Used to for waiters
	 * to release the struct_mutex for the reset to procede.
	 */
	wait_queue_head_t wait_queue;

1559 1560 1561 1562 1563
	/**
	 * Waitqueue to signal when the reset has completed. Used by clients
	 * that wait for dev_priv->mm.wedged to settle.
	 */
	wait_queue_head_t reset_queue;
1564

1565
	/* For missed irq/seqno simulation. */
1566
	unsigned long test_irq_rings;
1567 1568
};

1569 1570 1571 1572 1573 1574
enum modeset_restore {
	MODESET_ON_LID_OPEN,
	MODESET_DONE,
	MODESET_SUSPENDED,
};

1575 1576 1577 1578 1579
#define DP_AUX_A 0x40
#define DP_AUX_B 0x10
#define DP_AUX_C 0x20
#define DP_AUX_D 0x30

X
Xiong Zhang 已提交
1580 1581 1582 1583
#define DDC_PIN_B  0x05
#define DDC_PIN_C  0x04
#define DDC_PIN_D  0x06

1584
struct ddi_vbt_port_info {
1585 1586 1587 1588 1589 1590
	/*
	 * This is an index in the HDMI/DVI DDI buffer translation table.
	 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
	 * populate this field.
	 */
#define HDMI_LEVEL_SHIFT_UNKNOWN	0xff
1591
	uint8_t hdmi_level_shift;
1592 1593 1594 1595

	uint8_t supports_dvi:1;
	uint8_t supports_hdmi:1;
	uint8_t supports_dp:1;
1596
	uint8_t supports_edp:1;
1597 1598

	uint8_t alternate_aux_channel;
X
Xiong Zhang 已提交
1599
	uint8_t alternate_ddc_pin;
1600 1601 1602

	uint8_t dp_boost_level;
	uint8_t hdmi_boost_level;
1603 1604
};

R
Rodrigo Vivi 已提交
1605 1606 1607 1608 1609
enum psr_lines_to_wait {
	PSR_0_LINES_TO_WAIT = 0,
	PSR_1_LINE_TO_WAIT,
	PSR_4_LINES_TO_WAIT,
	PSR_8_LINES_TO_WAIT
1610 1611
};

1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623
struct intel_vbt_data {
	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */

	/* Feature bits */
	unsigned int int_tv_support:1;
	unsigned int lvds_dither:1;
	unsigned int lvds_vbt:1;
	unsigned int int_crt_support:1;
	unsigned int lvds_use_ssc:1;
	unsigned int display_clock_mode:1;
	unsigned int fdi_rx_polarity_inverted:1;
1624
	unsigned int panel_type:4;
1625 1626 1627
	int lvds_ssc_freq;
	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */

1628 1629
	enum drrs_support_type drrs_type;

1630 1631 1632 1633 1634
	struct {
		int rate;
		int lanes;
		int preemphasis;
		int vswing;
1635
		bool low_vswing;
1636 1637 1638 1639 1640
		bool initialized;
		bool support;
		int bpp;
		struct edp_power_seq pps;
	} edp;
1641

R
Rodrigo Vivi 已提交
1642 1643 1644 1645 1646 1647 1648 1649 1650
	struct {
		bool full_link;
		bool require_aux_wakeup;
		int idle_frames;
		enum psr_lines_to_wait lines_to_wait;
		int tp1_wakeup_time;
		int tp2_tp3_wakeup_time;
	} psr;

1651 1652
	struct {
		u16 pwm_freq_hz;
1653
		bool present;
1654
		bool active_low_pwm;
1655
		u8 min_brightness;	/* min_brightness/255 of max */
1656
		u8 controller;		/* brightness controller number */
1657
		enum intel_backlight_type type;
1658 1659
	} backlight;

1660 1661 1662
	/* MIPI DSI */
	struct {
		u16 panel_id;
1663 1664 1665 1666 1667
		struct mipi_config *config;
		struct mipi_pps_data *pps;
		u8 seq_version;
		u32 size;
		u8 *data;
1668
		const u8 *sequence[MIPI_SEQ_MAX];
1669 1670
	} dsi;

1671 1672 1673
	int crt_ddc_pin;

	int child_dev_num;
1674
	union child_device_config *child_dev;
1675 1676

	struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1677
	struct sdvo_device_mapping sdvo_mappings[2];
1678 1679
};

1680 1681 1682 1683 1684
enum intel_ddb_partitioning {
	INTEL_DDB_PART_1_2,
	INTEL_DDB_PART_5_6, /* IVB+ */
};

1685 1686 1687 1688 1689 1690 1691 1692
struct intel_wm_level {
	bool enable;
	uint32_t pri_val;
	uint32_t spr_val;
	uint32_t cur_val;
	uint32_t fbc_val;
};

1693
struct ilk_wm_values {
1694 1695 1696 1697 1698 1699 1700 1701
	uint32_t wm_pipe[3];
	uint32_t wm_lp[3];
	uint32_t wm_lp_spr[3];
	uint32_t wm_linetime[3];
	bool enable_fbc_wm;
	enum intel_ddb_partitioning partitioning;
};

1702
struct vlv_pipe_wm {
1703
	uint16_t plane[I915_MAX_PLANES];
1704
};
1705

1706 1707
struct vlv_sr_wm {
	uint16_t plane;
1708 1709 1710 1711 1712
	uint16_t cursor;
};

struct vlv_wm_ddl_values {
	uint8_t plane[I915_MAX_PLANES];
1713
};
1714

1715 1716 1717
struct vlv_wm_values {
	struct vlv_pipe_wm pipe[3];
	struct vlv_sr_wm sr;
1718
	struct vlv_wm_ddl_values ddl[3];
1719 1720
	uint8_t level;
	bool cxsr;
1721 1722
};

1723
struct skl_ddb_entry {
1724
	uint16_t start, end;	/* in number of blocks, 'end' is exclusive */
1725 1726 1727 1728
};

static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
{
1729
	return entry->end - entry->start;
1730 1731
}

1732 1733 1734 1735 1736 1737 1738 1739 1740
static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
				       const struct skl_ddb_entry *e2)
{
	if (e1->start == e2->start && e1->end == e2->end)
		return true;

	return false;
}

1741
struct skl_ddb_allocation {
1742
	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1743
	struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1744 1745
};

1746
struct skl_wm_values {
1747
	unsigned dirty_pipes;
1748
	struct skl_ddb_allocation ddb;
1749 1750 1751
};

struct skl_wm_level {
L
Lyude 已提交
1752 1753 1754
	bool plane_en;
	uint16_t plane_res_b;
	uint8_t plane_res_l;
1755 1756
};

1757
/*
1758 1759 1760 1761
 * This struct helps tracking the state needed for runtime PM, which puts the
 * device in PCI D3 state. Notice that when this happens, nothing on the
 * graphics device works, even register access, so we don't get interrupts nor
 * anything else.
1762
 *
1763 1764 1765
 * Every piece of our code that needs to actually touch the hardware needs to
 * either call intel_runtime_pm_get or call intel_display_power_get with the
 * appropriate power domain.
1766
 *
1767 1768
 * Our driver uses the autosuspend delay feature, which means we'll only really
 * suspend if we stay with zero refcount for a certain amount of time. The
1769
 * default value is currently very conservative (see intel_runtime_pm_enable), but
1770
 * it can be changed with the standard runtime PM files from sysfs.
1771 1772 1773 1774 1775
 *
 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
 * goes back to false exactly before we reenable the IRQs. We use this variable
 * to check if someone is trying to enable/disable IRQs while they're supposed
 * to be disabled. This shouldn't happen and we'll print some error messages in
1776
 * case it happens.
1777
 *
1778
 * For more, read the Documentation/power/runtime_pm.txt.
1779
 */
1780
struct i915_runtime_pm {
1781
	atomic_t wakeref_count;
1782
	bool suspended;
1783
	bool irqs_enabled;
1784 1785
};

1786 1787 1788 1789 1790
enum intel_pipe_crc_source {
	INTEL_PIPE_CRC_SOURCE_NONE,
	INTEL_PIPE_CRC_SOURCE_PLANE1,
	INTEL_PIPE_CRC_SOURCE_PLANE2,
	INTEL_PIPE_CRC_SOURCE_PF,
1791
	INTEL_PIPE_CRC_SOURCE_PIPE,
D
Daniel Vetter 已提交
1792 1793 1794 1795 1796
	/* TV/DP on pre-gen5/vlv can't use the pipe source. */
	INTEL_PIPE_CRC_SOURCE_TV,
	INTEL_PIPE_CRC_SOURCE_DP_B,
	INTEL_PIPE_CRC_SOURCE_DP_C,
	INTEL_PIPE_CRC_SOURCE_DP_D,
1797
	INTEL_PIPE_CRC_SOURCE_AUTO,
1798 1799 1800
	INTEL_PIPE_CRC_SOURCE_MAX,
};

1801
struct intel_pipe_crc_entry {
1802
	uint32_t frame;
1803 1804 1805
	uint32_t crc[5];
};

1806
#define INTEL_PIPE_CRC_ENTRIES_NR	128
1807
struct intel_pipe_crc {
1808 1809
	spinlock_t lock;
	bool opened;		/* exclusive access to the result file */
1810
	struct intel_pipe_crc_entry *entries;
1811
	enum intel_pipe_crc_source source;
1812
	int head, tail;
1813
	wait_queue_head_t wq;
T
Tomeu Vizoso 已提交
1814
	int skipped;
1815 1816
};

1817
struct i915_frontbuffer_tracking {
1818
	spinlock_t lock;
1819 1820 1821 1822 1823 1824 1825 1826 1827

	/*
	 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
	 * scheduled flips.
	 */
	unsigned busy_bits;
	unsigned flip_bits;
};

1828
struct i915_wa_reg {
1829
	i915_reg_t addr;
1830 1831 1832 1833 1834
	u32 value;
	/* bitmask representing WA bits */
	u32 mask;
};

1835 1836 1837 1838 1839 1840 1841
/*
 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
 * allowing it for RCS as we don't foresee any requirement of having
 * a whitelist for other engines. When it is really required for
 * other engines then the limit need to be increased.
 */
#define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1842 1843 1844 1845

struct i915_workarounds {
	struct i915_wa_reg reg[I915_MAX_WA_REGS];
	u32 count;
1846
	u32 hw_whitelist_count[I915_NUM_ENGINES];
1847 1848
};

1849 1850 1851 1852
struct i915_virtual_gpu {
	bool active;
};

1853 1854 1855 1856 1857 1858 1859
/* used in computing the new watermarks state */
struct intel_wm_config {
	unsigned int num_pipes_active;
	bool sprites_enabled;
	bool sprites_scaled;
};

1860 1861 1862 1863 1864
struct i915_oa_format {
	u32 format;
	int size;
};

1865 1866 1867 1868 1869
struct i915_oa_reg {
	i915_reg_t addr;
	u32 value;
};

1870 1871
struct i915_perf_stream;

1872 1873 1874
/**
 * struct i915_perf_stream_ops - the OPs to support a specific stream type
 */
1875
struct i915_perf_stream_ops {
1876 1877 1878 1879
	/**
	 * @enable: Enables the collection of HW samples, either in response to
	 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
	 * without `I915_PERF_FLAG_DISABLED`.
1880 1881 1882
	 */
	void (*enable)(struct i915_perf_stream *stream);

1883 1884 1885 1886
	/**
	 * @disable: Disables the collection of HW samples, either in response
	 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
	 * the stream.
1887 1888 1889
	 */
	void (*disable)(struct i915_perf_stream *stream);

1890 1891
	/**
	 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1892 1893 1894 1895 1896 1897
	 * once there is something ready to read() for the stream
	 */
	void (*poll_wait)(struct i915_perf_stream *stream,
			  struct file *file,
			  poll_table *wait);

1898 1899 1900
	/**
	 * @wait_unlocked: For handling a blocking read, wait until there is
	 * something to ready to read() for the stream. E.g. wait on the same
1901
	 * wait queue that would be passed to poll_wait().
1902 1903 1904
	 */
	int (*wait_unlocked)(struct i915_perf_stream *stream);

1905 1906 1907 1908 1909 1910 1911
	/**
	 * @read: Copy buffered metrics as records to userspace
	 * **buf**: the userspace, destination buffer
	 * **count**: the number of bytes to copy, requested by userspace
	 * **offset**: zero at the start of the read, updated as the read
	 * proceeds, it represents how many bytes have been copied so far and
	 * the buffer offset for copying the next record.
1912
	 *
1913 1914
	 * Copy as many buffered i915 perf samples and records for this stream
	 * to userspace as will fit in the given buffer.
1915
	 *
1916 1917
	 * Only write complete records; returning -%ENOSPC if there isn't room
	 * for a complete record.
1918
	 *
1919 1920 1921
	 * Return any error condition that results in a short read such as
	 * -%ENOSPC or -%EFAULT, even though these may be squashed before
	 * returning to userspace.
1922 1923 1924 1925 1926 1927
	 */
	int (*read)(struct i915_perf_stream *stream,
		    char __user *buf,
		    size_t count,
		    size_t *offset);

1928 1929
	/**
	 * @destroy: Cleanup any stream specific resources.
1930 1931 1932 1933 1934 1935
	 *
	 * The stream will always be disabled before this is called.
	 */
	void (*destroy)(struct i915_perf_stream *stream);
};

1936 1937 1938
/**
 * struct i915_perf_stream - state for a single open stream FD
 */
1939
struct i915_perf_stream {
1940 1941 1942
	/**
	 * @dev_priv: i915 drm device
	 */
1943 1944
	struct drm_i915_private *dev_priv;

1945 1946 1947
	/**
	 * @link: Links the stream into ``&drm_i915_private->streams``
	 */
1948 1949
	struct list_head link;

1950 1951 1952 1953 1954
	/**
	 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
	 * properties given when opening a stream, representing the contents
	 * of a single sample as read() by userspace.
	 */
1955
	u32 sample_flags;
1956 1957 1958 1959 1960 1961

	/**
	 * @sample_size: Considering the configured contents of a sample
	 * combined with the required header size, this is the total size
	 * of a single sample record.
	 */
1962
	int sample_size;
1963

1964 1965 1966 1967
	/**
	 * @ctx: %NULL if measuring system-wide across all contexts or a
	 * specific context that is being monitored.
	 */
1968
	struct i915_gem_context *ctx;
1969 1970 1971 1972 1973 1974

	/**
	 * @enabled: Whether the stream is currently enabled, considering
	 * whether the stream was opened in a disabled state and based
	 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
	 */
1975 1976
	bool enabled;

1977 1978 1979 1980
	/**
	 * @ops: The callbacks providing the implementation of this specific
	 * type of configured stream.
	 */
1981 1982 1983
	const struct i915_perf_stream_ops *ops;
};

1984 1985 1986
/**
 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
 */
1987
struct i915_oa_ops {
1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002
	/**
	 * @init_oa_buffer: Resets the head and tail pointers of the
	 * circular buffer for periodic OA reports.
	 *
	 * Called when first opening a stream for OA metrics, but also may be
	 * called in response to an OA buffer overflow or other error
	 * condition.
	 *
	 * Note it may be necessary to clear the full OA buffer here as part of
	 * maintaining the invariable that new reports must be written to
	 * zeroed memory for us to be able to reliable detect if an expected
	 * report has not yet landed in memory.  (At least on Haswell the OA
	 * buffer tail pointer is not synchronized with reports being visible
	 * to the CPU)
	 */
2003
	void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
2004 2005 2006 2007 2008 2009 2010

	/**
	 * @enable_metric_set: Applies any MUX configuration to set up the
	 * Boolean and Custom (B/C) counters that are part of the counter
	 * reports being sampled. May apply system constraints such as
	 * disabling EU clock gating as required.
	 */
2011
	int (*enable_metric_set)(struct drm_i915_private *dev_priv);
2012 2013 2014 2015 2016

	/**
	 * @disable_metric_set: Remove system constraints associated with using
	 * the OA unit.
	 */
2017
	void (*disable_metric_set)(struct drm_i915_private *dev_priv);
2018 2019 2020 2021

	/**
	 * @oa_enable: Enable periodic sampling
	 */
2022
	void (*oa_enable)(struct drm_i915_private *dev_priv);
2023 2024 2025 2026

	/**
	 * @oa_disable: Disable periodic sampling
	 */
2027
	void (*oa_disable)(struct drm_i915_private *dev_priv);
2028 2029 2030 2031 2032

	/**
	 * @read: Copy data from the circular OA buffer into a given userspace
	 * buffer.
	 */
2033 2034 2035 2036
	int (*read)(struct i915_perf_stream *stream,
		    char __user *buf,
		    size_t count,
		    size_t *offset);
2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051

	/**
	 * @oa_buffer_is_empty: Check if OA buffer empty (false positives OK)
	 *
	 * This is either called via fops or the poll check hrtimer (atomic
	 * ctx) without any locks taken.
	 *
	 * It's safe to read OA config state here unlocked, assuming that this
	 * is only called while the stream is enabled, while the global OA
	 * configuration can't be modified.
	 *
	 * Efficiency is more important than avoiding some false positives
	 * here, which will be handled gracefully - likely resulting in an
	 * %EAGAIN error for userspace.
	 */
2052
	bool (*oa_buffer_is_empty)(struct drm_i915_private *dev_priv);
2053 2054
};

2055
struct drm_i915_private {
2056 2057
	struct drm_device drm;

2058
	struct kmem_cache *objects;
2059
	struct kmem_cache *vmas;
2060
	struct kmem_cache *requests;
2061
	struct kmem_cache *dependencies;
2062

2063
	const struct intel_device_info info;
2064 2065 2066 2067 2068

	int relative_constants_mode;

	void __iomem *regs;

2069
	struct intel_uncore uncore;
2070

2071 2072
	struct i915_virtual_gpu vgpu;

2073
	struct intel_gvt *gvt;
2074

2075
	struct intel_huc huc;
2076 2077
	struct intel_guc guc;

2078 2079
	struct intel_csr csr;

2080
	struct intel_gmbus gmbus[GMBUS_NUM_PINS];
2081

2082 2083 2084 2085 2086 2087 2088 2089 2090
	/** gmbus_mutex protects against concurrent usage of the single hw gmbus
	 * controller on different i2c buses. */
	struct mutex gmbus_mutex;

	/**
	 * Base address of the gmbus and gpio block.
	 */
	uint32_t gpio_mmio_base;

2091 2092 2093
	/* MMIO base address for MIPI regs */
	uint32_t mipi_mmio_base;

2094 2095
	uint32_t psr_mmio_base;

2096 2097
	uint32_t pps_mmio_base;

2098 2099
	wait_queue_head_t gmbus_wait_queue;

2100
	struct pci_dev *bridge_dev;
2101
	struct i915_gem_context *kernel_context;
2102
	struct intel_engine_cs *engine[I915_NUM_ENGINES];
2103
	struct i915_vma *semaphore;
2104

2105
	struct drm_dma_handle *status_page_dmah;
2106 2107 2108 2109 2110
	struct resource mch_res;

	/* protects the irq masks */
	spinlock_t irq_lock;

2111 2112 2113
	/* protects the mmio flip data */
	spinlock_t mmio_flip_lock;

2114 2115
	bool display_irqs_enabled;

2116 2117 2118
	/* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
	struct pm_qos_request pm_qos;

V
Ville Syrjälä 已提交
2119 2120
	/* Sideband mailbox protection */
	struct mutex sb_lock;
2121 2122

	/** Cached value of IMR to avoid reads in updating the bitfield */
2123 2124 2125 2126
	union {
		u32 irq_mask;
		u32 de_irq_mask[I915_MAX_PIPES];
	};
2127
	u32 gt_irq_mask;
2128 2129
	u32 pm_imr;
	u32 pm_ier;
2130
	u32 pm_rps_events;
2131
	u32 pm_guc_events;
2132
	u32 pipestat_irq_mask[I915_MAX_PIPES];
2133

2134
	struct i915_hotplug hotplug;
2135
	struct intel_fbc fbc;
2136
	struct i915_drrs drrs;
2137
	struct intel_opregion opregion;
2138
	struct intel_vbt_data vbt;
2139

2140 2141
	bool preserve_bios_swizzle;

2142 2143 2144
	/* overlay */
	struct intel_overlay *overlay;

2145
	/* backlight registers and fields in struct intel_panel */
2146
	struct mutex backlight_lock;
2147

2148 2149 2150
	/* LVDS info */
	bool no_aux_handshake;

V
Ville Syrjälä 已提交
2151 2152 2153
	/* protects panel power sequencer state */
	struct mutex pps_mutex;

2154 2155 2156 2157
	struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
	int num_fence_regs; /* 8 on pre-965, 16 otherwise */

	unsigned int fsb_freq, mem_freq, is_ddr3;
2158
	unsigned int skl_preferred_vco_freq;
2159 2160 2161 2162 2163 2164 2165 2166
	unsigned int cdclk_freq, max_cdclk_freq;

	/*
	 * For reading holding any crtc lock is sufficient,
	 * for writing must hold all of them.
	 */
	unsigned int atomic_cdclk_freq;

M
Mika Kahola 已提交
2167
	unsigned int max_dotclk_freq;
2168
	unsigned int rawclk_freq;
2169
	unsigned int hpll_freq;
2170
	unsigned int czclk_freq;
2171

2172
	struct {
2173
		unsigned int vco, ref;
2174 2175
	} cdclk_pll;

2176 2177 2178 2179 2180 2181 2182
	/**
	 * wq - Driver workqueue for GEM.
	 *
	 * NOTE: Work items scheduled here are not allowed to grab any modeset
	 * locks, for otherwise the flushing done in the pageflip code will
	 * result in deadlocks.
	 */
2183 2184 2185 2186 2187 2188 2189
	struct workqueue_struct *wq;

	/* Display functions */
	struct drm_i915_display_funcs display;

	/* PCH chipset type */
	enum intel_pch pch_type;
2190
	unsigned short pch_id;
2191 2192 2193

	unsigned long quirks;

2194 2195
	enum modeset_restore modeset_restore;
	struct mutex modeset_restore_lock;
2196
	struct drm_atomic_state *modeset_restore_state;
2197
	struct drm_modeset_acquire_ctx reset_ctx;
2198

2199
	struct list_head vm_list; /* Global list of all address spaces */
2200
	struct i915_ggtt ggtt; /* VM representing the global address space */
B
Ben Widawsky 已提交
2201

2202
	struct i915_gem_mm mm;
2203 2204
	DECLARE_HASHTABLE(mm_structs, 7);
	struct mutex mm_lock;
2205

2206 2207 2208 2209 2210 2211 2212
	/* The hw wants to have a stable context identifier for the lifetime
	 * of the context (for OA, PASID, faults, etc). This is limited
	 * in execlists to 21 bits.
	 */
	struct ida context_hw_ida;
#define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */

2213 2214
	/* Kernel Modesetting */

2215 2216
	struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
	struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
2217 2218
	wait_queue_head_t pending_flip_queue;

2219 2220 2221 2222
#ifdef CONFIG_DEBUG_FS
	struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
#endif

2223
	/* dpll and cdclk state is protected by connection_mutex */
D
Daniel Vetter 已提交
2224 2225
	int num_shared_dpll;
	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
2226
	const struct intel_dpll_mgr *dpll_mgr;
2227

2228 2229 2230 2231 2232 2233 2234
	/*
	 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
	 * Must be global rather than per dpll, because on some platforms
	 * plls share registers.
	 */
	struct mutex dpll_lock;

2235 2236 2237
	unsigned int active_crtcs;
	unsigned int min_pixclk[I915_MAX_PIPES];

2238
	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
2239

2240
	struct i915_workarounds workarounds;
2241

2242 2243
	struct i915_frontbuffer_tracking fb_tracking;

2244 2245 2246 2247 2248
	struct intel_atomic_helper {
		struct llist_head free_list;
		struct work_struct free_work;
	} atomic_helper;

2249
	u16 orig_clock;
2250

2251
	bool mchbar_need_disable;
2252

2253 2254
	struct intel_l3_parity l3_parity;

B
Ben Widawsky 已提交
2255
	/* Cannot be determined by PCIID. You must always read a register. */
2256
	u32 edram_cap;
B
Ben Widawsky 已提交
2257

2258
	/* gen6+ rps state */
2259
	struct intel_gen6_power_mgmt rps;
2260

2261 2262
	/* ilk-only ips/rps state. Everything in here is protected by the global
	 * mchdev_lock in intel_pm.c */
2263
	struct intel_ilk_power_mgmt ips;
2264

2265
	struct i915_power_domains power_domains;
2266

R
Rodrigo Vivi 已提交
2267
	struct i915_psr psr;
2268

2269
	struct i915_gpu_error gpu_error;
2270

2271 2272
	struct drm_i915_gem_object *vlv_pctx;

2273
#ifdef CONFIG_DRM_FBDEV_EMULATION
2274 2275
	/* list of fbdev register on this device */
	struct intel_fbdev *fbdev;
2276
	struct work_struct fbdev_suspend_work;
2277
#endif
2278 2279

	struct drm_property *broadcast_rgb_property;
2280
	struct drm_property *force_audio_property;
2281

I
Imre Deak 已提交
2282
	/* hda/i915 audio component */
2283
	struct i915_audio_component *audio_component;
I
Imre Deak 已提交
2284
	bool audio_component_registered;
2285 2286 2287 2288 2289
	/**
	 * av_mutex - mutex for audio/video sync
	 *
	 */
	struct mutex av_mutex;
I
Imre Deak 已提交
2290

2291
	uint32_t hw_context_size;
2292
	struct list_head context_list;
2293

2294
	u32 fdi_rx_config;
2295

2296
	/* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2297
	u32 chv_phy_control;
2298 2299 2300 2301 2302 2303
	/*
	 * Shadows for CHV DPLL_MD regs to keep the state
	 * checker somewhat working in the presence hardware
	 * crappiness (can't read out DPLL_MD for pipes B & C).
	 */
	u32 chv_dpll_md[I915_MAX_PIPES];
2304
	u32 bxt_phy_grc;
2305

2306
	u32 suspend_count;
2307
	bool suspended_to_idle;
2308
	struct i915_suspend_saved_registers regfile;
2309
	struct vlv_s0ix_state vlv_s0ix_state;
2310

2311
	enum {
2312 2313 2314 2315 2316
		I915_SAGV_UNKNOWN = 0,
		I915_SAGV_DISABLED,
		I915_SAGV_ENABLED,
		I915_SAGV_NOT_CONTROLLED
	} sagv_status;
2317

2318
	struct {
2319 2320 2321
		/* protects DSPARB registers on pre-g4x/vlv/chv */
		spinlock_t dsparb_lock;

2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332
		/*
		 * Raw watermark latency values:
		 * in 0.1us units for WM0,
		 * in 0.5us units for WM1+.
		 */
		/* primary */
		uint16_t pri_latency[5];
		/* sprite */
		uint16_t spr_latency[5];
		/* cursor */
		uint16_t cur_latency[5];
2333 2334 2335 2336 2337 2338
		/*
		 * Raw watermark memory latency values
		 * for SKL for all 8 levels
		 * in 1us units.
		 */
		uint16_t skl_latency[8];
2339 2340

		/* current hardware state */
2341 2342 2343
		union {
			struct ilk_wm_values hw;
			struct skl_wm_values skl_hw;
2344
			struct vlv_wm_values vlv;
2345
		};
2346 2347

		uint8_t max_level;
2348 2349 2350 2351 2352 2353 2354

		/*
		 * Should be held around atomic WM register writing; also
		 * protects * intel_crtc->wm.active and
		 * cstate->wm.need_postvbl_update.
		 */
		struct mutex wm_mutex;
2355 2356 2357 2358 2359 2360 2361

		/*
		 * Set during HW readout of watermarks/DDB.  Some platforms
		 * need to know when we're still using BIOS-provided values
		 * (which we don't fully trust).
		 */
		bool distrust_bios_wm;
2362 2363
	} wm;

2364 2365
	struct i915_runtime_pm pm;

2366 2367
	struct {
		bool initialized;
2368

2369
		struct kobject *metrics_kobj;
2370
		struct ctl_table_header *sysctl_header;
2371

2372 2373
		struct mutex lock;
		struct list_head streams;
2374

2375 2376
		spinlock_t hook_lock;

2377
		struct {
2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392
			struct i915_perf_stream *exclusive_stream;

			u32 specific_ctx_id;

			struct hrtimer poll_check_timer;
			wait_queue_head_t poll_wq;
			bool pollin;

			bool periodic;
			int period_exponent;
			int timestamp_frequency;

			int tail_margin;

			int metrics_set;
2393 2394 2395 2396 2397

			const struct i915_oa_reg *mux_regs;
			int mux_regs_len;
			const struct i915_oa_reg *b_counter_regs;
			int b_counter_regs_len;
2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410

			struct {
				struct i915_vma *vma;
				u8 *vaddr;
				int format;
				int format_size;
			} oa_buffer;

			u32 gen7_latched_oastatus1;

			struct i915_oa_ops ops;
			const struct i915_oa_format *oa_formats;
			int n_builtin_sets;
2411
		} oa;
2412 2413
	} perf;

2414 2415
	/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
	struct {
2416
		void (*resume)(struct drm_i915_private *);
2417
		void (*cleanup_engine)(struct intel_engine_cs *engine);
2418

2419 2420
		struct list_head timelines;
		struct i915_gem_timeline global_timeline;
2421
		u32 active_requests;
2422

2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448
		/**
		 * Is the GPU currently considered idle, or busy executing
		 * userspace requests? Whilst idle, we allow runtime power
		 * management to power down the hardware and display clocks.
		 * In order to reduce the effect on performance, there
		 * is a slight delay before we do so.
		 */
		bool awake;

		/**
		 * We leave the user IRQ off as much as possible,
		 * but this means that requests will finish and never
		 * be retired once the system goes idle. Set a timer to
		 * fire periodically while the ring is running. When it
		 * fires, go retire requests.
		 */
		struct delayed_work retire_work;

		/**
		 * When we detect an idle GPU, we want to turn on
		 * powersaving features. So once we see that there
		 * are no more requests outstanding and no more
		 * arrive within a small period of time, we fire
		 * off the idle_work.
		 */
		struct delayed_work idle_work;
2449 2450

		ktime_t last_init_time;
2451 2452
	} gt;

2453 2454 2455
	/* perform PHY state sanity checks? */
	bool chv_phy_assert[2];

M
Mahesh Kumar 已提交
2456 2457
	bool ipc_enabled;

2458 2459
	/* Used to save the pipe-to-encoder mapping for audio */
	struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2460

2461 2462 2463 2464
	/*
	 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
	 * will be rejected. Instead look for a better place.
	 */
2465
};
L
Linus Torvalds 已提交
2466

2467 2468
static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
{
2469
	return container_of(dev, struct drm_i915_private, drm);
2470 2471
}

2472
static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
I
Imre Deak 已提交
2473
{
2474
	return to_i915(dev_get_drvdata(kdev));
I
Imre Deak 已提交
2475 2476
}

2477 2478 2479 2480 2481
static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
{
	return container_of(guc, struct drm_i915_private, guc);
}

2482
/* Simple iterator over all initialised engines */
2483 2484 2485 2486 2487
#define for_each_engine(engine__, dev_priv__, id__) \
	for ((id__) = 0; \
	     (id__) < I915_NUM_ENGINES; \
	     (id__)++) \
		for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2488

2489 2490 2491 2492 2493 2494
#define __mask_next_bit(mask) ({					\
	int __idx = ffs(mask) - 1;					\
	mask &= ~BIT(__idx);						\
	__idx;								\
})

2495
/* Iterator over subset of engines selected by mask */
2496 2497
#define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
	for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask;	\
2498
	     tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2499

2500 2501 2502 2503 2504 2505 2506
enum hdmi_force_audio {
	HDMI_AUDIO_OFF_DVI = -2,	/* no aux data for HDMI-DVI converter */
	HDMI_AUDIO_OFF,			/* force turn off HDMI audio */
	HDMI_AUDIO_AUTO,		/* trust EDID */
	HDMI_AUDIO_ON,			/* force turn on HDMI audio */
};

2507
#define I915_GTT_OFFSET_NONE ((u32)-1)
2508

2509 2510
/*
 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2511
 * considered to be the frontbuffer for the given plane interface-wise. This
2512 2513 2514 2515 2516
 * doesn't mean that the hw necessarily already scans it out, but that any
 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
 *
 * We have one bit per pipe and per scanout plane type.
 */
2517 2518
#define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2519 2520 2521
#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
	(1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
#define INTEL_FRONTBUFFER_CURSOR(pipe) \
2522 2523 2524
	(1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
#define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
	(1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2525
#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2526
	(1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2527
#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2528
	(0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2529

2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555
/*
 * Optimised SGL iterator for GEM objects
 */
static __always_inline struct sgt_iter {
	struct scatterlist *sgp;
	union {
		unsigned long pfn;
		dma_addr_t dma;
	};
	unsigned int curr;
	unsigned int max;
} __sgt_iter(struct scatterlist *sgl, bool dma) {
	struct sgt_iter s = { .sgp = sgl };

	if (s.sgp) {
		s.max = s.curr = s.sgp->offset;
		s.max += s.sgp->length;
		if (dma)
			s.dma = sg_dma_address(s.sgp);
		else
			s.pfn = page_to_pfn(sg_page(s.sgp));
	}

	return s;
}

2556 2557 2558 2559 2560 2561 2562 2563
static inline struct scatterlist *____sg_next(struct scatterlist *sg)
{
	++sg;
	if (unlikely(sg_is_chain(sg)))
		sg = sg_chain_ptr(sg);
	return sg;
}

2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577
/**
 * __sg_next - return the next scatterlist entry in a list
 * @sg:		The current sg entry
 *
 * Description:
 *   If the entry is the last, return NULL; otherwise, step to the next
 *   element in the array (@sg@+1). If that's a chain pointer, follow it;
 *   otherwise just return the pointer to the current element.
 **/
static inline struct scatterlist *__sg_next(struct scatterlist *sg)
{
#ifdef CONFIG_DEBUG_SG
	BUG_ON(sg->sg_magic != SG_MAGIC);
#endif
2578
	return sg_is_last(sg) ? NULL : ____sg_next(sg);
2579 2580
}

2581 2582 2583 2584 2585 2586 2587 2588 2589 2590
/**
 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
 * @__dmap:	DMA address (output)
 * @__iter:	'struct sgt_iter' (iterator state, internal)
 * @__sgt:	sg_table to iterate over (input)
 */
#define for_each_sgt_dma(__dmap, __iter, __sgt)				\
	for ((__iter) = __sgt_iter((__sgt)->sgl, true);			\
	     ((__dmap) = (__iter).dma + (__iter).curr);			\
	     (((__iter).curr += PAGE_SIZE) < (__iter).max) ||		\
2591
	     ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603

/**
 * for_each_sgt_page - iterate over the pages of the given sg_table
 * @__pp:	page pointer (output)
 * @__iter:	'struct sgt_iter' (iterator state, internal)
 * @__sgt:	sg_table to iterate over (input)
 */
#define for_each_sgt_page(__pp, __iter, __sgt)				\
	for ((__iter) = __sgt_iter((__sgt)->sgl, false);		\
	     ((__pp) = (__iter).pfn == 0 ? NULL :			\
	      pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
	     (((__iter).curr += PAGE_SIZE) < (__iter).max) ||		\
2604
	     ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2605

2606 2607 2608 2609 2610 2611 2612
static inline const struct intel_device_info *
intel_info(const struct drm_i915_private *dev_priv)
{
	return &dev_priv->info;
}

#define INTEL_INFO(dev_priv)	intel_info((dev_priv))
2613

2614
#define INTEL_GEN(dev_priv)	((dev_priv)->info.gen)
2615
#define INTEL_DEVID(dev_priv)	((dev_priv)->info.device_id)
2616

2617
#define REVID_FOREVER		0xff
2618
#define INTEL_REVID(dev_priv)	((dev_priv)->drm.pdev->revision)
2619 2620 2621 2622 2623 2624 2625

#define GEN_FOREVER (0)
/*
 * Returns true if Gen is in inclusive range [Start, End].
 *
 * Use GEN_FOREVER for unbound start and or end.
 */
2626
#define IS_GEN(dev_priv, s, e) ({ \
2627 2628 2629 2630 2631 2632 2633 2634 2635
	unsigned int __s = (s), __e = (e); \
	BUILD_BUG_ON(!__builtin_constant_p(s)); \
	BUILD_BUG_ON(!__builtin_constant_p(e)); \
	if ((__s) != GEN_FOREVER) \
		__s = (s) - 1; \
	if ((__e) == GEN_FOREVER) \
		__e = BITS_PER_LONG - 1; \
	else \
		__e = (e) - 1; \
2636
	!!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
2637 2638
})

2639 2640 2641 2642 2643 2644 2645 2646
/*
 * Return true if revision is in range [since,until] inclusive.
 *
 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
 */
#define IS_REVID(p, since, until) \
	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))

2647 2648
#define IS_I830(dev_priv)	((dev_priv)->info.platform == INTEL_I830)
#define IS_I845G(dev_priv)	((dev_priv)->info.platform == INTEL_I845G)
2649
#define IS_I85X(dev_priv)	((dev_priv)->info.platform == INTEL_I85X)
2650
#define IS_I865G(dev_priv)	((dev_priv)->info.platform == INTEL_I865G)
2651
#define IS_I915G(dev_priv)	((dev_priv)->info.platform == INTEL_I915G)
2652 2653
#define IS_I915GM(dev_priv)	((dev_priv)->info.platform == INTEL_I915GM)
#define IS_I945G(dev_priv)	((dev_priv)->info.platform == INTEL_I945G)
2654
#define IS_I945GM(dev_priv)	((dev_priv)->info.platform == INTEL_I945GM)
2655 2656
#define IS_I965G(dev_priv)	((dev_priv)->info.platform == INTEL_I965G)
#define IS_I965GM(dev_priv)	((dev_priv)->info.platform == INTEL_I965GM)
2657 2658 2659
#define IS_G45(dev_priv)	((dev_priv)->info.platform == INTEL_G45)
#define IS_GM45(dev_priv)	((dev_priv)->info.platform == INTEL_GM45)
#define IS_G4X(dev_priv)	(IS_G45(dev_priv) || IS_GM45(dev_priv))
2660 2661
#define IS_PINEVIEW_G(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa001)
#define IS_PINEVIEW_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa011)
2662
#define IS_PINEVIEW(dev_priv)	((dev_priv)->info.platform == INTEL_PINEVIEW)
2663
#define IS_G33(dev_priv)	((dev_priv)->info.platform == INTEL_G33)
2664
#define IS_IRONLAKE_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0046)
2665
#define IS_IVYBRIDGE(dev_priv)	((dev_priv)->info.platform == INTEL_IVYBRIDGE)
2666 2667 2668
#define IS_IVB_GT1(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0156 || \
				 INTEL_DEVID(dev_priv) == 0x0152 || \
				 INTEL_DEVID(dev_priv) == 0x015a)
2669 2670 2671 2672 2673 2674 2675 2676
#define IS_VALLEYVIEW(dev_priv)	((dev_priv)->info.platform == INTEL_VALLEYVIEW)
#define IS_CHERRYVIEW(dev_priv)	((dev_priv)->info.platform == INTEL_CHERRYVIEW)
#define IS_HASWELL(dev_priv)	((dev_priv)->info.platform == INTEL_HASWELL)
#define IS_BROADWELL(dev_priv)	((dev_priv)->info.platform == INTEL_BROADWELL)
#define IS_SKYLAKE(dev_priv)	((dev_priv)->info.platform == INTEL_SKYLAKE)
#define IS_BROXTON(dev_priv)	((dev_priv)->info.platform == INTEL_BROXTON)
#define IS_KABYLAKE(dev_priv)	((dev_priv)->info.platform == INTEL_KABYLAKE)
#define IS_GEMINILAKE(dev_priv)	((dev_priv)->info.platform == INTEL_GEMINILAKE)
2677
#define IS_MOBILE(dev_priv)	((dev_priv)->info.is_mobile)
2678 2679 2680 2681 2682 2683
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv)	(IS_BROADWELL(dev_priv) && \
				 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 ||	\
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xb ||	\
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
V
Ville Syrjälä 已提交
2684
/* ULX machines are also considered ULT. */
2685 2686 2687 2688 2689 2690 2691 2692
#define IS_BDW_ULX(dev_priv)	(IS_BROADWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
#define IS_BDW_GT3(dev_priv)	(IS_BROADWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
#define IS_HSW_ULT(dev_priv)	(IS_HASWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
#define IS_HSW_GT3(dev_priv)	(IS_HASWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2693
/* ULX machines are also considered ULT. */
2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712 2713 2714 2715
#define IS_HSW_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0A0E || \
				 INTEL_DEVID(dev_priv) == 0x0A1E)
#define IS_SKL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x1906 || \
				 INTEL_DEVID(dev_priv) == 0x1913 || \
				 INTEL_DEVID(dev_priv) == 0x1916 || \
				 INTEL_DEVID(dev_priv) == 0x1921 || \
				 INTEL_DEVID(dev_priv) == 0x1926)
#define IS_SKL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x190E || \
				 INTEL_DEVID(dev_priv) == 0x1915 || \
				 INTEL_DEVID(dev_priv) == 0x191E)
#define IS_KBL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x5906 || \
				 INTEL_DEVID(dev_priv) == 0x5913 || \
				 INTEL_DEVID(dev_priv) == 0x5916 || \
				 INTEL_DEVID(dev_priv) == 0x5921 || \
				 INTEL_DEVID(dev_priv) == 0x5926)
#define IS_KBL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x590E || \
				 INTEL_DEVID(dev_priv) == 0x5915 || \
				 INTEL_DEVID(dev_priv) == 0x591E)
#define IS_SKL_GT3(dev_priv)	(IS_SKYLAKE(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
#define IS_SKL_GT4(dev_priv)	(IS_SKYLAKE(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
2716

2717
#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2718

2719 2720 2721 2722 2723 2724
#define SKL_REVID_A0		0x0
#define SKL_REVID_B0		0x1
#define SKL_REVID_C0		0x2
#define SKL_REVID_D0		0x3
#define SKL_REVID_E0		0x4
#define SKL_REVID_F0		0x5
2725 2726
#define SKL_REVID_G0		0x6
#define SKL_REVID_H0		0x7
2727

2728 2729
#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))

2730
#define BXT_REVID_A0		0x0
2731
#define BXT_REVID_A1		0x1
2732
#define BXT_REVID_B0		0x3
2733
#define BXT_REVID_B_LAST	0x8
2734
#define BXT_REVID_C0		0x9
N
Nick Hoath 已提交
2735

2736 2737
#define IS_BXT_REVID(dev_priv, since, until) \
	(IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2738

M
Mika Kuoppala 已提交
2739 2740
#define KBL_REVID_A0		0x0
#define KBL_REVID_B0		0x1
2741 2742 2743
#define KBL_REVID_C0		0x2
#define KBL_REVID_D0		0x3
#define KBL_REVID_E0		0x4
M
Mika Kuoppala 已提交
2744

2745 2746
#define IS_KBL_REVID(dev_priv, since, until) \
	(IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
M
Mika Kuoppala 已提交
2747

2748 2749 2750 2751 2752 2753
/*
 * The genX designation typically refers to the render engine, so render
 * capability related checks should use IS_GEN, while display and other checks
 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
 * chips, etc.).
 */
2754 2755 2756 2757 2758 2759 2760 2761
#define IS_GEN2(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(1)))
#define IS_GEN3(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(2)))
#define IS_GEN4(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(3)))
#define IS_GEN5(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(4)))
#define IS_GEN6(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(5)))
#define IS_GEN7(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(6)))
#define IS_GEN8(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(7)))
#define IS_GEN9(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(8)))
2762

2763
#define IS_GEN9_LP(dev_priv)	(IS_GEN9(dev_priv) && INTEL_INFO(dev_priv)->is_lp)
2764
#define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
2765

2766 2767 2768 2769 2770 2771 2772 2773 2774
#define ENGINE_MASK(id)	BIT(id)
#define RENDER_RING	ENGINE_MASK(RCS)
#define BSD_RING	ENGINE_MASK(VCS)
#define BLT_RING	ENGINE_MASK(BCS)
#define VEBOX_RING	ENGINE_MASK(VECS)
#define BSD2_RING	ENGINE_MASK(VCS2)
#define ALL_ENGINES	(~0)

#define HAS_ENGINE(dev_priv, id) \
2775
	(!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2776 2777 2778 2779 2780 2781

#define HAS_BSD(dev_priv)	HAS_ENGINE(dev_priv, VCS)
#define HAS_BSD2(dev_priv)	HAS_ENGINE(dev_priv, VCS2)
#define HAS_BLT(dev_priv)	HAS_ENGINE(dev_priv, BCS)
#define HAS_VEBOX(dev_priv)	HAS_ENGINE(dev_priv, VECS)

2782 2783 2784
#define HAS_LLC(dev_priv)	((dev_priv)->info.has_llc)
#define HAS_SNOOP(dev_priv)	((dev_priv)->info.has_snoop)
#define HAS_EDRAM(dev_priv)	(!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2785 2786
#define HAS_WT(dev_priv)	((IS_HASWELL(dev_priv) || \
				 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2787

2788
#define HWS_NEEDS_PHYSICAL(dev_priv)	((dev_priv)->info.hws_needs_physical)
2789

2790 2791 2792 2793 2794 2795 2796 2797 2798 2799
#define HAS_HW_CONTEXTS(dev_priv)	    ((dev_priv)->info.has_hw_contexts)
#define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
		((dev_priv)->info.has_logical_ring_contexts)
#define USES_PPGTT(dev_priv)		(i915.enable_ppgtt)
#define USES_FULL_PPGTT(dev_priv)	(i915.enable_ppgtt >= 2)
#define USES_FULL_48BIT_PPGTT(dev_priv)	(i915.enable_ppgtt == 3)

#define HAS_OVERLAY(dev_priv)		 ((dev_priv)->info.has_overlay)
#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
		((dev_priv)->info.overlay_needs_physical)
2800

2801
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
2802
#define HAS_BROKEN_CS_TLB(dev_priv)	(IS_I830(dev_priv) || IS_I845G(dev_priv))
2803 2804

/* WaRsDisableCoarsePowerGating:skl,bxt */
2805 2806 2807 2808
#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
	(IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \
	 IS_SKL_GT3(dev_priv) || \
	 IS_SKL_GT4(dev_priv))
2809

2810 2811 2812 2813 2814 2815
/*
 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
 * even when in MSI mode. This results in spurious interrupt warnings if the
 * legacy irq no. is shared with another device. The kernel then disables that
 * interrupt source and so prevents the other device from working properly.
 */
2816 2817
#define HAS_AUX_IRQ(dev_priv)   ((dev_priv)->info.gen >= 5)
#define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
2818

2819 2820 2821
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 * rows, which changed the alignment requirements and fence programming.
 */
2822 2823 2824
#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
					 !(IS_I915G(dev_priv) || \
					 IS_I915GM(dev_priv)))
2825 2826
#define SUPPORTS_TV(dev_priv)		((dev_priv)->info.supports_tv)
#define I915_HAS_HOTPLUG(dev_priv)	((dev_priv)->info.has_hotplug)
2827

2828 2829 2830
#define HAS_FW_BLC(dev_priv) 	(INTEL_GEN(dev_priv) > 2)
#define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
#define HAS_FBC(dev_priv)	((dev_priv)->info.has_fbc)
2831

2832
#define HAS_IPS(dev_priv)	(IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2833

2834
#define HAS_DP_MST(dev_priv)	((dev_priv)->info.has_dp_mst)
2835

2836 2837 2838 2839 2840
#define HAS_DDI(dev_priv)		 ((dev_priv)->info.has_ddi)
#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
#define HAS_PSR(dev_priv)		 ((dev_priv)->info.has_psr)
#define HAS_RC6(dev_priv)		 ((dev_priv)->info.has_rc6)
#define HAS_RC6p(dev_priv)		 ((dev_priv)->info.has_rc6p)
P
Paulo Zanoni 已提交
2841

2842
#define HAS_CSR(dev_priv)	((dev_priv)->info.has_csr)
2843

2844
#define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2845 2846
#define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)

2847 2848 2849 2850 2851
/*
 * For now, anything with a GuC requires uCode loading, and then supports
 * command submission once loaded. But these are logically independent
 * properties, so we have separate macros to test them.
 */
2852 2853 2854
#define HAS_GUC(dev_priv)	((dev_priv)->info.has_guc)
#define HAS_GUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
#define HAS_GUC_SCHED(dev_priv)	(HAS_GUC(dev_priv))
2855
#define HAS_HUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
2856

2857
#define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2858

2859
#define HAS_POOLED_EU(dev_priv)	((dev_priv)->info.has_pooled_eu)
2860

2861 2862 2863 2864 2865 2866
#define INTEL_PCH_DEVICE_ID_MASK		0xff00
#define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
#define INTEL_PCH_PPT_DEVICE_ID_TYPE		0x1e00
#define INTEL_PCH_LPT_DEVICE_ID_TYPE		0x8c00
#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE		0x9c00
2867 2868
#define INTEL_PCH_SPT_DEVICE_ID_TYPE		0xA100
#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE		0x9D00
2869
#define INTEL_PCH_KBP_DEVICE_ID_TYPE		0xA200
2870
#define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
2871
#define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
2872
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
2873

2874 2875 2876 2877
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
#define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2878 2879 2880 2881
#define HAS_PCH_LPT_LP(dev_priv) \
	((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
#define HAS_PCH_LPT_H(dev_priv) \
	((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2882 2883 2884 2885
#define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
#define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2886

2887
#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2888

2889 2890
#define HAS_LSPCON(dev_priv) (IS_GEN9(dev_priv))

2891
/* DPF == dynamic parity feature */
2892
#define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2893 2894
#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
				 2 : HAS_L3_DPF(dev_priv))
2895

2896
#define GT_FREQUENCY_MULTIPLIER 50
A
Akash Goel 已提交
2897
#define GEN9_FREQ_SCALER 3
2898

2899 2900
#define HAS_DECOUPLED_MMIO(dev_priv) (INTEL_INFO(dev_priv)->has_decoupled_mmio)

2901 2902
#include "i915_trace.h"

2903 2904 2905 2906 2907 2908 2909 2910 2911
static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
{
#ifdef CONFIG_INTEL_IOMMU
	if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped)
		return true;
#endif
	return false;
}

2912
int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2913
				int enable_ppgtt);
2914

2915 2916
bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);

2917
/* i915_drv.c */
2918 2919 2920 2921 2922 2923 2924
void __printf(3, 4)
__i915_printk(struct drm_i915_private *dev_priv, const char *level,
	      const char *fmt, ...);

#define i915_report_error(dev_priv, fmt, ...)				   \
	__i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)

2925
#ifdef CONFIG_COMPAT
D
Dave Airlie 已提交
2926 2927
extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
			      unsigned long arg);
2928 2929
#else
#define i915_compat_ioctl NULL
2930
#endif
2931 2932 2933 2934 2935
extern const struct dev_pm_ops i915_pm_ops;

extern int i915_driver_load(struct pci_dev *pdev,
			    const struct pci_device_id *ent);
extern void i915_driver_unload(struct drm_device *dev);
2936 2937
extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2938
extern void i915_reset(struct drm_i915_private *dev_priv);
2939
extern int intel_guc_reset(struct drm_i915_private *dev_priv);
2940
extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2941
extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
2942 2943 2944 2945
extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2946
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2947

2948 2949 2950
int intel_engines_init_early(struct drm_i915_private *dev_priv);
int intel_engines_init(struct drm_i915_private *dev_priv);

2951
/* intel_hotplug.c */
2952 2953
void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
			   u32 pin_mask, u32 long_mask);
2954 2955 2956
void intel_hpd_init(struct drm_i915_private *dev_priv);
void intel_hpd_init_work(struct drm_i915_private *dev_priv);
void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2957
bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2958 2959
bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2960

L
Linus Torvalds 已提交
2961
/* i915_irq.c */
2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 2976 2977 2978
static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
{
	unsigned long delay;

	if (unlikely(!i915.enable_hangcheck))
		return;

	/* Don't continually defer the hangcheck so that it is always run at
	 * least once after work has been scheduled on any ring. Otherwise,
	 * we will ignore a hung ring if a second ring is kept busy.
	 */

	delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
	queue_delayed_work(system_long_wq,
			   &dev_priv->gpu_error.hangcheck_work, delay);
}

2979
__printf(3, 4)
2980 2981
void i915_handle_error(struct drm_i915_private *dev_priv,
		       u32 engine_mask,
2982
		       const char *fmt, ...);
L
Linus Torvalds 已提交
2983

2984
extern void intel_irq_init(struct drm_i915_private *dev_priv);
2985 2986
int intel_irq_install(struct drm_i915_private *dev_priv);
void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2987

2988 2989
extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
2990
					bool restore_forcewake);
2991
extern void intel_uncore_init(struct drm_i915_private *dev_priv);
2992
extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
2993
extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
2994 2995 2996
extern void intel_uncore_fini(struct drm_i915_private *dev_priv);
extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
					 bool restore);
2997
const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2998
void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2999
				enum forcewake_domains domains);
3000
void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
3001
				enum forcewake_domains domains);
3002 3003 3004 3005 3006 3007 3008
/* Like above but the caller must manage the uncore.lock itself.
 * Must be used with I915_READ_FW and friends.
 */
void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
					enum forcewake_domains domains);
void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
					enum forcewake_domains domains);
3009 3010
u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);

3011
void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
3012

3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023
int intel_wait_for_register(struct drm_i915_private *dev_priv,
			    i915_reg_t reg,
			    const u32 mask,
			    const u32 value,
			    const unsigned long timeout_ms);
int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
			       i915_reg_t reg,
			       const u32 mask,
			       const u32 value,
			       const unsigned long timeout_ms);

3024 3025
static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
{
3026
	return dev_priv->gvt;
3027 3028
}

3029
static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
3030
{
3031
	return dev_priv->vgpu.active;
3032
}
3033

3034
void
3035
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3036
		     u32 status_mask);
3037 3038

void
3039
i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3040
		      u32 status_mask);
3041

3042 3043
void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
3044 3045 3046
void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
				   uint32_t mask,
				   uint32_t bits);
3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057 3058 3059
void ilk_update_display_irq(struct drm_i915_private *dev_priv,
			    uint32_t interrupt_mask,
			    uint32_t enabled_irq_mask);
static inline void
ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, bits);
}
static inline void
ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, 0);
}
3060 3061 3062 3063 3064 3065 3066 3067 3068 3069 3070 3071 3072 3073
void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
			 enum pipe pipe,
			 uint32_t interrupt_mask,
			 uint32_t enabled_irq_mask);
static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
				       enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
}
static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
					enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
}
3074 3075 3076
void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
				  uint32_t interrupt_mask,
				  uint32_t enabled_irq_mask);
3077 3078 3079 3080 3081 3082 3083 3084 3085 3086 3087
static inline void
ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, bits);
}
static inline void
ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, 0);
}

3088 3089 3090 3091 3092 3093 3094 3095 3096
/* i915_gem.c */
int i915_gem_create_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3097 3098
int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3099 3100 3101 3102 3103 3104
int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
			     struct drm_file *file_priv);
int i915_gem_execbuffer(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
J
Jesse Barnes 已提交
3105 3106
int i915_gem_execbuffer2(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
3107 3108
int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
B
Ben Widawsky 已提交
3109 3110 3111 3112
int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
3113 3114
int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *file_priv);
3115 3116
int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
3117 3118 3119 3120
int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
3121
void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
3122 3123
int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file);
3124 3125
int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
3126 3127
int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3128
void i915_gem_sanitize(struct drm_i915_private *i915);
3129 3130
int i915_gem_load_init(struct drm_i915_private *dev_priv);
void i915_gem_load_cleanup(struct drm_i915_private *dev_priv);
3131
void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3132
int i915_gem_freeze(struct drm_i915_private *dev_priv);
3133 3134
int i915_gem_freeze_late(struct drm_i915_private *dev_priv);

3135
void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
3136
void i915_gem_object_free(struct drm_i915_gem_object *obj);
3137 3138
void i915_gem_object_init(struct drm_i915_gem_object *obj,
			 const struct drm_i915_gem_object_ops *ops);
3139 3140 3141 3142 3143
struct drm_i915_gem_object *
i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
struct drm_i915_gem_object *
i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
				 const void *data, size_t size);
3144
void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
3145
void i915_gem_free_object(struct drm_gem_object *obj);
3146

3147 3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159
static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
{
	/* A single pass should suffice to release all the freed objects (along
	 * most call paths) , but be a little more paranoid in that freeing
	 * the objects does take a little amount of time, during which the rcu
	 * callbacks could have added new objects into the freed list, and
	 * armed the work again.
	 */
	do {
		rcu_barrier();
	} while (flush_work(&i915->mm.free_work));
}

C
Chris Wilson 已提交
3160
struct i915_vma * __must_check
3161 3162
i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
			 const struct i915_ggtt_view *view,
3163
			 u64 size,
3164 3165
			 u64 alignment,
			 u64 flags);
3166

3167
int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
3168
void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3169

3170 3171
void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);

C
Chris Wilson 已提交
3172
static inline int __sg_page_count(const struct scatterlist *sg)
3173
{
3174 3175
	return sg->length >> PAGE_SHIFT;
}
3176

3177 3178 3179
struct scatterlist *
i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
		       unsigned int n, unsigned int *offset);
3180

3181 3182 3183
struct page *
i915_gem_object_get_page(struct drm_i915_gem_object *obj,
			 unsigned int n);
3184

3185 3186 3187
struct page *
i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
			       unsigned int n);
3188

3189 3190 3191
dma_addr_t
i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
				unsigned long n);
3192

3193 3194
void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
				 struct sg_table *pages);
C
Chris Wilson 已提交
3195 3196 3197 3198 3199
int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);

static inline int __must_check
i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
{
3200
	might_lock(&obj->mm.lock);
C
Chris Wilson 已提交
3201

3202
	if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
C
Chris Wilson 已提交
3203 3204 3205 3206 3207 3208 3209
		return 0;

	return __i915_gem_object_get_pages(obj);
}

static inline void
__i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3210
{
C
Chris Wilson 已提交
3211 3212
	GEM_BUG_ON(!obj->mm.pages);

3213
	atomic_inc(&obj->mm.pages_pin_count);
C
Chris Wilson 已提交
3214 3215 3216 3217 3218
}

static inline bool
i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
{
3219
	return atomic_read(&obj->mm.pages_pin_count);
C
Chris Wilson 已提交
3220 3221 3222 3223 3224 3225 3226 3227
}

static inline void
__i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
{
	GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
	GEM_BUG_ON(!obj->mm.pages);

3228
	atomic_dec(&obj->mm.pages_pin_count);
3229
}
3230

3231 3232
static inline void
i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3233
{
C
Chris Wilson 已提交
3234
	__i915_gem_object_unpin_pages(obj);
3235 3236
}

3237 3238 3239 3240 3241 3242 3243
enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
	I915_MM_NORMAL = 0,
	I915_MM_SHRINKER
};

void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
				 enum i915_mm_subclass subclass);
3244
void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
C
Chris Wilson 已提交
3245

3246 3247 3248 3249 3250
enum i915_map_type {
	I915_MAP_WB = 0,
	I915_MAP_WC,
};

3251 3252
/**
 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3253 3254
 * @obj: the object to map into kernel address space
 * @type: the type of mapping, used to select pgprot_t
3255 3256 3257
 *
 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
 * pages and then returns a contiguous mapping of the backing storage into
3258 3259
 * the kernel address space. Based on the @type of mapping, the PTE will be
 * set to either WriteBack or WriteCombine (via pgprot_t).
3260
 *
3261 3262
 * The caller is responsible for calling i915_gem_object_unpin_map() when the
 * mapping is no longer required.
3263
 *
3264 3265
 * Returns the pointer through which to access the mapped object, or an
 * ERR_PTR() on error.
3266
 */
3267 3268
void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
					   enum i915_map_type type);
3269 3270 3271

/**
 * i915_gem_object_unpin_map - releases an earlier mapping
3272
 * @obj: the object to unmap
3273 3274 3275 3276 3277 3278 3279 3280 3281 3282 3283
 *
 * After pinning the object and mapping its pages, once you are finished
 * with your access, call i915_gem_object_unpin_map() to release the pin
 * upon the mapping. Once the pin count reaches zero, that mapping may be
 * removed.
 */
static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
{
	i915_gem_object_unpin_pages(obj);
}

3284 3285 3286 3287 3288 3289 3290 3291 3292 3293 3294 3295 3296 3297
int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
				    unsigned int *needs_clflush);
int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
				     unsigned int *needs_clflush);
#define CLFLUSH_BEFORE 0x1
#define CLFLUSH_AFTER 0x2
#define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)

static inline void
i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
{
	i915_gem_object_unpin_pages(obj);
}

3298
int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
B
Ben Widawsky 已提交
3299
void i915_vma_move_to_active(struct i915_vma *vma,
3300 3301
			     struct drm_i915_gem_request *req,
			     unsigned int flags);
3302 3303 3304
int i915_gem_dumb_create(struct drm_file *file_priv,
			 struct drm_device *dev,
			 struct drm_mode_create_dumb *args);
3305 3306
int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
		      uint32_t handle, uint64_t *offset);
3307
int i915_gem_mmap_gtt_version(void);
3308 3309 3310 3311 3312

void i915_gem_track_fb(struct drm_i915_gem_object *old,
		       struct drm_i915_gem_object *new,
		       unsigned frontbuffer_bits);

3313
int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3314

3315
struct drm_i915_gem_request *
3316
i915_gem_find_active_request(struct intel_engine_cs *engine);
3317

3318
void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3319

3320 3321
static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
{
3322
	return unlikely(test_bit(I915_RESET_IN_PROGRESS, &error->flags));
3323 3324
}

3325
static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3326
{
3327
	return unlikely(test_bit(I915_WEDGED, &error->flags));
3328 3329
}

3330
static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error)
3331
{
3332
	return i915_reset_in_progress(error) | i915_terminally_wedged(error);
M
Mika Kuoppala 已提交
3333 3334 3335 3336
}

static inline u32 i915_reset_count(struct i915_gpu_error *error)
{
3337
	return READ_ONCE(error->reset_count);
3338
}
3339

3340
int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
3341
void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
3342
void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3343
void i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3344
void i915_gem_init_mmio(struct drm_i915_private *i915);
3345 3346
int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3347
void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3348
void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3349
int __must_check i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3350
					unsigned int flags);
3351 3352
int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
void i915_gem_resume(struct drm_i915_private *dev_priv);
3353
int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3354 3355 3356 3357
int i915_gem_object_wait(struct drm_i915_gem_object *obj,
			 unsigned int flags,
			 long timeout,
			 struct intel_rps_client *rps);
3358 3359 3360 3361 3362
int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
				  unsigned int flags,
				  int priority);
#define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX

3363
int __must_check
3364 3365 3366
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
				  bool write);
int __must_check
3367
i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
C
Chris Wilson 已提交
3368
struct i915_vma * __must_check
3369 3370
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
				     u32 alignment,
3371
				     const struct i915_ggtt_view *view);
C
Chris Wilson 已提交
3372
void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3373
int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3374
				int align);
3375
int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3376
void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3377

3378 3379 3380
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
				    enum i915_cache_level cache_level);

3381 3382 3383 3384 3385 3386
struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
				struct dma_buf *dma_buf);

struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
				struct drm_gem_object *gem_obj, int flags);

3387 3388 3389 3390 3391 3392
static inline struct i915_hw_ppgtt *
i915_vm_to_ppgtt(struct i915_address_space *vm)
{
	return container_of(vm, struct i915_hw_ppgtt, base);
}

J
Joonas Lahtinen 已提交
3393
/* i915_gem_fence_reg.c */
3394 3395 3396
int __must_check i915_vma_get_fence(struct i915_vma *vma);
int __must_check i915_vma_put_fence(struct i915_vma *vma);

3397
void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
3398
void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3399

3400
void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3401 3402 3403 3404
void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
				       struct sg_table *pages);
void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
					 struct sg_table *pages);
3405

3406 3407 3408 3409 3410
static inline struct i915_gem_context *
i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
{
	struct i915_gem_context *ctx;

3411
	lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
3412 3413 3414 3415 3416 3417 3418 3419

	ctx = idr_find(&file_priv->context_idr, id);
	if (!ctx)
		return ERR_PTR(-ENOENT);

	return ctx;
}

3420 3421
static inline struct i915_gem_context *
i915_gem_context_get(struct i915_gem_context *ctx)
3422
{
3423
	kref_get(&ctx->ref);
3424
	return ctx;
3425 3426
}

3427
static inline void i915_gem_context_put(struct i915_gem_context *ctx)
3428
{
3429
	lockdep_assert_held(&ctx->i915->drm.struct_mutex);
3430
	kref_put(&ctx->ref, i915_gem_context_free);
3431 3432
}

3433 3434
static inline void i915_gem_context_put_unlocked(struct i915_gem_context *ctx)
{
3435 3436 3437 3438
	struct mutex *lock = &ctx->i915->drm.struct_mutex;

	if (kref_put_mutex(&ctx->ref, i915_gem_context_free, lock))
		mutex_unlock(lock);
3439 3440
}

C
Chris Wilson 已提交
3441 3442 3443 3444 3445 3446 3447 3448 3449 3450
static inline struct intel_timeline *
i915_gem_context_lookup_timeline(struct i915_gem_context *ctx,
				 struct intel_engine_cs *engine)
{
	struct i915_address_space *vm;

	vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base;
	return &vm->timeline.engine[engine->id];
}

3451 3452 3453
int i915_perf_open_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file);

3454
/* i915_gem_evict.c */
3455
int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3456
					  u64 min_size, u64 alignment,
3457
					  unsigned cache_level,
3458
					  u64 start, u64 end,
3459
					  unsigned flags);
3460 3461 3462
int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
					 struct drm_mm_node *node,
					 unsigned int flags);
3463
int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3464

3465
/* belongs in i915_gem_gtt.h */
3466
static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3467
{
3468
	wmb();
3469
	if (INTEL_GEN(dev_priv) < 6)
3470 3471
		intel_gtt_chipset_flush();
}
3472

3473
/* i915_gem_stolen.c */
3474 3475 3476
int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
				struct drm_mm_node *node, u64 size,
				unsigned alignment);
3477 3478 3479 3480
int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
					 struct drm_mm_node *node, u64 size,
					 unsigned alignment, u64 start,
					 u64 end);
3481 3482
void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
				 struct drm_mm_node *node);
3483
int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3484
void i915_gem_cleanup_stolen(struct drm_device *dev);
3485
struct drm_i915_gem_object *
3486
i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, u32 size);
3487
struct drm_i915_gem_object *
3488
i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3489 3490 3491
					       u32 stolen_offset,
					       u32 gtt_offset,
					       u32 size);
3492

3493 3494 3495
/* i915_gem_internal.c */
struct drm_i915_gem_object *
i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3496
				phys_addr_t size);
3497

3498 3499
/* i915_gem_shrinker.c */
unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3500
			      unsigned long target,
3501 3502 3503 3504
			      unsigned flags);
#define I915_SHRINK_PURGEABLE 0x1
#define I915_SHRINK_UNBOUND 0x2
#define I915_SHRINK_BOUND 0x4
3505
#define I915_SHRINK_ACTIVE 0x8
3506
#define I915_SHRINK_VMAPS 0x10
3507 3508
unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3509
void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3510 3511


3512
/* i915_gem_tiling.c */
3513
static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3514
{
3515
	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3516 3517

	return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3518
		i915_gem_object_is_tiled(obj);
3519 3520
}

3521 3522 3523 3524 3525
u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
			unsigned int tiling, unsigned int stride);
u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
			     unsigned int tiling, unsigned int stride);

3526
/* i915_debugfs.c */
3527
#ifdef CONFIG_DEBUG_FS
3528 3529
int i915_debugfs_register(struct drm_i915_private *dev_priv);
void i915_debugfs_unregister(struct drm_i915_private *dev_priv);
J
Jani Nikula 已提交
3530
int i915_debugfs_connector_add(struct drm_connector *connector);
3531
void intel_display_crc_init(struct drm_i915_private *dev_priv);
3532
#else
3533 3534
static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
static inline void i915_debugfs_unregister(struct drm_i915_private *dev_priv) {}
3535 3536
static inline int i915_debugfs_connector_add(struct drm_connector *connector)
{ return 0; }
3537
static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3538
#endif
3539 3540

/* i915_gpu_error.c */
3541 3542
#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)

3543 3544
__printf(2, 3)
void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3545 3546
int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
			    const struct i915_error_state_file_priv *error);
3547
int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3548
			      struct drm_i915_private *i915,
3549 3550 3551 3552 3553 3554
			      size_t count, loff_t pos);
static inline void i915_error_state_buf_release(
	struct drm_i915_error_state_buf *eb)
{
	kfree(eb->buf);
}
3555 3556
void i915_capture_error_state(struct drm_i915_private *dev_priv,
			      u32 engine_mask,
3557
			      const char *error_msg);
3558 3559 3560
void i915_error_state_get(struct drm_device *dev,
			  struct i915_error_state_file_priv *error_priv);
void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3561
void i915_destroy_error_state(struct drm_i915_private *dev_priv);
3562

3563 3564 3565 3566 3567 3568 3569 3570
#else

static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
					    u32 engine_mask,
					    const char *error_msg)
{
}

3571
static inline void i915_destroy_error_state(struct drm_i915_private *dev_priv)
3572 3573 3574 3575 3576
{
}

#endif

3577
const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3578

3579
/* i915_cmd_parser.c */
3580
int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3581
void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3582 3583 3584 3585 3586 3587 3588
void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
int intel_engine_cmd_parser(struct intel_engine_cs *engine,
			    struct drm_i915_gem_object *batch_obj,
			    struct drm_i915_gem_object *shadow_batch_obj,
			    u32 batch_start_offset,
			    u32 batch_len,
			    bool is_master);
3589

3590 3591 3592
/* i915_perf.c */
extern void i915_perf_init(struct drm_i915_private *dev_priv);
extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3593 3594
extern void i915_perf_register(struct drm_i915_private *dev_priv);
extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3595

3596
/* i915_suspend.c */
3597 3598
extern int i915_save_state(struct drm_i915_private *dev_priv);
extern int i915_restore_state(struct drm_i915_private *dev_priv);
3599

B
Ben Widawsky 已提交
3600
/* i915_sysfs.c */
D
David Weinehall 已提交
3601 3602
void i915_setup_sysfs(struct drm_i915_private *dev_priv);
void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
B
Ben Widawsky 已提交
3603

3604
/* intel_i2c.c */
3605 3606
extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3607 3608
extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
				     unsigned int pin);
3609

3610 3611
extern struct i2c_adapter *
intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
C
Chris Wilson 已提交
3612 3613
extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3614
static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3615 3616 3617
{
	return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
}
3618
extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3619

3620
/* intel_bios.c */
3621
int intel_bios_init(struct drm_i915_private *dev_priv);
J
Jani Nikula 已提交
3622
bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3623
bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3624
bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3625
bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3626
bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3627
bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3628
bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3629 3630
bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
				     enum port port);
3631 3632 3633
bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
				enum port port);

3634

3635
/* intel_opregion.c */
3636
#ifdef CONFIG_ACPI
3637
extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3638 3639
extern void intel_opregion_register(struct drm_i915_private *dev_priv);
extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3640
extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3641 3642
extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
					 bool enable);
3643
extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3644
					 pci_power_t state);
3645
extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3646
#else
3647
static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3648 3649
static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
3650 3651 3652
static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
{
}
3653 3654 3655 3656 3657
static inline int
intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
{
	return 0;
}
3658
static inline int
3659
intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3660 3661 3662
{
	return 0;
}
3663
static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3664 3665 3666
{
	return -ENODEV;
}
3667
#endif
3668

J
Jesse Barnes 已提交
3669 3670 3671 3672 3673 3674 3675 3676 3677
/* intel_acpi.c */
#ifdef CONFIG_ACPI
extern void intel_register_dsm_handler(void);
extern void intel_unregister_dsm_handler(void);
#else
static inline void intel_register_dsm_handler(void) { return; }
static inline void intel_unregister_dsm_handler(void) { return; }
#endif /* CONFIG_ACPI */

3678 3679 3680 3681 3682 3683 3684
/* intel_device_info.c */
static inline struct intel_device_info *
mkwrite_device_info(struct drm_i915_private *dev_priv)
{
	return (struct intel_device_info *)&dev_priv->info;
}

3685
const char *intel_platform_name(enum intel_platform platform);
3686 3687 3688
void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
void intel_device_info_dump(struct drm_i915_private *dev_priv);

J
Jesse Barnes 已提交
3689
/* modesetting */
3690
extern void intel_modeset_init_hw(struct drm_device *dev);
3691
extern int intel_modeset_init(struct drm_device *dev);
3692
extern void intel_modeset_gem_init(struct drm_device *dev);
J
Jesse Barnes 已提交
3693
extern void intel_modeset_cleanup(struct drm_device *dev);
3694
extern int intel_connector_register(struct drm_connector *);
3695
extern void intel_connector_unregister(struct drm_connector *);
3696 3697
extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
				       bool state);
3698
extern void intel_display_resume(struct drm_device *dev);
3699 3700
extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3701
extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3702
extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3703
extern void intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3704
extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3705
				  bool enable);
3706

B
Ben Widawsky 已提交
3707 3708
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file);
3709

3710
/* overlay */
3711 3712
extern struct intel_overlay_error_state *
intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3713 3714
extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
					    struct intel_overlay_error_state *error);
3715

3716 3717
extern struct intel_display_error_state *
intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3718
extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3719
					    struct drm_i915_private *dev_priv,
3720
					    struct intel_display_error_state *error);
3721

3722 3723
int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3724 3725
int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
		      u32 reply_mask, u32 reply, int timeout_base_ms);
3726 3727

/* intel_sideband.c */
3728 3729
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3730
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3731 3732
u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3733 3734 3735 3736
u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3737 3738
u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3739 3740
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3741 3742 3743 3744
u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
		   enum intel_sbi_destination destination);
void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
		     enum intel_sbi_destination destination);
3745 3746
u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3747

3748
/* intel_dpio_phy.c */
3749
void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3750
			     enum dpio_phy *phy, enum dpio_channel *ch);
3751 3752 3753
void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
				  enum port port, u32 margin, u32 scale,
				  u32 enable, u32 deemphasis);
3754 3755 3756 3757 3758 3759 3760 3761 3762 3763 3764 3765
void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
			    enum dpio_phy phy);
bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
			      enum dpio_phy phy);
uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
					     uint8_t lane_count);
void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
				     uint8_t lane_lat_optim_mask);
uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);

3766 3767 3768
void chv_set_phy_signal_level(struct intel_encoder *encoder,
			      u32 deemph_reg_value, u32 margin_reg_value,
			      bool uniq_trans_scale);
3769 3770
void chv_data_lane_soft_reset(struct intel_encoder *encoder,
			      bool reset);
3771
void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3772 3773
void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3774
void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3775

3776 3777 3778
void vlv_set_phy_signal_level(struct intel_encoder *encoder,
			      u32 demph_reg_value, u32 preemph_reg_value,
			      u32 uniqtranscale_reg_value, u32 tx3_demph);
3779
void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3780
void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3781
void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3782

3783 3784
int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3785

3786 3787 3788 3789 3790 3791 3792 3793 3794 3795 3796 3797 3798
#define I915_READ8(reg)		dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
#define I915_WRITE8(reg, val)	dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)

#define I915_READ16(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
#define I915_WRITE16(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
#define I915_READ16_NOTRACE(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
#define I915_WRITE16_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)

#define I915_READ(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
#define I915_WRITE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
#define I915_READ_NOTRACE(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
#define I915_WRITE_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)

3799 3800 3801 3802
/* Be very careful with read/write 64-bit values. On 32-bit machines, they
 * will be implemented using 2 32-bit writes in an arbitrary order with
 * an arbitrary delay between them. This can cause the hardware to
 * act upon the intermediate value, possibly leading to corruption and
3803 3804 3805 3806 3807 3808 3809 3810 3811
 * machine death. For this reason we do not support I915_WRITE64, or
 * dev_priv->uncore.funcs.mmio_writeq.
 *
 * When reading a 64-bit value as two 32-bit values, the delay may cause
 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
 * occasionally a 64-bit register does not actualy support a full readq
 * and must be read using two 32-bit reads.
 *
 * You have been warned.
3812
 */
3813
#define I915_READ64(reg)	dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3814

3815
#define I915_READ64_2x32(lower_reg, upper_reg) ({			\
3816 3817
	u32 upper, lower, old_upper, loop = 0;				\
	upper = I915_READ(upper_reg);					\
3818
	do {								\
3819
		old_upper = upper;					\
3820
		lower = I915_READ(lower_reg);				\
3821 3822
		upper = I915_READ(upper_reg);				\
	} while (upper != old_upper && loop++ < 2);			\
3823
	(u64)upper << 32 | lower; })
3824

3825 3826 3827
#define POSTING_READ(reg)	(void)I915_READ_NOTRACE(reg)
#define POSTING_READ16(reg)	(void)I915_READ16_NOTRACE(reg)

3828 3829
#define __raw_read(x, s) \
static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3830
					     i915_reg_t reg) \
3831
{ \
3832
	return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3833 3834 3835 3836
}

#define __raw_write(x, s) \
static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3837
				       i915_reg_t reg, uint##x##_t val) \
3838
{ \
3839
	write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3840 3841 3842 3843 3844 3845 3846 3847 3848 3849 3850 3851 3852 3853
}
__raw_read(8, b)
__raw_read(16, w)
__raw_read(32, l)
__raw_read(64, q)

__raw_write(8, b)
__raw_write(16, w)
__raw_write(32, l)
__raw_write(64, q)

#undef __raw_read
#undef __raw_write

3854
/* These are untraced mmio-accessors that are only valid to be used inside
3855
 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3856
 * controlled.
3857
 *
3858
 * Think twice, and think again, before using these.
3859 3860 3861 3862 3863 3864 3865 3866 3867 3868 3869 3870 3871 3872 3873 3874 3875 3876 3877 3878
 *
 * As an example, these accessors can possibly be used between:
 *
 * spin_lock_irq(&dev_priv->uncore.lock);
 * intel_uncore_forcewake_get__locked();
 *
 * and
 *
 * intel_uncore_forcewake_put__locked();
 * spin_unlock_irq(&dev_priv->uncore.lock);
 *
 *
 * Note: some registers may not need forcewake held, so
 * intel_uncore_forcewake_{get,put} can be omitted, see
 * intel_uncore_forcewake_for_reg().
 *
 * Certain architectures will die if the same cacheline is concurrently accessed
 * by different clients (e.g. on Ivybridge). Access to registers should
 * therefore generally be serialised, by either the dev_priv->uncore.lock or
 * a more localised lock guarding all access to that bank of registers.
3879
 */
3880 3881
#define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3882
#define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3883 3884
#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)

3885 3886 3887 3888
/* "Broadcast RGB" property */
#define INTEL_BROADCAST_RGB_AUTO 0
#define INTEL_BROADCAST_RGB_FULL 1
#define INTEL_BROADCAST_RGB_LIMITED 2
3889

3890
static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
3891
{
3892
	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3893
		return VLV_VGACNTRL;
3894
	else if (INTEL_GEN(dev_priv) >= 5)
3895
		return CPU_VGACNTRL;
3896 3897 3898 3899
	else
		return VGACNTRL;
}

3900 3901 3902 3903 3904 3905 3906
static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
{
	unsigned long j = msecs_to_jiffies(m);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

3907 3908 3909 3910 3911
static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
{
        return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
}

3912 3913 3914 3915 3916 3917 3918 3919
static inline unsigned long
timespec_to_jiffies_timeout(const struct timespec *value)
{
	unsigned long j = timespec_to_jiffies(value);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

3920 3921 3922 3923 3924 3925 3926 3927 3928
/*
 * If you need to wait X milliseconds between events A and B, but event B
 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
 * when event A happened, then just before event B you call this function and
 * pass the timestamp as the first argument, and X as the second argument.
 */
static inline void
wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
{
3929
	unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3930 3931 3932 3933 3934 3935 3936 3937 3938 3939

	/*
	 * Don't re-read the value of "jiffies" every time since it may change
	 * behind our back and break the math.
	 */
	tmp_jiffies = jiffies;
	target_jiffies = timestamp_jiffies +
			 msecs_to_jiffies_timeout(to_wait_ms);

	if (time_after(target_jiffies, tmp_jiffies)) {
3940 3941 3942 3943
		remaining_jiffies = target_jiffies - tmp_jiffies;
		while (remaining_jiffies)
			remaining_jiffies =
			    schedule_timeout_uninterruptible(remaining_jiffies);
3944 3945
	}
}
3946 3947 3948

static inline bool
__i915_request_irq_complete(struct drm_i915_gem_request *req)
3949
{
3950 3951
	struct intel_engine_cs *engine = req->engine;

3952 3953 3954
	/* Before we do the heavier coherent read of the seqno,
	 * check the value (hopefully) in the CPU cacheline.
	 */
3955
	if (__i915_gem_request_completed(req))
3956 3957
		return true;

3958 3959 3960 3961 3962 3963 3964 3965 3966 3967 3968
	/* Ensure our read of the seqno is coherent so that we
	 * do not "miss an interrupt" (i.e. if this is the last
	 * request and the seqno write from the GPU is not visible
	 * by the time the interrupt fires, we will see that the
	 * request is incomplete and go back to sleep awaiting
	 * another interrupt that will never come.)
	 *
	 * Strictly, we only need to do this once after an interrupt,
	 * but it is easier and safer to do it every time the waiter
	 * is woken.
	 */
3969
	if (engine->irq_seqno_barrier &&
3970
	    rcu_access_pointer(engine->breadcrumbs.irq_seqno_bh) == current &&
3971
	    test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) {
3972 3973
		struct task_struct *tsk;

3974 3975 3976 3977 3978 3979 3980 3981 3982 3983 3984 3985
		/* The ordering of irq_posted versus applying the barrier
		 * is crucial. The clearing of the current irq_posted must
		 * be visible before we perform the barrier operation,
		 * such that if a subsequent interrupt arrives, irq_posted
		 * is reasserted and our task rewoken (which causes us to
		 * do another __i915_request_irq_complete() immediately
		 * and reapply the barrier). Conversely, if the clear
		 * occurs after the barrier, then an interrupt that arrived
		 * whilst we waited on the barrier would not trigger a
		 * barrier on the next pass, and the read may not see the
		 * seqno update.
		 */
3986
		engine->irq_seqno_barrier(engine);
3987 3988 3989 3990 3991 3992 3993 3994

		/* If we consume the irq, but we are no longer the bottom-half,
		 * the real bottom-half may not have serialised their own
		 * seqno check with the irq-barrier (i.e. may have inspected
		 * the seqno before we believe it coherent since they see
		 * irq_posted == false but we are still running).
		 */
		rcu_read_lock();
3995
		tsk = rcu_dereference(engine->breadcrumbs.irq_seqno_bh);
3996 3997 3998 3999 4000 4001 4002 4003 4004 4005
		if (tsk && tsk != current)
			/* Note that if the bottom-half is changed as we
			 * are sending the wake-up, the new bottom-half will
			 * be woken by whomever made the change. We only have
			 * to worry about when we steal the irq-posted for
			 * ourself.
			 */
			wake_up_process(tsk);
		rcu_read_unlock();

4006
		if (__i915_gem_request_completed(req))
4007 4008
			return true;
	}
4009 4010 4011 4012

	return false;
}

4013 4014 4015
void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);

4016 4017 4018 4019 4020 4021 4022 4023 4024 4025 4026 4027 4028 4029 4030 4031
/* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
 * perform the operation. To check beforehand, pass in the parameters to
 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
 * you only need to pass in the minor offsets, page-aligned pointers are
 * always valid.
 *
 * For just checking for SSE4.1, in the foreknowledge that the future use
 * will be correctly aligned, just use i915_has_memcpy_from_wc().
 */
#define i915_can_memcpy_from_wc(dst, src, len) \
	i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)

#define i915_has_memcpy_from_wc() \
	i915_memcpy_from_wc(NULL, NULL, 0)

4032 4033 4034 4035 4036
/* i915_mm.c */
int remap_io_mapping(struct vm_area_struct *vma,
		     unsigned long addr, unsigned long pfn, unsigned long size,
		     struct io_mapping *iomap);

L
Linus Torvalds 已提交
4037
#endif