i915_drv.h 118.5 KB
Newer Older
L
Linus Torvalds 已提交
1 2
/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
 */
D
Dave Airlie 已提交
3
/*
4
 *
L
Linus Torvalds 已提交
5 6
 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
D
Dave Airlie 已提交
28
 */
L
Linus Torvalds 已提交
29 30 31 32

#ifndef _I915_DRV_H_
#define _I915_DRV_H_

33
#include <uapi/drm/i915_drm.h>
34
#include <uapi/drm/drm_fourcc.h>
35

36
#include <linux/io-mapping.h>
37
#include <linux/i2c.h>
38
#include <linux/i2c-algo-bit.h>
39
#include <linux/backlight.h>
40
#include <linux/hashtable.h>
41
#include <linux/intel-iommu.h>
42
#include <linux/kref.h>
43
#include <linux/pm_qos.h>
44 45 46 47 48 49
#include <linux/shmem_fs.h>

#include <drm/drmP.h>
#include <drm/intel-gtt.h>
#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
#include <drm/drm_gem.h>
D
Daniel Vetter 已提交
50
#include <drm/drm_auth.h>
51 52 53 54 55

#include "i915_params.h"
#include "i915_reg.h"

#include "intel_bios.h"
56
#include "intel_dpll_mgr.h"
57 58 59 60
#include "intel_guc.h"
#include "intel_lrc.h"
#include "intel_ringbuffer.h"

61
#include "i915_gem.h"
62 63
#include "i915_gem_gtt.h"
#include "i915_gem_render_state.h"
64
#include "i915_gem_request.h"
65

66 67
#include "intel_gvt.h"

L
Linus Torvalds 已提交
68 69 70 71 72
/* General customization:
 */

#define DRIVER_NAME		"i915"
#define DRIVER_DESC		"Intel Graphics"
73
#define DRIVER_DATE		"20160919"
L
Linus Torvalds 已提交
74

75
#undef WARN_ON
76 77 78 79 80 81 82 83
/* Many gcc seem to no see through this and fall over :( */
#if 0
#define WARN_ON(x) ({ \
	bool __i915_warn_cond = (x); \
	if (__builtin_constant_p(__i915_warn_cond)) \
		BUILD_BUG_ON(__i915_warn_cond); \
	WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
#else
84
#define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
85 86
#endif

87
#undef WARN_ON_ONCE
88
#define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
89

90 91
#define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
			     (long) (x), __func__);
92

R
Rob Clark 已提交
93 94 95 96 97 98 99 100 101
/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
 * which may not necessarily be a user visible problem.  This will either
 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
 * enable distros and users to tailor their preferred amount of i915 abrt
 * spam.
 */
#define I915_STATE_WARN(condition, format...) ({			\
	int __ret_warn_on = !!(condition);				\
102 103
	if (unlikely(__ret_warn_on))					\
		if (!WARN(i915.verbose_state_checks, format))		\
R
Rob Clark 已提交
104 105 106 107
			DRM_ERROR(format);				\
	unlikely(__ret_warn_on);					\
})

108 109
#define I915_STATE_WARN_ON(x)						\
	I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
110

111 112 113 114
bool __i915_inject_load_failure(const char *func, int line);
#define i915_inject_load_failure() \
	__i915_inject_load_failure(__func__, __LINE__)

115 116 117 118 119
static inline const char *yesno(bool v)
{
	return v ? "yes" : "no";
}

120 121 122 123 124
static inline const char *onoff(bool v)
{
	return v ? "on" : "off";
}

125
enum pipe {
126
	INVALID_PIPE = -1,
127 128
	PIPE_A = 0,
	PIPE_B,
129
	PIPE_C,
130 131
	_PIPE_EDP,
	I915_MAX_PIPES = _PIPE_EDP
132
};
133
#define pipe_name(p) ((p) + 'A')
134

P
Paulo Zanoni 已提交
135 136 137 138
enum transcoder {
	TRANSCODER_A = 0,
	TRANSCODER_B,
	TRANSCODER_C,
139
	TRANSCODER_EDP,
J
Jani Nikula 已提交
140 141
	TRANSCODER_DSI_A,
	TRANSCODER_DSI_C,
142
	I915_MAX_TRANSCODERS
P
Paulo Zanoni 已提交
143
};
144 145 146 147 148 149 150 151 152 153 154 155

static inline const char *transcoder_name(enum transcoder transcoder)
{
	switch (transcoder) {
	case TRANSCODER_A:
		return "A";
	case TRANSCODER_B:
		return "B";
	case TRANSCODER_C:
		return "C";
	case TRANSCODER_EDP:
		return "EDP";
J
Jani Nikula 已提交
156 157 158 159
	case TRANSCODER_DSI_A:
		return "DSI A";
	case TRANSCODER_DSI_C:
		return "DSI C";
160 161 162 163
	default:
		return "<invalid>";
	}
}
P
Paulo Zanoni 已提交
164

J
Jani Nikula 已提交
165 166 167 168 169
static inline bool transcoder_is_dsi(enum transcoder transcoder)
{
	return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
}

170
/*
171 172 173 174
 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
 * number of planes per CRTC.  Not all platforms really have this many planes,
 * which means some arrays of size I915_MAX_PLANES may have unused entries
 * between the topmost sprite plane and the cursor plane.
175
 */
176 177 178
enum plane {
	PLANE_A = 0,
	PLANE_B,
179
	PLANE_C,
180 181
	PLANE_CURSOR,
	I915_MAX_PLANES,
182
};
183
#define plane_name(p) ((p) + 'A')
184

185
#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
186

187
enum port {
188
	PORT_NONE = -1,
189 190 191 192 193 194 195 196 197
	PORT_A = 0,
	PORT_B,
	PORT_C,
	PORT_D,
	PORT_E,
	I915_MAX_PORTS
};
#define port_name(p) ((p) + 'A')

198
#define I915_NUM_PHYS_VLV 2
199 200 201 202 203 204 205 206 207 208 209

enum dpio_channel {
	DPIO_CH0,
	DPIO_CH1
};

enum dpio_phy {
	DPIO_PHY0,
	DPIO_PHY1
};

210 211 212 213 214 215 216 217 218 219
enum intel_display_power_domain {
	POWER_DOMAIN_PIPE_A,
	POWER_DOMAIN_PIPE_B,
	POWER_DOMAIN_PIPE_C,
	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
	POWER_DOMAIN_TRANSCODER_A,
	POWER_DOMAIN_TRANSCODER_B,
	POWER_DOMAIN_TRANSCODER_C,
220
	POWER_DOMAIN_TRANSCODER_EDP,
J
Jani Nikula 已提交
221 222
	POWER_DOMAIN_TRANSCODER_DSI_A,
	POWER_DOMAIN_TRANSCODER_DSI_C,
223 224 225 226 227
	POWER_DOMAIN_PORT_DDI_A_LANES,
	POWER_DOMAIN_PORT_DDI_B_LANES,
	POWER_DOMAIN_PORT_DDI_C_LANES,
	POWER_DOMAIN_PORT_DDI_D_LANES,
	POWER_DOMAIN_PORT_DDI_E_LANES,
I
Imre Deak 已提交
228 229 230
	POWER_DOMAIN_PORT_DSI,
	POWER_DOMAIN_PORT_CRT,
	POWER_DOMAIN_PORT_OTHER,
V
Ville Syrjälä 已提交
231
	POWER_DOMAIN_VGA,
I
Imre Deak 已提交
232
	POWER_DOMAIN_AUDIO,
P
Paulo Zanoni 已提交
233
	POWER_DOMAIN_PLLS,
234 235 236 237
	POWER_DOMAIN_AUX_A,
	POWER_DOMAIN_AUX_B,
	POWER_DOMAIN_AUX_C,
	POWER_DOMAIN_AUX_D,
238
	POWER_DOMAIN_GMBUS,
239
	POWER_DOMAIN_MODESET,
240
	POWER_DOMAIN_INIT,
241 242

	POWER_DOMAIN_NUM,
243 244 245 246 247
};

#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
		((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
248 249 250
#define POWER_DOMAIN_TRANSCODER(tran) \
	((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
	 (tran) + POWER_DOMAIN_TRANSCODER_A)
251

252 253 254 255 256 257
enum hpd_pin {
	HPD_NONE = 0,
	HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
	HPD_CRT,
	HPD_SDVO_B,
	HPD_SDVO_C,
258
	HPD_PORT_A,
259 260 261
	HPD_PORT_B,
	HPD_PORT_C,
	HPD_PORT_D,
X
Xiong Zhang 已提交
262
	HPD_PORT_E,
263 264 265
	HPD_NUM_PINS
};

266 267 268
#define for_each_hpd_pin(__pin) \
	for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)

269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288
struct i915_hotplug {
	struct work_struct hotplug_work;

	struct {
		unsigned long last_jiffies;
		int count;
		enum {
			HPD_ENABLED = 0,
			HPD_DISABLED = 1,
			HPD_MARK_DISABLED = 2
		} state;
	} stats[HPD_NUM_PINS];
	u32 event_bits;
	struct delayed_work reenable_work;

	struct intel_digital_port *irq_port[I915_MAX_PORTS];
	u32 long_port_mask;
	u32 short_port_mask;
	struct work_struct dig_port_work;

289 290 291
	struct work_struct poll_init_work;
	bool poll_enabled;

292 293 294 295 296 297 298 299 300 301
	/*
	 * if we get a HPD irq from DP and a HPD irq from non-DP
	 * the non-DP HPD could block the workqueue on a mode config
	 * mutex getting, that userspace may have taken. However
	 * userspace is waiting on the DP workqueue to run which is
	 * blocked behind the non-DP one.
	 */
	struct workqueue_struct *dp_wq;
};

302 303 304 305 306 307
#define I915_GEM_GPU_DOMAINS \
	(I915_GEM_DOMAIN_RENDER | \
	 I915_GEM_DOMAIN_SAMPLER | \
	 I915_GEM_DOMAIN_COMMAND | \
	 I915_GEM_DOMAIN_INSTRUCTION | \
	 I915_GEM_DOMAIN_VERTEX)
308

309 310
#define for_each_pipe(__dev_priv, __p) \
	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
311 312 313
#define for_each_pipe_masked(__dev_priv, __p, __mask) \
	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
		for_each_if ((__mask) & (1 << (__p)))
314 315 316 317
#define for_each_plane(__dev_priv, __pipe, __p)				\
	for ((__p) = 0;							\
	     (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1;	\
	     (__p)++)
318 319 320 321
#define for_each_sprite(__dev_priv, __p, __s)				\
	for ((__s) = 0;							\
	     (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)];	\
	     (__s)++)
322

323 324 325 326
#define for_each_port_masked(__port, __ports_mask) \
	for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)	\
		for_each_if ((__ports_mask) & (1 << (__port)))

327
#define for_each_crtc(dev, crtc) \
328
	list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
329

330 331
#define for_each_intel_plane(dev, intel_plane) \
	list_for_each_entry(intel_plane,			\
332
			    &(dev)->mode_config.plane_list,	\
333 334
			    base.head)

335
#define for_each_intel_plane_mask(dev, intel_plane, plane_mask)		\
336 337
	list_for_each_entry(intel_plane,				\
			    &(dev)->mode_config.plane_list,		\
338 339 340 341
			    base.head)					\
		for_each_if ((plane_mask) &				\
			     (1 << drm_plane_index(&intel_plane->base)))

342 343 344 345
#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)	\
	list_for_each_entry(intel_plane,				\
			    &(dev)->mode_config.plane_list,		\
			    base.head)					\
346
		for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
347

348 349 350 351
#define for_each_intel_crtc(dev, intel_crtc)				\
	list_for_each_entry(intel_crtc,					\
			    &(dev)->mode_config.crtc_list,		\
			    base.head)
352

353 354 355 356
#define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask)		\
	list_for_each_entry(intel_crtc,					\
			    &(dev)->mode_config.crtc_list,		\
			    base.head)					\
357 358
		for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))

359 360 361 362 363
#define for_each_intel_encoder(dev, intel_encoder)		\
	list_for_each_entry(intel_encoder,			\
			    &(dev)->mode_config.encoder_list,	\
			    base.head)

364 365
#define for_each_intel_connector(dev, intel_connector)		\
	list_for_each_entry(intel_connector,			\
366
			    &(dev)->mode_config.connector_list,	\
367 368
			    base.head)

369 370
#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
371
		for_each_if ((intel_encoder)->base.crtc == (__crtc))
372

373 374
#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
	list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
375
		for_each_if ((intel_connector)->base.encoder == (__encoder))
376

377 378
#define for_each_power_domain(domain, mask)				\
	for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)	\
379
		for_each_if ((1 << (domain)) & (mask))
380

381
struct drm_i915_private;
382
struct i915_mm_struct;
383
struct i915_mmu_object;
384

385 386 387 388 389 390 391
struct drm_i915_file_private {
	struct drm_i915_private *dev_priv;
	struct drm_file *file;

	struct {
		spinlock_t lock;
		struct list_head request_list;
392 393 394 395 396 397
/* 20ms is a fairly arbitrary limit (greater than the average frame time)
 * chosen to prevent the CPU getting more than a frame ahead of the GPU
 * (when using lax throttling for the frontbuffer). We also use it to
 * offer free GPU waitboosts for severely congested workloads.
 */
#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
398 399 400
	} mm;
	struct idr context_idr;

401 402 403 404
	struct intel_rps_client {
		struct list_head link;
		unsigned boosts;
	} rps;
405

406
	unsigned int bsd_engine;
407 408
};

409 410 411 412 413 414 415 416 417 418 419 420 421
/* Used by dp and fdi links */
struct intel_link_m_n {
	uint32_t	tu;
	uint32_t	gmch_m;
	uint32_t	gmch_n;
	uint32_t	link_m;
	uint32_t	link_n;
};

void intel_link_compute_m_n(int bpp, int nlanes,
			    int pixel_clock, int link_clock,
			    struct intel_link_m_n *m_n);

L
Linus Torvalds 已提交
422 423 424
/* Interface history:
 *
 * 1.1: Original.
D
Dave Airlie 已提交
425 426
 * 1.2: Add Power Management
 * 1.3: Add vblank support
427
 * 1.4: Fix cmdbuffer path, add heap destroy
428
 * 1.5: Add vblank pipe configuration
=
=?utf-8?q?Michel_D=C3=A4nzer?= 已提交
429 430
 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 *      - Support vertical blank on secondary display pipe
L
Linus Torvalds 已提交
431 432
 */
#define DRIVER_MAJOR		1
=
=?utf-8?q?Michel_D=C3=A4nzer?= 已提交
433
#define DRIVER_MINOR		6
L
Linus Torvalds 已提交
434 435
#define DRIVER_PATCHLEVEL	0

436 437 438 439 440
struct opregion_header;
struct opregion_acpi;
struct opregion_swsci;
struct opregion_asle;

441
struct intel_opregion {
442 443 444
	struct opregion_header *header;
	struct opregion_acpi *acpi;
	struct opregion_swsci *swsci;
J
Jani Nikula 已提交
445 446
	u32 swsci_gbda_sub_functions;
	u32 swsci_sbcb_sub_functions;
447
	struct opregion_asle *asle;
448
	void *rvda;
449
	const void *vbt;
450
	u32 vbt_size;
451
	u32 *lid_state;
452
	struct work_struct asle_work;
453
};
454
#define OPREGION_SIZE            (8*1024)
455

456 457 458
struct intel_overlay;
struct intel_overlay_error_state;

459
struct drm_i915_fence_reg {
460
	struct list_head link;
461 462
	struct drm_i915_private *i915;
	struct i915_vma *vma;
463
	int pin_count;
464 465 466 467 468 469 470 471 472 473
	int id;
	/**
	 * Whether the tiling parameters for the currently
	 * associated fence register have changed. Note that
	 * for the purposes of tracking tiling changes we also
	 * treat the unfenced register, the register slot that
	 * the object occupies whilst it executes a fenced
	 * command (such as BLT on gen2/3), as a "fence".
	 */
	bool dirty;
474
};
475

476
struct sdvo_device_mapping {
C
Chris Wilson 已提交
477
	u8 initialized;
478 479 480
	u8 dvo_port;
	u8 slave_addr;
	u8 dvo_wiring;
C
Chris Wilson 已提交
481
	u8 i2c_pin;
482
	u8 ddc_pin;
483 484
};

485
struct intel_connector;
486
struct intel_encoder;
487
struct intel_crtc_state;
488
struct intel_initial_plane_config;
489
struct intel_crtc;
490 491
struct intel_limit;
struct dpll;
492

493 494 495
struct drm_i915_display_funcs {
	int (*get_display_clock_speed)(struct drm_device *dev);
	int (*get_fifo_size)(struct drm_device *dev, int plane);
496
	int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
497 498 499 500 501
	int (*compute_intermediate_wm)(struct drm_device *dev,
				       struct intel_crtc *intel_crtc,
				       struct intel_crtc_state *newstate);
	void (*initial_watermarks)(struct intel_crtc_state *cstate);
	void (*optimize_watermarks)(struct intel_crtc_state *cstate);
502
	int (*compute_global_watermarks)(struct drm_atomic_state *state);
503
	void (*update_wm)(struct drm_crtc *crtc);
504 505
	int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
	void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
506 507 508
	/* Returns the active state of the crtc, and if the crtc is active,
	 * fills out the pipe-config with the hw state. */
	bool (*get_pipe_config)(struct intel_crtc *,
509
				struct intel_crtc_state *);
510 511
	void (*get_initial_plane_config)(struct intel_crtc *,
					 struct intel_initial_plane_config *);
512 513
	int (*crtc_compute_clock)(struct intel_crtc *crtc,
				  struct intel_crtc_state *crtc_state);
514 515 516 517
	void (*crtc_enable)(struct intel_crtc_state *pipe_config,
			    struct drm_atomic_state *old_state);
	void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
			     struct drm_atomic_state *old_state);
518 519
	void (*update_crtcs)(struct drm_atomic_state *state,
			     unsigned int *crtc_vblank_mask);
520 521
	void (*audio_codec_enable)(struct drm_connector *connector,
				   struct intel_encoder *encoder,
522
				   const struct drm_display_mode *adjusted_mode);
523
	void (*audio_codec_disable)(struct intel_encoder *encoder);
524
	void (*fdi_link_train)(struct drm_crtc *crtc);
525
	void (*init_clock_gating)(struct drm_device *dev);
526 527 528 529 530
	int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
			  struct drm_framebuffer *fb,
			  struct drm_i915_gem_object *obj,
			  struct drm_i915_gem_request *req,
			  uint32_t flags);
531
	void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
532 533 534 535 536
	/* clock updates for mode set */
	/* cursor updates */
	/* render clock increase/decrease */
	/* display clock increase/decrease */
	/* pll clock increase/decrease */
537

538 539
	void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
	void (*load_luts)(struct drm_crtc_state *crtc_state);
540 541
};

542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558
enum forcewake_domain_id {
	FW_DOMAIN_ID_RENDER = 0,
	FW_DOMAIN_ID_BLITTER,
	FW_DOMAIN_ID_MEDIA,

	FW_DOMAIN_ID_COUNT
};

enum forcewake_domains {
	FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
	FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
	FORCEWAKE_MEDIA	= (1 << FW_DOMAIN_ID_MEDIA),
	FORCEWAKE_ALL = (FORCEWAKE_RENDER |
			 FORCEWAKE_BLITTER |
			 FORCEWAKE_MEDIA)
};

559 560 561 562 563 564 565
#define FW_REG_READ  (1)
#define FW_REG_WRITE (2)

enum forcewake_domains
intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
			       i915_reg_t reg, unsigned int op);

566
struct intel_uncore_funcs {
567
	void (*force_wake_get)(struct drm_i915_private *dev_priv,
568
							enum forcewake_domains domains);
569
	void (*force_wake_put)(struct drm_i915_private *dev_priv,
570
							enum forcewake_domains domains);
571

572 573 574 575
	uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
	uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
	uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
	uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
576

577
	void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
578
				uint8_t val, bool trace);
579
	void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
580
				uint16_t val, bool trace);
581
	void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
582
				uint32_t val, bool trace);
583 584
};

585 586 587 588 589 590
struct intel_uncore {
	spinlock_t lock; /** lock is also taken in irq contexts. */

	struct intel_uncore_funcs funcs;

	unsigned fifo_count;
591
	enum forcewake_domains fw_domains;
592 593 594

	struct intel_uncore_forcewake_domain {
		struct drm_i915_private *i915;
595
		enum forcewake_domain_id id;
596
		enum forcewake_domains mask;
597
		unsigned wake_count;
598
		struct hrtimer timer;
599
		i915_reg_t reg_set;
600 601
		u32 val_set;
		u32 val_clear;
602 603
		i915_reg_t reg_ack;
		i915_reg_t reg_post;
604
		u32 val_reset;
605
	} fw_domain[FW_DOMAIN_ID_COUNT];
606 607

	int unclaimed_mmio_check;
608 609 610
};

/* Iterate over initialised fw domains */
611 612 613 614 615 616 617 618
#define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
	for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
	     (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
	     (domain__)++) \
		for_each_if ((mask__) & (domain__)->mask)

#define for_each_fw_domain(domain__, dev_priv__) \
	for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
619

620 621 622 623
#define CSR_VERSION(major, minor)	((major) << 16 | (minor))
#define CSR_VERSION_MAJOR(version)	((version) >> 16)
#define CSR_VERSION_MINOR(version)	((version) & 0xffff)

624
struct intel_csr {
625
	struct work_struct work;
626
	const char *fw_path;
627
	uint32_t *dmc_payload;
628
	uint32_t dmc_fw_size;
629
	uint32_t version;
630
	uint32_t mmio_count;
631
	i915_reg_t mmioaddr[8];
632
	uint32_t mmiodata[8];
633
	uint32_t dc_state;
634
	uint32_t allowed_dc_mask;
635 636
};

637 638 639 640 641 642
#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
	func(is_mobile) sep \
	func(is_i85x) sep \
	func(is_i915g) sep \
	func(is_i945gm) sep \
	func(is_g33) sep \
643
	func(hws_needs_physical) sep \
644 645 646 647 648 649
	func(is_g4x) sep \
	func(is_pineview) sep \
	func(is_broadwater) sep \
	func(is_crestline) sep \
	func(is_ivybridge) sep \
	func(is_valleyview) sep \
650
	func(is_cherryview) sep \
651
	func(is_haswell) sep \
652
	func(is_broadwell) sep \
653
	func(is_skylake) sep \
654
	func(is_broxton) sep \
655
	func(is_kabylake) sep \
656
	func(is_preliminary) sep \
657
	func(has_fbc) sep \
658
	func(has_psr) sep \
659
	func(has_runtime_pm) sep \
660
	func(has_csr) sep \
661
	func(has_resource_streamer) sep \
662
	func(has_rc6) sep \
663
	func(has_rc6p) sep \
664
	func(has_dp_mst) sep \
665
	func(has_gmbus_irq) sep \
666
	func(has_hw_contexts) sep \
667
	func(has_logical_ring_contexts) sep \
668
	func(has_l3_dpf) sep \
669
	func(has_gmch_display) sep \
670
	func(has_guc) sep \
671 672 673 674 675 676
	func(has_pipe_cxsr) sep \
	func(has_hotplug) sep \
	func(cursor_needs_physical) sep \
	func(has_overlay) sep \
	func(overlay_needs_physical) sep \
	func(supports_tv) sep \
677
	func(has_llc) sep \
678
	func(has_snoop) sep \
679
	func(has_ddi) sep \
680 681
	func(has_fpga_dbg) sep \
	func(has_pooled_eu)
D
Daniel Vetter 已提交
682

683 684
#define DEFINE_FLAG(name) u8 name:1
#define SEP_SEMICOLON ;
D
Daniel Vetter 已提交
685

686
struct sseu_dev_info {
687
	u8 slice_mask;
688
	u8 subslice_mask;
689 690
	u8 eu_total;
	u8 eu_per_subslice;
691 692 693 694 695 696
	u8 min_eu_in_pool;
	/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
	u8 subslice_7eu[3];
	u8 has_slice_pg:1;
	u8 has_subslice_pg:1;
	u8 has_eu_pg:1;
697 698
};

699 700 701 702 703
static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
{
	return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
}

704
struct intel_device_info {
705
	u32 display_mmio_offset;
706
	u16 device_id;
707
	u8 num_pipes;
708
	u8 num_sprites[I915_MAX_PIPES];
709
	u8 gen;
710
	u16 gen_mask;
711
	u8 ring_mask; /* Rings supported by the HW */
712
	u8 num_rings;
713
	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
714
	u16 ddb_size; /* in blocks */
715 716 717 718
	/* Register offsets for the various display pipes and transcoders */
	int pipe_offsets[I915_MAX_TRANSCODERS];
	int trans_offsets[I915_MAX_TRANSCODERS];
	int palette_offsets[I915_MAX_PIPES];
719
	int cursor_offsets[I915_MAX_PIPES];
720 721

	/* Slice/subslice/EU info */
722
	struct sseu_dev_info sseu;
723 724 725 726 727

	struct color_luts {
		u16 degamma_lut_size;
		u16 gamma_lut_size;
	} color;
728 729
};

730 731 732
#undef DEFINE_FLAG
#undef SEP_SEMICOLON

733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762
struct intel_display_error_state;

struct drm_i915_error_state {
	struct kref ref;
	struct timeval time;

	char error_msg[128];
	bool simulated;
	int iommu;
	u32 reset_count;
	u32 suspend_count;
	struct intel_device_info device_info;

	/* Generic register state */
	u32 eir;
	u32 pgtbl_er;
	u32 ier;
	u32 gtier[4];
	u32 ccid;
	u32 derrmr;
	u32 forcewake;
	u32 error; /* gen6+ */
	u32 err_int; /* gen7 */
	u32 fault_data0; /* gen8, gen9 */
	u32 fault_data1; /* gen8, gen9 */
	u32 done_reg;
	u32 gac_eco;
	u32 gam_ecochk;
	u32 gab_ctl;
	u32 gfx_mode;
763

764 765 766
	u64 fence[I915_MAX_NUM_FENCES];
	struct intel_overlay_error_state *overlay;
	struct intel_display_error_state *display;
767
	struct drm_i915_error_object *semaphore;
768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790

	struct drm_i915_error_engine {
		int engine_id;
		/* Software tracked state */
		bool waiting;
		int num_waiters;
		int hangcheck_score;
		enum intel_engine_hangcheck_action hangcheck_action;
		struct i915_address_space *vm;
		int num_requests;

		/* our own tracking of ring head and tail */
		u32 cpu_ring_head;
		u32 cpu_ring_tail;

		u32 last_seqno;
		u32 semaphore_seqno[I915_NUM_ENGINES - 1];

		/* Register state */
		u32 start;
		u32 tail;
		u32 head;
		u32 ctl;
791
		u32 mode;
792 793 794 795 796 797 798 799 800 801 802 803 804
		u32 hws;
		u32 ipeir;
		u32 ipehr;
		u32 bbstate;
		u32 instpm;
		u32 instps;
		u32 seqno;
		u64 bbaddr;
		u64 acthd;
		u32 fault_reg;
		u64 faddr;
		u32 rc_psmi; /* sleep state */
		u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
805
		struct intel_instdone instdone;
806 807 808 809

		struct drm_i915_error_object {
			int page_count;
			u64 gtt_offset;
810
			u64 gtt_size;
811 812 813 814 815 816 817
			u32 *pages[0];
		} *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;

		struct drm_i915_error_object *wa_ctx;

		struct drm_i915_error_request {
			long jiffies;
818
			pid_t pid;
819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860
			u32 seqno;
			u32 head;
			u32 tail;
		} *requests;

		struct drm_i915_error_waiter {
			char comm[TASK_COMM_LEN];
			pid_t pid;
			u32 seqno;
		} *waiters;

		struct {
			u32 gfx_mode;
			union {
				u64 pdp[4];
				u32 pp_dir_base;
			};
		} vm_info;

		pid_t pid;
		char comm[TASK_COMM_LEN];
	} engine[I915_NUM_ENGINES];

	struct drm_i915_error_buffer {
		u32 size;
		u32 name;
		u32 rseqno[I915_NUM_ENGINES], wseqno;
		u64 gtt_offset;
		u32 read_domains;
		u32 write_domain;
		s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
		u32 tiling:2;
		u32 dirty:1;
		u32 purgeable:1;
		u32 userptr:1;
		s32 engine:4;
		u32 cache_level:3;
	} *active_bo[I915_NUM_ENGINES], *pinned_bo;
	u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
	struct i915_address_space *active_vm[I915_NUM_ENGINES];
};

861 862
enum i915_cache_level {
	I915_CACHE_NONE = 0,
863 864 865 866 867
	I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
	I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
			      caches, eg sampler/render caches, and the
			      large Last-Level-Cache. LLC is coherent with
			      the CPU, but L3 is only visible to the GPU. */
868
	I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
869 870
};

871 872 873 874 875 876
struct i915_ctx_hang_stats {
	/* This context had batch pending when hang was declared */
	unsigned batch_pending;

	/* This context had batch active when hang was declared */
	unsigned batch_active;
877 878 879 880

	/* Time when this context was last blamed for a GPU reset */
	unsigned long guilty_ts;

881 882 883 884 885
	/* If the contexts causes a second GPU hang within this time,
	 * it is permanently banned from submitting any more work.
	 */
	unsigned long ban_period_seconds;

886 887
	/* This context is banned to submit more work */
	bool banned;
888
};
889 890

/* This must match up with the value previously used for execbuf2.rsvd1. */
891
#define DEFAULT_CONTEXT_HANDLE 0
892

893
/**
894
 * struct i915_gem_context - as the name implies, represents a context.
895 896 897
 * @ref: reference count.
 * @user_handle: userspace tracking identity for this context.
 * @remap_slice: l3 row remapping information.
898 899
 * @flags: context specific flags:
 *         CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
900 901 902 903
 * @file_priv: filp associated with this context (NULL for global default
 *	       context).
 * @hang_stats: information about the role of this context in possible GPU
 *		hangs.
904
 * @ppgtt: virtual memory space used by this context.
905 906 907 908 909 910 911
 * @legacy_hw_ctx: render context backing object and whether it is correctly
 *                initialized (legacy ring submission mechanism only).
 * @link: link in the global list of contexts.
 *
 * Contexts are memory images used by the hardware to store copies of their
 * internal state.
 */
912
struct i915_gem_context {
913
	struct kref ref;
914
	struct drm_i915_private *i915;
915
	struct drm_i915_file_private *file_priv;
916
	struct i915_hw_ppgtt *ppgtt;
917
	struct pid *pid;
918

919 920 921
	struct i915_ctx_hang_stats hang_stats;

	unsigned long flags;
922 923
#define CONTEXT_NO_ZEROMAP		BIT(0)
#define CONTEXT_NO_ERROR_CAPTURE	BIT(1)
924 925 926

	/* Unique identifier for this context, used by the hw for tracking */
	unsigned int hw_id;
927
	u32 user_handle;
928

929 930
	u32 ggtt_alignment;

931
	struct intel_context {
932
		struct i915_vma *state;
933
		struct intel_ring *ring;
934
		uint32_t *lrc_reg_state;
935 936
		u64 lrc_desc;
		int pin_count;
937
		bool initialised;
938
	} engine[I915_NUM_ENGINES];
939
	u32 ring_size;
940
	u32 desc_template;
941
	struct atomic_notifier_head status_notifier;
942
	bool execlists_force_single_submission;
943

944
	struct list_head link;
945 946

	u8 remap_slice;
947
	bool closed:1;
948 949
};

950 951 952 953 954
enum fb_op_origin {
	ORIGIN_GTT,
	ORIGIN_CPU,
	ORIGIN_CS,
	ORIGIN_FLIP,
955
	ORIGIN_DIRTYFB,
956 957
};

958
struct intel_fbc {
P
Paulo Zanoni 已提交
959 960 961
	/* This is always the inner lock when overlapping with struct_mutex and
	 * it's the outer lock when overlapping with stolen_lock. */
	struct mutex lock;
B
Ben Widawsky 已提交
962
	unsigned threshold;
963 964
	unsigned int possible_framebuffer_bits;
	unsigned int busy_bits;
965
	unsigned int visible_pipes_mask;
966
	struct intel_crtc *crtc;
967

968
	struct drm_mm_node compressed_fb;
969 970
	struct drm_mm_node *compressed_llb;

971 972
	bool false_color;

973
	bool enabled;
974
	bool active;
975

976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997
	struct intel_fbc_state_cache {
		struct {
			unsigned int mode_flags;
			uint32_t hsw_bdw_pixel_rate;
		} crtc;

		struct {
			unsigned int rotation;
			int src_w;
			int src_h;
			bool visible;
		} plane;

		struct {
			u64 ilk_ggtt_offset;
			uint32_t pixel_format;
			unsigned int stride;
			int fence_reg;
			unsigned int tiling_mode;
		} fb;
	} state_cache;

998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014
	struct intel_fbc_reg_params {
		struct {
			enum pipe pipe;
			enum plane plane;
			unsigned int fence_y_offset;
		} crtc;

		struct {
			u64 ggtt_offset;
			uint32_t pixel_format;
			unsigned int stride;
			int fence_reg;
		} fb;

		int cfb_size;
	} params;

1015
	struct intel_fbc_work {
1016
		bool scheduled;
1017
		u32 scheduled_vblank;
1018 1019
		struct work_struct work;
	} work;
1020

1021
	const char *no_fbc_reason;
1022 1023
};

1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038
/**
 * HIGH_RR is the highest eDP panel refresh rate read from EDID
 * LOW_RR is the lowest eDP panel refresh rate found from EDID
 * parsing for same resolution.
 */
enum drrs_refresh_rate_type {
	DRRS_HIGH_RR,
	DRRS_LOW_RR,
	DRRS_MAX_RR, /* RR count */
};

enum drrs_support_type {
	DRRS_NOT_SUPPORTED = 0,
	STATIC_DRRS_SUPPORT = 1,
	SEAMLESS_DRRS_SUPPORT = 2
1039 1040
};

1041
struct intel_dp;
1042 1043 1044 1045 1046 1047 1048 1049 1050
struct i915_drrs {
	struct mutex mutex;
	struct delayed_work work;
	struct intel_dp *dp;
	unsigned busy_frontbuffer_bits;
	enum drrs_refresh_rate_type refresh_rate_type;
	enum drrs_support_type type;
};

R
Rodrigo Vivi 已提交
1051
struct i915_psr {
1052
	struct mutex lock;
R
Rodrigo Vivi 已提交
1053 1054
	bool sink_support;
	bool source_ok;
1055
	struct intel_dp *enabled;
1056 1057
	bool active;
	struct delayed_work work;
1058
	unsigned busy_frontbuffer_bits;
1059 1060
	bool psr2_support;
	bool aux_frame_sync;
1061
	bool link_standby;
1062
};
1063

1064
enum intel_pch {
1065
	PCH_NONE = 0,	/* No PCH present */
1066 1067
	PCH_IBX,	/* Ibexpeak PCH */
	PCH_CPT,	/* Cougarpoint PCH */
1068
	PCH_LPT,	/* Lynxpoint PCH */
1069
	PCH_SPT,        /* Sunrisepoint PCH */
1070
	PCH_KBP,        /* Kabypoint PCH */
B
Ben Widawsky 已提交
1071
	PCH_NOP,
1072 1073
};

1074 1075 1076 1077 1078
enum intel_sbi_destination {
	SBI_ICLK,
	SBI_MPHY,
};

1079
#define QUIRK_PIPEA_FORCE (1<<0)
1080
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
1081
#define QUIRK_INVERT_BRIGHTNESS (1<<2)
1082
#define QUIRK_BACKLIGHT_PRESENT (1<<3)
1083
#define QUIRK_PIPEB_FORCE (1<<4)
1084
#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1085

1086
struct intel_fbdev;
1087
struct intel_fbc_work;
1088

1089 1090
struct intel_gmbus {
	struct i2c_adapter adapter;
1091
#define GMBUS_FORCE_BIT_RETRY (1U << 31)
1092
	u32 force_bit;
1093
	u32 reg0;
1094
	i915_reg_t gpio_reg;
1095
	struct i2c_algo_bit_data bit_algo;
1096 1097 1098
	struct drm_i915_private *dev_priv;
};

1099
struct i915_suspend_saved_registers {
1100
	u32 saveDSPARB;
J
Jesse Barnes 已提交
1101
	u32 saveFBC_CONTROL;
1102 1103
	u32 saveCACHE_MODE_0;
	u32 saveMI_ARB_STATE;
J
Jesse Barnes 已提交
1104 1105
	u32 saveSWF0[16];
	u32 saveSWF1[16];
1106
	u32 saveSWF3[3];
1107
	uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1108
	u32 savePCH_PORT_HOTPLUG;
1109
	u16 saveGCDGMBUS;
1110
};
1111

1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169
struct vlv_s0ix_state {
	/* GAM */
	u32 wr_watermark;
	u32 gfx_prio_ctrl;
	u32 arb_mode;
	u32 gfx_pend_tlb0;
	u32 gfx_pend_tlb1;
	u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
	u32 media_max_req_count;
	u32 gfx_max_req_count;
	u32 render_hwsp;
	u32 ecochk;
	u32 bsd_hwsp;
	u32 blt_hwsp;
	u32 tlb_rd_addr;

	/* MBC */
	u32 g3dctl;
	u32 gsckgctl;
	u32 mbctl;

	/* GCP */
	u32 ucgctl1;
	u32 ucgctl3;
	u32 rcgctl1;
	u32 rcgctl2;
	u32 rstctl;
	u32 misccpctl;

	/* GPM */
	u32 gfxpause;
	u32 rpdeuhwtc;
	u32 rpdeuc;
	u32 ecobus;
	u32 pwrdwnupctl;
	u32 rp_down_timeout;
	u32 rp_deucsw;
	u32 rcubmabdtmr;
	u32 rcedata;
	u32 spare2gh;

	/* Display 1 CZ domain */
	u32 gt_imr;
	u32 gt_ier;
	u32 pm_imr;
	u32 pm_ier;
	u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];

	/* GT SA CZ domain */
	u32 tilectl;
	u32 gt_fifoctl;
	u32 gtlc_wake_ctrl;
	u32 gtlc_survive;
	u32 pmwgicz;

	/* Display 2 CZ domain */
	u32 gu_ctl0;
	u32 gu_ctl1;
1170
	u32 pcbr;
1171 1172 1173
	u32 clock_gate_dis2;
};

1174 1175 1176 1177
struct intel_rps_ei {
	u32 cz_clock;
	u32 render_c0;
	u32 media_c0;
1178 1179
};

1180
struct intel_gen6_power_mgmt {
I
Imre Deak 已提交
1181 1182 1183 1184
	/*
	 * work, interrupts_enabled and pm_iir are protected by
	 * dev_priv->irq_lock
	 */
1185
	struct work_struct work;
I
Imre Deak 已提交
1186
	bool interrupts_enabled;
1187
	u32 pm_iir;
1188

1189
	/* PM interrupt bits that should never be masked */
1190 1191
	u32 pm_intr_keep;

1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206
	/* Frequencies are stored in potentially platform dependent multiples.
	 * In other words, *_freq needs to be multiplied by X to be interesting.
	 * Soft limits are those which are used for the dynamic reclocking done
	 * by the driver (raise frequencies under heavy loads, and lower for
	 * lighter loads). Hard limits are those imposed by the hardware.
	 *
	 * A distinction is made for overclocking, which is never enabled by
	 * default, and is considered to be above the hard limit if it's
	 * possible at all.
	 */
	u8 cur_freq;		/* Current frequency (cached, may not == HW) */
	u8 min_freq_softlimit;	/* Minimum frequency permitted by the driver */
	u8 max_freq_softlimit;	/* Max frequency permitted by the driver */
	u8 max_freq;		/* Maximum frequency, RP0 if not overclocking */
	u8 min_freq;		/* AKA RPn. Minimum frequency */
1207
	u8 boost_freq;		/* Frequency to request when wait boosting */
1208
	u8 idle_freq;		/* Frequency to request when we are idle */
1209 1210 1211
	u8 efficient_freq;	/* AKA RPe. Pre-determined balanced frequency */
	u8 rp1_freq;		/* "less than" RP0 power/freqency */
	u8 rp0_freq;		/* Non-overclocked max frequency. */
1212
	u16 gpll_ref_freq;	/* vlv/chv GPLL reference frequency */
1213

1214 1215 1216
	u8 up_threshold; /* Current %busy required to uplock */
	u8 down_threshold; /* Current %busy required to downclock */

1217 1218 1219
	int last_adj;
	enum { LOW_POWER, BETWEEN, HIGH_POWER } power;

1220 1221 1222 1223
	spinlock_t client_lock;
	struct list_head clients;
	bool client_boost;

1224
	bool enabled;
1225
	struct delayed_work autoenable_work;
1226
	unsigned boosts;
1227

1228 1229 1230
	/* manual wa residency calculations */
	struct intel_rps_ei up_ei, down_ei;

1231 1232
	/*
	 * Protects RPS/RC6 register access and PCU communication.
1233 1234 1235
	 * Must be taken after struct_mutex if nested. Note that
	 * this lock may be held for long periods of time when
	 * talking to hw - so only take it when talking to hw!
1236 1237
	 */
	struct mutex hw_lock;
1238 1239
};

D
Daniel Vetter 已提交
1240 1241 1242
/* defined intel_pm.c */
extern spinlock_t mchdev_lock;

1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253
struct intel_ilk_power_mgmt {
	u8 cur_delay;
	u8 min_delay;
	u8 max_delay;
	u8 fmax;
	u8 fstart;

	u64 last_count1;
	unsigned long last_time1;
	unsigned long chipset_power;
	u64 last_count2;
1254
	u64 last_time2;
1255 1256 1257 1258 1259 1260 1261
	unsigned long gfx_power;
	u8 corr;

	int c_m;
	int r_t;
};

1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291
struct drm_i915_private;
struct i915_power_well;

struct i915_power_well_ops {
	/*
	 * Synchronize the well's hw state to match the current sw state, for
	 * example enable/disable it based on the current refcount. Called
	 * during driver init and resume time, possibly after first calling
	 * the enable/disable handlers.
	 */
	void (*sync_hw)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/*
	 * Enable the well and resources that depend on it (for example
	 * interrupts located on the well). Called after the 0->1 refcount
	 * transition.
	 */
	void (*enable)(struct drm_i915_private *dev_priv,
		       struct i915_power_well *power_well);
	/*
	 * Disable the well and resources that depend on it. Called after
	 * the 1->0 refcount transition.
	 */
	void (*disable)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/* Returns the hw enabled state. */
	bool (*is_enabled)(struct drm_i915_private *dev_priv,
			   struct i915_power_well *power_well);
};

1292 1293
/* Power well structure for haswell */
struct i915_power_well {
1294
	const char *name;
1295
	bool always_on;
1296 1297
	/* power well enable/disable usage count */
	int count;
1298 1299
	/* cached hw enabled state */
	bool hw_enabled;
1300
	unsigned long domains;
1301
	unsigned long data;
1302
	const struct i915_power_well_ops *ops;
1303 1304
};

1305
struct i915_power_domains {
1306 1307 1308 1309 1310
	/*
	 * Power wells needed for initialization at driver init and suspend
	 * time are on. They are kept on until after the first modeset.
	 */
	bool init_power_on;
1311
	bool initializing;
1312
	int power_well_count;
1313

1314
	struct mutex lock;
1315
	int domain_use_count[POWER_DOMAIN_NUM];
1316
	struct i915_power_well *power_wells;
1317 1318
};

1319
#define MAX_L3_SLICES 2
1320
struct intel_l3_parity {
1321
	u32 *remap_info[MAX_L3_SLICES];
1322
	struct work_struct error_work;
1323
	int which_slice;
1324 1325
};

1326 1327 1328
struct i915_gem_mm {
	/** Memory allocator for GTT stolen memory */
	struct drm_mm stolen;
1329 1330 1331 1332
	/** Protects the usage of the GTT stolen memory allocator. This is
	 * always the inner lock when overlapping with struct_mutex. */
	struct mutex stolen_lock;

1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348
	/** List of all objects in gtt_space. Used to restore gtt
	 * mappings on resume */
	struct list_head bound_list;
	/**
	 * List of objects which are not bound to the GTT (thus
	 * are idle and not used by the GPU) but still have
	 * (presumably uncached) pages still attached.
	 */
	struct list_head unbound_list;

	/** Usable portion of the GTT for GEM */
	unsigned long stolen_base; /* limited to low memory (32-bit) */

	/** PPGTT used for aliasing the PPGTT with the GTT */
	struct i915_hw_ppgtt *aliasing_ppgtt;

1349
	struct notifier_block oom_notifier;
1350
	struct notifier_block vmap_notifier;
1351
	struct shrinker shrinker;
1352 1353 1354 1355 1356 1357 1358 1359 1360 1361

	/** LRU list of objects with fence regs on them. */
	struct list_head fence_list;

	/**
	 * Are we in a non-interruptible section of code like
	 * modesetting?
	 */
	bool interruptible;

1362
	/* the indicator for dispatch video commands on two BSD rings */
1363
	atomic_t bsd_engine_dispatch_index;
1364

1365 1366 1367 1368 1369 1370
	/** Bit 6 swizzling required for X tiling */
	uint32_t bit_6_swizzle_x;
	/** Bit 6 swizzling required for Y tiling */
	uint32_t bit_6_swizzle_y;

	/* accounting, useful for userland debugging */
1371
	spinlock_t object_stat_lock;
1372 1373 1374 1375
	size_t object_memory;
	u32 object_count;
};

1376
struct drm_i915_error_state_buf {
1377
	struct drm_i915_private *i915;
1378 1379 1380 1381 1382 1383 1384 1385
	unsigned bytes;
	unsigned size;
	int err;
	u8 *buf;
	loff_t start;
	loff_t pos;
};

1386 1387 1388 1389 1390
struct i915_error_state_file_priv {
	struct drm_device *dev;
	struct drm_i915_error_state *error;
};

1391 1392 1393 1394
struct i915_gpu_error {
	/* For hangcheck timer */
#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1395 1396 1397
	/* Hang gpu twice in this window and your context gets banned */
#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)

1398
	struct delayed_work hangcheck_work;
1399 1400 1401 1402 1403

	/* For reset and error_state handling. */
	spinlock_t lock;
	/* Protected by the above dev->gpu_error.lock. */
	struct drm_i915_error_state *first_error;
1404 1405 1406

	unsigned long missed_irq_rings;

1407
	/**
M
Mika Kuoppala 已提交
1408
	 * State variable controlling the reset flow and count
1409
	 *
M
Mika Kuoppala 已提交
1410
	 * This is a counter which gets incremented when reset is triggered,
1411 1412 1413 1414
	 *
	 * Before the reset commences, the I915_RESET_IN_PROGRESS bit is set
	 * meaning that any waiters holding onto the struct_mutex should
	 * relinquish the lock immediately in order for the reset to start.
M
Mika Kuoppala 已提交
1415 1416 1417 1418 1419 1420 1421 1422 1423
	 *
	 * If reset is not completed succesfully, the I915_WEDGE bit is
	 * set meaning that hardware is terminally sour and there is no
	 * recovery. All waiters on the reset_queue will be woken when
	 * that happens.
	 *
	 * This counter is used by the wait_seqno code to notice that reset
	 * event happened and it needs to restart the entire ioctl (since most
	 * likely the seqno it waited for won't ever signal anytime soon).
1424 1425 1426 1427
	 *
	 * This is important for lock-free wait paths, where no contended lock
	 * naturally enforces the correct ordering between the bail-out of the
	 * waiter and the gpu reset work code.
1428
	 */
1429
	unsigned long reset_count;
1430

1431 1432 1433
	unsigned long flags;
#define I915_RESET_IN_PROGRESS	0
#define I915_WEDGED		(BITS_PER_LONG - 1)
1434

1435 1436 1437 1438 1439 1440
	/**
	 * Waitqueue to signal when a hang is detected. Used to for waiters
	 * to release the struct_mutex for the reset to procede.
	 */
	wait_queue_head_t wait_queue;

1441 1442 1443 1444 1445
	/**
	 * Waitqueue to signal when the reset has completed. Used by clients
	 * that wait for dev_priv->mm.wedged to settle.
	 */
	wait_queue_head_t reset_queue;
1446

1447
	/* For missed irq/seqno simulation. */
1448
	unsigned long test_irq_rings;
1449 1450
};

1451 1452 1453 1454 1455 1456
enum modeset_restore {
	MODESET_ON_LID_OPEN,
	MODESET_DONE,
	MODESET_SUSPENDED,
};

1457 1458 1459 1460 1461
#define DP_AUX_A 0x40
#define DP_AUX_B 0x10
#define DP_AUX_C 0x20
#define DP_AUX_D 0x30

X
Xiong Zhang 已提交
1462 1463 1464 1465
#define DDC_PIN_B  0x05
#define DDC_PIN_C  0x04
#define DDC_PIN_D  0x06

1466
struct ddi_vbt_port_info {
1467 1468 1469 1470 1471 1472
	/*
	 * This is an index in the HDMI/DVI DDI buffer translation table.
	 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
	 * populate this field.
	 */
#define HDMI_LEVEL_SHIFT_UNKNOWN	0xff
1473
	uint8_t hdmi_level_shift;
1474 1475 1476 1477

	uint8_t supports_dvi:1;
	uint8_t supports_hdmi:1;
	uint8_t supports_dp:1;
1478 1479

	uint8_t alternate_aux_channel;
X
Xiong Zhang 已提交
1480
	uint8_t alternate_ddc_pin;
1481 1482 1483

	uint8_t dp_boost_level;
	uint8_t hdmi_boost_level;
1484 1485
};

R
Rodrigo Vivi 已提交
1486 1487 1488 1489 1490
enum psr_lines_to_wait {
	PSR_0_LINES_TO_WAIT = 0,
	PSR_1_LINE_TO_WAIT,
	PSR_4_LINES_TO_WAIT,
	PSR_8_LINES_TO_WAIT
1491 1492
};

1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504
struct intel_vbt_data {
	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */

	/* Feature bits */
	unsigned int int_tv_support:1;
	unsigned int lvds_dither:1;
	unsigned int lvds_vbt:1;
	unsigned int int_crt_support:1;
	unsigned int lvds_use_ssc:1;
	unsigned int display_clock_mode:1;
	unsigned int fdi_rx_polarity_inverted:1;
1505
	unsigned int panel_type:4;
1506 1507 1508
	int lvds_ssc_freq;
	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */

1509 1510
	enum drrs_support_type drrs_type;

1511 1512 1513 1514 1515
	struct {
		int rate;
		int lanes;
		int preemphasis;
		int vswing;
1516
		bool low_vswing;
1517 1518 1519 1520 1521
		bool initialized;
		bool support;
		int bpp;
		struct edp_power_seq pps;
	} edp;
1522

R
Rodrigo Vivi 已提交
1523 1524 1525 1526 1527 1528 1529 1530 1531
	struct {
		bool full_link;
		bool require_aux_wakeup;
		int idle_frames;
		enum psr_lines_to_wait lines_to_wait;
		int tp1_wakeup_time;
		int tp2_tp3_wakeup_time;
	} psr;

1532 1533
	struct {
		u16 pwm_freq_hz;
1534
		bool present;
1535
		bool active_low_pwm;
1536
		u8 min_brightness;	/* min_brightness/255 of max */
1537
		enum intel_backlight_type type;
1538 1539
	} backlight;

1540 1541 1542
	/* MIPI DSI */
	struct {
		u16 panel_id;
1543 1544 1545 1546 1547
		struct mipi_config *config;
		struct mipi_pps_data *pps;
		u8 seq_version;
		u32 size;
		u8 *data;
1548
		const u8 *sequence[MIPI_SEQ_MAX];
1549 1550
	} dsi;

1551 1552 1553
	int crt_ddc_pin;

	int child_dev_num;
1554
	union child_device_config *child_dev;
1555 1556

	struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1557
	struct sdvo_device_mapping sdvo_mappings[2];
1558 1559
};

1560 1561 1562 1563 1564
enum intel_ddb_partitioning {
	INTEL_DDB_PART_1_2,
	INTEL_DDB_PART_5_6, /* IVB+ */
};

1565 1566 1567 1568 1569 1570 1571 1572
struct intel_wm_level {
	bool enable;
	uint32_t pri_val;
	uint32_t spr_val;
	uint32_t cur_val;
	uint32_t fbc_val;
};

1573
struct ilk_wm_values {
1574 1575 1576 1577 1578 1579 1580 1581
	uint32_t wm_pipe[3];
	uint32_t wm_lp[3];
	uint32_t wm_lp_spr[3];
	uint32_t wm_linetime[3];
	bool enable_fbc_wm;
	enum intel_ddb_partitioning partitioning;
};

1582 1583 1584 1585 1586
struct vlv_pipe_wm {
	uint16_t primary;
	uint16_t sprite[2];
	uint8_t cursor;
};
1587

1588 1589 1590 1591
struct vlv_sr_wm {
	uint16_t plane;
	uint8_t cursor;
};
1592

1593 1594 1595
struct vlv_wm_values {
	struct vlv_pipe_wm pipe[3];
	struct vlv_sr_wm sr;
1596 1597 1598 1599 1600
	struct {
		uint8_t cursor;
		uint8_t sprite[2];
		uint8_t primary;
	} ddl[3];
1601 1602
	uint8_t level;
	bool cxsr;
1603 1604
};

1605
struct skl_ddb_entry {
1606
	uint16_t start, end;	/* in number of blocks, 'end' is exclusive */
1607 1608 1609 1610
};

static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
{
1611
	return entry->end - entry->start;
1612 1613
}

1614 1615 1616 1617 1618 1619 1620 1621 1622
static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
				       const struct skl_ddb_entry *e2)
{
	if (e1->start == e2->start && e1->end == e2->end)
		return true;

	return false;
}

1623
struct skl_ddb_allocation {
1624
	struct skl_ddb_entry pipe[I915_MAX_PIPES];
1625
	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1626
	struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1627 1628
};

1629
struct skl_wm_values {
1630
	unsigned dirty_pipes;
1631
	struct skl_ddb_allocation ddb;
1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642
	uint32_t wm_linetime[I915_MAX_PIPES];
	uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
	uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
};

struct skl_wm_level {
	bool plane_en[I915_MAX_PLANES];
	uint16_t plane_res_b[I915_MAX_PLANES];
	uint8_t plane_res_l[I915_MAX_PLANES];
};

1643
/*
1644 1645 1646 1647
 * This struct helps tracking the state needed for runtime PM, which puts the
 * device in PCI D3 state. Notice that when this happens, nothing on the
 * graphics device works, even register access, so we don't get interrupts nor
 * anything else.
1648
 *
1649 1650 1651
 * Every piece of our code that needs to actually touch the hardware needs to
 * either call intel_runtime_pm_get or call intel_display_power_get with the
 * appropriate power domain.
1652
 *
1653 1654
 * Our driver uses the autosuspend delay feature, which means we'll only really
 * suspend if we stay with zero refcount for a certain amount of time. The
1655
 * default value is currently very conservative (see intel_runtime_pm_enable), but
1656
 * it can be changed with the standard runtime PM files from sysfs.
1657 1658 1659 1660 1661
 *
 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
 * goes back to false exactly before we reenable the IRQs. We use this variable
 * to check if someone is trying to enable/disable IRQs while they're supposed
 * to be disabled. This shouldn't happen and we'll print some error messages in
1662
 * case it happens.
1663
 *
1664
 * For more, read the Documentation/power/runtime_pm.txt.
1665
 */
1666
struct i915_runtime_pm {
1667
	atomic_t wakeref_count;
1668
	atomic_t atomic_seq;
1669
	bool suspended;
1670
	bool irqs_enabled;
1671 1672
};

1673 1674 1675 1676 1677
enum intel_pipe_crc_source {
	INTEL_PIPE_CRC_SOURCE_NONE,
	INTEL_PIPE_CRC_SOURCE_PLANE1,
	INTEL_PIPE_CRC_SOURCE_PLANE2,
	INTEL_PIPE_CRC_SOURCE_PF,
1678
	INTEL_PIPE_CRC_SOURCE_PIPE,
D
Daniel Vetter 已提交
1679 1680 1681 1682 1683
	/* TV/DP on pre-gen5/vlv can't use the pipe source. */
	INTEL_PIPE_CRC_SOURCE_TV,
	INTEL_PIPE_CRC_SOURCE_DP_B,
	INTEL_PIPE_CRC_SOURCE_DP_C,
	INTEL_PIPE_CRC_SOURCE_DP_D,
1684
	INTEL_PIPE_CRC_SOURCE_AUTO,
1685 1686 1687
	INTEL_PIPE_CRC_SOURCE_MAX,
};

1688
struct intel_pipe_crc_entry {
1689
	uint32_t frame;
1690 1691 1692
	uint32_t crc[5];
};

1693
#define INTEL_PIPE_CRC_ENTRIES_NR	128
1694
struct intel_pipe_crc {
1695 1696
	spinlock_t lock;
	bool opened;		/* exclusive access to the result file */
1697
	struct intel_pipe_crc_entry *entries;
1698
	enum intel_pipe_crc_source source;
1699
	int head, tail;
1700
	wait_queue_head_t wq;
1701 1702
};

1703
struct i915_frontbuffer_tracking {
1704
	spinlock_t lock;
1705 1706 1707 1708 1709 1710 1711 1712 1713

	/*
	 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
	 * scheduled flips.
	 */
	unsigned busy_bits;
	unsigned flip_bits;
};

1714
struct i915_wa_reg {
1715
	i915_reg_t addr;
1716 1717 1718 1719 1720
	u32 value;
	/* bitmask representing WA bits */
	u32 mask;
};

1721 1722 1723 1724 1725 1726 1727
/*
 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
 * allowing it for RCS as we don't foresee any requirement of having
 * a whitelist for other engines. When it is really required for
 * other engines then the limit need to be increased.
 */
#define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1728 1729 1730 1731

struct i915_workarounds {
	struct i915_wa_reg reg[I915_MAX_WA_REGS];
	u32 count;
1732
	u32 hw_whitelist_count[I915_NUM_ENGINES];
1733 1734
};

1735 1736 1737 1738
struct i915_virtual_gpu {
	bool active;
};

1739 1740 1741 1742 1743 1744 1745
/* used in computing the new watermarks state */
struct intel_wm_config {
	unsigned int num_pipes_active;
	bool sprites_enabled;
	bool sprites_scaled;
};

1746
struct drm_i915_private {
1747 1748
	struct drm_device drm;

1749
	struct kmem_cache *objects;
1750
	struct kmem_cache *vmas;
1751
	struct kmem_cache *requests;
1752

1753
	const struct intel_device_info info;
1754 1755 1756 1757 1758

	int relative_constants_mode;

	void __iomem *regs;

1759
	struct intel_uncore uncore;
1760

1761 1762
	struct i915_virtual_gpu vgpu;

1763 1764
	struct intel_gvt gvt;

1765 1766
	struct intel_guc guc;

1767 1768
	struct intel_csr csr;

1769
	struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1770

1771 1772 1773 1774 1775 1776 1777 1778 1779
	/** gmbus_mutex protects against concurrent usage of the single hw gmbus
	 * controller on different i2c buses. */
	struct mutex gmbus_mutex;

	/**
	 * Base address of the gmbus and gpio block.
	 */
	uint32_t gpio_mmio_base;

1780 1781 1782
	/* MMIO base address for MIPI regs */
	uint32_t mipi_mmio_base;

1783 1784
	uint32_t psr_mmio_base;

1785 1786
	uint32_t pps_mmio_base;

1787 1788
	wait_queue_head_t gmbus_wait_queue;

1789
	struct pci_dev *bridge_dev;
1790
	struct i915_gem_context *kernel_context;
1791
	struct intel_engine_cs engine[I915_NUM_ENGINES];
1792
	struct i915_vma *semaphore;
1793
	u32 next_seqno;
1794

1795
	struct drm_dma_handle *status_page_dmah;
1796 1797 1798 1799 1800
	struct resource mch_res;

	/* protects the irq masks */
	spinlock_t irq_lock;

1801 1802 1803
	/* protects the mmio flip data */
	spinlock_t mmio_flip_lock;

1804 1805
	bool display_irqs_enabled;

1806 1807 1808
	/* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
	struct pm_qos_request pm_qos;

V
Ville Syrjälä 已提交
1809 1810
	/* Sideband mailbox protection */
	struct mutex sb_lock;
1811 1812

	/** Cached value of IMR to avoid reads in updating the bitfield */
1813 1814 1815 1816
	union {
		u32 irq_mask;
		u32 de_irq_mask[I915_MAX_PIPES];
	};
1817
	u32 gt_irq_mask;
1818
	u32 pm_irq_mask;
1819
	u32 pm_rps_events;
1820
	u32 pipestat_irq_mask[I915_MAX_PIPES];
1821

1822
	struct i915_hotplug hotplug;
1823
	struct intel_fbc fbc;
1824
	struct i915_drrs drrs;
1825
	struct intel_opregion opregion;
1826
	struct intel_vbt_data vbt;
1827

1828 1829
	bool preserve_bios_swizzle;

1830 1831 1832
	/* overlay */
	struct intel_overlay *overlay;

1833
	/* backlight registers and fields in struct intel_panel */
1834
	struct mutex backlight_lock;
1835

1836 1837 1838
	/* LVDS info */
	bool no_aux_handshake;

V
Ville Syrjälä 已提交
1839 1840 1841
	/* protects panel power sequencer state */
	struct mutex pps_mutex;

1842 1843 1844 1845
	struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
	int num_fence_regs; /* 8 on pre-965, 16 otherwise */

	unsigned int fsb_freq, mem_freq, is_ddr3;
1846
	unsigned int skl_preferred_vco_freq;
1847
	unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
M
Mika Kahola 已提交
1848
	unsigned int max_dotclk_freq;
1849
	unsigned int rawclk_freq;
1850
	unsigned int hpll_freq;
1851
	unsigned int czclk_freq;
1852

1853
	struct {
1854
		unsigned int vco, ref;
1855 1856
	} cdclk_pll;

1857 1858 1859 1860 1861 1862 1863
	/**
	 * wq - Driver workqueue for GEM.
	 *
	 * NOTE: Work items scheduled here are not allowed to grab any modeset
	 * locks, for otherwise the flushing done in the pageflip code will
	 * result in deadlocks.
	 */
1864 1865 1866 1867 1868 1869 1870
	struct workqueue_struct *wq;

	/* Display functions */
	struct drm_i915_display_funcs display;

	/* PCH chipset type */
	enum intel_pch pch_type;
1871
	unsigned short pch_id;
1872 1873 1874

	unsigned long quirks;

1875 1876
	enum modeset_restore modeset_restore;
	struct mutex modeset_restore_lock;
1877
	struct drm_atomic_state *modeset_restore_state;
1878
	struct drm_modeset_acquire_ctx reset_ctx;
1879

1880
	struct list_head vm_list; /* Global list of all address spaces */
1881
	struct i915_ggtt ggtt; /* VM representing the global address space */
B
Ben Widawsky 已提交
1882

1883
	struct i915_gem_mm mm;
1884 1885
	DECLARE_HASHTABLE(mm_structs, 7);
	struct mutex mm_lock;
1886

1887 1888 1889 1890 1891 1892 1893
	/* The hw wants to have a stable context identifier for the lifetime
	 * of the context (for OA, PASID, faults, etc). This is limited
	 * in execlists to 21 bits.
	 */
	struct ida context_hw_ida;
#define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */

1894 1895
	/* Kernel Modesetting */

1896 1897
	struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
	struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1898 1899
	wait_queue_head_t pending_flip_queue;

1900 1901 1902 1903
#ifdef CONFIG_DEBUG_FS
	struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
#endif

1904
	/* dpll and cdclk state is protected by connection_mutex */
D
Daniel Vetter 已提交
1905 1906
	int num_shared_dpll;
	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1907
	const struct intel_dpll_mgr *dpll_mgr;
1908

1909 1910 1911 1912 1913 1914 1915
	/*
	 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
	 * Must be global rather than per dpll, because on some platforms
	 * plls share registers.
	 */
	struct mutex dpll_lock;

1916 1917 1918
	unsigned int active_crtcs;
	unsigned int min_pixclk[I915_MAX_PIPES];

1919
	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1920

1921
	struct i915_workarounds workarounds;
1922

1923 1924
	struct i915_frontbuffer_tracking fb_tracking;

1925
	u16 orig_clock;
1926

1927
	bool mchbar_need_disable;
1928

1929 1930
	struct intel_l3_parity l3_parity;

B
Ben Widawsky 已提交
1931
	/* Cannot be determined by PCIID. You must always read a register. */
1932
	u32 edram_cap;
B
Ben Widawsky 已提交
1933

1934
	/* gen6+ rps state */
1935
	struct intel_gen6_power_mgmt rps;
1936

1937 1938
	/* ilk-only ips/rps state. Everything in here is protected by the global
	 * mchdev_lock in intel_pm.c */
1939
	struct intel_ilk_power_mgmt ips;
1940

1941
	struct i915_power_domains power_domains;
1942

R
Rodrigo Vivi 已提交
1943
	struct i915_psr psr;
1944

1945
	struct i915_gpu_error gpu_error;
1946

1947 1948
	struct drm_i915_gem_object *vlv_pctx;

1949
#ifdef CONFIG_DRM_FBDEV_EMULATION
1950 1951
	/* list of fbdev register on this device */
	struct intel_fbdev *fbdev;
1952
	struct work_struct fbdev_suspend_work;
1953
#endif
1954 1955

	struct drm_property *broadcast_rgb_property;
1956
	struct drm_property *force_audio_property;
1957

I
Imre Deak 已提交
1958
	/* hda/i915 audio component */
1959
	struct i915_audio_component *audio_component;
I
Imre Deak 已提交
1960
	bool audio_component_registered;
1961 1962 1963 1964 1965
	/**
	 * av_mutex - mutex for audio/video sync
	 *
	 */
	struct mutex av_mutex;
I
Imre Deak 已提交
1966

1967
	uint32_t hw_context_size;
1968
	struct list_head context_list;
1969

1970
	u32 fdi_rx_config;
1971

1972
	/* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1973
	u32 chv_phy_control;
1974 1975 1976 1977 1978 1979
	/*
	 * Shadows for CHV DPLL_MD regs to keep the state
	 * checker somewhat working in the presence hardware
	 * crappiness (can't read out DPLL_MD for pipes B & C).
	 */
	u32 chv_dpll_md[I915_MAX_PIPES];
1980
	u32 bxt_phy_grc;
1981

1982
	u32 suspend_count;
1983
	bool suspended_to_idle;
1984
	struct i915_suspend_saved_registers regfile;
1985
	struct vlv_s0ix_state vlv_s0ix_state;
1986

1987 1988 1989 1990 1991 1992 1993
	enum {
		I915_SKL_SAGV_UNKNOWN = 0,
		I915_SKL_SAGV_DISABLED,
		I915_SKL_SAGV_ENABLED,
		I915_SKL_SAGV_NOT_CONTROLLED
	} skl_sagv_status;

1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005
	struct {
		/*
		 * Raw watermark latency values:
		 * in 0.1us units for WM0,
		 * in 0.5us units for WM1+.
		 */
		/* primary */
		uint16_t pri_latency[5];
		/* sprite */
		uint16_t spr_latency[5];
		/* cursor */
		uint16_t cur_latency[5];
2006 2007 2008 2009 2010 2011
		/*
		 * Raw watermark memory latency values
		 * for SKL for all 8 levels
		 * in 1us units.
		 */
		uint16_t skl_latency[8];
2012

2013 2014 2015 2016 2017 2018 2019
		/*
		 * The skl_wm_values structure is a bit too big for stack
		 * allocation, so we keep the staging struct where we store
		 * intermediate results here instead.
		 */
		struct skl_wm_values skl_results;

2020
		/* current hardware state */
2021 2022 2023
		union {
			struct ilk_wm_values hw;
			struct skl_wm_values skl_hw;
2024
			struct vlv_wm_values vlv;
2025
		};
2026 2027

		uint8_t max_level;
2028 2029 2030 2031 2032 2033 2034

		/*
		 * Should be held around atomic WM register writing; also
		 * protects * intel_crtc->wm.active and
		 * cstate->wm.need_postvbl_update.
		 */
		struct mutex wm_mutex;
2035 2036 2037 2038 2039 2040 2041

		/*
		 * Set during HW readout of watermarks/DDB.  Some platforms
		 * need to know when we're still using BIOS-provided values
		 * (which we don't fully trust).
		 */
		bool distrust_bios_wm;
2042 2043
	} wm;

2044 2045
	struct i915_runtime_pm pm;

2046 2047
	/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
	struct {
2048
		void (*resume)(struct drm_i915_private *);
2049
		void (*cleanup_engine)(struct intel_engine_cs *engine);
2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077

		/**
		 * Is the GPU currently considered idle, or busy executing
		 * userspace requests? Whilst idle, we allow runtime power
		 * management to power down the hardware and display clocks.
		 * In order to reduce the effect on performance, there
		 * is a slight delay before we do so.
		 */
		unsigned int active_engines;
		bool awake;

		/**
		 * We leave the user IRQ off as much as possible,
		 * but this means that requests will finish and never
		 * be retired once the system goes idle. Set a timer to
		 * fire periodically while the ring is running. When it
		 * fires, go retire requests.
		 */
		struct delayed_work retire_work;

		/**
		 * When we detect an idle GPU, we want to turn on
		 * powersaving features. So once we see that there
		 * are no more requests outstanding and no more
		 * arrive within a small period of time, we fire
		 * off the idle_work.
		 */
		struct delayed_work idle_work;
2078 2079
	} gt;

2080 2081 2082
	/* perform PHY state sanity checks? */
	bool chv_phy_assert[2];

2083 2084
	struct intel_encoder *dig_port_map[I915_MAX_PORTS];

2085 2086 2087 2088
	/*
	 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
	 * will be rejected. Instead look for a better place.
	 */
2089
};
L
Linus Torvalds 已提交
2090

2091 2092
static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
{
2093
	return container_of(dev, struct drm_i915_private, drm);
2094 2095
}

2096
static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
I
Imre Deak 已提交
2097
{
2098
	return to_i915(dev_get_drvdata(kdev));
I
Imre Deak 已提交
2099 2100
}

2101 2102 2103 2104 2105
static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
{
	return container_of(guc, struct drm_i915_private, guc);
}

2106 2107 2108 2109 2110 2111
/* Simple iterator over all initialised engines */
#define for_each_engine(engine__, dev_priv__) \
	for ((engine__) = &(dev_priv__)->engine[0]; \
	     (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
	     (engine__)++) \
		for_each_if (intel_engine_initialized(engine__))
2112

2113 2114 2115 2116 2117 2118 2119 2120
/* Iterator with engine_id */
#define for_each_engine_id(engine__, dev_priv__, id__) \
	for ((engine__) = &(dev_priv__)->engine[0], (id__) = 0; \
	     (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
	     (engine__)++) \
		for_each_if (((id__) = (engine__)->id, \
			      intel_engine_initialized(engine__)))

2121 2122 2123 2124 2125 2126
#define __mask_next_bit(mask) ({					\
	int __idx = ffs(mask) - 1;					\
	mask &= ~BIT(__idx);						\
	__idx;								\
})

2127
/* Iterator over subset of engines selected by mask */
2128 2129 2130
#define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
	for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask;	\
	     tmp__ ? (engine__ = &(dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2131

2132 2133 2134 2135 2136 2137 2138
enum hdmi_force_audio {
	HDMI_AUDIO_OFF_DVI = -2,	/* no aux data for HDMI-DVI converter */
	HDMI_AUDIO_OFF,			/* force turn off HDMI audio */
	HDMI_AUDIO_AUTO,		/* trust EDID */
	HDMI_AUDIO_ON,			/* force turn on HDMI audio */
};

2139
#define I915_GTT_OFFSET_NONE ((u32)-1)
2140

2141
struct drm_i915_gem_object_ops {
2142 2143 2144
	unsigned int flags;
#define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1

2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159
	/* Interface between the GEM object and its backing storage.
	 * get_pages() is called once prior to the use of the associated set
	 * of pages before to binding them into the GTT, and put_pages() is
	 * called after we no longer need them. As we expect there to be
	 * associated cost with migrating pages between the backing storage
	 * and making them available for the GPU (e.g. clflush), we may hold
	 * onto the pages after they are no longer referenced by the GPU
	 * in case they may be used again shortly (for example migrating the
	 * pages to a different memory domain within the GTT). put_pages()
	 * will therefore most likely be called when the object itself is
	 * being released or under memory pressure (where we attempt to
	 * reap pages for the shrinker).
	 */
	int (*get_pages)(struct drm_i915_gem_object *);
	void (*put_pages)(struct drm_i915_gem_object *);
2160

2161 2162
	int (*dmabuf_export)(struct drm_i915_gem_object *);
	void (*release)(struct drm_i915_gem_object *);
2163 2164
};

2165 2166
/*
 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2167
 * considered to be the frontbuffer for the given plane interface-wise. This
2168 2169 2170 2171 2172
 * doesn't mean that the hw necessarily already scans it out, but that any
 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
 *
 * We have one bit per pipe and per scanout plane type.
 */
2173 2174
#define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2175 2176 2177
#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
	(1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
#define INTEL_FRONTBUFFER_CURSOR(pipe) \
2178 2179 2180
	(1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
#define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
	(1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2181
#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2182
	(1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2183
#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2184
	(0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2185

2186
struct drm_i915_gem_object {
2187
	struct drm_gem_object base;
2188

2189 2190
	const struct drm_i915_gem_object_ops *ops;

B
Ben Widawsky 已提交
2191 2192 2193
	/** List of VMAs backed by this object */
	struct list_head vma_list;

2194 2195
	/** Stolen memory for this object, instead of being backed by shmem. */
	struct drm_mm_node *stolen;
2196
	struct list_head global_list;
2197

2198 2199
	/** Used in execbuf to temporarily hold a ref */
	struct list_head obj_exec_link;
2200

2201
	struct list_head batch_pool_link;
2202

2203
	unsigned long flags;
2204
	/**
2205 2206 2207
	 * This is set if the object is on the active lists (has pending
	 * rendering and so a non-zero seqno), and is not set if it i s on
	 * inactive (ready to be unbound) list.
2208
	 */
2209 2210 2211 2212
#define I915_BO_ACTIVE_SHIFT 0
#define I915_BO_ACTIVE_MASK ((1 << I915_NUM_ENGINES) - 1)
#define __I915_BO_ACTIVE(bo) \
	((READ_ONCE((bo)->flags) >> I915_BO_ACTIVE_SHIFT) & I915_BO_ACTIVE_MASK)
2213 2214 2215 2216 2217

	/**
	 * This is set if the object has been written to since last bound
	 * to the GTT
	 */
2218
	unsigned int dirty:1;
2219 2220 2221 2222

	/**
	 * Advice: are the backing pages purgeable?
	 */
2223
	unsigned int madv:2;
2224

2225 2226 2227 2228 2229
	/**
	 * Whether the current gtt mapping needs to be mappable (and isn't just
	 * mappable by accident). Track pin and fault separate for a more
	 * accurate mappable working set.
	 */
2230
	unsigned int fault_mappable:1;
2231

2232 2233 2234 2235 2236
	/*
	 * Is the object to be mapped as read-only to the GPU
	 * Only honoured if hardware has relevant pte bit
	 */
	unsigned long gt_ro:1;
2237
	unsigned int cache_level:3;
2238
	unsigned int cache_dirty:1;
2239

2240
	atomic_t frontbuffer_bits;
2241
	unsigned int frontbuffer_ggtt_origin; /* write once */
2242

2243
	/** Current tiling stride for the object, if it's tiled. */
2244 2245 2246 2247
	unsigned int tiling_and_stride;
#define FENCE_MINIMUM_STRIDE 128 /* See i915_tiling_ok() */
#define TILING_MASK (FENCE_MINIMUM_STRIDE-1)
#define STRIDE_MASK (~TILING_MASK)
2248

2249 2250
	/** Count of VMA actually bound by this object */
	unsigned int bind_count;
2251 2252
	unsigned int pin_display;

2253
	struct sg_table *pages;
2254
	int pages_pin_count;
2255 2256 2257 2258
	struct get_page {
		struct scatterlist *sg;
		int last;
	} get_page;
2259
	void *mapping;
2260

2261 2262 2263 2264 2265 2266 2267 2268 2269
	/** Breadcrumb of last rendering to the buffer.
	 * There can only be one writer, but we allow for multiple readers.
	 * If there is a writer that necessarily implies that all other
	 * read requests are complete - but we may only be lazily clearing
	 * the read requests. A read request is naturally the most recent
	 * request on a ring, so we may have two different write and read
	 * requests on one ring where the write request is older than the
	 * read request. This allows for the CPU to read from an active
	 * buffer by only waiting for the write to complete.
2270 2271 2272
	 */
	struct i915_gem_active last_read[I915_NUM_ENGINES];
	struct i915_gem_active last_write;
2273

2274 2275 2276
	/** References from framebuffers, locks out tiling changes. */
	unsigned long framebuffer_references;

2277
	/** Record of address bit 17 of each page at last unbind. */
2278
	unsigned long *bit_17;
2279

2280
	union {
2281 2282 2283
		/** for phy allocated objects */
		struct drm_dma_handle *phys_handle;

2284 2285 2286 2287 2288 2289
		struct i915_gem_userptr {
			uintptr_t ptr;
			unsigned read_only :1;
			unsigned workers :4;
#define I915_GEM_USERPTR_MAX_WORKERS 15

2290 2291
			struct i915_mm_struct *mm;
			struct i915_mmu_object *mmu_object;
2292 2293 2294 2295
			struct work_struct *work;
		} userptr;
	};
};
2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314

static inline struct drm_i915_gem_object *
to_intel_bo(struct drm_gem_object *gem)
{
	/* Assert that to_intel_bo(NULL) == NULL */
	BUILD_BUG_ON(offsetof(struct drm_i915_gem_object, base));

	return container_of(gem, struct drm_i915_gem_object, base);
}

static inline struct drm_i915_gem_object *
i915_gem_object_lookup(struct drm_file *file, u32 handle)
{
	return to_intel_bo(drm_gem_object_lookup(file, handle));
}

__deprecated
extern struct drm_gem_object *
drm_gem_object_lookup(struct drm_file *file, u32 handle);
2315

2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326
__attribute__((nonnull))
static inline struct drm_i915_gem_object *
i915_gem_object_get(struct drm_i915_gem_object *obj)
{
	drm_gem_object_reference(&obj->base);
	return obj;
}

__deprecated
extern void drm_gem_object_reference(struct drm_gem_object *);

2327 2328 2329 2330 2331 2332 2333 2334 2335 2336
__attribute__((nonnull))
static inline void
i915_gem_object_put(struct drm_i915_gem_object *obj)
{
	drm_gem_object_unreference(&obj->base);
}

__deprecated
extern void drm_gem_object_unreference(struct drm_gem_object *);

2337 2338 2339 2340 2341 2342 2343 2344 2345 2346
__attribute__((nonnull))
static inline void
i915_gem_object_put_unlocked(struct drm_i915_gem_object *obj)
{
	drm_gem_object_unreference_unlocked(&obj->base);
}

__deprecated
extern void drm_gem_object_unreference_unlocked(struct drm_gem_object *);

2347 2348 2349 2350 2351 2352
static inline bool
i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj)
{
	return obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE;
}

2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383
static inline unsigned long
i915_gem_object_get_active(const struct drm_i915_gem_object *obj)
{
	return (obj->flags >> I915_BO_ACTIVE_SHIFT) & I915_BO_ACTIVE_MASK;
}

static inline bool
i915_gem_object_is_active(const struct drm_i915_gem_object *obj)
{
	return i915_gem_object_get_active(obj);
}

static inline void
i915_gem_object_set_active(struct drm_i915_gem_object *obj, int engine)
{
	obj->flags |= BIT(engine + I915_BO_ACTIVE_SHIFT);
}

static inline void
i915_gem_object_clear_active(struct drm_i915_gem_object *obj, int engine)
{
	obj->flags &= ~BIT(engine + I915_BO_ACTIVE_SHIFT);
}

static inline bool
i915_gem_object_has_active_engine(const struct drm_i915_gem_object *obj,
				  int engine)
{
	return obj->flags & BIT(engine + I915_BO_ACTIVE_SHIFT);
}

2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401
static inline unsigned int
i915_gem_object_get_tiling(struct drm_i915_gem_object *obj)
{
	return obj->tiling_and_stride & TILING_MASK;
}

static inline bool
i915_gem_object_is_tiled(struct drm_i915_gem_object *obj)
{
	return i915_gem_object_get_tiling(obj) != I915_TILING_NONE;
}

static inline unsigned int
i915_gem_object_get_stride(struct drm_i915_gem_object *obj)
{
	return obj->tiling_and_stride & STRIDE_MASK;
}

2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413
static inline struct i915_vma *i915_vma_get(struct i915_vma *vma)
{
	i915_gem_object_get(vma->obj);
	return vma;
}

static inline void i915_vma_put(struct i915_vma *vma)
{
	lockdep_assert_held(&vma->vm->dev->struct_mutex);
	i915_gem_object_put(vma->obj);
}

2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439
/*
 * Optimised SGL iterator for GEM objects
 */
static __always_inline struct sgt_iter {
	struct scatterlist *sgp;
	union {
		unsigned long pfn;
		dma_addr_t dma;
	};
	unsigned int curr;
	unsigned int max;
} __sgt_iter(struct scatterlist *sgl, bool dma) {
	struct sgt_iter s = { .sgp = sgl };

	if (s.sgp) {
		s.max = s.curr = s.sgp->offset;
		s.max += s.sgp->length;
		if (dma)
			s.dma = sg_dma_address(s.sgp);
		else
			s.pfn = page_to_pfn(sg_page(s.sgp));
	}

	return s;
}

2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458
/**
 * __sg_next - return the next scatterlist entry in a list
 * @sg:		The current sg entry
 *
 * Description:
 *   If the entry is the last, return NULL; otherwise, step to the next
 *   element in the array (@sg@+1). If that's a chain pointer, follow it;
 *   otherwise just return the pointer to the current element.
 **/
static inline struct scatterlist *__sg_next(struct scatterlist *sg)
{
#ifdef CONFIG_DEBUG_SG
	BUG_ON(sg->sg_magic != SG_MAGIC);
#endif
	return sg_is_last(sg) ? NULL :
		likely(!sg_is_chain(++sg)) ? sg :
		sg_chain_ptr(sg);
}

2459 2460 2461 2462 2463 2464 2465 2466 2467 2468
/**
 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
 * @__dmap:	DMA address (output)
 * @__iter:	'struct sgt_iter' (iterator state, internal)
 * @__sgt:	sg_table to iterate over (input)
 */
#define for_each_sgt_dma(__dmap, __iter, __sgt)				\
	for ((__iter) = __sgt_iter((__sgt)->sgl, true);			\
	     ((__dmap) = (__iter).dma + (__iter).curr);			\
	     (((__iter).curr += PAGE_SIZE) < (__iter).max) ||		\
2469
	     ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481

/**
 * for_each_sgt_page - iterate over the pages of the given sg_table
 * @__pp:	page pointer (output)
 * @__iter:	'struct sgt_iter' (iterator state, internal)
 * @__sgt:	sg_table to iterate over (input)
 */
#define for_each_sgt_page(__pp, __iter, __sgt)				\
	for ((__iter) = __sgt_iter((__sgt)->sgl, false);		\
	     ((__pp) = (__iter).pfn == 0 ? NULL :			\
	      pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
	     (((__iter).curr += PAGE_SIZE) < (__iter).max) ||		\
2482
	     ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2483

2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535
/*
 * A command that requires special handling by the command parser.
 */
struct drm_i915_cmd_descriptor {
	/*
	 * Flags describing how the command parser processes the command.
	 *
	 * CMD_DESC_FIXED: The command has a fixed length if this is set,
	 *                 a length mask if not set
	 * CMD_DESC_SKIP: The command is allowed but does not follow the
	 *                standard length encoding for the opcode range in
	 *                which it falls
	 * CMD_DESC_REJECT: The command is never allowed
	 * CMD_DESC_REGISTER: The command should be checked against the
	 *                    register whitelist for the appropriate ring
	 * CMD_DESC_MASTER: The command is allowed if the submitting process
	 *                  is the DRM master
	 */
	u32 flags;
#define CMD_DESC_FIXED    (1<<0)
#define CMD_DESC_SKIP     (1<<1)
#define CMD_DESC_REJECT   (1<<2)
#define CMD_DESC_REGISTER (1<<3)
#define CMD_DESC_BITMASK  (1<<4)
#define CMD_DESC_MASTER   (1<<5)

	/*
	 * The command's unique identification bits and the bitmask to get them.
	 * This isn't strictly the opcode field as defined in the spec and may
	 * also include type, subtype, and/or subop fields.
	 */
	struct {
		u32 value;
		u32 mask;
	} cmd;

	/*
	 * The command's length. The command is either fixed length (i.e. does
	 * not include a length field) or has a length field mask. The flag
	 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
	 * a length mask. All command entries in a command table must include
	 * length information.
	 */
	union {
		u32 fixed;
		u32 mask;
	} length;

	/*
	 * Describes where to find a register address in the command to check
	 * against the ring's register whitelist. Only valid if flags has the
	 * CMD_DESC_REGISTER bit set.
2536 2537 2538 2539
	 *
	 * A non-zero step value implies that the command may access multiple
	 * registers in sequence (e.g. LRI), in that case step gives the
	 * distance in dwords between individual offset fields.
2540 2541 2542 2543
	 */
	struct {
		u32 offset;
		u32 mask;
2544
		u32 step;
2545 2546 2547 2548 2549 2550 2551 2552 2553
	} reg;

#define MAX_CMD_DESC_BITMASKS 3
	/*
	 * Describes command checks where a particular dword is masked and
	 * compared against an expected value. If the command does not match
	 * the expected value, the parser rejects it. Only valid if flags has
	 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
	 * are valid.
2554 2555 2556 2557
	 *
	 * If the check specifies a non-zero condition_mask then the parser
	 * only performs the check when the bits specified by condition_mask
	 * are non-zero.
2558 2559 2560 2561 2562
	 */
	struct {
		u32 offset;
		u32 mask;
		u32 expected;
2563 2564
		u32 condition_offset;
		u32 condition_mask;
2565 2566 2567 2568 2569 2570
	} bits[MAX_CMD_DESC_BITMASKS];
};

/*
 * A table of commands requiring special handling by the command parser.
 *
2571 2572 2573
 * Each engine has an array of tables. Each table consists of an array of
 * command descriptors, which must be sorted with command opcodes in
 * ascending order.
2574 2575 2576 2577 2578 2579
 */
struct drm_i915_cmd_table {
	const struct drm_i915_cmd_descriptor *table;
	int count;
};

C
Chris Wilson 已提交
2580
/* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2581 2582 2583 2584 2585 2586 2587 2588 2589 2590
#define __I915__(p) ({ \
	struct drm_i915_private *__p; \
	if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
		__p = (struct drm_i915_private *)p; \
	else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
		__p = to_i915((struct drm_device *)p); \
	else \
		BUILD_BUG(); \
	__p; \
})
2591
#define INTEL_INFO(p)	(&__I915__(p)->info)
2592
#define INTEL_GEN(p)	(INTEL_INFO(p)->gen)
2593
#define INTEL_DEVID(p)	(INTEL_INFO(p)->device_id)
2594

2595
#define REVID_FOREVER		0xff
2596
#define INTEL_REVID(p)	(__I915__(p)->drm.pdev->revision)
2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616

#define GEN_FOREVER (0)
/*
 * Returns true if Gen is in inclusive range [Start, End].
 *
 * Use GEN_FOREVER for unbound start and or end.
 */
#define IS_GEN(p, s, e) ({ \
	unsigned int __s = (s), __e = (e); \
	BUILD_BUG_ON(!__builtin_constant_p(s)); \
	BUILD_BUG_ON(!__builtin_constant_p(e)); \
	if ((__s) != GEN_FOREVER) \
		__s = (s) - 1; \
	if ((__e) == GEN_FOREVER) \
		__e = BITS_PER_LONG - 1; \
	else \
		__e = (e) - 1; \
	!!(INTEL_INFO(p)->gen_mask & GENMASK((__e), (__s))); \
})

2617 2618 2619 2620 2621 2622 2623 2624
/*
 * Return true if revision is in range [since,until] inclusive.
 *
 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
 */
#define IS_REVID(p, since, until) \
	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))

2625 2626
#define IS_I830(dev)		(INTEL_DEVID(dev) == 0x3577)
#define IS_845G(dev)		(INTEL_DEVID(dev) == 0x2562)
2627
#define IS_I85X(dev)		(INTEL_INFO(dev)->is_i85x)
2628
#define IS_I865G(dev)		(INTEL_DEVID(dev) == 0x2572)
2629
#define IS_I915G(dev)		(INTEL_INFO(dev)->is_i915g)
2630 2631
#define IS_I915GM(dev)		(INTEL_DEVID(dev) == 0x2592)
#define IS_I945G(dev)		(INTEL_DEVID(dev) == 0x2772)
2632 2633 2634
#define IS_I945GM(dev)		(INTEL_INFO(dev)->is_i945gm)
#define IS_BROADWATER(dev)	(INTEL_INFO(dev)->is_broadwater)
#define IS_CRESTLINE(dev)	(INTEL_INFO(dev)->is_crestline)
2635
#define IS_GM45(dev)		(INTEL_DEVID(dev) == 0x2A42)
2636
#define IS_G4X(dev)		(INTEL_INFO(dev)->is_g4x)
2637 2638
#define IS_PINEVIEW_G(dev)	(INTEL_DEVID(dev) == 0xa001)
#define IS_PINEVIEW_M(dev)	(INTEL_DEVID(dev) == 0xa011)
2639 2640
#define IS_PINEVIEW(dev)	(INTEL_INFO(dev)->is_pineview)
#define IS_G33(dev)		(INTEL_INFO(dev)->is_g33)
2641
#define IS_IRONLAKE_M(dev)	(INTEL_DEVID(dev) == 0x0046)
2642
#define IS_IVYBRIDGE(dev)	(INTEL_INFO(dev)->is_ivybridge)
2643 2644 2645
#define IS_IVB_GT1(dev)		(INTEL_DEVID(dev) == 0x0156 || \
				 INTEL_DEVID(dev) == 0x0152 || \
				 INTEL_DEVID(dev) == 0x015a)
2646
#define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)
2647
#define IS_CHERRYVIEW(dev)	(INTEL_INFO(dev)->is_cherryview)
2648
#define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
2649
#define IS_BROADWELL(dev)	(INTEL_INFO(dev)->is_broadwell)
2650
#define IS_SKYLAKE(dev)	(INTEL_INFO(dev)->is_skylake)
2651
#define IS_BROXTON(dev)		(INTEL_INFO(dev)->is_broxton)
2652
#define IS_KABYLAKE(dev)	(INTEL_INFO(dev)->is_kabylake)
2653
#define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
2654
#define IS_HSW_EARLY_SDV(dev)	(IS_HASWELL(dev) && \
2655
				 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
B
Ben Widawsky 已提交
2656
#define IS_BDW_ULT(dev)		(IS_BROADWELL(dev) && \
2657
				 ((INTEL_DEVID(dev) & 0xf) == 0x6 ||	\
2658
				 (INTEL_DEVID(dev) & 0xf) == 0xb ||	\
2659
				 (INTEL_DEVID(dev) & 0xf) == 0xe))
V
Ville Syrjälä 已提交
2660 2661 2662
/* ULX machines are also considered ULT. */
#define IS_BDW_ULX(dev)		(IS_BROADWELL(dev) && \
				 (INTEL_DEVID(dev) & 0xf) == 0xe)
R
Rodrigo Vivi 已提交
2663 2664
#define IS_BDW_GT3(dev)		(IS_BROADWELL(dev) && \
				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
B
Ben Widawsky 已提交
2665
#define IS_HSW_ULT(dev)		(IS_HASWELL(dev) && \
2666
				 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2667
#define IS_HSW_GT3(dev)		(IS_HASWELL(dev) && \
2668
				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2669
/* ULX machines are also considered ULT. */
2670 2671
#define IS_HSW_ULX(dev)		(INTEL_DEVID(dev) == 0x0A0E || \
				 INTEL_DEVID(dev) == 0x0A1E)
2672 2673 2674 2675 2676 2677 2678 2679
#define IS_SKL_ULT(dev)		(INTEL_DEVID(dev) == 0x1906 || \
				 INTEL_DEVID(dev) == 0x1913 || \
				 INTEL_DEVID(dev) == 0x1916 || \
				 INTEL_DEVID(dev) == 0x1921 || \
				 INTEL_DEVID(dev) == 0x1926)
#define IS_SKL_ULX(dev)		(INTEL_DEVID(dev) == 0x190E || \
				 INTEL_DEVID(dev) == 0x1915 || \
				 INTEL_DEVID(dev) == 0x191E)
2680 2681 2682 2683 2684 2685 2686 2687
#define IS_KBL_ULT(dev)		(INTEL_DEVID(dev) == 0x5906 || \
				 INTEL_DEVID(dev) == 0x5913 || \
				 INTEL_DEVID(dev) == 0x5916 || \
				 INTEL_DEVID(dev) == 0x5921 || \
				 INTEL_DEVID(dev) == 0x5926)
#define IS_KBL_ULX(dev)		(INTEL_DEVID(dev) == 0x590E || \
				 INTEL_DEVID(dev) == 0x5915 || \
				 INTEL_DEVID(dev) == 0x591E)
2688 2689 2690 2691 2692
#define IS_SKL_GT3(dev)		(IS_SKYLAKE(dev) && \
				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
#define IS_SKL_GT4(dev)		(IS_SKYLAKE(dev) && \
				 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)

2693
#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2694

2695 2696 2697 2698 2699 2700
#define SKL_REVID_A0		0x0
#define SKL_REVID_B0		0x1
#define SKL_REVID_C0		0x2
#define SKL_REVID_D0		0x3
#define SKL_REVID_E0		0x4
#define SKL_REVID_F0		0x5
2701 2702
#define SKL_REVID_G0		0x6
#define SKL_REVID_H0		0x7
2703

2704 2705
#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))

2706
#define BXT_REVID_A0		0x0
2707
#define BXT_REVID_A1		0x1
2708 2709
#define BXT_REVID_B0		0x3
#define BXT_REVID_C0		0x9
N
Nick Hoath 已提交
2710

2711 2712
#define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))

M
Mika Kuoppala 已提交
2713 2714
#define KBL_REVID_A0		0x0
#define KBL_REVID_B0		0x1
2715 2716 2717
#define KBL_REVID_C0		0x2
#define KBL_REVID_D0		0x3
#define KBL_REVID_E0		0x4
M
Mika Kuoppala 已提交
2718 2719 2720 2721

#define IS_KBL_REVID(p, since, until) \
	(IS_KABYLAKE(p) && IS_REVID(p, since, until))

2722 2723 2724 2725 2726 2727
/*
 * The genX designation typically refers to the render engine, so render
 * capability related checks should use IS_GEN, while display and other checks
 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
 * chips, etc.).
 */
2728 2729 2730 2731 2732 2733 2734 2735
#define IS_GEN2(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(1)))
#define IS_GEN3(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(2)))
#define IS_GEN4(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(3)))
#define IS_GEN5(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(4)))
#define IS_GEN6(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(5)))
#define IS_GEN7(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(6)))
#define IS_GEN8(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(7)))
#define IS_GEN9(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(8)))
2736

2737 2738 2739 2740 2741 2742 2743 2744 2745
#define ENGINE_MASK(id)	BIT(id)
#define RENDER_RING	ENGINE_MASK(RCS)
#define BSD_RING	ENGINE_MASK(VCS)
#define BLT_RING	ENGINE_MASK(BCS)
#define VEBOX_RING	ENGINE_MASK(VECS)
#define BSD2_RING	ENGINE_MASK(VCS2)
#define ALL_ENGINES	(~0)

#define HAS_ENGINE(dev_priv, id) \
2746
	(!!(INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id)))
2747 2748 2749 2750 2751 2752

#define HAS_BSD(dev_priv)	HAS_ENGINE(dev_priv, VCS)
#define HAS_BSD2(dev_priv)	HAS_ENGINE(dev_priv, VCS2)
#define HAS_BLT(dev_priv)	HAS_ENGINE(dev_priv, BCS)
#define HAS_VEBOX(dev_priv)	HAS_ENGINE(dev_priv, VECS)

2753
#define HAS_LLC(dev)		(INTEL_INFO(dev)->has_llc)
2754
#define HAS_SNOOP(dev)		(INTEL_INFO(dev)->has_snoop)
2755
#define HAS_EDRAM(dev)		(!!(__I915__(dev)->edram_cap & EDRAM_ENABLED))
2756
#define HAS_WT(dev)		((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2757
				 HAS_EDRAM(dev))
2758
#define HWS_NEEDS_PHYSICAL(dev)	(INTEL_INFO(dev)->hws_needs_physical)
2759

2760
#define HAS_HW_CONTEXTS(dev)	(INTEL_INFO(dev)->has_hw_contexts)
2761
#define HAS_LOGICAL_RING_CONTEXTS(dev)	(INTEL_INFO(dev)->has_logical_ring_contexts)
2762
#define USES_PPGTT(dev)		(i915.enable_ppgtt)
2763 2764
#define USES_FULL_PPGTT(dev)	(i915.enable_ppgtt >= 2)
#define USES_FULL_48BIT_PPGTT(dev)	(i915.enable_ppgtt == 3)
2765

2766
#define HAS_OVERLAY(dev)		(INTEL_INFO(dev)->has_overlay)
2767 2768
#define OVERLAY_NEEDS_PHYSICAL(dev)	(INTEL_INFO(dev)->overlay_needs_physical)

2769 2770
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
#define HAS_BROKEN_CS_TLB(dev)		(IS_I830(dev) || IS_845G(dev))
2771 2772

/* WaRsDisableCoarsePowerGating:skl,bxt */
2773 2774 2775 2776
#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
	(IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \
	 IS_SKL_GT3(dev_priv) || \
	 IS_SKL_GT4(dev_priv))
2777

2778 2779 2780 2781 2782 2783 2784
/*
 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
 * even when in MSI mode. This results in spurious interrupt warnings if the
 * legacy irq no. is shared with another device. The kernel then disables that
 * interrupt source and so prevents the other device from working properly.
 */
#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2785
#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->has_gmbus_irq)
2786

2787 2788 2789 2790 2791 2792 2793 2794 2795 2796
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 * rows, which changed the alignment requirements and fence programming.
 */
#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
						      IS_I915GM(dev)))
#define SUPPORTS_TV(dev)		(INTEL_INFO(dev)->supports_tv)
#define I915_HAS_HOTPLUG(dev)		 (INTEL_INFO(dev)->has_hotplug)

#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2797
#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2798

2799
#define HAS_IPS(dev)		(IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2800

2801
#define HAS_DP_MST(dev)	(INTEL_INFO(dev)->has_dp_mst)
2802

2803
#define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)
2804
#define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
2805
#define HAS_PSR(dev)		(INTEL_INFO(dev)->has_psr)
2806
#define HAS_RUNTIME_PM(dev)	(INTEL_INFO(dev)->has_runtime_pm)
2807
#define HAS_RC6(dev)		(INTEL_INFO(dev)->has_rc6)
2808
#define HAS_RC6p(dev)		(INTEL_INFO(dev)->has_rc6p)
P
Paulo Zanoni 已提交
2809

2810
#define HAS_CSR(dev)	(INTEL_INFO(dev)->has_csr)
2811

2812 2813 2814 2815 2816
/*
 * For now, anything with a GuC requires uCode loading, and then supports
 * command submission once loaded. But these are logically independent
 * properties, so we have separate macros to test them.
 */
2817
#define HAS_GUC(dev)		(INTEL_INFO(dev)->has_guc)
2818 2819
#define HAS_GUC_UCODE(dev)	(HAS_GUC(dev))
#define HAS_GUC_SCHED(dev)	(HAS_GUC(dev))
2820

2821
#define HAS_RESOURCE_STREAMER(dev) (INTEL_INFO(dev)->has_resource_streamer)
2822

2823 2824
#define HAS_POOLED_EU(dev)	(INTEL_INFO(dev)->has_pooled_eu)

2825 2826 2827 2828 2829 2830
#define INTEL_PCH_DEVICE_ID_MASK		0xff00
#define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
#define INTEL_PCH_PPT_DEVICE_ID_TYPE		0x1e00
#define INTEL_PCH_LPT_DEVICE_ID_TYPE		0x8c00
#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE		0x9c00
2831 2832
#define INTEL_PCH_SPT_DEVICE_ID_TYPE		0xA100
#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE		0x9D00
2833
#define INTEL_PCH_KBP_DEVICE_ID_TYPE		0xA200
2834
#define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
2835
#define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
2836
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
2837

2838
#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2839
#define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP)
2840
#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2841
#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2842
#define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
V
Ville Syrjälä 已提交
2843
#define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2844 2845
#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
B
Ben Widawsky 已提交
2846
#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2847
#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2848

2849
#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->has_gmch_display)
2850

2851
/* DPF == dynamic parity feature */
2852
#define HAS_L3_DPF(dev) (INTEL_INFO(dev)->has_l3_dpf)
2853
#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2854

2855
#define GT_FREQUENCY_MULTIPLIER 50
A
Akash Goel 已提交
2856
#define GEN9_FREQ_SCALER 3
2857

2858 2859
#include "i915_trace.h"

2860 2861 2862 2863 2864 2865 2866 2867 2868
static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
{
#ifdef CONFIG_INTEL_IOMMU
	if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped)
		return true;
#endif
	return false;
}

2869 2870
extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
extern int i915_resume_switcheroo(struct drm_device *dev);
2871

2872
int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2873
				int enable_ppgtt);
2874

2875 2876
bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);

2877
/* i915_drv.c */
2878 2879 2880 2881 2882 2883 2884
void __printf(3, 4)
__i915_printk(struct drm_i915_private *dev_priv, const char *level,
	      const char *fmt, ...);

#define i915_report_error(dev_priv, fmt, ...)				   \
	__i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)

2885
#ifdef CONFIG_COMPAT
D
Dave Airlie 已提交
2886 2887
extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
			      unsigned long arg);
2888
#endif
2889 2890 2891 2892 2893
extern const struct dev_pm_ops i915_pm_ops;

extern int i915_driver_load(struct pci_dev *pdev,
			    const struct pci_device_id *ent);
extern void i915_driver_unload(struct drm_device *dev);
2894 2895
extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2896
extern void i915_reset(struct drm_i915_private *dev_priv);
2897
extern int intel_guc_reset(struct drm_i915_private *dev_priv);
2898
extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2899 2900 2901 2902
extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2903
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2904

2905
/* intel_hotplug.c */
2906 2907
void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
			   u32 pin_mask, u32 long_mask);
2908 2909 2910
void intel_hpd_init(struct drm_i915_private *dev_priv);
void intel_hpd_init_work(struct drm_i915_private *dev_priv);
void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2911
bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2912 2913
bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2914

L
Linus Torvalds 已提交
2915
/* i915_irq.c */
2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931 2932
static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
{
	unsigned long delay;

	if (unlikely(!i915.enable_hangcheck))
		return;

	/* Don't continually defer the hangcheck so that it is always run at
	 * least once after work has been scheduled on any ring. Otherwise,
	 * we will ignore a hung ring if a second ring is kept busy.
	 */

	delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
	queue_delayed_work(system_long_wq,
			   &dev_priv->gpu_error.hangcheck_work, delay);
}

2933
__printf(3, 4)
2934 2935
void i915_handle_error(struct drm_i915_private *dev_priv,
		       u32 engine_mask,
2936
		       const char *fmt, ...);
L
Linus Torvalds 已提交
2937

2938
extern void intel_irq_init(struct drm_i915_private *dev_priv);
2939 2940
int intel_irq_install(struct drm_i915_private *dev_priv);
void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2941

2942 2943
extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
2944
					bool restore_forcewake);
2945
extern void intel_uncore_init(struct drm_i915_private *dev_priv);
2946
extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
2947
extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
2948 2949 2950
extern void intel_uncore_fini(struct drm_i915_private *dev_priv);
extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
					 bool restore);
2951
const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2952
void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2953
				enum forcewake_domains domains);
2954
void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2955
				enum forcewake_domains domains);
2956 2957 2958 2959 2960 2961 2962
/* Like above but the caller must manage the uncore.lock itself.
 * Must be used with I915_READ_FW and friends.
 */
void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
					enum forcewake_domains domains);
void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
					enum forcewake_domains domains);
2963 2964
u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);

2965
void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2966

2967 2968 2969 2970 2971 2972 2973 2974 2975 2976 2977
int intel_wait_for_register(struct drm_i915_private *dev_priv,
			    i915_reg_t reg,
			    const u32 mask,
			    const u32 value,
			    const unsigned long timeout_ms);
int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
			       i915_reg_t reg,
			       const u32 mask,
			       const u32 value,
			       const unsigned long timeout_ms);

2978 2979 2980 2981 2982
static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
{
	return dev_priv->gvt.initialized;
}

2983
static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2984
{
2985
	return dev_priv->vgpu.active;
2986
}
2987

2988
void
2989
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2990
		     u32 status_mask);
2991 2992

void
2993
i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2994
		      u32 status_mask);
2995

2996 2997
void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2998 2999 3000
void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
				   uint32_t mask,
				   uint32_t bits);
3001 3002 3003 3004 3005 3006 3007 3008 3009 3010 3011 3012 3013
void ilk_update_display_irq(struct drm_i915_private *dev_priv,
			    uint32_t interrupt_mask,
			    uint32_t enabled_irq_mask);
static inline void
ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, bits);
}
static inline void
ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, 0);
}
3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 3027
void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
			 enum pipe pipe,
			 uint32_t interrupt_mask,
			 uint32_t enabled_irq_mask);
static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
				       enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
}
static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
					enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
}
3028 3029 3030
void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
				  uint32_t interrupt_mask,
				  uint32_t enabled_irq_mask);
3031 3032 3033 3034 3035 3036 3037 3038 3039 3040 3041
static inline void
ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, bits);
}
static inline void
ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, 0);
}

3042 3043 3044 3045 3046 3047 3048 3049 3050
/* i915_gem.c */
int i915_gem_create_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3051 3052
int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3053 3054 3055 3056 3057 3058
int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
			     struct drm_file *file_priv);
int i915_gem_execbuffer(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
J
Jesse Barnes 已提交
3059 3060
int i915_gem_execbuffer2(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
3061 3062
int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
B
Ben Widawsky 已提交
3063 3064 3065 3066
int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
3067 3068
int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *file_priv);
3069 3070
int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
3071 3072 3073 3074
int i915_gem_set_tiling(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
int i915_gem_get_tiling(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3075
void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
3076 3077
int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file);
3078 3079
int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
3080 3081
int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3082 3083
void i915_gem_load_init(struct drm_device *dev);
void i915_gem_load_cleanup(struct drm_device *dev);
3084
void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3085
int i915_gem_freeze(struct drm_i915_private *dev_priv);
3086 3087
int i915_gem_freeze_late(struct drm_i915_private *dev_priv);

3088 3089
void *i915_gem_object_alloc(struct drm_device *dev);
void i915_gem_object_free(struct drm_i915_gem_object *obj);
3090 3091
void i915_gem_object_init(struct drm_i915_gem_object *obj,
			 const struct drm_i915_gem_object_ops *ops);
3092
struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev,
3093
						  size_t size);
3094 3095
struct drm_i915_gem_object *i915_gem_object_create_from_data(
		struct drm_device *dev, const void *data, size_t size);
3096
void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
3097
void i915_gem_free_object(struct drm_gem_object *obj);
3098

C
Chris Wilson 已提交
3099
struct i915_vma * __must_check
3100 3101
i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
			 const struct i915_ggtt_view *view,
3102
			 u64 size,
3103 3104
			 u64 alignment,
			 u64 flags);
3105 3106 3107

int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
		  u32 flags);
3108
void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
3109
int __must_check i915_vma_unbind(struct i915_vma *vma);
3110 3111
void i915_vma_close(struct i915_vma *vma);
void i915_vma_destroy(struct i915_vma *vma);
3112 3113

int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
3114
int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
3115
void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
3116
void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3117

3118
int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
3119 3120

static inline int __sg_page_count(struct scatterlist *sg)
3121
{
3122 3123
	return sg->length >> PAGE_SHIFT;
}
3124

3125 3126 3127
struct page *
i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n);

3128 3129 3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143 3144
static inline dma_addr_t
i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, int n)
{
	if (n < obj->get_page.last) {
		obj->get_page.sg = obj->pages->sgl;
		obj->get_page.last = 0;
	}

	while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
		obj->get_page.last += __sg_page_count(obj->get_page.sg++);
		if (unlikely(sg_is_chain(obj->get_page.sg)))
			obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
	}

	return sg_dma_address(obj->get_page.sg) + ((n - obj->get_page.last) << PAGE_SHIFT);
}

3145 3146
static inline struct page *
i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
3147
{
3148 3149
	if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
		return NULL;
3150

3151 3152 3153 3154
	if (n < obj->get_page.last) {
		obj->get_page.sg = obj->pages->sgl;
		obj->get_page.last = 0;
	}
3155

3156 3157 3158 3159 3160
	while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
		obj->get_page.last += __sg_page_count(obj->get_page.sg++);
		if (unlikely(sg_is_chain(obj->get_page.sg)))
			obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
	}
3161

3162
	return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
3163
}
3164

3165 3166 3167 3168 3169
static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
{
	BUG_ON(obj->pages == NULL);
	obj->pages_pin_count++;
}
3170

3171 3172 3173 3174 3175 3176
static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
{
	BUG_ON(obj->pages_pin_count == 0);
	obj->pages_pin_count--;
}

3177 3178 3179 3180 3181
enum i915_map_type {
	I915_MAP_WB = 0,
	I915_MAP_WC,
};

3182 3183 3184
/**
 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
 * @obj - the object to map into kernel address space
3185
 * @type - the type of mapping, used to select pgprot_t
3186 3187 3188
 *
 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
 * pages and then returns a contiguous mapping of the backing storage into
3189 3190
 * the kernel address space. Based on the @type of mapping, the PTE will be
 * set to either WriteBack or WriteCombine (via pgprot_t).
3191
 *
3192 3193
 * The caller must hold the struct_mutex, and is responsible for calling
 * i915_gem_object_unpin_map() when the mapping is no longer required.
3194
 *
3195 3196
 * Returns the pointer through which to access the mapped object, or an
 * ERR_PTR() on error.
3197
 */
3198 3199
void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
					   enum i915_map_type type);
3200 3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211 3212 3213 3214 3215 3216 3217

/**
 * i915_gem_object_unpin_map - releases an earlier mapping
 * @obj - the object to unmap
 *
 * After pinning the object and mapping its pages, once you are finished
 * with your access, call i915_gem_object_unpin_map() to release the pin
 * upon the mapping. Once the pin count reaches zero, that mapping may be
 * removed.
 *
 * The caller must hold the struct_mutex.
 */
static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
{
	lockdep_assert_held(&obj->base.dev->struct_mutex);
	i915_gem_object_unpin_pages(obj);
}

3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231
int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
				    unsigned int *needs_clflush);
int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
				     unsigned int *needs_clflush);
#define CLFLUSH_BEFORE 0x1
#define CLFLUSH_AFTER 0x2
#define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)

static inline void
i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
{
	i915_gem_object_unpin_pages(obj);
}

3232
int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
B
Ben Widawsky 已提交
3233
void i915_vma_move_to_active(struct i915_vma *vma,
3234 3235
			     struct drm_i915_gem_request *req,
			     unsigned int flags);
3236 3237 3238
int i915_gem_dumb_create(struct drm_file *file_priv,
			 struct drm_device *dev,
			 struct drm_mode_create_dumb *args);
3239 3240
int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
		      uint32_t handle, uint64_t *offset);
3241
int i915_gem_mmap_gtt_version(void);
3242 3243 3244 3245 3246

void i915_gem_track_fb(struct drm_i915_gem_object *old,
		       struct drm_i915_gem_object *new,
		       unsigned frontbuffer_bits);

3247
int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
3248

3249
struct drm_i915_gem_request *
3250
i915_gem_find_active_request(struct intel_engine_cs *engine);
3251

3252
void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3253

3254 3255
static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
{
3256
	return unlikely(test_bit(I915_RESET_IN_PROGRESS, &error->flags));
3257 3258
}

3259
static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3260
{
3261
	return unlikely(test_bit(I915_WEDGED, &error->flags));
3262 3263
}

3264
static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error)
3265
{
3266
	return i915_reset_in_progress(error) | i915_terminally_wedged(error);
M
Mika Kuoppala 已提交
3267 3268 3269 3270
}

static inline u32 i915_reset_count(struct i915_gpu_error *error)
{
3271
	return READ_ONCE(error->reset_count);
3272
}
3273

3274 3275
void i915_gem_reset(struct drm_i915_private *dev_priv);
void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3276
bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3277
int __must_check i915_gem_init(struct drm_device *dev);
3278 3279
int __must_check i915_gem_init_hw(struct drm_device *dev);
void i915_gem_init_swizzling(struct drm_device *dev);
3280
void i915_gem_cleanup_engines(struct drm_device *dev);
3281
int __must_check i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3282
					unsigned int flags);
3283
int __must_check i915_gem_suspend(struct drm_device *dev);
3284
void i915_gem_resume(struct drm_device *dev);
3285
int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3286
int __must_check
3287 3288 3289
i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
			       bool readonly);
int __must_check
3290 3291 3292
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
				  bool write);
int __must_check
3293
i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
C
Chris Wilson 已提交
3294
struct i915_vma * __must_check
3295 3296
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
				     u32 alignment,
3297
				     const struct i915_ggtt_view *view);
C
Chris Wilson 已提交
3298
void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3299
int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3300
				int align);
3301
int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3302
void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3303

3304 3305 3306
u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, u64 size,
			   int tiling_mode);
u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size,
3307
				int tiling_mode, bool fenced);
3308

3309 3310 3311
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
				    enum i915_cache_level cache_level);

3312 3313 3314 3315 3316 3317
struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
				struct dma_buf *dma_buf);

struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
				struct drm_gem_object *gem_obj, int flags);

3318
struct i915_vma *
3319
i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
C
Chris Wilson 已提交
3320 3321
		     struct i915_address_space *vm,
		     const struct i915_ggtt_view *view);
3322

3323 3324
struct i915_vma *
i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
C
Chris Wilson 已提交
3325 3326
				  struct i915_address_space *vm,
				  const struct i915_ggtt_view *view);
3327

3328 3329 3330 3331 3332 3333
static inline struct i915_hw_ppgtt *
i915_vm_to_ppgtt(struct i915_address_space *vm)
{
	return container_of(vm, struct i915_hw_ppgtt, base);
}

C
Chris Wilson 已提交
3334 3335 3336
static inline struct i915_vma *
i915_gem_object_to_ggtt(struct drm_i915_gem_object *obj,
			const struct i915_ggtt_view *view)
3337
{
C
Chris Wilson 已提交
3338
	return i915_gem_obj_to_vma(obj, &to_i915(obj->base.dev)->ggtt.base, view);
3339 3340
}

C
Chris Wilson 已提交
3341 3342 3343
static inline unsigned long
i915_gem_object_ggtt_offset(struct drm_i915_gem_object *o,
			    const struct i915_ggtt_view *view)
3344
{
3345
	return i915_ggtt_offset(i915_gem_object_to_ggtt(o, view));
3346
}
3347

3348
/* i915_gem_fence.c */
3349 3350 3351 3352 3353 3354 3355 3356 3357 3358 3359 3360 3361 3362 3363 3364 3365 3366 3367 3368 3369 3370 3371 3372 3373 3374 3375
int __must_check i915_vma_get_fence(struct i915_vma *vma);
int __must_check i915_vma_put_fence(struct i915_vma *vma);

/**
 * i915_vma_pin_fence - pin fencing state
 * @vma: vma to pin fencing for
 *
 * This pins the fencing state (whether tiled or untiled) to make sure the
 * vma (and its object) is ready to be used as a scanout target. Fencing
 * status must be synchronize first by calling i915_vma_get_fence():
 *
 * The resulting fence pin reference must be released again with
 * i915_vma_unpin_fence().
 *
 * Returns:
 *
 * True if the vma has a fence, false otherwise.
 */
static inline bool
i915_vma_pin_fence(struct i915_vma *vma)
{
	if (vma->fence) {
		vma->fence->pin_count++;
		return true;
	} else
		return false;
}
3376

3377 3378 3379 3380 3381 3382 3383 3384 3385 3386 3387 3388 3389 3390 3391 3392
/**
 * i915_vma_unpin_fence - unpin fencing state
 * @vma: vma to unpin fencing for
 *
 * This releases the fence pin reference acquired through
 * i915_vma_pin_fence. It will handle both objects with and without an
 * attached fence correctly, callers do not need to distinguish this.
 */
static inline void
i915_vma_unpin_fence(struct i915_vma *vma)
{
	if (vma->fence) {
		GEM_BUG_ON(vma->fence->pin_count <= 0);
		vma->fence->pin_count--;
	}
}
3393 3394 3395

void i915_gem_restore_fences(struct drm_device *dev);

3396 3397 3398 3399
void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);

3400
/* i915_gem_context.c */
3401
int __must_check i915_gem_context_init(struct drm_device *dev);
3402
void i915_gem_context_lost(struct drm_i915_private *dev_priv);
3403
void i915_gem_context_fini(struct drm_device *dev);
3404
int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3405
void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3406
int i915_switch_context(struct drm_i915_gem_request *req);
3407
int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv);
3408
void i915_gem_context_free(struct kref *ctx_ref);
3409 3410
struct drm_i915_gem_object *
i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3411 3412
struct i915_gem_context *
i915_gem_context_create_gvt(struct drm_device *dev);
3413 3414 3415 3416 3417 3418

static inline struct i915_gem_context *
i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
{
	struct i915_gem_context *ctx;

3419
	lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
3420 3421 3422 3423 3424 3425 3426 3427

	ctx = idr_find(&file_priv->context_idr, id);
	if (!ctx)
		return ERR_PTR(-ENOENT);

	return ctx;
}

3428 3429
static inline struct i915_gem_context *
i915_gem_context_get(struct i915_gem_context *ctx)
3430
{
3431
	kref_get(&ctx->ref);
3432
	return ctx;
3433 3434
}

3435
static inline void i915_gem_context_put(struct i915_gem_context *ctx)
3436
{
3437
	lockdep_assert_held(&ctx->i915->drm.struct_mutex);
3438
	kref_put(&ctx->ref, i915_gem_context_free);
3439 3440
}

3441
static inline bool i915_gem_context_is_default(const struct i915_gem_context *c)
3442
{
3443
	return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3444 3445
}

3446 3447 3448 3449
int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
				  struct drm_file *file);
int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
				   struct drm_file *file);
3450 3451 3452 3453
int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
				    struct drm_file *file_priv);
int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
				    struct drm_file *file_priv);
3454 3455
int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data,
				       struct drm_file *file);
3456

3457
/* i915_gem_evict.c */
3458
int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3459
					  u64 min_size, u64 alignment,
3460
					  unsigned cache_level,
3461
					  u64 start, u64 end,
3462
					  unsigned flags);
3463
int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
3464
int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3465

3466
/* belongs in i915_gem_gtt.h */
3467
static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3468
{
3469
	wmb();
3470
	if (INTEL_GEN(dev_priv) < 6)
3471 3472
		intel_gtt_chipset_flush();
}
3473

3474
/* i915_gem_stolen.c */
3475 3476 3477
int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
				struct drm_mm_node *node, u64 size,
				unsigned alignment);
3478 3479 3480 3481
int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
					 struct drm_mm_node *node, u64 size,
					 unsigned alignment, u64 start,
					 u64 end);
3482 3483
void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
				 struct drm_mm_node *node);
3484 3485
int i915_gem_init_stolen(struct drm_device *dev);
void i915_gem_cleanup_stolen(struct drm_device *dev);
3486 3487
struct drm_i915_gem_object *
i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3488 3489 3490 3491 3492
struct drm_i915_gem_object *
i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
					       u32 stolen_offset,
					       u32 gtt_offset,
					       u32 size);
3493

3494 3495
/* i915_gem_shrinker.c */
unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3496
			      unsigned long target,
3497 3498 3499 3500
			      unsigned flags);
#define I915_SHRINK_PURGEABLE 0x1
#define I915_SHRINK_UNBOUND 0x2
#define I915_SHRINK_BOUND 0x4
3501
#define I915_SHRINK_ACTIVE 0x8
3502
#define I915_SHRINK_VMAPS 0x10
3503 3504
unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3505
void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3506 3507


3508
/* i915_gem_tiling.c */
3509
static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3510
{
3511
	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3512 3513

	return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3514
		i915_gem_object_is_tiled(obj);
3515 3516
}

3517
/* i915_debugfs.c */
3518
#ifdef CONFIG_DEBUG_FS
3519 3520
int i915_debugfs_register(struct drm_i915_private *dev_priv);
void i915_debugfs_unregister(struct drm_i915_private *dev_priv);
J
Jani Nikula 已提交
3521
int i915_debugfs_connector_add(struct drm_connector *connector);
3522
void intel_display_crc_init(struct drm_i915_private *dev_priv);
3523
#else
3524 3525
static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
static inline void i915_debugfs_unregister(struct drm_i915_private *dev_priv) {}
3526 3527
static inline int i915_debugfs_connector_add(struct drm_connector *connector)
{ return 0; }
3528
static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3529
#endif
3530 3531

/* i915_gpu_error.c */
3532 3533
__printf(2, 3)
void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3534 3535
int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
			    const struct i915_error_state_file_priv *error);
3536
int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3537
			      struct drm_i915_private *i915,
3538 3539 3540 3541 3542 3543
			      size_t count, loff_t pos);
static inline void i915_error_state_buf_release(
	struct drm_i915_error_state_buf *eb)
{
	kfree(eb->buf);
}
3544 3545
void i915_capture_error_state(struct drm_i915_private *dev_priv,
			      u32 engine_mask,
3546
			      const char *error_msg);
3547 3548 3549 3550 3551
void i915_error_state_get(struct drm_device *dev,
			  struct i915_error_state_file_priv *error_priv);
void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
void i915_destroy_error_state(struct drm_device *dev);

3552 3553 3554
void i915_get_engine_instdone(struct drm_i915_private *dev_priv,
			      enum intel_engine_id engine_id,
			      struct intel_instdone *instdone);
3555
const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3556

3557
/* i915_cmd_parser.c */
3558
int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3559
void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3560 3561 3562 3563 3564 3565 3566 3567
void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
bool intel_engine_needs_cmd_parser(struct intel_engine_cs *engine);
int intel_engine_cmd_parser(struct intel_engine_cs *engine,
			    struct drm_i915_gem_object *batch_obj,
			    struct drm_i915_gem_object *shadow_batch_obj,
			    u32 batch_start_offset,
			    u32 batch_len,
			    bool is_master);
3568

3569 3570 3571
/* i915_suspend.c */
extern int i915_save_state(struct drm_device *dev);
extern int i915_restore_state(struct drm_device *dev);
3572

B
Ben Widawsky 已提交
3573
/* i915_sysfs.c */
D
David Weinehall 已提交
3574 3575
void i915_setup_sysfs(struct drm_i915_private *dev_priv);
void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
B
Ben Widawsky 已提交
3576

3577 3578 3579
/* intel_i2c.c */
extern int intel_setup_gmbus(struct drm_device *dev);
extern void intel_teardown_gmbus(struct drm_device *dev);
3580 3581
extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
				     unsigned int pin);
3582

3583 3584
extern struct i2c_adapter *
intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
C
Chris Wilson 已提交
3585 3586
extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3587
static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3588 3589 3590
{
	return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
}
3591 3592
extern void intel_i2c_reset(struct drm_device *dev);

3593
/* intel_bios.c */
3594
int intel_bios_init(struct drm_i915_private *dev_priv);
J
Jani Nikula 已提交
3595
bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3596
bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3597
bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3598
bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3599
bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3600
bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3601
bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3602 3603
bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
				     enum port port);
3604

3605
/* intel_opregion.c */
3606
#ifdef CONFIG_ACPI
3607
extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3608 3609
extern void intel_opregion_register(struct drm_i915_private *dev_priv);
extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3610
extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3611 3612
extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
					 bool enable);
3613
extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3614
					 pci_power_t state);
3615
extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3616
#else
3617
static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3618 3619
static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
3620 3621 3622
static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
{
}
3623 3624 3625 3626 3627
static inline int
intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
{
	return 0;
}
3628
static inline int
3629
intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3630 3631 3632
{
	return 0;
}
3633
static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3634 3635 3636
{
	return -ENODEV;
}
3637
#endif
3638

J
Jesse Barnes 已提交
3639 3640 3641 3642 3643 3644 3645 3646 3647
/* intel_acpi.c */
#ifdef CONFIG_ACPI
extern void intel_register_dsm_handler(void);
extern void intel_unregister_dsm_handler(void);
#else
static inline void intel_register_dsm_handler(void) { return; }
static inline void intel_unregister_dsm_handler(void) { return; }
#endif /* CONFIG_ACPI */

3648 3649 3650 3651 3652 3653 3654 3655 3656 3657
/* intel_device_info.c */
static inline struct intel_device_info *
mkwrite_device_info(struct drm_i915_private *dev_priv)
{
	return (struct intel_device_info *)&dev_priv->info;
}

void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
void intel_device_info_dump(struct drm_i915_private *dev_priv);

J
Jesse Barnes 已提交
3658
/* modesetting */
3659
extern void intel_modeset_init_hw(struct drm_device *dev);
J
Jesse Barnes 已提交
3660
extern void intel_modeset_init(struct drm_device *dev);
3661
extern void intel_modeset_gem_init(struct drm_device *dev);
J
Jesse Barnes 已提交
3662
extern void intel_modeset_cleanup(struct drm_device *dev);
3663
extern int intel_connector_register(struct drm_connector *);
3664
extern void intel_connector_unregister(struct drm_connector *);
3665
extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3666
extern void intel_display_resume(struct drm_device *dev);
3667
extern void i915_redisable_vga(struct drm_device *dev);
3668
extern void i915_redisable_vga_power_on(struct drm_device *dev);
3669
extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
P
Paulo Zanoni 已提交
3670
extern void intel_init_pch_refclk(struct drm_device *dev);
3671
extern void intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3672 3673
extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
				  bool enable);
3674

B
Ben Widawsky 已提交
3675 3676
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file);
3677

3678
/* overlay */
3679 3680
extern struct intel_overlay_error_state *
intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3681 3682
extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
					    struct intel_overlay_error_state *error);
3683

3684 3685
extern struct intel_display_error_state *
intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3686
extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3687 3688
					    struct drm_device *dev,
					    struct intel_display_error_state *error);
3689

3690 3691
int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3692 3693

/* intel_sideband.c */
3694 3695
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3696
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3697 3698
u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3699 3700 3701 3702
u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3703 3704
u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3705 3706
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3707 3708 3709 3710
u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
		   enum intel_sbi_destination destination);
void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
		     enum intel_sbi_destination destination);
3711 3712
u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3713

3714 3715 3716 3717
/* intel_dpio_phy.c */
void chv_set_phy_signal_level(struct intel_encoder *encoder,
			      u32 deemph_reg_value, u32 margin_reg_value,
			      bool uniq_trans_scale);
3718 3719
void chv_data_lane_soft_reset(struct intel_encoder *encoder,
			      bool reset);
3720
void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3721 3722
void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3723
void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3724

3725 3726 3727
void vlv_set_phy_signal_level(struct intel_encoder *encoder,
			      u32 demph_reg_value, u32 preemph_reg_value,
			      u32 uniqtranscale_reg_value, u32 tx3_demph);
3728
void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3729
void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3730
void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3731

3732 3733
int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3734

3735 3736 3737 3738 3739 3740 3741 3742 3743 3744 3745 3746 3747
#define I915_READ8(reg)		dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
#define I915_WRITE8(reg, val)	dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)

#define I915_READ16(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
#define I915_WRITE16(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
#define I915_READ16_NOTRACE(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
#define I915_WRITE16_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)

#define I915_READ(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
#define I915_WRITE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
#define I915_READ_NOTRACE(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
#define I915_WRITE_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)

3748 3749 3750 3751
/* Be very careful with read/write 64-bit values. On 32-bit machines, they
 * will be implemented using 2 32-bit writes in an arbitrary order with
 * an arbitrary delay between them. This can cause the hardware to
 * act upon the intermediate value, possibly leading to corruption and
3752 3753 3754 3755 3756 3757 3758 3759 3760
 * machine death. For this reason we do not support I915_WRITE64, or
 * dev_priv->uncore.funcs.mmio_writeq.
 *
 * When reading a 64-bit value as two 32-bit values, the delay may cause
 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
 * occasionally a 64-bit register does not actualy support a full readq
 * and must be read using two 32-bit reads.
 *
 * You have been warned.
3761
 */
3762
#define I915_READ64(reg)	dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3763

3764
#define I915_READ64_2x32(lower_reg, upper_reg) ({			\
3765 3766
	u32 upper, lower, old_upper, loop = 0;				\
	upper = I915_READ(upper_reg);					\
3767
	do {								\
3768
		old_upper = upper;					\
3769
		lower = I915_READ(lower_reg);				\
3770 3771
		upper = I915_READ(upper_reg);				\
	} while (upper != old_upper && loop++ < 2);			\
3772
	(u64)upper << 32 | lower; })
3773

3774 3775 3776
#define POSTING_READ(reg)	(void)I915_READ_NOTRACE(reg)
#define POSTING_READ16(reg)	(void)I915_READ16_NOTRACE(reg)

3777 3778
#define __raw_read(x, s) \
static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3779
					     i915_reg_t reg) \
3780
{ \
3781
	return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3782 3783 3784 3785
}

#define __raw_write(x, s) \
static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3786
				       i915_reg_t reg, uint##x##_t val) \
3787
{ \
3788
	write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3789 3790 3791 3792 3793 3794 3795 3796 3797 3798 3799 3800 3801 3802
}
__raw_read(8, b)
__raw_read(16, w)
__raw_read(32, l)
__raw_read(64, q)

__raw_write(8, b)
__raw_write(16, w)
__raw_write(32, l)
__raw_write(64, q)

#undef __raw_read
#undef __raw_write

3803
/* These are untraced mmio-accessors that are only valid to be used inside
3804
 * critical sections inside IRQ handlers where forcewake is explicitly
3805 3806 3807 3808 3809
 * controlled.
 * Think twice, and think again, before using these.
 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
 * intel_uncore_forcewake_irqunlock().
 */
3810 3811
#define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3812
#define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3813 3814
#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)

3815 3816 3817 3818
/* "Broadcast RGB" property */
#define INTEL_BROADCAST_RGB_AUTO 0
#define INTEL_BROADCAST_RGB_FULL 1
#define INTEL_BROADCAST_RGB_LIMITED 2
3819

3820
static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
3821
{
3822
	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
3823
		return VLV_VGACNTRL;
3824 3825
	else if (INTEL_INFO(dev)->gen >= 5)
		return CPU_VGACNTRL;
3826 3827 3828 3829
	else
		return VGACNTRL;
}

3830 3831 3832 3833 3834 3835 3836
static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
{
	unsigned long j = msecs_to_jiffies(m);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

3837 3838 3839 3840 3841
static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
{
        return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
}

3842 3843 3844 3845 3846 3847 3848 3849
static inline unsigned long
timespec_to_jiffies_timeout(const struct timespec *value)
{
	unsigned long j = timespec_to_jiffies(value);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

3850 3851 3852 3853 3854 3855 3856 3857 3858
/*
 * If you need to wait X milliseconds between events A and B, but event B
 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
 * when event A happened, then just before event B you call this function and
 * pass the timestamp as the first argument, and X as the second argument.
 */
static inline void
wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
{
3859
	unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3860 3861 3862 3863 3864 3865 3866 3867 3868 3869

	/*
	 * Don't re-read the value of "jiffies" every time since it may change
	 * behind our back and break the math.
	 */
	tmp_jiffies = jiffies;
	target_jiffies = timestamp_jiffies +
			 msecs_to_jiffies_timeout(to_wait_ms);

	if (time_after(target_jiffies, tmp_jiffies)) {
3870 3871 3872 3873
		remaining_jiffies = target_jiffies - tmp_jiffies;
		while (remaining_jiffies)
			remaining_jiffies =
			    schedule_timeout_uninterruptible(remaining_jiffies);
3874 3875
	}
}
3876 3877 3878

static inline bool
__i915_request_irq_complete(struct drm_i915_gem_request *req)
3879
{
3880 3881
	struct intel_engine_cs *engine = req->engine;

3882 3883 3884 3885 3886 3887
	/* Before we do the heavier coherent read of the seqno,
	 * check the value (hopefully) in the CPU cacheline.
	 */
	if (i915_gem_request_completed(req))
		return true;

3888 3889 3890 3891 3892 3893 3894 3895 3896 3897 3898
	/* Ensure our read of the seqno is coherent so that we
	 * do not "miss an interrupt" (i.e. if this is the last
	 * request and the seqno write from the GPU is not visible
	 * by the time the interrupt fires, we will see that the
	 * request is incomplete and go back to sleep awaiting
	 * another interrupt that will never come.)
	 *
	 * Strictly, we only need to do this once after an interrupt,
	 * but it is easier and safer to do it every time the waiter
	 * is woken.
	 */
3899
	if (engine->irq_seqno_barrier &&
3900
	    rcu_access_pointer(engine->breadcrumbs.irq_seqno_bh) == current &&
3901
	    cmpxchg_relaxed(&engine->breadcrumbs.irq_posted, 1, 0)) {
3902 3903
		struct task_struct *tsk;

3904 3905 3906 3907 3908 3909 3910 3911 3912 3913 3914 3915
		/* The ordering of irq_posted versus applying the barrier
		 * is crucial. The clearing of the current irq_posted must
		 * be visible before we perform the barrier operation,
		 * such that if a subsequent interrupt arrives, irq_posted
		 * is reasserted and our task rewoken (which causes us to
		 * do another __i915_request_irq_complete() immediately
		 * and reapply the barrier). Conversely, if the clear
		 * occurs after the barrier, then an interrupt that arrived
		 * whilst we waited on the barrier would not trigger a
		 * barrier on the next pass, and the read may not see the
		 * seqno update.
		 */
3916
		engine->irq_seqno_barrier(engine);
3917 3918 3919 3920 3921 3922 3923 3924

		/* If we consume the irq, but we are no longer the bottom-half,
		 * the real bottom-half may not have serialised their own
		 * seqno check with the irq-barrier (i.e. may have inspected
		 * the seqno before we believe it coherent since they see
		 * irq_posted == false but we are still running).
		 */
		rcu_read_lock();
3925
		tsk = rcu_dereference(engine->breadcrumbs.irq_seqno_bh);
3926 3927 3928 3929 3930 3931 3932 3933 3934 3935
		if (tsk && tsk != current)
			/* Note that if the bottom-half is changed as we
			 * are sending the wake-up, the new bottom-half will
			 * be woken by whomever made the change. We only have
			 * to worry about when we steal the irq-posted for
			 * ourself.
			 */
			wake_up_process(tsk);
		rcu_read_unlock();

3936 3937 3938
		if (i915_gem_request_completed(req))
			return true;
	}
3939 3940 3941 3942

	return false;
}

3943 3944 3945
void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);

3946 3947 3948 3949 3950
/* i915_mm.c */
int remap_io_mapping(struct vm_area_struct *vma,
		     unsigned long addr, unsigned long pfn, unsigned long size,
		     struct io_mapping *iomap);

3951 3952 3953 3954 3955
#define ptr_mask_bits(ptr) ({						\
	unsigned long __v = (unsigned long)(ptr);			\
	(typeof(ptr))(__v & PAGE_MASK);					\
})

3956 3957 3958 3959 3960 3961 3962 3963 3964
#define ptr_unpack_bits(ptr, bits) ({					\
	unsigned long __v = (unsigned long)(ptr);			\
	(bits) = __v & ~PAGE_MASK;					\
	(typeof(ptr))(__v & PAGE_MASK);					\
})

#define ptr_pack_bits(ptr, bits)					\
	((typeof(ptr))((unsigned long)(ptr) | (bits)))

3965 3966 3967 3968 3969 3970
#define fetch_and_zero(ptr) ({						\
	typeof(*ptr) __T = *(ptr);					\
	*(ptr) = (typeof(*ptr))0;					\
	__T;								\
})

L
Linus Torvalds 已提交
3971
#endif