i915_drv.h 116.2 KB
Newer Older
L
Linus Torvalds 已提交
1 2
/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
 */
D
Dave Airlie 已提交
3
/*
4
 *
L
Linus Torvalds 已提交
5 6
 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
D
Dave Airlie 已提交
28
 */
L
Linus Torvalds 已提交
29 30 31 32

#ifndef _I915_DRV_H_
#define _I915_DRV_H_

33
#include <uapi/drm/i915_drm.h>
34
#include <uapi/drm/drm_fourcc.h>
35

36
#include <linux/io-mapping.h>
37
#include <linux/i2c.h>
38
#include <linux/i2c-algo-bit.h>
39
#include <linux/backlight.h>
40
#include <linux/hash.h>
41
#include <linux/intel-iommu.h>
42
#include <linux/kref.h>
43
#include <linux/perf_event.h>
44
#include <linux/pm_qos.h>
45
#include <linux/reservation.h>
46 47 48 49 50 51
#include <linux/shmem_fs.h>

#include <drm/drmP.h>
#include <drm/intel-gtt.h>
#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
#include <drm/drm_gem.h>
D
Daniel Vetter 已提交
52
#include <drm/drm_auth.h>
53
#include <drm/drm_cache.h>
54 55 56

#include "i915_params.h"
#include "i915_reg.h"
57
#include "i915_utils.h"
58 59

#include "intel_bios.h"
60
#include "intel_device_info.h"
61
#include "intel_display.h"
62
#include "intel_dpll_mgr.h"
63
#include "intel_lrc.h"
64
#include "intel_opregion.h"
65
#include "intel_ringbuffer.h"
66
#include "intel_uncore.h"
67
#include "intel_wopcm.h"
68
#include "intel_uc.h"
69

70
#include "i915_gem.h"
71
#include "i915_gem_context.h"
J
Joonas Lahtinen 已提交
72 73
#include "i915_gem_fence_reg.h"
#include "i915_gem_object.h"
74
#include "i915_gem_gtt.h"
75
#include "i915_gem_timeline.h"
76
#include "i915_gpu_error.h"
77
#include "i915_request.h"
J
Joonas Lahtinen 已提交
78 79
#include "i915_vma.h"

80 81
#include "intel_gvt.h"

L
Linus Torvalds 已提交
82 83 84 85 86
/* General customization:
 */

#define DRIVER_NAME		"i915"
#define DRIVER_DESC		"Intel Graphics"
87 88
#define DRIVER_DATE		"20180308"
#define DRIVER_TIMESTAMP	1520513379
L
Linus Torvalds 已提交
89

R
Rob Clark 已提交
90 91 92 93 94 95 96 97 98
/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
 * which may not necessarily be a user visible problem.  This will either
 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
 * enable distros and users to tailor their preferred amount of i915 abrt
 * spam.
 */
#define I915_STATE_WARN(condition, format...) ({			\
	int __ret_warn_on = !!(condition);				\
99
	if (unlikely(__ret_warn_on))					\
100
		if (!WARN(i915_modparams.verbose_state_checks, format))	\
R
Rob Clark 已提交
101 102 103 104
			DRM_ERROR(format);				\
	unlikely(__ret_warn_on);					\
})

105 106
#define I915_STATE_WARN_ON(x)						\
	I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
107

108
#if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
109 110 111
bool __i915_inject_load_failure(const char *func, int line);
#define i915_inject_load_failure() \
	__i915_inject_load_failure(__func__, __LINE__)
112 113 114
#else
#define i915_inject_load_failure() false
#endif
115

116 117 118 119 120 121 122 123 124 125
typedef struct {
	uint32_t val;
} uint_fixed_16_16_t;

#define FP_16_16_MAX ({ \
	uint_fixed_16_16_t fp; \
	fp.val = UINT_MAX; \
	fp; \
})

126 127 128 129 130 131 132
static inline bool is_fixed16_zero(uint_fixed_16_16_t val)
{
	if (val.val == 0)
		return true;
	return false;
}

133
static inline uint_fixed_16_16_t u32_to_fixed16(uint32_t val)
134 135 136
{
	uint_fixed_16_16_t fp;

137
	WARN_ON(val > U16_MAX);
138 139 140 141 142

	fp.val = val << 16;
	return fp;
}

143
static inline uint32_t fixed16_to_u32_round_up(uint_fixed_16_16_t fp)
144 145 146 147
{
	return DIV_ROUND_UP(fp.val, 1 << 16);
}

148
static inline uint32_t fixed16_to_u32(uint_fixed_16_16_t fp)
149 150 151 152
{
	return fp.val >> 16;
}

153
static inline uint_fixed_16_16_t min_fixed16(uint_fixed_16_16_t min1,
154 155 156 157 158 159 160 161
						 uint_fixed_16_16_t min2)
{
	uint_fixed_16_16_t min;

	min.val = min(min1.val, min2.val);
	return min;
}

162
static inline uint_fixed_16_16_t max_fixed16(uint_fixed_16_16_t max1,
163 164 165 166 167 168 169 170
						 uint_fixed_16_16_t max2)
{
	uint_fixed_16_16_t max;

	max.val = max(max1.val, max2.val);
	return max;
}

171 172 173
static inline uint_fixed_16_16_t clamp_u64_to_fixed16(uint64_t val)
{
	uint_fixed_16_16_t fp;
174 175
	WARN_ON(val > U32_MAX);
	fp.val = (uint32_t) val;
176 177 178
	return fp;
}

179 180 181 182 183 184 185 186 187 188 189 190 191
static inline uint32_t div_round_up_fixed16(uint_fixed_16_16_t val,
					    uint_fixed_16_16_t d)
{
	return DIV_ROUND_UP(val.val, d.val);
}

static inline uint32_t mul_round_up_u32_fixed16(uint32_t val,
						uint_fixed_16_16_t mul)
{
	uint64_t intermediate_val;

	intermediate_val = (uint64_t) val * mul.val;
	intermediate_val = DIV_ROUND_UP_ULL(intermediate_val, 1 << 16);
192 193
	WARN_ON(intermediate_val > U32_MAX);
	return (uint32_t) intermediate_val;
194 195 196 197 198 199 200 201 202
}

static inline uint_fixed_16_16_t mul_fixed16(uint_fixed_16_16_t val,
					     uint_fixed_16_16_t mul)
{
	uint64_t intermediate_val;

	intermediate_val = (uint64_t) val.val * mul.val;
	intermediate_val = intermediate_val >> 16;
203
	return clamp_u64_to_fixed16(intermediate_val);
204 205
}

206
static inline uint_fixed_16_16_t div_fixed16(uint32_t val, uint32_t d)
207 208 209 210 211
{
	uint64_t interm_val;

	interm_val = (uint64_t)val << 16;
	interm_val = DIV_ROUND_UP_ULL(interm_val, d);
212
	return clamp_u64_to_fixed16(interm_val);
213 214
}

215 216 217 218 219 220 221
static inline uint32_t div_round_up_u32_fixed16(uint32_t val,
						uint_fixed_16_16_t d)
{
	uint64_t interm_val;

	interm_val = (uint64_t)val << 16;
	interm_val = DIV_ROUND_UP_ULL(interm_val, d.val);
222 223
	WARN_ON(interm_val > U32_MAX);
	return (uint32_t) interm_val;
224 225
}

226
static inline uint_fixed_16_16_t mul_u32_fixed16(uint32_t val,
227 228 229 230 231
						     uint_fixed_16_16_t mul)
{
	uint64_t intermediate_val;

	intermediate_val = (uint64_t) val * mul.val;
232
	return clamp_u64_to_fixed16(intermediate_val);
233 234
}

235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253
static inline uint_fixed_16_16_t add_fixed16(uint_fixed_16_16_t add1,
					     uint_fixed_16_16_t add2)
{
	uint64_t interm_sum;

	interm_sum = (uint64_t) add1.val + add2.val;
	return clamp_u64_to_fixed16(interm_sum);
}

static inline uint_fixed_16_16_t add_fixed16_u32(uint_fixed_16_16_t add1,
						 uint32_t add2)
{
	uint64_t interm_sum;
	uint_fixed_16_16_t interm_add2 = u32_to_fixed16(add2);

	interm_sum = (uint64_t) add1.val + interm_add2.val;
	return clamp_u64_to_fixed16(interm_sum);
}

254 255 256 257 258 259
enum hpd_pin {
	HPD_NONE = 0,
	HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
	HPD_CRT,
	HPD_SDVO_B,
	HPD_SDVO_C,
260
	HPD_PORT_A,
261 262 263
	HPD_PORT_B,
	HPD_PORT_C,
	HPD_PORT_D,
X
Xiong Zhang 已提交
264
	HPD_PORT_E,
265
	HPD_PORT_F,
266 267 268
	HPD_NUM_PINS
};

269 270 271
#define for_each_hpd_pin(__pin) \
	for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)

L
Lyude 已提交
272 273
#define HPD_STORM_DEFAULT_THRESHOLD 5

274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293
struct i915_hotplug {
	struct work_struct hotplug_work;

	struct {
		unsigned long last_jiffies;
		int count;
		enum {
			HPD_ENABLED = 0,
			HPD_DISABLED = 1,
			HPD_MARK_DISABLED = 2
		} state;
	} stats[HPD_NUM_PINS];
	u32 event_bits;
	struct delayed_work reenable_work;

	struct intel_digital_port *irq_port[I915_MAX_PORTS];
	u32 long_port_mask;
	u32 short_port_mask;
	struct work_struct dig_port_work;

294 295 296
	struct work_struct poll_init_work;
	bool poll_enabled;

L
Lyude 已提交
297 298
	unsigned int hpd_storm_threshold;

299 300 301 302 303 304 305 306 307 308
	/*
	 * if we get a HPD irq from DP and a HPD irq from non-DP
	 * the non-DP HPD could block the workqueue on a mode config
	 * mutex getting, that userspace may have taken. However
	 * userspace is waiting on the DP workqueue to run which is
	 * blocked behind the non-DP one.
	 */
	struct workqueue_struct *dp_wq;
};

309 310 311 312 313 314
#define I915_GEM_GPU_DOMAINS \
	(I915_GEM_DOMAIN_RENDER | \
	 I915_GEM_DOMAIN_SAMPLER | \
	 I915_GEM_DOMAIN_COMMAND | \
	 I915_GEM_DOMAIN_INSTRUCTION | \
	 I915_GEM_DOMAIN_VERTEX)
315

316
struct drm_i915_private;
317
struct i915_mm_struct;
318
struct i915_mmu_object;
319

320 321 322 323 324 325 326
struct drm_i915_file_private {
	struct drm_i915_private *dev_priv;
	struct drm_file *file;

	struct {
		spinlock_t lock;
		struct list_head request_list;
327 328 329 330 331 332
/* 20ms is a fairly arbitrary limit (greater than the average frame time)
 * chosen to prevent the CPU getting more than a frame ahead of the GPU
 * (when using lax throttling for the frontbuffer). We also use it to
 * offer free GPU waitboosts for severely congested workloads.
 */
#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
333 334 335
	} mm;
	struct idr context_idr;

336
	struct intel_rps_client {
337
		atomic_t boosts;
338
	} rps_client;
339

340
	unsigned int bsd_engine;
341 342 343 344 345 346 347 348

/* Client can have a maximum of 3 contexts banned before
 * it is denied of creating new contexts. As one context
 * ban needs 4 consecutive hangs, and more if there is
 * progress in between, this is a last resort stop gap measure
 * to limit the badly behaving clients access to gpu.
 */
#define I915_MAX_CLIENT_CONTEXT_BANS 3
349
	atomic_t context_bans;
350 351
};

L
Linus Torvalds 已提交
352 353 354
/* Interface history:
 *
 * 1.1: Original.
D
Dave Airlie 已提交
355 356
 * 1.2: Add Power Management
 * 1.3: Add vblank support
357
 * 1.4: Fix cmdbuffer path, add heap destroy
358
 * 1.5: Add vblank pipe configuration
=
=?utf-8?q?Michel_D=C3=A4nzer?= 已提交
359 360
 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 *      - Support vertical blank on secondary display pipe
L
Linus Torvalds 已提交
361 362
 */
#define DRIVER_MAJOR		1
=
=?utf-8?q?Michel_D=C3=A4nzer?= 已提交
363
#define DRIVER_MINOR		6
L
Linus Torvalds 已提交
364 365
#define DRIVER_PATCHLEVEL	0

366 367 368
struct intel_overlay;
struct intel_overlay_error_state;

369
struct sdvo_device_mapping {
C
Chris Wilson 已提交
370
	u8 initialized;
371 372 373
	u8 dvo_port;
	u8 slave_addr;
	u8 dvo_wiring;
C
Chris Wilson 已提交
374
	u8 i2c_pin;
375
	u8 ddc_pin;
376 377
};

378
struct intel_connector;
379
struct intel_encoder;
380
struct intel_atomic_state;
381
struct intel_crtc_state;
382
struct intel_initial_plane_config;
383
struct intel_crtc;
384 385
struct intel_limit;
struct dpll;
386
struct intel_cdclk_state;
387

388
struct drm_i915_display_funcs {
389 390
	void (*get_cdclk)(struct drm_i915_private *dev_priv,
			  struct intel_cdclk_state *cdclk_state);
391 392
	void (*set_cdclk)(struct drm_i915_private *dev_priv,
			  const struct intel_cdclk_state *cdclk_state);
393 394
	int (*get_fifo_size)(struct drm_i915_private *dev_priv,
			     enum i9xx_plane_id i9xx_plane);
395
	int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
396 397 398
	int (*compute_intermediate_wm)(struct drm_device *dev,
				       struct intel_crtc *intel_crtc,
				       struct intel_crtc_state *newstate);
399 400 401 402 403 404
	void (*initial_watermarks)(struct intel_atomic_state *state,
				   struct intel_crtc_state *cstate);
	void (*atomic_update_watermarks)(struct intel_atomic_state *state,
					 struct intel_crtc_state *cstate);
	void (*optimize_watermarks)(struct intel_atomic_state *state,
				    struct intel_crtc_state *cstate);
405
	int (*compute_global_watermarks)(struct drm_atomic_state *state);
406
	void (*update_wm)(struct intel_crtc *crtc);
407
	int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
408 409 410
	/* Returns the active state of the crtc, and if the crtc is active,
	 * fills out the pipe-config with the hw state. */
	bool (*get_pipe_config)(struct intel_crtc *,
411
				struct intel_crtc_state *);
412 413
	void (*get_initial_plane_config)(struct intel_crtc *,
					 struct intel_initial_plane_config *);
414 415
	int (*crtc_compute_clock)(struct intel_crtc *crtc,
				  struct intel_crtc_state *crtc_state);
416 417 418 419
	void (*crtc_enable)(struct intel_crtc_state *pipe_config,
			    struct drm_atomic_state *old_state);
	void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
			     struct drm_atomic_state *old_state);
420
	void (*update_crtcs)(struct drm_atomic_state *state);
421 422 423 424 425 426
	void (*audio_codec_enable)(struct intel_encoder *encoder,
				   const struct intel_crtc_state *crtc_state,
				   const struct drm_connector_state *conn_state);
	void (*audio_codec_disable)(struct intel_encoder *encoder,
				    const struct intel_crtc_state *old_crtc_state,
				    const struct drm_connector_state *old_conn_state);
427 428
	void (*fdi_link_train)(struct intel_crtc *crtc,
			       const struct intel_crtc_state *crtc_state);
429
	void (*init_clock_gating)(struct drm_i915_private *dev_priv);
430
	void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
431 432 433 434 435
	/* clock updates for mode set */
	/* cursor updates */
	/* render clock increase/decrease */
	/* display clock increase/decrease */
	/* pll clock increase/decrease */
436

437 438
	void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
	void (*load_luts)(struct drm_crtc_state *crtc_state);
439 440
};

441 442 443 444
#define CSR_VERSION(major, minor)	((major) << 16 | (minor))
#define CSR_VERSION_MAJOR(version)	((version) >> 16)
#define CSR_VERSION_MINOR(version)	((version) & 0xffff)

445
struct intel_csr {
446
	struct work_struct work;
447
	const char *fw_path;
448
	uint32_t *dmc_payload;
449
	uint32_t dmc_fw_size;
450
	uint32_t version;
451
	uint32_t mmio_count;
452
	i915_reg_t mmioaddr[8];
453
	uint32_t mmiodata[8];
454
	uint32_t dc_state;
455
	uint32_t allowed_dc_mask;
456 457
};

458 459
enum i915_cache_level {
	I915_CACHE_NONE = 0,
460 461 462 463 464
	I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
	I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
			      caches, eg sampler/render caches, and the
			      large Last-Level-Cache. LLC is coherent with
			      the CPU, but L3 is only visible to the GPU. */
465
	I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
466 467
};

468 469
#define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */

470 471 472 473 474
enum fb_op_origin {
	ORIGIN_GTT,
	ORIGIN_CPU,
	ORIGIN_CS,
	ORIGIN_FLIP,
475
	ORIGIN_DIRTYFB,
476 477
};

478
struct intel_fbc {
P
Paulo Zanoni 已提交
479 480 481
	/* This is always the inner lock when overlapping with struct_mutex and
	 * it's the outer lock when overlapping with stolen_lock. */
	struct mutex lock;
B
Ben Widawsky 已提交
482
	unsigned threshold;
483 484
	unsigned int possible_framebuffer_bits;
	unsigned int busy_bits;
485
	unsigned int visible_pipes_mask;
486
	struct intel_crtc *crtc;
487

488
	struct drm_mm_node compressed_fb;
489 490
	struct drm_mm_node *compressed_llb;

491 492
	bool false_color;

493
	bool enabled;
494
	bool active;
495

496 497 498
	bool underrun_detected;
	struct work_struct underrun_work;

499 500 501 502 503
	/*
	 * Due to the atomic rules we can't access some structures without the
	 * appropriate locking, so we cache information here in order to avoid
	 * these problems.
	 */
504
	struct intel_fbc_state_cache {
505
		struct i915_vma *vma;
506
		unsigned long flags;
507

508 509 510 511 512 513 514 515 516 517
		struct {
			unsigned int mode_flags;
			uint32_t hsw_bdw_pixel_rate;
		} crtc;

		struct {
			unsigned int rotation;
			int src_w;
			int src_h;
			bool visible;
518 519 520 521 522 523 524 525
			/*
			 * Display surface base address adjustement for
			 * pageflips. Note that on gen4+ this only adjusts up
			 * to a tile, offsets within a tile are handled in
			 * the hw itself (with the TILEOFF register).
			 */
			int adjusted_x;
			int adjusted_y;
526 527

			int y;
528 529 530
		} plane;

		struct {
531
			const struct drm_format_info *format;
532 533 534 535
			unsigned int stride;
		} fb;
	} state_cache;

536 537 538 539 540 541 542
	/*
	 * This structure contains everything that's relevant to program the
	 * hardware registers. When we want to figure out if we need to disable
	 * and re-enable FBC for a new configuration we just check if there's
	 * something different in the struct. The genx_fbc_activate functions
	 * are supposed to read from it in order to program the registers.
	 */
543
	struct intel_fbc_reg_params {
544
		struct i915_vma *vma;
545
		unsigned long flags;
546

547 548
		struct {
			enum pipe pipe;
549
			enum i9xx_plane_id i9xx_plane;
550 551 552 553
			unsigned int fence_y_offset;
		} crtc;

		struct {
554
			const struct drm_format_info *format;
555 556 557 558
			unsigned int stride;
		} fb;

		int cfb_size;
559
		unsigned int gen9_wa_cfb_stride;
560 561
	} params;

562
	struct intel_fbc_work {
563
		bool scheduled;
564
		u64 scheduled_vblank;
565 566
		struct work_struct work;
	} work;
567

568
	const char *no_fbc_reason;
569 570
};

571
/*
572 573 574 575 576 577 578 579 580 581 582 583 584 585
 * HIGH_RR is the highest eDP panel refresh rate read from EDID
 * LOW_RR is the lowest eDP panel refresh rate found from EDID
 * parsing for same resolution.
 */
enum drrs_refresh_rate_type {
	DRRS_HIGH_RR,
	DRRS_LOW_RR,
	DRRS_MAX_RR, /* RR count */
};

enum drrs_support_type {
	DRRS_NOT_SUPPORTED = 0,
	STATIC_DRRS_SUPPORT = 1,
	SEAMLESS_DRRS_SUPPORT = 2
586 587
};

588
struct intel_dp;
589 590 591 592 593 594 595 596 597
struct i915_drrs {
	struct mutex mutex;
	struct delayed_work work;
	struct intel_dp *dp;
	unsigned busy_frontbuffer_bits;
	enum drrs_refresh_rate_type refresh_rate_type;
	enum drrs_support_type type;
};

R
Rodrigo Vivi 已提交
598
struct i915_psr {
599
	struct mutex lock;
R
Rodrigo Vivi 已提交
600
	bool sink_support;
601
	struct intel_dp *enabled;
602 603
	bool active;
	struct delayed_work work;
604
	unsigned busy_frontbuffer_bits;
605
	bool sink_psr2_support;
606
	bool link_standby;
607
	bool colorimetry_support;
608
	bool alpm;
609
	bool has_hw_tracking;
610
	bool psr2_enabled;
611
	u8 sink_sync_latency;
612

613 614
	void (*enable_source)(struct intel_dp *,
			      const struct intel_crtc_state *);
615 616
	void (*disable_source)(struct intel_dp *,
			       const struct intel_crtc_state *);
617
	void (*enable_sink)(struct intel_dp *);
R
Rodrigo Vivi 已提交
618
	void (*activate)(struct intel_dp *);
619
	void (*setup_vsc)(struct intel_dp *, const struct intel_crtc_state *);
620
};
621

622
enum intel_pch {
623
	PCH_NONE = 0,	/* No PCH present */
624
	PCH_IBX,	/* Ibexpeak PCH */
625 626
	PCH_CPT,	/* Cougarpoint/Pantherpoint PCH */
	PCH_LPT,	/* Lynxpoint/Wildcatpoint PCH */
627
	PCH_SPT,        /* Sunrisepoint PCH */
628 629
	PCH_KBP,        /* Kaby Lake PCH */
	PCH_CNP,        /* Cannon Lake PCH */
630
	PCH_ICP,	/* Ice Lake PCH */
B
Ben Widawsky 已提交
631
	PCH_NOP,
632 633
};

634 635 636 637 638
enum intel_sbi_destination {
	SBI_ICLK,
	SBI_MPHY,
};

639
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
640
#define QUIRK_INVERT_BRIGHTNESS (1<<2)
641
#define QUIRK_BACKLIGHT_PRESENT (1<<3)
642
#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
643
#define QUIRK_INCREASE_T12_DELAY (1<<6)
644

645
struct intel_fbdev;
646
struct intel_fbc_work;
647

648 649
struct intel_gmbus {
	struct i2c_adapter adapter;
650
#define GMBUS_FORCE_BIT_RETRY (1U << 31)
651
	u32 force_bit;
652
	u32 reg0;
653
	i915_reg_t gpio_reg;
654
	struct i2c_algo_bit_data bit_algo;
655 656 657
	struct drm_i915_private *dev_priv;
};

658
struct i915_suspend_saved_registers {
659
	u32 saveDSPARB;
J
Jesse Barnes 已提交
660
	u32 saveFBC_CONTROL;
661 662
	u32 saveCACHE_MODE_0;
	u32 saveMI_ARB_STATE;
J
Jesse Barnes 已提交
663 664
	u32 saveSWF0[16];
	u32 saveSWF1[16];
665
	u32 saveSWF3[3];
666
	uint64_t saveFENCE[I915_MAX_NUM_FENCES];
667
	u32 savePCH_PORT_HOTPLUG;
668
	u16 saveGCDGMBUS;
669
};
670

671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728
struct vlv_s0ix_state {
	/* GAM */
	u32 wr_watermark;
	u32 gfx_prio_ctrl;
	u32 arb_mode;
	u32 gfx_pend_tlb0;
	u32 gfx_pend_tlb1;
	u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
	u32 media_max_req_count;
	u32 gfx_max_req_count;
	u32 render_hwsp;
	u32 ecochk;
	u32 bsd_hwsp;
	u32 blt_hwsp;
	u32 tlb_rd_addr;

	/* MBC */
	u32 g3dctl;
	u32 gsckgctl;
	u32 mbctl;

	/* GCP */
	u32 ucgctl1;
	u32 ucgctl3;
	u32 rcgctl1;
	u32 rcgctl2;
	u32 rstctl;
	u32 misccpctl;

	/* GPM */
	u32 gfxpause;
	u32 rpdeuhwtc;
	u32 rpdeuc;
	u32 ecobus;
	u32 pwrdwnupctl;
	u32 rp_down_timeout;
	u32 rp_deucsw;
	u32 rcubmabdtmr;
	u32 rcedata;
	u32 spare2gh;

	/* Display 1 CZ domain */
	u32 gt_imr;
	u32 gt_ier;
	u32 pm_imr;
	u32 pm_ier;
	u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];

	/* GT SA CZ domain */
	u32 tilectl;
	u32 gt_fifoctl;
	u32 gtlc_wake_ctrl;
	u32 gtlc_survive;
	u32 pmwgicz;

	/* Display 2 CZ domain */
	u32 gu_ctl0;
	u32 gu_ctl1;
729
	u32 pcbr;
730 731 732
	u32 clock_gate_dis2;
};

733
struct intel_rps_ei {
734
	ktime_t ktime;
735 736
	u32 render_c0;
	u32 media_c0;
737 738
};

739
struct intel_rps {
I
Imre Deak 已提交
740 741 742 743
	/*
	 * work, interrupts_enabled and pm_iir are protected by
	 * dev_priv->irq_lock
	 */
744
	struct work_struct work;
I
Imre Deak 已提交
745
	bool interrupts_enabled;
746
	u32 pm_iir;
747

748
	/* PM interrupt bits that should never be masked */
749
	u32 pm_intrmsk_mbz;
750

751 752 753 754 755 756 757 758 759 760 761 762 763 764 765
	/* Frequencies are stored in potentially platform dependent multiples.
	 * In other words, *_freq needs to be multiplied by X to be interesting.
	 * Soft limits are those which are used for the dynamic reclocking done
	 * by the driver (raise frequencies under heavy loads, and lower for
	 * lighter loads). Hard limits are those imposed by the hardware.
	 *
	 * A distinction is made for overclocking, which is never enabled by
	 * default, and is considered to be above the hard limit if it's
	 * possible at all.
	 */
	u8 cur_freq;		/* Current frequency (cached, may not == HW) */
	u8 min_freq_softlimit;	/* Minimum frequency permitted by the driver */
	u8 max_freq_softlimit;	/* Max frequency permitted by the driver */
	u8 max_freq;		/* Maximum frequency, RP0 if not overclocking */
	u8 min_freq;		/* AKA RPn. Minimum frequency */
766
	u8 boost_freq;		/* Frequency to request when wait boosting */
767
	u8 idle_freq;		/* Frequency to request when we are idle */
768 769 770
	u8 efficient_freq;	/* AKA RPe. Pre-determined balanced frequency */
	u8 rp1_freq;		/* "less than" RP0 power/freqency */
	u8 rp0_freq;		/* Non-overclocked max frequency. */
771
	u16 gpll_ref_freq;	/* vlv/chv GPLL reference frequency */
772

773 774 775
	u8 up_threshold; /* Current %busy required to uplock */
	u8 down_threshold; /* Current %busy required to downclock */

776 777 778
	int last_adj;
	enum { LOW_POWER, BETWEEN, HIGH_POWER } power;

779
	bool enabled;
780 781
	atomic_t num_waiters;
	atomic_t boosts;
782

783
	/* manual wa residency calculations */
784
	struct intel_rps_ei ei;
785 786
};

787 788
struct intel_rc6 {
	bool enabled;
789 790
	u64 prev_hw_residency[4];
	u64 cur_residency[4];
791 792 793 794 795 796
};

struct intel_llc_pstate {
	bool enabled;
};

797 798
struct intel_gen6_power_mgmt {
	struct intel_rps rps;
799 800
	struct intel_rc6 rc6;
	struct intel_llc_pstate llc_pstate;
801 802
};

D
Daniel Vetter 已提交
803 804 805
/* defined intel_pm.c */
extern spinlock_t mchdev_lock;

806 807 808 809 810 811 812 813 814 815 816
struct intel_ilk_power_mgmt {
	u8 cur_delay;
	u8 min_delay;
	u8 max_delay;
	u8 fmax;
	u8 fstart;

	u64 last_count1;
	unsigned long last_time1;
	unsigned long chipset_power;
	u64 last_count2;
817
	u64 last_time2;
818 819 820 821 822 823 824
	unsigned long gfx_power;
	u8 corr;

	int c_m;
	int r_t;
};

825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854
struct drm_i915_private;
struct i915_power_well;

struct i915_power_well_ops {
	/*
	 * Synchronize the well's hw state to match the current sw state, for
	 * example enable/disable it based on the current refcount. Called
	 * during driver init and resume time, possibly after first calling
	 * the enable/disable handlers.
	 */
	void (*sync_hw)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/*
	 * Enable the well and resources that depend on it (for example
	 * interrupts located on the well). Called after the 0->1 refcount
	 * transition.
	 */
	void (*enable)(struct drm_i915_private *dev_priv,
		       struct i915_power_well *power_well);
	/*
	 * Disable the well and resources that depend on it. Called after
	 * the 1->0 refcount transition.
	 */
	void (*disable)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/* Returns the hw enabled state. */
	bool (*is_enabled)(struct drm_i915_private *dev_priv,
			   struct i915_power_well *power_well);
};

855 856
/* Power well structure for haswell */
struct i915_power_well {
857
	const char *name;
858
	bool always_on;
859 860
	/* power well enable/disable usage count */
	int count;
861 862
	/* cached hw enabled state */
	bool hw_enabled;
863
	u64 domains;
864
	/* unique identifier for this power well */
I
Imre Deak 已提交
865
	enum i915_power_well_id id;
866 867 868 869
	/*
	 * Arbitraty data associated with this power well. Platform and power
	 * well specific.
	 */
870 871 872 873
	union {
		struct {
			enum dpio_phy phy;
		} bxt;
874 875 876 877 878
		struct {
			/* Mask of pipes whose IRQ logic is backed by the pw */
			u8 irq_pipe_mask;
			/* The pw is backing the VGA functionality */
			bool has_vga:1;
879
			bool has_fuses:1;
880
		} hsw;
881
	};
882
	const struct i915_power_well_ops *ops;
883 884
};

885
struct i915_power_domains {
886 887 888 889 890
	/*
	 * Power wells needed for initialization at driver init and suspend
	 * time are on. They are kept on until after the first modeset.
	 */
	bool init_power_on;
891
	bool initializing;
892
	int power_well_count;
893

894
	struct mutex lock;
895
	int domain_use_count[POWER_DOMAIN_NUM];
896
	struct i915_power_well *power_wells;
897 898
};

899
#define MAX_L3_SLICES 2
900
struct intel_l3_parity {
901
	u32 *remap_info[MAX_L3_SLICES];
902
	struct work_struct error_work;
903
	int which_slice;
904 905
};

906 907 908
struct i915_gem_mm {
	/** Memory allocator for GTT stolen memory */
	struct drm_mm stolen;
909 910 911 912
	/** Protects the usage of the GTT stolen memory allocator. This is
	 * always the inner lock when overlapping with struct_mutex. */
	struct mutex stolen_lock;

913 914 915
	/* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
	spinlock_t obj_lock;

916 917 918 919 920
	/** List of all objects in gtt_space. Used to restore gtt
	 * mappings on resume */
	struct list_head bound_list;
	/**
	 * List of objects which are not bound to the GTT (thus
921 922
	 * are idle and not used by the GPU). These objects may or may
	 * not actually have any pages attached.
923 924 925
	 */
	struct list_head unbound_list;

926 927 928 929 930
	/** List of all objects in gtt_space, currently mmaped by userspace.
	 * All objects within this list must also be on bound_list.
	 */
	struct list_head userfault_list;

931 932 933 934 935
	/**
	 * List of objects which are pending destruction.
	 */
	struct llist_head free_list;
	struct work_struct free_work;
936
	spinlock_t free_lock;
937 938 939 940 941
	/**
	 * Count of objects pending destructions. Used to skip needlessly
	 * waiting on an RCU barrier if no objects are waiting to be freed.
	 */
	atomic_t free_count;
942

943 944 945 946 947
	/**
	 * Small stash of WC pages
	 */
	struct pagevec wc_stash;

M
Matthew Auld 已提交
948 949 950 951 952
	/**
	 * tmpfs instance used for shmem backed objects
	 */
	struct vfsmount *gemfs;

953 954 955
	/** PPGTT used for aliasing the PPGTT with the GTT */
	struct i915_hw_ppgtt *aliasing_ppgtt;

956
	struct notifier_block oom_notifier;
957
	struct notifier_block vmap_notifier;
958
	struct shrinker shrinker;
959 960 961 962

	/** LRU list of objects with fence regs on them. */
	struct list_head fence_list;

963 964 965 966 967 968 969
	/**
	 * Workqueue to fault in userptr pages, flushed by the execbuf
	 * when required but otherwise left to userspace to try again
	 * on EAGAIN.
	 */
	struct workqueue_struct *userptr_wq;

970 971
	u64 unordered_timeline;

972
	/* the indicator for dispatch video commands on two BSD rings */
973
	atomic_t bsd_engine_dispatch_index;
974

975 976 977 978 979 980
	/** Bit 6 swizzling required for X tiling */
	uint32_t bit_6_swizzle_x;
	/** Bit 6 swizzling required for Y tiling */
	uint32_t bit_6_swizzle_y;

	/* accounting, useful for userland debugging */
981
	spinlock_t object_stat_lock;
982
	u64 object_memory;
983 984 985
	u32 object_count;
};

986 987
#define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */

988 989 990
#define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
#define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */

991 992 993
#define I915_ENGINE_DEAD_TIMEOUT  (4 * HZ)  /* Seqno, head and subunits dead */
#define I915_SEQNO_DEAD_TIMEOUT   (12 * HZ) /* Seqno dead with active head */

994 995 996 997 998 999
enum modeset_restore {
	MODESET_ON_LID_OPEN,
	MODESET_DONE,
	MODESET_SUSPENDED,
};

1000 1001 1002 1003
#define DP_AUX_A 0x40
#define DP_AUX_B 0x10
#define DP_AUX_C 0x20
#define DP_AUX_D 0x30
R
Rodrigo Vivi 已提交
1004
#define DP_AUX_F 0x60
1005

X
Xiong Zhang 已提交
1006 1007 1008 1009
#define DDC_PIN_B  0x05
#define DDC_PIN_C  0x04
#define DDC_PIN_D  0x06

1010
struct ddi_vbt_port_info {
1011 1012
	int max_tmds_clock;

1013 1014 1015 1016 1017 1018
	/*
	 * This is an index in the HDMI/DVI DDI buffer translation table.
	 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
	 * populate this field.
	 */
#define HDMI_LEVEL_SHIFT_UNKNOWN	0xff
1019
	uint8_t hdmi_level_shift;
1020 1021 1022 1023

	uint8_t supports_dvi:1;
	uint8_t supports_hdmi:1;
	uint8_t supports_dp:1;
1024
	uint8_t supports_edp:1;
1025 1026

	uint8_t alternate_aux_channel;
X
Xiong Zhang 已提交
1027
	uint8_t alternate_ddc_pin;
1028 1029 1030

	uint8_t dp_boost_level;
	uint8_t hdmi_boost_level;
1031
	int dp_max_link_rate;		/* 0 for not limited by VBT */
1032 1033
};

R
Rodrigo Vivi 已提交
1034 1035 1036 1037 1038
enum psr_lines_to_wait {
	PSR_0_LINES_TO_WAIT = 0,
	PSR_1_LINE_TO_WAIT,
	PSR_4_LINES_TO_WAIT,
	PSR_8_LINES_TO_WAIT
1039 1040
};

1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052
struct intel_vbt_data {
	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */

	/* Feature bits */
	unsigned int int_tv_support:1;
	unsigned int lvds_dither:1;
	unsigned int lvds_vbt:1;
	unsigned int int_crt_support:1;
	unsigned int lvds_use_ssc:1;
	unsigned int display_clock_mode:1;
	unsigned int fdi_rx_polarity_inverted:1;
1053
	unsigned int panel_type:4;
1054 1055 1056
	int lvds_ssc_freq;
	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */

1057 1058
	enum drrs_support_type drrs_type;

1059 1060 1061 1062 1063
	struct {
		int rate;
		int lanes;
		int preemphasis;
		int vswing;
1064
		bool low_vswing;
1065 1066 1067 1068 1069
		bool initialized;
		bool support;
		int bpp;
		struct edp_power_seq pps;
	} edp;
1070

R
Rodrigo Vivi 已提交
1071 1072 1073 1074 1075 1076 1077 1078 1079
	struct {
		bool full_link;
		bool require_aux_wakeup;
		int idle_frames;
		enum psr_lines_to_wait lines_to_wait;
		int tp1_wakeup_time;
		int tp2_tp3_wakeup_time;
	} psr;

1080 1081
	struct {
		u16 pwm_freq_hz;
1082
		bool present;
1083
		bool active_low_pwm;
1084
		u8 min_brightness;	/* min_brightness/255 of max */
1085
		u8 controller;		/* brightness controller number */
1086
		enum intel_backlight_type type;
1087 1088
	} backlight;

1089 1090 1091
	/* MIPI DSI */
	struct {
		u16 panel_id;
1092 1093
		struct mipi_config *config;
		struct mipi_pps_data *pps;
1094 1095
		u16 bl_ports;
		u16 cabc_ports;
1096 1097 1098
		u8 seq_version;
		u32 size;
		u8 *data;
1099
		const u8 *sequence[MIPI_SEQ_MAX];
1100
		u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
1101 1102
	} dsi;

1103 1104 1105
	int crt_ddc_pin;

	int child_dev_num;
1106
	struct child_device_config *child_dev;
1107 1108

	struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1109
	struct sdvo_device_mapping sdvo_mappings[2];
1110 1111
};

1112 1113 1114 1115 1116
enum intel_ddb_partitioning {
	INTEL_DDB_PART_1_2,
	INTEL_DDB_PART_5_6, /* IVB+ */
};

1117 1118 1119 1120 1121 1122 1123 1124
struct intel_wm_level {
	bool enable;
	uint32_t pri_val;
	uint32_t spr_val;
	uint32_t cur_val;
	uint32_t fbc_val;
};

1125
struct ilk_wm_values {
1126 1127 1128 1129 1130 1131 1132 1133
	uint32_t wm_pipe[3];
	uint32_t wm_lp[3];
	uint32_t wm_lp_spr[3];
	uint32_t wm_linetime[3];
	bool enable_fbc_wm;
	enum intel_ddb_partitioning partitioning;
};

1134
struct g4x_pipe_wm {
1135
	uint16_t plane[I915_MAX_PLANES];
1136
	uint16_t fbc;
1137
};
1138

1139
struct g4x_sr_wm {
1140
	uint16_t plane;
1141
	uint16_t cursor;
1142
	uint16_t fbc;
1143 1144 1145 1146
};

struct vlv_wm_ddl_values {
	uint8_t plane[I915_MAX_PLANES];
1147
};
1148

1149
struct vlv_wm_values {
1150 1151
	struct g4x_pipe_wm pipe[3];
	struct g4x_sr_wm sr;
1152
	struct vlv_wm_ddl_values ddl[3];
1153 1154
	uint8_t level;
	bool cxsr;
1155 1156
};

1157 1158 1159 1160 1161 1162 1163 1164 1165
struct g4x_wm_values {
	struct g4x_pipe_wm pipe[2];
	struct g4x_sr_wm sr;
	struct g4x_sr_wm hpll;
	bool cxsr;
	bool hpll_en;
	bool fbc_en;
};

1166
struct skl_ddb_entry {
1167
	uint16_t start, end;	/* in number of blocks, 'end' is exclusive */
1168 1169 1170 1171
};

static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
{
1172
	return entry->end - entry->start;
1173 1174
}

1175 1176 1177 1178 1179 1180 1181 1182 1183
static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
				       const struct skl_ddb_entry *e2)
{
	if (e1->start == e2->start && e1->end == e2->end)
		return true;

	return false;
}

1184
struct skl_ddb_allocation {
1185 1186 1187
	/* packed/y */
	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
	struct skl_ddb_entry uv_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1188 1189
};

1190
struct skl_ddb_values {
1191
	unsigned dirty_pipes;
1192
	struct skl_ddb_allocation ddb;
1193 1194 1195
};

struct skl_wm_level {
L
Lyude 已提交
1196 1197 1198
	bool plane_en;
	uint16_t plane_res_b;
	uint8_t plane_res_l;
1199 1200
};

1201 1202 1203 1204
/* Stores plane specific WM parameters */
struct skl_wm_params {
	bool x_tiled, y_tiled;
	bool rc_surface;
1205
	bool is_planar;
1206 1207 1208 1209 1210 1211 1212 1213
	uint32_t width;
	uint8_t cpp;
	uint32_t plane_pixel_rate;
	uint32_t y_min_scanlines;
	uint32_t plane_bytes_per_line;
	uint_fixed_16_16_t plane_blocks_per_line;
	uint_fixed_16_16_t y_tile_minimum;
	uint32_t linetime_us;
1214
	uint32_t dbuf_block_size;
1215 1216
};

1217
/*
1218 1219 1220 1221
 * This struct helps tracking the state needed for runtime PM, which puts the
 * device in PCI D3 state. Notice that when this happens, nothing on the
 * graphics device works, even register access, so we don't get interrupts nor
 * anything else.
1222
 *
1223 1224 1225
 * Every piece of our code that needs to actually touch the hardware needs to
 * either call intel_runtime_pm_get or call intel_display_power_get with the
 * appropriate power domain.
1226
 *
1227 1228
 * Our driver uses the autosuspend delay feature, which means we'll only really
 * suspend if we stay with zero refcount for a certain amount of time. The
1229
 * default value is currently very conservative (see intel_runtime_pm_enable), but
1230
 * it can be changed with the standard runtime PM files from sysfs.
1231 1232 1233 1234 1235
 *
 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
 * goes back to false exactly before we reenable the IRQs. We use this variable
 * to check if someone is trying to enable/disable IRQs while they're supposed
 * to be disabled. This shouldn't happen and we'll print some error messages in
1236
 * case it happens.
1237
 *
1238
 * For more, read the Documentation/power/runtime_pm.txt.
1239
 */
1240
struct i915_runtime_pm {
1241
	atomic_t wakeref_count;
1242
	bool suspended;
1243
	bool irqs_enabled;
1244 1245
};

1246 1247 1248 1249 1250
enum intel_pipe_crc_source {
	INTEL_PIPE_CRC_SOURCE_NONE,
	INTEL_PIPE_CRC_SOURCE_PLANE1,
	INTEL_PIPE_CRC_SOURCE_PLANE2,
	INTEL_PIPE_CRC_SOURCE_PF,
1251
	INTEL_PIPE_CRC_SOURCE_PIPE,
D
Daniel Vetter 已提交
1252 1253 1254 1255 1256
	/* TV/DP on pre-gen5/vlv can't use the pipe source. */
	INTEL_PIPE_CRC_SOURCE_TV,
	INTEL_PIPE_CRC_SOURCE_DP_B,
	INTEL_PIPE_CRC_SOURCE_DP_C,
	INTEL_PIPE_CRC_SOURCE_DP_D,
1257
	INTEL_PIPE_CRC_SOURCE_AUTO,
1258 1259 1260
	INTEL_PIPE_CRC_SOURCE_MAX,
};

1261
struct intel_pipe_crc_entry {
1262
	uint32_t frame;
1263 1264 1265
	uint32_t crc[5];
};

1266
#define INTEL_PIPE_CRC_ENTRIES_NR	128
1267
struct intel_pipe_crc {
1268 1269
	spinlock_t lock;
	bool opened;		/* exclusive access to the result file */
1270
	struct intel_pipe_crc_entry *entries;
1271
	enum intel_pipe_crc_source source;
1272
	int head, tail;
1273
	wait_queue_head_t wq;
T
Tomeu Vizoso 已提交
1274
	int skipped;
1275 1276
};

1277
struct i915_frontbuffer_tracking {
1278
	spinlock_t lock;
1279 1280 1281 1282 1283 1284 1285 1286 1287

	/*
	 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
	 * scheduled flips.
	 */
	unsigned busy_bits;
	unsigned flip_bits;
};

1288
struct i915_wa_reg {
1289
	i915_reg_t addr;
1290 1291 1292 1293 1294
	u32 value;
	/* bitmask representing WA bits */
	u32 mask;
};

1295
#define I915_MAX_WA_REGS 16
1296 1297 1298 1299

struct i915_workarounds {
	struct i915_wa_reg reg[I915_MAX_WA_REGS];
	u32 count;
1300
	u32 hw_whitelist_count[I915_NUM_ENGINES];
1301 1302
};

1303 1304
struct i915_virtual_gpu {
	bool active;
1305
	u32 caps;
1306 1307
};

1308 1309 1310 1311 1312 1313 1314
/* used in computing the new watermarks state */
struct intel_wm_config {
	unsigned int num_pipes_active;
	bool sprites_enabled;
	bool sprites_scaled;
};

1315 1316 1317 1318 1319
struct i915_oa_format {
	u32 format;
	int size;
};

1320 1321 1322 1323 1324
struct i915_oa_reg {
	i915_reg_t addr;
	u32 value;
};

1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338
struct i915_oa_config {
	char uuid[UUID_STRING_LEN + 1];
	int id;

	const struct i915_oa_reg *mux_regs;
	u32 mux_regs_len;
	const struct i915_oa_reg *b_counter_regs;
	u32 b_counter_regs_len;
	const struct i915_oa_reg *flex_regs;
	u32 flex_regs_len;

	struct attribute_group sysfs_metric;
	struct attribute *attrs[2];
	struct device_attribute sysfs_metric_id;
1339 1340

	atomic_t ref_count;
1341 1342
};

1343 1344
struct i915_perf_stream;

1345 1346 1347
/**
 * struct i915_perf_stream_ops - the OPs to support a specific stream type
 */
1348
struct i915_perf_stream_ops {
1349 1350 1351 1352
	/**
	 * @enable: Enables the collection of HW samples, either in response to
	 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
	 * without `I915_PERF_FLAG_DISABLED`.
1353 1354 1355
	 */
	void (*enable)(struct i915_perf_stream *stream);

1356 1357 1358 1359
	/**
	 * @disable: Disables the collection of HW samples, either in response
	 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
	 * the stream.
1360 1361 1362
	 */
	void (*disable)(struct i915_perf_stream *stream);

1363 1364
	/**
	 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1365 1366 1367 1368 1369 1370
	 * once there is something ready to read() for the stream
	 */
	void (*poll_wait)(struct i915_perf_stream *stream,
			  struct file *file,
			  poll_table *wait);

1371 1372 1373
	/**
	 * @wait_unlocked: For handling a blocking read, wait until there is
	 * something to ready to read() for the stream. E.g. wait on the same
1374
	 * wait queue that would be passed to poll_wait().
1375 1376 1377
	 */
	int (*wait_unlocked)(struct i915_perf_stream *stream);

1378 1379 1380 1381 1382 1383 1384
	/**
	 * @read: Copy buffered metrics as records to userspace
	 * **buf**: the userspace, destination buffer
	 * **count**: the number of bytes to copy, requested by userspace
	 * **offset**: zero at the start of the read, updated as the read
	 * proceeds, it represents how many bytes have been copied so far and
	 * the buffer offset for copying the next record.
1385
	 *
1386 1387
	 * Copy as many buffered i915 perf samples and records for this stream
	 * to userspace as will fit in the given buffer.
1388
	 *
1389 1390
	 * Only write complete records; returning -%ENOSPC if there isn't room
	 * for a complete record.
1391
	 *
1392 1393 1394
	 * Return any error condition that results in a short read such as
	 * -%ENOSPC or -%EFAULT, even though these may be squashed before
	 * returning to userspace.
1395 1396 1397 1398 1399 1400
	 */
	int (*read)(struct i915_perf_stream *stream,
		    char __user *buf,
		    size_t count,
		    size_t *offset);

1401 1402
	/**
	 * @destroy: Cleanup any stream specific resources.
1403 1404 1405 1406 1407 1408
	 *
	 * The stream will always be disabled before this is called.
	 */
	void (*destroy)(struct i915_perf_stream *stream);
};

1409 1410 1411
/**
 * struct i915_perf_stream - state for a single open stream FD
 */
1412
struct i915_perf_stream {
1413 1414 1415
	/**
	 * @dev_priv: i915 drm device
	 */
1416 1417
	struct drm_i915_private *dev_priv;

1418 1419 1420
	/**
	 * @link: Links the stream into ``&drm_i915_private->streams``
	 */
1421 1422
	struct list_head link;

1423 1424 1425 1426 1427
	/**
	 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
	 * properties given when opening a stream, representing the contents
	 * of a single sample as read() by userspace.
	 */
1428
	u32 sample_flags;
1429 1430 1431 1432 1433 1434

	/**
	 * @sample_size: Considering the configured contents of a sample
	 * combined with the required header size, this is the total size
	 * of a single sample record.
	 */
1435
	int sample_size;
1436

1437 1438 1439 1440
	/**
	 * @ctx: %NULL if measuring system-wide across all contexts or a
	 * specific context that is being monitored.
	 */
1441
	struct i915_gem_context *ctx;
1442 1443 1444 1445 1446 1447

	/**
	 * @enabled: Whether the stream is currently enabled, considering
	 * whether the stream was opened in a disabled state and based
	 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
	 */
1448 1449
	bool enabled;

1450 1451 1452 1453
	/**
	 * @ops: The callbacks providing the implementation of this specific
	 * type of configured stream.
	 */
1454
	const struct i915_perf_stream_ops *ops;
1455 1456 1457 1458 1459

	/**
	 * @oa_config: The OA configuration used by the stream.
	 */
	struct i915_oa_config *oa_config;
1460 1461
};

1462 1463 1464
/**
 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
 */
1465
struct i915_oa_ops {
1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484
	/**
	 * @is_valid_b_counter_reg: Validates register's address for
	 * programming boolean counters for a particular platform.
	 */
	bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv,
				       u32 addr);

	/**
	 * @is_valid_mux_reg: Validates register's address for programming mux
	 * for a particular platform.
	 */
	bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr);

	/**
	 * @is_valid_flex_reg: Validates register's address for programming
	 * flex EU filtering for a particular platform.
	 */
	bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr);

1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499
	/**
	 * @init_oa_buffer: Resets the head and tail pointers of the
	 * circular buffer for periodic OA reports.
	 *
	 * Called when first opening a stream for OA metrics, but also may be
	 * called in response to an OA buffer overflow or other error
	 * condition.
	 *
	 * Note it may be necessary to clear the full OA buffer here as part of
	 * maintaining the invariable that new reports must be written to
	 * zeroed memory for us to be able to reliable detect if an expected
	 * report has not yet landed in memory.  (At least on Haswell the OA
	 * buffer tail pointer is not synchronized with reports being visible
	 * to the CPU)
	 */
1500
	void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
1501

1502 1503 1504 1505
	/**
	 * @enable_metric_set: Selects and applies any MUX configuration to set
	 * up the Boolean and Custom (B/C) counters that are part of the
	 * counter reports being sampled. May apply system constraints such as
1506 1507
	 * disabling EU clock gating as required.
	 */
1508 1509
	int (*enable_metric_set)(struct drm_i915_private *dev_priv,
				 const struct i915_oa_config *oa_config);
1510 1511 1512 1513 1514

	/**
	 * @disable_metric_set: Remove system constraints associated with using
	 * the OA unit.
	 */
1515
	void (*disable_metric_set)(struct drm_i915_private *dev_priv);
1516 1517 1518 1519

	/**
	 * @oa_enable: Enable periodic sampling
	 */
1520
	void (*oa_enable)(struct drm_i915_private *dev_priv);
1521 1522 1523 1524

	/**
	 * @oa_disable: Disable periodic sampling
	 */
1525
	void (*oa_disable)(struct drm_i915_private *dev_priv);
1526 1527 1528 1529 1530

	/**
	 * @read: Copy data from the circular OA buffer into a given userspace
	 * buffer.
	 */
1531 1532 1533 1534
	int (*read)(struct i915_perf_stream *stream,
		    char __user *buf,
		    size_t count,
		    size_t *offset);
1535 1536

	/**
1537
	 * @oa_hw_tail_read: read the OA tail pointer register
1538
	 *
1539 1540 1541
	 * In particular this enables us to share all the fiddly code for
	 * handling the OA unit tail pointer race that affects multiple
	 * generations.
1542
	 */
1543
	u32 (*oa_hw_tail_read)(struct drm_i915_private *dev_priv);
1544 1545
};

1546
struct intel_cdclk_state {
1547
	unsigned int cdclk, vco, ref, bypass;
1548
	u8 voltage_level;
1549 1550
};

1551
struct drm_i915_private {
1552 1553
	struct drm_device drm;

1554
	struct kmem_cache *objects;
1555
	struct kmem_cache *vmas;
1556
	struct kmem_cache *luts;
1557
	struct kmem_cache *requests;
1558
	struct kmem_cache *dependencies;
1559
	struct kmem_cache *priorities;
1560

1561
	const struct intel_device_info info;
1562
	struct intel_driver_caps caps;
1563

1564 1565 1566
	/**
	 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
	 * end of stolen which we can optionally use to create GEM objects
1567
	 * backed by stolen memory. Note that stolen_usable_size tells us
1568 1569 1570 1571
	 * exactly how much of this we are actually allowed to use, given that
	 * some portion of it is in fact reserved for use by hardware functions.
	 */
	struct resource dsm;
1572 1573 1574 1575
	/**
	 * Reseved portion of Data Stolen Memory
	 */
	struct resource dsm_reserved;
1576

1577 1578 1579 1580 1581 1582 1583 1584 1585
	/*
	 * Stolen memory is segmented in hardware with different portions
	 * offlimits to certain functions.
	 *
	 * The drm_mm is initialised to the total accessible range, as found
	 * from the PCI config. On Broadwell+, this is further restricted to
	 * avoid the first page! The upper end of stolen memory is reserved for
	 * hardware functions and similarly removed from the accessible range.
	 */
1586
	resource_size_t stolen_usable_size;	/* Total size minus reserved ranges */
1587

1588 1589
	void __iomem *regs;

1590
	struct intel_uncore uncore;
1591

1592 1593
	struct i915_virtual_gpu vgpu;

1594
	struct intel_gvt *gvt;
1595

1596 1597
	struct intel_wopcm wopcm;

1598
	struct intel_huc huc;
1599 1600
	struct intel_guc guc;

1601 1602
	struct intel_csr csr;

1603
	struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1604

1605 1606 1607 1608 1609 1610 1611 1612 1613
	/** gmbus_mutex protects against concurrent usage of the single hw gmbus
	 * controller on different i2c buses. */
	struct mutex gmbus_mutex;

	/**
	 * Base address of the gmbus and gpio block.
	 */
	uint32_t gpio_mmio_base;

1614 1615 1616
	/* MMIO base address for MIPI regs */
	uint32_t mipi_mmio_base;

1617 1618
	uint32_t psr_mmio_base;

1619 1620
	uint32_t pps_mmio_base;

1621 1622
	wait_queue_head_t gmbus_wait_queue;

1623
	struct pci_dev *bridge_dev;
1624
	struct intel_engine_cs *engine[I915_NUM_ENGINES];
1625 1626 1627 1628
	/* Context used internally to idle the GPU and setup initial state */
	struct i915_gem_context *kernel_context;
	/* Context only to be used for injecting preemption commands */
	struct i915_gem_context *preempt_context;
1629 1630
	struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1]
					    [MAX_ENGINE_INSTANCE + 1];
1631

1632
	struct drm_dma_handle *status_page_dmah;
1633 1634 1635 1636 1637
	struct resource mch_res;

	/* protects the irq masks */
	spinlock_t irq_lock;

1638 1639
	bool display_irqs_enabled;

1640 1641 1642
	/* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
	struct pm_qos_request pm_qos;

V
Ville Syrjälä 已提交
1643 1644
	/* Sideband mailbox protection */
	struct mutex sb_lock;
1645 1646

	/** Cached value of IMR to avoid reads in updating the bitfield */
1647 1648 1649 1650
	union {
		u32 irq_mask;
		u32 de_irq_mask[I915_MAX_PIPES];
	};
1651
	u32 gt_irq_mask;
1652 1653
	u32 pm_imr;
	u32 pm_ier;
1654
	u32 pm_rps_events;
1655
	u32 pm_guc_events;
1656
	u32 pipestat_irq_mask[I915_MAX_PIPES];
1657

1658
	struct i915_hotplug hotplug;
1659
	struct intel_fbc fbc;
1660
	struct i915_drrs drrs;
1661
	struct intel_opregion opregion;
1662
	struct intel_vbt_data vbt;
1663

1664 1665
	bool preserve_bios_swizzle;

1666 1667 1668
	/* overlay */
	struct intel_overlay *overlay;

1669
	/* backlight registers and fields in struct intel_panel */
1670
	struct mutex backlight_lock;
1671

1672 1673 1674
	/* LVDS info */
	bool no_aux_handshake;

V
Ville Syrjälä 已提交
1675 1676 1677
	/* protects panel power sequencer state */
	struct mutex pps_mutex;

1678 1679 1680 1681
	struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
	int num_fence_regs; /* 8 on pre-965, 16 otherwise */

	unsigned int fsb_freq, mem_freq, is_ddr3;
1682
	unsigned int skl_preferred_vco_freq;
1683
	unsigned int max_cdclk_freq;
1684

M
Mika Kahola 已提交
1685
	unsigned int max_dotclk_freq;
1686
	unsigned int rawclk_freq;
1687
	unsigned int hpll_freq;
1688
	unsigned int fdi_pll_freq;
1689
	unsigned int czclk_freq;
1690

1691
	struct {
1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705
		/*
		 * The current logical cdclk state.
		 * See intel_atomic_state.cdclk.logical
		 *
		 * For reading holding any crtc lock is sufficient,
		 * for writing must hold all of them.
		 */
		struct intel_cdclk_state logical;
		/*
		 * The current actual cdclk state.
		 * See intel_atomic_state.cdclk.actual
		 */
		struct intel_cdclk_state actual;
		/* The current hardware cdclk state */
1706 1707
		struct intel_cdclk_state hw;
	} cdclk;
1708

1709 1710 1711 1712 1713 1714 1715
	/**
	 * wq - Driver workqueue for GEM.
	 *
	 * NOTE: Work items scheduled here are not allowed to grab any modeset
	 * locks, for otherwise the flushing done in the pageflip code will
	 * result in deadlocks.
	 */
1716 1717
	struct workqueue_struct *wq;

1718 1719 1720
	/* ordered wq for modesets */
	struct workqueue_struct *modeset_wq;

1721 1722 1723 1724 1725
	/* Display functions */
	struct drm_i915_display_funcs display;

	/* PCH chipset type */
	enum intel_pch pch_type;
1726
	unsigned short pch_id;
1727 1728 1729

	unsigned long quirks;

1730 1731
	enum modeset_restore modeset_restore;
	struct mutex modeset_restore_lock;
1732
	struct drm_atomic_state *modeset_restore_state;
1733
	struct drm_modeset_acquire_ctx reset_ctx;
1734

1735
	struct list_head vm_list; /* Global list of all address spaces */
1736
	struct i915_ggtt ggtt; /* VM representing the global address space */
B
Ben Widawsky 已提交
1737

1738
	struct i915_gem_mm mm;
1739 1740
	DECLARE_HASHTABLE(mm_structs, 7);
	struct mutex mm_lock;
1741

1742 1743
	struct intel_ppat ppat;

1744 1745
	/* Kernel Modesetting */

1746 1747
	struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
	struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1748

1749 1750 1751 1752
#ifdef CONFIG_DEBUG_FS
	struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
#endif

1753
	/* dpll and cdclk state is protected by connection_mutex */
D
Daniel Vetter 已提交
1754 1755
	int num_shared_dpll;
	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1756
	const struct intel_dpll_mgr *dpll_mgr;
1757

1758 1759 1760 1761 1762 1763 1764
	/*
	 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
	 * Must be global rather than per dpll, because on some platforms
	 * plls share registers.
	 */
	struct mutex dpll_lock;

1765
	unsigned int active_crtcs;
1766 1767
	/* minimum acceptable cdclk for each pipe */
	int min_cdclk[I915_MAX_PIPES];
1768 1769
	/* minimum acceptable voltage level for each pipe */
	u8 min_voltage_level[I915_MAX_PIPES];
1770

1771
	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1772

1773
	struct i915_workarounds workarounds;
1774

1775 1776
	struct i915_frontbuffer_tracking fb_tracking;

1777 1778 1779 1780 1781
	struct intel_atomic_helper {
		struct llist_head free_list;
		struct work_struct free_work;
	} atomic_helper;

1782
	u16 orig_clock;
1783

1784
	bool mchbar_need_disable;
1785

1786 1787
	struct intel_l3_parity l3_parity;

B
Ben Widawsky 已提交
1788
	/* Cannot be determined by PCIID. You must always read a register. */
1789
	u32 edram_cap;
B
Ben Widawsky 已提交
1790

1791 1792 1793 1794 1795 1796 1797 1798
	/*
	 * Protects RPS/RC6 register access and PCU communication.
	 * Must be taken after struct_mutex if nested. Note that
	 * this lock may be held for long periods of time when
	 * talking to hw - so only take it when talking to hw!
	 */
	struct mutex pcu_lock;

1799 1800
	/* gen6+ GT PM state */
	struct intel_gen6_power_mgmt gt_pm;
1801

1802 1803
	/* ilk-only ips/rps state. Everything in here is protected by the global
	 * mchdev_lock in intel_pm.c */
1804
	struct intel_ilk_power_mgmt ips;
1805

1806
	struct i915_power_domains power_domains;
1807

R
Rodrigo Vivi 已提交
1808
	struct i915_psr psr;
1809

1810
	struct i915_gpu_error gpu_error;
1811

1812 1813
	struct drm_i915_gem_object *vlv_pctx;

1814 1815
	/* list of fbdev register on this device */
	struct intel_fbdev *fbdev;
1816
	struct work_struct fbdev_suspend_work;
1817 1818

	struct drm_property *broadcast_rgb_property;
1819
	struct drm_property *force_audio_property;
1820

I
Imre Deak 已提交
1821
	/* hda/i915 audio component */
1822
	struct i915_audio_component *audio_component;
I
Imre Deak 已提交
1823
	bool audio_component_registered;
1824 1825 1826 1827 1828
	/**
	 * av_mutex - mutex for audio/video sync
	 *
	 */
	struct mutex av_mutex;
I
Imre Deak 已提交
1829

1830 1831
	struct {
		struct list_head list;
1832 1833
		struct llist_head free_list;
		struct work_struct free_work;
1834 1835 1836 1837 1838 1839 1840

		/* The hw wants to have a stable context identifier for the
		 * lifetime of the context (for OA, PASID, faults, etc).
		 * This is limited in execlists to 21 bits.
		 */
		struct ida hw_ida;
#define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1841
#define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
1842
	} contexts;
1843

1844
	u32 fdi_rx_config;
1845

1846
	/* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1847
	u32 chv_phy_control;
1848 1849 1850 1851 1852 1853
	/*
	 * Shadows for CHV DPLL_MD regs to keep the state
	 * checker somewhat working in the presence hardware
	 * crappiness (can't read out DPLL_MD for pipes B & C).
	 */
	u32 chv_dpll_md[I915_MAX_PIPES];
1854
	u32 bxt_phy_grc;
1855

1856
	u32 suspend_count;
1857
	bool power_domains_suspended;
1858
	struct i915_suspend_saved_registers regfile;
1859
	struct vlv_s0ix_state vlv_s0ix_state;
1860

1861
	enum {
1862 1863 1864 1865 1866
		I915_SAGV_UNKNOWN = 0,
		I915_SAGV_DISABLED,
		I915_SAGV_ENABLED,
		I915_SAGV_NOT_CONTROLLED
	} sagv_status;
1867

1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879
	struct {
		/*
		 * Raw watermark latency values:
		 * in 0.1us units for WM0,
		 * in 0.5us units for WM1+.
		 */
		/* primary */
		uint16_t pri_latency[5];
		/* sprite */
		uint16_t spr_latency[5];
		/* cursor */
		uint16_t cur_latency[5];
1880 1881 1882 1883 1884 1885
		/*
		 * Raw watermark memory latency values
		 * for SKL for all 8 levels
		 * in 1us units.
		 */
		uint16_t skl_latency[8];
1886 1887

		/* current hardware state */
1888 1889
		union {
			struct ilk_wm_values hw;
1890
			struct skl_ddb_values skl_hw;
1891
			struct vlv_wm_values vlv;
1892
			struct g4x_wm_values g4x;
1893
		};
1894 1895

		uint8_t max_level;
1896 1897 1898 1899 1900 1901 1902

		/*
		 * Should be held around atomic WM register writing; also
		 * protects * intel_crtc->wm.active and
		 * cstate->wm.need_postvbl_update.
		 */
		struct mutex wm_mutex;
1903 1904 1905 1906 1907 1908 1909

		/*
		 * Set during HW readout of watermarks/DDB.  Some platforms
		 * need to know when we're still using BIOS-provided values
		 * (which we don't fully trust).
		 */
		bool distrust_bios_wm;
1910 1911
	} wm;

1912
	struct i915_runtime_pm runtime_pm;
1913

1914 1915
	struct {
		bool initialized;
1916

1917
		struct kobject *metrics_kobj;
1918
		struct ctl_table_header *sysctl_header;
1919

1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935
		/*
		 * Lock associated with adding/modifying/removing OA configs
		 * in dev_priv->perf.metrics_idr.
		 */
		struct mutex metrics_lock;

		/*
		 * List of dynamic configurations, you need to hold
		 * dev_priv->perf.metrics_lock to access it.
		 */
		struct idr metrics_idr;

		/*
		 * Lock associated with anything below within this structure
		 * except exclusive_stream.
		 */
1936 1937
		struct mutex lock;
		struct list_head streams;
1938 1939

		struct {
1940 1941 1942 1943 1944 1945
			/*
			 * The stream currently using the OA unit. If accessed
			 * outside a syscall associated to its file
			 * descriptor, you need to hold
			 * dev_priv->drm.struct_mutex.
			 */
1946 1947 1948 1949 1950 1951 1952 1953
			struct i915_perf_stream *exclusive_stream;

			u32 specific_ctx_id;

			struct hrtimer poll_check_timer;
			wait_queue_head_t poll_wq;
			bool pollin;

1954 1955 1956 1957 1958 1959
			/**
			 * For rate limiting any notifications of spurious
			 * invalid OA reports
			 */
			struct ratelimit_state spurious_report_rs;

1960 1961 1962
			bool periodic;
			int period_exponent;

1963
			struct i915_oa_config test_config;
1964 1965 1966 1967

			struct {
				struct i915_vma *vma;
				u8 *vaddr;
1968
				u32 last_ctx_id;
1969 1970
				int format;
				int format_size;
1971

1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024
				/**
				 * Locks reads and writes to all head/tail state
				 *
				 * Consider: the head and tail pointer state
				 * needs to be read consistently from a hrtimer
				 * callback (atomic context) and read() fop
				 * (user context) with tail pointer updates
				 * happening in atomic context and head updates
				 * in user context and the (unlikely)
				 * possibility of read() errors needing to
				 * reset all head/tail state.
				 *
				 * Note: Contention or performance aren't
				 * currently a significant concern here
				 * considering the relatively low frequency of
				 * hrtimer callbacks (5ms period) and that
				 * reads typically only happen in response to a
				 * hrtimer event and likely complete before the
				 * next callback.
				 *
				 * Note: This lock is not held *while* reading
				 * and copying data to userspace so the value
				 * of head observed in htrimer callbacks won't
				 * represent any partial consumption of data.
				 */
				spinlock_t ptr_lock;

				/**
				 * One 'aging' tail pointer and one 'aged'
				 * tail pointer ready to used for reading.
				 *
				 * Initial values of 0xffffffff are invalid
				 * and imply that an update is required
				 * (and should be ignored by an attempted
				 * read)
				 */
				struct {
					u32 offset;
				} tails[2];

				/**
				 * Index for the aged tail ready to read()
				 * data up to.
				 */
				unsigned int aged_tail_idx;

				/**
				 * A monotonic timestamp for when the current
				 * aging tail pointer was read; used to
				 * determine when it is old enough to trust.
				 */
				u64 aging_timestamp;

2025 2026 2027 2028 2029 2030 2031 2032 2033 2034
				/**
				 * Although we can always read back the head
				 * pointer register, we prefer to avoid
				 * trusting the HW state, just to avoid any
				 * risk that some hardware condition could
				 * somehow bump the head pointer unpredictably
				 * and cause us to forward the wrong OA buffer
				 * data to userspace.
				 */
				u32 head;
2035 2036 2037
			} oa_buffer;

			u32 gen7_latched_oastatus1;
2038 2039 2040 2041 2042 2043 2044 2045 2046
			u32 ctx_oactxctrl_offset;
			u32 ctx_flexeu0_offset;

			/**
			 * The RPT_ID/reason field for Gen8+ includes a bit
			 * to determine if the CTX ID in the report is valid
			 * but the specific bit differs between Gen 8 and 9
			 */
			u32 gen8_valid_ctx_bit;
2047 2048 2049

			struct i915_oa_ops ops;
			const struct i915_oa_format *oa_formats;
2050
		} oa;
2051 2052
	} perf;

2053 2054
	/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
	struct {
2055
		void (*resume)(struct drm_i915_private *);
2056
		void (*cleanup_engine)(struct intel_engine_cs *engine);
2057

2058 2059
		struct list_head timelines;
		struct i915_gem_timeline global_timeline;
2060
		u32 active_requests;
2061

2062 2063 2064 2065 2066 2067 2068 2069 2070
		/**
		 * Is the GPU currently considered idle, or busy executing
		 * userspace requests? Whilst idle, we allow runtime power
		 * management to power down the hardware and display clocks.
		 * In order to reduce the effect on performance, there
		 * is a slight delay before we do so.
		 */
		bool awake;

2071 2072 2073 2074 2075 2076
		/**
		 * The number of times we have woken up.
		 */
		unsigned int epoch;
#define I915_EPOCH_INVALID 0

2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093
		/**
		 * We leave the user IRQ off as much as possible,
		 * but this means that requests will finish and never
		 * be retired once the system goes idle. Set a timer to
		 * fire periodically while the ring is running. When it
		 * fires, go retire requests.
		 */
		struct delayed_work retire_work;

		/**
		 * When we detect an idle GPU, we want to turn on
		 * powersaving features. So once we see that there
		 * are no more requests outstanding and no more
		 * arrive within a small period of time, we fire
		 * off the idle_work.
		 */
		struct delayed_work idle_work;
2094 2095

		ktime_t last_init_time;
2096 2097
	} gt;

2098 2099 2100
	/* perform PHY state sanity checks? */
	bool chv_phy_assert[2];

M
Mahesh Kumar 已提交
2101 2102
	bool ipc_enabled;

2103 2104
	/* Used to save the pipe-to-encoder mapping for audio */
	struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2105

2106 2107 2108 2109 2110 2111
	/* necessary resource sharing with HDMI LPE audio driver. */
	struct {
		struct platform_device *platdev;
		int	irq;
	} lpe_audio;

2112 2113
	struct i915_pmu pmu;

2114 2115 2116 2117
	/*
	 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
	 * will be rejected. Instead look for a better place.
	 */
2118
};
L
Linus Torvalds 已提交
2119

2120 2121
static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
{
2122
	return container_of(dev, struct drm_i915_private, drm);
2123 2124
}

2125
static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
I
Imre Deak 已提交
2126
{
2127
	return to_i915(dev_get_drvdata(kdev));
I
Imre Deak 已提交
2128 2129
}

2130 2131 2132 2133 2134
static inline struct drm_i915_private *wopcm_to_i915(struct intel_wopcm *wopcm)
{
	return container_of(wopcm, struct drm_i915_private, wopcm);
}

2135 2136 2137 2138 2139
static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
{
	return container_of(guc, struct drm_i915_private, guc);
}

A
Arkadiusz Hiler 已提交
2140 2141 2142 2143 2144
static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
{
	return container_of(huc, struct drm_i915_private, huc);
}

2145
/* Simple iterator over all initialised engines */
2146 2147 2148 2149 2150
#define for_each_engine(engine__, dev_priv__, id__) \
	for ((id__) = 0; \
	     (id__) < I915_NUM_ENGINES; \
	     (id__)++) \
		for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2151 2152

/* Iterator over subset of engines selected by mask */
2153
#define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2154 2155 2156 2157
	for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->ring_mask; \
	     (tmp__) ? \
	     ((engine__) = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : \
	     0;)
2158

2159 2160 2161 2162 2163 2164 2165
enum hdmi_force_audio {
	HDMI_AUDIO_OFF_DVI = -2,	/* no aux data for HDMI-DVI converter */
	HDMI_AUDIO_OFF,			/* force turn off HDMI audio */
	HDMI_AUDIO_AUTO,		/* trust EDID */
	HDMI_AUDIO_ON,			/* force turn on HDMI audio */
};

2166
#define I915_GTT_OFFSET_NONE ((u32)-1)
2167

2168 2169
/*
 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2170
 * considered to be the frontbuffer for the given plane interface-wise. This
2171 2172 2173 2174 2175
 * doesn't mean that the hw necessarily already scans it out, but that any
 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
 *
 * We have one bit per pipe and per scanout plane type.
 */
2176
#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2177 2178 2179 2180 2181
#define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
	BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
	BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
	BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
})
2182
#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2183
	BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2184
#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2185 2186
	GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
		INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2187

2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213
/*
 * Optimised SGL iterator for GEM objects
 */
static __always_inline struct sgt_iter {
	struct scatterlist *sgp;
	union {
		unsigned long pfn;
		dma_addr_t dma;
	};
	unsigned int curr;
	unsigned int max;
} __sgt_iter(struct scatterlist *sgl, bool dma) {
	struct sgt_iter s = { .sgp = sgl };

	if (s.sgp) {
		s.max = s.curr = s.sgp->offset;
		s.max += s.sgp->length;
		if (dma)
			s.dma = sg_dma_address(s.sgp);
		else
			s.pfn = page_to_pfn(sg_page(s.sgp));
	}

	return s;
}

2214 2215 2216 2217 2218 2219 2220 2221
static inline struct scatterlist *____sg_next(struct scatterlist *sg)
{
	++sg;
	if (unlikely(sg_is_chain(sg)))
		sg = sg_chain_ptr(sg);
	return sg;
}

2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235
/**
 * __sg_next - return the next scatterlist entry in a list
 * @sg:		The current sg entry
 *
 * Description:
 *   If the entry is the last, return NULL; otherwise, step to the next
 *   element in the array (@sg@+1). If that's a chain pointer, follow it;
 *   otherwise just return the pointer to the current element.
 **/
static inline struct scatterlist *__sg_next(struct scatterlist *sg)
{
#ifdef CONFIG_DEBUG_SG
	BUG_ON(sg->sg_magic != SG_MAGIC);
#endif
2236
	return sg_is_last(sg) ? NULL : ____sg_next(sg);
2237 2238
}

2239 2240 2241 2242 2243 2244 2245 2246 2247
/**
 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
 * @__dmap:	DMA address (output)
 * @__iter:	'struct sgt_iter' (iterator state, internal)
 * @__sgt:	sg_table to iterate over (input)
 */
#define for_each_sgt_dma(__dmap, __iter, __sgt)				\
	for ((__iter) = __sgt_iter((__sgt)->sgl, true);			\
	     ((__dmap) = (__iter).dma + (__iter).curr);			\
2248 2249
	     (((__iter).curr += PAGE_SIZE) >= (__iter).max) ?		\
	     (__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0)
2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260

/**
 * for_each_sgt_page - iterate over the pages of the given sg_table
 * @__pp:	page pointer (output)
 * @__iter:	'struct sgt_iter' (iterator state, internal)
 * @__sgt:	sg_table to iterate over (input)
 */
#define for_each_sgt_page(__pp, __iter, __sgt)				\
	for ((__iter) = __sgt_iter((__sgt)->sgl, false);		\
	     ((__pp) = (__iter).pfn == 0 ? NULL :			\
	      pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2261 2262
	     (((__iter).curr += PAGE_SIZE) >= (__iter).max) ?		\
	     (__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0 : 0)
2263

2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278
static inline unsigned int i915_sg_page_sizes(struct scatterlist *sg)
{
	unsigned int page_sizes;

	page_sizes = 0;
	while (sg) {
		GEM_BUG_ON(sg->offset);
		GEM_BUG_ON(!IS_ALIGNED(sg->length, PAGE_SIZE));
		page_sizes |= sg->length;
		sg = __sg_next(sg);
	}

	return page_sizes;
}

2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293
static inline unsigned int i915_sg_segment_size(void)
{
	unsigned int size = swiotlb_max_segment();

	if (size == 0)
		return SCATTERLIST_MAX_SEGMENT;

	size = rounddown(size, PAGE_SIZE);
	/* swiotlb_max_segment_size can return 1 byte when it means one page. */
	if (size < PAGE_SIZE)
		size = PAGE_SIZE;

	return size;
}

2294 2295 2296 2297 2298 2299 2300
static inline const struct intel_device_info *
intel_info(const struct drm_i915_private *dev_priv)
{
	return &dev_priv->info;
}

#define INTEL_INFO(dev_priv)	intel_info((dev_priv))
2301

2302
#define INTEL_GEN(dev_priv)	((dev_priv)->info.gen)
2303
#define INTEL_DEVID(dev_priv)	((dev_priv)->info.device_id)
2304

2305
#define REVID_FOREVER		0xff
2306
#define INTEL_REVID(dev_priv)	((dev_priv)->drm.pdev->revision)
2307 2308

#define GEN_FOREVER (0)
2309 2310 2311 2312 2313 2314 2315 2316

#define INTEL_GEN_MASK(s, e) ( \
	BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
	BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
	GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \
		(s) != GEN_FOREVER ? (s) - 1 : 0) \
)

2317 2318 2319 2320 2321
/*
 * Returns true if Gen is in inclusive range [Start, End].
 *
 * Use GEN_FOREVER for unbound start and or end.
 */
2322 2323
#define IS_GEN(dev_priv, s, e) \
	(!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
2324

2325 2326 2327 2328 2329 2330 2331 2332
/*
 * Return true if revision is in range [since,until] inclusive.
 *
 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
 */
#define IS_REVID(p, since, until) \
	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))

2333
#define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
T
Tvrtko Ursulin 已提交
2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346

#define IS_I830(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I830)
#define IS_I845G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I845G)
#define IS_I85X(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I85X)
#define IS_I865G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I865G)
#define IS_I915G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915G)
#define IS_I915GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915GM)
#define IS_I945G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I945G)
#define IS_I945GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I945GM)
#define IS_I965G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I965G)
#define IS_I965GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I965GM)
#define IS_G45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G45)
#define IS_GM45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GM45)
2347
#define IS_G4X(dev_priv)	(IS_G45(dev_priv) || IS_GM45(dev_priv))
2348 2349
#define IS_PINEVIEW_G(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa001)
#define IS_PINEVIEW_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa011)
T
Tvrtko Ursulin 已提交
2350 2351
#define IS_PINEVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
#define IS_G33(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G33)
2352
#define IS_IRONLAKE_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0046)
T
Tvrtko Ursulin 已提交
2353
#define IS_IVYBRIDGE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
2354 2355
#define IS_IVB_GT1(dev_priv)	(IS_IVYBRIDGE(dev_priv) && \
				 (dev_priv)->info.gt == 1)
T
Tvrtko Ursulin 已提交
2356 2357 2358 2359 2360 2361 2362 2363 2364 2365
#define IS_VALLEYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
#define IS_CHERRYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
#define IS_HASWELL(dev_priv)	IS_PLATFORM(dev_priv, INTEL_HASWELL)
#define IS_BROADWELL(dev_priv)	IS_PLATFORM(dev_priv, INTEL_BROADWELL)
#define IS_SKYLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
#define IS_BROXTON(dev_priv)	IS_PLATFORM(dev_priv, INTEL_BROXTON)
#define IS_KABYLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
#define IS_GEMINILAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
#define IS_COFFEELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
#define IS_CANNONLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
2366
#define IS_ICELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ICELAKE)
2367
#define IS_MOBILE(dev_priv)	((dev_priv)->info.is_mobile)
2368 2369 2370 2371 2372 2373
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv)	(IS_BROADWELL(dev_priv) && \
				 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 ||	\
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xb ||	\
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
V
Ville Syrjälä 已提交
2374
/* ULX machines are also considered ULT. */
2375 2376 2377
#define IS_BDW_ULX(dev_priv)	(IS_BROADWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
#define IS_BDW_GT3(dev_priv)	(IS_BROADWELL(dev_priv) && \
2378
				 (dev_priv)->info.gt == 3)
2379 2380 2381
#define IS_HSW_ULT(dev_priv)	(IS_HASWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
#define IS_HSW_GT3(dev_priv)	(IS_HASWELL(dev_priv) && \
2382
				 (dev_priv)->info.gt == 3)
2383
/* ULX machines are also considered ULT. */
2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401
#define IS_HSW_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0A0E || \
				 INTEL_DEVID(dev_priv) == 0x0A1E)
#define IS_SKL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x1906 || \
				 INTEL_DEVID(dev_priv) == 0x1913 || \
				 INTEL_DEVID(dev_priv) == 0x1916 || \
				 INTEL_DEVID(dev_priv) == 0x1921 || \
				 INTEL_DEVID(dev_priv) == 0x1926)
#define IS_SKL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x190E || \
				 INTEL_DEVID(dev_priv) == 0x1915 || \
				 INTEL_DEVID(dev_priv) == 0x191E)
#define IS_KBL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x5906 || \
				 INTEL_DEVID(dev_priv) == 0x5913 || \
				 INTEL_DEVID(dev_priv) == 0x5916 || \
				 INTEL_DEVID(dev_priv) == 0x5921 || \
				 INTEL_DEVID(dev_priv) == 0x5926)
#define IS_KBL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x590E || \
				 INTEL_DEVID(dev_priv) == 0x5915 || \
				 INTEL_DEVID(dev_priv) == 0x591E)
2402
#define IS_SKL_GT2(dev_priv)	(IS_SKYLAKE(dev_priv) && \
2403
				 (dev_priv)->info.gt == 2)
2404
#define IS_SKL_GT3(dev_priv)	(IS_SKYLAKE(dev_priv) && \
2405
				 (dev_priv)->info.gt == 3)
2406
#define IS_SKL_GT4(dev_priv)	(IS_SKYLAKE(dev_priv) && \
2407
				 (dev_priv)->info.gt == 4)
2408
#define IS_KBL_GT2(dev_priv)	(IS_KABYLAKE(dev_priv) && \
2409
				 (dev_priv)->info.gt == 2)
2410
#define IS_KBL_GT3(dev_priv)	(IS_KABYLAKE(dev_priv) && \
2411
				 (dev_priv)->info.gt == 3)
2412 2413
#define IS_CFL_ULT(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
2414 2415
#define IS_CFL_GT2(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
				 (dev_priv)->info.gt == 2)
2416 2417
#define IS_CFL_GT3(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
				 (dev_priv)->info.gt == 3)
2418 2419
#define IS_CNL_WITH_PORT_F(dev_priv)   (IS_CANNONLAKE(dev_priv) && \
					(INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
2420

2421
#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2422

2423 2424 2425 2426 2427 2428
#define SKL_REVID_A0		0x0
#define SKL_REVID_B0		0x1
#define SKL_REVID_C0		0x2
#define SKL_REVID_D0		0x3
#define SKL_REVID_E0		0x4
#define SKL_REVID_F0		0x5
2429 2430
#define SKL_REVID_G0		0x6
#define SKL_REVID_H0		0x7
2431

2432 2433
#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))

2434
#define BXT_REVID_A0		0x0
2435
#define BXT_REVID_A1		0x1
2436
#define BXT_REVID_B0		0x3
2437
#define BXT_REVID_B_LAST	0x8
2438
#define BXT_REVID_C0		0x9
N
Nick Hoath 已提交
2439

2440 2441
#define IS_BXT_REVID(dev_priv, since, until) \
	(IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2442

M
Mika Kuoppala 已提交
2443 2444
#define KBL_REVID_A0		0x0
#define KBL_REVID_B0		0x1
2445 2446 2447
#define KBL_REVID_C0		0x2
#define KBL_REVID_D0		0x3
#define KBL_REVID_E0		0x4
M
Mika Kuoppala 已提交
2448

2449 2450
#define IS_KBL_REVID(dev_priv, since, until) \
	(IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
M
Mika Kuoppala 已提交
2451

2452 2453 2454 2455 2456 2457
#define GLK_REVID_A0		0x0
#define GLK_REVID_A1		0x1

#define IS_GLK_REVID(dev_priv, since, until) \
	(IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))

2458 2459
#define CNL_REVID_A0		0x0
#define CNL_REVID_B0		0x1
R
Rodrigo Vivi 已提交
2460
#define CNL_REVID_C0		0x2
2461 2462 2463 2464

#define IS_CNL_REVID(p, since, until) \
	(IS_CANNONLAKE(p) && IS_REVID(p, since, until))

2465 2466 2467 2468 2469 2470
/*
 * The genX designation typically refers to the render engine, so render
 * capability related checks should use IS_GEN, while display and other checks
 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
 * chips, etc.).
 */
2471 2472 2473 2474 2475 2476 2477 2478
#define IS_GEN2(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(1)))
#define IS_GEN3(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(2)))
#define IS_GEN4(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(3)))
#define IS_GEN5(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(4)))
#define IS_GEN6(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(5)))
#define IS_GEN7(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(6)))
#define IS_GEN8(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(7)))
#define IS_GEN9(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(8)))
2479
#define IS_GEN10(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(9)))
2480
#define IS_GEN11(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(10)))
2481

2482
#define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
2483 2484
#define IS_GEN9_LP(dev_priv)	(IS_GEN9(dev_priv) && IS_LP(dev_priv))
#define IS_GEN9_BC(dev_priv)	(IS_GEN9(dev_priv) && !IS_LP(dev_priv))
2485

2486 2487 2488 2489 2490 2491
#define ENGINE_MASK(id)	BIT(id)
#define RENDER_RING	ENGINE_MASK(RCS)
#define BSD_RING	ENGINE_MASK(VCS)
#define BLT_RING	ENGINE_MASK(BCS)
#define VEBOX_RING	ENGINE_MASK(VECS)
#define BSD2_RING	ENGINE_MASK(VCS2)
2492 2493 2494
#define BSD3_RING	ENGINE_MASK(VCS3)
#define BSD4_RING	ENGINE_MASK(VCS4)
#define VEBOX2_RING	ENGINE_MASK(VECS2)
2495 2496 2497
#define ALL_ENGINES	(~0)

#define HAS_ENGINE(dev_priv, id) \
2498
	(!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2499 2500 2501 2502 2503 2504

#define HAS_BSD(dev_priv)	HAS_ENGINE(dev_priv, VCS)
#define HAS_BSD2(dev_priv)	HAS_ENGINE(dev_priv, VCS2)
#define HAS_BLT(dev_priv)	HAS_ENGINE(dev_priv, BCS)
#define HAS_VEBOX(dev_priv)	HAS_ENGINE(dev_priv, VECS)

2505 2506
#define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN7(dev_priv)

2507 2508 2509
#define HAS_LLC(dev_priv)	((dev_priv)->info.has_llc)
#define HAS_SNOOP(dev_priv)	((dev_priv)->info.has_snoop)
#define HAS_EDRAM(dev_priv)	(!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2510 2511
#define HAS_WT(dev_priv)	((IS_HASWELL(dev_priv) || \
				 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2512

2513
#define HWS_NEEDS_PHYSICAL(dev_priv)	((dev_priv)->info.hws_needs_physical)
2514

2515 2516
#define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
		((dev_priv)->info.has_logical_ring_contexts)
2517 2518
#define HAS_LOGICAL_RING_ELSQ(dev_priv) \
		((dev_priv)->info.has_logical_ring_elsq)
2519 2520
#define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
		((dev_priv)->info.has_logical_ring_preemption)
2521 2522 2523

#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)

2524 2525 2526
#define USES_PPGTT(dev_priv)		(i915_modparams.enable_ppgtt)
#define USES_FULL_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt >= 2)
#define USES_FULL_48BIT_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt == 3)
2527 2528 2529 2530
#define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
	GEM_BUG_ON((sizes) == 0); \
	((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
})
2531 2532 2533 2534

#define HAS_OVERLAY(dev_priv)		 ((dev_priv)->info.has_overlay)
#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
		((dev_priv)->info.overlay_needs_physical)
2535

2536
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
2537
#define HAS_BROKEN_CS_TLB(dev_priv)	(IS_I830(dev_priv) || IS_I845G(dev_priv))
2538

2539
/* WaRsDisableCoarsePowerGating:skl,cnl */
2540
#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2541 2542
	(IS_CANNONLAKE(dev_priv) || \
	 IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2543

2544 2545 2546 2547 2548
/*
 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
 * even when in MSI mode. This results in spurious interrupt warnings if the
 * legacy irq no. is shared with another device. The kernel then disables that
 * interrupt source and so prevents the other device from working properly.
2549 2550 2551
 *
 * Since we don't enable MSI anymore on gen4, we can always use GMBUS/AUX
 * interrupts.
2552
 */
2553 2554
#define HAS_AUX_IRQ(dev_priv)   true
#define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
2555

2556 2557 2558
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 * rows, which changed the alignment requirements and fence programming.
 */
2559 2560 2561
#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
					 !(IS_I915G(dev_priv) || \
					 IS_I915GM(dev_priv)))
2562 2563
#define SUPPORTS_TV(dev_priv)		((dev_priv)->info.supports_tv)
#define I915_HAS_HOTPLUG(dev_priv)	((dev_priv)->info.has_hotplug)
2564

2565 2566
#define HAS_FW_BLC(dev_priv) 	(INTEL_GEN(dev_priv) > 2)
#define HAS_FBC(dev_priv)	((dev_priv)->info.has_fbc)
2567
#define HAS_CUR_FBC(dev_priv)	(!HAS_GMCH_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 7)
2568

2569
#define HAS_IPS(dev_priv)	(IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2570

2571
#define HAS_DP_MST(dev_priv)	((dev_priv)->info.has_dp_mst)
2572

2573 2574 2575
#define HAS_DDI(dev_priv)		 ((dev_priv)->info.has_ddi)
#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
#define HAS_PSR(dev_priv)		 ((dev_priv)->info.has_psr)
2576

2577 2578
#define HAS_RC6(dev_priv)		 ((dev_priv)->info.has_rc6)
#define HAS_RC6p(dev_priv)		 ((dev_priv)->info.has_rc6p)
2579
#define HAS_RC6pp(dev_priv)		 (false) /* HW was never validated */
P
Paulo Zanoni 已提交
2580

2581
#define HAS_CSR(dev_priv)	((dev_priv)->info.has_csr)
2582

2583
#define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2584 2585
#define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)

2586 2587
#define HAS_IPC(dev_priv)		 ((dev_priv)->info.has_ipc)

2588 2589 2590 2591 2592
/*
 * For now, anything with a GuC requires uCode loading, and then supports
 * command submission once loaded. But these are logically independent
 * properties, so we have separate macros to test them.
 */
2593
#define HAS_GUC(dev_priv)	((dev_priv)->info.has_guc)
2594
#define HAS_GUC_CT(dev_priv)	((dev_priv)->info.has_guc_ct)
2595 2596
#define HAS_GUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
#define HAS_GUC_SCHED(dev_priv)	(HAS_GUC(dev_priv))
2597 2598 2599

/* For now, anything with a GuC has also HuC */
#define HAS_HUC(dev_priv)	(HAS_GUC(dev_priv))
2600
#define HAS_HUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
2601

2602
/* Having a GuC is not the same as using a GuC */
2603 2604 2605
#define USES_GUC(dev_priv)		intel_uc_is_using_guc()
#define USES_GUC_SUBMISSION(dev_priv)	intel_uc_is_using_guc_submission()
#define USES_HUC(dev_priv)		intel_uc_is_using_huc()
2606

2607
#define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2608

2609
#define HAS_POOLED_EU(dev_priv)	((dev_priv)->info.has_pooled_eu)
2610

2611
#define INTEL_PCH_DEVICE_ID_MASK		0xff80
2612 2613 2614 2615 2616
#define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
#define INTEL_PCH_PPT_DEVICE_ID_TYPE		0x1e00
#define INTEL_PCH_LPT_DEVICE_ID_TYPE		0x8c00
#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE		0x9c00
2617 2618
#define INTEL_PCH_WPT_DEVICE_ID_TYPE		0x8c80
#define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE		0x9c80
2619 2620
#define INTEL_PCH_SPT_DEVICE_ID_TYPE		0xA100
#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE		0x9D00
2621
#define INTEL_PCH_KBP_DEVICE_ID_TYPE		0xA280
2622
#define INTEL_PCH_CNP_DEVICE_ID_TYPE		0xA300
2623
#define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE		0x9D80
2624
#define INTEL_PCH_ICP_DEVICE_ID_TYPE		0x3480
2625
#define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
2626
#define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
2627
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
2628

2629
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2630
#define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
2631
#define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
2632
#define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
2633
#define HAS_PCH_CNP_LP(dev_priv) \
2634
	(INTEL_PCH_ID(dev_priv) == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE)
2635 2636 2637
#define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2638
#define HAS_PCH_LPT_LP(dev_priv) \
2639 2640
	(INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
	 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
2641
#define HAS_PCH_LPT_H(dev_priv) \
2642 2643
	(INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
	 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE)
2644 2645 2646 2647
#define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
#define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2648

2649
#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2650

2651
#define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
2652

2653
/* DPF == dynamic parity feature */
2654
#define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2655 2656
#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
				 2 : HAS_L3_DPF(dev_priv))
2657

2658
#define GT_FREQUENCY_MULTIPLIER 50
A
Akash Goel 已提交
2659
#define GEN9_FREQ_SCALER 3
2660

2661 2662
#include "i915_trace.h"

2663
static inline bool intel_vtd_active(void)
2664 2665
{
#ifdef CONFIG_INTEL_IOMMU
2666
	if (intel_iommu_gfx_mapped)
2667 2668 2669 2670 2671
		return true;
#endif
	return false;
}

2672 2673 2674 2675 2676
static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
{
	return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
}

2677 2678 2679
static inline bool
intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
{
2680
	return IS_BROXTON(dev_priv) && intel_vtd_active();
2681 2682
}

2683
int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2684
				int enable_ppgtt);
2685

2686
/* i915_drv.c */
2687 2688 2689 2690 2691 2692 2693
void __printf(3, 4)
__i915_printk(struct drm_i915_private *dev_priv, const char *level,
	      const char *fmt, ...);

#define i915_report_error(dev_priv, fmt, ...)				   \
	__i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)

2694
#ifdef CONFIG_COMPAT
D
Dave Airlie 已提交
2695 2696
extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
			      unsigned long arg);
2697 2698
#else
#define i915_compat_ioctl NULL
2699
#endif
2700 2701 2702 2703 2704
extern const struct dev_pm_ops i915_pm_ops;

extern int i915_driver_load(struct pci_dev *pdev,
			    const struct pci_device_id *ent);
extern void i915_driver_unload(struct drm_device *dev);
2705 2706
extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2707

2708 2709 2710 2711 2712
extern void i915_reset(struct drm_i915_private *i915,
		       unsigned int stalled_mask,
		       const char *reason);
extern int i915_reset_engine(struct intel_engine_cs *engine,
			     const char *reason);
2713

2714
extern bool intel_has_reset_engine(struct drm_i915_private *dev_priv);
2715
extern int intel_reset_guc(struct drm_i915_private *dev_priv);
2716 2717
extern int intel_guc_reset_engine(struct intel_guc *guc,
				  struct intel_engine_cs *engine);
2718
extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2719
extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
2720 2721 2722 2723
extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2724
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2725

2726
int intel_engines_init_mmio(struct drm_i915_private *dev_priv);
2727 2728
int intel_engines_init(struct drm_i915_private *dev_priv);

2729
/* intel_hotplug.c */
2730 2731
void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
			   u32 pin_mask, u32 long_mask);
2732 2733 2734
void intel_hpd_init(struct drm_i915_private *dev_priv);
void intel_hpd_init_work(struct drm_i915_private *dev_priv);
void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2735 2736 2737 2738
enum port intel_hpd_pin_to_port(struct drm_i915_private *dev_priv,
				enum hpd_pin pin);
enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
				   enum port port);
2739 2740
bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2741

L
Linus Torvalds 已提交
2742
/* i915_irq.c */
2743 2744 2745 2746
static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
{
	unsigned long delay;

2747
	if (unlikely(!i915_modparams.enable_hangcheck))
2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758 2759
		return;

	/* Don't continually defer the hangcheck so that it is always run at
	 * least once after work has been scheduled on any ring. Otherwise,
	 * we will ignore a hung ring if a second ring is kept busy.
	 */

	delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
	queue_delayed_work(system_long_wq,
			   &dev_priv->gpu_error.hangcheck_work, delay);
}

2760
__printf(4, 5)
2761 2762
void i915_handle_error(struct drm_i915_private *dev_priv,
		       u32 engine_mask,
2763
		       unsigned long flags,
2764
		       const char *fmt, ...);
2765
#define I915_ERROR_CAPTURE BIT(0)
L
Linus Torvalds 已提交
2766

2767
extern void intel_irq_init(struct drm_i915_private *dev_priv);
2768
extern void intel_irq_fini(struct drm_i915_private *dev_priv);
2769 2770
int intel_irq_install(struct drm_i915_private *dev_priv);
void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2771

2772 2773
static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
{
2774
	return dev_priv->gvt;
2775 2776
}

2777
static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2778
{
2779
	return dev_priv->vgpu.active;
2780
}
2781

2782 2783
u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
			      enum pipe pipe);
2784
void
2785
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2786
		     u32 status_mask);
2787 2788

void
2789
i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2790
		      u32 status_mask);
2791

2792 2793
void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2794 2795 2796
void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
				   uint32_t mask,
				   uint32_t bits);
2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809
void ilk_update_display_irq(struct drm_i915_private *dev_priv,
			    uint32_t interrupt_mask,
			    uint32_t enabled_irq_mask);
static inline void
ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, bits);
}
static inline void
ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, 0);
}
2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823
void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
			 enum pipe pipe,
			 uint32_t interrupt_mask,
			 uint32_t enabled_irq_mask);
static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
				       enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
}
static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
					enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
}
2824 2825 2826
void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
				  uint32_t interrupt_mask,
				  uint32_t enabled_irq_mask);
2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837
static inline void
ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, bits);
}
static inline void
ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, 0);
}

2838 2839 2840 2841 2842 2843 2844 2845 2846
/* i915_gem.c */
int i915_gem_create_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2847 2848
int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2849 2850 2851 2852
int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
			     struct drm_file *file_priv);
2853 2854 2855 2856
int i915_gem_execbuffer_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file_priv);
2857 2858
int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
B
Ben Widawsky 已提交
2859 2860 2861 2862
int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
2863 2864
int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *file_priv);
2865 2866
int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
2867 2868 2869 2870
int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
2871 2872
int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
2873 2874
int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file);
2875 2876
int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
2877 2878
int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2879
void i915_gem_sanitize(struct drm_i915_private *i915);
2880 2881
int i915_gem_init_early(struct drm_i915_private *dev_priv);
void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
2882
void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
2883
int i915_gem_freeze(struct drm_i915_private *dev_priv);
2884 2885
int i915_gem_freeze_late(struct drm_i915_private *dev_priv);

2886
void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
2887
void i915_gem_object_free(struct drm_i915_gem_object *obj);
2888 2889
void i915_gem_object_init(struct drm_i915_gem_object *obj,
			 const struct drm_i915_gem_object_ops *ops);
2890 2891 2892 2893 2894
struct drm_i915_gem_object *
i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
struct drm_i915_gem_object *
i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
				 const void *data, size_t size);
2895
void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
2896
void i915_gem_free_object(struct drm_gem_object *obj);
2897

2898 2899
static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
{
2900 2901 2902
	if (!atomic_read(&i915->mm.free_count))
		return;

2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913
	/* A single pass should suffice to release all the freed objects (along
	 * most call paths) , but be a little more paranoid in that freeing
	 * the objects does take a little amount of time, during which the rcu
	 * callbacks could have added new objects into the freed list, and
	 * armed the work again.
	 */
	do {
		rcu_barrier();
	} while (flush_work(&i915->mm.free_work));
}

2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931 2932 2933
static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
{
	/*
	 * Similar to objects above (see i915_gem_drain_freed-objects), in
	 * general we have workers that are armed by RCU and then rearm
	 * themselves in their callbacks. To be paranoid, we need to
	 * drain the workqueue a second time after waiting for the RCU
	 * grace period so that we catch work queued via RCU from the first
	 * pass. As neither drain_workqueue() nor flush_workqueue() report
	 * a result, we make an assumption that we only don't require more
	 * than 2 passes to catch all recursive RCU delayed work.
	 *
	 */
	int pass = 2;
	do {
		rcu_barrier();
		drain_workqueue(i915->wq);
	} while (--pass);
}

C
Chris Wilson 已提交
2934
struct i915_vma * __must_check
2935 2936
i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
			 const struct i915_ggtt_view *view,
2937
			 u64 size,
2938 2939
			 u64 alignment,
			 u64 flags);
2940

2941
int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
2942
void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2943

2944 2945
void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);

C
Chris Wilson 已提交
2946
static inline int __sg_page_count(const struct scatterlist *sg)
2947
{
2948 2949
	return sg->length >> PAGE_SHIFT;
}
2950

2951 2952 2953
struct scatterlist *
i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
		       unsigned int n, unsigned int *offset);
2954

2955 2956 2957
struct page *
i915_gem_object_get_page(struct drm_i915_gem_object *obj,
			 unsigned int n);
2958

2959 2960 2961
struct page *
i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
			       unsigned int n);
2962

2963 2964 2965
dma_addr_t
i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
				unsigned long n);
2966

2967
void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
2968
				 struct sg_table *pages,
M
Matthew Auld 已提交
2969
				 unsigned int sg_page_sizes);
C
Chris Wilson 已提交
2970 2971 2972 2973 2974
int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);

static inline int __must_check
i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
{
2975
	might_lock(&obj->mm.lock);
C
Chris Wilson 已提交
2976

2977
	if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
C
Chris Wilson 已提交
2978 2979 2980 2981 2982
		return 0;

	return __i915_gem_object_get_pages(obj);
}

2983 2984 2985 2986 2987 2988
static inline bool
i915_gem_object_has_pages(struct drm_i915_gem_object *obj)
{
	return !IS_ERR_OR_NULL(READ_ONCE(obj->mm.pages));
}

C
Chris Wilson 已提交
2989 2990
static inline void
__i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2991
{
2992
	GEM_BUG_ON(!i915_gem_object_has_pages(obj));
C
Chris Wilson 已提交
2993

2994
	atomic_inc(&obj->mm.pages_pin_count);
C
Chris Wilson 已提交
2995 2996 2997 2998 2999
}

static inline bool
i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
{
3000
	return atomic_read(&obj->mm.pages_pin_count);
C
Chris Wilson 已提交
3001 3002 3003 3004 3005
}

static inline void
__i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
{
3006
	GEM_BUG_ON(!i915_gem_object_has_pages(obj));
C
Chris Wilson 已提交
3007 3008
	GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));

3009
	atomic_dec(&obj->mm.pages_pin_count);
3010
}
3011

3012 3013
static inline void
i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3014
{
C
Chris Wilson 已提交
3015
	__i915_gem_object_unpin_pages(obj);
3016 3017
}

3018 3019 3020 3021 3022 3023 3024
enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
	I915_MM_NORMAL = 0,
	I915_MM_SHRINKER
};

void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
				 enum i915_mm_subclass subclass);
3025
void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
C
Chris Wilson 已提交
3026

3027 3028 3029
enum i915_map_type {
	I915_MAP_WB = 0,
	I915_MAP_WC,
3030 3031 3032
#define I915_MAP_OVERRIDE BIT(31)
	I915_MAP_FORCE_WB = I915_MAP_WB | I915_MAP_OVERRIDE,
	I915_MAP_FORCE_WC = I915_MAP_WC | I915_MAP_OVERRIDE,
3033 3034
};

3035 3036
/**
 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3037 3038
 * @obj: the object to map into kernel address space
 * @type: the type of mapping, used to select pgprot_t
3039 3040 3041
 *
 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
 * pages and then returns a contiguous mapping of the backing storage into
3042 3043
 * the kernel address space. Based on the @type of mapping, the PTE will be
 * set to either WriteBack or WriteCombine (via pgprot_t).
3044
 *
3045 3046
 * The caller is responsible for calling i915_gem_object_unpin_map() when the
 * mapping is no longer required.
3047
 *
3048 3049
 * Returns the pointer through which to access the mapped object, or an
 * ERR_PTR() on error.
3050
 */
3051 3052
void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
					   enum i915_map_type type);
3053 3054 3055

/**
 * i915_gem_object_unpin_map - releases an earlier mapping
3056
 * @obj: the object to unmap
3057 3058 3059 3060 3061 3062 3063 3064 3065 3066 3067
 *
 * After pinning the object and mapping its pages, once you are finished
 * with your access, call i915_gem_object_unpin_map() to release the pin
 * upon the mapping. Once the pin count reaches zero, that mapping may be
 * removed.
 */
static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
{
	i915_gem_object_unpin_pages(obj);
}

3068 3069 3070 3071
int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
				    unsigned int *needs_clflush);
int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
				     unsigned int *needs_clflush);
3072 3073 3074
#define CLFLUSH_BEFORE	BIT(0)
#define CLFLUSH_AFTER	BIT(1)
#define CLFLUSH_FLAGS	(CLFLUSH_BEFORE | CLFLUSH_AFTER)
3075 3076 3077 3078 3079 3080 3081

static inline void
i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
{
	i915_gem_object_unpin_pages(obj);
}

3082
int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
B
Ben Widawsky 已提交
3083
void i915_vma_move_to_active(struct i915_vma *vma,
3084
			     struct i915_request *rq,
3085
			     unsigned int flags);
3086 3087 3088
int i915_gem_dumb_create(struct drm_file *file_priv,
			 struct drm_device *dev,
			 struct drm_mode_create_dumb *args);
3089 3090
int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
		      uint32_t handle, uint64_t *offset);
3091
int i915_gem_mmap_gtt_version(void);
3092 3093 3094 3095 3096

void i915_gem_track_fb(struct drm_i915_gem_object *old,
		       struct drm_i915_gem_object *new,
		       unsigned frontbuffer_bits);

3097
int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3098

3099
struct i915_request *
3100
i915_gem_find_active_request(struct intel_engine_cs *engine);
3101

3102 3103 3104 3105 3106 3107
static inline bool i915_reset_backoff(struct i915_gpu_error *error)
{
	return unlikely(test_bit(I915_RESET_BACKOFF, &error->flags));
}

static inline bool i915_reset_handoff(struct i915_gpu_error *error)
3108
{
3109
	return unlikely(test_bit(I915_RESET_HANDOFF, &error->flags));
3110 3111
}

3112
static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3113
{
3114
	return unlikely(test_bit(I915_WEDGED, &error->flags));
3115 3116
}

3117
static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error *error)
3118
{
3119
	return i915_reset_backoff(error) | i915_terminally_wedged(error);
M
Mika Kuoppala 已提交
3120 3121 3122 3123
}

static inline u32 i915_reset_count(struct i915_gpu_error *error)
{
3124
	return READ_ONCE(error->reset_count);
3125
}
3126

3127 3128 3129 3130 3131 3132
static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
					  struct intel_engine_cs *engine)
{
	return READ_ONCE(error->reset_engine_count[engine->id]);
}

3133
struct i915_request *
3134
i915_gem_reset_prepare_engine(struct intel_engine_cs *engine);
3135
int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
3136 3137
void i915_gem_reset(struct drm_i915_private *dev_priv,
		    unsigned int stalled_mask);
3138
void i915_gem_reset_finish_engine(struct intel_engine_cs *engine);
3139
void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
3140
void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3141
bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
3142
void i915_gem_reset_engine(struct intel_engine_cs *engine,
3143 3144
			   struct i915_request *request,
			   bool stalled);
3145

3146
void i915_gem_init_mmio(struct drm_i915_private *i915);
3147 3148
int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3149
void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3150
void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3151 3152
int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
			   unsigned int flags);
3153 3154
int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
void i915_gem_resume(struct drm_i915_private *dev_priv);
3155
int i915_gem_fault(struct vm_fault *vmf);
3156 3157 3158 3159
int i915_gem_object_wait(struct drm_i915_gem_object *obj,
			 unsigned int flags,
			 long timeout,
			 struct intel_rps_client *rps);
3160 3161 3162 3163 3164
int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
				  unsigned int flags,
				  int priority);
#define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX

3165
int __must_check
3166 3167 3168
i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write);
int __must_check
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write);
3169
int __must_check
3170
i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
C
Chris Wilson 已提交
3171
struct i915_vma * __must_check
3172 3173
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
				     u32 alignment,
3174 3175
				     const struct i915_ggtt_view *view,
				     unsigned int flags);
C
Chris Wilson 已提交
3176
void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3177
int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3178
				int align);
3179
int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
3180
void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3181

3182 3183 3184
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
				    enum i915_cache_level cache_level);

3185 3186 3187 3188 3189 3190
struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
				struct dma_buf *dma_buf);

struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
				struct drm_gem_object *gem_obj, int flags);

3191 3192 3193 3194 3195 3196
static inline struct i915_hw_ppgtt *
i915_vm_to_ppgtt(struct i915_address_space *vm)
{
	return container_of(vm, struct i915_hw_ppgtt, base);
}

J
Joonas Lahtinen 已提交
3197
/* i915_gem_fence_reg.c */
3198 3199 3200
struct drm_i915_fence_reg *
i915_reserve_fence(struct drm_i915_private *dev_priv);
void i915_unreserve_fence(struct drm_i915_fence_reg *fence);
3201

3202
void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
3203
void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3204

3205
void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3206 3207 3208 3209
void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
				       struct sg_table *pages);
void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
					 struct sg_table *pages);
3210

3211 3212 3213 3214 3215 3216
static inline struct i915_gem_context *
__i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
{
	return idr_find(&file_priv->context_idr, id);
}

3217 3218 3219 3220 3221
static inline struct i915_gem_context *
i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
{
	struct i915_gem_context *ctx;

3222 3223 3224 3225 3226
	rcu_read_lock();
	ctx = __i915_gem_context_lookup_rcu(file_priv, id);
	if (ctx && !kref_get_unless_zero(&ctx->ref))
		ctx = NULL;
	rcu_read_unlock();
3227 3228 3229 3230

	return ctx;
}

C
Chris Wilson 已提交
3231 3232 3233 3234 3235 3236 3237 3238 3239 3240
static inline struct intel_timeline *
i915_gem_context_lookup_timeline(struct i915_gem_context *ctx,
				 struct intel_engine_cs *engine)
{
	struct i915_address_space *vm;

	vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base;
	return &vm->timeline.engine[engine->id];
}

3241 3242
int i915_perf_open_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file);
3243 3244 3245 3246
int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
				  struct drm_file *file);
3247 3248 3249
void i915_oa_init_reg_state(struct intel_engine_cs *engine,
			    struct i915_gem_context *ctx,
			    uint32_t *reg_state);
3250

3251
/* i915_gem_evict.c */
3252
int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3253
					  u64 min_size, u64 alignment,
3254
					  unsigned cache_level,
3255
					  u64 start, u64 end,
3256
					  unsigned flags);
3257 3258 3259
int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
					 struct drm_mm_node *node,
					 unsigned int flags);
3260
int i915_gem_evict_vm(struct i915_address_space *vm);
3261

3262 3263
void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv);

3264
/* belongs in i915_gem_gtt.h */
3265
static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3266
{
3267
	wmb();
3268
	if (INTEL_GEN(dev_priv) < 6)
3269 3270
		intel_gtt_chipset_flush();
}
3271

3272
/* i915_gem_stolen.c */
3273 3274 3275
int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
				struct drm_mm_node *node, u64 size,
				unsigned alignment);
3276 3277 3278 3279
int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
					 struct drm_mm_node *node, u64 size,
					 unsigned alignment, u64 start,
					 u64 end);
3280 3281
void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
				 struct drm_mm_node *node);
3282
int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3283
void i915_gem_cleanup_stolen(struct drm_device *dev);
3284
struct drm_i915_gem_object *
3285 3286
i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
			      resource_size_t size);
3287
struct drm_i915_gem_object *
3288
i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3289 3290 3291
					       resource_size_t stolen_offset,
					       resource_size_t gtt_offset,
					       resource_size_t size);
3292

3293 3294 3295
/* i915_gem_internal.c */
struct drm_i915_gem_object *
i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3296
				phys_addr_t size);
3297

3298
/* i915_gem_shrinker.c */
3299
unsigned long i915_gem_shrink(struct drm_i915_private *i915,
3300
			      unsigned long target,
3301
			      unsigned long *nr_scanned,
3302 3303 3304 3305
			      unsigned flags);
#define I915_SHRINK_PURGEABLE 0x1
#define I915_SHRINK_UNBOUND 0x2
#define I915_SHRINK_BOUND 0x4
3306
#define I915_SHRINK_ACTIVE 0x8
3307
#define I915_SHRINK_VMAPS 0x10
3308 3309 3310
unsigned long i915_gem_shrink_all(struct drm_i915_private *i915);
void i915_gem_shrinker_register(struct drm_i915_private *i915);
void i915_gem_shrinker_unregister(struct drm_i915_private *i915);
3311 3312


3313
/* i915_gem_tiling.c */
3314
static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3315
{
3316
	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3317 3318

	return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3319
		i915_gem_object_is_tiled(obj);
3320 3321
}

3322 3323 3324 3325 3326
u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
			unsigned int tiling, unsigned int stride);
u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
			     unsigned int tiling, unsigned int stride);

3327
/* i915_debugfs.c */
3328
#ifdef CONFIG_DEBUG_FS
3329
int i915_debugfs_register(struct drm_i915_private *dev_priv);
J
Jani Nikula 已提交
3330
int i915_debugfs_connector_add(struct drm_connector *connector);
3331
void intel_display_crc_init(struct drm_i915_private *dev_priv);
3332
#else
3333
static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3334 3335
static inline int i915_debugfs_connector_add(struct drm_connector *connector)
{ return 0; }
3336
static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3337
#endif
3338

3339
const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3340

3341
/* i915_cmd_parser.c */
3342
int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3343
void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3344 3345 3346 3347 3348 3349 3350
void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
int intel_engine_cmd_parser(struct intel_engine_cs *engine,
			    struct drm_i915_gem_object *batch_obj,
			    struct drm_i915_gem_object *shadow_batch_obj,
			    u32 batch_start_offset,
			    u32 batch_len,
			    bool is_master);
3351

3352 3353 3354
/* i915_perf.c */
extern void i915_perf_init(struct drm_i915_private *dev_priv);
extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3355 3356
extern void i915_perf_register(struct drm_i915_private *dev_priv);
extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3357

3358
/* i915_suspend.c */
3359 3360
extern int i915_save_state(struct drm_i915_private *dev_priv);
extern int i915_restore_state(struct drm_i915_private *dev_priv);
3361

B
Ben Widawsky 已提交
3362
/* i915_sysfs.c */
D
David Weinehall 已提交
3363 3364
void i915_setup_sysfs(struct drm_i915_private *dev_priv);
void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
B
Ben Widawsky 已提交
3365

3366 3367 3368 3369
/* intel_lpe_audio.c */
int  intel_lpe_audio_init(struct drm_i915_private *dev_priv);
void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv);
void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv);
3370
void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
3371 3372
			    enum pipe pipe, enum port port,
			    const void *eld, int ls_clock, bool dp_output);
3373

3374
/* intel_i2c.c */
3375 3376
extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3377 3378
extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
				     unsigned int pin);
3379
extern int intel_gmbus_output_aksv(struct i2c_adapter *adapter);
3380

3381 3382
extern struct i2c_adapter *
intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
C
Chris Wilson 已提交
3383 3384
extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3385
static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3386 3387 3388
{
	return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
}
3389
extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3390

3391
/* intel_bios.c */
3392
void intel_bios_init(struct drm_i915_private *dev_priv);
3393
void intel_bios_cleanup(struct drm_i915_private *dev_priv);
J
Jani Nikula 已提交
3394
bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3395
bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3396
bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3397
bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3398
bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3399
bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3400
bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3401 3402
bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
				     enum port port);
3403 3404 3405
bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
				enum port port);

J
Jesse Barnes 已提交
3406 3407 3408 3409 3410 3411 3412 3413 3414
/* intel_acpi.c */
#ifdef CONFIG_ACPI
extern void intel_register_dsm_handler(void);
extern void intel_unregister_dsm_handler(void);
#else
static inline void intel_register_dsm_handler(void) { return; }
static inline void intel_unregister_dsm_handler(void) { return; }
#endif /* CONFIG_ACPI */

3415 3416 3417 3418 3419 3420 3421
/* intel_device_info.c */
static inline struct intel_device_info *
mkwrite_device_info(struct drm_i915_private *dev_priv)
{
	return (struct intel_device_info *)&dev_priv->info;
}

J
Jesse Barnes 已提交
3422
/* modesetting */
3423
extern void intel_modeset_init_hw(struct drm_device *dev);
3424
extern int intel_modeset_init(struct drm_device *dev);
J
Jesse Barnes 已提交
3425
extern void intel_modeset_cleanup(struct drm_device *dev);
3426
extern int intel_connector_register(struct drm_connector *);
3427
extern void intel_connector_unregister(struct drm_connector *);
3428 3429
extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
				       bool state);
3430
extern void intel_display_resume(struct drm_device *dev);
3431 3432
extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3433
extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3434
extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3435
extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3436
extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3437
				  bool enable);
3438

B
Ben Widawsky 已提交
3439 3440
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file);
3441

3442
/* overlay */
3443 3444
extern struct intel_overlay_error_state *
intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3445 3446
extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
					    struct intel_overlay_error_state *error);
3447

3448 3449
extern struct intel_display_error_state *
intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3450
extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3451
					    struct intel_display_error_state *error);
3452

3453
int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3454
int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv, u32 mbox,
3455 3456
				    u32 val, int fast_timeout_us,
				    int slow_timeout_ms);
3457
#define sandybridge_pcode_write(dev_priv, mbox, val)	\
3458
	sandybridge_pcode_write_timeout(dev_priv, mbox, val, 500, 0)
3459

3460 3461
int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
		      u32 reply_mask, u32 reply, int timeout_base_ms);
3462 3463

/* intel_sideband.c */
3464
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3465
int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3466
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3467 3468
u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3469 3470 3471 3472
u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3473 3474
u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3475 3476
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3477 3478 3479 3480
u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
		   enum intel_sbi_destination destination);
void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
		     enum intel_sbi_destination destination);
3481 3482
u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3483

3484
/* intel_dpio_phy.c */
3485
void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3486
			     enum dpio_phy *phy, enum dpio_channel *ch);
3487 3488 3489
void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
				  enum port port, u32 margin, u32 scale,
				  u32 enable, u32 deemphasis);
3490 3491 3492 3493 3494 3495
void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
			    enum dpio_phy phy);
bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
			      enum dpio_phy phy);
3496
uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(uint8_t lane_count);
3497 3498 3499 3500
void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
				     uint8_t lane_lat_optim_mask);
uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);

3501 3502 3503
void chv_set_phy_signal_level(struct intel_encoder *encoder,
			      u32 deemph_reg_value, u32 margin_reg_value,
			      bool uniq_trans_scale);
3504
void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3505
			      const struct intel_crtc_state *crtc_state,
3506
			      bool reset);
3507 3508 3509 3510
void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
			    const struct intel_crtc_state *crtc_state);
void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
				const struct intel_crtc_state *crtc_state);
3511
void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3512 3513
void chv_phy_post_pll_disable(struct intel_encoder *encoder,
			      const struct intel_crtc_state *old_crtc_state);
3514

3515 3516 3517
void vlv_set_phy_signal_level(struct intel_encoder *encoder,
			      u32 demph_reg_value, u32 preemph_reg_value,
			      u32 uniqtranscale_reg_value, u32 tx3_demph);
3518 3519 3520 3521 3522 3523
void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
			    const struct intel_crtc_state *crtc_state);
void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
				const struct intel_crtc_state *crtc_state);
void vlv_phy_reset_lanes(struct intel_encoder *encoder,
			 const struct intel_crtc_state *old_crtc_state);
3524

3525 3526
int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3527
u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
3528
			   const i915_reg_t reg);
3529

T
Tvrtko Ursulin 已提交
3530 3531
u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1);

3532 3533 3534 3535 3536 3537
static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
					 const i915_reg_t reg)
{
	return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(dev_priv, reg), 1000);
}

3538 3539 3540 3541 3542 3543 3544 3545 3546 3547 3548 3549 3550
#define I915_READ8(reg)		dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
#define I915_WRITE8(reg, val)	dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)

#define I915_READ16(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
#define I915_WRITE16(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
#define I915_READ16_NOTRACE(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
#define I915_WRITE16_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)

#define I915_READ(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
#define I915_WRITE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
#define I915_READ_NOTRACE(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
#define I915_WRITE_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)

3551 3552 3553 3554
/* Be very careful with read/write 64-bit values. On 32-bit machines, they
 * will be implemented using 2 32-bit writes in an arbitrary order with
 * an arbitrary delay between them. This can cause the hardware to
 * act upon the intermediate value, possibly leading to corruption and
3555 3556 3557 3558 3559 3560 3561 3562 3563
 * machine death. For this reason we do not support I915_WRITE64, or
 * dev_priv->uncore.funcs.mmio_writeq.
 *
 * When reading a 64-bit value as two 32-bit values, the delay may cause
 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
 * occasionally a 64-bit register does not actualy support a full readq
 * and must be read using two 32-bit reads.
 *
 * You have been warned.
3564
 */
3565
#define I915_READ64(reg)	dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3566

3567
#define I915_READ64_2x32(lower_reg, upper_reg) ({			\
3568 3569
	u32 upper, lower, old_upper, loop = 0;				\
	upper = I915_READ(upper_reg);					\
3570
	do {								\
3571
		old_upper = upper;					\
3572
		lower = I915_READ(lower_reg);				\
3573 3574
		upper = I915_READ(upper_reg);				\
	} while (upper != old_upper && loop++ < 2);			\
3575
	(u64)upper << 32 | lower; })
3576

3577 3578 3579
#define POSTING_READ(reg)	(void)I915_READ_NOTRACE(reg)
#define POSTING_READ16(reg)	(void)I915_READ16_NOTRACE(reg)

3580
#define __raw_read(x, s) \
3581
static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
3582
					     i915_reg_t reg) \
3583
{ \
3584
	return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3585 3586 3587
}

#define __raw_write(x, s) \
3588
static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
3589
				       i915_reg_t reg, uint##x##_t val) \
3590
{ \
3591
	write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3592 3593 3594 3595 3596 3597 3598 3599 3600 3601 3602 3603 3604 3605
}
__raw_read(8, b)
__raw_read(16, w)
__raw_read(32, l)
__raw_read(64, q)

__raw_write(8, b)
__raw_write(16, w)
__raw_write(32, l)
__raw_write(64, q)

#undef __raw_read
#undef __raw_write

3606
/* These are untraced mmio-accessors that are only valid to be used inside
3607
 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3608
 * controlled.
3609
 *
3610
 * Think twice, and think again, before using these.
3611 3612 3613 3614 3615 3616 3617 3618 3619 3620 3621 3622 3623 3624 3625 3626 3627 3628 3629 3630
 *
 * As an example, these accessors can possibly be used between:
 *
 * spin_lock_irq(&dev_priv->uncore.lock);
 * intel_uncore_forcewake_get__locked();
 *
 * and
 *
 * intel_uncore_forcewake_put__locked();
 * spin_unlock_irq(&dev_priv->uncore.lock);
 *
 *
 * Note: some registers may not need forcewake held, so
 * intel_uncore_forcewake_{get,put} can be omitted, see
 * intel_uncore_forcewake_for_reg().
 *
 * Certain architectures will die if the same cacheline is concurrently accessed
 * by different clients (e.g. on Ivybridge). Access to registers should
 * therefore generally be serialised, by either the dev_priv->uncore.lock or
 * a more localised lock guarding all access to that bank of registers.
3631
 */
3632 3633
#define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3634
#define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3635 3636
#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)

3637 3638 3639 3640
/* "Broadcast RGB" property */
#define INTEL_BROADCAST_RGB_AUTO 0
#define INTEL_BROADCAST_RGB_FULL 1
#define INTEL_BROADCAST_RGB_LIMITED 2
3641

3642
static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
3643
{
3644
	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3645
		return VLV_VGACNTRL;
3646
	else if (INTEL_GEN(dev_priv) >= 5)
3647
		return CPU_VGACNTRL;
3648 3649 3650 3651
	else
		return VGACNTRL;
}

3652 3653 3654 3655 3656 3657 3658
static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
{
	unsigned long j = msecs_to_jiffies(m);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

3659 3660
static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
{
3661 3662 3663 3664 3665
	/* nsecs_to_jiffies64() does not guard against overflow */
	if (NSEC_PER_SEC % HZ &&
	    div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ)
		return MAX_JIFFY_OFFSET;

3666 3667 3668
        return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
}

3669 3670 3671 3672 3673 3674 3675 3676
static inline unsigned long
timespec_to_jiffies_timeout(const struct timespec *value)
{
	unsigned long j = timespec_to_jiffies(value);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

3677 3678 3679 3680 3681 3682 3683 3684 3685
/*
 * If you need to wait X milliseconds between events A and B, but event B
 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
 * when event A happened, then just before event B you call this function and
 * pass the timestamp as the first argument, and X as the second argument.
 */
static inline void
wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
{
3686
	unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3687 3688 3689 3690 3691 3692 3693 3694 3695 3696

	/*
	 * Don't re-read the value of "jiffies" every time since it may change
	 * behind our back and break the math.
	 */
	tmp_jiffies = jiffies;
	target_jiffies = timestamp_jiffies +
			 msecs_to_jiffies_timeout(to_wait_ms);

	if (time_after(target_jiffies, tmp_jiffies)) {
3697 3698 3699 3700
		remaining_jiffies = target_jiffies - tmp_jiffies;
		while (remaining_jiffies)
			remaining_jiffies =
			    schedule_timeout_uninterruptible(remaining_jiffies);
3701 3702
	}
}
3703 3704

static inline bool
3705
__i915_request_irq_complete(const struct i915_request *rq)
3706
{
3707
	struct intel_engine_cs *engine = rq->engine;
3708
	u32 seqno;
3709

3710 3711 3712 3713 3714 3715
	/* Note that the engine may have wrapped around the seqno, and
	 * so our request->global_seqno will be ahead of the hardware,
	 * even though it completed the request before wrapping. We catch
	 * this by kicking all the waiters before resetting the seqno
	 * in hardware, and also signal the fence.
	 */
3716
	if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags))
3717 3718
		return true;

3719 3720 3721 3722 3723 3724
	/* The request was dequeued before we were awoken. We check after
	 * inspecting the hw to confirm that this was the same request
	 * that generated the HWS update. The memory barriers within
	 * the request execution are sufficient to ensure that a check
	 * after reading the value from hw matches this request.
	 */
3725
	seqno = i915_request_global_seqno(rq);
3726 3727 3728
	if (!seqno)
		return false;

3729 3730 3731
	/* Before we do the heavier coherent read of the seqno,
	 * check the value (hopefully) in the CPU cacheline.
	 */
3732
	if (__i915_request_completed(rq, seqno))
3733 3734
		return true;

3735 3736 3737 3738 3739 3740 3741 3742 3743 3744 3745
	/* Ensure our read of the seqno is coherent so that we
	 * do not "miss an interrupt" (i.e. if this is the last
	 * request and the seqno write from the GPU is not visible
	 * by the time the interrupt fires, we will see that the
	 * request is incomplete and go back to sleep awaiting
	 * another interrupt that will never come.)
	 *
	 * Strictly, we only need to do this once after an interrupt,
	 * but it is easier and safer to do it every time the waiter
	 * is woken.
	 */
3746
	if (engine->irq_seqno_barrier &&
3747
	    test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) {
3748
		struct intel_breadcrumbs *b = &engine->breadcrumbs;
3749

3750 3751 3752 3753 3754 3755 3756 3757 3758 3759 3760 3761
		/* The ordering of irq_posted versus applying the barrier
		 * is crucial. The clearing of the current irq_posted must
		 * be visible before we perform the barrier operation,
		 * such that if a subsequent interrupt arrives, irq_posted
		 * is reasserted and our task rewoken (which causes us to
		 * do another __i915_request_irq_complete() immediately
		 * and reapply the barrier). Conversely, if the clear
		 * occurs after the barrier, then an interrupt that arrived
		 * whilst we waited on the barrier would not trigger a
		 * barrier on the next pass, and the read may not see the
		 * seqno update.
		 */
3762
		engine->irq_seqno_barrier(engine);
3763 3764 3765 3766 3767 3768 3769

		/* If we consume the irq, but we are no longer the bottom-half,
		 * the real bottom-half may not have serialised their own
		 * seqno check with the irq-barrier (i.e. may have inspected
		 * the seqno before we believe it coherent since they see
		 * irq_posted == false but we are still running).
		 */
3770
		spin_lock_irq(&b->irq_lock);
3771
		if (b->irq_wait && b->irq_wait->tsk != current)
3772 3773 3774 3775 3776 3777
			/* Note that if the bottom-half is changed as we
			 * are sending the wake-up, the new bottom-half will
			 * be woken by whomever made the change. We only have
			 * to worry about when we steal the irq-posted for
			 * ourself.
			 */
3778
			wake_up_process(b->irq_wait->tsk);
3779
		spin_unlock_irq(&b->irq_lock);
3780

3781
		if (__i915_request_completed(rq, seqno))
3782 3783
			return true;
	}
3784 3785 3786 3787

	return false;
}

3788 3789 3790
void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);

3791 3792 3793 3794 3795 3796 3797 3798 3799 3800 3801 3802 3803 3804 3805 3806
/* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
 * perform the operation. To check beforehand, pass in the parameters to
 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
 * you only need to pass in the minor offsets, page-aligned pointers are
 * always valid.
 *
 * For just checking for SSE4.1, in the foreknowledge that the future use
 * will be correctly aligned, just use i915_has_memcpy_from_wc().
 */
#define i915_can_memcpy_from_wc(dst, src, len) \
	i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)

#define i915_has_memcpy_from_wc() \
	i915_memcpy_from_wc(NULL, NULL, 0)

3807 3808 3809 3810 3811
/* i915_mm.c */
int remap_io_mapping(struct vm_area_struct *vma,
		     unsigned long addr, unsigned long pfn, unsigned long size,
		     struct io_mapping *iomap);

3812 3813 3814 3815 3816 3817 3818 3819
static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
{
	if (INTEL_GEN(i915) >= 10)
		return CNL_HWS_CSB_WRITE_INDEX;
	else
		return I915_HWS_CSB_WRITE_INDEX;
}

L
Linus Torvalds 已提交
3820
#endif