i915_drv.h 132.8 KB
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/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
 */
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/*
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 *
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#ifndef _I915_DRV_H_
#define _I915_DRV_H_

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#include <uapi/drm/i915_drm.h>
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#include <uapi/drm/drm_fourcc.h>
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#include <linux/io-mapping.h>
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include <linux/backlight.h>
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#include <linux/hash.h>
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#include <linux/intel-iommu.h>
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#include <linux/kref.h>
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#include <linux/pm_qos.h>
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#include <linux/reservation.h>
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#include <linux/shmem_fs.h>

#include <drm/drmP.h>
#include <drm/intel-gtt.h>
#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
#include <drm/drm_gem.h>
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#include <drm/drm_auth.h>
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#include <drm/drm_cache.h>
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#include "i915_params.h"
#include "i915_reg.h"
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#include "i915_utils.h"
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#include "intel_uncore.h"
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#include "intel_bios.h"
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#include "intel_dpll_mgr.h"
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#include "intel_uc.h"
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#include "intel_lrc.h"
#include "intel_ringbuffer.h"

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#include "i915_gem.h"
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#include "i915_gem_context.h"
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#include "i915_gem_fence_reg.h"
#include "i915_gem_object.h"
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#include "i915_gem_gtt.h"
#include "i915_gem_render_state.h"
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#include "i915_gem_request.h"
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#include "i915_gem_timeline.h"
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#include "i915_vma.h"

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#include "intel_gvt.h"

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/* General customization:
 */

#define DRIVER_NAME		"i915"
#define DRIVER_DESC		"Intel Graphics"
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#define DRIVER_DATE		"20171012"
#define DRIVER_TIMESTAMP	1507831511
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/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
 * which may not necessarily be a user visible problem.  This will either
 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
 * enable distros and users to tailor their preferred amount of i915 abrt
 * spam.
 */
#define I915_STATE_WARN(condition, format...) ({			\
	int __ret_warn_on = !!(condition);				\
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	if (unlikely(__ret_warn_on))					\
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		if (!WARN(i915_modparams.verbose_state_checks, format))	\
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			DRM_ERROR(format);				\
	unlikely(__ret_warn_on);					\
})

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#define I915_STATE_WARN_ON(x)						\
	I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
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bool __i915_inject_load_failure(const char *func, int line);
#define i915_inject_load_failure() \
	__i915_inject_load_failure(__func__, __LINE__)

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typedef struct {
	uint32_t val;
} uint_fixed_16_16_t;

#define FP_16_16_MAX ({ \
	uint_fixed_16_16_t fp; \
	fp.val = UINT_MAX; \
	fp; \
})

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static inline bool is_fixed16_zero(uint_fixed_16_16_t val)
{
	if (val.val == 0)
		return true;
	return false;
}

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static inline uint_fixed_16_16_t u32_to_fixed16(uint32_t val)
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{
	uint_fixed_16_16_t fp;

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	WARN_ON(val > U16_MAX);
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	fp.val = val << 16;
	return fp;
}

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static inline uint32_t fixed16_to_u32_round_up(uint_fixed_16_16_t fp)
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{
	return DIV_ROUND_UP(fp.val, 1 << 16);
}

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static inline uint32_t fixed16_to_u32(uint_fixed_16_16_t fp)
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{
	return fp.val >> 16;
}

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static inline uint_fixed_16_16_t min_fixed16(uint_fixed_16_16_t min1,
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						 uint_fixed_16_16_t min2)
{
	uint_fixed_16_16_t min;

	min.val = min(min1.val, min2.val);
	return min;
}

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static inline uint_fixed_16_16_t max_fixed16(uint_fixed_16_16_t max1,
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						 uint_fixed_16_16_t max2)
{
	uint_fixed_16_16_t max;

	max.val = max(max1.val, max2.val);
	return max;
}

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static inline uint_fixed_16_16_t clamp_u64_to_fixed16(uint64_t val)
{
	uint_fixed_16_16_t fp;
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	WARN_ON(val > U32_MAX);
	fp.val = (uint32_t) val;
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	return fp;
}

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static inline uint32_t div_round_up_fixed16(uint_fixed_16_16_t val,
					    uint_fixed_16_16_t d)
{
	return DIV_ROUND_UP(val.val, d.val);
}

static inline uint32_t mul_round_up_u32_fixed16(uint32_t val,
						uint_fixed_16_16_t mul)
{
	uint64_t intermediate_val;

	intermediate_val = (uint64_t) val * mul.val;
	intermediate_val = DIV_ROUND_UP_ULL(intermediate_val, 1 << 16);
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	WARN_ON(intermediate_val > U32_MAX);
	return (uint32_t) intermediate_val;
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}

static inline uint_fixed_16_16_t mul_fixed16(uint_fixed_16_16_t val,
					     uint_fixed_16_16_t mul)
{
	uint64_t intermediate_val;

	intermediate_val = (uint64_t) val.val * mul.val;
	intermediate_val = intermediate_val >> 16;
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	return clamp_u64_to_fixed16(intermediate_val);
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}

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static inline uint_fixed_16_16_t div_fixed16(uint32_t val, uint32_t d)
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{
	uint64_t interm_val;

	interm_val = (uint64_t)val << 16;
	interm_val = DIV_ROUND_UP_ULL(interm_val, d);
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	return clamp_u64_to_fixed16(interm_val);
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}

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static inline uint32_t div_round_up_u32_fixed16(uint32_t val,
						uint_fixed_16_16_t d)
{
	uint64_t interm_val;

	interm_val = (uint64_t)val << 16;
	interm_val = DIV_ROUND_UP_ULL(interm_val, d.val);
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	WARN_ON(interm_val > U32_MAX);
	return (uint32_t) interm_val;
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}

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static inline uint_fixed_16_16_t mul_u32_fixed16(uint32_t val,
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						     uint_fixed_16_16_t mul)
{
	uint64_t intermediate_val;

	intermediate_val = (uint64_t) val * mul.val;
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	return clamp_u64_to_fixed16(intermediate_val);
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}

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static inline uint_fixed_16_16_t add_fixed16(uint_fixed_16_16_t add1,
					     uint_fixed_16_16_t add2)
{
	uint64_t interm_sum;

	interm_sum = (uint64_t) add1.val + add2.val;
	return clamp_u64_to_fixed16(interm_sum);
}

static inline uint_fixed_16_16_t add_fixed16_u32(uint_fixed_16_16_t add1,
						 uint32_t add2)
{
	uint64_t interm_sum;
	uint_fixed_16_16_t interm_add2 = u32_to_fixed16(add2);

	interm_sum = (uint64_t) add1.val + interm_add2.val;
	return clamp_u64_to_fixed16(interm_sum);
}

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static inline const char *yesno(bool v)
{
	return v ? "yes" : "no";
}

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static inline const char *onoff(bool v)
{
	return v ? "on" : "off";
}

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static inline const char *enableddisabled(bool v)
{
	return v ? "enabled" : "disabled";
}

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enum pipe {
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	INVALID_PIPE = -1,
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	PIPE_A = 0,
	PIPE_B,
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	PIPE_C,
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	_PIPE_EDP,
	I915_MAX_PIPES = _PIPE_EDP
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};
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#define pipe_name(p) ((p) + 'A')
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enum transcoder {
	TRANSCODER_A = 0,
	TRANSCODER_B,
	TRANSCODER_C,
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	TRANSCODER_EDP,
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	TRANSCODER_DSI_A,
	TRANSCODER_DSI_C,
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	I915_MAX_TRANSCODERS
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};
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static inline const char *transcoder_name(enum transcoder transcoder)
{
	switch (transcoder) {
	case TRANSCODER_A:
		return "A";
	case TRANSCODER_B:
		return "B";
	case TRANSCODER_C:
		return "C";
	case TRANSCODER_EDP:
		return "EDP";
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	case TRANSCODER_DSI_A:
		return "DSI A";
	case TRANSCODER_DSI_C:
		return "DSI C";
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	default:
		return "<invalid>";
	}
}
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static inline bool transcoder_is_dsi(enum transcoder transcoder)
{
	return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
}

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/*
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 * Global legacy plane identifier. Valid only for primary/sprite
 * planes on pre-g4x, and only for primary planes on g4x+.
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 */
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enum plane {
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	PLANE_A,
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	PLANE_B,
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	PLANE_C,
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};
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#define plane_name(p) ((p) + 'A')
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#define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
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/*
 * Per-pipe plane identifier.
 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
 * number of planes per CRTC.  Not all platforms really have this many planes,
 * which means some arrays of size I915_MAX_PLANES may have unused entries
 * between the topmost sprite plane and the cursor plane.
 *
 * This is expected to be passed to various register macros
 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
 */
enum plane_id {
	PLANE_PRIMARY,
	PLANE_SPRITE0,
	PLANE_SPRITE1,
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	PLANE_SPRITE2,
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	PLANE_CURSOR,
	I915_MAX_PLANES,
};

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#define for_each_plane_id_on_crtc(__crtc, __p) \
	for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
		for_each_if ((__crtc)->plane_ids_mask & BIT(__p))

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enum port {
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	PORT_NONE = -1,
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	PORT_A = 0,
	PORT_B,
	PORT_C,
	PORT_D,
	PORT_E,
	I915_MAX_PORTS
};
#define port_name(p) ((p) + 'A')

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#define I915_NUM_PHYS_VLV 2
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enum dpio_channel {
	DPIO_CH0,
	DPIO_CH1
};

enum dpio_phy {
	DPIO_PHY0,
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	DPIO_PHY1,
	DPIO_PHY2,
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};

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enum intel_display_power_domain {
	POWER_DOMAIN_PIPE_A,
	POWER_DOMAIN_PIPE_B,
	POWER_DOMAIN_PIPE_C,
	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
	POWER_DOMAIN_TRANSCODER_A,
	POWER_DOMAIN_TRANSCODER_B,
	POWER_DOMAIN_TRANSCODER_C,
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	POWER_DOMAIN_TRANSCODER_EDP,
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	POWER_DOMAIN_TRANSCODER_DSI_A,
	POWER_DOMAIN_TRANSCODER_DSI_C,
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	POWER_DOMAIN_PORT_DDI_A_LANES,
	POWER_DOMAIN_PORT_DDI_B_LANES,
	POWER_DOMAIN_PORT_DDI_C_LANES,
	POWER_DOMAIN_PORT_DDI_D_LANES,
	POWER_DOMAIN_PORT_DDI_E_LANES,
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	POWER_DOMAIN_PORT_DDI_A_IO,
	POWER_DOMAIN_PORT_DDI_B_IO,
	POWER_DOMAIN_PORT_DDI_C_IO,
	POWER_DOMAIN_PORT_DDI_D_IO,
	POWER_DOMAIN_PORT_DDI_E_IO,
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	POWER_DOMAIN_PORT_DSI,
	POWER_DOMAIN_PORT_CRT,
	POWER_DOMAIN_PORT_OTHER,
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	POWER_DOMAIN_VGA,
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	POWER_DOMAIN_AUDIO,
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	POWER_DOMAIN_PLLS,
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	POWER_DOMAIN_AUX_A,
	POWER_DOMAIN_AUX_B,
	POWER_DOMAIN_AUX_C,
	POWER_DOMAIN_AUX_D,
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	POWER_DOMAIN_GMBUS,
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	POWER_DOMAIN_MODESET,
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	POWER_DOMAIN_INIT,
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	POWER_DOMAIN_NUM,
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};

#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
		((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
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#define POWER_DOMAIN_TRANSCODER(tran) \
	((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
	 (tran) + POWER_DOMAIN_TRANSCODER_A)
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enum hpd_pin {
	HPD_NONE = 0,
	HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
	HPD_CRT,
	HPD_SDVO_B,
	HPD_SDVO_C,
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	HPD_PORT_A,
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	HPD_PORT_B,
	HPD_PORT_C,
	HPD_PORT_D,
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	HPD_PORT_E,
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	HPD_NUM_PINS
};

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#define for_each_hpd_pin(__pin) \
	for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)

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#define HPD_STORM_DEFAULT_THRESHOLD 5

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struct i915_hotplug {
	struct work_struct hotplug_work;

	struct {
		unsigned long last_jiffies;
		int count;
		enum {
			HPD_ENABLED = 0,
			HPD_DISABLED = 1,
			HPD_MARK_DISABLED = 2
		} state;
	} stats[HPD_NUM_PINS];
	u32 event_bits;
	struct delayed_work reenable_work;

	struct intel_digital_port *irq_port[I915_MAX_PORTS];
	u32 long_port_mask;
	u32 short_port_mask;
	struct work_struct dig_port_work;

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	struct work_struct poll_init_work;
	bool poll_enabled;

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	unsigned int hpd_storm_threshold;

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	/*
	 * if we get a HPD irq from DP and a HPD irq from non-DP
	 * the non-DP HPD could block the workqueue on a mode config
	 * mutex getting, that userspace may have taken. However
	 * userspace is waiting on the DP workqueue to run which is
	 * blocked behind the non-DP one.
	 */
	struct workqueue_struct *dp_wq;
};

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#define I915_GEM_GPU_DOMAINS \
	(I915_GEM_DOMAIN_RENDER | \
	 I915_GEM_DOMAIN_SAMPLER | \
	 I915_GEM_DOMAIN_COMMAND | \
	 I915_GEM_DOMAIN_INSTRUCTION | \
	 I915_GEM_DOMAIN_VERTEX)
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#define for_each_pipe(__dev_priv, __p) \
	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
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#define for_each_pipe_masked(__dev_priv, __p, __mask) \
	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
		for_each_if ((__mask) & (1 << (__p)))
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#define for_each_universal_plane(__dev_priv, __pipe, __p)		\
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	for ((__p) = 0;							\
	     (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1;	\
	     (__p)++)
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#define for_each_sprite(__dev_priv, __p, __s)				\
	for ((__s) = 0;							\
	     (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)];	\
	     (__s)++)
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#define for_each_port_masked(__port, __ports_mask) \
	for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)	\
		for_each_if ((__ports_mask) & (1 << (__port)))

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#define for_each_crtc(dev, crtc) \
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	list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
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#define for_each_intel_plane(dev, intel_plane) \
	list_for_each_entry(intel_plane,			\
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			    &(dev)->mode_config.plane_list,	\
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			    base.head)

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#define for_each_intel_plane_mask(dev, intel_plane, plane_mask)		\
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	list_for_each_entry(intel_plane,				\
			    &(dev)->mode_config.plane_list,		\
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			    base.head)					\
		for_each_if ((plane_mask) &				\
			     (1 << drm_plane_index(&intel_plane->base)))

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#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)	\
	list_for_each_entry(intel_plane,				\
			    &(dev)->mode_config.plane_list,		\
			    base.head)					\
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		for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
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#define for_each_intel_crtc(dev, intel_crtc)				\
	list_for_each_entry(intel_crtc,					\
			    &(dev)->mode_config.crtc_list,		\
			    base.head)
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#define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask)		\
	list_for_each_entry(intel_crtc,					\
			    &(dev)->mode_config.crtc_list,		\
			    base.head)					\
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		for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))

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#define for_each_intel_encoder(dev, intel_encoder)		\
	list_for_each_entry(intel_encoder,			\
			    &(dev)->mode_config.encoder_list,	\
			    base.head)

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#define for_each_intel_connector_iter(intel_connector, iter) \
	while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))

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#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
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		for_each_if ((intel_encoder)->base.crtc == (__crtc))
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#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
	list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
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		for_each_if ((intel_connector)->base.encoder == (__encoder))
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#define for_each_power_domain(domain, mask)				\
	for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)	\
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		for_each_if (BIT_ULL(domain) & (mask))
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#define for_each_power_well(__dev_priv, __power_well)				\
	for ((__power_well) = (__dev_priv)->power_domains.power_wells;	\
	     (__power_well) - (__dev_priv)->power_domains.power_wells <	\
		(__dev_priv)->power_domains.power_well_count;		\
	     (__power_well)++)

#define for_each_power_well_rev(__dev_priv, __power_well)			\
	for ((__power_well) = (__dev_priv)->power_domains.power_wells +		\
			      (__dev_priv)->power_domains.power_well_count - 1;	\
	     (__power_well) - (__dev_priv)->power_domains.power_wells >= 0;	\
	     (__power_well)--)

#define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask)	\
	for_each_power_well(__dev_priv, __power_well)				\
		for_each_if ((__power_well)->domains & (__domain_mask))

#define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \
	for_each_power_well_rev(__dev_priv, __power_well)		        \
		for_each_if ((__power_well)->domains & (__domain_mask))

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#define for_each_intel_plane_in_state(__state, plane, plane_state, __i) \
	for ((__i) = 0; \
	     (__i) < (__state)->base.dev->mode_config.num_total_plane && \
		     ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
		      (plane_state) = to_intel_plane_state((__state)->base.planes[__i].state), 1); \
	     (__i)++) \
		for_each_if (plane_state)

572 573 574 575 576 577 578 579 580
#define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
	for ((__i) = 0; \
	     (__i) < (__state)->base.dev->mode_config.num_crtc && \
		     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
		      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
	     (__i)++) \
		for_each_if (crtc)


581 582 583 584 585 586 587 588 589
#define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
	for ((__i) = 0; \
	     (__i) < (__state)->base.dev->mode_config.num_total_plane && \
		     ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
		      (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
		      (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
	     (__i)++) \
		for_each_if (plane)

590
struct drm_i915_private;
591
struct i915_mm_struct;
592
struct i915_mmu_object;
593

594 595 596 597 598 599 600
struct drm_i915_file_private {
	struct drm_i915_private *dev_priv;
	struct drm_file *file;

	struct {
		spinlock_t lock;
		struct list_head request_list;
601 602 603 604 605 606
/* 20ms is a fairly arbitrary limit (greater than the average frame time)
 * chosen to prevent the CPU getting more than a frame ahead of the GPU
 * (when using lax throttling for the frontbuffer). We also use it to
 * offer free GPU waitboosts for severely congested workloads.
 */
#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
607 608 609
	} mm;
	struct idr context_idr;

610
	struct intel_rps_client {
611
		atomic_t boosts;
612
	} rps_client;
613

614
	unsigned int bsd_engine;
615 616 617 618 619 620 621 622

/* Client can have a maximum of 3 contexts banned before
 * it is denied of creating new contexts. As one context
 * ban needs 4 consecutive hangs, and more if there is
 * progress in between, this is a last resort stop gap measure
 * to limit the badly behaving clients access to gpu.
 */
#define I915_MAX_CLIENT_CONTEXT_BANS 3
623
	atomic_t context_bans;
624 625
};

626 627 628 629 630 631 632 633 634 635 636
/* Used by dp and fdi links */
struct intel_link_m_n {
	uint32_t	tu;
	uint32_t	gmch_m;
	uint32_t	gmch_n;
	uint32_t	link_m;
	uint32_t	link_n;
};

void intel_link_compute_m_n(int bpp, int nlanes,
			    int pixel_clock, int link_clock,
637 638
			    struct intel_link_m_n *m_n,
			    bool reduce_m_n);
639

L
Linus Torvalds 已提交
640 641 642
/* Interface history:
 *
 * 1.1: Original.
D
Dave Airlie 已提交
643 644
 * 1.2: Add Power Management
 * 1.3: Add vblank support
645
 * 1.4: Fix cmdbuffer path, add heap destroy
646
 * 1.5: Add vblank pipe configuration
=
=?utf-8?q?Michel_D=C3=A4nzer?= 已提交
647 648
 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 *      - Support vertical blank on secondary display pipe
L
Linus Torvalds 已提交
649 650
 */
#define DRIVER_MAJOR		1
=
=?utf-8?q?Michel_D=C3=A4nzer?= 已提交
651
#define DRIVER_MINOR		6
L
Linus Torvalds 已提交
652 653
#define DRIVER_PATCHLEVEL	0

654 655 656 657 658
struct opregion_header;
struct opregion_acpi;
struct opregion_swsci;
struct opregion_asle;

659
struct intel_opregion {
660 661 662
	struct opregion_header *header;
	struct opregion_acpi *acpi;
	struct opregion_swsci *swsci;
J
Jani Nikula 已提交
663 664
	u32 swsci_gbda_sub_functions;
	u32 swsci_sbcb_sub_functions;
665
	struct opregion_asle *asle;
666
	void *rvda;
667
	void *vbt_firmware;
668
	const void *vbt;
669
	u32 vbt_size;
670
	u32 *lid_state;
671
	struct work_struct asle_work;
672
};
673
#define OPREGION_SIZE            (8*1024)
674

675 676 677
struct intel_overlay;
struct intel_overlay_error_state;

678
struct sdvo_device_mapping {
C
Chris Wilson 已提交
679
	u8 initialized;
680 681 682
	u8 dvo_port;
	u8 slave_addr;
	u8 dvo_wiring;
C
Chris Wilson 已提交
683
	u8 i2c_pin;
684
	u8 ddc_pin;
685 686
};

687
struct intel_connector;
688
struct intel_encoder;
689
struct intel_atomic_state;
690
struct intel_crtc_state;
691
struct intel_initial_plane_config;
692
struct intel_crtc;
693 694
struct intel_limit;
struct dpll;
695
struct intel_cdclk_state;
696

697
struct drm_i915_display_funcs {
698 699
	void (*get_cdclk)(struct drm_i915_private *dev_priv,
			  struct intel_cdclk_state *cdclk_state);
700 701
	void (*set_cdclk)(struct drm_i915_private *dev_priv,
			  const struct intel_cdclk_state *cdclk_state);
702
	int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane);
703
	int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
704 705 706
	int (*compute_intermediate_wm)(struct drm_device *dev,
				       struct intel_crtc *intel_crtc,
				       struct intel_crtc_state *newstate);
707 708 709 710 711 712
	void (*initial_watermarks)(struct intel_atomic_state *state,
				   struct intel_crtc_state *cstate);
	void (*atomic_update_watermarks)(struct intel_atomic_state *state,
					 struct intel_crtc_state *cstate);
	void (*optimize_watermarks)(struct intel_atomic_state *state,
				    struct intel_crtc_state *cstate);
713
	int (*compute_global_watermarks)(struct drm_atomic_state *state);
714
	void (*update_wm)(struct intel_crtc *crtc);
715
	int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
716 717 718
	/* Returns the active state of the crtc, and if the crtc is active,
	 * fills out the pipe-config with the hw state. */
	bool (*get_pipe_config)(struct intel_crtc *,
719
				struct intel_crtc_state *);
720 721
	void (*get_initial_plane_config)(struct intel_crtc *,
					 struct intel_initial_plane_config *);
722 723
	int (*crtc_compute_clock)(struct intel_crtc *crtc,
				  struct intel_crtc_state *crtc_state);
724 725 726 727
	void (*crtc_enable)(struct intel_crtc_state *pipe_config,
			    struct drm_atomic_state *old_state);
	void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
			     struct drm_atomic_state *old_state);
728
	void (*update_crtcs)(struct drm_atomic_state *state);
729 730
	void (*audio_codec_enable)(struct drm_connector *connector,
				   struct intel_encoder *encoder,
731
				   const struct drm_display_mode *adjusted_mode);
732
	void (*audio_codec_disable)(struct intel_encoder *encoder);
733 734
	void (*fdi_link_train)(struct intel_crtc *crtc,
			       const struct intel_crtc_state *crtc_state);
735
	void (*init_clock_gating)(struct drm_i915_private *dev_priv);
736
	void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
737 738 739 740 741
	/* clock updates for mode set */
	/* cursor updates */
	/* render clock increase/decrease */
	/* display clock increase/decrease */
	/* pll clock increase/decrease */
742

743 744
	void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
	void (*load_luts)(struct drm_crtc_state *crtc_state);
745 746
};

747 748 749 750
#define CSR_VERSION(major, minor)	((major) << 16 | (minor))
#define CSR_VERSION_MAJOR(version)	((version) >> 16)
#define CSR_VERSION_MINOR(version)	((version) & 0xffff)

751
struct intel_csr {
752
	struct work_struct work;
753
	const char *fw_path;
754
	uint32_t *dmc_payload;
755
	uint32_t dmc_fw_size;
756
	uint32_t version;
757
	uint32_t mmio_count;
758
	i915_reg_t mmioaddr[8];
759
	uint32_t mmiodata[8];
760
	uint32_t dc_state;
761
	uint32_t allowed_dc_mask;
762 763
};

764 765
#define DEV_INFO_FOR_EACH_FLAG(func) \
	func(is_mobile); \
766
	func(is_lp); \
767
	func(is_alpha_support); \
768
	/* Keep has_* in alphabetical order */ \
769
	func(has_64bit_reloc); \
770
	func(has_aliasing_ppgtt); \
771
	func(has_csr); \
772
	func(has_ddi); \
773
	func(has_dp_mst); \
774
	func(has_reset_engine); \
775 776
	func(has_fbc); \
	func(has_fpga_dbg); \
777 778
	func(has_full_ppgtt); \
	func(has_full_48bit_ppgtt); \
779 780
	func(has_gmch_display); \
	func(has_guc); \
781
	func(has_guc_ct); \
782
	func(has_hotplug); \
783
	func(has_l3_dpf); \
784
	func(has_llc); \
785
	func(has_logical_ring_contexts); \
786
	func(has_logical_ring_preemption); \
787 788 789 790 791 792 793 794
	func(has_overlay); \
	func(has_pipe_cxsr); \
	func(has_pooled_eu); \
	func(has_psr); \
	func(has_rc6); \
	func(has_rc6p); \
	func(has_resource_streamer); \
	func(has_runtime_pm); \
795
	func(has_snoop); \
796
	func(unfenced_needs_alignment); \
797 798 799
	func(cursor_needs_physical); \
	func(hws_needs_physical); \
	func(overlay_needs_physical); \
800 801
	func(supports_tv); \
	func(has_ipc);
D
Daniel Vetter 已提交
802

803
struct sseu_dev_info {
804
	u8 slice_mask;
805
	u8 subslice_mask;
806 807
	u8 eu_total;
	u8 eu_per_subslice;
808 809 810 811 812 813
	u8 min_eu_in_pool;
	/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
	u8 subslice_7eu[3];
	u8 has_slice_pg:1;
	u8 has_subslice_pg:1;
	u8 has_eu_pg:1;
814 815
};

816 817 818 819 820
static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
{
	return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
}

821 822 823 824 825 826 827 828 829 830 831 832 833
/* Keep in gen based order, and chronological order within a gen */
enum intel_platform {
	INTEL_PLATFORM_UNINITIALIZED = 0,
	INTEL_I830,
	INTEL_I845G,
	INTEL_I85X,
	INTEL_I865G,
	INTEL_I915G,
	INTEL_I915GM,
	INTEL_I945G,
	INTEL_I945GM,
	INTEL_G33,
	INTEL_PINEVIEW,
834 835
	INTEL_I965G,
	INTEL_I965GM,
836 837
	INTEL_G45,
	INTEL_GM45,
838 839 840 841 842 843 844 845 846 847 848
	INTEL_IRONLAKE,
	INTEL_SANDYBRIDGE,
	INTEL_IVYBRIDGE,
	INTEL_VALLEYVIEW,
	INTEL_HASWELL,
	INTEL_BROADWELL,
	INTEL_CHERRYVIEW,
	INTEL_SKYLAKE,
	INTEL_BROXTON,
	INTEL_KABYLAKE,
	INTEL_GEMINILAKE,
849
	INTEL_COFFEELAKE,
850
	INTEL_CANNONLAKE,
851
	INTEL_MAX_PLATFORMS
852 853
};

854
struct intel_device_info {
855
	u16 device_id;
856
	u16 gen_mask;
857 858

	u8 gen;
859
	u8 gt; /* GT number, 0 if undefined */
860
	u8 num_rings;
861 862 863
	u8 ring_mask; /* Rings supported by the HW */

	enum intel_platform platform;
864
	u32 platform_mask;
865 866 867 868 869 870 871

	u32 display_mmio_offset;

	u8 num_pipes;
	u8 num_sprites[I915_MAX_PIPES];
	u8 num_scalers[I915_MAX_PIPES];

872 873
	unsigned int page_sizes; /* page sizes supported by the HW */

874 875 876
#define DEFINE_FLAG(name) u8 name:1
	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
#undef DEFINE_FLAG
877
	u16 ddb_size; /* in blocks */
878

879 880 881 882
	/* Register offsets for the various display pipes and transcoders */
	int pipe_offsets[I915_MAX_TRANSCODERS];
	int trans_offsets[I915_MAX_TRANSCODERS];
	int palette_offsets[I915_MAX_PIPES];
883
	int cursor_offsets[I915_MAX_PIPES];
884 885

	/* Slice/subslice/EU info */
886
	struct sseu_dev_info sseu;
887 888 889 890 891

	struct color_luts {
		u16 degamma_lut_size;
		u16 gamma_lut_size;
	} color;
892 893
};

894 895
struct intel_display_error_state;

896
struct i915_gpu_state {
897 898
	struct kref ref;
	struct timeval time;
899 900
	struct timeval boottime;
	struct timeval uptime;
901

902 903
	struct drm_i915_private *i915;

904 905
	char error_msg[128];
	bool simulated;
906
	bool awake;
907 908
	bool wakelock;
	bool suspended;
909 910 911 912
	int iommu;
	u32 reset_count;
	u32 suspend_count;
	struct intel_device_info device_info;
913
	struct i915_params params;
914 915 916 917 918

	/* Generic register state */
	u32 eir;
	u32 pgtbl_er;
	u32 ier;
919
	u32 gtier[4], ngtier;
920 921 922 923 924 925 926 927 928 929 930 931
	u32 ccid;
	u32 derrmr;
	u32 forcewake;
	u32 error; /* gen6+ */
	u32 err_int; /* gen7 */
	u32 fault_data0; /* gen8, gen9 */
	u32 fault_data1; /* gen8, gen9 */
	u32 done_reg;
	u32 gac_eco;
	u32 gam_ecochk;
	u32 gab_ctl;
	u32 gfx_mode;
932

933
	u32 nfence;
934 935 936
	u64 fence[I915_MAX_NUM_FENCES];
	struct intel_overlay_error_state *overlay;
	struct intel_display_error_state *display;
937
	struct drm_i915_error_object *semaphore;
938
	struct drm_i915_error_object *guc_log;
939 940 941 942 943 944

	struct drm_i915_error_engine {
		int engine_id;
		/* Software tracked state */
		bool waiting;
		int num_waiters;
945 946
		unsigned long hangcheck_timestamp;
		bool hangcheck_stalled;
947 948 949
		enum intel_engine_hangcheck_action hangcheck_action;
		struct i915_address_space *vm;
		int num_requests;
950
		u32 reset_count;
951

952 953 954
		/* position of active request inside the ring */
		u32 rq_head, rq_post, rq_tail;

955 956 957 958 959 960 961 962 963 964 965
		/* our own tracking of ring head and tail */
		u32 cpu_ring_head;
		u32 cpu_ring_tail;

		u32 last_seqno;

		/* Register state */
		u32 start;
		u32 tail;
		u32 head;
		u32 ctl;
966
		u32 mode;
967 968 969 970 971 972 973 974 975 976 977 978 979
		u32 hws;
		u32 ipeir;
		u32 ipehr;
		u32 bbstate;
		u32 instpm;
		u32 instps;
		u32 seqno;
		u64 bbaddr;
		u64 acthd;
		u32 fault_reg;
		u64 faddr;
		u32 rc_psmi; /* sleep state */
		u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
980
		struct intel_instdone instdone;
981

982 983 984 985 986
		struct drm_i915_error_context {
			char comm[TASK_COMM_LEN];
			pid_t pid;
			u32 handle;
			u32 hw_id;
987
			int priority;
988 989 990 991 992
			int ban_score;
			int active;
			int guilty;
		} context;

993 994
		struct drm_i915_error_object {
			u64 gtt_offset;
995
			u64 gtt_size;
996 997
			int page_count;
			int unused;
998 999 1000
			u32 *pages[0];
		} *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;

1001 1002 1003
		struct drm_i915_error_object **user_bo;
		long user_bo_count;

1004 1005 1006 1007
		struct drm_i915_error_object *wa_ctx;

		struct drm_i915_error_request {
			long jiffies;
1008
			pid_t pid;
1009
			u32 context;
1010
			int priority;
1011
			int ban_score;
1012 1013 1014
			u32 seqno;
			u32 head;
			u32 tail;
1015 1016
		} *requests, execlist[EXECLIST_MAX_PORTS];
		unsigned int num_ports;
1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051

		struct drm_i915_error_waiter {
			char comm[TASK_COMM_LEN];
			pid_t pid;
			u32 seqno;
		} *waiters;

		struct {
			u32 gfx_mode;
			union {
				u64 pdp[4];
				u32 pp_dir_base;
			};
		} vm_info;
	} engine[I915_NUM_ENGINES];

	struct drm_i915_error_buffer {
		u32 size;
		u32 name;
		u32 rseqno[I915_NUM_ENGINES], wseqno;
		u64 gtt_offset;
		u32 read_domains;
		u32 write_domain;
		s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
		u32 tiling:2;
		u32 dirty:1;
		u32 purgeable:1;
		u32 userptr:1;
		s32 engine:4;
		u32 cache_level:3;
	} *active_bo[I915_NUM_ENGINES], *pinned_bo;
	u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
	struct i915_address_space *active_vm[I915_NUM_ENGINES];
};

1052 1053
enum i915_cache_level {
	I915_CACHE_NONE = 0,
1054 1055 1056 1057 1058
	I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
	I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
			      caches, eg sampler/render caches, and the
			      large Last-Level-Cache. LLC is coherent with
			      the CPU, but L3 is only visible to the GPU. */
1059
	I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
1060 1061
};

1062 1063
#define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */

1064 1065 1066 1067 1068
enum fb_op_origin {
	ORIGIN_GTT,
	ORIGIN_CPU,
	ORIGIN_CS,
	ORIGIN_FLIP,
1069
	ORIGIN_DIRTYFB,
1070 1071
};

1072
struct intel_fbc {
P
Paulo Zanoni 已提交
1073 1074 1075
	/* This is always the inner lock when overlapping with struct_mutex and
	 * it's the outer lock when overlapping with stolen_lock. */
	struct mutex lock;
B
Ben Widawsky 已提交
1076
	unsigned threshold;
1077 1078
	unsigned int possible_framebuffer_bits;
	unsigned int busy_bits;
1079
	unsigned int visible_pipes_mask;
1080
	struct intel_crtc *crtc;
1081

1082
	struct drm_mm_node compressed_fb;
1083 1084
	struct drm_mm_node *compressed_llb;

1085 1086
	bool false_color;

1087
	bool enabled;
1088
	bool active;
1089

1090 1091 1092
	bool underrun_detected;
	struct work_struct underrun_work;

1093 1094 1095 1096 1097
	/*
	 * Due to the atomic rules we can't access some structures without the
	 * appropriate locking, so we cache information here in order to avoid
	 * these problems.
	 */
1098
	struct intel_fbc_state_cache {
1099 1100
		struct i915_vma *vma;

1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113
		struct {
			unsigned int mode_flags;
			uint32_t hsw_bdw_pixel_rate;
		} crtc;

		struct {
			unsigned int rotation;
			int src_w;
			int src_h;
			bool visible;
		} plane;

		struct {
1114
			const struct drm_format_info *format;
1115 1116 1117 1118
			unsigned int stride;
		} fb;
	} state_cache;

1119 1120 1121 1122 1123 1124 1125
	/*
	 * This structure contains everything that's relevant to program the
	 * hardware registers. When we want to figure out if we need to disable
	 * and re-enable FBC for a new configuration we just check if there's
	 * something different in the struct. The genx_fbc_activate functions
	 * are supposed to read from it in order to program the registers.
	 */
1126
	struct intel_fbc_reg_params {
1127 1128
		struct i915_vma *vma;

1129 1130 1131 1132 1133 1134 1135
		struct {
			enum pipe pipe;
			enum plane plane;
			unsigned int fence_y_offset;
		} crtc;

		struct {
1136
			const struct drm_format_info *format;
1137 1138 1139 1140
			unsigned int stride;
		} fb;

		int cfb_size;
1141
		unsigned int gen9_wa_cfb_stride;
1142 1143
	} params;

1144
	struct intel_fbc_work {
1145
		bool scheduled;
1146
		u32 scheduled_vblank;
1147 1148
		struct work_struct work;
	} work;
1149

1150
	const char *no_fbc_reason;
1151 1152
};

1153
/*
1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167
 * HIGH_RR is the highest eDP panel refresh rate read from EDID
 * LOW_RR is the lowest eDP panel refresh rate found from EDID
 * parsing for same resolution.
 */
enum drrs_refresh_rate_type {
	DRRS_HIGH_RR,
	DRRS_LOW_RR,
	DRRS_MAX_RR, /* RR count */
};

enum drrs_support_type {
	DRRS_NOT_SUPPORTED = 0,
	STATIC_DRRS_SUPPORT = 1,
	SEAMLESS_DRRS_SUPPORT = 2
1168 1169
};

1170
struct intel_dp;
1171 1172 1173 1174 1175 1176 1177 1178 1179
struct i915_drrs {
	struct mutex mutex;
	struct delayed_work work;
	struct intel_dp *dp;
	unsigned busy_frontbuffer_bits;
	enum drrs_refresh_rate_type refresh_rate_type;
	enum drrs_support_type type;
};

R
Rodrigo Vivi 已提交
1180
struct i915_psr {
1181
	struct mutex lock;
R
Rodrigo Vivi 已提交
1182 1183
	bool sink_support;
	bool source_ok;
1184
	struct intel_dp *enabled;
1185 1186
	bool active;
	struct delayed_work work;
1187
	unsigned busy_frontbuffer_bits;
1188 1189
	bool psr2_support;
	bool aux_frame_sync;
1190
	bool link_standby;
1191 1192
	bool y_cord_support;
	bool colorimetry_support;
1193
	bool alpm;
1194

1195 1196
	void (*enable_source)(struct intel_dp *,
			      const struct intel_crtc_state *);
1197 1198
	void (*disable_source)(struct intel_dp *,
			       const struct intel_crtc_state *);
1199
	void (*enable_sink)(struct intel_dp *);
R
Rodrigo Vivi 已提交
1200
	void (*activate)(struct intel_dp *);
1201
	void (*setup_vsc)(struct intel_dp *, const struct intel_crtc_state *);
1202
};
1203

1204
enum intel_pch {
1205
	PCH_NONE = 0,	/* No PCH present */
1206
	PCH_IBX,	/* Ibexpeak PCH */
1207 1208
	PCH_CPT,	/* Cougarpoint/Pantherpoint PCH */
	PCH_LPT,	/* Lynxpoint/Wildcatpoint PCH */
1209
	PCH_SPT,        /* Sunrisepoint PCH */
1210 1211
	PCH_KBP,        /* Kaby Lake PCH */
	PCH_CNP,        /* Cannon Lake PCH */
B
Ben Widawsky 已提交
1212
	PCH_NOP,
1213 1214
};

1215 1216 1217 1218 1219
enum intel_sbi_destination {
	SBI_ICLK,
	SBI_MPHY,
};

1220
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
1221
#define QUIRK_INVERT_BRIGHTNESS (1<<2)
1222
#define QUIRK_BACKLIGHT_PRESENT (1<<3)
1223
#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1224
#define QUIRK_INCREASE_T12_DELAY (1<<6)
1225

1226
struct intel_fbdev;
1227
struct intel_fbc_work;
1228

1229 1230
struct intel_gmbus {
	struct i2c_adapter adapter;
1231
#define GMBUS_FORCE_BIT_RETRY (1U << 31)
1232
	u32 force_bit;
1233
	u32 reg0;
1234
	i915_reg_t gpio_reg;
1235
	struct i2c_algo_bit_data bit_algo;
1236 1237 1238
	struct drm_i915_private *dev_priv;
};

1239
struct i915_suspend_saved_registers {
1240
	u32 saveDSPARB;
J
Jesse Barnes 已提交
1241
	u32 saveFBC_CONTROL;
1242 1243
	u32 saveCACHE_MODE_0;
	u32 saveMI_ARB_STATE;
J
Jesse Barnes 已提交
1244 1245
	u32 saveSWF0[16];
	u32 saveSWF1[16];
1246
	u32 saveSWF3[3];
1247
	uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1248
	u32 savePCH_PORT_HOTPLUG;
1249
	u16 saveGCDGMBUS;
1250
};
1251

1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309
struct vlv_s0ix_state {
	/* GAM */
	u32 wr_watermark;
	u32 gfx_prio_ctrl;
	u32 arb_mode;
	u32 gfx_pend_tlb0;
	u32 gfx_pend_tlb1;
	u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
	u32 media_max_req_count;
	u32 gfx_max_req_count;
	u32 render_hwsp;
	u32 ecochk;
	u32 bsd_hwsp;
	u32 blt_hwsp;
	u32 tlb_rd_addr;

	/* MBC */
	u32 g3dctl;
	u32 gsckgctl;
	u32 mbctl;

	/* GCP */
	u32 ucgctl1;
	u32 ucgctl3;
	u32 rcgctl1;
	u32 rcgctl2;
	u32 rstctl;
	u32 misccpctl;

	/* GPM */
	u32 gfxpause;
	u32 rpdeuhwtc;
	u32 rpdeuc;
	u32 ecobus;
	u32 pwrdwnupctl;
	u32 rp_down_timeout;
	u32 rp_deucsw;
	u32 rcubmabdtmr;
	u32 rcedata;
	u32 spare2gh;

	/* Display 1 CZ domain */
	u32 gt_imr;
	u32 gt_ier;
	u32 pm_imr;
	u32 pm_ier;
	u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];

	/* GT SA CZ domain */
	u32 tilectl;
	u32 gt_fifoctl;
	u32 gtlc_wake_ctrl;
	u32 gtlc_survive;
	u32 pmwgicz;

	/* Display 2 CZ domain */
	u32 gu_ctl0;
	u32 gu_ctl1;
1310
	u32 pcbr;
1311 1312 1313
	u32 clock_gate_dis2;
};

1314
struct intel_rps_ei {
1315
	ktime_t ktime;
1316 1317
	u32 render_c0;
	u32 media_c0;
1318 1319
};

1320
struct intel_rps {
I
Imre Deak 已提交
1321 1322 1323 1324
	/*
	 * work, interrupts_enabled and pm_iir are protected by
	 * dev_priv->irq_lock
	 */
1325
	struct work_struct work;
I
Imre Deak 已提交
1326
	bool interrupts_enabled;
1327
	u32 pm_iir;
1328

1329
	/* PM interrupt bits that should never be masked */
1330
	u32 pm_intrmsk_mbz;
1331

1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346
	/* Frequencies are stored in potentially platform dependent multiples.
	 * In other words, *_freq needs to be multiplied by X to be interesting.
	 * Soft limits are those which are used for the dynamic reclocking done
	 * by the driver (raise frequencies under heavy loads, and lower for
	 * lighter loads). Hard limits are those imposed by the hardware.
	 *
	 * A distinction is made for overclocking, which is never enabled by
	 * default, and is considered to be above the hard limit if it's
	 * possible at all.
	 */
	u8 cur_freq;		/* Current frequency (cached, may not == HW) */
	u8 min_freq_softlimit;	/* Minimum frequency permitted by the driver */
	u8 max_freq_softlimit;	/* Max frequency permitted by the driver */
	u8 max_freq;		/* Maximum frequency, RP0 if not overclocking */
	u8 min_freq;		/* AKA RPn. Minimum frequency */
1347
	u8 boost_freq;		/* Frequency to request when wait boosting */
1348
	u8 idle_freq;		/* Frequency to request when we are idle */
1349 1350 1351
	u8 efficient_freq;	/* AKA RPe. Pre-determined balanced frequency */
	u8 rp1_freq;		/* "less than" RP0 power/freqency */
	u8 rp0_freq;		/* Non-overclocked max frequency. */
1352
	u16 gpll_ref_freq;	/* vlv/chv GPLL reference frequency */
1353

1354 1355 1356
	u8 up_threshold; /* Current %busy required to uplock */
	u8 down_threshold; /* Current %busy required to downclock */

1357 1358 1359
	int last_adj;
	enum { LOW_POWER, BETWEEN, HIGH_POWER } power;

1360
	bool enabled;
1361 1362
	atomic_t num_waiters;
	atomic_t boosts;
1363

1364
	/* manual wa residency calculations */
1365
	struct intel_rps_ei ei;
1366 1367
};

1368 1369 1370 1371 1372 1373 1374 1375
struct intel_rc6 {
	bool enabled;
};

struct intel_llc_pstate {
	bool enabled;
};

1376 1377
struct intel_gen6_power_mgmt {
	struct intel_rps rps;
1378 1379
	struct intel_rc6 rc6;
	struct intel_llc_pstate llc_pstate;
1380 1381 1382
	struct delayed_work autoenable_work;
};

D
Daniel Vetter 已提交
1383 1384 1385
/* defined intel_pm.c */
extern spinlock_t mchdev_lock;

1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396
struct intel_ilk_power_mgmt {
	u8 cur_delay;
	u8 min_delay;
	u8 max_delay;
	u8 fmax;
	u8 fstart;

	u64 last_count1;
	unsigned long last_time1;
	unsigned long chipset_power;
	u64 last_count2;
1397
	u64 last_time2;
1398 1399 1400 1401 1402 1403 1404
	unsigned long gfx_power;
	u8 corr;

	int c_m;
	int r_t;
};

1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434
struct drm_i915_private;
struct i915_power_well;

struct i915_power_well_ops {
	/*
	 * Synchronize the well's hw state to match the current sw state, for
	 * example enable/disable it based on the current refcount. Called
	 * during driver init and resume time, possibly after first calling
	 * the enable/disable handlers.
	 */
	void (*sync_hw)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/*
	 * Enable the well and resources that depend on it (for example
	 * interrupts located on the well). Called after the 0->1 refcount
	 * transition.
	 */
	void (*enable)(struct drm_i915_private *dev_priv,
		       struct i915_power_well *power_well);
	/*
	 * Disable the well and resources that depend on it. Called after
	 * the 1->0 refcount transition.
	 */
	void (*disable)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/* Returns the hw enabled state. */
	bool (*is_enabled)(struct drm_i915_private *dev_priv,
			   struct i915_power_well *power_well);
};

1435 1436
/* Power well structure for haswell */
struct i915_power_well {
1437
	const char *name;
1438
	bool always_on;
1439 1440
	/* power well enable/disable usage count */
	int count;
1441 1442
	/* cached hw enabled state */
	bool hw_enabled;
1443
	u64 domains;
1444
	/* unique identifier for this power well */
I
Imre Deak 已提交
1445
	enum i915_power_well_id id;
1446 1447 1448 1449
	/*
	 * Arbitraty data associated with this power well. Platform and power
	 * well specific.
	 */
1450 1451 1452 1453
	union {
		struct {
			enum dpio_phy phy;
		} bxt;
1454 1455 1456 1457 1458
		struct {
			/* Mask of pipes whose IRQ logic is backed by the pw */
			u8 irq_pipe_mask;
			/* The pw is backing the VGA functionality */
			bool has_vga:1;
1459
			bool has_fuses:1;
1460
		} hsw;
1461
	};
1462
	const struct i915_power_well_ops *ops;
1463 1464
};

1465
struct i915_power_domains {
1466 1467 1468 1469 1470
	/*
	 * Power wells needed for initialization at driver init and suspend
	 * time are on. They are kept on until after the first modeset.
	 */
	bool init_power_on;
1471
	bool initializing;
1472
	int power_well_count;
1473

1474
	struct mutex lock;
1475
	int domain_use_count[POWER_DOMAIN_NUM];
1476
	struct i915_power_well *power_wells;
1477 1478
};

1479
#define MAX_L3_SLICES 2
1480
struct intel_l3_parity {
1481
	u32 *remap_info[MAX_L3_SLICES];
1482
	struct work_struct error_work;
1483
	int which_slice;
1484 1485
};

1486 1487 1488
struct i915_gem_mm {
	/** Memory allocator for GTT stolen memory */
	struct drm_mm stolen;
1489 1490 1491 1492
	/** Protects the usage of the GTT stolen memory allocator. This is
	 * always the inner lock when overlapping with struct_mutex. */
	struct mutex stolen_lock;

1493 1494 1495
	/* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
	spinlock_t obj_lock;

1496 1497 1498 1499 1500
	/** List of all objects in gtt_space. Used to restore gtt
	 * mappings on resume */
	struct list_head bound_list;
	/**
	 * List of objects which are not bound to the GTT (thus
1501 1502
	 * are idle and not used by the GPU). These objects may or may
	 * not actually have any pages attached.
1503 1504 1505
	 */
	struct list_head unbound_list;

1506 1507 1508 1509 1510
	/** List of all objects in gtt_space, currently mmaped by userspace.
	 * All objects within this list must also be on bound_list.
	 */
	struct list_head userfault_list;

1511 1512 1513 1514 1515
	/**
	 * List of objects which are pending destruction.
	 */
	struct llist_head free_list;
	struct work_struct free_work;
1516
	spinlock_t free_lock;
1517

1518 1519 1520 1521 1522
	/**
	 * Small stash of WC pages
	 */
	struct pagevec wc_stash;

1523
	/** Usable portion of the GTT for GEM */
1524
	dma_addr_t stolen_base; /* limited to low memory (32-bit) */
1525

M
Matthew Auld 已提交
1526 1527 1528 1529 1530
	/**
	 * tmpfs instance used for shmem backed objects
	 */
	struct vfsmount *gemfs;

1531 1532 1533
	/** PPGTT used for aliasing the PPGTT with the GTT */
	struct i915_hw_ppgtt *aliasing_ppgtt;

1534
	struct notifier_block oom_notifier;
1535
	struct notifier_block vmap_notifier;
1536
	struct shrinker shrinker;
1537 1538 1539 1540

	/** LRU list of objects with fence regs on them. */
	struct list_head fence_list;

1541 1542 1543 1544 1545 1546 1547
	/**
	 * Workqueue to fault in userptr pages, flushed by the execbuf
	 * when required but otherwise left to userspace to try again
	 * on EAGAIN.
	 */
	struct workqueue_struct *userptr_wq;

1548 1549
	u64 unordered_timeline;

1550
	/* the indicator for dispatch video commands on two BSD rings */
1551
	atomic_t bsd_engine_dispatch_index;
1552

1553 1554 1555 1556 1557 1558
	/** Bit 6 swizzling required for X tiling */
	uint32_t bit_6_swizzle_x;
	/** Bit 6 swizzling required for Y tiling */
	uint32_t bit_6_swizzle_y;

	/* accounting, useful for userland debugging */
1559
	spinlock_t object_stat_lock;
1560
	u64 object_memory;
1561 1562 1563
	u32 object_count;
};

1564
struct drm_i915_error_state_buf {
1565
	struct drm_i915_private *i915;
1566 1567 1568 1569 1570 1571 1572 1573
	unsigned bytes;
	unsigned size;
	int err;
	u8 *buf;
	loff_t start;
	loff_t pos;
};

1574 1575 1576
#define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
#define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */

1577 1578 1579
#define I915_ENGINE_DEAD_TIMEOUT  (4 * HZ)  /* Seqno, head and subunits dead */
#define I915_SEQNO_DEAD_TIMEOUT   (12 * HZ) /* Seqno dead with active head */

1580 1581 1582 1583
struct i915_gpu_error {
	/* For hangcheck timer */
#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1584

1585
	struct delayed_work hangcheck_work;
1586 1587 1588 1589

	/* For reset and error_state handling. */
	spinlock_t lock;
	/* Protected by the above dev->gpu_error.lock. */
1590
	struct i915_gpu_state *first_error;
1591

1592 1593
	atomic_t pending_fb_pin;

1594 1595
	unsigned long missed_irq_rings;

1596
	/**
M
Mika Kuoppala 已提交
1597
	 * State variable controlling the reset flow and count
1598
	 *
M
Mika Kuoppala 已提交
1599
	 * This is a counter which gets incremented when reset is triggered,
1600
	 *
1601
	 * Before the reset commences, the I915_RESET_BACKOFF bit is set
1602 1603
	 * meaning that any waiters holding onto the struct_mutex should
	 * relinquish the lock immediately in order for the reset to start.
M
Mika Kuoppala 已提交
1604 1605 1606 1607 1608 1609 1610 1611 1612
	 *
	 * If reset is not completed succesfully, the I915_WEDGE bit is
	 * set meaning that hardware is terminally sour and there is no
	 * recovery. All waiters on the reset_queue will be woken when
	 * that happens.
	 *
	 * This counter is used by the wait_seqno code to notice that reset
	 * event happened and it needs to restart the entire ioctl (since most
	 * likely the seqno it waited for won't ever signal anytime soon).
1613 1614 1615 1616
	 *
	 * This is important for lock-free wait paths, where no contended lock
	 * naturally enforces the correct ordering between the bail-out of the
	 * waiter and the gpu reset work code.
1617
	 */
1618
	unsigned long reset_count;
1619

1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638
	/**
	 * flags: Control various stages of the GPU reset
	 *
	 * #I915_RESET_BACKOFF - When we start a reset, we want to stop any
	 * other users acquiring the struct_mutex. To do this we set the
	 * #I915_RESET_BACKOFF bit in the error flags when we detect a reset
	 * and then check for that bit before acquiring the struct_mutex (in
	 * i915_mutex_lock_interruptible()?). I915_RESET_BACKOFF serves a
	 * secondary role in preventing two concurrent global reset attempts.
	 *
	 * #I915_RESET_HANDOFF - To perform the actual GPU reset, we need the
	 * struct_mutex. We try to acquire the struct_mutex in the reset worker,
	 * but it may be held by some long running waiter (that we cannot
	 * interrupt without causing trouble). Once we are ready to do the GPU
	 * reset, we set the I915_RESET_HANDOFF bit and wakeup any waiters. If
	 * they already hold the struct_mutex and want to participate they can
	 * inspect the bit and do the reset directly, otherwise the worker
	 * waits for the struct_mutex.
	 *
1639 1640 1641 1642 1643 1644
	 * #I915_RESET_ENGINE[num_engines] - Since the driver doesn't need to
	 * acquire the struct_mutex to reset an engine, we need an explicit
	 * flag to prevent two concurrent reset attempts in the same engine.
	 * As the number of engines continues to grow, allocate the flags from
	 * the most significant bits.
	 *
1645 1646 1647 1648 1649
	 * #I915_WEDGED - If reset fails and we can no longer use the GPU,
	 * we set the #I915_WEDGED bit. Prior to command submission, e.g.
	 * i915_gem_request_alloc(), this bit is checked and the sequence
	 * aborted (with -EIO reported to userspace) if set.
	 */
1650
	unsigned long flags;
1651 1652
#define I915_RESET_BACKOFF	0
#define I915_RESET_HANDOFF	1
1653
#define I915_RESET_MODESET	2
1654
#define I915_WEDGED		(BITS_PER_LONG - 1)
1655
#define I915_RESET_ENGINE	(I915_WEDGED - I915_NUM_ENGINES)
1656

1657 1658 1659
	/** Number of times an engine has been reset */
	u32 reset_engine_count[I915_NUM_ENGINES];

1660 1661 1662 1663 1664 1665
	/**
	 * Waitqueue to signal when a hang is detected. Used to for waiters
	 * to release the struct_mutex for the reset to procede.
	 */
	wait_queue_head_t wait_queue;

1666 1667 1668 1669 1670
	/**
	 * Waitqueue to signal when the reset has completed. Used by clients
	 * that wait for dev_priv->mm.wedged to settle.
	 */
	wait_queue_head_t reset_queue;
1671

1672
	/* For missed irq/seqno simulation. */
1673
	unsigned long test_irq_rings;
1674 1675
};

1676 1677 1678 1679 1680 1681
enum modeset_restore {
	MODESET_ON_LID_OPEN,
	MODESET_DONE,
	MODESET_SUSPENDED,
};

1682 1683 1684 1685 1686
#define DP_AUX_A 0x40
#define DP_AUX_B 0x10
#define DP_AUX_C 0x20
#define DP_AUX_D 0x30

X
Xiong Zhang 已提交
1687 1688 1689 1690
#define DDC_PIN_B  0x05
#define DDC_PIN_C  0x04
#define DDC_PIN_D  0x06

1691
struct ddi_vbt_port_info {
1692 1693 1694 1695 1696 1697
	/*
	 * This is an index in the HDMI/DVI DDI buffer translation table.
	 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
	 * populate this field.
	 */
#define HDMI_LEVEL_SHIFT_UNKNOWN	0xff
1698
	uint8_t hdmi_level_shift;
1699 1700 1701 1702

	uint8_t supports_dvi:1;
	uint8_t supports_hdmi:1;
	uint8_t supports_dp:1;
1703
	uint8_t supports_edp:1;
1704 1705

	uint8_t alternate_aux_channel;
X
Xiong Zhang 已提交
1706
	uint8_t alternate_ddc_pin;
1707 1708 1709

	uint8_t dp_boost_level;
	uint8_t hdmi_boost_level;
1710 1711
};

R
Rodrigo Vivi 已提交
1712 1713 1714 1715 1716
enum psr_lines_to_wait {
	PSR_0_LINES_TO_WAIT = 0,
	PSR_1_LINE_TO_WAIT,
	PSR_4_LINES_TO_WAIT,
	PSR_8_LINES_TO_WAIT
1717 1718
};

1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730
struct intel_vbt_data {
	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */

	/* Feature bits */
	unsigned int int_tv_support:1;
	unsigned int lvds_dither:1;
	unsigned int lvds_vbt:1;
	unsigned int int_crt_support:1;
	unsigned int lvds_use_ssc:1;
	unsigned int display_clock_mode:1;
	unsigned int fdi_rx_polarity_inverted:1;
1731
	unsigned int panel_type:4;
1732 1733 1734
	int lvds_ssc_freq;
	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */

1735 1736
	enum drrs_support_type drrs_type;

1737 1738 1739 1740 1741
	struct {
		int rate;
		int lanes;
		int preemphasis;
		int vswing;
1742
		bool low_vswing;
1743 1744 1745 1746 1747
		bool initialized;
		bool support;
		int bpp;
		struct edp_power_seq pps;
	} edp;
1748

R
Rodrigo Vivi 已提交
1749 1750 1751 1752 1753 1754 1755 1756 1757
	struct {
		bool full_link;
		bool require_aux_wakeup;
		int idle_frames;
		enum psr_lines_to_wait lines_to_wait;
		int tp1_wakeup_time;
		int tp2_tp3_wakeup_time;
	} psr;

1758 1759
	struct {
		u16 pwm_freq_hz;
1760
		bool present;
1761
		bool active_low_pwm;
1762
		u8 min_brightness;	/* min_brightness/255 of max */
1763
		u8 controller;		/* brightness controller number */
1764
		enum intel_backlight_type type;
1765 1766
	} backlight;

1767 1768 1769
	/* MIPI DSI */
	struct {
		u16 panel_id;
1770 1771 1772 1773 1774
		struct mipi_config *config;
		struct mipi_pps_data *pps;
		u8 seq_version;
		u32 size;
		u8 *data;
1775
		const u8 *sequence[MIPI_SEQ_MAX];
1776 1777
	} dsi;

1778 1779 1780
	int crt_ddc_pin;

	int child_dev_num;
1781
	struct child_device_config *child_dev;
1782 1783

	struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1784
	struct sdvo_device_mapping sdvo_mappings[2];
1785 1786
};

1787 1788 1789 1790 1791
enum intel_ddb_partitioning {
	INTEL_DDB_PART_1_2,
	INTEL_DDB_PART_5_6, /* IVB+ */
};

1792 1793 1794 1795 1796 1797 1798 1799
struct intel_wm_level {
	bool enable;
	uint32_t pri_val;
	uint32_t spr_val;
	uint32_t cur_val;
	uint32_t fbc_val;
};

1800
struct ilk_wm_values {
1801 1802 1803 1804 1805 1806 1807 1808
	uint32_t wm_pipe[3];
	uint32_t wm_lp[3];
	uint32_t wm_lp_spr[3];
	uint32_t wm_linetime[3];
	bool enable_fbc_wm;
	enum intel_ddb_partitioning partitioning;
};

1809
struct g4x_pipe_wm {
1810
	uint16_t plane[I915_MAX_PLANES];
1811
	uint16_t fbc;
1812
};
1813

1814
struct g4x_sr_wm {
1815
	uint16_t plane;
1816
	uint16_t cursor;
1817
	uint16_t fbc;
1818 1819 1820 1821
};

struct vlv_wm_ddl_values {
	uint8_t plane[I915_MAX_PLANES];
1822
};
1823

1824
struct vlv_wm_values {
1825 1826
	struct g4x_pipe_wm pipe[3];
	struct g4x_sr_wm sr;
1827
	struct vlv_wm_ddl_values ddl[3];
1828 1829
	uint8_t level;
	bool cxsr;
1830 1831
};

1832 1833 1834 1835 1836 1837 1838 1839 1840
struct g4x_wm_values {
	struct g4x_pipe_wm pipe[2];
	struct g4x_sr_wm sr;
	struct g4x_sr_wm hpll;
	bool cxsr;
	bool hpll_en;
	bool fbc_en;
};

1841
struct skl_ddb_entry {
1842
	uint16_t start, end;	/* in number of blocks, 'end' is exclusive */
1843 1844 1845 1846
};

static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
{
1847
	return entry->end - entry->start;
1848 1849
}

1850 1851 1852 1853 1854 1855 1856 1857 1858
static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
				       const struct skl_ddb_entry *e2)
{
	if (e1->start == e2->start && e1->end == e2->end)
		return true;

	return false;
}

1859
struct skl_ddb_allocation {
1860
	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1861
	struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1862 1863
};

1864
struct skl_wm_values {
1865
	unsigned dirty_pipes;
1866
	struct skl_ddb_allocation ddb;
1867 1868 1869
};

struct skl_wm_level {
L
Lyude 已提交
1870 1871 1872
	bool plane_en;
	uint16_t plane_res_b;
	uint8_t plane_res_l;
1873 1874
};

1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888
/* Stores plane specific WM parameters */
struct skl_wm_params {
	bool x_tiled, y_tiled;
	bool rc_surface;
	uint32_t width;
	uint8_t cpp;
	uint32_t plane_pixel_rate;
	uint32_t y_min_scanlines;
	uint32_t plane_bytes_per_line;
	uint_fixed_16_16_t plane_blocks_per_line;
	uint_fixed_16_16_t y_tile_minimum;
	uint32_t linetime_us;
};

1889
/*
1890 1891 1892 1893
 * This struct helps tracking the state needed for runtime PM, which puts the
 * device in PCI D3 state. Notice that when this happens, nothing on the
 * graphics device works, even register access, so we don't get interrupts nor
 * anything else.
1894
 *
1895 1896 1897
 * Every piece of our code that needs to actually touch the hardware needs to
 * either call intel_runtime_pm_get or call intel_display_power_get with the
 * appropriate power domain.
1898
 *
1899 1900
 * Our driver uses the autosuspend delay feature, which means we'll only really
 * suspend if we stay with zero refcount for a certain amount of time. The
1901
 * default value is currently very conservative (see intel_runtime_pm_enable), but
1902
 * it can be changed with the standard runtime PM files from sysfs.
1903 1904 1905 1906 1907
 *
 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
 * goes back to false exactly before we reenable the IRQs. We use this variable
 * to check if someone is trying to enable/disable IRQs while they're supposed
 * to be disabled. This shouldn't happen and we'll print some error messages in
1908
 * case it happens.
1909
 *
1910
 * For more, read the Documentation/power/runtime_pm.txt.
1911
 */
1912
struct i915_runtime_pm {
1913
	atomic_t wakeref_count;
1914
	bool suspended;
1915
	bool irqs_enabled;
1916 1917
};

1918 1919 1920 1921 1922
enum intel_pipe_crc_source {
	INTEL_PIPE_CRC_SOURCE_NONE,
	INTEL_PIPE_CRC_SOURCE_PLANE1,
	INTEL_PIPE_CRC_SOURCE_PLANE2,
	INTEL_PIPE_CRC_SOURCE_PF,
1923
	INTEL_PIPE_CRC_SOURCE_PIPE,
D
Daniel Vetter 已提交
1924 1925 1926 1927 1928
	/* TV/DP on pre-gen5/vlv can't use the pipe source. */
	INTEL_PIPE_CRC_SOURCE_TV,
	INTEL_PIPE_CRC_SOURCE_DP_B,
	INTEL_PIPE_CRC_SOURCE_DP_C,
	INTEL_PIPE_CRC_SOURCE_DP_D,
1929
	INTEL_PIPE_CRC_SOURCE_AUTO,
1930 1931 1932
	INTEL_PIPE_CRC_SOURCE_MAX,
};

1933
struct intel_pipe_crc_entry {
1934
	uint32_t frame;
1935 1936 1937
	uint32_t crc[5];
};

1938
#define INTEL_PIPE_CRC_ENTRIES_NR	128
1939
struct intel_pipe_crc {
1940 1941
	spinlock_t lock;
	bool opened;		/* exclusive access to the result file */
1942
	struct intel_pipe_crc_entry *entries;
1943
	enum intel_pipe_crc_source source;
1944
	int head, tail;
1945
	wait_queue_head_t wq;
T
Tomeu Vizoso 已提交
1946
	int skipped;
1947 1948
};

1949
struct i915_frontbuffer_tracking {
1950
	spinlock_t lock;
1951 1952 1953 1954 1955 1956 1957 1958 1959

	/*
	 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
	 * scheduled flips.
	 */
	unsigned busy_bits;
	unsigned flip_bits;
};

1960
struct i915_wa_reg {
1961
	i915_reg_t addr;
1962 1963 1964 1965 1966
	u32 value;
	/* bitmask representing WA bits */
	u32 mask;
};

1967
#define I915_MAX_WA_REGS 16
1968 1969 1970 1971

struct i915_workarounds {
	struct i915_wa_reg reg[I915_MAX_WA_REGS];
	u32 count;
1972
	u32 hw_whitelist_count[I915_NUM_ENGINES];
1973 1974
};

1975 1976
struct i915_virtual_gpu {
	bool active;
1977
	u32 caps;
1978 1979
};

1980 1981 1982 1983 1984 1985 1986
/* used in computing the new watermarks state */
struct intel_wm_config {
	unsigned int num_pipes_active;
	bool sprites_enabled;
	bool sprites_scaled;
};

1987 1988 1989 1990 1991
struct i915_oa_format {
	u32 format;
	int size;
};

1992 1993 1994 1995 1996
struct i915_oa_reg {
	i915_reg_t addr;
	u32 value;
};

1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010
struct i915_oa_config {
	char uuid[UUID_STRING_LEN + 1];
	int id;

	const struct i915_oa_reg *mux_regs;
	u32 mux_regs_len;
	const struct i915_oa_reg *b_counter_regs;
	u32 b_counter_regs_len;
	const struct i915_oa_reg *flex_regs;
	u32 flex_regs_len;

	struct attribute_group sysfs_metric;
	struct attribute *attrs[2];
	struct device_attribute sysfs_metric_id;
2011 2012

	atomic_t ref_count;
2013 2014
};

2015 2016
struct i915_perf_stream;

2017 2018 2019
/**
 * struct i915_perf_stream_ops - the OPs to support a specific stream type
 */
2020
struct i915_perf_stream_ops {
2021 2022 2023 2024
	/**
	 * @enable: Enables the collection of HW samples, either in response to
	 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
	 * without `I915_PERF_FLAG_DISABLED`.
2025 2026 2027
	 */
	void (*enable)(struct i915_perf_stream *stream);

2028 2029 2030 2031
	/**
	 * @disable: Disables the collection of HW samples, either in response
	 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
	 * the stream.
2032 2033 2034
	 */
	void (*disable)(struct i915_perf_stream *stream);

2035 2036
	/**
	 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
2037 2038 2039 2040 2041 2042
	 * once there is something ready to read() for the stream
	 */
	void (*poll_wait)(struct i915_perf_stream *stream,
			  struct file *file,
			  poll_table *wait);

2043 2044 2045
	/**
	 * @wait_unlocked: For handling a blocking read, wait until there is
	 * something to ready to read() for the stream. E.g. wait on the same
2046
	 * wait queue that would be passed to poll_wait().
2047 2048 2049
	 */
	int (*wait_unlocked)(struct i915_perf_stream *stream);

2050 2051 2052 2053 2054 2055 2056
	/**
	 * @read: Copy buffered metrics as records to userspace
	 * **buf**: the userspace, destination buffer
	 * **count**: the number of bytes to copy, requested by userspace
	 * **offset**: zero at the start of the read, updated as the read
	 * proceeds, it represents how many bytes have been copied so far and
	 * the buffer offset for copying the next record.
2057
	 *
2058 2059
	 * Copy as many buffered i915 perf samples and records for this stream
	 * to userspace as will fit in the given buffer.
2060
	 *
2061 2062
	 * Only write complete records; returning -%ENOSPC if there isn't room
	 * for a complete record.
2063
	 *
2064 2065 2066
	 * Return any error condition that results in a short read such as
	 * -%ENOSPC or -%EFAULT, even though these may be squashed before
	 * returning to userspace.
2067 2068 2069 2070 2071 2072
	 */
	int (*read)(struct i915_perf_stream *stream,
		    char __user *buf,
		    size_t count,
		    size_t *offset);

2073 2074
	/**
	 * @destroy: Cleanup any stream specific resources.
2075 2076 2077 2078 2079 2080
	 *
	 * The stream will always be disabled before this is called.
	 */
	void (*destroy)(struct i915_perf_stream *stream);
};

2081 2082 2083
/**
 * struct i915_perf_stream - state for a single open stream FD
 */
2084
struct i915_perf_stream {
2085 2086 2087
	/**
	 * @dev_priv: i915 drm device
	 */
2088 2089
	struct drm_i915_private *dev_priv;

2090 2091 2092
	/**
	 * @link: Links the stream into ``&drm_i915_private->streams``
	 */
2093 2094
	struct list_head link;

2095 2096 2097 2098 2099
	/**
	 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
	 * properties given when opening a stream, representing the contents
	 * of a single sample as read() by userspace.
	 */
2100
	u32 sample_flags;
2101 2102 2103 2104 2105 2106

	/**
	 * @sample_size: Considering the configured contents of a sample
	 * combined with the required header size, this is the total size
	 * of a single sample record.
	 */
2107
	int sample_size;
2108

2109 2110 2111 2112
	/**
	 * @ctx: %NULL if measuring system-wide across all contexts or a
	 * specific context that is being monitored.
	 */
2113
	struct i915_gem_context *ctx;
2114 2115 2116 2117 2118 2119

	/**
	 * @enabled: Whether the stream is currently enabled, considering
	 * whether the stream was opened in a disabled state and based
	 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
	 */
2120 2121
	bool enabled;

2122 2123 2124 2125
	/**
	 * @ops: The callbacks providing the implementation of this specific
	 * type of configured stream.
	 */
2126
	const struct i915_perf_stream_ops *ops;
2127 2128 2129 2130 2131

	/**
	 * @oa_config: The OA configuration used by the stream.
	 */
	struct i915_oa_config *oa_config;
2132 2133
};

2134 2135 2136
/**
 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
 */
2137
struct i915_oa_ops {
2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156
	/**
	 * @is_valid_b_counter_reg: Validates register's address for
	 * programming boolean counters for a particular platform.
	 */
	bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv,
				       u32 addr);

	/**
	 * @is_valid_mux_reg: Validates register's address for programming mux
	 * for a particular platform.
	 */
	bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr);

	/**
	 * @is_valid_flex_reg: Validates register's address for programming
	 * flex EU filtering for a particular platform.
	 */
	bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr);

2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171
	/**
	 * @init_oa_buffer: Resets the head and tail pointers of the
	 * circular buffer for periodic OA reports.
	 *
	 * Called when first opening a stream for OA metrics, but also may be
	 * called in response to an OA buffer overflow or other error
	 * condition.
	 *
	 * Note it may be necessary to clear the full OA buffer here as part of
	 * maintaining the invariable that new reports must be written to
	 * zeroed memory for us to be able to reliable detect if an expected
	 * report has not yet landed in memory.  (At least on Haswell the OA
	 * buffer tail pointer is not synchronized with reports being visible
	 * to the CPU)
	 */
2172
	void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
2173

2174 2175 2176 2177
	/**
	 * @enable_metric_set: Selects and applies any MUX configuration to set
	 * up the Boolean and Custom (B/C) counters that are part of the
	 * counter reports being sampled. May apply system constraints such as
2178 2179
	 * disabling EU clock gating as required.
	 */
2180 2181
	int (*enable_metric_set)(struct drm_i915_private *dev_priv,
				 const struct i915_oa_config *oa_config);
2182 2183 2184 2185 2186

	/**
	 * @disable_metric_set: Remove system constraints associated with using
	 * the OA unit.
	 */
2187
	void (*disable_metric_set)(struct drm_i915_private *dev_priv);
2188 2189 2190 2191

	/**
	 * @oa_enable: Enable periodic sampling
	 */
2192
	void (*oa_enable)(struct drm_i915_private *dev_priv);
2193 2194 2195 2196

	/**
	 * @oa_disable: Disable periodic sampling
	 */
2197
	void (*oa_disable)(struct drm_i915_private *dev_priv);
2198 2199 2200 2201 2202

	/**
	 * @read: Copy data from the circular OA buffer into a given userspace
	 * buffer.
	 */
2203 2204 2205 2206
	int (*read)(struct i915_perf_stream *stream,
		    char __user *buf,
		    size_t count,
		    size_t *offset);
2207 2208

	/**
2209
	 * @oa_hw_tail_read: read the OA tail pointer register
2210
	 *
2211 2212 2213
	 * In particular this enables us to share all the fiddly code for
	 * handling the OA unit tail pointer race that affects multiple
	 * generations.
2214
	 */
2215
	u32 (*oa_hw_tail_read)(struct drm_i915_private *dev_priv);
2216 2217
};

2218 2219 2220 2221
struct intel_cdclk_state {
	unsigned int cdclk, vco, ref;
};

2222
struct drm_i915_private {
2223 2224
	struct drm_device drm;

2225
	struct kmem_cache *objects;
2226
	struct kmem_cache *vmas;
2227
	struct kmem_cache *luts;
2228
	struct kmem_cache *requests;
2229
	struct kmem_cache *dependencies;
2230
	struct kmem_cache *priorities;
2231

2232
	const struct intel_device_info info;
2233 2234 2235

	void __iomem *regs;

2236
	struct intel_uncore uncore;
2237

2238 2239
	struct i915_virtual_gpu vgpu;

2240
	struct intel_gvt *gvt;
2241

2242
	struct intel_huc huc;
2243 2244
	struct intel_guc guc;

2245 2246
	struct intel_csr csr;

2247
	struct intel_gmbus gmbus[GMBUS_NUM_PINS];
2248

2249 2250 2251 2252 2253 2254 2255 2256 2257
	/** gmbus_mutex protects against concurrent usage of the single hw gmbus
	 * controller on different i2c buses. */
	struct mutex gmbus_mutex;

	/**
	 * Base address of the gmbus and gpio block.
	 */
	uint32_t gpio_mmio_base;

2258 2259 2260
	/* MMIO base address for MIPI regs */
	uint32_t mipi_mmio_base;

2261 2262
	uint32_t psr_mmio_base;

2263 2264
	uint32_t pps_mmio_base;

2265 2266
	wait_queue_head_t gmbus_wait_queue;

2267
	struct pci_dev *bridge_dev;
2268
	struct intel_engine_cs *engine[I915_NUM_ENGINES];
2269 2270 2271 2272
	/* Context used internally to idle the GPU and setup initial state */
	struct i915_gem_context *kernel_context;
	/* Context only to be used for injecting preemption commands */
	struct i915_gem_context *preempt_context;
2273
	struct i915_vma *semaphore;
2274

2275
	struct drm_dma_handle *status_page_dmah;
2276 2277 2278 2279 2280
	struct resource mch_res;

	/* protects the irq masks */
	spinlock_t irq_lock;

2281 2282
	bool display_irqs_enabled;

2283 2284 2285
	/* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
	struct pm_qos_request pm_qos;

V
Ville Syrjälä 已提交
2286 2287
	/* Sideband mailbox protection */
	struct mutex sb_lock;
2288 2289

	/** Cached value of IMR to avoid reads in updating the bitfield */
2290 2291 2292 2293
	union {
		u32 irq_mask;
		u32 de_irq_mask[I915_MAX_PIPES];
	};
2294
	u32 gt_irq_mask;
2295 2296
	u32 pm_imr;
	u32 pm_ier;
2297
	u32 pm_rps_events;
2298
	u32 pm_guc_events;
2299
	u32 pipestat_irq_mask[I915_MAX_PIPES];
2300

2301
	struct i915_hotplug hotplug;
2302
	struct intel_fbc fbc;
2303
	struct i915_drrs drrs;
2304
	struct intel_opregion opregion;
2305
	struct intel_vbt_data vbt;
2306

2307 2308
	bool preserve_bios_swizzle;

2309 2310 2311
	/* overlay */
	struct intel_overlay *overlay;

2312
	/* backlight registers and fields in struct intel_panel */
2313
	struct mutex backlight_lock;
2314

2315 2316 2317
	/* LVDS info */
	bool no_aux_handshake;

V
Ville Syrjälä 已提交
2318 2319 2320
	/* protects panel power sequencer state */
	struct mutex pps_mutex;

2321 2322 2323 2324
	struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
	int num_fence_regs; /* 8 on pre-965, 16 otherwise */

	unsigned int fsb_freq, mem_freq, is_ddr3;
2325
	unsigned int skl_preferred_vco_freq;
2326
	unsigned int max_cdclk_freq;
2327

M
Mika Kahola 已提交
2328
	unsigned int max_dotclk_freq;
2329
	unsigned int rawclk_freq;
2330
	unsigned int hpll_freq;
2331
	unsigned int czclk_freq;
2332

2333
	struct {
2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347
		/*
		 * The current logical cdclk state.
		 * See intel_atomic_state.cdclk.logical
		 *
		 * For reading holding any crtc lock is sufficient,
		 * for writing must hold all of them.
		 */
		struct intel_cdclk_state logical;
		/*
		 * The current actual cdclk state.
		 * See intel_atomic_state.cdclk.actual
		 */
		struct intel_cdclk_state actual;
		/* The current hardware cdclk state */
2348 2349
		struct intel_cdclk_state hw;
	} cdclk;
2350

2351 2352 2353 2354 2355 2356 2357
	/**
	 * wq - Driver workqueue for GEM.
	 *
	 * NOTE: Work items scheduled here are not allowed to grab any modeset
	 * locks, for otherwise the flushing done in the pageflip code will
	 * result in deadlocks.
	 */
2358 2359 2360 2361 2362 2363 2364
	struct workqueue_struct *wq;

	/* Display functions */
	struct drm_i915_display_funcs display;

	/* PCH chipset type */
	enum intel_pch pch_type;
2365
	unsigned short pch_id;
2366 2367 2368

	unsigned long quirks;

2369 2370
	enum modeset_restore modeset_restore;
	struct mutex modeset_restore_lock;
2371
	struct drm_atomic_state *modeset_restore_state;
2372
	struct drm_modeset_acquire_ctx reset_ctx;
2373

2374
	struct list_head vm_list; /* Global list of all address spaces */
2375
	struct i915_ggtt ggtt; /* VM representing the global address space */
B
Ben Widawsky 已提交
2376

2377
	struct i915_gem_mm mm;
2378 2379
	DECLARE_HASHTABLE(mm_structs, 7);
	struct mutex mm_lock;
2380

2381 2382
	struct intel_ppat ppat;

2383 2384
	/* Kernel Modesetting */

2385 2386
	struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
	struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
2387

2388 2389 2390 2391
#ifdef CONFIG_DEBUG_FS
	struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
#endif

2392
	/* dpll and cdclk state is protected by connection_mutex */
D
Daniel Vetter 已提交
2393 2394
	int num_shared_dpll;
	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
2395
	const struct intel_dpll_mgr *dpll_mgr;
2396

2397 2398 2399 2400 2401 2402 2403
	/*
	 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
	 * Must be global rather than per dpll, because on some platforms
	 * plls share registers.
	 */
	struct mutex dpll_lock;

2404
	unsigned int active_crtcs;
2405 2406
	/* minimum acceptable cdclk for each pipe */
	int min_cdclk[I915_MAX_PIPES];
2407

2408
	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
2409

2410
	struct i915_workarounds workarounds;
2411

2412 2413
	struct i915_frontbuffer_tracking fb_tracking;

2414 2415 2416 2417 2418
	struct intel_atomic_helper {
		struct llist_head free_list;
		struct work_struct free_work;
	} atomic_helper;

2419
	u16 orig_clock;
2420

2421
	bool mchbar_need_disable;
2422

2423 2424
	struct intel_l3_parity l3_parity;

B
Ben Widawsky 已提交
2425
	/* Cannot be determined by PCIID. You must always read a register. */
2426
	u32 edram_cap;
B
Ben Widawsky 已提交
2427

2428 2429 2430 2431 2432 2433 2434 2435
	/*
	 * Protects RPS/RC6 register access and PCU communication.
	 * Must be taken after struct_mutex if nested. Note that
	 * this lock may be held for long periods of time when
	 * talking to hw - so only take it when talking to hw!
	 */
	struct mutex pcu_lock;

2436 2437
	/* gen6+ GT PM state */
	struct intel_gen6_power_mgmt gt_pm;
2438

2439 2440
	/* ilk-only ips/rps state. Everything in here is protected by the global
	 * mchdev_lock in intel_pm.c */
2441
	struct intel_ilk_power_mgmt ips;
2442

2443
	struct i915_power_domains power_domains;
2444

R
Rodrigo Vivi 已提交
2445
	struct i915_psr psr;
2446

2447
	struct i915_gpu_error gpu_error;
2448

2449 2450
	struct drm_i915_gem_object *vlv_pctx;

2451 2452
	/* list of fbdev register on this device */
	struct intel_fbdev *fbdev;
2453
	struct work_struct fbdev_suspend_work;
2454 2455

	struct drm_property *broadcast_rgb_property;
2456
	struct drm_property *force_audio_property;
2457

I
Imre Deak 已提交
2458
	/* hda/i915 audio component */
2459
	struct i915_audio_component *audio_component;
I
Imre Deak 已提交
2460
	bool audio_component_registered;
2461 2462 2463 2464 2465
	/**
	 * av_mutex - mutex for audio/video sync
	 *
	 */
	struct mutex av_mutex;
I
Imre Deak 已提交
2466

2467 2468
	struct {
		struct list_head list;
2469 2470
		struct llist_head free_list;
		struct work_struct free_work;
2471 2472 2473 2474 2475 2476 2477 2478

		/* The hw wants to have a stable context identifier for the
		 * lifetime of the context (for OA, PASID, faults, etc).
		 * This is limited in execlists to 21 bits.
		 */
		struct ida hw_ida;
#define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
	} contexts;
2479

2480
	u32 fdi_rx_config;
2481

2482
	/* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2483
	u32 chv_phy_control;
2484 2485 2486 2487 2488 2489
	/*
	 * Shadows for CHV DPLL_MD regs to keep the state
	 * checker somewhat working in the presence hardware
	 * crappiness (can't read out DPLL_MD for pipes B & C).
	 */
	u32 chv_dpll_md[I915_MAX_PIPES];
2490
	u32 bxt_phy_grc;
2491

2492
	u32 suspend_count;
2493
	bool suspended_to_idle;
2494
	struct i915_suspend_saved_registers regfile;
2495
	struct vlv_s0ix_state vlv_s0ix_state;
2496

2497
	enum {
2498 2499 2500 2501 2502
		I915_SAGV_UNKNOWN = 0,
		I915_SAGV_DISABLED,
		I915_SAGV_ENABLED,
		I915_SAGV_NOT_CONTROLLED
	} sagv_status;
2503

2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515
	struct {
		/*
		 * Raw watermark latency values:
		 * in 0.1us units for WM0,
		 * in 0.5us units for WM1+.
		 */
		/* primary */
		uint16_t pri_latency[5];
		/* sprite */
		uint16_t spr_latency[5];
		/* cursor */
		uint16_t cur_latency[5];
2516 2517 2518 2519 2520 2521
		/*
		 * Raw watermark memory latency values
		 * for SKL for all 8 levels
		 * in 1us units.
		 */
		uint16_t skl_latency[8];
2522 2523

		/* current hardware state */
2524 2525 2526
		union {
			struct ilk_wm_values hw;
			struct skl_wm_values skl_hw;
2527
			struct vlv_wm_values vlv;
2528
			struct g4x_wm_values g4x;
2529
		};
2530 2531

		uint8_t max_level;
2532 2533 2534 2535 2536 2537 2538

		/*
		 * Should be held around atomic WM register writing; also
		 * protects * intel_crtc->wm.active and
		 * cstate->wm.need_postvbl_update.
		 */
		struct mutex wm_mutex;
2539 2540 2541 2542 2543 2544 2545

		/*
		 * Set during HW readout of watermarks/DDB.  Some platforms
		 * need to know when we're still using BIOS-provided values
		 * (which we don't fully trust).
		 */
		bool distrust_bios_wm;
2546 2547
	} wm;

2548
	struct i915_runtime_pm runtime_pm;
2549

2550 2551
	struct {
		bool initialized;
2552

2553
		struct kobject *metrics_kobj;
2554
		struct ctl_table_header *sysctl_header;
2555

2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571
		/*
		 * Lock associated with adding/modifying/removing OA configs
		 * in dev_priv->perf.metrics_idr.
		 */
		struct mutex metrics_lock;

		/*
		 * List of dynamic configurations, you need to hold
		 * dev_priv->perf.metrics_lock to access it.
		 */
		struct idr metrics_idr;

		/*
		 * Lock associated with anything below within this structure
		 * except exclusive_stream.
		 */
2572 2573
		struct mutex lock;
		struct list_head streams;
2574 2575

		struct {
2576 2577 2578 2579 2580 2581
			/*
			 * The stream currently using the OA unit. If accessed
			 * outside a syscall associated to its file
			 * descriptor, you need to hold
			 * dev_priv->drm.struct_mutex.
			 */
2582 2583 2584 2585 2586 2587 2588 2589
			struct i915_perf_stream *exclusive_stream;

			u32 specific_ctx_id;

			struct hrtimer poll_check_timer;
			wait_queue_head_t poll_wq;
			bool pollin;

2590 2591 2592 2593 2594 2595
			/**
			 * For rate limiting any notifications of spurious
			 * invalid OA reports
			 */
			struct ratelimit_state spurious_report_rs;

2596 2597
			bool periodic;
			int period_exponent;
2598
			int timestamp_frequency;
2599

2600
			struct i915_oa_config test_config;
2601 2602 2603 2604

			struct {
				struct i915_vma *vma;
				u8 *vaddr;
2605
				u32 last_ctx_id;
2606 2607
				int format;
				int format_size;
2608

2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661
				/**
				 * Locks reads and writes to all head/tail state
				 *
				 * Consider: the head and tail pointer state
				 * needs to be read consistently from a hrtimer
				 * callback (atomic context) and read() fop
				 * (user context) with tail pointer updates
				 * happening in atomic context and head updates
				 * in user context and the (unlikely)
				 * possibility of read() errors needing to
				 * reset all head/tail state.
				 *
				 * Note: Contention or performance aren't
				 * currently a significant concern here
				 * considering the relatively low frequency of
				 * hrtimer callbacks (5ms period) and that
				 * reads typically only happen in response to a
				 * hrtimer event and likely complete before the
				 * next callback.
				 *
				 * Note: This lock is not held *while* reading
				 * and copying data to userspace so the value
				 * of head observed in htrimer callbacks won't
				 * represent any partial consumption of data.
				 */
				spinlock_t ptr_lock;

				/**
				 * One 'aging' tail pointer and one 'aged'
				 * tail pointer ready to used for reading.
				 *
				 * Initial values of 0xffffffff are invalid
				 * and imply that an update is required
				 * (and should be ignored by an attempted
				 * read)
				 */
				struct {
					u32 offset;
				} tails[2];

				/**
				 * Index for the aged tail ready to read()
				 * data up to.
				 */
				unsigned int aged_tail_idx;

				/**
				 * A monotonic timestamp for when the current
				 * aging tail pointer was read; used to
				 * determine when it is old enough to trust.
				 */
				u64 aging_timestamp;

2662 2663 2664 2665 2666 2667 2668 2669 2670 2671
				/**
				 * Although we can always read back the head
				 * pointer register, we prefer to avoid
				 * trusting the HW state, just to avoid any
				 * risk that some hardware condition could
				 * somehow bump the head pointer unpredictably
				 * and cause us to forward the wrong OA buffer
				 * data to userspace.
				 */
				u32 head;
2672 2673 2674
			} oa_buffer;

			u32 gen7_latched_oastatus1;
2675 2676 2677 2678 2679 2680 2681 2682 2683
			u32 ctx_oactxctrl_offset;
			u32 ctx_flexeu0_offset;

			/**
			 * The RPT_ID/reason field for Gen8+ includes a bit
			 * to determine if the CTX ID in the report is valid
			 * but the specific bit differs between Gen 8 and 9
			 */
			u32 gen8_valid_ctx_bit;
2684 2685 2686

			struct i915_oa_ops ops;
			const struct i915_oa_format *oa_formats;
2687
		} oa;
2688 2689
	} perf;

2690 2691
	/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
	struct {
2692
		void (*resume)(struct drm_i915_private *);
2693
		void (*cleanup_engine)(struct intel_engine_cs *engine);
2694

2695 2696
		struct list_head timelines;
		struct i915_gem_timeline global_timeline;
2697
		u32 active_requests;
2698

2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724
		/**
		 * Is the GPU currently considered idle, or busy executing
		 * userspace requests? Whilst idle, we allow runtime power
		 * management to power down the hardware and display clocks.
		 * In order to reduce the effect on performance, there
		 * is a slight delay before we do so.
		 */
		bool awake;

		/**
		 * We leave the user IRQ off as much as possible,
		 * but this means that requests will finish and never
		 * be retired once the system goes idle. Set a timer to
		 * fire periodically while the ring is running. When it
		 * fires, go retire requests.
		 */
		struct delayed_work retire_work;

		/**
		 * When we detect an idle GPU, we want to turn on
		 * powersaving features. So once we see that there
		 * are no more requests outstanding and no more
		 * arrive within a small period of time, we fire
		 * off the idle_work.
		 */
		struct delayed_work idle_work;
2725 2726

		ktime_t last_init_time;
2727 2728
	} gt;

2729 2730 2731
	/* perform PHY state sanity checks? */
	bool chv_phy_assert[2];

M
Mahesh Kumar 已提交
2732 2733
	bool ipc_enabled;

2734 2735
	/* Used to save the pipe-to-encoder mapping for audio */
	struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2736

2737 2738 2739 2740 2741 2742
	/* necessary resource sharing with HDMI LPE audio driver. */
	struct {
		struct platform_device *platdev;
		int	irq;
	} lpe_audio;

2743 2744 2745 2746
	/*
	 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
	 * will be rejected. Instead look for a better place.
	 */
2747
};
L
Linus Torvalds 已提交
2748

2749 2750
static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
{
2751
	return container_of(dev, struct drm_i915_private, drm);
2752 2753
}

2754
static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
I
Imre Deak 已提交
2755
{
2756
	return to_i915(dev_get_drvdata(kdev));
I
Imre Deak 已提交
2757 2758
}

2759 2760 2761 2762 2763
static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
{
	return container_of(guc, struct drm_i915_private, guc);
}

A
Arkadiusz Hiler 已提交
2764 2765 2766 2767 2768
static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
{
	return container_of(huc, struct drm_i915_private, huc);
}

2769
/* Simple iterator over all initialised engines */
2770 2771 2772 2773 2774
#define for_each_engine(engine__, dev_priv__, id__) \
	for ((id__) = 0; \
	     (id__) < I915_NUM_ENGINES; \
	     (id__)++) \
		for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2775 2776

/* Iterator over subset of engines selected by mask */
2777 2778
#define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
	for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask;	\
2779
	     tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2780

2781 2782 2783 2784 2785 2786 2787
enum hdmi_force_audio {
	HDMI_AUDIO_OFF_DVI = -2,	/* no aux data for HDMI-DVI converter */
	HDMI_AUDIO_OFF,			/* force turn off HDMI audio */
	HDMI_AUDIO_AUTO,		/* trust EDID */
	HDMI_AUDIO_ON,			/* force turn on HDMI audio */
};

2788
#define I915_GTT_OFFSET_NONE ((u32)-1)
2789

2790 2791
/*
 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2792
 * considered to be the frontbuffer for the given plane interface-wise. This
2793 2794 2795 2796 2797
 * doesn't mean that the hw necessarily already scans it out, but that any
 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
 *
 * We have one bit per pipe and per scanout plane type.
 */
2798 2799
#define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2800 2801 2802
#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
	(1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
#define INTEL_FRONTBUFFER_CURSOR(pipe) \
2803 2804 2805
	(1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
#define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
	(1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2806
#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2807
	(1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2808
#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2809
	(0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2810

2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836
/*
 * Optimised SGL iterator for GEM objects
 */
static __always_inline struct sgt_iter {
	struct scatterlist *sgp;
	union {
		unsigned long pfn;
		dma_addr_t dma;
	};
	unsigned int curr;
	unsigned int max;
} __sgt_iter(struct scatterlist *sgl, bool dma) {
	struct sgt_iter s = { .sgp = sgl };

	if (s.sgp) {
		s.max = s.curr = s.sgp->offset;
		s.max += s.sgp->length;
		if (dma)
			s.dma = sg_dma_address(s.sgp);
		else
			s.pfn = page_to_pfn(sg_page(s.sgp));
	}

	return s;
}

2837 2838 2839 2840 2841 2842 2843 2844
static inline struct scatterlist *____sg_next(struct scatterlist *sg)
{
	++sg;
	if (unlikely(sg_is_chain(sg)))
		sg = sg_chain_ptr(sg);
	return sg;
}

2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858
/**
 * __sg_next - return the next scatterlist entry in a list
 * @sg:		The current sg entry
 *
 * Description:
 *   If the entry is the last, return NULL; otherwise, step to the next
 *   element in the array (@sg@+1). If that's a chain pointer, follow it;
 *   otherwise just return the pointer to the current element.
 **/
static inline struct scatterlist *__sg_next(struct scatterlist *sg)
{
#ifdef CONFIG_DEBUG_SG
	BUG_ON(sg->sg_magic != SG_MAGIC);
#endif
2859
	return sg_is_last(sg) ? NULL : ____sg_next(sg);
2860 2861
}

2862 2863 2864 2865 2866 2867 2868 2869 2870
/**
 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
 * @__dmap:	DMA address (output)
 * @__iter:	'struct sgt_iter' (iterator state, internal)
 * @__sgt:	sg_table to iterate over (input)
 */
#define for_each_sgt_dma(__dmap, __iter, __sgt)				\
	for ((__iter) = __sgt_iter((__sgt)->sgl, true);			\
	     ((__dmap) = (__iter).dma + (__iter).curr);			\
2871 2872
	     (((__iter).curr += PAGE_SIZE) >= (__iter).max) ?		\
	     (__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0)
2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883

/**
 * for_each_sgt_page - iterate over the pages of the given sg_table
 * @__pp:	page pointer (output)
 * @__iter:	'struct sgt_iter' (iterator state, internal)
 * @__sgt:	sg_table to iterate over (input)
 */
#define for_each_sgt_page(__pp, __iter, __sgt)				\
	for ((__iter) = __sgt_iter((__sgt)->sgl, false);		\
	     ((__pp) = (__iter).pfn == 0 ? NULL :			\
	      pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2884 2885
	     (((__iter).curr += PAGE_SIZE) >= (__iter).max) ?		\
	     (__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0 : 0)
2886

2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900 2901
static inline unsigned int i915_sg_page_sizes(struct scatterlist *sg)
{
	unsigned int page_sizes;

	page_sizes = 0;
	while (sg) {
		GEM_BUG_ON(sg->offset);
		GEM_BUG_ON(!IS_ALIGNED(sg->length, PAGE_SIZE));
		page_sizes |= sg->length;
		sg = __sg_next(sg);
	}

	return page_sizes;
}

2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916
static inline unsigned int i915_sg_segment_size(void)
{
	unsigned int size = swiotlb_max_segment();

	if (size == 0)
		return SCATTERLIST_MAX_SEGMENT;

	size = rounddown(size, PAGE_SIZE);
	/* swiotlb_max_segment_size can return 1 byte when it means one page. */
	if (size < PAGE_SIZE)
		size = PAGE_SIZE;

	return size;
}

2917 2918 2919 2920 2921 2922 2923
static inline const struct intel_device_info *
intel_info(const struct drm_i915_private *dev_priv)
{
	return &dev_priv->info;
}

#define INTEL_INFO(dev_priv)	intel_info((dev_priv))
2924

2925
#define INTEL_GEN(dev_priv)	((dev_priv)->info.gen)
2926
#define INTEL_DEVID(dev_priv)	((dev_priv)->info.device_id)
2927

2928
#define REVID_FOREVER		0xff
2929
#define INTEL_REVID(dev_priv)	((dev_priv)->drm.pdev->revision)
2930 2931

#define GEN_FOREVER (0)
2932 2933 2934 2935 2936 2937 2938 2939

#define INTEL_GEN_MASK(s, e) ( \
	BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
	BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
	GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \
		(s) != GEN_FOREVER ? (s) - 1 : 0) \
)

2940 2941 2942 2943 2944
/*
 * Returns true if Gen is in inclusive range [Start, End].
 *
 * Use GEN_FOREVER for unbound start and or end.
 */
2945 2946
#define IS_GEN(dev_priv, s, e) \
	(!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
2947

2948 2949 2950 2951 2952 2953 2954 2955
/*
 * Return true if revision is in range [since,until] inclusive.
 *
 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
 */
#define IS_REVID(p, since, until) \
	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))

2956
#define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
T
Tvrtko Ursulin 已提交
2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969

#define IS_I830(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I830)
#define IS_I845G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I845G)
#define IS_I85X(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I85X)
#define IS_I865G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I865G)
#define IS_I915G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915G)
#define IS_I915GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915GM)
#define IS_I945G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I945G)
#define IS_I945GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I945GM)
#define IS_I965G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I965G)
#define IS_I965GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I965GM)
#define IS_G45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G45)
#define IS_GM45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GM45)
2970
#define IS_G4X(dev_priv)	(IS_G45(dev_priv) || IS_GM45(dev_priv))
2971 2972
#define IS_PINEVIEW_G(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa001)
#define IS_PINEVIEW_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa011)
T
Tvrtko Ursulin 已提交
2973 2974
#define IS_PINEVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
#define IS_G33(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G33)
2975
#define IS_IRONLAKE_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0046)
T
Tvrtko Ursulin 已提交
2976
#define IS_IVYBRIDGE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
2977 2978
#define IS_IVB_GT1(dev_priv)	(IS_IVYBRIDGE(dev_priv) && \
				 (dev_priv)->info.gt == 1)
T
Tvrtko Ursulin 已提交
2979 2980 2981 2982 2983 2984 2985 2986 2987 2988
#define IS_VALLEYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
#define IS_CHERRYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
#define IS_HASWELL(dev_priv)	IS_PLATFORM(dev_priv, INTEL_HASWELL)
#define IS_BROADWELL(dev_priv)	IS_PLATFORM(dev_priv, INTEL_BROADWELL)
#define IS_SKYLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
#define IS_BROXTON(dev_priv)	IS_PLATFORM(dev_priv, INTEL_BROXTON)
#define IS_KABYLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
#define IS_GEMINILAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
#define IS_COFFEELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
#define IS_CANNONLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
2989
#define IS_MOBILE(dev_priv)	((dev_priv)->info.is_mobile)
2990 2991 2992 2993 2994 2995
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv)	(IS_BROADWELL(dev_priv) && \
				 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 ||	\
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xb ||	\
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
V
Ville Syrjälä 已提交
2996
/* ULX machines are also considered ULT. */
2997 2998 2999
#define IS_BDW_ULX(dev_priv)	(IS_BROADWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
#define IS_BDW_GT3(dev_priv)	(IS_BROADWELL(dev_priv) && \
3000
				 (dev_priv)->info.gt == 3)
3001 3002 3003
#define IS_HSW_ULT(dev_priv)	(IS_HASWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
#define IS_HSW_GT3(dev_priv)	(IS_HASWELL(dev_priv) && \
3004
				 (dev_priv)->info.gt == 3)
3005
/* ULX machines are also considered ULT. */
3006 3007 3008 3009 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023
#define IS_HSW_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0A0E || \
				 INTEL_DEVID(dev_priv) == 0x0A1E)
#define IS_SKL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x1906 || \
				 INTEL_DEVID(dev_priv) == 0x1913 || \
				 INTEL_DEVID(dev_priv) == 0x1916 || \
				 INTEL_DEVID(dev_priv) == 0x1921 || \
				 INTEL_DEVID(dev_priv) == 0x1926)
#define IS_SKL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x190E || \
				 INTEL_DEVID(dev_priv) == 0x1915 || \
				 INTEL_DEVID(dev_priv) == 0x191E)
#define IS_KBL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x5906 || \
				 INTEL_DEVID(dev_priv) == 0x5913 || \
				 INTEL_DEVID(dev_priv) == 0x5916 || \
				 INTEL_DEVID(dev_priv) == 0x5921 || \
				 INTEL_DEVID(dev_priv) == 0x5926)
#define IS_KBL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x590E || \
				 INTEL_DEVID(dev_priv) == 0x5915 || \
				 INTEL_DEVID(dev_priv) == 0x591E)
3024
#define IS_SKL_GT2(dev_priv)	(IS_SKYLAKE(dev_priv) && \
3025
				 (dev_priv)->info.gt == 2)
3026
#define IS_SKL_GT3(dev_priv)	(IS_SKYLAKE(dev_priv) && \
3027
				 (dev_priv)->info.gt == 3)
3028
#define IS_SKL_GT4(dev_priv)	(IS_SKYLAKE(dev_priv) && \
3029
				 (dev_priv)->info.gt == 4)
3030
#define IS_KBL_GT2(dev_priv)	(IS_KABYLAKE(dev_priv) && \
3031
				 (dev_priv)->info.gt == 2)
3032
#define IS_KBL_GT3(dev_priv)	(IS_KABYLAKE(dev_priv) && \
3033
				 (dev_priv)->info.gt == 3)
3034 3035
#define IS_CFL_ULT(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
3036 3037
#define IS_CFL_GT2(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
				 (dev_priv)->info.gt == 2)
3038

3039
#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
3040

3041 3042 3043 3044 3045 3046
#define SKL_REVID_A0		0x0
#define SKL_REVID_B0		0x1
#define SKL_REVID_C0		0x2
#define SKL_REVID_D0		0x3
#define SKL_REVID_E0		0x4
#define SKL_REVID_F0		0x5
3047 3048
#define SKL_REVID_G0		0x6
#define SKL_REVID_H0		0x7
3049

3050 3051
#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))

3052
#define BXT_REVID_A0		0x0
3053
#define BXT_REVID_A1		0x1
3054
#define BXT_REVID_B0		0x3
3055
#define BXT_REVID_B_LAST	0x8
3056
#define BXT_REVID_C0		0x9
N
Nick Hoath 已提交
3057

3058 3059
#define IS_BXT_REVID(dev_priv, since, until) \
	(IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
3060

M
Mika Kuoppala 已提交
3061 3062
#define KBL_REVID_A0		0x0
#define KBL_REVID_B0		0x1
3063 3064 3065
#define KBL_REVID_C0		0x2
#define KBL_REVID_D0		0x3
#define KBL_REVID_E0		0x4
M
Mika Kuoppala 已提交
3066

3067 3068
#define IS_KBL_REVID(dev_priv, since, until) \
	(IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
M
Mika Kuoppala 已提交
3069

3070 3071 3072 3073 3074 3075
#define GLK_REVID_A0		0x0
#define GLK_REVID_A1		0x1

#define IS_GLK_REVID(dev_priv, since, until) \
	(IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))

3076 3077
#define CNL_REVID_A0		0x0
#define CNL_REVID_B0		0x1
R
Rodrigo Vivi 已提交
3078
#define CNL_REVID_C0		0x2
3079 3080 3081 3082

#define IS_CNL_REVID(p, since, until) \
	(IS_CANNONLAKE(p) && IS_REVID(p, since, until))

3083 3084 3085 3086 3087 3088
/*
 * The genX designation typically refers to the render engine, so render
 * capability related checks should use IS_GEN, while display and other checks
 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
 * chips, etc.).
 */
3089 3090 3091 3092 3093 3094 3095 3096
#define IS_GEN2(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(1)))
#define IS_GEN3(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(2)))
#define IS_GEN4(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(3)))
#define IS_GEN5(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(4)))
#define IS_GEN6(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(5)))
#define IS_GEN7(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(6)))
#define IS_GEN8(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(7)))
#define IS_GEN9(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(8)))
3097
#define IS_GEN10(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(9)))
3098

3099
#define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
3100 3101
#define IS_GEN9_LP(dev_priv)	(IS_GEN9(dev_priv) && IS_LP(dev_priv))
#define IS_GEN9_BC(dev_priv)	(IS_GEN9(dev_priv) && !IS_LP(dev_priv))
3102

3103 3104 3105 3106 3107 3108 3109 3110 3111
#define ENGINE_MASK(id)	BIT(id)
#define RENDER_RING	ENGINE_MASK(RCS)
#define BSD_RING	ENGINE_MASK(VCS)
#define BLT_RING	ENGINE_MASK(BCS)
#define VEBOX_RING	ENGINE_MASK(VECS)
#define BSD2_RING	ENGINE_MASK(VCS2)
#define ALL_ENGINES	(~0)

#define HAS_ENGINE(dev_priv, id) \
3112
	(!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
3113 3114 3115 3116 3117 3118

#define HAS_BSD(dev_priv)	HAS_ENGINE(dev_priv, VCS)
#define HAS_BSD2(dev_priv)	HAS_ENGINE(dev_priv, VCS2)
#define HAS_BLT(dev_priv)	HAS_ENGINE(dev_priv, BCS)
#define HAS_VEBOX(dev_priv)	HAS_ENGINE(dev_priv, VECS)

3119 3120 3121
#define HAS_LLC(dev_priv)	((dev_priv)->info.has_llc)
#define HAS_SNOOP(dev_priv)	((dev_priv)->info.has_snoop)
#define HAS_EDRAM(dev_priv)	(!!((dev_priv)->edram_cap & EDRAM_ENABLED))
3122 3123
#define HAS_WT(dev_priv)	((IS_HASWELL(dev_priv) || \
				 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
3124

3125
#define HWS_NEEDS_PHYSICAL(dev_priv)	((dev_priv)->info.hws_needs_physical)
3126

3127 3128
#define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
		((dev_priv)->info.has_logical_ring_contexts)
3129 3130 3131
#define USES_PPGTT(dev_priv)		(i915_modparams.enable_ppgtt)
#define USES_FULL_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt >= 2)
#define USES_FULL_48BIT_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt == 3)
3132 3133 3134 3135
#define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
	GEM_BUG_ON((sizes) == 0); \
	((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
})
3136 3137 3138 3139

#define HAS_OVERLAY(dev_priv)		 ((dev_priv)->info.has_overlay)
#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
		((dev_priv)->info.overlay_needs_physical)
3140

3141
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
3142
#define HAS_BROKEN_CS_TLB(dev_priv)	(IS_I830(dev_priv) || IS_I845G(dev_priv))
3143 3144

/* WaRsDisableCoarsePowerGating:skl,bxt */
3145
#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
3146
	(IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
3147

3148 3149 3150 3151 3152
/*
 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
 * even when in MSI mode. This results in spurious interrupt warnings if the
 * legacy irq no. is shared with another device. The kernel then disables that
 * interrupt source and so prevents the other device from working properly.
3153 3154 3155
 *
 * Since we don't enable MSI anymore on gen4, we can always use GMBUS/AUX
 * interrupts.
3156
 */
3157 3158
#define HAS_AUX_IRQ(dev_priv)   true
#define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
3159

3160 3161 3162
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 * rows, which changed the alignment requirements and fence programming.
 */
3163 3164 3165
#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
					 !(IS_I915G(dev_priv) || \
					 IS_I915GM(dev_priv)))
3166 3167
#define SUPPORTS_TV(dev_priv)		((dev_priv)->info.supports_tv)
#define I915_HAS_HOTPLUG(dev_priv)	((dev_priv)->info.has_hotplug)
3168

3169 3170 3171
#define HAS_FW_BLC(dev_priv) 	(INTEL_GEN(dev_priv) > 2)
#define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
#define HAS_FBC(dev_priv)	((dev_priv)->info.has_fbc)
3172
#define HAS_CUR_FBC(dev_priv)	(!HAS_GMCH_DISPLAY(dev_priv) && INTEL_INFO(dev_priv)->gen >= 7)
3173

3174
#define HAS_IPS(dev_priv)	(IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
3175

3176
#define HAS_DP_MST(dev_priv)	((dev_priv)->info.has_dp_mst)
3177

3178 3179 3180 3181 3182
#define HAS_DDI(dev_priv)		 ((dev_priv)->info.has_ddi)
#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
#define HAS_PSR(dev_priv)		 ((dev_priv)->info.has_psr)
#define HAS_RC6(dev_priv)		 ((dev_priv)->info.has_rc6)
#define HAS_RC6p(dev_priv)		 ((dev_priv)->info.has_rc6p)
P
Paulo Zanoni 已提交
3183

3184
#define HAS_CSR(dev_priv)	((dev_priv)->info.has_csr)
3185

3186
#define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
3187 3188
#define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)

3189 3190
#define HAS_IPC(dev_priv)		 ((dev_priv)->info.has_ipc)

3191 3192 3193 3194 3195
/*
 * For now, anything with a GuC requires uCode loading, and then supports
 * command submission once loaded. But these are logically independent
 * properties, so we have separate macros to test them.
 */
3196
#define HAS_GUC(dev_priv)	((dev_priv)->info.has_guc)
3197
#define HAS_GUC_CT(dev_priv)	((dev_priv)->info.has_guc_ct)
3198 3199
#define HAS_GUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
#define HAS_GUC_SCHED(dev_priv)	(HAS_GUC(dev_priv))
3200
#define HAS_HUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
3201

3202
#define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
3203

3204
#define HAS_POOLED_EU(dev_priv)	((dev_priv)->info.has_pooled_eu)
3205

3206
#define INTEL_PCH_DEVICE_ID_MASK		0xff80
3207 3208 3209 3210 3211
#define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
#define INTEL_PCH_PPT_DEVICE_ID_TYPE		0x1e00
#define INTEL_PCH_LPT_DEVICE_ID_TYPE		0x8c00
#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE		0x9c00
3212 3213
#define INTEL_PCH_WPT_DEVICE_ID_TYPE		0x8c80
#define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE		0x9c80
3214 3215
#define INTEL_PCH_SPT_DEVICE_ID_TYPE		0xA100
#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE		0x9D00
3216
#define INTEL_PCH_KBP_DEVICE_ID_TYPE		0xA280
3217
#define INTEL_PCH_CNP_DEVICE_ID_TYPE		0xA300
3218
#define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE		0x9D80
3219
#define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
3220
#define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
3221
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
3222

3223
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
3224
#define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
3225 3226
#define HAS_PCH_CNP_LP(dev_priv) \
	((dev_priv)->pch_id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE)
3227 3228 3229
#define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
3230
#define HAS_PCH_LPT_LP(dev_priv) \
3231 3232
	((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
	 (dev_priv)->pch_id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
3233
#define HAS_PCH_LPT_H(dev_priv) \
3234 3235
	((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
	 (dev_priv)->pch_id == INTEL_PCH_WPT_DEVICE_ID_TYPE)
3236 3237 3238 3239
#define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
#define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
3240

3241
#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
3242

3243
#define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
3244

3245
/* DPF == dynamic parity feature */
3246
#define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
3247 3248
#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
				 2 : HAS_L3_DPF(dev_priv))
3249

3250
#define GT_FREQUENCY_MULTIPLIER 50
A
Akash Goel 已提交
3251
#define GEN9_FREQ_SCALER 3
3252

3253 3254
#include "i915_trace.h"

3255
static inline bool intel_vtd_active(void)
3256 3257
{
#ifdef CONFIG_INTEL_IOMMU
3258
	if (intel_iommu_gfx_mapped)
3259 3260 3261 3262 3263
		return true;
#endif
	return false;
}

3264 3265 3266 3267 3268
static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
{
	return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
}

3269 3270 3271
static inline bool
intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
{
3272
	return IS_BROXTON(dev_priv) && intel_vtd_active();
3273 3274
}

3275
int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
3276
				int enable_ppgtt);
3277

3278 3279
bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);

3280
/* i915_drv.c */
3281 3282 3283 3284 3285 3286 3287
void __printf(3, 4)
__i915_printk(struct drm_i915_private *dev_priv, const char *level,
	      const char *fmt, ...);

#define i915_report_error(dev_priv, fmt, ...)				   \
	__i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)

3288
#ifdef CONFIG_COMPAT
D
Dave Airlie 已提交
3289 3290
extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
			      unsigned long arg);
3291 3292
#else
#define i915_compat_ioctl NULL
3293
#endif
3294 3295 3296 3297 3298
extern const struct dev_pm_ops i915_pm_ops;

extern int i915_driver_load(struct pci_dev *pdev,
			    const struct pci_device_id *ent);
extern void i915_driver_unload(struct drm_device *dev);
3299 3300
extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
3301 3302 3303 3304 3305 3306

#define I915_RESET_QUIET BIT(0)
extern void i915_reset(struct drm_i915_private *i915, unsigned int flags);
extern int i915_reset_engine(struct intel_engine_cs *engine,
			     unsigned int flags);

3307
extern bool intel_has_reset_engine(struct drm_i915_private *dev_priv);
3308
extern int intel_guc_reset(struct drm_i915_private *dev_priv);
3309
extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
3310
extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
3311 3312 3313 3314
extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
3315
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
3316

3317
int intel_engines_init_mmio(struct drm_i915_private *dev_priv);
3318 3319
int intel_engines_init(struct drm_i915_private *dev_priv);

3320
/* intel_hotplug.c */
3321 3322
void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
			   u32 pin_mask, u32 long_mask);
3323 3324 3325
void intel_hpd_init(struct drm_i915_private *dev_priv);
void intel_hpd_init_work(struct drm_i915_private *dev_priv);
void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
3326
enum port intel_hpd_pin_to_port(enum hpd_pin pin);
3327
enum hpd_pin intel_hpd_pin(enum port port);
3328 3329
bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
3330

L
Linus Torvalds 已提交
3331
/* i915_irq.c */
3332 3333 3334 3335
static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
{
	unsigned long delay;

3336
	if (unlikely(!i915_modparams.enable_hangcheck))
3337 3338 3339 3340 3341 3342 3343 3344 3345 3346 3347 3348
		return;

	/* Don't continually defer the hangcheck so that it is always run at
	 * least once after work has been scheduled on any ring. Otherwise,
	 * we will ignore a hung ring if a second ring is kept busy.
	 */

	delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
	queue_delayed_work(system_long_wq,
			   &dev_priv->gpu_error.hangcheck_work, delay);
}

3349
__printf(3, 4)
3350 3351
void i915_handle_error(struct drm_i915_private *dev_priv,
		       u32 engine_mask,
3352
		       const char *fmt, ...);
L
Linus Torvalds 已提交
3353

3354
extern void intel_irq_init(struct drm_i915_private *dev_priv);
3355
extern void intel_irq_fini(struct drm_i915_private *dev_priv);
3356 3357
int intel_irq_install(struct drm_i915_private *dev_priv);
void intel_irq_uninstall(struct drm_i915_private *dev_priv);
3358

3359 3360
static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
{
3361
	return dev_priv->gvt;
3362 3363
}

3364
static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
3365
{
3366
	return dev_priv->vgpu.active;
3367
}
3368

3369 3370
u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
			      enum pipe pipe);
3371
void
3372
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3373
		     u32 status_mask);
3374 3375

void
3376
i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3377
		      u32 status_mask);
3378

3379 3380
void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
3381 3382 3383
void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
				   uint32_t mask,
				   uint32_t bits);
3384 3385 3386 3387 3388 3389 3390 3391 3392 3393 3394 3395 3396
void ilk_update_display_irq(struct drm_i915_private *dev_priv,
			    uint32_t interrupt_mask,
			    uint32_t enabled_irq_mask);
static inline void
ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, bits);
}
static inline void
ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, 0);
}
3397 3398 3399 3400 3401 3402 3403 3404 3405 3406 3407 3408 3409 3410
void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
			 enum pipe pipe,
			 uint32_t interrupt_mask,
			 uint32_t enabled_irq_mask);
static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
				       enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
}
static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
					enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
}
3411 3412 3413
void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
				  uint32_t interrupt_mask,
				  uint32_t enabled_irq_mask);
3414 3415 3416 3417 3418 3419 3420 3421 3422 3423 3424
static inline void
ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, bits);
}
static inline void
ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, 0);
}

3425 3426 3427 3428 3429 3430 3431 3432 3433
/* i915_gem.c */
int i915_gem_create_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3434 3435
int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3436 3437 3438 3439 3440 3441
int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
			     struct drm_file *file_priv);
int i915_gem_execbuffer(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
J
Jesse Barnes 已提交
3442 3443
int i915_gem_execbuffer2(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
3444 3445
int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
B
Ben Widawsky 已提交
3446 3447 3448 3449
int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
3450 3451
int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *file_priv);
3452 3453
int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
3454 3455 3456 3457
int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
3458 3459
int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
3460 3461
int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file);
3462 3463
int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
3464 3465
int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3466
void i915_gem_sanitize(struct drm_i915_private *i915);
3467 3468
int i915_gem_load_init(struct drm_i915_private *dev_priv);
void i915_gem_load_cleanup(struct drm_i915_private *dev_priv);
3469
void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3470
int i915_gem_freeze(struct drm_i915_private *dev_priv);
3471 3472
int i915_gem_freeze_late(struct drm_i915_private *dev_priv);

3473
void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
3474
void i915_gem_object_free(struct drm_i915_gem_object *obj);
3475 3476
void i915_gem_object_init(struct drm_i915_gem_object *obj,
			 const struct drm_i915_gem_object_ops *ops);
3477 3478 3479 3480 3481
struct drm_i915_gem_object *
i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
struct drm_i915_gem_object *
i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
				 const void *data, size_t size);
3482
void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
3483
void i915_gem_free_object(struct drm_gem_object *obj);
3484

3485 3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497
static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
{
	/* A single pass should suffice to release all the freed objects (along
	 * most call paths) , but be a little more paranoid in that freeing
	 * the objects does take a little amount of time, during which the rcu
	 * callbacks could have added new objects into the freed list, and
	 * armed the work again.
	 */
	do {
		rcu_barrier();
	} while (flush_work(&i915->mm.free_work));
}

3498 3499 3500 3501 3502 3503 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517
static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
{
	/*
	 * Similar to objects above (see i915_gem_drain_freed-objects), in
	 * general we have workers that are armed by RCU and then rearm
	 * themselves in their callbacks. To be paranoid, we need to
	 * drain the workqueue a second time after waiting for the RCU
	 * grace period so that we catch work queued via RCU from the first
	 * pass. As neither drain_workqueue() nor flush_workqueue() report
	 * a result, we make an assumption that we only don't require more
	 * than 2 passes to catch all recursive RCU delayed work.
	 *
	 */
	int pass = 2;
	do {
		rcu_barrier();
		drain_workqueue(i915->wq);
	} while (--pass);
}

C
Chris Wilson 已提交
3518
struct i915_vma * __must_check
3519 3520
i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
			 const struct i915_ggtt_view *view,
3521
			 u64 size,
3522 3523
			 u64 alignment,
			 u64 flags);
3524

3525
int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
3526
void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3527

3528 3529
void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);

C
Chris Wilson 已提交
3530
static inline int __sg_page_count(const struct scatterlist *sg)
3531
{
3532 3533
	return sg->length >> PAGE_SHIFT;
}
3534

3535 3536 3537
struct scatterlist *
i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
		       unsigned int n, unsigned int *offset);
3538

3539 3540 3541
struct page *
i915_gem_object_get_page(struct drm_i915_gem_object *obj,
			 unsigned int n);
3542

3543 3544 3545
struct page *
i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
			       unsigned int n);
3546

3547 3548 3549
dma_addr_t
i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
				unsigned long n);
3550

3551
void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
3552
				 struct sg_table *pages,
M
Matthew Auld 已提交
3553
				 unsigned int sg_page_sizes);
C
Chris Wilson 已提交
3554 3555 3556 3557 3558
int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);

static inline int __must_check
i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
{
3559
	might_lock(&obj->mm.lock);
C
Chris Wilson 已提交
3560

3561
	if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
C
Chris Wilson 已提交
3562 3563 3564 3565 3566
		return 0;

	return __i915_gem_object_get_pages(obj);
}

3567 3568 3569 3570 3571 3572
static inline bool
i915_gem_object_has_pages(struct drm_i915_gem_object *obj)
{
	return !IS_ERR_OR_NULL(READ_ONCE(obj->mm.pages));
}

C
Chris Wilson 已提交
3573 3574
static inline void
__i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3575
{
3576
	GEM_BUG_ON(!i915_gem_object_has_pages(obj));
C
Chris Wilson 已提交
3577

3578
	atomic_inc(&obj->mm.pages_pin_count);
C
Chris Wilson 已提交
3579 3580 3581 3582 3583
}

static inline bool
i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
{
3584
	return atomic_read(&obj->mm.pages_pin_count);
C
Chris Wilson 已提交
3585 3586 3587 3588 3589
}

static inline void
__i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
{
3590
	GEM_BUG_ON(!i915_gem_object_has_pages(obj));
C
Chris Wilson 已提交
3591 3592
	GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));

3593
	atomic_dec(&obj->mm.pages_pin_count);
3594
}
3595

3596 3597
static inline void
i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3598
{
C
Chris Wilson 已提交
3599
	__i915_gem_object_unpin_pages(obj);
3600 3601
}

3602 3603 3604 3605 3606 3607 3608
enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
	I915_MM_NORMAL = 0,
	I915_MM_SHRINKER
};

void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
				 enum i915_mm_subclass subclass);
3609
void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
C
Chris Wilson 已提交
3610

3611 3612 3613
enum i915_map_type {
	I915_MAP_WB = 0,
	I915_MAP_WC,
3614 3615 3616
#define I915_MAP_OVERRIDE BIT(31)
	I915_MAP_FORCE_WB = I915_MAP_WB | I915_MAP_OVERRIDE,
	I915_MAP_FORCE_WC = I915_MAP_WC | I915_MAP_OVERRIDE,
3617 3618
};

3619 3620
/**
 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3621 3622
 * @obj: the object to map into kernel address space
 * @type: the type of mapping, used to select pgprot_t
3623 3624 3625
 *
 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
 * pages and then returns a contiguous mapping of the backing storage into
3626 3627
 * the kernel address space. Based on the @type of mapping, the PTE will be
 * set to either WriteBack or WriteCombine (via pgprot_t).
3628
 *
3629 3630
 * The caller is responsible for calling i915_gem_object_unpin_map() when the
 * mapping is no longer required.
3631
 *
3632 3633
 * Returns the pointer through which to access the mapped object, or an
 * ERR_PTR() on error.
3634
 */
3635 3636
void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
					   enum i915_map_type type);
3637 3638 3639

/**
 * i915_gem_object_unpin_map - releases an earlier mapping
3640
 * @obj: the object to unmap
3641 3642 3643 3644 3645 3646 3647 3648 3649 3650 3651
 *
 * After pinning the object and mapping its pages, once you are finished
 * with your access, call i915_gem_object_unpin_map() to release the pin
 * upon the mapping. Once the pin count reaches zero, that mapping may be
 * removed.
 */
static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
{
	i915_gem_object_unpin_pages(obj);
}

3652 3653 3654 3655
int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
				    unsigned int *needs_clflush);
int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
				     unsigned int *needs_clflush);
3656 3657 3658
#define CLFLUSH_BEFORE	BIT(0)
#define CLFLUSH_AFTER	BIT(1)
#define CLFLUSH_FLAGS	(CLFLUSH_BEFORE | CLFLUSH_AFTER)
3659 3660 3661 3662 3663 3664 3665

static inline void
i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
{
	i915_gem_object_unpin_pages(obj);
}

3666
int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
B
Ben Widawsky 已提交
3667
void i915_vma_move_to_active(struct i915_vma *vma,
3668 3669
			     struct drm_i915_gem_request *req,
			     unsigned int flags);
3670 3671 3672
int i915_gem_dumb_create(struct drm_file *file_priv,
			 struct drm_device *dev,
			 struct drm_mode_create_dumb *args);
3673 3674
int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
		      uint32_t handle, uint64_t *offset);
3675
int i915_gem_mmap_gtt_version(void);
3676 3677 3678 3679 3680

void i915_gem_track_fb(struct drm_i915_gem_object *old,
		       struct drm_i915_gem_object *new,
		       unsigned frontbuffer_bits);

3681
int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3682

3683
struct drm_i915_gem_request *
3684
i915_gem_find_active_request(struct intel_engine_cs *engine);
3685

3686
void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3687

3688 3689 3690 3691 3692 3693
static inline bool i915_reset_backoff(struct i915_gpu_error *error)
{
	return unlikely(test_bit(I915_RESET_BACKOFF, &error->flags));
}

static inline bool i915_reset_handoff(struct i915_gpu_error *error)
3694
{
3695
	return unlikely(test_bit(I915_RESET_HANDOFF, &error->flags));
3696 3697
}

3698
static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3699
{
3700
	return unlikely(test_bit(I915_WEDGED, &error->flags));
3701 3702
}

3703
static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error *error)
3704
{
3705
	return i915_reset_backoff(error) | i915_terminally_wedged(error);
M
Mika Kuoppala 已提交
3706 3707 3708 3709
}

static inline u32 i915_reset_count(struct i915_gpu_error *error)
{
3710
	return READ_ONCE(error->reset_count);
3711
}
3712

3713 3714 3715 3716 3717 3718
static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
					  struct intel_engine_cs *engine)
{
	return READ_ONCE(error->reset_engine_count[engine->id]);
}

3719 3720
struct drm_i915_gem_request *
i915_gem_reset_prepare_engine(struct intel_engine_cs *engine);
3721
int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
3722
void i915_gem_reset(struct drm_i915_private *dev_priv);
3723
void i915_gem_reset_finish_engine(struct intel_engine_cs *engine);
3724
void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
3725
void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3726
bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
3727 3728
void i915_gem_reset_engine(struct intel_engine_cs *engine,
			   struct drm_i915_gem_request *request);
3729

3730
void i915_gem_init_mmio(struct drm_i915_private *i915);
3731 3732
int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3733
void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3734
void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3735 3736
int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
			   unsigned int flags);
3737 3738
int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
void i915_gem_resume(struct drm_i915_private *dev_priv);
3739
int i915_gem_fault(struct vm_fault *vmf);
3740 3741 3742 3743
int i915_gem_object_wait(struct drm_i915_gem_object *obj,
			 unsigned int flags,
			 long timeout,
			 struct intel_rps_client *rps);
3744 3745 3746 3747 3748
int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
				  unsigned int flags,
				  int priority);
#define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX

3749
int __must_check
3750 3751 3752
i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write);
int __must_check
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write);
3753
int __must_check
3754
i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
C
Chris Wilson 已提交
3755
struct i915_vma * __must_check
3756 3757
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
				     u32 alignment,
3758
				     const struct i915_ggtt_view *view);
C
Chris Wilson 已提交
3759
void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3760
int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3761
				int align);
3762
int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
3763
void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3764

3765 3766 3767
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
				    enum i915_cache_level cache_level);

3768 3769 3770 3771 3772 3773
struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
				struct dma_buf *dma_buf);

struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
				struct drm_gem_object *gem_obj, int flags);

3774 3775 3776 3777 3778 3779
static inline struct i915_hw_ppgtt *
i915_vm_to_ppgtt(struct i915_address_space *vm)
{
	return container_of(vm, struct i915_hw_ppgtt, base);
}

J
Joonas Lahtinen 已提交
3780
/* i915_gem_fence_reg.c */
3781 3782 3783
struct drm_i915_fence_reg *
i915_reserve_fence(struct drm_i915_private *dev_priv);
void i915_unreserve_fence(struct drm_i915_fence_reg *fence);
3784

3785
void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
3786
void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3787

3788
void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3789 3790 3791 3792
void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
				       struct sg_table *pages);
void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
					 struct sg_table *pages);
3793

3794 3795 3796 3797 3798 3799
static inline struct i915_gem_context *
__i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
{
	return idr_find(&file_priv->context_idr, id);
}

3800 3801 3802 3803 3804
static inline struct i915_gem_context *
i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
{
	struct i915_gem_context *ctx;

3805 3806 3807 3808 3809
	rcu_read_lock();
	ctx = __i915_gem_context_lookup_rcu(file_priv, id);
	if (ctx && !kref_get_unless_zero(&ctx->ref))
		ctx = NULL;
	rcu_read_unlock();
3810 3811 3812 3813

	return ctx;
}

C
Chris Wilson 已提交
3814 3815 3816 3817 3818 3819 3820 3821 3822 3823
static inline struct intel_timeline *
i915_gem_context_lookup_timeline(struct i915_gem_context *ctx,
				 struct intel_engine_cs *engine)
{
	struct i915_address_space *vm;

	vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base;
	return &vm->timeline.engine[engine->id];
}

3824 3825
int i915_perf_open_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file);
3826 3827 3828 3829
int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
				  struct drm_file *file);
3830 3831 3832
void i915_oa_init_reg_state(struct intel_engine_cs *engine,
			    struct i915_gem_context *ctx,
			    uint32_t *reg_state);
3833

3834
/* i915_gem_evict.c */
3835
int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3836
					  u64 min_size, u64 alignment,
3837
					  unsigned cache_level,
3838
					  u64 start, u64 end,
3839
					  unsigned flags);
3840 3841 3842
int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
					 struct drm_mm_node *node,
					 unsigned int flags);
3843
int i915_gem_evict_vm(struct i915_address_space *vm);
3844

3845
/* belongs in i915_gem_gtt.h */
3846
static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3847
{
3848
	wmb();
3849
	if (INTEL_GEN(dev_priv) < 6)
3850 3851
		intel_gtt_chipset_flush();
}
3852

3853
/* i915_gem_stolen.c */
3854 3855 3856
int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
				struct drm_mm_node *node, u64 size,
				unsigned alignment);
3857 3858 3859 3860
int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
					 struct drm_mm_node *node, u64 size,
					 unsigned alignment, u64 start,
					 u64 end);
3861 3862
void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
				 struct drm_mm_node *node);
3863
int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3864
void i915_gem_cleanup_stolen(struct drm_device *dev);
3865
struct drm_i915_gem_object *
3866
i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, u32 size);
3867
struct drm_i915_gem_object *
3868
i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3869 3870 3871
					       u32 stolen_offset,
					       u32 gtt_offset,
					       u32 size);
3872

3873 3874 3875
/* i915_gem_internal.c */
struct drm_i915_gem_object *
i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3876
				phys_addr_t size);
3877

3878 3879
/* i915_gem_shrinker.c */
unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3880
			      unsigned long target,
3881
			      unsigned long *nr_scanned,
3882 3883 3884 3885
			      unsigned flags);
#define I915_SHRINK_PURGEABLE 0x1
#define I915_SHRINK_UNBOUND 0x2
#define I915_SHRINK_BOUND 0x4
3886
#define I915_SHRINK_ACTIVE 0x8
3887
#define I915_SHRINK_VMAPS 0x10
3888 3889
unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3890
void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3891 3892


3893
/* i915_gem_tiling.c */
3894
static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3895
{
3896
	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3897 3898

	return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3899
		i915_gem_object_is_tiled(obj);
3900 3901
}

3902 3903 3904 3905 3906
u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
			unsigned int tiling, unsigned int stride);
u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
			     unsigned int tiling, unsigned int stride);

3907
/* i915_debugfs.c */
3908
#ifdef CONFIG_DEBUG_FS
3909
int i915_debugfs_register(struct drm_i915_private *dev_priv);
J
Jani Nikula 已提交
3910
int i915_debugfs_connector_add(struct drm_connector *connector);
3911
void intel_display_crc_init(struct drm_i915_private *dev_priv);
3912
#else
3913
static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3914 3915
static inline int i915_debugfs_connector_add(struct drm_connector *connector)
{ return 0; }
3916
static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3917
#endif
3918 3919

/* i915_gpu_error.c */
3920 3921
#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)

3922 3923
__printf(2, 3)
void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3924
int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3925
			    const struct i915_gpu_state *gpu);
3926
int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3927
			      struct drm_i915_private *i915,
3928 3929 3930 3931 3932 3933
			      size_t count, loff_t pos);
static inline void i915_error_state_buf_release(
	struct drm_i915_error_state_buf *eb)
{
	kfree(eb->buf);
}
3934 3935

struct i915_gpu_state *i915_capture_gpu_state(struct drm_i915_private *i915);
3936 3937
void i915_capture_error_state(struct drm_i915_private *dev_priv,
			      u32 engine_mask,
3938
			      const char *error_msg);
3939 3940 3941 3942 3943 3944 3945 3946 3947 3948 3949 3950 3951 3952 3953 3954 3955

static inline struct i915_gpu_state *
i915_gpu_state_get(struct i915_gpu_state *gpu)
{
	kref_get(&gpu->ref);
	return gpu;
}

void __i915_gpu_state_free(struct kref *kref);
static inline void i915_gpu_state_put(struct i915_gpu_state *gpu)
{
	if (gpu)
		kref_put(&gpu->ref, __i915_gpu_state_free);
}

struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915);
void i915_reset_error_state(struct drm_i915_private *i915);
3956

3957 3958 3959 3960 3961 3962 3963 3964
#else

static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
					    u32 engine_mask,
					    const char *error_msg)
{
}

3965 3966 3967 3968 3969 3970 3971
static inline struct i915_gpu_state *
i915_first_error_state(struct drm_i915_private *i915)
{
	return NULL;
}

static inline void i915_reset_error_state(struct drm_i915_private *i915)
3972 3973 3974 3975 3976
{
}

#endif

3977
const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3978

3979
/* i915_cmd_parser.c */
3980
int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3981
void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3982 3983 3984 3985 3986 3987 3988
void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
int intel_engine_cmd_parser(struct intel_engine_cs *engine,
			    struct drm_i915_gem_object *batch_obj,
			    struct drm_i915_gem_object *shadow_batch_obj,
			    u32 batch_start_offset,
			    u32 batch_len,
			    bool is_master);
3989

3990 3991 3992
/* i915_perf.c */
extern void i915_perf_init(struct drm_i915_private *dev_priv);
extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3993 3994
extern void i915_perf_register(struct drm_i915_private *dev_priv);
extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3995

3996
/* i915_suspend.c */
3997 3998
extern int i915_save_state(struct drm_i915_private *dev_priv);
extern int i915_restore_state(struct drm_i915_private *dev_priv);
3999

B
Ben Widawsky 已提交
4000
/* i915_sysfs.c */
D
David Weinehall 已提交
4001 4002
void i915_setup_sysfs(struct drm_i915_private *dev_priv);
void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
B
Ben Widawsky 已提交
4003

4004 4005 4006 4007
/* intel_lpe_audio.c */
int  intel_lpe_audio_init(struct drm_i915_private *dev_priv);
void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv);
void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv);
4008
void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
4009 4010
			    enum pipe pipe, enum port port,
			    const void *eld, int ls_clock, bool dp_output);
4011

4012
/* intel_i2c.c */
4013 4014
extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
4015 4016
extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
				     unsigned int pin);
4017

4018 4019
extern struct i2c_adapter *
intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
C
Chris Wilson 已提交
4020 4021
extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
4022
static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
4023 4024 4025
{
	return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
}
4026
extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
4027

4028
/* intel_bios.c */
4029
void intel_bios_init(struct drm_i915_private *dev_priv);
J
Jani Nikula 已提交
4030
bool intel_bios_is_valid_vbt(const void *buf, size_t size);
4031
bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
4032
bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
4033
bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
4034
bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
4035
bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
4036
bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
4037 4038
bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
				     enum port port);
4039 4040 4041
bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
				enum port port);

4042

4043
/* intel_opregion.c */
4044
#ifdef CONFIG_ACPI
4045
extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
4046 4047
extern void intel_opregion_register(struct drm_i915_private *dev_priv);
extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
4048
extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
4049 4050
extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
					 bool enable);
4051
extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
4052
					 pci_power_t state);
4053
extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
4054
#else
4055
static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
4056 4057
static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
4058 4059 4060
static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
{
}
4061 4062 4063 4064 4065
static inline int
intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
{
	return 0;
}
4066
static inline int
4067
intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
4068 4069 4070
{
	return 0;
}
4071
static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
4072 4073 4074
{
	return -ENODEV;
}
4075
#endif
4076

J
Jesse Barnes 已提交
4077 4078 4079 4080 4081 4082 4083 4084 4085
/* intel_acpi.c */
#ifdef CONFIG_ACPI
extern void intel_register_dsm_handler(void);
extern void intel_unregister_dsm_handler(void);
#else
static inline void intel_register_dsm_handler(void) { return; }
static inline void intel_unregister_dsm_handler(void) { return; }
#endif /* CONFIG_ACPI */

4086 4087 4088 4089 4090 4091 4092
/* intel_device_info.c */
static inline struct intel_device_info *
mkwrite_device_info(struct drm_i915_private *dev_priv)
{
	return (struct intel_device_info *)&dev_priv->info;
}

4093
const char *intel_platform_name(enum intel_platform platform);
4094 4095 4096
void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
void intel_device_info_dump(struct drm_i915_private *dev_priv);

J
Jesse Barnes 已提交
4097
/* modesetting */
4098
extern void intel_modeset_init_hw(struct drm_device *dev);
4099
extern int intel_modeset_init(struct drm_device *dev);
4100
extern void intel_modeset_gem_init(struct drm_device *dev);
J
Jesse Barnes 已提交
4101
extern void intel_modeset_cleanup(struct drm_device *dev);
4102
extern int intel_connector_register(struct drm_connector *);
4103
extern void intel_connector_unregister(struct drm_connector *);
4104 4105
extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
				       bool state);
4106
extern void intel_display_resume(struct drm_device *dev);
4107 4108
extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
4109
extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
4110
extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
4111
extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
4112
extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
4113
				  bool enable);
4114

B
Ben Widawsky 已提交
4115 4116
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file);
4117

4118
/* overlay */
4119 4120
extern struct intel_overlay_error_state *
intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
4121 4122
extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
					    struct intel_overlay_error_state *error);
4123

4124 4125
extern struct intel_display_error_state *
intel_display_capture_error_state(struct drm_i915_private *dev_priv);
4126
extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
4127
					    struct intel_display_error_state *error);
4128

4129 4130
int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
4131 4132
int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
		      u32 reply_mask, u32 reply, int timeout_base_ms);
4133 4134

/* intel_sideband.c */
4135
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
4136
int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
4137
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
4138 4139
u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
4140 4141 4142 4143
u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
4144 4145
u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
4146 4147
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
4148 4149 4150 4151
u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
		   enum intel_sbi_destination destination);
void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
		     enum intel_sbi_destination destination);
4152 4153
u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
4154

4155
/* intel_dpio_phy.c */
4156
void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
4157
			     enum dpio_phy *phy, enum dpio_channel *ch);
4158 4159 4160
void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
				  enum port port, u32 margin, u32 scale,
				  u32 enable, u32 deemphasis);
4161 4162 4163 4164 4165 4166 4167 4168 4169 4170 4171 4172
void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
			    enum dpio_phy phy);
bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
			      enum dpio_phy phy);
uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
					     uint8_t lane_count);
void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
				     uint8_t lane_lat_optim_mask);
uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);

4173 4174 4175
void chv_set_phy_signal_level(struct intel_encoder *encoder,
			      u32 deemph_reg_value, u32 margin_reg_value,
			      bool uniq_trans_scale);
4176 4177
void chv_data_lane_soft_reset(struct intel_encoder *encoder,
			      bool reset);
4178
void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
4179 4180
void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
void chv_phy_release_cl2_override(struct intel_encoder *encoder);
4181
void chv_phy_post_pll_disable(struct intel_encoder *encoder);
4182

4183 4184 4185
void vlv_set_phy_signal_level(struct intel_encoder *encoder,
			      u32 demph_reg_value, u32 preemph_reg_value,
			      u32 uniqtranscale_reg_value, u32 tx3_demph);
4186
void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
4187
void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
4188
void vlv_phy_reset_lanes(struct intel_encoder *encoder);
4189

4190 4191
int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
4192 4193
u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
			   const i915_reg_t reg);
4194

4195 4196 4197 4198 4199 4200 4201 4202 4203 4204 4205 4206 4207
#define I915_READ8(reg)		dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
#define I915_WRITE8(reg, val)	dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)

#define I915_READ16(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
#define I915_WRITE16(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
#define I915_READ16_NOTRACE(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
#define I915_WRITE16_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)

#define I915_READ(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
#define I915_WRITE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
#define I915_READ_NOTRACE(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
#define I915_WRITE_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)

4208 4209 4210 4211
/* Be very careful with read/write 64-bit values. On 32-bit machines, they
 * will be implemented using 2 32-bit writes in an arbitrary order with
 * an arbitrary delay between them. This can cause the hardware to
 * act upon the intermediate value, possibly leading to corruption and
4212 4213 4214 4215 4216 4217 4218 4219 4220
 * machine death. For this reason we do not support I915_WRITE64, or
 * dev_priv->uncore.funcs.mmio_writeq.
 *
 * When reading a 64-bit value as two 32-bit values, the delay may cause
 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
 * occasionally a 64-bit register does not actualy support a full readq
 * and must be read using two 32-bit reads.
 *
 * You have been warned.
4221
 */
4222
#define I915_READ64(reg)	dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
4223

4224
#define I915_READ64_2x32(lower_reg, upper_reg) ({			\
4225 4226
	u32 upper, lower, old_upper, loop = 0;				\
	upper = I915_READ(upper_reg);					\
4227
	do {								\
4228
		old_upper = upper;					\
4229
		lower = I915_READ(lower_reg);				\
4230 4231
		upper = I915_READ(upper_reg);				\
	} while (upper != old_upper && loop++ < 2);			\
4232
	(u64)upper << 32 | lower; })
4233

4234 4235 4236
#define POSTING_READ(reg)	(void)I915_READ_NOTRACE(reg)
#define POSTING_READ16(reg)	(void)I915_READ16_NOTRACE(reg)

4237
#define __raw_read(x, s) \
4238
static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
4239
					     i915_reg_t reg) \
4240
{ \
4241
	return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
4242 4243 4244
}

#define __raw_write(x, s) \
4245
static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
4246
				       i915_reg_t reg, uint##x##_t val) \
4247
{ \
4248
	write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
4249 4250 4251 4252 4253 4254 4255 4256 4257 4258 4259 4260 4261 4262
}
__raw_read(8, b)
__raw_read(16, w)
__raw_read(32, l)
__raw_read(64, q)

__raw_write(8, b)
__raw_write(16, w)
__raw_write(32, l)
__raw_write(64, q)

#undef __raw_read
#undef __raw_write

4263
/* These are untraced mmio-accessors that are only valid to be used inside
4264
 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
4265
 * controlled.
4266
 *
4267
 * Think twice, and think again, before using these.
4268 4269 4270 4271 4272 4273 4274 4275 4276 4277 4278 4279 4280 4281 4282 4283 4284 4285 4286 4287
 *
 * As an example, these accessors can possibly be used between:
 *
 * spin_lock_irq(&dev_priv->uncore.lock);
 * intel_uncore_forcewake_get__locked();
 *
 * and
 *
 * intel_uncore_forcewake_put__locked();
 * spin_unlock_irq(&dev_priv->uncore.lock);
 *
 *
 * Note: some registers may not need forcewake held, so
 * intel_uncore_forcewake_{get,put} can be omitted, see
 * intel_uncore_forcewake_for_reg().
 *
 * Certain architectures will die if the same cacheline is concurrently accessed
 * by different clients (e.g. on Ivybridge). Access to registers should
 * therefore generally be serialised, by either the dev_priv->uncore.lock or
 * a more localised lock guarding all access to that bank of registers.
4288
 */
4289 4290
#define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
4291
#define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
4292 4293
#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)

4294 4295 4296 4297
/* "Broadcast RGB" property */
#define INTEL_BROADCAST_RGB_AUTO 0
#define INTEL_BROADCAST_RGB_FULL 1
#define INTEL_BROADCAST_RGB_LIMITED 2
4298

4299
static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
4300
{
4301
	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4302
		return VLV_VGACNTRL;
4303
	else if (INTEL_GEN(dev_priv) >= 5)
4304
		return CPU_VGACNTRL;
4305 4306 4307 4308
	else
		return VGACNTRL;
}

4309 4310 4311 4312 4313 4314 4315
static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
{
	unsigned long j = msecs_to_jiffies(m);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

4316 4317
static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
{
4318 4319 4320 4321 4322
	/* nsecs_to_jiffies64() does not guard against overflow */
	if (NSEC_PER_SEC % HZ &&
	    div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ)
		return MAX_JIFFY_OFFSET;

4323 4324 4325
        return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
}

4326 4327 4328 4329 4330 4331 4332 4333
static inline unsigned long
timespec_to_jiffies_timeout(const struct timespec *value)
{
	unsigned long j = timespec_to_jiffies(value);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

4334 4335 4336 4337 4338 4339 4340 4341 4342
/*
 * If you need to wait X milliseconds between events A and B, but event B
 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
 * when event A happened, then just before event B you call this function and
 * pass the timestamp as the first argument, and X as the second argument.
 */
static inline void
wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
{
4343
	unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
4344 4345 4346 4347 4348 4349 4350 4351 4352 4353

	/*
	 * Don't re-read the value of "jiffies" every time since it may change
	 * behind our back and break the math.
	 */
	tmp_jiffies = jiffies;
	target_jiffies = timestamp_jiffies +
			 msecs_to_jiffies_timeout(to_wait_ms);

	if (time_after(target_jiffies, tmp_jiffies)) {
4354 4355 4356 4357
		remaining_jiffies = target_jiffies - tmp_jiffies;
		while (remaining_jiffies)
			remaining_jiffies =
			    schedule_timeout_uninterruptible(remaining_jiffies);
4358 4359
	}
}
4360 4361

static inline bool
4362
__i915_request_irq_complete(const struct drm_i915_gem_request *req)
4363
{
4364
	struct intel_engine_cs *engine = req->engine;
4365
	u32 seqno;
4366

4367 4368 4369 4370 4371 4372 4373 4374 4375
	/* Note that the engine may have wrapped around the seqno, and
	 * so our request->global_seqno will be ahead of the hardware,
	 * even though it completed the request before wrapping. We catch
	 * this by kicking all the waiters before resetting the seqno
	 * in hardware, and also signal the fence.
	 */
	if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &req->fence.flags))
		return true;

4376 4377 4378 4379 4380 4381 4382 4383 4384 4385
	/* The request was dequeued before we were awoken. We check after
	 * inspecting the hw to confirm that this was the same request
	 * that generated the HWS update. The memory barriers within
	 * the request execution are sufficient to ensure that a check
	 * after reading the value from hw matches this request.
	 */
	seqno = i915_gem_request_global_seqno(req);
	if (!seqno)
		return false;

4386 4387 4388
	/* Before we do the heavier coherent read of the seqno,
	 * check the value (hopefully) in the CPU cacheline.
	 */
4389
	if (__i915_gem_request_completed(req, seqno))
4390 4391
		return true;

4392 4393 4394 4395 4396 4397 4398 4399 4400 4401 4402
	/* Ensure our read of the seqno is coherent so that we
	 * do not "miss an interrupt" (i.e. if this is the last
	 * request and the seqno write from the GPU is not visible
	 * by the time the interrupt fires, we will see that the
	 * request is incomplete and go back to sleep awaiting
	 * another interrupt that will never come.)
	 *
	 * Strictly, we only need to do this once after an interrupt,
	 * but it is easier and safer to do it every time the waiter
	 * is woken.
	 */
4403
	if (engine->irq_seqno_barrier &&
4404
	    test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) {
4405
		struct intel_breadcrumbs *b = &engine->breadcrumbs;
4406

4407 4408 4409 4410 4411 4412 4413 4414 4415 4416 4417 4418
		/* The ordering of irq_posted versus applying the barrier
		 * is crucial. The clearing of the current irq_posted must
		 * be visible before we perform the barrier operation,
		 * such that if a subsequent interrupt arrives, irq_posted
		 * is reasserted and our task rewoken (which causes us to
		 * do another __i915_request_irq_complete() immediately
		 * and reapply the barrier). Conversely, if the clear
		 * occurs after the barrier, then an interrupt that arrived
		 * whilst we waited on the barrier would not trigger a
		 * barrier on the next pass, and the read may not see the
		 * seqno update.
		 */
4419
		engine->irq_seqno_barrier(engine);
4420 4421 4422 4423 4424 4425 4426

		/* If we consume the irq, but we are no longer the bottom-half,
		 * the real bottom-half may not have serialised their own
		 * seqno check with the irq-barrier (i.e. may have inspected
		 * the seqno before we believe it coherent since they see
		 * irq_posted == false but we are still running).
		 */
4427
		spin_lock_irq(&b->irq_lock);
4428
		if (b->irq_wait && b->irq_wait->tsk != current)
4429 4430 4431 4432 4433 4434
			/* Note that if the bottom-half is changed as we
			 * are sending the wake-up, the new bottom-half will
			 * be woken by whomever made the change. We only have
			 * to worry about when we steal the irq-posted for
			 * ourself.
			 */
4435
			wake_up_process(b->irq_wait->tsk);
4436
		spin_unlock_irq(&b->irq_lock);
4437

4438
		if (__i915_gem_request_completed(req, seqno))
4439 4440
			return true;
	}
4441 4442 4443 4444

	return false;
}

4445 4446 4447
void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);

4448 4449 4450 4451 4452 4453 4454 4455 4456 4457 4458 4459 4460 4461 4462 4463
/* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
 * perform the operation. To check beforehand, pass in the parameters to
 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
 * you only need to pass in the minor offsets, page-aligned pointers are
 * always valid.
 *
 * For just checking for SSE4.1, in the foreknowledge that the future use
 * will be correctly aligned, just use i915_has_memcpy_from_wc().
 */
#define i915_can_memcpy_from_wc(dst, src, len) \
	i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)

#define i915_has_memcpy_from_wc() \
	i915_memcpy_from_wc(NULL, NULL, 0)

4464 4465 4466 4467 4468
/* i915_mm.c */
int remap_io_mapping(struct vm_area_struct *vma,
		     unsigned long addr, unsigned long pfn, unsigned long size,
		     struct io_mapping *iomap);

4469 4470 4471 4472 4473 4474 4475 4476
static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
{
	if (INTEL_GEN(i915) >= 10)
		return CNL_HWS_CSB_WRITE_INDEX;
	else
		return I915_HWS_CSB_WRITE_INDEX;
}

L
Linus Torvalds 已提交
4477
#endif