i915_drv.h 120.6 KB
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/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
 */
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/*
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 *
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#ifndef _I915_DRV_H_
#define _I915_DRV_H_

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#include <uapi/drm/i915_drm.h>
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#include <uapi/drm/drm_fourcc.h>
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#include <linux/io-mapping.h>
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include <linux/backlight.h>
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#include <linux/hashtable.h>
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#include <linux/intel-iommu.h>
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#include <linux/kref.h>
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#include <linux/pm_qos.h>
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#include <linux/reservation.h>
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#include <linux/shmem_fs.h>

#include <drm/drmP.h>
#include <drm/intel-gtt.h>
#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
#include <drm/drm_gem.h>
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#include <drm/drm_auth.h>
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#include <drm/drm_cache.h>
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#include "i915_params.h"
#include "i915_reg.h"
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#include "i915_utils.h"
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#include "intel_uncore.h"
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#include "intel_bios.h"
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#include "intel_dpll_mgr.h"
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#include "intel_uc.h"
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#include "intel_lrc.h"
#include "intel_ringbuffer.h"

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#include "i915_gem.h"
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#include "i915_gem_context.h"
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#include "i915_gem_fence_reg.h"
#include "i915_gem_object.h"
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#include "i915_gem_gtt.h"
#include "i915_gem_render_state.h"
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#include "i915_gem_request.h"
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#include "i915_gem_timeline.h"
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#include "i915_vma.h"

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#include "intel_gvt.h"

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/* General customization:
 */

#define DRIVER_NAME		"i915"
#define DRIVER_DESC		"Intel Graphics"
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#define DRIVER_DATE		"20170502"
#define DRIVER_TIMESTAMP	1493710187
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/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
 * which may not necessarily be a user visible problem.  This will either
 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
 * enable distros and users to tailor their preferred amount of i915 abrt
 * spam.
 */
#define I915_STATE_WARN(condition, format...) ({			\
	int __ret_warn_on = !!(condition);				\
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	if (unlikely(__ret_warn_on))					\
		if (!WARN(i915.verbose_state_checks, format))		\
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			DRM_ERROR(format);				\
	unlikely(__ret_warn_on);					\
})

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#define I915_STATE_WARN_ON(x)						\
	I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
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bool __i915_inject_load_failure(const char *func, int line);
#define i915_inject_load_failure() \
	__i915_inject_load_failure(__func__, __LINE__)

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typedef struct {
	uint32_t val;
} uint_fixed_16_16_t;

#define FP_16_16_MAX ({ \
	uint_fixed_16_16_t fp; \
	fp.val = UINT_MAX; \
	fp; \
})

static inline uint_fixed_16_16_t u32_to_fixed_16_16(uint32_t val)
{
	uint_fixed_16_16_t fp;

	WARN_ON(val >> 16);

	fp.val = val << 16;
	return fp;
}

static inline uint32_t fixed_16_16_to_u32_round_up(uint_fixed_16_16_t fp)
{
	return DIV_ROUND_UP(fp.val, 1 << 16);
}

static inline uint32_t fixed_16_16_to_u32(uint_fixed_16_16_t fp)
{
	return fp.val >> 16;
}

static inline uint_fixed_16_16_t min_fixed_16_16(uint_fixed_16_16_t min1,
						 uint_fixed_16_16_t min2)
{
	uint_fixed_16_16_t min;

	min.val = min(min1.val, min2.val);
	return min;
}

static inline uint_fixed_16_16_t max_fixed_16_16(uint_fixed_16_16_t max1,
						 uint_fixed_16_16_t max2)
{
	uint_fixed_16_16_t max;

	max.val = max(max1.val, max2.val);
	return max;
}

static inline uint_fixed_16_16_t fixed_16_16_div_round_up(uint32_t val,
							  uint32_t d)
{
	uint_fixed_16_16_t fp, res;

	fp = u32_to_fixed_16_16(val);
	res.val = DIV_ROUND_UP(fp.val, d);
	return res;
}

static inline uint_fixed_16_16_t fixed_16_16_div_round_up_u64(uint32_t val,
							      uint32_t d)
{
	uint_fixed_16_16_t res;
	uint64_t interm_val;

	interm_val = (uint64_t)val << 16;
	interm_val = DIV_ROUND_UP_ULL(interm_val, d);
	WARN_ON(interm_val >> 32);
	res.val = (uint32_t) interm_val;

	return res;
}

static inline uint_fixed_16_16_t mul_u32_fixed_16_16(uint32_t val,
						     uint_fixed_16_16_t mul)
{
	uint64_t intermediate_val;
	uint_fixed_16_16_t fp;

	intermediate_val = (uint64_t) val * mul.val;
	WARN_ON(intermediate_val >> 32);
	fp.val = (uint32_t) intermediate_val;
	return fp;
}

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static inline const char *yesno(bool v)
{
	return v ? "yes" : "no";
}

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static inline const char *onoff(bool v)
{
	return v ? "on" : "off";
}

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static inline const char *enableddisabled(bool v)
{
	return v ? "enabled" : "disabled";
}

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enum pipe {
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	INVALID_PIPE = -1,
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	PIPE_A = 0,
	PIPE_B,
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	PIPE_C,
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	_PIPE_EDP,
	I915_MAX_PIPES = _PIPE_EDP
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};
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#define pipe_name(p) ((p) + 'A')
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enum transcoder {
	TRANSCODER_A = 0,
	TRANSCODER_B,
	TRANSCODER_C,
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	TRANSCODER_EDP,
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	TRANSCODER_DSI_A,
	TRANSCODER_DSI_C,
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	I915_MAX_TRANSCODERS
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};
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static inline const char *transcoder_name(enum transcoder transcoder)
{
	switch (transcoder) {
	case TRANSCODER_A:
		return "A";
	case TRANSCODER_B:
		return "B";
	case TRANSCODER_C:
		return "C";
	case TRANSCODER_EDP:
		return "EDP";
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	case TRANSCODER_DSI_A:
		return "DSI A";
	case TRANSCODER_DSI_C:
		return "DSI C";
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	default:
		return "<invalid>";
	}
}
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static inline bool transcoder_is_dsi(enum transcoder transcoder)
{
	return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
}

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/*
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 * Global legacy plane identifier. Valid only for primary/sprite
 * planes on pre-g4x, and only for primary planes on g4x+.
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 */
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enum plane {
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	PLANE_A,
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	PLANE_B,
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	PLANE_C,
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};
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#define plane_name(p) ((p) + 'A')
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#define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
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/*
 * Per-pipe plane identifier.
 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
 * number of planes per CRTC.  Not all platforms really have this many planes,
 * which means some arrays of size I915_MAX_PLANES may have unused entries
 * between the topmost sprite plane and the cursor plane.
 *
 * This is expected to be passed to various register macros
 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
 */
enum plane_id {
	PLANE_PRIMARY,
	PLANE_SPRITE0,
	PLANE_SPRITE1,
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	PLANE_SPRITE2,
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	PLANE_CURSOR,
	I915_MAX_PLANES,
};

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#define for_each_plane_id_on_crtc(__crtc, __p) \
	for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
		for_each_if ((__crtc)->plane_ids_mask & BIT(__p))

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enum port {
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	PORT_NONE = -1,
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	PORT_A = 0,
	PORT_B,
	PORT_C,
	PORT_D,
	PORT_E,
	I915_MAX_PORTS
};
#define port_name(p) ((p) + 'A')

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#define I915_NUM_PHYS_VLV 2
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enum dpio_channel {
	DPIO_CH0,
	DPIO_CH1
};

enum dpio_phy {
	DPIO_PHY0,
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	DPIO_PHY1,
	DPIO_PHY2,
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};

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enum intel_display_power_domain {
	POWER_DOMAIN_PIPE_A,
	POWER_DOMAIN_PIPE_B,
	POWER_DOMAIN_PIPE_C,
	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
	POWER_DOMAIN_TRANSCODER_A,
	POWER_DOMAIN_TRANSCODER_B,
	POWER_DOMAIN_TRANSCODER_C,
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	POWER_DOMAIN_TRANSCODER_EDP,
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	POWER_DOMAIN_TRANSCODER_DSI_A,
	POWER_DOMAIN_TRANSCODER_DSI_C,
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	POWER_DOMAIN_PORT_DDI_A_LANES,
	POWER_DOMAIN_PORT_DDI_B_LANES,
	POWER_DOMAIN_PORT_DDI_C_LANES,
	POWER_DOMAIN_PORT_DDI_D_LANES,
	POWER_DOMAIN_PORT_DDI_E_LANES,
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	POWER_DOMAIN_PORT_DDI_A_IO,
	POWER_DOMAIN_PORT_DDI_B_IO,
	POWER_DOMAIN_PORT_DDI_C_IO,
	POWER_DOMAIN_PORT_DDI_D_IO,
	POWER_DOMAIN_PORT_DDI_E_IO,
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	POWER_DOMAIN_PORT_DSI,
	POWER_DOMAIN_PORT_CRT,
	POWER_DOMAIN_PORT_OTHER,
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	POWER_DOMAIN_VGA,
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	POWER_DOMAIN_AUDIO,
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	POWER_DOMAIN_PLLS,
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	POWER_DOMAIN_AUX_A,
	POWER_DOMAIN_AUX_B,
	POWER_DOMAIN_AUX_C,
	POWER_DOMAIN_AUX_D,
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	POWER_DOMAIN_GMBUS,
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	POWER_DOMAIN_MODESET,
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	POWER_DOMAIN_INIT,
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	POWER_DOMAIN_NUM,
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};

#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
		((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
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#define POWER_DOMAIN_TRANSCODER(tran) \
	((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
	 (tran) + POWER_DOMAIN_TRANSCODER_A)
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enum hpd_pin {
	HPD_NONE = 0,
	HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
	HPD_CRT,
	HPD_SDVO_B,
	HPD_SDVO_C,
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	HPD_PORT_A,
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	HPD_PORT_B,
	HPD_PORT_C,
	HPD_PORT_D,
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	HPD_PORT_E,
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	HPD_NUM_PINS
};

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#define for_each_hpd_pin(__pin) \
	for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)

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#define HPD_STORM_DEFAULT_THRESHOLD 5

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struct i915_hotplug {
	struct work_struct hotplug_work;

	struct {
		unsigned long last_jiffies;
		int count;
		enum {
			HPD_ENABLED = 0,
			HPD_DISABLED = 1,
			HPD_MARK_DISABLED = 2
		} state;
	} stats[HPD_NUM_PINS];
	u32 event_bits;
	struct delayed_work reenable_work;

	struct intel_digital_port *irq_port[I915_MAX_PORTS];
	u32 long_port_mask;
	u32 short_port_mask;
	struct work_struct dig_port_work;

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	struct work_struct poll_init_work;
	bool poll_enabled;

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	unsigned int hpd_storm_threshold;

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	/*
	 * if we get a HPD irq from DP and a HPD irq from non-DP
	 * the non-DP HPD could block the workqueue on a mode config
	 * mutex getting, that userspace may have taken. However
	 * userspace is waiting on the DP workqueue to run which is
	 * blocked behind the non-DP one.
	 */
	struct workqueue_struct *dp_wq;
};

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#define I915_GEM_GPU_DOMAINS \
	(I915_GEM_DOMAIN_RENDER | \
	 I915_GEM_DOMAIN_SAMPLER | \
	 I915_GEM_DOMAIN_COMMAND | \
	 I915_GEM_DOMAIN_INSTRUCTION | \
	 I915_GEM_DOMAIN_VERTEX)
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#define for_each_pipe(__dev_priv, __p) \
	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
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#define for_each_pipe_masked(__dev_priv, __p, __mask) \
	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
		for_each_if ((__mask) & (1 << (__p)))
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#define for_each_universal_plane(__dev_priv, __pipe, __p)		\
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	for ((__p) = 0;							\
	     (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1;	\
	     (__p)++)
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#define for_each_sprite(__dev_priv, __p, __s)				\
	for ((__s) = 0;							\
	     (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)];	\
	     (__s)++)
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#define for_each_port_masked(__port, __ports_mask) \
	for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)	\
		for_each_if ((__ports_mask) & (1 << (__port)))

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#define for_each_crtc(dev, crtc) \
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	list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
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#define for_each_intel_plane(dev, intel_plane) \
	list_for_each_entry(intel_plane,			\
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			    &(dev)->mode_config.plane_list,	\
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			    base.head)

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#define for_each_intel_plane_mask(dev, intel_plane, plane_mask)		\
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	list_for_each_entry(intel_plane,				\
			    &(dev)->mode_config.plane_list,		\
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			    base.head)					\
		for_each_if ((plane_mask) &				\
			     (1 << drm_plane_index(&intel_plane->base)))

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#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)	\
	list_for_each_entry(intel_plane,				\
			    &(dev)->mode_config.plane_list,		\
			    base.head)					\
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		for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
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#define for_each_intel_crtc(dev, intel_crtc)				\
	list_for_each_entry(intel_crtc,					\
			    &(dev)->mode_config.crtc_list,		\
			    base.head)
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#define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask)		\
	list_for_each_entry(intel_crtc,					\
			    &(dev)->mode_config.crtc_list,		\
			    base.head)					\
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		for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))

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#define for_each_intel_encoder(dev, intel_encoder)		\
	list_for_each_entry(intel_encoder,			\
			    &(dev)->mode_config.encoder_list,	\
			    base.head)

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#define for_each_intel_connector_iter(intel_connector, iter) \
	while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))

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#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
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		for_each_if ((intel_encoder)->base.crtc == (__crtc))
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#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
	list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
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		for_each_if ((intel_connector)->base.encoder == (__encoder))
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#define for_each_power_domain(domain, mask)				\
	for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)	\
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		for_each_if (BIT_ULL(domain) & (mask))
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#define for_each_power_well(__dev_priv, __power_well)				\
	for ((__power_well) = (__dev_priv)->power_domains.power_wells;	\
	     (__power_well) - (__dev_priv)->power_domains.power_wells <	\
		(__dev_priv)->power_domains.power_well_count;		\
	     (__power_well)++)

#define for_each_power_well_rev(__dev_priv, __power_well)			\
	for ((__power_well) = (__dev_priv)->power_domains.power_wells +		\
			      (__dev_priv)->power_domains.power_well_count - 1;	\
	     (__power_well) - (__dev_priv)->power_domains.power_wells >= 0;	\
	     (__power_well)--)

#define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask)	\
	for_each_power_well(__dev_priv, __power_well)				\
		for_each_if ((__power_well)->domains & (__domain_mask))

#define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \
	for_each_power_well_rev(__dev_priv, __power_well)		        \
		for_each_if ((__power_well)->domains & (__domain_mask))

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#define for_each_intel_plane_in_state(__state, plane, plane_state, __i) \
	for ((__i) = 0; \
	     (__i) < (__state)->base.dev->mode_config.num_total_plane && \
		     ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
		      (plane_state) = to_intel_plane_state((__state)->base.planes[__i].state), 1); \
	     (__i)++) \
		for_each_if (plane_state)

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struct drm_i915_private;
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struct i915_mm_struct;
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struct i915_mmu_object;
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struct drm_i915_file_private {
	struct drm_i915_private *dev_priv;
	struct drm_file *file;

	struct {
		spinlock_t lock;
		struct list_head request_list;
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/* 20ms is a fairly arbitrary limit (greater than the average frame time)
 * chosen to prevent the CPU getting more than a frame ahead of the GPU
 * (when using lax throttling for the frontbuffer). We also use it to
 * offer free GPU waitboosts for severely congested workloads.
 */
#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
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	} mm;
	struct idr context_idr;

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	struct intel_rps_client {
		struct list_head link;
		unsigned boosts;
	} rps;
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	unsigned int bsd_engine;
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/* Client can have a maximum of 3 contexts banned before
 * it is denied of creating new contexts. As one context
 * ban needs 4 consecutive hangs, and more if there is
 * progress in between, this is a last resort stop gap measure
 * to limit the badly behaving clients access to gpu.
 */
#define I915_MAX_CLIENT_CONTEXT_BANS 3
	int context_bans;
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};

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/* Used by dp and fdi links */
struct intel_link_m_n {
	uint32_t	tu;
	uint32_t	gmch_m;
	uint32_t	gmch_n;
	uint32_t	link_m;
	uint32_t	link_n;
};

void intel_link_compute_m_n(int bpp, int nlanes,
			    int pixel_clock, int link_clock,
			    struct intel_link_m_n *m_n);

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/* Interface history:
 *
 * 1.1: Original.
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 * 1.2: Add Power Management
 * 1.3: Add vblank support
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 * 1.4: Fix cmdbuffer path, add heap destroy
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 * 1.5: Add vblank pipe configuration
=
=?utf-8?q?Michel_D=C3=A4nzer?= 已提交
575 576
 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 *      - Support vertical blank on secondary display pipe
L
Linus Torvalds 已提交
577 578
 */
#define DRIVER_MAJOR		1
=
=?utf-8?q?Michel_D=C3=A4nzer?= 已提交
579
#define DRIVER_MINOR		6
L
Linus Torvalds 已提交
580 581
#define DRIVER_PATCHLEVEL	0

582 583 584 585 586
struct opregion_header;
struct opregion_acpi;
struct opregion_swsci;
struct opregion_asle;

587
struct intel_opregion {
588 589 590
	struct opregion_header *header;
	struct opregion_acpi *acpi;
	struct opregion_swsci *swsci;
J
Jani Nikula 已提交
591 592
	u32 swsci_gbda_sub_functions;
	u32 swsci_sbcb_sub_functions;
593
	struct opregion_asle *asle;
594
	void *rvda;
595
	const void *vbt;
596
	u32 vbt_size;
597
	u32 *lid_state;
598
	struct work_struct asle_work;
599
};
600
#define OPREGION_SIZE            (8*1024)
601

602 603 604
struct intel_overlay;
struct intel_overlay_error_state;

605
struct sdvo_device_mapping {
C
Chris Wilson 已提交
606
	u8 initialized;
607 608 609
	u8 dvo_port;
	u8 slave_addr;
	u8 dvo_wiring;
C
Chris Wilson 已提交
610
	u8 i2c_pin;
611
	u8 ddc_pin;
612 613
};

614
struct intel_connector;
615
struct intel_encoder;
616
struct intel_atomic_state;
617
struct intel_crtc_state;
618
struct intel_initial_plane_config;
619
struct intel_crtc;
620 621
struct intel_limit;
struct dpll;
622
struct intel_cdclk_state;
623

624
struct drm_i915_display_funcs {
625 626
	void (*get_cdclk)(struct drm_i915_private *dev_priv,
			  struct intel_cdclk_state *cdclk_state);
627 628
	void (*set_cdclk)(struct drm_i915_private *dev_priv,
			  const struct intel_cdclk_state *cdclk_state);
629
	int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane);
630
	int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
631 632 633
	int (*compute_intermediate_wm)(struct drm_device *dev,
				       struct intel_crtc *intel_crtc,
				       struct intel_crtc_state *newstate);
634 635 636 637 638 639
	void (*initial_watermarks)(struct intel_atomic_state *state,
				   struct intel_crtc_state *cstate);
	void (*atomic_update_watermarks)(struct intel_atomic_state *state,
					 struct intel_crtc_state *cstate);
	void (*optimize_watermarks)(struct intel_atomic_state *state,
				    struct intel_crtc_state *cstate);
640
	int (*compute_global_watermarks)(struct drm_atomic_state *state);
641
	void (*update_wm)(struct intel_crtc *crtc);
642
	int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
643 644 645
	/* Returns the active state of the crtc, and if the crtc is active,
	 * fills out the pipe-config with the hw state. */
	bool (*get_pipe_config)(struct intel_crtc *,
646
				struct intel_crtc_state *);
647 648
	void (*get_initial_plane_config)(struct intel_crtc *,
					 struct intel_initial_plane_config *);
649 650
	int (*crtc_compute_clock)(struct intel_crtc *crtc,
				  struct intel_crtc_state *crtc_state);
651 652 653 654
	void (*crtc_enable)(struct intel_crtc_state *pipe_config,
			    struct drm_atomic_state *old_state);
	void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
			     struct drm_atomic_state *old_state);
655 656
	void (*update_crtcs)(struct drm_atomic_state *state,
			     unsigned int *crtc_vblank_mask);
657 658
	void (*audio_codec_enable)(struct drm_connector *connector,
				   struct intel_encoder *encoder,
659
				   const struct drm_display_mode *adjusted_mode);
660
	void (*audio_codec_disable)(struct intel_encoder *encoder);
661 662
	void (*fdi_link_train)(struct intel_crtc *crtc,
			       const struct intel_crtc_state *crtc_state);
663
	void (*init_clock_gating)(struct drm_i915_private *dev_priv);
664 665 666 667 668
	int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
			  struct drm_framebuffer *fb,
			  struct drm_i915_gem_object *obj,
			  struct drm_i915_gem_request *req,
			  uint32_t flags);
669
	void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
670 671 672 673 674
	/* clock updates for mode set */
	/* cursor updates */
	/* render clock increase/decrease */
	/* display clock increase/decrease */
	/* pll clock increase/decrease */
675

676 677
	void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
	void (*load_luts)(struct drm_crtc_state *crtc_state);
678 679
};

680 681 682 683
#define CSR_VERSION(major, minor)	((major) << 16 | (minor))
#define CSR_VERSION_MAJOR(version)	((version) >> 16)
#define CSR_VERSION_MINOR(version)	((version) & 0xffff)

684
struct intel_csr {
685
	struct work_struct work;
686
	const char *fw_path;
687
	uint32_t *dmc_payload;
688
	uint32_t dmc_fw_size;
689
	uint32_t version;
690
	uint32_t mmio_count;
691
	i915_reg_t mmioaddr[8];
692
	uint32_t mmiodata[8];
693
	uint32_t dc_state;
694
	uint32_t allowed_dc_mask;
695 696
};

697 698
#define DEV_INFO_FOR_EACH_FLAG(func) \
	func(is_mobile); \
699
	func(is_lp); \
700
	func(is_alpha_support); \
701
	/* Keep has_* in alphabetical order */ \
702
	func(has_64bit_reloc); \
703
	func(has_aliasing_ppgtt); \
704
	func(has_csr); \
705
	func(has_ddi); \
706
	func(has_decoupled_mmio); \
707
	func(has_dp_mst); \
708 709
	func(has_fbc); \
	func(has_fpga_dbg); \
710 711
	func(has_full_ppgtt); \
	func(has_full_48bit_ppgtt); \
712 713 714 715
	func(has_gmbus_irq); \
	func(has_gmch_display); \
	func(has_guc); \
	func(has_hotplug); \
716
	func(has_l3_dpf); \
717
	func(has_llc); \
718 719 720 721 722 723 724 725 726
	func(has_logical_ring_contexts); \
	func(has_overlay); \
	func(has_pipe_cxsr); \
	func(has_pooled_eu); \
	func(has_psr); \
	func(has_rc6); \
	func(has_rc6p); \
	func(has_resource_streamer); \
	func(has_runtime_pm); \
727
	func(has_snoop); \
728
	func(unfenced_needs_alignment); \
729 730 731
	func(cursor_needs_physical); \
	func(hws_needs_physical); \
	func(overlay_needs_physical); \
732
	func(supports_tv);
D
Daniel Vetter 已提交
733

734
struct sseu_dev_info {
735
	u8 slice_mask;
736
	u8 subslice_mask;
737 738
	u8 eu_total;
	u8 eu_per_subslice;
739 740 741 742 743 744
	u8 min_eu_in_pool;
	/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
	u8 subslice_7eu[3];
	u8 has_slice_pg:1;
	u8 has_subslice_pg:1;
	u8 has_eu_pg:1;
745 746
};

747 748 749 750 751
static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
{
	return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
}

752 753 754 755 756 757 758 759 760 761 762 763 764
/* Keep in gen based order, and chronological order within a gen */
enum intel_platform {
	INTEL_PLATFORM_UNINITIALIZED = 0,
	INTEL_I830,
	INTEL_I845G,
	INTEL_I85X,
	INTEL_I865G,
	INTEL_I915G,
	INTEL_I915GM,
	INTEL_I945G,
	INTEL_I945GM,
	INTEL_G33,
	INTEL_PINEVIEW,
765 766
	INTEL_I965G,
	INTEL_I965GM,
767 768
	INTEL_G45,
	INTEL_GM45,
769 770 771 772 773 774 775 776 777 778 779
	INTEL_IRONLAKE,
	INTEL_SANDYBRIDGE,
	INTEL_IVYBRIDGE,
	INTEL_VALLEYVIEW,
	INTEL_HASWELL,
	INTEL_BROADWELL,
	INTEL_CHERRYVIEW,
	INTEL_SKYLAKE,
	INTEL_BROXTON,
	INTEL_KABYLAKE,
	INTEL_GEMINILAKE,
780
	INTEL_MAX_PLATFORMS
781 782
};

783
struct intel_device_info {
784
	u32 display_mmio_offset;
785
	u16 device_id;
786
	u8 num_pipes;
787
	u8 num_sprites[I915_MAX_PIPES];
788
	u8 num_scalers[I915_MAX_PIPES];
789
	u8 gen;
790
	u16 gen_mask;
791
	enum intel_platform platform;
792
	u8 ring_mask; /* Rings supported by the HW */
793
	u8 num_rings;
794 795 796
#define DEFINE_FLAG(name) u8 name:1
	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
#undef DEFINE_FLAG
797
	u16 ddb_size; /* in blocks */
798 799 800 801
	/* Register offsets for the various display pipes and transcoders */
	int pipe_offsets[I915_MAX_TRANSCODERS];
	int trans_offsets[I915_MAX_TRANSCODERS];
	int palette_offsets[I915_MAX_PIPES];
802
	int cursor_offsets[I915_MAX_PIPES];
803 804

	/* Slice/subslice/EU info */
805
	struct sseu_dev_info sseu;
806 807 808 809 810

	struct color_luts {
		u16 degamma_lut_size;
		u16 gamma_lut_size;
	} color;
811 812
};

813 814
struct intel_display_error_state;

815
struct i915_gpu_state {
816 817
	struct kref ref;
	struct timeval time;
818 819
	struct timeval boottime;
	struct timeval uptime;
820

821 822
	struct drm_i915_private *i915;

823 824
	char error_msg[128];
	bool simulated;
825
	bool awake;
826 827
	bool wakelock;
	bool suspended;
828 829 830 831
	int iommu;
	u32 reset_count;
	u32 suspend_count;
	struct intel_device_info device_info;
832
	struct i915_params params;
833 834 835 836 837

	/* Generic register state */
	u32 eir;
	u32 pgtbl_er;
	u32 ier;
838
	u32 gtier[4], ngtier;
839 840 841 842 843 844 845 846 847 848 849 850
	u32 ccid;
	u32 derrmr;
	u32 forcewake;
	u32 error; /* gen6+ */
	u32 err_int; /* gen7 */
	u32 fault_data0; /* gen8, gen9 */
	u32 fault_data1; /* gen8, gen9 */
	u32 done_reg;
	u32 gac_eco;
	u32 gam_ecochk;
	u32 gab_ctl;
	u32 gfx_mode;
851

852
	u32 nfence;
853 854 855
	u64 fence[I915_MAX_NUM_FENCES];
	struct intel_overlay_error_state *overlay;
	struct intel_display_error_state *display;
856
	struct drm_i915_error_object *semaphore;
857
	struct drm_i915_error_object *guc_log;
858 859 860 861 862 863

	struct drm_i915_error_engine {
		int engine_id;
		/* Software tracked state */
		bool waiting;
		int num_waiters;
864 865
		unsigned long hangcheck_timestamp;
		bool hangcheck_stalled;
866 867 868 869
		enum intel_engine_hangcheck_action hangcheck_action;
		struct i915_address_space *vm;
		int num_requests;

870 871 872
		/* position of active request inside the ring */
		u32 rq_head, rq_post, rq_tail;

873 874 875 876 877 878 879 880 881 882 883
		/* our own tracking of ring head and tail */
		u32 cpu_ring_head;
		u32 cpu_ring_tail;

		u32 last_seqno;

		/* Register state */
		u32 start;
		u32 tail;
		u32 head;
		u32 ctl;
884
		u32 mode;
885 886 887 888 889 890 891 892 893 894 895 896 897
		u32 hws;
		u32 ipeir;
		u32 ipehr;
		u32 bbstate;
		u32 instpm;
		u32 instps;
		u32 seqno;
		u64 bbaddr;
		u64 acthd;
		u32 fault_reg;
		u64 faddr;
		u32 rc_psmi; /* sleep state */
		u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
898
		struct intel_instdone instdone;
899

900 901 902 903 904 905 906 907 908 909
		struct drm_i915_error_context {
			char comm[TASK_COMM_LEN];
			pid_t pid;
			u32 handle;
			u32 hw_id;
			int ban_score;
			int active;
			int guilty;
		} context;

910 911
		struct drm_i915_error_object {
			u64 gtt_offset;
912
			u64 gtt_size;
913 914
			int page_count;
			int unused;
915 916 917
			u32 *pages[0];
		} *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;

918 919 920
		struct drm_i915_error_object **user_bo;
		long user_bo_count;

921 922 923 924
		struct drm_i915_error_object *wa_ctx;

		struct drm_i915_error_request {
			long jiffies;
925
			pid_t pid;
926
			u32 context;
927
			int ban_score;
928 929 930
			u32 seqno;
			u32 head;
			u32 tail;
931
		} *requests, execlist[2];
932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966

		struct drm_i915_error_waiter {
			char comm[TASK_COMM_LEN];
			pid_t pid;
			u32 seqno;
		} *waiters;

		struct {
			u32 gfx_mode;
			union {
				u64 pdp[4];
				u32 pp_dir_base;
			};
		} vm_info;
	} engine[I915_NUM_ENGINES];

	struct drm_i915_error_buffer {
		u32 size;
		u32 name;
		u32 rseqno[I915_NUM_ENGINES], wseqno;
		u64 gtt_offset;
		u32 read_domains;
		u32 write_domain;
		s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
		u32 tiling:2;
		u32 dirty:1;
		u32 purgeable:1;
		u32 userptr:1;
		s32 engine:4;
		u32 cache_level:3;
	} *active_bo[I915_NUM_ENGINES], *pinned_bo;
	u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
	struct i915_address_space *active_vm[I915_NUM_ENGINES];
};

967 968
enum i915_cache_level {
	I915_CACHE_NONE = 0,
969 970 971 972 973
	I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
	I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
			      caches, eg sampler/render caches, and the
			      large Last-Level-Cache. LLC is coherent with
			      the CPU, but L3 is only visible to the GPU. */
974
	I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
975 976
};

977 978
#define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */

979 980 981 982 983
enum fb_op_origin {
	ORIGIN_GTT,
	ORIGIN_CPU,
	ORIGIN_CS,
	ORIGIN_FLIP,
984
	ORIGIN_DIRTYFB,
985 986
};

987
struct intel_fbc {
P
Paulo Zanoni 已提交
988 989 990
	/* This is always the inner lock when overlapping with struct_mutex and
	 * it's the outer lock when overlapping with stolen_lock. */
	struct mutex lock;
B
Ben Widawsky 已提交
991
	unsigned threshold;
992 993
	unsigned int possible_framebuffer_bits;
	unsigned int busy_bits;
994
	unsigned int visible_pipes_mask;
995
	struct intel_crtc *crtc;
996

997
	struct drm_mm_node compressed_fb;
998 999
	struct drm_mm_node *compressed_llb;

1000 1001
	bool false_color;

1002
	bool enabled;
1003
	bool active;
1004

1005 1006 1007
	bool underrun_detected;
	struct work_struct underrun_work;

1008
	struct intel_fbc_state_cache {
1009 1010
		struct i915_vma *vma;

1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023
		struct {
			unsigned int mode_flags;
			uint32_t hsw_bdw_pixel_rate;
		} crtc;

		struct {
			unsigned int rotation;
			int src_w;
			int src_h;
			bool visible;
		} plane;

		struct {
1024
			const struct drm_format_info *format;
1025 1026 1027 1028
			unsigned int stride;
		} fb;
	} state_cache;

1029
	struct intel_fbc_reg_params {
1030 1031
		struct i915_vma *vma;

1032 1033 1034 1035 1036 1037 1038
		struct {
			enum pipe pipe;
			enum plane plane;
			unsigned int fence_y_offset;
		} crtc;

		struct {
1039
			const struct drm_format_info *format;
1040 1041 1042 1043 1044 1045
			unsigned int stride;
		} fb;

		int cfb_size;
	} params;

1046
	struct intel_fbc_work {
1047
		bool scheduled;
1048
		u32 scheduled_vblank;
1049 1050
		struct work_struct work;
	} work;
1051

1052
	const char *no_fbc_reason;
1053 1054
};

1055
/*
1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069
 * HIGH_RR is the highest eDP panel refresh rate read from EDID
 * LOW_RR is the lowest eDP panel refresh rate found from EDID
 * parsing for same resolution.
 */
enum drrs_refresh_rate_type {
	DRRS_HIGH_RR,
	DRRS_LOW_RR,
	DRRS_MAX_RR, /* RR count */
};

enum drrs_support_type {
	DRRS_NOT_SUPPORTED = 0,
	STATIC_DRRS_SUPPORT = 1,
	SEAMLESS_DRRS_SUPPORT = 2
1070 1071
};

1072
struct intel_dp;
1073 1074 1075 1076 1077 1078 1079 1080 1081
struct i915_drrs {
	struct mutex mutex;
	struct delayed_work work;
	struct intel_dp *dp;
	unsigned busy_frontbuffer_bits;
	enum drrs_refresh_rate_type refresh_rate_type;
	enum drrs_support_type type;
};

R
Rodrigo Vivi 已提交
1082
struct i915_psr {
1083
	struct mutex lock;
R
Rodrigo Vivi 已提交
1084 1085
	bool sink_support;
	bool source_ok;
1086
	struct intel_dp *enabled;
1087 1088
	bool active;
	struct delayed_work work;
1089
	unsigned busy_frontbuffer_bits;
1090 1091
	bool psr2_support;
	bool aux_frame_sync;
1092
	bool link_standby;
1093 1094
	bool y_cord_support;
	bool colorimetry_support;
1095
	bool alpm;
1096
};
1097

1098
enum intel_pch {
1099
	PCH_NONE = 0,	/* No PCH present */
1100 1101
	PCH_IBX,	/* Ibexpeak PCH */
	PCH_CPT,	/* Cougarpoint PCH */
1102
	PCH_LPT,	/* Lynxpoint PCH */
1103
	PCH_SPT,        /* Sunrisepoint PCH */
1104
	PCH_KBP,        /* Kabypoint PCH */
B
Ben Widawsky 已提交
1105
	PCH_NOP,
1106 1107
};

1108 1109 1110 1111 1112
enum intel_sbi_destination {
	SBI_ICLK,
	SBI_MPHY,
};

1113
#define QUIRK_PIPEA_FORCE (1<<0)
1114
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
1115
#define QUIRK_INVERT_BRIGHTNESS (1<<2)
1116
#define QUIRK_BACKLIGHT_PRESENT (1<<3)
1117
#define QUIRK_PIPEB_FORCE (1<<4)
1118
#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1119

1120
struct intel_fbdev;
1121
struct intel_fbc_work;
1122

1123 1124
struct intel_gmbus {
	struct i2c_adapter adapter;
1125
#define GMBUS_FORCE_BIT_RETRY (1U << 31)
1126
	u32 force_bit;
1127
	u32 reg0;
1128
	i915_reg_t gpio_reg;
1129
	struct i2c_algo_bit_data bit_algo;
1130 1131 1132
	struct drm_i915_private *dev_priv;
};

1133
struct i915_suspend_saved_registers {
1134
	u32 saveDSPARB;
J
Jesse Barnes 已提交
1135
	u32 saveFBC_CONTROL;
1136 1137
	u32 saveCACHE_MODE_0;
	u32 saveMI_ARB_STATE;
J
Jesse Barnes 已提交
1138 1139
	u32 saveSWF0[16];
	u32 saveSWF1[16];
1140
	u32 saveSWF3[3];
1141
	uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1142
	u32 savePCH_PORT_HOTPLUG;
1143
	u16 saveGCDGMBUS;
1144
};
1145

1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203
struct vlv_s0ix_state {
	/* GAM */
	u32 wr_watermark;
	u32 gfx_prio_ctrl;
	u32 arb_mode;
	u32 gfx_pend_tlb0;
	u32 gfx_pend_tlb1;
	u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
	u32 media_max_req_count;
	u32 gfx_max_req_count;
	u32 render_hwsp;
	u32 ecochk;
	u32 bsd_hwsp;
	u32 blt_hwsp;
	u32 tlb_rd_addr;

	/* MBC */
	u32 g3dctl;
	u32 gsckgctl;
	u32 mbctl;

	/* GCP */
	u32 ucgctl1;
	u32 ucgctl3;
	u32 rcgctl1;
	u32 rcgctl2;
	u32 rstctl;
	u32 misccpctl;

	/* GPM */
	u32 gfxpause;
	u32 rpdeuhwtc;
	u32 rpdeuc;
	u32 ecobus;
	u32 pwrdwnupctl;
	u32 rp_down_timeout;
	u32 rp_deucsw;
	u32 rcubmabdtmr;
	u32 rcedata;
	u32 spare2gh;

	/* Display 1 CZ domain */
	u32 gt_imr;
	u32 gt_ier;
	u32 pm_imr;
	u32 pm_ier;
	u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];

	/* GT SA CZ domain */
	u32 tilectl;
	u32 gt_fifoctl;
	u32 gtlc_wake_ctrl;
	u32 gtlc_survive;
	u32 pmwgicz;

	/* Display 2 CZ domain */
	u32 gu_ctl0;
	u32 gu_ctl1;
1204
	u32 pcbr;
1205 1206 1207
	u32 clock_gate_dis2;
};

1208
struct intel_rps_ei {
1209
	ktime_t ktime;
1210 1211
	u32 render_c0;
	u32 media_c0;
1212 1213
};

1214
struct intel_gen6_power_mgmt {
I
Imre Deak 已提交
1215 1216 1217 1218
	/*
	 * work, interrupts_enabled and pm_iir are protected by
	 * dev_priv->irq_lock
	 */
1219
	struct work_struct work;
I
Imre Deak 已提交
1220
	bool interrupts_enabled;
1221
	u32 pm_iir;
1222

1223
	/* PM interrupt bits that should never be masked */
1224
	u32 pm_intrmsk_mbz;
1225

1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240
	/* Frequencies are stored in potentially platform dependent multiples.
	 * In other words, *_freq needs to be multiplied by X to be interesting.
	 * Soft limits are those which are used for the dynamic reclocking done
	 * by the driver (raise frequencies under heavy loads, and lower for
	 * lighter loads). Hard limits are those imposed by the hardware.
	 *
	 * A distinction is made for overclocking, which is never enabled by
	 * default, and is considered to be above the hard limit if it's
	 * possible at all.
	 */
	u8 cur_freq;		/* Current frequency (cached, may not == HW) */
	u8 min_freq_softlimit;	/* Minimum frequency permitted by the driver */
	u8 max_freq_softlimit;	/* Max frequency permitted by the driver */
	u8 max_freq;		/* Maximum frequency, RP0 if not overclocking */
	u8 min_freq;		/* AKA RPn. Minimum frequency */
1241
	u8 boost_freq;		/* Frequency to request when wait boosting */
1242
	u8 idle_freq;		/* Frequency to request when we are idle */
1243 1244 1245
	u8 efficient_freq;	/* AKA RPe. Pre-determined balanced frequency */
	u8 rp1_freq;		/* "less than" RP0 power/freqency */
	u8 rp0_freq;		/* Non-overclocked max frequency. */
1246
	u16 gpll_ref_freq;	/* vlv/chv GPLL reference frequency */
1247

1248 1249 1250
	u8 up_threshold; /* Current %busy required to uplock */
	u8 down_threshold; /* Current %busy required to downclock */

1251 1252 1253
	int last_adj;
	enum { LOW_POWER, BETWEEN, HIGH_POWER } power;

1254 1255 1256 1257
	spinlock_t client_lock;
	struct list_head clients;
	bool client_boost;

1258
	bool enabled;
1259
	struct delayed_work autoenable_work;
1260
	unsigned boosts;
1261

1262
	/* manual wa residency calculations */
1263
	struct intel_rps_ei ei;
1264

1265 1266
	/*
	 * Protects RPS/RC6 register access and PCU communication.
1267 1268 1269
	 * Must be taken after struct_mutex if nested. Note that
	 * this lock may be held for long periods of time when
	 * talking to hw - so only take it when talking to hw!
1270 1271
	 */
	struct mutex hw_lock;
1272 1273
};

D
Daniel Vetter 已提交
1274 1275 1276
/* defined intel_pm.c */
extern spinlock_t mchdev_lock;

1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287
struct intel_ilk_power_mgmt {
	u8 cur_delay;
	u8 min_delay;
	u8 max_delay;
	u8 fmax;
	u8 fstart;

	u64 last_count1;
	unsigned long last_time1;
	unsigned long chipset_power;
	u64 last_count2;
1288
	u64 last_time2;
1289 1290 1291 1292 1293 1294 1295
	unsigned long gfx_power;
	u8 corr;

	int c_m;
	int r_t;
};

1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325
struct drm_i915_private;
struct i915_power_well;

struct i915_power_well_ops {
	/*
	 * Synchronize the well's hw state to match the current sw state, for
	 * example enable/disable it based on the current refcount. Called
	 * during driver init and resume time, possibly after first calling
	 * the enable/disable handlers.
	 */
	void (*sync_hw)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/*
	 * Enable the well and resources that depend on it (for example
	 * interrupts located on the well). Called after the 0->1 refcount
	 * transition.
	 */
	void (*enable)(struct drm_i915_private *dev_priv,
		       struct i915_power_well *power_well);
	/*
	 * Disable the well and resources that depend on it. Called after
	 * the 1->0 refcount transition.
	 */
	void (*disable)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/* Returns the hw enabled state. */
	bool (*is_enabled)(struct drm_i915_private *dev_priv,
			   struct i915_power_well *power_well);
};

1326 1327
/* Power well structure for haswell */
struct i915_power_well {
1328
	const char *name;
1329
	bool always_on;
1330 1331
	/* power well enable/disable usage count */
	int count;
1332 1333
	/* cached hw enabled state */
	bool hw_enabled;
1334
	u64 domains;
1335 1336
	/* unique identifier for this power well */
	unsigned long id;
1337 1338 1339 1340 1341
	/*
	 * Arbitraty data associated with this power well. Platform and power
	 * well specific.
	 */
	unsigned long data;
1342
	const struct i915_power_well_ops *ops;
1343 1344
};

1345
struct i915_power_domains {
1346 1347 1348 1349 1350
	/*
	 * Power wells needed for initialization at driver init and suspend
	 * time are on. They are kept on until after the first modeset.
	 */
	bool init_power_on;
1351
	bool initializing;
1352
	int power_well_count;
1353

1354
	struct mutex lock;
1355
	int domain_use_count[POWER_DOMAIN_NUM];
1356
	struct i915_power_well *power_wells;
1357 1358
};

1359
#define MAX_L3_SLICES 2
1360
struct intel_l3_parity {
1361
	u32 *remap_info[MAX_L3_SLICES];
1362
	struct work_struct error_work;
1363
	int which_slice;
1364 1365
};

1366 1367 1368
struct i915_gem_mm {
	/** Memory allocator for GTT stolen memory */
	struct drm_mm stolen;
1369 1370 1371 1372
	/** Protects the usage of the GTT stolen memory allocator. This is
	 * always the inner lock when overlapping with struct_mutex. */
	struct mutex stolen_lock;

1373 1374 1375 1376 1377
	/** List of all objects in gtt_space. Used to restore gtt
	 * mappings on resume */
	struct list_head bound_list;
	/**
	 * List of objects which are not bound to the GTT (thus
1378 1379
	 * are idle and not used by the GPU). These objects may or may
	 * not actually have any pages attached.
1380 1381 1382
	 */
	struct list_head unbound_list;

1383 1384 1385 1386 1387
	/** List of all objects in gtt_space, currently mmaped by userspace.
	 * All objects within this list must also be on bound_list.
	 */
	struct list_head userfault_list;

1388 1389 1390 1391 1392 1393
	/**
	 * List of objects which are pending destruction.
	 */
	struct llist_head free_list;
	struct work_struct free_work;

1394
	/** Usable portion of the GTT for GEM */
1395
	dma_addr_t stolen_base; /* limited to low memory (32-bit) */
1396 1397 1398 1399

	/** PPGTT used for aliasing the PPGTT with the GTT */
	struct i915_hw_ppgtt *aliasing_ppgtt;

1400
	struct notifier_block oom_notifier;
1401
	struct notifier_block vmap_notifier;
1402
	struct shrinker shrinker;
1403 1404 1405 1406

	/** LRU list of objects with fence regs on them. */
	struct list_head fence_list;

1407 1408
	u64 unordered_timeline;

1409
	/* the indicator for dispatch video commands on two BSD rings */
1410
	atomic_t bsd_engine_dispatch_index;
1411

1412 1413 1414 1415 1416 1417
	/** Bit 6 swizzling required for X tiling */
	uint32_t bit_6_swizzle_x;
	/** Bit 6 swizzling required for Y tiling */
	uint32_t bit_6_swizzle_y;

	/* accounting, useful for userland debugging */
1418
	spinlock_t object_stat_lock;
1419
	u64 object_memory;
1420 1421 1422
	u32 object_count;
};

1423
struct drm_i915_error_state_buf {
1424
	struct drm_i915_private *i915;
1425 1426 1427 1428 1429 1430 1431 1432
	unsigned bytes;
	unsigned size;
	int err;
	u8 *buf;
	loff_t start;
	loff_t pos;
};

1433 1434 1435
#define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
#define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */

1436 1437 1438
#define I915_ENGINE_DEAD_TIMEOUT  (4 * HZ)  /* Seqno, head and subunits dead */
#define I915_SEQNO_DEAD_TIMEOUT   (12 * HZ) /* Seqno dead with active head */

1439 1440 1441 1442
struct i915_gpu_error {
	/* For hangcheck timer */
#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1443

1444
	struct delayed_work hangcheck_work;
1445 1446 1447 1448

	/* For reset and error_state handling. */
	spinlock_t lock;
	/* Protected by the above dev->gpu_error.lock. */
1449
	struct i915_gpu_state *first_error;
1450 1451 1452

	unsigned long missed_irq_rings;

1453
	/**
M
Mika Kuoppala 已提交
1454
	 * State variable controlling the reset flow and count
1455
	 *
M
Mika Kuoppala 已提交
1456
	 * This is a counter which gets incremented when reset is triggered,
1457
	 *
1458
	 * Before the reset commences, the I915_RESET_BACKOFF bit is set
1459 1460
	 * meaning that any waiters holding onto the struct_mutex should
	 * relinquish the lock immediately in order for the reset to start.
M
Mika Kuoppala 已提交
1461 1462 1463 1464 1465 1466 1467 1468 1469
	 *
	 * If reset is not completed succesfully, the I915_WEDGE bit is
	 * set meaning that hardware is terminally sour and there is no
	 * recovery. All waiters on the reset_queue will be woken when
	 * that happens.
	 *
	 * This counter is used by the wait_seqno code to notice that reset
	 * event happened and it needs to restart the entire ioctl (since most
	 * likely the seqno it waited for won't ever signal anytime soon).
1470 1471 1472 1473
	 *
	 * This is important for lock-free wait paths, where no contended lock
	 * naturally enforces the correct ordering between the bail-out of the
	 * waiter and the gpu reset work code.
1474
	 */
1475
	unsigned long reset_count;
1476

1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500
	/**
	 * flags: Control various stages of the GPU reset
	 *
	 * #I915_RESET_BACKOFF - When we start a reset, we want to stop any
	 * other users acquiring the struct_mutex. To do this we set the
	 * #I915_RESET_BACKOFF bit in the error flags when we detect a reset
	 * and then check for that bit before acquiring the struct_mutex (in
	 * i915_mutex_lock_interruptible()?). I915_RESET_BACKOFF serves a
	 * secondary role in preventing two concurrent global reset attempts.
	 *
	 * #I915_RESET_HANDOFF - To perform the actual GPU reset, we need the
	 * struct_mutex. We try to acquire the struct_mutex in the reset worker,
	 * but it may be held by some long running waiter (that we cannot
	 * interrupt without causing trouble). Once we are ready to do the GPU
	 * reset, we set the I915_RESET_HANDOFF bit and wakeup any waiters. If
	 * they already hold the struct_mutex and want to participate they can
	 * inspect the bit and do the reset directly, otherwise the worker
	 * waits for the struct_mutex.
	 *
	 * #I915_WEDGED - If reset fails and we can no longer use the GPU,
	 * we set the #I915_WEDGED bit. Prior to command submission, e.g.
	 * i915_gem_request_alloc(), this bit is checked and the sequence
	 * aborted (with -EIO reported to userspace) if set.
	 */
1501
	unsigned long flags;
1502 1503
#define I915_RESET_BACKOFF	0
#define I915_RESET_HANDOFF	1
1504
#define I915_WEDGED		(BITS_PER_LONG - 1)
1505

1506 1507 1508 1509 1510 1511
	/**
	 * Waitqueue to signal when a hang is detected. Used to for waiters
	 * to release the struct_mutex for the reset to procede.
	 */
	wait_queue_head_t wait_queue;

1512 1513 1514 1515 1516
	/**
	 * Waitqueue to signal when the reset has completed. Used by clients
	 * that wait for dev_priv->mm.wedged to settle.
	 */
	wait_queue_head_t reset_queue;
1517

1518
	/* For missed irq/seqno simulation. */
1519
	unsigned long test_irq_rings;
1520 1521
};

1522 1523 1524 1525 1526 1527
enum modeset_restore {
	MODESET_ON_LID_OPEN,
	MODESET_DONE,
	MODESET_SUSPENDED,
};

1528 1529 1530 1531 1532
#define DP_AUX_A 0x40
#define DP_AUX_B 0x10
#define DP_AUX_C 0x20
#define DP_AUX_D 0x30

X
Xiong Zhang 已提交
1533 1534 1535 1536
#define DDC_PIN_B  0x05
#define DDC_PIN_C  0x04
#define DDC_PIN_D  0x06

1537
struct ddi_vbt_port_info {
1538 1539 1540 1541 1542 1543
	/*
	 * This is an index in the HDMI/DVI DDI buffer translation table.
	 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
	 * populate this field.
	 */
#define HDMI_LEVEL_SHIFT_UNKNOWN	0xff
1544
	uint8_t hdmi_level_shift;
1545 1546 1547 1548

	uint8_t supports_dvi:1;
	uint8_t supports_hdmi:1;
	uint8_t supports_dp:1;
1549
	uint8_t supports_edp:1;
1550 1551

	uint8_t alternate_aux_channel;
X
Xiong Zhang 已提交
1552
	uint8_t alternate_ddc_pin;
1553 1554 1555

	uint8_t dp_boost_level;
	uint8_t hdmi_boost_level;
1556 1557
};

R
Rodrigo Vivi 已提交
1558 1559 1560 1561 1562
enum psr_lines_to_wait {
	PSR_0_LINES_TO_WAIT = 0,
	PSR_1_LINE_TO_WAIT,
	PSR_4_LINES_TO_WAIT,
	PSR_8_LINES_TO_WAIT
1563 1564
};

1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576
struct intel_vbt_data {
	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */

	/* Feature bits */
	unsigned int int_tv_support:1;
	unsigned int lvds_dither:1;
	unsigned int lvds_vbt:1;
	unsigned int int_crt_support:1;
	unsigned int lvds_use_ssc:1;
	unsigned int display_clock_mode:1;
	unsigned int fdi_rx_polarity_inverted:1;
1577
	unsigned int panel_type:4;
1578 1579 1580
	int lvds_ssc_freq;
	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */

1581 1582
	enum drrs_support_type drrs_type;

1583 1584 1585 1586 1587
	struct {
		int rate;
		int lanes;
		int preemphasis;
		int vswing;
1588
		bool low_vswing;
1589 1590 1591 1592 1593
		bool initialized;
		bool support;
		int bpp;
		struct edp_power_seq pps;
	} edp;
1594

R
Rodrigo Vivi 已提交
1595 1596 1597 1598 1599 1600 1601 1602 1603
	struct {
		bool full_link;
		bool require_aux_wakeup;
		int idle_frames;
		enum psr_lines_to_wait lines_to_wait;
		int tp1_wakeup_time;
		int tp2_tp3_wakeup_time;
	} psr;

1604 1605
	struct {
		u16 pwm_freq_hz;
1606
		bool present;
1607
		bool active_low_pwm;
1608
		u8 min_brightness;	/* min_brightness/255 of max */
1609
		u8 controller;		/* brightness controller number */
1610
		enum intel_backlight_type type;
1611 1612
	} backlight;

1613 1614 1615
	/* MIPI DSI */
	struct {
		u16 panel_id;
1616 1617 1618 1619 1620
		struct mipi_config *config;
		struct mipi_pps_data *pps;
		u8 seq_version;
		u32 size;
		u8 *data;
1621
		const u8 *sequence[MIPI_SEQ_MAX];
1622 1623
	} dsi;

1624 1625 1626
	int crt_ddc_pin;

	int child_dev_num;
1627
	union child_device_config *child_dev;
1628 1629

	struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1630
	struct sdvo_device_mapping sdvo_mappings[2];
1631 1632
};

1633 1634 1635 1636 1637
enum intel_ddb_partitioning {
	INTEL_DDB_PART_1_2,
	INTEL_DDB_PART_5_6, /* IVB+ */
};

1638 1639 1640 1641 1642 1643 1644 1645
struct intel_wm_level {
	bool enable;
	uint32_t pri_val;
	uint32_t spr_val;
	uint32_t cur_val;
	uint32_t fbc_val;
};

1646
struct ilk_wm_values {
1647 1648 1649 1650 1651 1652 1653 1654
	uint32_t wm_pipe[3];
	uint32_t wm_lp[3];
	uint32_t wm_lp_spr[3];
	uint32_t wm_linetime[3];
	bool enable_fbc_wm;
	enum intel_ddb_partitioning partitioning;
};

1655
struct g4x_pipe_wm {
1656
	uint16_t plane[I915_MAX_PLANES];
1657
	uint16_t fbc;
1658
};
1659

1660
struct g4x_sr_wm {
1661
	uint16_t plane;
1662
	uint16_t cursor;
1663
	uint16_t fbc;
1664 1665 1666 1667
};

struct vlv_wm_ddl_values {
	uint8_t plane[I915_MAX_PLANES];
1668
};
1669

1670
struct vlv_wm_values {
1671 1672
	struct g4x_pipe_wm pipe[3];
	struct g4x_sr_wm sr;
1673
	struct vlv_wm_ddl_values ddl[3];
1674 1675
	uint8_t level;
	bool cxsr;
1676 1677
};

1678 1679 1680 1681 1682 1683 1684 1685 1686
struct g4x_wm_values {
	struct g4x_pipe_wm pipe[2];
	struct g4x_sr_wm sr;
	struct g4x_sr_wm hpll;
	bool cxsr;
	bool hpll_en;
	bool fbc_en;
};

1687
struct skl_ddb_entry {
1688
	uint16_t start, end;	/* in number of blocks, 'end' is exclusive */
1689 1690 1691 1692
};

static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
{
1693
	return entry->end - entry->start;
1694 1695
}

1696 1697 1698 1699 1700 1701 1702 1703 1704
static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
				       const struct skl_ddb_entry *e2)
{
	if (e1->start == e2->start && e1->end == e2->end)
		return true;

	return false;
}

1705
struct skl_ddb_allocation {
1706
	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1707
	struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1708 1709
};

1710
struct skl_wm_values {
1711
	unsigned dirty_pipes;
1712
	struct skl_ddb_allocation ddb;
1713 1714 1715
};

struct skl_wm_level {
L
Lyude 已提交
1716 1717 1718
	bool plane_en;
	uint16_t plane_res_b;
	uint8_t plane_res_l;
1719 1720
};

1721
/*
1722 1723 1724 1725
 * This struct helps tracking the state needed for runtime PM, which puts the
 * device in PCI D3 state. Notice that when this happens, nothing on the
 * graphics device works, even register access, so we don't get interrupts nor
 * anything else.
1726
 *
1727 1728 1729
 * Every piece of our code that needs to actually touch the hardware needs to
 * either call intel_runtime_pm_get or call intel_display_power_get with the
 * appropriate power domain.
1730
 *
1731 1732
 * Our driver uses the autosuspend delay feature, which means we'll only really
 * suspend if we stay with zero refcount for a certain amount of time. The
1733
 * default value is currently very conservative (see intel_runtime_pm_enable), but
1734
 * it can be changed with the standard runtime PM files from sysfs.
1735 1736 1737 1738 1739
 *
 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
 * goes back to false exactly before we reenable the IRQs. We use this variable
 * to check if someone is trying to enable/disable IRQs while they're supposed
 * to be disabled. This shouldn't happen and we'll print some error messages in
1740
 * case it happens.
1741
 *
1742
 * For more, read the Documentation/power/runtime_pm.txt.
1743
 */
1744
struct i915_runtime_pm {
1745
	atomic_t wakeref_count;
1746
	bool suspended;
1747
	bool irqs_enabled;
1748 1749
};

1750 1751 1752 1753 1754
enum intel_pipe_crc_source {
	INTEL_PIPE_CRC_SOURCE_NONE,
	INTEL_PIPE_CRC_SOURCE_PLANE1,
	INTEL_PIPE_CRC_SOURCE_PLANE2,
	INTEL_PIPE_CRC_SOURCE_PF,
1755
	INTEL_PIPE_CRC_SOURCE_PIPE,
D
Daniel Vetter 已提交
1756 1757 1758 1759 1760
	/* TV/DP on pre-gen5/vlv can't use the pipe source. */
	INTEL_PIPE_CRC_SOURCE_TV,
	INTEL_PIPE_CRC_SOURCE_DP_B,
	INTEL_PIPE_CRC_SOURCE_DP_C,
	INTEL_PIPE_CRC_SOURCE_DP_D,
1761
	INTEL_PIPE_CRC_SOURCE_AUTO,
1762 1763 1764
	INTEL_PIPE_CRC_SOURCE_MAX,
};

1765
struct intel_pipe_crc_entry {
1766
	uint32_t frame;
1767 1768 1769
	uint32_t crc[5];
};

1770
#define INTEL_PIPE_CRC_ENTRIES_NR	128
1771
struct intel_pipe_crc {
1772 1773
	spinlock_t lock;
	bool opened;		/* exclusive access to the result file */
1774
	struct intel_pipe_crc_entry *entries;
1775
	enum intel_pipe_crc_source source;
1776
	int head, tail;
1777
	wait_queue_head_t wq;
T
Tomeu Vizoso 已提交
1778
	int skipped;
1779 1780
};

1781
struct i915_frontbuffer_tracking {
1782
	spinlock_t lock;
1783 1784 1785 1786 1787 1788 1789 1790 1791

	/*
	 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
	 * scheduled flips.
	 */
	unsigned busy_bits;
	unsigned flip_bits;
};

1792
struct i915_wa_reg {
1793
	i915_reg_t addr;
1794 1795 1796 1797 1798
	u32 value;
	/* bitmask representing WA bits */
	u32 mask;
};

1799 1800 1801 1802 1803 1804 1805
/*
 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
 * allowing it for RCS as we don't foresee any requirement of having
 * a whitelist for other engines. When it is really required for
 * other engines then the limit need to be increased.
 */
#define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1806 1807 1808 1809

struct i915_workarounds {
	struct i915_wa_reg reg[I915_MAX_WA_REGS];
	u32 count;
1810
	u32 hw_whitelist_count[I915_NUM_ENGINES];
1811 1812
};

1813 1814 1815 1816
struct i915_virtual_gpu {
	bool active;
};

1817 1818 1819 1820 1821 1822 1823
/* used in computing the new watermarks state */
struct intel_wm_config {
	unsigned int num_pipes_active;
	bool sprites_enabled;
	bool sprites_scaled;
};

1824 1825 1826 1827 1828
struct i915_oa_format {
	u32 format;
	int size;
};

1829 1830 1831 1832 1833
struct i915_oa_reg {
	i915_reg_t addr;
	u32 value;
};

1834 1835
struct i915_perf_stream;

1836 1837 1838
/**
 * struct i915_perf_stream_ops - the OPs to support a specific stream type
 */
1839
struct i915_perf_stream_ops {
1840 1841 1842 1843
	/**
	 * @enable: Enables the collection of HW samples, either in response to
	 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
	 * without `I915_PERF_FLAG_DISABLED`.
1844 1845 1846
	 */
	void (*enable)(struct i915_perf_stream *stream);

1847 1848 1849 1850
	/**
	 * @disable: Disables the collection of HW samples, either in response
	 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
	 * the stream.
1851 1852 1853
	 */
	void (*disable)(struct i915_perf_stream *stream);

1854 1855
	/**
	 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1856 1857 1858 1859 1860 1861
	 * once there is something ready to read() for the stream
	 */
	void (*poll_wait)(struct i915_perf_stream *stream,
			  struct file *file,
			  poll_table *wait);

1862 1863 1864
	/**
	 * @wait_unlocked: For handling a blocking read, wait until there is
	 * something to ready to read() for the stream. E.g. wait on the same
1865
	 * wait queue that would be passed to poll_wait().
1866 1867 1868
	 */
	int (*wait_unlocked)(struct i915_perf_stream *stream);

1869 1870 1871 1872 1873 1874 1875
	/**
	 * @read: Copy buffered metrics as records to userspace
	 * **buf**: the userspace, destination buffer
	 * **count**: the number of bytes to copy, requested by userspace
	 * **offset**: zero at the start of the read, updated as the read
	 * proceeds, it represents how many bytes have been copied so far and
	 * the buffer offset for copying the next record.
1876
	 *
1877 1878
	 * Copy as many buffered i915 perf samples and records for this stream
	 * to userspace as will fit in the given buffer.
1879
	 *
1880 1881
	 * Only write complete records; returning -%ENOSPC if there isn't room
	 * for a complete record.
1882
	 *
1883 1884 1885
	 * Return any error condition that results in a short read such as
	 * -%ENOSPC or -%EFAULT, even though these may be squashed before
	 * returning to userspace.
1886 1887 1888 1889 1890 1891
	 */
	int (*read)(struct i915_perf_stream *stream,
		    char __user *buf,
		    size_t count,
		    size_t *offset);

1892 1893
	/**
	 * @destroy: Cleanup any stream specific resources.
1894 1895 1896 1897 1898 1899
	 *
	 * The stream will always be disabled before this is called.
	 */
	void (*destroy)(struct i915_perf_stream *stream);
};

1900 1901 1902
/**
 * struct i915_perf_stream - state for a single open stream FD
 */
1903
struct i915_perf_stream {
1904 1905 1906
	/**
	 * @dev_priv: i915 drm device
	 */
1907 1908
	struct drm_i915_private *dev_priv;

1909 1910 1911
	/**
	 * @link: Links the stream into ``&drm_i915_private->streams``
	 */
1912 1913
	struct list_head link;

1914 1915 1916 1917 1918
	/**
	 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
	 * properties given when opening a stream, representing the contents
	 * of a single sample as read() by userspace.
	 */
1919
	u32 sample_flags;
1920 1921 1922 1923 1924 1925

	/**
	 * @sample_size: Considering the configured contents of a sample
	 * combined with the required header size, this is the total size
	 * of a single sample record.
	 */
1926
	int sample_size;
1927

1928 1929 1930 1931
	/**
	 * @ctx: %NULL if measuring system-wide across all contexts or a
	 * specific context that is being monitored.
	 */
1932
	struct i915_gem_context *ctx;
1933 1934 1935 1936 1937 1938

	/**
	 * @enabled: Whether the stream is currently enabled, considering
	 * whether the stream was opened in a disabled state and based
	 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
	 */
1939 1940
	bool enabled;

1941 1942 1943 1944
	/**
	 * @ops: The callbacks providing the implementation of this specific
	 * type of configured stream.
	 */
1945 1946 1947
	const struct i915_perf_stream_ops *ops;
};

1948 1949 1950
/**
 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
 */
1951
struct i915_oa_ops {
1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966
	/**
	 * @init_oa_buffer: Resets the head and tail pointers of the
	 * circular buffer for periodic OA reports.
	 *
	 * Called when first opening a stream for OA metrics, but also may be
	 * called in response to an OA buffer overflow or other error
	 * condition.
	 *
	 * Note it may be necessary to clear the full OA buffer here as part of
	 * maintaining the invariable that new reports must be written to
	 * zeroed memory for us to be able to reliable detect if an expected
	 * report has not yet landed in memory.  (At least on Haswell the OA
	 * buffer tail pointer is not synchronized with reports being visible
	 * to the CPU)
	 */
1967
	void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
1968 1969 1970 1971 1972 1973 1974

	/**
	 * @enable_metric_set: Applies any MUX configuration to set up the
	 * Boolean and Custom (B/C) counters that are part of the counter
	 * reports being sampled. May apply system constraints such as
	 * disabling EU clock gating as required.
	 */
1975
	int (*enable_metric_set)(struct drm_i915_private *dev_priv);
1976 1977 1978 1979 1980

	/**
	 * @disable_metric_set: Remove system constraints associated with using
	 * the OA unit.
	 */
1981
	void (*disable_metric_set)(struct drm_i915_private *dev_priv);
1982 1983 1984 1985

	/**
	 * @oa_enable: Enable periodic sampling
	 */
1986
	void (*oa_enable)(struct drm_i915_private *dev_priv);
1987 1988 1989 1990

	/**
	 * @oa_disable: Disable periodic sampling
	 */
1991
	void (*oa_disable)(struct drm_i915_private *dev_priv);
1992 1993 1994 1995 1996

	/**
	 * @read: Copy data from the circular OA buffer into a given userspace
	 * buffer.
	 */
1997 1998 1999 2000
	int (*read)(struct i915_perf_stream *stream,
		    char __user *buf,
		    size_t count,
		    size_t *offset);
2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015

	/**
	 * @oa_buffer_is_empty: Check if OA buffer empty (false positives OK)
	 *
	 * This is either called via fops or the poll check hrtimer (atomic
	 * ctx) without any locks taken.
	 *
	 * It's safe to read OA config state here unlocked, assuming that this
	 * is only called while the stream is enabled, while the global OA
	 * configuration can't be modified.
	 *
	 * Efficiency is more important than avoiding some false positives
	 * here, which will be handled gracefully - likely resulting in an
	 * %EAGAIN error for userspace.
	 */
2016
	bool (*oa_buffer_is_empty)(struct drm_i915_private *dev_priv);
2017 2018
};

2019 2020 2021 2022
struct intel_cdclk_state {
	unsigned int cdclk, vco, ref;
};

2023
struct drm_i915_private {
2024 2025
	struct drm_device drm;

2026
	struct kmem_cache *objects;
2027
	struct kmem_cache *vmas;
2028
	struct kmem_cache *requests;
2029
	struct kmem_cache *dependencies;
2030

2031
	const struct intel_device_info info;
2032 2033 2034

	void __iomem *regs;

2035
	struct intel_uncore uncore;
2036

2037 2038
	struct i915_virtual_gpu vgpu;

2039
	struct intel_gvt *gvt;
2040

2041
	struct intel_huc huc;
2042 2043
	struct intel_guc guc;

2044 2045
	struct intel_csr csr;

2046
	struct intel_gmbus gmbus[GMBUS_NUM_PINS];
2047

2048 2049 2050 2051 2052 2053 2054 2055 2056
	/** gmbus_mutex protects against concurrent usage of the single hw gmbus
	 * controller on different i2c buses. */
	struct mutex gmbus_mutex;

	/**
	 * Base address of the gmbus and gpio block.
	 */
	uint32_t gpio_mmio_base;

2057 2058 2059
	/* MMIO base address for MIPI regs */
	uint32_t mipi_mmio_base;

2060 2061
	uint32_t psr_mmio_base;

2062 2063
	uint32_t pps_mmio_base;

2064 2065
	wait_queue_head_t gmbus_wait_queue;

2066
	struct pci_dev *bridge_dev;
2067
	struct i915_gem_context *kernel_context;
2068
	struct intel_engine_cs *engine[I915_NUM_ENGINES];
2069
	struct i915_vma *semaphore;
2070

2071
	struct drm_dma_handle *status_page_dmah;
2072 2073 2074 2075 2076
	struct resource mch_res;

	/* protects the irq masks */
	spinlock_t irq_lock;

2077 2078 2079
	/* protects the mmio flip data */
	spinlock_t mmio_flip_lock;

2080 2081
	bool display_irqs_enabled;

2082 2083 2084
	/* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
	struct pm_qos_request pm_qos;

V
Ville Syrjälä 已提交
2085 2086
	/* Sideband mailbox protection */
	struct mutex sb_lock;
2087 2088

	/** Cached value of IMR to avoid reads in updating the bitfield */
2089 2090 2091 2092
	union {
		u32 irq_mask;
		u32 de_irq_mask[I915_MAX_PIPES];
	};
2093
	u32 gt_irq_mask;
2094 2095
	u32 pm_imr;
	u32 pm_ier;
2096
	u32 pm_rps_events;
2097
	u32 pm_guc_events;
2098
	u32 pipestat_irq_mask[I915_MAX_PIPES];
2099

2100
	struct i915_hotplug hotplug;
2101
	struct intel_fbc fbc;
2102
	struct i915_drrs drrs;
2103
	struct intel_opregion opregion;
2104
	struct intel_vbt_data vbt;
2105

2106 2107
	bool preserve_bios_swizzle;

2108 2109 2110
	/* overlay */
	struct intel_overlay *overlay;

2111
	/* backlight registers and fields in struct intel_panel */
2112
	struct mutex backlight_lock;
2113

2114 2115 2116
	/* LVDS info */
	bool no_aux_handshake;

V
Ville Syrjälä 已提交
2117 2118 2119
	/* protects panel power sequencer state */
	struct mutex pps_mutex;

2120 2121 2122 2123
	struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
	int num_fence_regs; /* 8 on pre-965, 16 otherwise */

	unsigned int fsb_freq, mem_freq, is_ddr3;
2124
	unsigned int skl_preferred_vco_freq;
2125
	unsigned int max_cdclk_freq;
2126

M
Mika Kahola 已提交
2127
	unsigned int max_dotclk_freq;
2128
	unsigned int rawclk_freq;
2129
	unsigned int hpll_freq;
2130
	unsigned int czclk_freq;
2131

2132
	struct {
2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146
		/*
		 * The current logical cdclk state.
		 * See intel_atomic_state.cdclk.logical
		 *
		 * For reading holding any crtc lock is sufficient,
		 * for writing must hold all of them.
		 */
		struct intel_cdclk_state logical;
		/*
		 * The current actual cdclk state.
		 * See intel_atomic_state.cdclk.actual
		 */
		struct intel_cdclk_state actual;
		/* The current hardware cdclk state */
2147 2148
		struct intel_cdclk_state hw;
	} cdclk;
2149

2150 2151 2152 2153 2154 2155 2156
	/**
	 * wq - Driver workqueue for GEM.
	 *
	 * NOTE: Work items scheduled here are not allowed to grab any modeset
	 * locks, for otherwise the flushing done in the pageflip code will
	 * result in deadlocks.
	 */
2157 2158 2159 2160 2161 2162 2163
	struct workqueue_struct *wq;

	/* Display functions */
	struct drm_i915_display_funcs display;

	/* PCH chipset type */
	enum intel_pch pch_type;
2164
	unsigned short pch_id;
2165 2166 2167

	unsigned long quirks;

2168 2169
	enum modeset_restore modeset_restore;
	struct mutex modeset_restore_lock;
2170
	struct drm_atomic_state *modeset_restore_state;
2171
	struct drm_modeset_acquire_ctx reset_ctx;
2172

2173
	struct list_head vm_list; /* Global list of all address spaces */
2174
	struct i915_ggtt ggtt; /* VM representing the global address space */
B
Ben Widawsky 已提交
2175

2176
	struct i915_gem_mm mm;
2177 2178
	DECLARE_HASHTABLE(mm_structs, 7);
	struct mutex mm_lock;
2179

2180 2181 2182 2183 2184 2185 2186
	/* The hw wants to have a stable context identifier for the lifetime
	 * of the context (for OA, PASID, faults, etc). This is limited
	 * in execlists to 21 bits.
	 */
	struct ida context_hw_ida;
#define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */

2187 2188
	/* Kernel Modesetting */

2189 2190
	struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
	struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
2191 2192
	wait_queue_head_t pending_flip_queue;

2193 2194 2195 2196
#ifdef CONFIG_DEBUG_FS
	struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
#endif

2197
	/* dpll and cdclk state is protected by connection_mutex */
D
Daniel Vetter 已提交
2198 2199
	int num_shared_dpll;
	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
2200
	const struct intel_dpll_mgr *dpll_mgr;
2201

2202 2203 2204 2205 2206 2207 2208
	/*
	 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
	 * Must be global rather than per dpll, because on some platforms
	 * plls share registers.
	 */
	struct mutex dpll_lock;

2209 2210 2211
	unsigned int active_crtcs;
	unsigned int min_pixclk[I915_MAX_PIPES];

2212
	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
2213

2214
	struct i915_workarounds workarounds;
2215

2216 2217
	struct i915_frontbuffer_tracking fb_tracking;

2218 2219 2220 2221 2222
	struct intel_atomic_helper {
		struct llist_head free_list;
		struct work_struct free_work;
	} atomic_helper;

2223
	u16 orig_clock;
2224

2225
	bool mchbar_need_disable;
2226

2227 2228
	struct intel_l3_parity l3_parity;

B
Ben Widawsky 已提交
2229
	/* Cannot be determined by PCIID. You must always read a register. */
2230
	u32 edram_cap;
B
Ben Widawsky 已提交
2231

2232
	/* gen6+ rps state */
2233
	struct intel_gen6_power_mgmt rps;
2234

2235 2236
	/* ilk-only ips/rps state. Everything in here is protected by the global
	 * mchdev_lock in intel_pm.c */
2237
	struct intel_ilk_power_mgmt ips;
2238

2239
	struct i915_power_domains power_domains;
2240

R
Rodrigo Vivi 已提交
2241
	struct i915_psr psr;
2242

2243
	struct i915_gpu_error gpu_error;
2244

2245 2246
	struct drm_i915_gem_object *vlv_pctx;

2247
#ifdef CONFIG_DRM_FBDEV_EMULATION
2248 2249
	/* list of fbdev register on this device */
	struct intel_fbdev *fbdev;
2250
	struct work_struct fbdev_suspend_work;
2251
#endif
2252 2253

	struct drm_property *broadcast_rgb_property;
2254
	struct drm_property *force_audio_property;
2255

I
Imre Deak 已提交
2256
	/* hda/i915 audio component */
2257
	struct i915_audio_component *audio_component;
I
Imre Deak 已提交
2258
	bool audio_component_registered;
2259 2260 2261 2262 2263
	/**
	 * av_mutex - mutex for audio/video sync
	 *
	 */
	struct mutex av_mutex;
I
Imre Deak 已提交
2264

2265
	struct list_head context_list;
2266

2267
	u32 fdi_rx_config;
2268

2269
	/* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2270
	u32 chv_phy_control;
2271 2272 2273 2274 2275 2276
	/*
	 * Shadows for CHV DPLL_MD regs to keep the state
	 * checker somewhat working in the presence hardware
	 * crappiness (can't read out DPLL_MD for pipes B & C).
	 */
	u32 chv_dpll_md[I915_MAX_PIPES];
2277
	u32 bxt_phy_grc;
2278

2279
	u32 suspend_count;
2280
	bool suspended_to_idle;
2281
	struct i915_suspend_saved_registers regfile;
2282
	struct vlv_s0ix_state vlv_s0ix_state;
2283

2284
	enum {
2285 2286 2287 2288 2289
		I915_SAGV_UNKNOWN = 0,
		I915_SAGV_DISABLED,
		I915_SAGV_ENABLED,
		I915_SAGV_NOT_CONTROLLED
	} sagv_status;
2290

2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302
	struct {
		/*
		 * Raw watermark latency values:
		 * in 0.1us units for WM0,
		 * in 0.5us units for WM1+.
		 */
		/* primary */
		uint16_t pri_latency[5];
		/* sprite */
		uint16_t spr_latency[5];
		/* cursor */
		uint16_t cur_latency[5];
2303 2304 2305 2306 2307 2308
		/*
		 * Raw watermark memory latency values
		 * for SKL for all 8 levels
		 * in 1us units.
		 */
		uint16_t skl_latency[8];
2309 2310

		/* current hardware state */
2311 2312 2313
		union {
			struct ilk_wm_values hw;
			struct skl_wm_values skl_hw;
2314
			struct vlv_wm_values vlv;
2315
			struct g4x_wm_values g4x;
2316
		};
2317 2318

		uint8_t max_level;
2319 2320 2321 2322 2323 2324 2325

		/*
		 * Should be held around atomic WM register writing; also
		 * protects * intel_crtc->wm.active and
		 * cstate->wm.need_postvbl_update.
		 */
		struct mutex wm_mutex;
2326 2327 2328 2329 2330 2331 2332

		/*
		 * Set during HW readout of watermarks/DDB.  Some platforms
		 * need to know when we're still using BIOS-provided values
		 * (which we don't fully trust).
		 */
		bool distrust_bios_wm;
2333 2334
	} wm;

2335 2336
	struct i915_runtime_pm pm;

2337 2338
	struct {
		bool initialized;
2339

2340
		struct kobject *metrics_kobj;
2341
		struct ctl_table_header *sysctl_header;
2342

2343 2344
		struct mutex lock;
		struct list_head streams;
2345

2346 2347
		spinlock_t hook_lock;

2348
		struct {
2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363
			struct i915_perf_stream *exclusive_stream;

			u32 specific_ctx_id;

			struct hrtimer poll_check_timer;
			wait_queue_head_t poll_wq;
			bool pollin;

			bool periodic;
			int period_exponent;
			int timestamp_frequency;

			int tail_margin;

			int metrics_set;
2364 2365 2366 2367 2368

			const struct i915_oa_reg *mux_regs;
			int mux_regs_len;
			const struct i915_oa_reg *b_counter_regs;
			int b_counter_regs_len;
2369 2370 2371 2372 2373 2374

			struct {
				struct i915_vma *vma;
				u8 *vaddr;
				int format;
				int format_size;
2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385

				/**
				 * Although we can always read back the head
				 * pointer register, we prefer to avoid
				 * trusting the HW state, just to avoid any
				 * risk that some hardware condition could
				 * somehow bump the head pointer unpredictably
				 * and cause us to forward the wrong OA buffer
				 * data to userspace.
				 */
				u32 head;
2386 2387 2388 2389 2390 2391 2392
			} oa_buffer;

			u32 gen7_latched_oastatus1;

			struct i915_oa_ops ops;
			const struct i915_oa_format *oa_formats;
			int n_builtin_sets;
2393
		} oa;
2394 2395
	} perf;

2396 2397
	/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
	struct {
2398
		void (*resume)(struct drm_i915_private *);
2399
		void (*cleanup_engine)(struct intel_engine_cs *engine);
2400

2401 2402
		struct list_head timelines;
		struct i915_gem_timeline global_timeline;
2403
		u32 active_requests;
2404

2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430
		/**
		 * Is the GPU currently considered idle, or busy executing
		 * userspace requests? Whilst idle, we allow runtime power
		 * management to power down the hardware and display clocks.
		 * In order to reduce the effect on performance, there
		 * is a slight delay before we do so.
		 */
		bool awake;

		/**
		 * We leave the user IRQ off as much as possible,
		 * but this means that requests will finish and never
		 * be retired once the system goes idle. Set a timer to
		 * fire periodically while the ring is running. When it
		 * fires, go retire requests.
		 */
		struct delayed_work retire_work;

		/**
		 * When we detect an idle GPU, we want to turn on
		 * powersaving features. So once we see that there
		 * are no more requests outstanding and no more
		 * arrive within a small period of time, we fire
		 * off the idle_work.
		 */
		struct delayed_work idle_work;
2431 2432

		ktime_t last_init_time;
2433 2434
	} gt;

2435 2436 2437
	/* perform PHY state sanity checks? */
	bool chv_phy_assert[2];

M
Mahesh Kumar 已提交
2438 2439
	bool ipc_enabled;

2440 2441
	/* Used to save the pipe-to-encoder mapping for audio */
	struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2442

2443 2444 2445 2446 2447 2448
	/* necessary resource sharing with HDMI LPE audio driver. */
	struct {
		struct platform_device *platdev;
		int	irq;
	} lpe_audio;

2449 2450 2451 2452
	/*
	 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
	 * will be rejected. Instead look for a better place.
	 */
2453
};
L
Linus Torvalds 已提交
2454

2455 2456
static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
{
2457
	return container_of(dev, struct drm_i915_private, drm);
2458 2459
}

2460
static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
I
Imre Deak 已提交
2461
{
2462
	return to_i915(dev_get_drvdata(kdev));
I
Imre Deak 已提交
2463 2464
}

2465 2466 2467 2468 2469
static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
{
	return container_of(guc, struct drm_i915_private, guc);
}

A
Arkadiusz Hiler 已提交
2470 2471 2472 2473 2474
static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
{
	return container_of(huc, struct drm_i915_private, huc);
}

2475
/* Simple iterator over all initialised engines */
2476 2477 2478 2479 2480
#define for_each_engine(engine__, dev_priv__, id__) \
	for ((id__) = 0; \
	     (id__) < I915_NUM_ENGINES; \
	     (id__)++) \
		for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2481 2482

/* Iterator over subset of engines selected by mask */
2483 2484
#define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
	for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask;	\
2485
	     tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2486

2487 2488 2489 2490 2491 2492 2493
enum hdmi_force_audio {
	HDMI_AUDIO_OFF_DVI = -2,	/* no aux data for HDMI-DVI converter */
	HDMI_AUDIO_OFF,			/* force turn off HDMI audio */
	HDMI_AUDIO_AUTO,		/* trust EDID */
	HDMI_AUDIO_ON,			/* force turn on HDMI audio */
};

2494
#define I915_GTT_OFFSET_NONE ((u32)-1)
2495

2496 2497
/*
 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2498
 * considered to be the frontbuffer for the given plane interface-wise. This
2499 2500 2501 2502 2503
 * doesn't mean that the hw necessarily already scans it out, but that any
 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
 *
 * We have one bit per pipe and per scanout plane type.
 */
2504 2505
#define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2506 2507 2508
#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
	(1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
#define INTEL_FRONTBUFFER_CURSOR(pipe) \
2509 2510 2511
	(1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
#define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
	(1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2512
#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2513
	(1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2514
#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2515
	(0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2516

2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542
/*
 * Optimised SGL iterator for GEM objects
 */
static __always_inline struct sgt_iter {
	struct scatterlist *sgp;
	union {
		unsigned long pfn;
		dma_addr_t dma;
	};
	unsigned int curr;
	unsigned int max;
} __sgt_iter(struct scatterlist *sgl, bool dma) {
	struct sgt_iter s = { .sgp = sgl };

	if (s.sgp) {
		s.max = s.curr = s.sgp->offset;
		s.max += s.sgp->length;
		if (dma)
			s.dma = sg_dma_address(s.sgp);
		else
			s.pfn = page_to_pfn(sg_page(s.sgp));
	}

	return s;
}

2543 2544 2545 2546 2547 2548 2549 2550
static inline struct scatterlist *____sg_next(struct scatterlist *sg)
{
	++sg;
	if (unlikely(sg_is_chain(sg)))
		sg = sg_chain_ptr(sg);
	return sg;
}

2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564
/**
 * __sg_next - return the next scatterlist entry in a list
 * @sg:		The current sg entry
 *
 * Description:
 *   If the entry is the last, return NULL; otherwise, step to the next
 *   element in the array (@sg@+1). If that's a chain pointer, follow it;
 *   otherwise just return the pointer to the current element.
 **/
static inline struct scatterlist *__sg_next(struct scatterlist *sg)
{
#ifdef CONFIG_DEBUG_SG
	BUG_ON(sg->sg_magic != SG_MAGIC);
#endif
2565
	return sg_is_last(sg) ? NULL : ____sg_next(sg);
2566 2567
}

2568 2569 2570 2571 2572 2573 2574 2575 2576 2577
/**
 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
 * @__dmap:	DMA address (output)
 * @__iter:	'struct sgt_iter' (iterator state, internal)
 * @__sgt:	sg_table to iterate over (input)
 */
#define for_each_sgt_dma(__dmap, __iter, __sgt)				\
	for ((__iter) = __sgt_iter((__sgt)->sgl, true);			\
	     ((__dmap) = (__iter).dma + (__iter).curr);			\
	     (((__iter).curr += PAGE_SIZE) < (__iter).max) ||		\
2578
	     ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590

/**
 * for_each_sgt_page - iterate over the pages of the given sg_table
 * @__pp:	page pointer (output)
 * @__iter:	'struct sgt_iter' (iterator state, internal)
 * @__sgt:	sg_table to iterate over (input)
 */
#define for_each_sgt_page(__pp, __iter, __sgt)				\
	for ((__iter) = __sgt_iter((__sgt)->sgl, false);		\
	     ((__pp) = (__iter).pfn == 0 ? NULL :			\
	      pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
	     (((__iter).curr += PAGE_SIZE) < (__iter).max) ||		\
2591
	     ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2592

2593 2594 2595 2596 2597 2598 2599
static inline const struct intel_device_info *
intel_info(const struct drm_i915_private *dev_priv)
{
	return &dev_priv->info;
}

#define INTEL_INFO(dev_priv)	intel_info((dev_priv))
2600

2601
#define INTEL_GEN(dev_priv)	((dev_priv)->info.gen)
2602
#define INTEL_DEVID(dev_priv)	((dev_priv)->info.device_id)
2603

2604
#define REVID_FOREVER		0xff
2605
#define INTEL_REVID(dev_priv)	((dev_priv)->drm.pdev->revision)
2606 2607 2608 2609 2610 2611 2612

#define GEN_FOREVER (0)
/*
 * Returns true if Gen is in inclusive range [Start, End].
 *
 * Use GEN_FOREVER for unbound start and or end.
 */
2613
#define IS_GEN(dev_priv, s, e) ({ \
2614 2615 2616 2617 2618 2619 2620 2621 2622
	unsigned int __s = (s), __e = (e); \
	BUILD_BUG_ON(!__builtin_constant_p(s)); \
	BUILD_BUG_ON(!__builtin_constant_p(e)); \
	if ((__s) != GEN_FOREVER) \
		__s = (s) - 1; \
	if ((__e) == GEN_FOREVER) \
		__e = BITS_PER_LONG - 1; \
	else \
		__e = (e) - 1; \
2623
	!!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
2624 2625
})

2626 2627 2628 2629 2630 2631 2632 2633
/*
 * Return true if revision is in range [since,until] inclusive.
 *
 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
 */
#define IS_REVID(p, since, until) \
	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))

2634 2635
#define IS_I830(dev_priv)	((dev_priv)->info.platform == INTEL_I830)
#define IS_I845G(dev_priv)	((dev_priv)->info.platform == INTEL_I845G)
2636
#define IS_I85X(dev_priv)	((dev_priv)->info.platform == INTEL_I85X)
2637
#define IS_I865G(dev_priv)	((dev_priv)->info.platform == INTEL_I865G)
2638
#define IS_I915G(dev_priv)	((dev_priv)->info.platform == INTEL_I915G)
2639 2640
#define IS_I915GM(dev_priv)	((dev_priv)->info.platform == INTEL_I915GM)
#define IS_I945G(dev_priv)	((dev_priv)->info.platform == INTEL_I945G)
2641
#define IS_I945GM(dev_priv)	((dev_priv)->info.platform == INTEL_I945GM)
2642 2643
#define IS_I965G(dev_priv)	((dev_priv)->info.platform == INTEL_I965G)
#define IS_I965GM(dev_priv)	((dev_priv)->info.platform == INTEL_I965GM)
2644 2645 2646
#define IS_G45(dev_priv)	((dev_priv)->info.platform == INTEL_G45)
#define IS_GM45(dev_priv)	((dev_priv)->info.platform == INTEL_GM45)
#define IS_G4X(dev_priv)	(IS_G45(dev_priv) || IS_GM45(dev_priv))
2647 2648
#define IS_PINEVIEW_G(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa001)
#define IS_PINEVIEW_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa011)
2649
#define IS_PINEVIEW(dev_priv)	((dev_priv)->info.platform == INTEL_PINEVIEW)
2650
#define IS_G33(dev_priv)	((dev_priv)->info.platform == INTEL_G33)
2651
#define IS_IRONLAKE_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0046)
2652
#define IS_IVYBRIDGE(dev_priv)	((dev_priv)->info.platform == INTEL_IVYBRIDGE)
2653 2654 2655
#define IS_IVB_GT1(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0156 || \
				 INTEL_DEVID(dev_priv) == 0x0152 || \
				 INTEL_DEVID(dev_priv) == 0x015a)
2656 2657 2658 2659 2660 2661 2662 2663
#define IS_VALLEYVIEW(dev_priv)	((dev_priv)->info.platform == INTEL_VALLEYVIEW)
#define IS_CHERRYVIEW(dev_priv)	((dev_priv)->info.platform == INTEL_CHERRYVIEW)
#define IS_HASWELL(dev_priv)	((dev_priv)->info.platform == INTEL_HASWELL)
#define IS_BROADWELL(dev_priv)	((dev_priv)->info.platform == INTEL_BROADWELL)
#define IS_SKYLAKE(dev_priv)	((dev_priv)->info.platform == INTEL_SKYLAKE)
#define IS_BROXTON(dev_priv)	((dev_priv)->info.platform == INTEL_BROXTON)
#define IS_KABYLAKE(dev_priv)	((dev_priv)->info.platform == INTEL_KABYLAKE)
#define IS_GEMINILAKE(dev_priv)	((dev_priv)->info.platform == INTEL_GEMINILAKE)
2664
#define IS_MOBILE(dev_priv)	((dev_priv)->info.is_mobile)
2665 2666 2667 2668 2669 2670
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv)	(IS_BROADWELL(dev_priv) && \
				 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 ||	\
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xb ||	\
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
V
Ville Syrjälä 已提交
2671
/* ULX machines are also considered ULT. */
2672 2673 2674 2675 2676 2677 2678 2679
#define IS_BDW_ULX(dev_priv)	(IS_BROADWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
#define IS_BDW_GT3(dev_priv)	(IS_BROADWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
#define IS_HSW_ULT(dev_priv)	(IS_HASWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
#define IS_HSW_GT3(dev_priv)	(IS_HASWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2680
/* ULX machines are also considered ULT. */
2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702
#define IS_HSW_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0A0E || \
				 INTEL_DEVID(dev_priv) == 0x0A1E)
#define IS_SKL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x1906 || \
				 INTEL_DEVID(dev_priv) == 0x1913 || \
				 INTEL_DEVID(dev_priv) == 0x1916 || \
				 INTEL_DEVID(dev_priv) == 0x1921 || \
				 INTEL_DEVID(dev_priv) == 0x1926)
#define IS_SKL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x190E || \
				 INTEL_DEVID(dev_priv) == 0x1915 || \
				 INTEL_DEVID(dev_priv) == 0x191E)
#define IS_KBL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x5906 || \
				 INTEL_DEVID(dev_priv) == 0x5913 || \
				 INTEL_DEVID(dev_priv) == 0x5916 || \
				 INTEL_DEVID(dev_priv) == 0x5921 || \
				 INTEL_DEVID(dev_priv) == 0x5926)
#define IS_KBL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x590E || \
				 INTEL_DEVID(dev_priv) == 0x5915 || \
				 INTEL_DEVID(dev_priv) == 0x591E)
#define IS_SKL_GT3(dev_priv)	(IS_SKYLAKE(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
#define IS_SKL_GT4(dev_priv)	(IS_SKYLAKE(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
2703

2704
#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2705

2706 2707 2708 2709 2710 2711
#define SKL_REVID_A0		0x0
#define SKL_REVID_B0		0x1
#define SKL_REVID_C0		0x2
#define SKL_REVID_D0		0x3
#define SKL_REVID_E0		0x4
#define SKL_REVID_F0		0x5
2712 2713
#define SKL_REVID_G0		0x6
#define SKL_REVID_H0		0x7
2714

2715 2716
#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))

2717
#define BXT_REVID_A0		0x0
2718
#define BXT_REVID_A1		0x1
2719
#define BXT_REVID_B0		0x3
2720
#define BXT_REVID_B_LAST	0x8
2721
#define BXT_REVID_C0		0x9
N
Nick Hoath 已提交
2722

2723 2724
#define IS_BXT_REVID(dev_priv, since, until) \
	(IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2725

M
Mika Kuoppala 已提交
2726 2727
#define KBL_REVID_A0		0x0
#define KBL_REVID_B0		0x1
2728 2729 2730
#define KBL_REVID_C0		0x2
#define KBL_REVID_D0		0x3
#define KBL_REVID_E0		0x4
M
Mika Kuoppala 已提交
2731

2732 2733
#define IS_KBL_REVID(dev_priv, since, until) \
	(IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
M
Mika Kuoppala 已提交
2734

2735 2736 2737 2738 2739 2740
#define GLK_REVID_A0		0x0
#define GLK_REVID_A1		0x1

#define IS_GLK_REVID(dev_priv, since, until) \
	(IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))

2741 2742 2743 2744 2745 2746
/*
 * The genX designation typically refers to the render engine, so render
 * capability related checks should use IS_GEN, while display and other checks
 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
 * chips, etc.).
 */
2747 2748 2749 2750 2751 2752 2753 2754
#define IS_GEN2(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(1)))
#define IS_GEN3(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(2)))
#define IS_GEN4(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(3)))
#define IS_GEN5(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(4)))
#define IS_GEN6(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(5)))
#define IS_GEN7(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(6)))
#define IS_GEN8(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(7)))
#define IS_GEN9(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(8)))
2755

2756
#define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
2757 2758
#define IS_GEN9_LP(dev_priv)	(IS_GEN9(dev_priv) && IS_LP(dev_priv))
#define IS_GEN9_BC(dev_priv)	(IS_GEN9(dev_priv) && !IS_LP(dev_priv))
2759

2760 2761 2762 2763 2764 2765 2766 2767 2768
#define ENGINE_MASK(id)	BIT(id)
#define RENDER_RING	ENGINE_MASK(RCS)
#define BSD_RING	ENGINE_MASK(VCS)
#define BLT_RING	ENGINE_MASK(BCS)
#define VEBOX_RING	ENGINE_MASK(VECS)
#define BSD2_RING	ENGINE_MASK(VCS2)
#define ALL_ENGINES	(~0)

#define HAS_ENGINE(dev_priv, id) \
2769
	(!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2770 2771 2772 2773 2774 2775

#define HAS_BSD(dev_priv)	HAS_ENGINE(dev_priv, VCS)
#define HAS_BSD2(dev_priv)	HAS_ENGINE(dev_priv, VCS2)
#define HAS_BLT(dev_priv)	HAS_ENGINE(dev_priv, BCS)
#define HAS_VEBOX(dev_priv)	HAS_ENGINE(dev_priv, VECS)

2776 2777 2778
#define HAS_LLC(dev_priv)	((dev_priv)->info.has_llc)
#define HAS_SNOOP(dev_priv)	((dev_priv)->info.has_snoop)
#define HAS_EDRAM(dev_priv)	(!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2779 2780
#define HAS_WT(dev_priv)	((IS_HASWELL(dev_priv) || \
				 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2781

2782
#define HWS_NEEDS_PHYSICAL(dev_priv)	((dev_priv)->info.hws_needs_physical)
2783

2784 2785 2786 2787 2788 2789 2790 2791 2792
#define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
		((dev_priv)->info.has_logical_ring_contexts)
#define USES_PPGTT(dev_priv)		(i915.enable_ppgtt)
#define USES_FULL_PPGTT(dev_priv)	(i915.enable_ppgtt >= 2)
#define USES_FULL_48BIT_PPGTT(dev_priv)	(i915.enable_ppgtt == 3)

#define HAS_OVERLAY(dev_priv)		 ((dev_priv)->info.has_overlay)
#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
		((dev_priv)->info.overlay_needs_physical)
2793

2794
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
2795
#define HAS_BROKEN_CS_TLB(dev_priv)	(IS_I830(dev_priv) || IS_I845G(dev_priv))
2796 2797

/* WaRsDisableCoarsePowerGating:skl,bxt */
2798
#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2799
	(IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2800

2801 2802 2803 2804 2805 2806
/*
 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
 * even when in MSI mode. This results in spurious interrupt warnings if the
 * legacy irq no. is shared with another device. The kernel then disables that
 * interrupt source and so prevents the other device from working properly.
 */
2807 2808
#define HAS_AUX_IRQ(dev_priv)   ((dev_priv)->info.gen >= 5)
#define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
2809

2810 2811 2812
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 * rows, which changed the alignment requirements and fence programming.
 */
2813 2814 2815
#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
					 !(IS_I915G(dev_priv) || \
					 IS_I915GM(dev_priv)))
2816 2817
#define SUPPORTS_TV(dev_priv)		((dev_priv)->info.supports_tv)
#define I915_HAS_HOTPLUG(dev_priv)	((dev_priv)->info.has_hotplug)
2818

2819 2820 2821
#define HAS_FW_BLC(dev_priv) 	(INTEL_GEN(dev_priv) > 2)
#define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
#define HAS_FBC(dev_priv)	((dev_priv)->info.has_fbc)
2822
#define HAS_CUR_FBC(dev_priv)	(!HAS_GMCH_DISPLAY(dev_priv) && INTEL_INFO(dev_priv)->gen >= 7)
2823

2824
#define HAS_IPS(dev_priv)	(IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2825

2826
#define HAS_DP_MST(dev_priv)	((dev_priv)->info.has_dp_mst)
2827

2828 2829 2830 2831 2832
#define HAS_DDI(dev_priv)		 ((dev_priv)->info.has_ddi)
#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
#define HAS_PSR(dev_priv)		 ((dev_priv)->info.has_psr)
#define HAS_RC6(dev_priv)		 ((dev_priv)->info.has_rc6)
#define HAS_RC6p(dev_priv)		 ((dev_priv)->info.has_rc6p)
P
Paulo Zanoni 已提交
2833

2834
#define HAS_CSR(dev_priv)	((dev_priv)->info.has_csr)
2835

2836
#define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2837 2838
#define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)

2839 2840 2841 2842 2843
/*
 * For now, anything with a GuC requires uCode loading, and then supports
 * command submission once loaded. But these are logically independent
 * properties, so we have separate macros to test them.
 */
2844 2845 2846
#define HAS_GUC(dev_priv)	((dev_priv)->info.has_guc)
#define HAS_GUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
#define HAS_GUC_SCHED(dev_priv)	(HAS_GUC(dev_priv))
2847
#define HAS_HUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
2848

2849
#define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2850

2851
#define HAS_POOLED_EU(dev_priv)	((dev_priv)->info.has_pooled_eu)
2852

2853 2854 2855 2856 2857 2858
#define INTEL_PCH_DEVICE_ID_MASK		0xff00
#define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
#define INTEL_PCH_PPT_DEVICE_ID_TYPE		0x1e00
#define INTEL_PCH_LPT_DEVICE_ID_TYPE		0x8c00
#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE		0x9c00
2859 2860
#define INTEL_PCH_SPT_DEVICE_ID_TYPE		0xA100
#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE		0x9D00
2861
#define INTEL_PCH_KBP_DEVICE_ID_TYPE		0xA200
2862
#define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
2863
#define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
2864
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
2865

2866 2867 2868 2869
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
#define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2870 2871 2872 2873
#define HAS_PCH_LPT_LP(dev_priv) \
	((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
#define HAS_PCH_LPT_H(dev_priv) \
	((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2874 2875 2876 2877
#define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
#define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2878

2879
#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2880

2881 2882
#define HAS_LSPCON(dev_priv) (IS_GEN9(dev_priv))

2883
/* DPF == dynamic parity feature */
2884
#define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2885 2886
#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
				 2 : HAS_L3_DPF(dev_priv))
2887

2888
#define GT_FREQUENCY_MULTIPLIER 50
A
Akash Goel 已提交
2889
#define GEN9_FREQ_SCALER 3
2890

2891 2892
#define HAS_DECOUPLED_MMIO(dev_priv) (INTEL_INFO(dev_priv)->has_decoupled_mmio)

2893 2894
#include "i915_trace.h"

2895 2896 2897 2898 2899 2900 2901 2902 2903
static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
{
#ifdef CONFIG_INTEL_IOMMU
	if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped)
		return true;
#endif
	return false;
}

2904
int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2905
				int enable_ppgtt);
2906

2907 2908
bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);

2909
/* i915_drv.c */
2910 2911 2912 2913 2914 2915 2916
void __printf(3, 4)
__i915_printk(struct drm_i915_private *dev_priv, const char *level,
	      const char *fmt, ...);

#define i915_report_error(dev_priv, fmt, ...)				   \
	__i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)

2917
#ifdef CONFIG_COMPAT
D
Dave Airlie 已提交
2918 2919
extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
			      unsigned long arg);
2920 2921
#else
#define i915_compat_ioctl NULL
2922
#endif
2923 2924 2925 2926 2927
extern const struct dev_pm_ops i915_pm_ops;

extern int i915_driver_load(struct pci_dev *pdev,
			    const struct pci_device_id *ent);
extern void i915_driver_unload(struct drm_device *dev);
2928 2929
extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2930
extern void i915_reset(struct drm_i915_private *dev_priv);
2931
extern int intel_guc_reset(struct drm_i915_private *dev_priv);
2932
extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2933
extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
2934 2935 2936 2937
extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2938
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2939

2940
int intel_engines_init_mmio(struct drm_i915_private *dev_priv);
2941 2942
int intel_engines_init(struct drm_i915_private *dev_priv);

2943
/* intel_hotplug.c */
2944 2945
void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
			   u32 pin_mask, u32 long_mask);
2946 2947 2948
void intel_hpd_init(struct drm_i915_private *dev_priv);
void intel_hpd_init_work(struct drm_i915_private *dev_priv);
void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2949
bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2950 2951
bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2952

L
Linus Torvalds 已提交
2953
/* i915_irq.c */
2954 2955 2956 2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970
static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
{
	unsigned long delay;

	if (unlikely(!i915.enable_hangcheck))
		return;

	/* Don't continually defer the hangcheck so that it is always run at
	 * least once after work has been scheduled on any ring. Otherwise,
	 * we will ignore a hung ring if a second ring is kept busy.
	 */

	delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
	queue_delayed_work(system_long_wq,
			   &dev_priv->gpu_error.hangcheck_work, delay);
}

2971
__printf(3, 4)
2972 2973
void i915_handle_error(struct drm_i915_private *dev_priv,
		       u32 engine_mask,
2974
		       const char *fmt, ...);
L
Linus Torvalds 已提交
2975

2976
extern void intel_irq_init(struct drm_i915_private *dev_priv);
2977
extern void intel_irq_fini(struct drm_i915_private *dev_priv);
2978 2979
int intel_irq_install(struct drm_i915_private *dev_priv);
void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2980

2981 2982
static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
{
2983
	return dev_priv->gvt;
2984 2985
}

2986
static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2987
{
2988
	return dev_priv->vgpu.active;
2989
}
2990

2991
void
2992
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2993
		     u32 status_mask);
2994 2995

void
2996
i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2997
		      u32 status_mask);
2998

2999 3000
void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
3001 3002 3003
void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
				   uint32_t mask,
				   uint32_t bits);
3004 3005 3006 3007 3008 3009 3010 3011 3012 3013 3014 3015 3016
void ilk_update_display_irq(struct drm_i915_private *dev_priv,
			    uint32_t interrupt_mask,
			    uint32_t enabled_irq_mask);
static inline void
ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, bits);
}
static inline void
ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, 0);
}
3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 3027 3028 3029 3030
void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
			 enum pipe pipe,
			 uint32_t interrupt_mask,
			 uint32_t enabled_irq_mask);
static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
				       enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
}
static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
					enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
}
3031 3032 3033
void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
				  uint32_t interrupt_mask,
				  uint32_t enabled_irq_mask);
3034 3035 3036 3037 3038 3039 3040 3041 3042 3043 3044
static inline void
ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, bits);
}
static inline void
ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, 0);
}

3045 3046 3047 3048 3049 3050 3051 3052 3053
/* i915_gem.c */
int i915_gem_create_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3054 3055
int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3056 3057 3058 3059 3060 3061
int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
			     struct drm_file *file_priv);
int i915_gem_execbuffer(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
J
Jesse Barnes 已提交
3062 3063
int i915_gem_execbuffer2(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
3064 3065
int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
B
Ben Widawsky 已提交
3066 3067 3068 3069
int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
3070 3071
int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *file_priv);
3072 3073
int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
3074 3075 3076 3077
int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
3078
void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
3079 3080
int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file);
3081 3082
int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
3083 3084
int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3085
void i915_gem_sanitize(struct drm_i915_private *i915);
3086 3087
int i915_gem_load_init(struct drm_i915_private *dev_priv);
void i915_gem_load_cleanup(struct drm_i915_private *dev_priv);
3088
void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3089
int i915_gem_freeze(struct drm_i915_private *dev_priv);
3090 3091
int i915_gem_freeze_late(struct drm_i915_private *dev_priv);

3092
void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
3093
void i915_gem_object_free(struct drm_i915_gem_object *obj);
3094 3095
void i915_gem_object_init(struct drm_i915_gem_object *obj,
			 const struct drm_i915_gem_object_ops *ops);
3096 3097 3098 3099 3100
struct drm_i915_gem_object *
i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
struct drm_i915_gem_object *
i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
				 const void *data, size_t size);
3101
void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
3102
void i915_gem_free_object(struct drm_gem_object *obj);
3103

3104 3105 3106 3107 3108 3109 3110 3111 3112 3113 3114 3115 3116
static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
{
	/* A single pass should suffice to release all the freed objects (along
	 * most call paths) , but be a little more paranoid in that freeing
	 * the objects does take a little amount of time, during which the rcu
	 * callbacks could have added new objects into the freed list, and
	 * armed the work again.
	 */
	do {
		rcu_barrier();
	} while (flush_work(&i915->mm.free_work));
}

C
Chris Wilson 已提交
3117
struct i915_vma * __must_check
3118 3119
i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
			 const struct i915_ggtt_view *view,
3120
			 u64 size,
3121 3122
			 u64 alignment,
			 u64 flags);
3123

3124
int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
3125
void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3126

3127 3128
void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);

C
Chris Wilson 已提交
3129
static inline int __sg_page_count(const struct scatterlist *sg)
3130
{
3131 3132
	return sg->length >> PAGE_SHIFT;
}
3133

3134 3135 3136
struct scatterlist *
i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
		       unsigned int n, unsigned int *offset);
3137

3138 3139 3140
struct page *
i915_gem_object_get_page(struct drm_i915_gem_object *obj,
			 unsigned int n);
3141

3142 3143 3144
struct page *
i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
			       unsigned int n);
3145

3146 3147 3148
dma_addr_t
i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
				unsigned long n);
3149

3150 3151
void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
				 struct sg_table *pages);
C
Chris Wilson 已提交
3152 3153 3154 3155 3156
int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);

static inline int __must_check
i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
{
3157
	might_lock(&obj->mm.lock);
C
Chris Wilson 已提交
3158

3159
	if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
C
Chris Wilson 已提交
3160 3161 3162 3163 3164 3165 3166
		return 0;

	return __i915_gem_object_get_pages(obj);
}

static inline void
__i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3167
{
C
Chris Wilson 已提交
3168 3169
	GEM_BUG_ON(!obj->mm.pages);

3170
	atomic_inc(&obj->mm.pages_pin_count);
C
Chris Wilson 已提交
3171 3172 3173 3174 3175
}

static inline bool
i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
{
3176
	return atomic_read(&obj->mm.pages_pin_count);
C
Chris Wilson 已提交
3177 3178 3179 3180 3181 3182 3183 3184
}

static inline void
__i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
{
	GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
	GEM_BUG_ON(!obj->mm.pages);

3185
	atomic_dec(&obj->mm.pages_pin_count);
3186
}
3187

3188 3189
static inline void
i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3190
{
C
Chris Wilson 已提交
3191
	__i915_gem_object_unpin_pages(obj);
3192 3193
}

3194 3195 3196 3197 3198 3199 3200
enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
	I915_MM_NORMAL = 0,
	I915_MM_SHRINKER
};

void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
				 enum i915_mm_subclass subclass);
3201
void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
C
Chris Wilson 已提交
3202

3203 3204 3205 3206 3207
enum i915_map_type {
	I915_MAP_WB = 0,
	I915_MAP_WC,
};

3208 3209
/**
 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3210 3211
 * @obj: the object to map into kernel address space
 * @type: the type of mapping, used to select pgprot_t
3212 3213 3214
 *
 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
 * pages and then returns a contiguous mapping of the backing storage into
3215 3216
 * the kernel address space. Based on the @type of mapping, the PTE will be
 * set to either WriteBack or WriteCombine (via pgprot_t).
3217
 *
3218 3219
 * The caller is responsible for calling i915_gem_object_unpin_map() when the
 * mapping is no longer required.
3220
 *
3221 3222
 * Returns the pointer through which to access the mapped object, or an
 * ERR_PTR() on error.
3223
 */
3224 3225
void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
					   enum i915_map_type type);
3226 3227 3228

/**
 * i915_gem_object_unpin_map - releases an earlier mapping
3229
 * @obj: the object to unmap
3230 3231 3232 3233 3234 3235 3236 3237 3238 3239 3240
 *
 * After pinning the object and mapping its pages, once you are finished
 * with your access, call i915_gem_object_unpin_map() to release the pin
 * upon the mapping. Once the pin count reaches zero, that mapping may be
 * removed.
 */
static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
{
	i915_gem_object_unpin_pages(obj);
}

3241 3242 3243 3244
int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
				    unsigned int *needs_clflush);
int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
				     unsigned int *needs_clflush);
3245 3246 3247
#define CLFLUSH_BEFORE	BIT(0)
#define CLFLUSH_AFTER	BIT(1)
#define CLFLUSH_FLAGS	(CLFLUSH_BEFORE | CLFLUSH_AFTER)
3248 3249 3250 3251 3252 3253 3254

static inline void
i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
{
	i915_gem_object_unpin_pages(obj);
}

3255
int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
B
Ben Widawsky 已提交
3256
void i915_vma_move_to_active(struct i915_vma *vma,
3257 3258
			     struct drm_i915_gem_request *req,
			     unsigned int flags);
3259 3260 3261
int i915_gem_dumb_create(struct drm_file *file_priv,
			 struct drm_device *dev,
			 struct drm_mode_create_dumb *args);
3262 3263
int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
		      uint32_t handle, uint64_t *offset);
3264
int i915_gem_mmap_gtt_version(void);
3265 3266 3267 3268 3269

void i915_gem_track_fb(struct drm_i915_gem_object *old,
		       struct drm_i915_gem_object *new,
		       unsigned frontbuffer_bits);

3270
int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3271

3272
struct drm_i915_gem_request *
3273
i915_gem_find_active_request(struct intel_engine_cs *engine);
3274

3275
void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3276

3277 3278 3279 3280 3281 3282
static inline bool i915_reset_backoff(struct i915_gpu_error *error)
{
	return unlikely(test_bit(I915_RESET_BACKOFF, &error->flags));
}

static inline bool i915_reset_handoff(struct i915_gpu_error *error)
3283
{
3284
	return unlikely(test_bit(I915_RESET_HANDOFF, &error->flags));
3285 3286
}

3287
static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3288
{
3289
	return unlikely(test_bit(I915_WEDGED, &error->flags));
3290 3291
}

3292
static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error *error)
3293
{
3294
	return i915_reset_backoff(error) | i915_terminally_wedged(error);
M
Mika Kuoppala 已提交
3295 3296 3297 3298
}

static inline u32 i915_reset_count(struct i915_gpu_error *error)
{
3299
	return READ_ONCE(error->reset_count);
3300
}
3301

3302
int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
3303
void i915_gem_reset(struct drm_i915_private *dev_priv);
3304
void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
3305
void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3306
bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
3307

3308
void i915_gem_init_mmio(struct drm_i915_private *i915);
3309 3310
int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3311
void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3312
void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3313 3314
int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
			   unsigned int flags);
3315 3316
int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
void i915_gem_resume(struct drm_i915_private *dev_priv);
3317
int i915_gem_fault(struct vm_fault *vmf);
3318 3319 3320 3321
int i915_gem_object_wait(struct drm_i915_gem_object *obj,
			 unsigned int flags,
			 long timeout,
			 struct intel_rps_client *rps);
3322 3323 3324 3325 3326
int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
				  unsigned int flags,
				  int priority);
#define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX

3327
int __must_check
3328 3329 3330
i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write);
int __must_check
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write);
3331
int __must_check
3332
i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
C
Chris Wilson 已提交
3333
struct i915_vma * __must_check
3334 3335
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
				     u32 alignment,
3336
				     const struct i915_ggtt_view *view);
C
Chris Wilson 已提交
3337
void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3338
int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3339
				int align);
3340
int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3341
void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3342

3343 3344 3345
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
				    enum i915_cache_level cache_level);

3346 3347 3348 3349 3350 3351
struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
				struct dma_buf *dma_buf);

struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
				struct drm_gem_object *gem_obj, int flags);

3352 3353 3354 3355 3356 3357
static inline struct i915_hw_ppgtt *
i915_vm_to_ppgtt(struct i915_address_space *vm)
{
	return container_of(vm, struct i915_hw_ppgtt, base);
}

J
Joonas Lahtinen 已提交
3358
/* i915_gem_fence_reg.c */
3359 3360 3361
int __must_check i915_vma_get_fence(struct i915_vma *vma);
int __must_check i915_vma_put_fence(struct i915_vma *vma);

3362
void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
3363
void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3364

3365
void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3366 3367 3368 3369
void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
				       struct sg_table *pages);
void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
					 struct sg_table *pages);
3370

3371 3372 3373 3374 3375
static inline struct i915_gem_context *
i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
{
	struct i915_gem_context *ctx;

3376
	lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
3377 3378 3379 3380 3381 3382 3383 3384

	ctx = idr_find(&file_priv->context_idr, id);
	if (!ctx)
		return ERR_PTR(-ENOENT);

	return ctx;
}

3385 3386
static inline struct i915_gem_context *
i915_gem_context_get(struct i915_gem_context *ctx)
3387
{
3388
	kref_get(&ctx->ref);
3389
	return ctx;
3390 3391
}

3392
static inline void i915_gem_context_put(struct i915_gem_context *ctx)
3393
{
3394
	lockdep_assert_held(&ctx->i915->drm.struct_mutex);
3395
	kref_put(&ctx->ref, i915_gem_context_free);
3396 3397
}

3398 3399
static inline void i915_gem_context_put_unlocked(struct i915_gem_context *ctx)
{
3400 3401 3402 3403
	struct mutex *lock = &ctx->i915->drm.struct_mutex;

	if (kref_put_mutex(&ctx->ref, i915_gem_context_free, lock))
		mutex_unlock(lock);
3404 3405
}

C
Chris Wilson 已提交
3406 3407 3408 3409 3410 3411 3412 3413 3414 3415
static inline struct intel_timeline *
i915_gem_context_lookup_timeline(struct i915_gem_context *ctx,
				 struct intel_engine_cs *engine)
{
	struct i915_address_space *vm;

	vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base;
	return &vm->timeline.engine[engine->id];
}

3416 3417 3418
int i915_perf_open_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file);

3419
/* i915_gem_evict.c */
3420
int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3421
					  u64 min_size, u64 alignment,
3422
					  unsigned cache_level,
3423
					  u64 start, u64 end,
3424
					  unsigned flags);
3425 3426 3427
int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
					 struct drm_mm_node *node,
					 unsigned int flags);
3428
int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3429

3430
/* belongs in i915_gem_gtt.h */
3431
static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3432
{
3433
	wmb();
3434
	if (INTEL_GEN(dev_priv) < 6)
3435 3436
		intel_gtt_chipset_flush();
}
3437

3438
/* i915_gem_stolen.c */
3439 3440 3441
int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
				struct drm_mm_node *node, u64 size,
				unsigned alignment);
3442 3443 3444 3445
int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
					 struct drm_mm_node *node, u64 size,
					 unsigned alignment, u64 start,
					 u64 end);
3446 3447
void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
				 struct drm_mm_node *node);
3448
int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3449
void i915_gem_cleanup_stolen(struct drm_device *dev);
3450
struct drm_i915_gem_object *
3451
i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, u32 size);
3452
struct drm_i915_gem_object *
3453
i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3454 3455 3456
					       u32 stolen_offset,
					       u32 gtt_offset,
					       u32 size);
3457

3458 3459 3460
/* i915_gem_internal.c */
struct drm_i915_gem_object *
i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3461
				phys_addr_t size);
3462

3463 3464
/* i915_gem_shrinker.c */
unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3465
			      unsigned long target,
3466 3467 3468 3469
			      unsigned flags);
#define I915_SHRINK_PURGEABLE 0x1
#define I915_SHRINK_UNBOUND 0x2
#define I915_SHRINK_BOUND 0x4
3470
#define I915_SHRINK_ACTIVE 0x8
3471
#define I915_SHRINK_VMAPS 0x10
3472 3473
unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3474
void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3475 3476


3477
/* i915_gem_tiling.c */
3478
static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3479
{
3480
	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3481 3482

	return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3483
		i915_gem_object_is_tiled(obj);
3484 3485
}

3486 3487 3488 3489 3490
u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
			unsigned int tiling, unsigned int stride);
u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
			     unsigned int tiling, unsigned int stride);

3491
/* i915_debugfs.c */
3492
#ifdef CONFIG_DEBUG_FS
3493
int i915_debugfs_register(struct drm_i915_private *dev_priv);
J
Jani Nikula 已提交
3494
int i915_debugfs_connector_add(struct drm_connector *connector);
3495
void intel_display_crc_init(struct drm_i915_private *dev_priv);
3496
#else
3497
static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3498 3499
static inline int i915_debugfs_connector_add(struct drm_connector *connector)
{ return 0; }
3500
static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3501
#endif
3502 3503

/* i915_gpu_error.c */
3504 3505
#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)

3506 3507
__printf(2, 3)
void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3508
int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3509
			    const struct i915_gpu_state *gpu);
3510
int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3511
			      struct drm_i915_private *i915,
3512 3513 3514 3515 3516 3517
			      size_t count, loff_t pos);
static inline void i915_error_state_buf_release(
	struct drm_i915_error_state_buf *eb)
{
	kfree(eb->buf);
}
3518 3519

struct i915_gpu_state *i915_capture_gpu_state(struct drm_i915_private *i915);
3520 3521
void i915_capture_error_state(struct drm_i915_private *dev_priv,
			      u32 engine_mask,
3522
			      const char *error_msg);
3523 3524 3525 3526 3527 3528 3529 3530 3531 3532 3533 3534 3535 3536 3537 3538 3539

static inline struct i915_gpu_state *
i915_gpu_state_get(struct i915_gpu_state *gpu)
{
	kref_get(&gpu->ref);
	return gpu;
}

void __i915_gpu_state_free(struct kref *kref);
static inline void i915_gpu_state_put(struct i915_gpu_state *gpu)
{
	if (gpu)
		kref_put(&gpu->ref, __i915_gpu_state_free);
}

struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915);
void i915_reset_error_state(struct drm_i915_private *i915);
3540

3541 3542 3543 3544 3545 3546 3547 3548
#else

static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
					    u32 engine_mask,
					    const char *error_msg)
{
}

3549 3550 3551 3552 3553 3554 3555
static inline struct i915_gpu_state *
i915_first_error_state(struct drm_i915_private *i915)
{
	return NULL;
}

static inline void i915_reset_error_state(struct drm_i915_private *i915)
3556 3557 3558 3559 3560
{
}

#endif

3561
const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3562

3563
/* i915_cmd_parser.c */
3564
int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3565
void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3566 3567 3568 3569 3570 3571 3572
void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
int intel_engine_cmd_parser(struct intel_engine_cs *engine,
			    struct drm_i915_gem_object *batch_obj,
			    struct drm_i915_gem_object *shadow_batch_obj,
			    u32 batch_start_offset,
			    u32 batch_len,
			    bool is_master);
3573

3574 3575 3576
/* i915_perf.c */
extern void i915_perf_init(struct drm_i915_private *dev_priv);
extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3577 3578
extern void i915_perf_register(struct drm_i915_private *dev_priv);
extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3579

3580
/* i915_suspend.c */
3581 3582
extern int i915_save_state(struct drm_i915_private *dev_priv);
extern int i915_restore_state(struct drm_i915_private *dev_priv);
3583

B
Ben Widawsky 已提交
3584
/* i915_sysfs.c */
D
David Weinehall 已提交
3585 3586
void i915_setup_sysfs(struct drm_i915_private *dev_priv);
void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
B
Ben Widawsky 已提交
3587

3588 3589 3590 3591
/* intel_lpe_audio.c */
int  intel_lpe_audio_init(struct drm_i915_private *dev_priv);
void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv);
void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv);
3592
void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
3593 3594
			    enum pipe pipe, enum port port,
			    const void *eld, int ls_clock, bool dp_output);
3595

3596
/* intel_i2c.c */
3597 3598
extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3599 3600
extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
				     unsigned int pin);
3601

3602 3603
extern struct i2c_adapter *
intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
C
Chris Wilson 已提交
3604 3605
extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3606
static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3607 3608 3609
{
	return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
}
3610
extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3611

3612
/* intel_bios.c */
3613
void intel_bios_init(struct drm_i915_private *dev_priv);
J
Jani Nikula 已提交
3614
bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3615
bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3616
bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3617
bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3618
bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3619
bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3620
bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3621 3622
bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
				     enum port port);
3623 3624 3625
bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
				enum port port);

3626

3627
/* intel_opregion.c */
3628
#ifdef CONFIG_ACPI
3629
extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3630 3631
extern void intel_opregion_register(struct drm_i915_private *dev_priv);
extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3632
extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3633 3634
extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
					 bool enable);
3635
extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3636
					 pci_power_t state);
3637
extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3638
#else
3639
static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3640 3641
static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
3642 3643 3644
static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
{
}
3645 3646 3647 3648 3649
static inline int
intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
{
	return 0;
}
3650
static inline int
3651
intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3652 3653 3654
{
	return 0;
}
3655
static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3656 3657 3658
{
	return -ENODEV;
}
3659
#endif
3660

J
Jesse Barnes 已提交
3661 3662 3663 3664 3665 3666 3667 3668 3669
/* intel_acpi.c */
#ifdef CONFIG_ACPI
extern void intel_register_dsm_handler(void);
extern void intel_unregister_dsm_handler(void);
#else
static inline void intel_register_dsm_handler(void) { return; }
static inline void intel_unregister_dsm_handler(void) { return; }
#endif /* CONFIG_ACPI */

3670 3671 3672 3673 3674 3675 3676
/* intel_device_info.c */
static inline struct intel_device_info *
mkwrite_device_info(struct drm_i915_private *dev_priv)
{
	return (struct intel_device_info *)&dev_priv->info;
}

3677
const char *intel_platform_name(enum intel_platform platform);
3678 3679 3680
void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
void intel_device_info_dump(struct drm_i915_private *dev_priv);

J
Jesse Barnes 已提交
3681
/* modesetting */
3682
extern void intel_modeset_init_hw(struct drm_device *dev);
3683
extern int intel_modeset_init(struct drm_device *dev);
3684
extern void intel_modeset_gem_init(struct drm_device *dev);
J
Jesse Barnes 已提交
3685
extern void intel_modeset_cleanup(struct drm_device *dev);
3686
extern int intel_connector_register(struct drm_connector *);
3687
extern void intel_connector_unregister(struct drm_connector *);
3688 3689
extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
				       bool state);
3690
extern void intel_display_resume(struct drm_device *dev);
3691 3692
extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3693
extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3694
extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3695
extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3696
extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3697
				  bool enable);
3698

B
Ben Widawsky 已提交
3699 3700
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file);
3701

3702
/* overlay */
3703 3704
extern struct intel_overlay_error_state *
intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3705 3706
extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
					    struct intel_overlay_error_state *error);
3707

3708 3709
extern struct intel_display_error_state *
intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3710
extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3711
					    struct intel_display_error_state *error);
3712

3713 3714
int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3715 3716
int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
		      u32 reply_mask, u32 reply, int timeout_base_ms);
3717 3718

/* intel_sideband.c */
3719
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3720
int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3721
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3722 3723
u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3724 3725 3726 3727
u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3728 3729
u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3730 3731
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3732 3733 3734 3735
u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
		   enum intel_sbi_destination destination);
void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
		     enum intel_sbi_destination destination);
3736 3737
u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3738

3739
/* intel_dpio_phy.c */
3740
void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3741
			     enum dpio_phy *phy, enum dpio_channel *ch);
3742 3743 3744
void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
				  enum port port, u32 margin, u32 scale,
				  u32 enable, u32 deemphasis);
3745 3746 3747 3748 3749 3750 3751 3752 3753 3754 3755 3756
void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
			    enum dpio_phy phy);
bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
			      enum dpio_phy phy);
uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
					     uint8_t lane_count);
void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
				     uint8_t lane_lat_optim_mask);
uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);

3757 3758 3759
void chv_set_phy_signal_level(struct intel_encoder *encoder,
			      u32 deemph_reg_value, u32 margin_reg_value,
			      bool uniq_trans_scale);
3760 3761
void chv_data_lane_soft_reset(struct intel_encoder *encoder,
			      bool reset);
3762
void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3763 3764
void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3765
void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3766

3767 3768 3769
void vlv_set_phy_signal_level(struct intel_encoder *encoder,
			      u32 demph_reg_value, u32 preemph_reg_value,
			      u32 uniqtranscale_reg_value, u32 tx3_demph);
3770
void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3771
void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3772
void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3773

3774 3775
int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3776 3777
u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
			   const i915_reg_t reg);
3778

3779 3780 3781 3782 3783 3784 3785 3786 3787 3788 3789 3790 3791
#define I915_READ8(reg)		dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
#define I915_WRITE8(reg, val)	dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)

#define I915_READ16(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
#define I915_WRITE16(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
#define I915_READ16_NOTRACE(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
#define I915_WRITE16_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)

#define I915_READ(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
#define I915_WRITE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
#define I915_READ_NOTRACE(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
#define I915_WRITE_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)

3792 3793 3794 3795
/* Be very careful with read/write 64-bit values. On 32-bit machines, they
 * will be implemented using 2 32-bit writes in an arbitrary order with
 * an arbitrary delay between them. This can cause the hardware to
 * act upon the intermediate value, possibly leading to corruption and
3796 3797 3798 3799 3800 3801 3802 3803 3804
 * machine death. For this reason we do not support I915_WRITE64, or
 * dev_priv->uncore.funcs.mmio_writeq.
 *
 * When reading a 64-bit value as two 32-bit values, the delay may cause
 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
 * occasionally a 64-bit register does not actualy support a full readq
 * and must be read using two 32-bit reads.
 *
 * You have been warned.
3805
 */
3806
#define I915_READ64(reg)	dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3807

3808
#define I915_READ64_2x32(lower_reg, upper_reg) ({			\
3809 3810
	u32 upper, lower, old_upper, loop = 0;				\
	upper = I915_READ(upper_reg);					\
3811
	do {								\
3812
		old_upper = upper;					\
3813
		lower = I915_READ(lower_reg);				\
3814 3815
		upper = I915_READ(upper_reg);				\
	} while (upper != old_upper && loop++ < 2);			\
3816
	(u64)upper << 32 | lower; })
3817

3818 3819 3820
#define POSTING_READ(reg)	(void)I915_READ_NOTRACE(reg)
#define POSTING_READ16(reg)	(void)I915_READ16_NOTRACE(reg)

3821
#define __raw_read(x, s) \
3822
static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
3823
					     i915_reg_t reg) \
3824
{ \
3825
	return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3826 3827 3828
}

#define __raw_write(x, s) \
3829
static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
3830
				       i915_reg_t reg, uint##x##_t val) \
3831
{ \
3832
	write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3833 3834 3835 3836 3837 3838 3839 3840 3841 3842 3843 3844 3845 3846
}
__raw_read(8, b)
__raw_read(16, w)
__raw_read(32, l)
__raw_read(64, q)

__raw_write(8, b)
__raw_write(16, w)
__raw_write(32, l)
__raw_write(64, q)

#undef __raw_read
#undef __raw_write

3847
/* These are untraced mmio-accessors that are only valid to be used inside
3848
 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3849
 * controlled.
3850
 *
3851
 * Think twice, and think again, before using these.
3852 3853 3854 3855 3856 3857 3858 3859 3860 3861 3862 3863 3864 3865 3866 3867 3868 3869 3870 3871
 *
 * As an example, these accessors can possibly be used between:
 *
 * spin_lock_irq(&dev_priv->uncore.lock);
 * intel_uncore_forcewake_get__locked();
 *
 * and
 *
 * intel_uncore_forcewake_put__locked();
 * spin_unlock_irq(&dev_priv->uncore.lock);
 *
 *
 * Note: some registers may not need forcewake held, so
 * intel_uncore_forcewake_{get,put} can be omitted, see
 * intel_uncore_forcewake_for_reg().
 *
 * Certain architectures will die if the same cacheline is concurrently accessed
 * by different clients (e.g. on Ivybridge). Access to registers should
 * therefore generally be serialised, by either the dev_priv->uncore.lock or
 * a more localised lock guarding all access to that bank of registers.
3872
 */
3873 3874
#define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3875
#define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3876 3877
#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)

3878 3879 3880 3881
/* "Broadcast RGB" property */
#define INTEL_BROADCAST_RGB_AUTO 0
#define INTEL_BROADCAST_RGB_FULL 1
#define INTEL_BROADCAST_RGB_LIMITED 2
3882

3883
static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
3884
{
3885
	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3886
		return VLV_VGACNTRL;
3887
	else if (INTEL_GEN(dev_priv) >= 5)
3888
		return CPU_VGACNTRL;
3889 3890 3891 3892
	else
		return VGACNTRL;
}

3893 3894 3895 3896 3897 3898 3899
static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
{
	unsigned long j = msecs_to_jiffies(m);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

3900 3901 3902 3903 3904
static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
{
        return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
}

3905 3906 3907 3908 3909 3910 3911 3912
static inline unsigned long
timespec_to_jiffies_timeout(const struct timespec *value)
{
	unsigned long j = timespec_to_jiffies(value);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

3913 3914 3915 3916 3917 3918 3919 3920 3921
/*
 * If you need to wait X milliseconds between events A and B, but event B
 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
 * when event A happened, then just before event B you call this function and
 * pass the timestamp as the first argument, and X as the second argument.
 */
static inline void
wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
{
3922
	unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3923 3924 3925 3926 3927 3928 3929 3930 3931 3932

	/*
	 * Don't re-read the value of "jiffies" every time since it may change
	 * behind our back and break the math.
	 */
	tmp_jiffies = jiffies;
	target_jiffies = timestamp_jiffies +
			 msecs_to_jiffies_timeout(to_wait_ms);

	if (time_after(target_jiffies, tmp_jiffies)) {
3933 3934 3935 3936
		remaining_jiffies = target_jiffies - tmp_jiffies;
		while (remaining_jiffies)
			remaining_jiffies =
			    schedule_timeout_uninterruptible(remaining_jiffies);
3937 3938
	}
}
3939 3940

static inline bool
3941
__i915_request_irq_complete(const struct drm_i915_gem_request *req)
3942
{
3943
	struct intel_engine_cs *engine = req->engine;
3944
	u32 seqno;
3945

3946 3947 3948 3949 3950 3951 3952 3953 3954
	/* Note that the engine may have wrapped around the seqno, and
	 * so our request->global_seqno will be ahead of the hardware,
	 * even though it completed the request before wrapping. We catch
	 * this by kicking all the waiters before resetting the seqno
	 * in hardware, and also signal the fence.
	 */
	if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &req->fence.flags))
		return true;

3955 3956 3957 3958 3959 3960 3961 3962 3963 3964
	/* The request was dequeued before we were awoken. We check after
	 * inspecting the hw to confirm that this was the same request
	 * that generated the HWS update. The memory barriers within
	 * the request execution are sufficient to ensure that a check
	 * after reading the value from hw matches this request.
	 */
	seqno = i915_gem_request_global_seqno(req);
	if (!seqno)
		return false;

3965 3966 3967
	/* Before we do the heavier coherent read of the seqno,
	 * check the value (hopefully) in the CPU cacheline.
	 */
3968
	if (__i915_gem_request_completed(req, seqno))
3969 3970
		return true;

3971 3972 3973 3974 3975 3976 3977 3978 3979 3980 3981
	/* Ensure our read of the seqno is coherent so that we
	 * do not "miss an interrupt" (i.e. if this is the last
	 * request and the seqno write from the GPU is not visible
	 * by the time the interrupt fires, we will see that the
	 * request is incomplete and go back to sleep awaiting
	 * another interrupt that will never come.)
	 *
	 * Strictly, we only need to do this once after an interrupt,
	 * but it is easier and safer to do it every time the waiter
	 * is woken.
	 */
3982
	if (engine->irq_seqno_barrier &&
3983
	    test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) {
3984
		struct intel_breadcrumbs *b = &engine->breadcrumbs;
3985

3986 3987 3988 3989 3990 3991 3992 3993 3994 3995 3996 3997
		/* The ordering of irq_posted versus applying the barrier
		 * is crucial. The clearing of the current irq_posted must
		 * be visible before we perform the barrier operation,
		 * such that if a subsequent interrupt arrives, irq_posted
		 * is reasserted and our task rewoken (which causes us to
		 * do another __i915_request_irq_complete() immediately
		 * and reapply the barrier). Conversely, if the clear
		 * occurs after the barrier, then an interrupt that arrived
		 * whilst we waited on the barrier would not trigger a
		 * barrier on the next pass, and the read may not see the
		 * seqno update.
		 */
3998
		engine->irq_seqno_barrier(engine);
3999 4000 4001 4002 4003 4004 4005

		/* If we consume the irq, but we are no longer the bottom-half,
		 * the real bottom-half may not have serialised their own
		 * seqno check with the irq-barrier (i.e. may have inspected
		 * the seqno before we believe it coherent since they see
		 * irq_posted == false but we are still running).
		 */
4006
		spin_lock_irq(&b->irq_lock);
4007
		if (b->irq_wait && b->irq_wait->tsk != current)
4008 4009 4010 4011 4012 4013
			/* Note that if the bottom-half is changed as we
			 * are sending the wake-up, the new bottom-half will
			 * be woken by whomever made the change. We only have
			 * to worry about when we steal the irq-posted for
			 * ourself.
			 */
4014
			wake_up_process(b->irq_wait->tsk);
4015
		spin_unlock_irq(&b->irq_lock);
4016

4017
		if (__i915_gem_request_completed(req, seqno))
4018 4019
			return true;
	}
4020 4021 4022 4023

	return false;
}

4024 4025 4026
void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);

4027 4028 4029 4030 4031 4032 4033 4034 4035 4036 4037 4038 4039 4040 4041 4042
/* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
 * perform the operation. To check beforehand, pass in the parameters to
 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
 * you only need to pass in the minor offsets, page-aligned pointers are
 * always valid.
 *
 * For just checking for SSE4.1, in the foreknowledge that the future use
 * will be correctly aligned, just use i915_has_memcpy_from_wc().
 */
#define i915_can_memcpy_from_wc(dst, src, len) \
	i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)

#define i915_has_memcpy_from_wc() \
	i915_memcpy_from_wc(NULL, NULL, 0)

4043 4044 4045 4046 4047
/* i915_mm.c */
int remap_io_mapping(struct vm_area_struct *vma,
		     unsigned long addr, unsigned long pfn, unsigned long size,
		     struct io_mapping *iomap);

4048 4049 4050 4051 4052 4053
static inline bool i915_gem_object_is_coherent(struct drm_i915_gem_object *obj)
{
	return (obj->cache_level != I915_CACHE_NONE ||
		HAS_LLC(to_i915(obj->base.dev)));
}

L
Linus Torvalds 已提交
4054
#endif