i915_drv.h 125.5 KB
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/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
 */
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/*
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 *
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#ifndef _I915_DRV_H_
#define _I915_DRV_H_

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#include <uapi/drm/i915_drm.h>
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#include <uapi/drm/drm_fourcc.h>
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#include <linux/io-mapping.h>
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include <linux/backlight.h>
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#include <linux/hash.h>
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#include <linux/intel-iommu.h>
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#include <linux/kref.h>
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#include <linux/pm_qos.h>
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#include <linux/reservation.h>
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#include <linux/shmem_fs.h>

#include <drm/drmP.h>
#include <drm/intel-gtt.h>
#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
#include <drm/drm_gem.h>
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#include <drm/drm_auth.h>
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#include <drm/drm_cache.h>
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#include "i915_params.h"
#include "i915_reg.h"
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#include "i915_utils.h"
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#include "intel_uncore.h"
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#include "intel_bios.h"
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#include "intel_dpll_mgr.h"
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#include "intel_uc.h"
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#include "intel_lrc.h"
#include "intel_ringbuffer.h"

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#include "i915_gem.h"
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#include "i915_gem_context.h"
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#include "i915_gem_fence_reg.h"
#include "i915_gem_object.h"
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#include "i915_gem_gtt.h"
#include "i915_gem_render_state.h"
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#include "i915_gem_request.h"
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#include "i915_gem_timeline.h"
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#include "i915_vma.h"

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#include "intel_gvt.h"

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/* General customization:
 */

#define DRIVER_NAME		"i915"
#define DRIVER_DESC		"Intel Graphics"
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#define DRIVER_DATE		"20170619"
#define DRIVER_TIMESTAMP	1497857498
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/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
 * which may not necessarily be a user visible problem.  This will either
 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
 * enable distros and users to tailor their preferred amount of i915 abrt
 * spam.
 */
#define I915_STATE_WARN(condition, format...) ({			\
	int __ret_warn_on = !!(condition);				\
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	if (unlikely(__ret_warn_on))					\
		if (!WARN(i915.verbose_state_checks, format))		\
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			DRM_ERROR(format);				\
	unlikely(__ret_warn_on);					\
})

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#define I915_STATE_WARN_ON(x)						\
	I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
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bool __i915_inject_load_failure(const char *func, int line);
#define i915_inject_load_failure() \
	__i915_inject_load_failure(__func__, __LINE__)

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typedef struct {
	uint32_t val;
} uint_fixed_16_16_t;

#define FP_16_16_MAX ({ \
	uint_fixed_16_16_t fp; \
	fp.val = UINT_MAX; \
	fp; \
})

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static inline bool is_fixed16_zero(uint_fixed_16_16_t val)
{
	if (val.val == 0)
		return true;
	return false;
}

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static inline uint_fixed_16_16_t u32_to_fixed_16_16(uint32_t val)
{
	uint_fixed_16_16_t fp;

	WARN_ON(val >> 16);

	fp.val = val << 16;
	return fp;
}

static inline uint32_t fixed_16_16_to_u32_round_up(uint_fixed_16_16_t fp)
{
	return DIV_ROUND_UP(fp.val, 1 << 16);
}

static inline uint32_t fixed_16_16_to_u32(uint_fixed_16_16_t fp)
{
	return fp.val >> 16;
}

static inline uint_fixed_16_16_t min_fixed_16_16(uint_fixed_16_16_t min1,
						 uint_fixed_16_16_t min2)
{
	uint_fixed_16_16_t min;

	min.val = min(min1.val, min2.val);
	return min;
}

static inline uint_fixed_16_16_t max_fixed_16_16(uint_fixed_16_16_t max1,
						 uint_fixed_16_16_t max2)
{
	uint_fixed_16_16_t max;

	max.val = max(max1.val, max2.val);
	return max;
}

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static inline uint32_t div_round_up_fixed16(uint_fixed_16_16_t val,
					    uint_fixed_16_16_t d)
{
	return DIV_ROUND_UP(val.val, d.val);
}

static inline uint32_t mul_round_up_u32_fixed16(uint32_t val,
						uint_fixed_16_16_t mul)
{
	uint64_t intermediate_val;
	uint32_t result;

	intermediate_val = (uint64_t) val * mul.val;
	intermediate_val = DIV_ROUND_UP_ULL(intermediate_val, 1 << 16);
	WARN_ON(intermediate_val >> 32);
	result = clamp_t(uint32_t, intermediate_val, 0, ~0);
	return result;
}

static inline uint_fixed_16_16_t mul_fixed16(uint_fixed_16_16_t val,
					     uint_fixed_16_16_t mul)
{
	uint64_t intermediate_val;
	uint_fixed_16_16_t fp;

	intermediate_val = (uint64_t) val.val * mul.val;
	intermediate_val = intermediate_val >> 16;
	WARN_ON(intermediate_val >> 32);
	fp.val = clamp_t(uint32_t, intermediate_val, 0, ~0);
	return fp;
}

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static inline uint_fixed_16_16_t fixed_16_16_div(uint32_t val, uint32_t d)
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{
	uint_fixed_16_16_t fp, res;

	fp = u32_to_fixed_16_16(val);
	res.val = DIV_ROUND_UP(fp.val, d);
	return res;
}

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static inline uint_fixed_16_16_t fixed_16_16_div_u64(uint32_t val, uint32_t d)
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{
	uint_fixed_16_16_t res;
	uint64_t interm_val;

	interm_val = (uint64_t)val << 16;
	interm_val = DIV_ROUND_UP_ULL(interm_val, d);
	WARN_ON(interm_val >> 32);
	res.val = (uint32_t) interm_val;

	return res;
}

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static inline uint32_t div_round_up_u32_fixed16(uint32_t val,
						uint_fixed_16_16_t d)
{
	uint64_t interm_val;

	interm_val = (uint64_t)val << 16;
	interm_val = DIV_ROUND_UP_ULL(interm_val, d.val);
	WARN_ON(interm_val >> 32);
	return clamp_t(uint32_t, interm_val, 0, ~0);
}

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static inline uint_fixed_16_16_t mul_u32_fixed_16_16(uint32_t val,
						     uint_fixed_16_16_t mul)
{
	uint64_t intermediate_val;
	uint_fixed_16_16_t fp;

	intermediate_val = (uint64_t) val * mul.val;
	WARN_ON(intermediate_val >> 32);
	fp.val = (uint32_t) intermediate_val;
	return fp;
}

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static inline const char *yesno(bool v)
{
	return v ? "yes" : "no";
}

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static inline const char *onoff(bool v)
{
	return v ? "on" : "off";
}

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static inline const char *enableddisabled(bool v)
{
	return v ? "enabled" : "disabled";
}

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enum pipe {
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	INVALID_PIPE = -1,
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	PIPE_A = 0,
	PIPE_B,
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	PIPE_C,
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	_PIPE_EDP,
	I915_MAX_PIPES = _PIPE_EDP
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};
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#define pipe_name(p) ((p) + 'A')
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enum transcoder {
	TRANSCODER_A = 0,
	TRANSCODER_B,
	TRANSCODER_C,
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	TRANSCODER_EDP,
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	TRANSCODER_DSI_A,
	TRANSCODER_DSI_C,
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	I915_MAX_TRANSCODERS
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};
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static inline const char *transcoder_name(enum transcoder transcoder)
{
	switch (transcoder) {
	case TRANSCODER_A:
		return "A";
	case TRANSCODER_B:
		return "B";
	case TRANSCODER_C:
		return "C";
	case TRANSCODER_EDP:
		return "EDP";
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	case TRANSCODER_DSI_A:
		return "DSI A";
	case TRANSCODER_DSI_C:
		return "DSI C";
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	default:
		return "<invalid>";
	}
}
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static inline bool transcoder_is_dsi(enum transcoder transcoder)
{
	return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
}

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/*
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 * Global legacy plane identifier. Valid only for primary/sprite
 * planes on pre-g4x, and only for primary planes on g4x+.
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 */
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enum plane {
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	PLANE_A,
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	PLANE_B,
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	PLANE_C,
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};
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#define plane_name(p) ((p) + 'A')
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#define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
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/*
 * Per-pipe plane identifier.
 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
 * number of planes per CRTC.  Not all platforms really have this many planes,
 * which means some arrays of size I915_MAX_PLANES may have unused entries
 * between the topmost sprite plane and the cursor plane.
 *
 * This is expected to be passed to various register macros
 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
 */
enum plane_id {
	PLANE_PRIMARY,
	PLANE_SPRITE0,
	PLANE_SPRITE1,
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	PLANE_SPRITE2,
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	PLANE_CURSOR,
	I915_MAX_PLANES,
};

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#define for_each_plane_id_on_crtc(__crtc, __p) \
	for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
		for_each_if ((__crtc)->plane_ids_mask & BIT(__p))

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enum port {
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	PORT_NONE = -1,
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	PORT_A = 0,
	PORT_B,
	PORT_C,
	PORT_D,
	PORT_E,
	I915_MAX_PORTS
};
#define port_name(p) ((p) + 'A')

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#define I915_NUM_PHYS_VLV 2
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enum dpio_channel {
	DPIO_CH0,
	DPIO_CH1
};

enum dpio_phy {
	DPIO_PHY0,
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	DPIO_PHY1,
	DPIO_PHY2,
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};

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enum intel_display_power_domain {
	POWER_DOMAIN_PIPE_A,
	POWER_DOMAIN_PIPE_B,
	POWER_DOMAIN_PIPE_C,
	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
	POWER_DOMAIN_TRANSCODER_A,
	POWER_DOMAIN_TRANSCODER_B,
	POWER_DOMAIN_TRANSCODER_C,
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	POWER_DOMAIN_TRANSCODER_EDP,
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	POWER_DOMAIN_TRANSCODER_DSI_A,
	POWER_DOMAIN_TRANSCODER_DSI_C,
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	POWER_DOMAIN_PORT_DDI_A_LANES,
	POWER_DOMAIN_PORT_DDI_B_LANES,
	POWER_DOMAIN_PORT_DDI_C_LANES,
	POWER_DOMAIN_PORT_DDI_D_LANES,
	POWER_DOMAIN_PORT_DDI_E_LANES,
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	POWER_DOMAIN_PORT_DDI_A_IO,
	POWER_DOMAIN_PORT_DDI_B_IO,
	POWER_DOMAIN_PORT_DDI_C_IO,
	POWER_DOMAIN_PORT_DDI_D_IO,
	POWER_DOMAIN_PORT_DDI_E_IO,
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	POWER_DOMAIN_PORT_DSI,
	POWER_DOMAIN_PORT_CRT,
	POWER_DOMAIN_PORT_OTHER,
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	POWER_DOMAIN_VGA,
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	POWER_DOMAIN_AUDIO,
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	POWER_DOMAIN_PLLS,
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	POWER_DOMAIN_AUX_A,
	POWER_DOMAIN_AUX_B,
	POWER_DOMAIN_AUX_C,
	POWER_DOMAIN_AUX_D,
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	POWER_DOMAIN_GMBUS,
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	POWER_DOMAIN_MODESET,
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	POWER_DOMAIN_INIT,
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	POWER_DOMAIN_NUM,
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};

#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
		((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
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#define POWER_DOMAIN_TRANSCODER(tran) \
	((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
	 (tran) + POWER_DOMAIN_TRANSCODER_A)
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enum hpd_pin {
	HPD_NONE = 0,
	HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
	HPD_CRT,
	HPD_SDVO_B,
	HPD_SDVO_C,
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	HPD_PORT_A,
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	HPD_PORT_B,
	HPD_PORT_C,
	HPD_PORT_D,
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	HPD_PORT_E,
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	HPD_NUM_PINS
};

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#define for_each_hpd_pin(__pin) \
	for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)

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#define HPD_STORM_DEFAULT_THRESHOLD 5

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struct i915_hotplug {
	struct work_struct hotplug_work;

	struct {
		unsigned long last_jiffies;
		int count;
		enum {
			HPD_ENABLED = 0,
			HPD_DISABLED = 1,
			HPD_MARK_DISABLED = 2
		} state;
	} stats[HPD_NUM_PINS];
	u32 event_bits;
	struct delayed_work reenable_work;

	struct intel_digital_port *irq_port[I915_MAX_PORTS];
	u32 long_port_mask;
	u32 short_port_mask;
	struct work_struct dig_port_work;

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	struct work_struct poll_init_work;
	bool poll_enabled;

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	unsigned int hpd_storm_threshold;

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	/*
	 * if we get a HPD irq from DP and a HPD irq from non-DP
	 * the non-DP HPD could block the workqueue on a mode config
	 * mutex getting, that userspace may have taken. However
	 * userspace is waiting on the DP workqueue to run which is
	 * blocked behind the non-DP one.
	 */
	struct workqueue_struct *dp_wq;
};

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#define I915_GEM_GPU_DOMAINS \
	(I915_GEM_DOMAIN_RENDER | \
	 I915_GEM_DOMAIN_SAMPLER | \
	 I915_GEM_DOMAIN_COMMAND | \
	 I915_GEM_DOMAIN_INSTRUCTION | \
	 I915_GEM_DOMAIN_VERTEX)
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#define for_each_pipe(__dev_priv, __p) \
	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
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#define for_each_pipe_masked(__dev_priv, __p, __mask) \
	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
		for_each_if ((__mask) & (1 << (__p)))
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#define for_each_universal_plane(__dev_priv, __pipe, __p)		\
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	for ((__p) = 0;							\
	     (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1;	\
	     (__p)++)
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#define for_each_sprite(__dev_priv, __p, __s)				\
	for ((__s) = 0;							\
	     (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)];	\
	     (__s)++)
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#define for_each_port_masked(__port, __ports_mask) \
	for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)	\
		for_each_if ((__ports_mask) & (1 << (__port)))

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#define for_each_crtc(dev, crtc) \
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	list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
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#define for_each_intel_plane(dev, intel_plane) \
	list_for_each_entry(intel_plane,			\
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			    &(dev)->mode_config.plane_list,	\
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			    base.head)

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#define for_each_intel_plane_mask(dev, intel_plane, plane_mask)		\
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	list_for_each_entry(intel_plane,				\
			    &(dev)->mode_config.plane_list,		\
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			    base.head)					\
		for_each_if ((plane_mask) &				\
			     (1 << drm_plane_index(&intel_plane->base)))

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#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)	\
	list_for_each_entry(intel_plane,				\
			    &(dev)->mode_config.plane_list,		\
			    base.head)					\
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		for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
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#define for_each_intel_crtc(dev, intel_crtc)				\
	list_for_each_entry(intel_crtc,					\
			    &(dev)->mode_config.crtc_list,		\
			    base.head)
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#define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask)		\
	list_for_each_entry(intel_crtc,					\
			    &(dev)->mode_config.crtc_list,		\
			    base.head)					\
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		for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))

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#define for_each_intel_encoder(dev, intel_encoder)		\
	list_for_each_entry(intel_encoder,			\
			    &(dev)->mode_config.encoder_list,	\
			    base.head)

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#define for_each_intel_connector_iter(intel_connector, iter) \
	while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))

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#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
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		for_each_if ((intel_encoder)->base.crtc == (__crtc))
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#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
	list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
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		for_each_if ((intel_connector)->base.encoder == (__encoder))
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#define for_each_power_domain(domain, mask)				\
	for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)	\
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		for_each_if (BIT_ULL(domain) & (mask))
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#define for_each_power_well(__dev_priv, __power_well)				\
	for ((__power_well) = (__dev_priv)->power_domains.power_wells;	\
	     (__power_well) - (__dev_priv)->power_domains.power_wells <	\
		(__dev_priv)->power_domains.power_well_count;		\
	     (__power_well)++)

#define for_each_power_well_rev(__dev_priv, __power_well)			\
	for ((__power_well) = (__dev_priv)->power_domains.power_wells +		\
			      (__dev_priv)->power_domains.power_well_count - 1;	\
	     (__power_well) - (__dev_priv)->power_domains.power_wells >= 0;	\
	     (__power_well)--)

#define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask)	\
	for_each_power_well(__dev_priv, __power_well)				\
		for_each_if ((__power_well)->domains & (__domain_mask))

#define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \
	for_each_power_well_rev(__dev_priv, __power_well)		        \
		for_each_if ((__power_well)->domains & (__domain_mask))

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#define for_each_intel_plane_in_state(__state, plane, plane_state, __i) \
	for ((__i) = 0; \
	     (__i) < (__state)->base.dev->mode_config.num_total_plane && \
		     ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
		      (plane_state) = to_intel_plane_state((__state)->base.planes[__i].state), 1); \
	     (__i)++) \
		for_each_if (plane_state)

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struct drm_i915_private;
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struct i915_mm_struct;
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struct i915_mmu_object;
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struct drm_i915_file_private {
	struct drm_i915_private *dev_priv;
	struct drm_file *file;

	struct {
		spinlock_t lock;
		struct list_head request_list;
577 578 579 580 581 582
/* 20ms is a fairly arbitrary limit (greater than the average frame time)
 * chosen to prevent the CPU getting more than a frame ahead of the GPU
 * (when using lax throttling for the frontbuffer). We also use it to
 * offer free GPU waitboosts for severely congested workloads.
 */
#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
583 584 585
	} mm;
	struct idr context_idr;

586 587 588 589
	struct intel_rps_client {
		struct list_head link;
		unsigned boosts;
	} rps;
590

591
	unsigned int bsd_engine;
592 593 594 595 596 597 598 599 600

/* Client can have a maximum of 3 contexts banned before
 * it is denied of creating new contexts. As one context
 * ban needs 4 consecutive hangs, and more if there is
 * progress in between, this is a last resort stop gap measure
 * to limit the badly behaving clients access to gpu.
 */
#define I915_MAX_CLIENT_CONTEXT_BANS 3
	int context_bans;
601 602
};

603 604 605 606 607 608 609 610 611 612 613 614 615
/* Used by dp and fdi links */
struct intel_link_m_n {
	uint32_t	tu;
	uint32_t	gmch_m;
	uint32_t	gmch_n;
	uint32_t	link_m;
	uint32_t	link_n;
};

void intel_link_compute_m_n(int bpp, int nlanes,
			    int pixel_clock, int link_clock,
			    struct intel_link_m_n *m_n);

L
Linus Torvalds 已提交
616 617 618
/* Interface history:
 *
 * 1.1: Original.
D
Dave Airlie 已提交
619 620
 * 1.2: Add Power Management
 * 1.3: Add vblank support
621
 * 1.4: Fix cmdbuffer path, add heap destroy
622
 * 1.5: Add vblank pipe configuration
=
=?utf-8?q?Michel_D=C3=A4nzer?= 已提交
623 624
 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 *      - Support vertical blank on secondary display pipe
L
Linus Torvalds 已提交
625 626
 */
#define DRIVER_MAJOR		1
=
=?utf-8?q?Michel_D=C3=A4nzer?= 已提交
627
#define DRIVER_MINOR		6
L
Linus Torvalds 已提交
628 629
#define DRIVER_PATCHLEVEL	0

630 631 632 633 634
struct opregion_header;
struct opregion_acpi;
struct opregion_swsci;
struct opregion_asle;

635
struct intel_opregion {
636 637 638
	struct opregion_header *header;
	struct opregion_acpi *acpi;
	struct opregion_swsci *swsci;
J
Jani Nikula 已提交
639 640
	u32 swsci_gbda_sub_functions;
	u32 swsci_sbcb_sub_functions;
641
	struct opregion_asle *asle;
642
	void *rvda;
643
	const void *vbt;
644
	u32 vbt_size;
645
	u32 *lid_state;
646
	struct work_struct asle_work;
647
};
648
#define OPREGION_SIZE            (8*1024)
649

650 651 652
struct intel_overlay;
struct intel_overlay_error_state;

653
struct sdvo_device_mapping {
C
Chris Wilson 已提交
654
	u8 initialized;
655 656 657
	u8 dvo_port;
	u8 slave_addr;
	u8 dvo_wiring;
C
Chris Wilson 已提交
658
	u8 i2c_pin;
659
	u8 ddc_pin;
660 661
};

662
struct intel_connector;
663
struct intel_encoder;
664
struct intel_atomic_state;
665
struct intel_crtc_state;
666
struct intel_initial_plane_config;
667
struct intel_crtc;
668 669
struct intel_limit;
struct dpll;
670
struct intel_cdclk_state;
671

672
struct drm_i915_display_funcs {
673 674
	void (*get_cdclk)(struct drm_i915_private *dev_priv,
			  struct intel_cdclk_state *cdclk_state);
675 676
	void (*set_cdclk)(struct drm_i915_private *dev_priv,
			  const struct intel_cdclk_state *cdclk_state);
677
	int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane);
678
	int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
679 680 681
	int (*compute_intermediate_wm)(struct drm_device *dev,
				       struct intel_crtc *intel_crtc,
				       struct intel_crtc_state *newstate);
682 683 684 685 686 687
	void (*initial_watermarks)(struct intel_atomic_state *state,
				   struct intel_crtc_state *cstate);
	void (*atomic_update_watermarks)(struct intel_atomic_state *state,
					 struct intel_crtc_state *cstate);
	void (*optimize_watermarks)(struct intel_atomic_state *state,
				    struct intel_crtc_state *cstate);
688
	int (*compute_global_watermarks)(struct drm_atomic_state *state);
689
	void (*update_wm)(struct intel_crtc *crtc);
690
	int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
691 692 693
	/* Returns the active state of the crtc, and if the crtc is active,
	 * fills out the pipe-config with the hw state. */
	bool (*get_pipe_config)(struct intel_crtc *,
694
				struct intel_crtc_state *);
695 696
	void (*get_initial_plane_config)(struct intel_crtc *,
					 struct intel_initial_plane_config *);
697 698
	int (*crtc_compute_clock)(struct intel_crtc *crtc,
				  struct intel_crtc_state *crtc_state);
699 700 701 702
	void (*crtc_enable)(struct intel_crtc_state *pipe_config,
			    struct drm_atomic_state *old_state);
	void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
			     struct drm_atomic_state *old_state);
703 704
	void (*update_crtcs)(struct drm_atomic_state *state,
			     unsigned int *crtc_vblank_mask);
705 706
	void (*audio_codec_enable)(struct drm_connector *connector,
				   struct intel_encoder *encoder,
707
				   const struct drm_display_mode *adjusted_mode);
708
	void (*audio_codec_disable)(struct intel_encoder *encoder);
709 710
	void (*fdi_link_train)(struct intel_crtc *crtc,
			       const struct intel_crtc_state *crtc_state);
711
	void (*init_clock_gating)(struct drm_i915_private *dev_priv);
712 713 714 715 716
	int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
			  struct drm_framebuffer *fb,
			  struct drm_i915_gem_object *obj,
			  struct drm_i915_gem_request *req,
			  uint32_t flags);
717
	void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
718 719 720 721 722
	/* clock updates for mode set */
	/* cursor updates */
	/* render clock increase/decrease */
	/* display clock increase/decrease */
	/* pll clock increase/decrease */
723

724 725
	void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
	void (*load_luts)(struct drm_crtc_state *crtc_state);
726 727
};

728 729 730 731
#define CSR_VERSION(major, minor)	((major) << 16 | (minor))
#define CSR_VERSION_MAJOR(version)	((version) >> 16)
#define CSR_VERSION_MINOR(version)	((version) & 0xffff)

732
struct intel_csr {
733
	struct work_struct work;
734
	const char *fw_path;
735
	uint32_t *dmc_payload;
736
	uint32_t dmc_fw_size;
737
	uint32_t version;
738
	uint32_t mmio_count;
739
	i915_reg_t mmioaddr[8];
740
	uint32_t mmiodata[8];
741
	uint32_t dc_state;
742
	uint32_t allowed_dc_mask;
743 744
};

745 746
#define DEV_INFO_FOR_EACH_FLAG(func) \
	func(is_mobile); \
747
	func(is_lp); \
748
	func(is_alpha_support); \
749
	/* Keep has_* in alphabetical order */ \
750
	func(has_64bit_reloc); \
751
	func(has_aliasing_ppgtt); \
752
	func(has_csr); \
753
	func(has_ddi); \
754
	func(has_dp_mst); \
755 756
	func(has_fbc); \
	func(has_fpga_dbg); \
757 758
	func(has_full_ppgtt); \
	func(has_full_48bit_ppgtt); \
759 760 761
	func(has_gmbus_irq); \
	func(has_gmch_display); \
	func(has_guc); \
762
	func(has_guc_ct); \
763
	func(has_hotplug); \
764
	func(has_l3_dpf); \
765
	func(has_llc); \
766 767 768 769 770 771 772 773 774
	func(has_logical_ring_contexts); \
	func(has_overlay); \
	func(has_pipe_cxsr); \
	func(has_pooled_eu); \
	func(has_psr); \
	func(has_rc6); \
	func(has_rc6p); \
	func(has_resource_streamer); \
	func(has_runtime_pm); \
775
	func(has_snoop); \
776
	func(unfenced_needs_alignment); \
777 778 779
	func(cursor_needs_physical); \
	func(hws_needs_physical); \
	func(overlay_needs_physical); \
780
	func(supports_tv);
D
Daniel Vetter 已提交
781

782
struct sseu_dev_info {
783
	u8 slice_mask;
784
	u8 subslice_mask;
785 786
	u8 eu_total;
	u8 eu_per_subslice;
787 788 789 790 791 792
	u8 min_eu_in_pool;
	/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
	u8 subslice_7eu[3];
	u8 has_slice_pg:1;
	u8 has_subslice_pg:1;
	u8 has_eu_pg:1;
793 794
};

795 796 797 798 799
static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
{
	return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
}

800 801 802 803 804 805 806 807 808 809 810 811 812
/* Keep in gen based order, and chronological order within a gen */
enum intel_platform {
	INTEL_PLATFORM_UNINITIALIZED = 0,
	INTEL_I830,
	INTEL_I845G,
	INTEL_I85X,
	INTEL_I865G,
	INTEL_I915G,
	INTEL_I915GM,
	INTEL_I945G,
	INTEL_I945GM,
	INTEL_G33,
	INTEL_PINEVIEW,
813 814
	INTEL_I965G,
	INTEL_I965GM,
815 816
	INTEL_G45,
	INTEL_GM45,
817 818 819 820 821 822 823 824 825 826 827
	INTEL_IRONLAKE,
	INTEL_SANDYBRIDGE,
	INTEL_IVYBRIDGE,
	INTEL_VALLEYVIEW,
	INTEL_HASWELL,
	INTEL_BROADWELL,
	INTEL_CHERRYVIEW,
	INTEL_SKYLAKE,
	INTEL_BROXTON,
	INTEL_KABYLAKE,
	INTEL_GEMINILAKE,
828
	INTEL_COFFEELAKE,
829
	INTEL_CANNONLAKE,
830
	INTEL_MAX_PLATFORMS
831 832
};

833
struct intel_device_info {
834
	u32 display_mmio_offset;
835
	u16 device_id;
836
	u8 num_pipes;
837
	u8 num_sprites[I915_MAX_PIPES];
838
	u8 num_scalers[I915_MAX_PIPES];
839
	u8 gen;
840
	u16 gen_mask;
841
	enum intel_platform platform;
842
	u8 ring_mask; /* Rings supported by the HW */
843
	u8 num_rings;
844 845 846
#define DEFINE_FLAG(name) u8 name:1
	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
#undef DEFINE_FLAG
847
	u16 ddb_size; /* in blocks */
848 849 850 851
	/* Register offsets for the various display pipes and transcoders */
	int pipe_offsets[I915_MAX_TRANSCODERS];
	int trans_offsets[I915_MAX_TRANSCODERS];
	int palette_offsets[I915_MAX_PIPES];
852
	int cursor_offsets[I915_MAX_PIPES];
853 854

	/* Slice/subslice/EU info */
855
	struct sseu_dev_info sseu;
856 857 858 859 860

	struct color_luts {
		u16 degamma_lut_size;
		u16 gamma_lut_size;
	} color;
861 862
};

863 864
struct intel_display_error_state;

865
struct i915_gpu_state {
866 867
	struct kref ref;
	struct timeval time;
868 869
	struct timeval boottime;
	struct timeval uptime;
870

871 872
	struct drm_i915_private *i915;

873 874
	char error_msg[128];
	bool simulated;
875
	bool awake;
876 877
	bool wakelock;
	bool suspended;
878 879 880 881
	int iommu;
	u32 reset_count;
	u32 suspend_count;
	struct intel_device_info device_info;
882
	struct i915_params params;
883 884 885 886 887

	/* Generic register state */
	u32 eir;
	u32 pgtbl_er;
	u32 ier;
888
	u32 gtier[4], ngtier;
889 890 891 892 893 894 895 896 897 898 899 900
	u32 ccid;
	u32 derrmr;
	u32 forcewake;
	u32 error; /* gen6+ */
	u32 err_int; /* gen7 */
	u32 fault_data0; /* gen8, gen9 */
	u32 fault_data1; /* gen8, gen9 */
	u32 done_reg;
	u32 gac_eco;
	u32 gam_ecochk;
	u32 gab_ctl;
	u32 gfx_mode;
901

902
	u32 nfence;
903 904 905
	u64 fence[I915_MAX_NUM_FENCES];
	struct intel_overlay_error_state *overlay;
	struct intel_display_error_state *display;
906
	struct drm_i915_error_object *semaphore;
907
	struct drm_i915_error_object *guc_log;
908 909 910 911 912 913

	struct drm_i915_error_engine {
		int engine_id;
		/* Software tracked state */
		bool waiting;
		int num_waiters;
914 915
		unsigned long hangcheck_timestamp;
		bool hangcheck_stalled;
916 917 918 919
		enum intel_engine_hangcheck_action hangcheck_action;
		struct i915_address_space *vm;
		int num_requests;

920 921 922
		/* position of active request inside the ring */
		u32 rq_head, rq_post, rq_tail;

923 924 925 926 927 928 929 930 931 932 933
		/* our own tracking of ring head and tail */
		u32 cpu_ring_head;
		u32 cpu_ring_tail;

		u32 last_seqno;

		/* Register state */
		u32 start;
		u32 tail;
		u32 head;
		u32 ctl;
934
		u32 mode;
935 936 937 938 939 940 941 942 943 944 945 946 947
		u32 hws;
		u32 ipeir;
		u32 ipehr;
		u32 bbstate;
		u32 instpm;
		u32 instps;
		u32 seqno;
		u64 bbaddr;
		u64 acthd;
		u32 fault_reg;
		u64 faddr;
		u32 rc_psmi; /* sleep state */
		u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
948
		struct intel_instdone instdone;
949

950 951 952 953 954 955 956 957 958 959
		struct drm_i915_error_context {
			char comm[TASK_COMM_LEN];
			pid_t pid;
			u32 handle;
			u32 hw_id;
			int ban_score;
			int active;
			int guilty;
		} context;

960 961
		struct drm_i915_error_object {
			u64 gtt_offset;
962
			u64 gtt_size;
963 964
			int page_count;
			int unused;
965 966 967
			u32 *pages[0];
		} *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;

968 969 970
		struct drm_i915_error_object **user_bo;
		long user_bo_count;

971 972 973 974
		struct drm_i915_error_object *wa_ctx;

		struct drm_i915_error_request {
			long jiffies;
975
			pid_t pid;
976
			u32 context;
977
			int ban_score;
978 979 980
			u32 seqno;
			u32 head;
			u32 tail;
981
		} *requests, execlist[2];
982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016

		struct drm_i915_error_waiter {
			char comm[TASK_COMM_LEN];
			pid_t pid;
			u32 seqno;
		} *waiters;

		struct {
			u32 gfx_mode;
			union {
				u64 pdp[4];
				u32 pp_dir_base;
			};
		} vm_info;
	} engine[I915_NUM_ENGINES];

	struct drm_i915_error_buffer {
		u32 size;
		u32 name;
		u32 rseqno[I915_NUM_ENGINES], wseqno;
		u64 gtt_offset;
		u32 read_domains;
		u32 write_domain;
		s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
		u32 tiling:2;
		u32 dirty:1;
		u32 purgeable:1;
		u32 userptr:1;
		s32 engine:4;
		u32 cache_level:3;
	} *active_bo[I915_NUM_ENGINES], *pinned_bo;
	u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
	struct i915_address_space *active_vm[I915_NUM_ENGINES];
};

1017 1018
enum i915_cache_level {
	I915_CACHE_NONE = 0,
1019 1020 1021 1022 1023
	I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
	I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
			      caches, eg sampler/render caches, and the
			      large Last-Level-Cache. LLC is coherent with
			      the CPU, but L3 is only visible to the GPU. */
1024
	I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
1025 1026
};

1027 1028
#define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */

1029 1030 1031 1032 1033
enum fb_op_origin {
	ORIGIN_GTT,
	ORIGIN_CPU,
	ORIGIN_CS,
	ORIGIN_FLIP,
1034
	ORIGIN_DIRTYFB,
1035 1036
};

1037
struct intel_fbc {
P
Paulo Zanoni 已提交
1038 1039 1040
	/* This is always the inner lock when overlapping with struct_mutex and
	 * it's the outer lock when overlapping with stolen_lock. */
	struct mutex lock;
B
Ben Widawsky 已提交
1041
	unsigned threshold;
1042 1043
	unsigned int possible_framebuffer_bits;
	unsigned int busy_bits;
1044
	unsigned int visible_pipes_mask;
1045
	struct intel_crtc *crtc;
1046

1047
	struct drm_mm_node compressed_fb;
1048 1049
	struct drm_mm_node *compressed_llb;

1050 1051
	bool false_color;

1052
	bool enabled;
1053
	bool active;
1054

1055 1056 1057
	bool underrun_detected;
	struct work_struct underrun_work;

1058
	struct intel_fbc_state_cache {
1059 1060
		struct i915_vma *vma;

1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073
		struct {
			unsigned int mode_flags;
			uint32_t hsw_bdw_pixel_rate;
		} crtc;

		struct {
			unsigned int rotation;
			int src_w;
			int src_h;
			bool visible;
		} plane;

		struct {
1074
			const struct drm_format_info *format;
1075 1076 1077 1078
			unsigned int stride;
		} fb;
	} state_cache;

1079
	struct intel_fbc_reg_params {
1080 1081
		struct i915_vma *vma;

1082 1083 1084 1085 1086 1087 1088
		struct {
			enum pipe pipe;
			enum plane plane;
			unsigned int fence_y_offset;
		} crtc;

		struct {
1089
			const struct drm_format_info *format;
1090 1091 1092 1093 1094 1095
			unsigned int stride;
		} fb;

		int cfb_size;
	} params;

1096
	struct intel_fbc_work {
1097
		bool scheduled;
1098
		u32 scheduled_vblank;
1099 1100
		struct work_struct work;
	} work;
1101

1102
	const char *no_fbc_reason;
1103 1104
};

1105
/*
1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119
 * HIGH_RR is the highest eDP panel refresh rate read from EDID
 * LOW_RR is the lowest eDP panel refresh rate found from EDID
 * parsing for same resolution.
 */
enum drrs_refresh_rate_type {
	DRRS_HIGH_RR,
	DRRS_LOW_RR,
	DRRS_MAX_RR, /* RR count */
};

enum drrs_support_type {
	DRRS_NOT_SUPPORTED = 0,
	STATIC_DRRS_SUPPORT = 1,
	SEAMLESS_DRRS_SUPPORT = 2
1120 1121
};

1122
struct intel_dp;
1123 1124 1125 1126 1127 1128 1129 1130 1131
struct i915_drrs {
	struct mutex mutex;
	struct delayed_work work;
	struct intel_dp *dp;
	unsigned busy_frontbuffer_bits;
	enum drrs_refresh_rate_type refresh_rate_type;
	enum drrs_support_type type;
};

R
Rodrigo Vivi 已提交
1132
struct i915_psr {
1133
	struct mutex lock;
R
Rodrigo Vivi 已提交
1134 1135
	bool sink_support;
	bool source_ok;
1136
	struct intel_dp *enabled;
1137 1138
	bool active;
	struct delayed_work work;
1139
	unsigned busy_frontbuffer_bits;
1140 1141
	bool psr2_support;
	bool aux_frame_sync;
1142
	bool link_standby;
1143 1144
	bool y_cord_support;
	bool colorimetry_support;
1145
	bool alpm;
1146
};
1147

1148
enum intel_pch {
1149
	PCH_NONE = 0,	/* No PCH present */
1150 1151
	PCH_IBX,	/* Ibexpeak PCH */
	PCH_CPT,	/* Cougarpoint PCH */
1152
	PCH_LPT,	/* Lynxpoint PCH */
1153
	PCH_SPT,        /* Sunrisepoint PCH */
1154
	PCH_KBP,        /* Kabypoint PCH */
1155
	PCH_CNP,        /* Cannonpoint PCH */
B
Ben Widawsky 已提交
1156
	PCH_NOP,
1157 1158
};

1159 1160 1161 1162 1163
enum intel_sbi_destination {
	SBI_ICLK,
	SBI_MPHY,
};

1164
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
1165
#define QUIRK_INVERT_BRIGHTNESS (1<<2)
1166
#define QUIRK_BACKLIGHT_PRESENT (1<<3)
1167
#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1168

1169
struct intel_fbdev;
1170
struct intel_fbc_work;
1171

1172 1173
struct intel_gmbus {
	struct i2c_adapter adapter;
1174
#define GMBUS_FORCE_BIT_RETRY (1U << 31)
1175
	u32 force_bit;
1176
	u32 reg0;
1177
	i915_reg_t gpio_reg;
1178
	struct i2c_algo_bit_data bit_algo;
1179 1180 1181
	struct drm_i915_private *dev_priv;
};

1182
struct i915_suspend_saved_registers {
1183
	u32 saveDSPARB;
J
Jesse Barnes 已提交
1184
	u32 saveFBC_CONTROL;
1185 1186
	u32 saveCACHE_MODE_0;
	u32 saveMI_ARB_STATE;
J
Jesse Barnes 已提交
1187 1188
	u32 saveSWF0[16];
	u32 saveSWF1[16];
1189
	u32 saveSWF3[3];
1190
	uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1191
	u32 savePCH_PORT_HOTPLUG;
1192
	u16 saveGCDGMBUS;
1193
};
1194

1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252
struct vlv_s0ix_state {
	/* GAM */
	u32 wr_watermark;
	u32 gfx_prio_ctrl;
	u32 arb_mode;
	u32 gfx_pend_tlb0;
	u32 gfx_pend_tlb1;
	u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
	u32 media_max_req_count;
	u32 gfx_max_req_count;
	u32 render_hwsp;
	u32 ecochk;
	u32 bsd_hwsp;
	u32 blt_hwsp;
	u32 tlb_rd_addr;

	/* MBC */
	u32 g3dctl;
	u32 gsckgctl;
	u32 mbctl;

	/* GCP */
	u32 ucgctl1;
	u32 ucgctl3;
	u32 rcgctl1;
	u32 rcgctl2;
	u32 rstctl;
	u32 misccpctl;

	/* GPM */
	u32 gfxpause;
	u32 rpdeuhwtc;
	u32 rpdeuc;
	u32 ecobus;
	u32 pwrdwnupctl;
	u32 rp_down_timeout;
	u32 rp_deucsw;
	u32 rcubmabdtmr;
	u32 rcedata;
	u32 spare2gh;

	/* Display 1 CZ domain */
	u32 gt_imr;
	u32 gt_ier;
	u32 pm_imr;
	u32 pm_ier;
	u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];

	/* GT SA CZ domain */
	u32 tilectl;
	u32 gt_fifoctl;
	u32 gtlc_wake_ctrl;
	u32 gtlc_survive;
	u32 pmwgicz;

	/* Display 2 CZ domain */
	u32 gu_ctl0;
	u32 gu_ctl1;
1253
	u32 pcbr;
1254 1255 1256
	u32 clock_gate_dis2;
};

1257
struct intel_rps_ei {
1258
	ktime_t ktime;
1259 1260
	u32 render_c0;
	u32 media_c0;
1261 1262
};

1263
struct intel_gen6_power_mgmt {
I
Imre Deak 已提交
1264 1265 1266 1267
	/*
	 * work, interrupts_enabled and pm_iir are protected by
	 * dev_priv->irq_lock
	 */
1268
	struct work_struct work;
I
Imre Deak 已提交
1269
	bool interrupts_enabled;
1270
	u32 pm_iir;
1271

1272
	/* PM interrupt bits that should never be masked */
1273
	u32 pm_intrmsk_mbz;
1274

1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289
	/* Frequencies are stored in potentially platform dependent multiples.
	 * In other words, *_freq needs to be multiplied by X to be interesting.
	 * Soft limits are those which are used for the dynamic reclocking done
	 * by the driver (raise frequencies under heavy loads, and lower for
	 * lighter loads). Hard limits are those imposed by the hardware.
	 *
	 * A distinction is made for overclocking, which is never enabled by
	 * default, and is considered to be above the hard limit if it's
	 * possible at all.
	 */
	u8 cur_freq;		/* Current frequency (cached, may not == HW) */
	u8 min_freq_softlimit;	/* Minimum frequency permitted by the driver */
	u8 max_freq_softlimit;	/* Max frequency permitted by the driver */
	u8 max_freq;		/* Maximum frequency, RP0 if not overclocking */
	u8 min_freq;		/* AKA RPn. Minimum frequency */
1290
	u8 boost_freq;		/* Frequency to request when wait boosting */
1291
	u8 idle_freq;		/* Frequency to request when we are idle */
1292 1293 1294
	u8 efficient_freq;	/* AKA RPe. Pre-determined balanced frequency */
	u8 rp1_freq;		/* "less than" RP0 power/freqency */
	u8 rp0_freq;		/* Non-overclocked max frequency. */
1295
	u16 gpll_ref_freq;	/* vlv/chv GPLL reference frequency */
1296

1297 1298 1299
	u8 up_threshold; /* Current %busy required to uplock */
	u8 down_threshold; /* Current %busy required to downclock */

1300 1301 1302
	int last_adj;
	enum { LOW_POWER, BETWEEN, HIGH_POWER } power;

1303 1304 1305 1306
	spinlock_t client_lock;
	struct list_head clients;
	bool client_boost;

1307
	bool enabled;
1308
	struct delayed_work autoenable_work;
1309
	unsigned boosts;
1310

1311
	/* manual wa residency calculations */
1312
	struct intel_rps_ei ei;
1313

1314 1315
	/*
	 * Protects RPS/RC6 register access and PCU communication.
1316 1317 1318
	 * Must be taken after struct_mutex if nested. Note that
	 * this lock may be held for long periods of time when
	 * talking to hw - so only take it when talking to hw!
1319 1320
	 */
	struct mutex hw_lock;
1321 1322
};

D
Daniel Vetter 已提交
1323 1324 1325
/* defined intel_pm.c */
extern spinlock_t mchdev_lock;

1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336
struct intel_ilk_power_mgmt {
	u8 cur_delay;
	u8 min_delay;
	u8 max_delay;
	u8 fmax;
	u8 fstart;

	u64 last_count1;
	unsigned long last_time1;
	unsigned long chipset_power;
	u64 last_count2;
1337
	u64 last_time2;
1338 1339 1340 1341 1342 1343 1344
	unsigned long gfx_power;
	u8 corr;

	int c_m;
	int r_t;
};

1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374
struct drm_i915_private;
struct i915_power_well;

struct i915_power_well_ops {
	/*
	 * Synchronize the well's hw state to match the current sw state, for
	 * example enable/disable it based on the current refcount. Called
	 * during driver init and resume time, possibly after first calling
	 * the enable/disable handlers.
	 */
	void (*sync_hw)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/*
	 * Enable the well and resources that depend on it (for example
	 * interrupts located on the well). Called after the 0->1 refcount
	 * transition.
	 */
	void (*enable)(struct drm_i915_private *dev_priv,
		       struct i915_power_well *power_well);
	/*
	 * Disable the well and resources that depend on it. Called after
	 * the 1->0 refcount transition.
	 */
	void (*disable)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/* Returns the hw enabled state. */
	bool (*is_enabled)(struct drm_i915_private *dev_priv,
			   struct i915_power_well *power_well);
};

1375 1376
/* Power well structure for haswell */
struct i915_power_well {
1377
	const char *name;
1378
	bool always_on;
1379 1380
	/* power well enable/disable usage count */
	int count;
1381 1382
	/* cached hw enabled state */
	bool hw_enabled;
1383
	u64 domains;
1384 1385
	/* unique identifier for this power well */
	unsigned long id;
1386 1387 1388 1389 1390
	/*
	 * Arbitraty data associated with this power well. Platform and power
	 * well specific.
	 */
	unsigned long data;
1391
	const struct i915_power_well_ops *ops;
1392 1393
};

1394
struct i915_power_domains {
1395 1396 1397 1398 1399
	/*
	 * Power wells needed for initialization at driver init and suspend
	 * time are on. They are kept on until after the first modeset.
	 */
	bool init_power_on;
1400
	bool initializing;
1401
	int power_well_count;
1402

1403
	struct mutex lock;
1404
	int domain_use_count[POWER_DOMAIN_NUM];
1405
	struct i915_power_well *power_wells;
1406 1407
};

1408
#define MAX_L3_SLICES 2
1409
struct intel_l3_parity {
1410
	u32 *remap_info[MAX_L3_SLICES];
1411
	struct work_struct error_work;
1412
	int which_slice;
1413 1414
};

1415 1416 1417
struct i915_gem_mm {
	/** Memory allocator for GTT stolen memory */
	struct drm_mm stolen;
1418 1419 1420 1421
	/** Protects the usage of the GTT stolen memory allocator. This is
	 * always the inner lock when overlapping with struct_mutex. */
	struct mutex stolen_lock;

1422 1423 1424 1425 1426
	/** List of all objects in gtt_space. Used to restore gtt
	 * mappings on resume */
	struct list_head bound_list;
	/**
	 * List of objects which are not bound to the GTT (thus
1427 1428
	 * are idle and not used by the GPU). These objects may or may
	 * not actually have any pages attached.
1429 1430 1431
	 */
	struct list_head unbound_list;

1432 1433 1434 1435 1436
	/** List of all objects in gtt_space, currently mmaped by userspace.
	 * All objects within this list must also be on bound_list.
	 */
	struct list_head userfault_list;

1437 1438 1439 1440 1441 1442
	/**
	 * List of objects which are pending destruction.
	 */
	struct llist_head free_list;
	struct work_struct free_work;

1443
	/** Usable portion of the GTT for GEM */
1444
	dma_addr_t stolen_base; /* limited to low memory (32-bit) */
1445 1446 1447 1448

	/** PPGTT used for aliasing the PPGTT with the GTT */
	struct i915_hw_ppgtt *aliasing_ppgtt;

1449
	struct notifier_block oom_notifier;
1450
	struct notifier_block vmap_notifier;
1451
	struct shrinker shrinker;
1452 1453 1454 1455

	/** LRU list of objects with fence regs on them. */
	struct list_head fence_list;

1456 1457 1458 1459 1460 1461 1462
	/**
	 * Workqueue to fault in userptr pages, flushed by the execbuf
	 * when required but otherwise left to userspace to try again
	 * on EAGAIN.
	 */
	struct workqueue_struct *userptr_wq;

1463 1464
	u64 unordered_timeline;

1465
	/* the indicator for dispatch video commands on two BSD rings */
1466
	atomic_t bsd_engine_dispatch_index;
1467

1468 1469 1470 1471 1472 1473
	/** Bit 6 swizzling required for X tiling */
	uint32_t bit_6_swizzle_x;
	/** Bit 6 swizzling required for Y tiling */
	uint32_t bit_6_swizzle_y;

	/* accounting, useful for userland debugging */
1474
	spinlock_t object_stat_lock;
1475
	u64 object_memory;
1476 1477 1478
	u32 object_count;
};

1479
struct drm_i915_error_state_buf {
1480
	struct drm_i915_private *i915;
1481 1482 1483 1484 1485 1486 1487 1488
	unsigned bytes;
	unsigned size;
	int err;
	u8 *buf;
	loff_t start;
	loff_t pos;
};

1489 1490 1491
#define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
#define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */

1492 1493 1494
#define I915_ENGINE_DEAD_TIMEOUT  (4 * HZ)  /* Seqno, head and subunits dead */
#define I915_SEQNO_DEAD_TIMEOUT   (12 * HZ) /* Seqno dead with active head */

1495 1496 1497 1498
struct i915_gpu_error {
	/* For hangcheck timer */
#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1499

1500
	struct delayed_work hangcheck_work;
1501 1502 1503 1504

	/* For reset and error_state handling. */
	spinlock_t lock;
	/* Protected by the above dev->gpu_error.lock. */
1505
	struct i915_gpu_state *first_error;
1506 1507 1508

	unsigned long missed_irq_rings;

1509
	/**
M
Mika Kuoppala 已提交
1510
	 * State variable controlling the reset flow and count
1511
	 *
M
Mika Kuoppala 已提交
1512
	 * This is a counter which gets incremented when reset is triggered,
1513
	 *
1514
	 * Before the reset commences, the I915_RESET_BACKOFF bit is set
1515 1516
	 * meaning that any waiters holding onto the struct_mutex should
	 * relinquish the lock immediately in order for the reset to start.
M
Mika Kuoppala 已提交
1517 1518 1519 1520 1521 1522 1523 1524 1525
	 *
	 * If reset is not completed succesfully, the I915_WEDGE bit is
	 * set meaning that hardware is terminally sour and there is no
	 * recovery. All waiters on the reset_queue will be woken when
	 * that happens.
	 *
	 * This counter is used by the wait_seqno code to notice that reset
	 * event happened and it needs to restart the entire ioctl (since most
	 * likely the seqno it waited for won't ever signal anytime soon).
1526 1527 1528 1529
	 *
	 * This is important for lock-free wait paths, where no contended lock
	 * naturally enforces the correct ordering between the bail-out of the
	 * waiter and the gpu reset work code.
1530
	 */
1531
	unsigned long reset_count;
1532

1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556
	/**
	 * flags: Control various stages of the GPU reset
	 *
	 * #I915_RESET_BACKOFF - When we start a reset, we want to stop any
	 * other users acquiring the struct_mutex. To do this we set the
	 * #I915_RESET_BACKOFF bit in the error flags when we detect a reset
	 * and then check for that bit before acquiring the struct_mutex (in
	 * i915_mutex_lock_interruptible()?). I915_RESET_BACKOFF serves a
	 * secondary role in preventing two concurrent global reset attempts.
	 *
	 * #I915_RESET_HANDOFF - To perform the actual GPU reset, we need the
	 * struct_mutex. We try to acquire the struct_mutex in the reset worker,
	 * but it may be held by some long running waiter (that we cannot
	 * interrupt without causing trouble). Once we are ready to do the GPU
	 * reset, we set the I915_RESET_HANDOFF bit and wakeup any waiters. If
	 * they already hold the struct_mutex and want to participate they can
	 * inspect the bit and do the reset directly, otherwise the worker
	 * waits for the struct_mutex.
	 *
	 * #I915_WEDGED - If reset fails and we can no longer use the GPU,
	 * we set the #I915_WEDGED bit. Prior to command submission, e.g.
	 * i915_gem_request_alloc(), this bit is checked and the sequence
	 * aborted (with -EIO reported to userspace) if set.
	 */
1557
	unsigned long flags;
1558 1559
#define I915_RESET_BACKOFF	0
#define I915_RESET_HANDOFF	1
1560
#define I915_WEDGED		(BITS_PER_LONG - 1)
1561

1562 1563 1564 1565 1566 1567
	/**
	 * Waitqueue to signal when a hang is detected. Used to for waiters
	 * to release the struct_mutex for the reset to procede.
	 */
	wait_queue_head_t wait_queue;

1568 1569 1570 1571 1572
	/**
	 * Waitqueue to signal when the reset has completed. Used by clients
	 * that wait for dev_priv->mm.wedged to settle.
	 */
	wait_queue_head_t reset_queue;
1573

1574
	/* For missed irq/seqno simulation. */
1575
	unsigned long test_irq_rings;
1576 1577
};

1578 1579 1580 1581 1582 1583
enum modeset_restore {
	MODESET_ON_LID_OPEN,
	MODESET_DONE,
	MODESET_SUSPENDED,
};

1584 1585 1586 1587 1588
#define DP_AUX_A 0x40
#define DP_AUX_B 0x10
#define DP_AUX_C 0x20
#define DP_AUX_D 0x30

X
Xiong Zhang 已提交
1589 1590 1591 1592
#define DDC_PIN_B  0x05
#define DDC_PIN_C  0x04
#define DDC_PIN_D  0x06

1593
struct ddi_vbt_port_info {
1594 1595 1596 1597 1598 1599
	/*
	 * This is an index in the HDMI/DVI DDI buffer translation table.
	 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
	 * populate this field.
	 */
#define HDMI_LEVEL_SHIFT_UNKNOWN	0xff
1600
	uint8_t hdmi_level_shift;
1601 1602 1603 1604

	uint8_t supports_dvi:1;
	uint8_t supports_hdmi:1;
	uint8_t supports_dp:1;
1605
	uint8_t supports_edp:1;
1606 1607

	uint8_t alternate_aux_channel;
X
Xiong Zhang 已提交
1608
	uint8_t alternate_ddc_pin;
1609 1610 1611

	uint8_t dp_boost_level;
	uint8_t hdmi_boost_level;
1612 1613
};

R
Rodrigo Vivi 已提交
1614 1615 1616 1617 1618
enum psr_lines_to_wait {
	PSR_0_LINES_TO_WAIT = 0,
	PSR_1_LINE_TO_WAIT,
	PSR_4_LINES_TO_WAIT,
	PSR_8_LINES_TO_WAIT
1619 1620
};

1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632
struct intel_vbt_data {
	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */

	/* Feature bits */
	unsigned int int_tv_support:1;
	unsigned int lvds_dither:1;
	unsigned int lvds_vbt:1;
	unsigned int int_crt_support:1;
	unsigned int lvds_use_ssc:1;
	unsigned int display_clock_mode:1;
	unsigned int fdi_rx_polarity_inverted:1;
1633
	unsigned int panel_type:4;
1634 1635 1636
	int lvds_ssc_freq;
	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */

1637 1638
	enum drrs_support_type drrs_type;

1639 1640 1641 1642 1643
	struct {
		int rate;
		int lanes;
		int preemphasis;
		int vswing;
1644
		bool low_vswing;
1645 1646 1647 1648 1649
		bool initialized;
		bool support;
		int bpp;
		struct edp_power_seq pps;
	} edp;
1650

R
Rodrigo Vivi 已提交
1651 1652 1653 1654 1655 1656 1657 1658 1659
	struct {
		bool full_link;
		bool require_aux_wakeup;
		int idle_frames;
		enum psr_lines_to_wait lines_to_wait;
		int tp1_wakeup_time;
		int tp2_tp3_wakeup_time;
	} psr;

1660 1661
	struct {
		u16 pwm_freq_hz;
1662
		bool present;
1663
		bool active_low_pwm;
1664
		u8 min_brightness;	/* min_brightness/255 of max */
1665
		u8 controller;		/* brightness controller number */
1666
		enum intel_backlight_type type;
1667 1668
	} backlight;

1669 1670 1671
	/* MIPI DSI */
	struct {
		u16 panel_id;
1672 1673 1674 1675 1676
		struct mipi_config *config;
		struct mipi_pps_data *pps;
		u8 seq_version;
		u32 size;
		u8 *data;
1677
		const u8 *sequence[MIPI_SEQ_MAX];
1678 1679
	} dsi;

1680 1681 1682
	int crt_ddc_pin;

	int child_dev_num;
1683
	union child_device_config *child_dev;
1684 1685

	struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1686
	struct sdvo_device_mapping sdvo_mappings[2];
1687 1688
};

1689 1690 1691 1692 1693
enum intel_ddb_partitioning {
	INTEL_DDB_PART_1_2,
	INTEL_DDB_PART_5_6, /* IVB+ */
};

1694 1695 1696 1697 1698 1699 1700 1701
struct intel_wm_level {
	bool enable;
	uint32_t pri_val;
	uint32_t spr_val;
	uint32_t cur_val;
	uint32_t fbc_val;
};

1702
struct ilk_wm_values {
1703 1704 1705 1706 1707 1708 1709 1710
	uint32_t wm_pipe[3];
	uint32_t wm_lp[3];
	uint32_t wm_lp_spr[3];
	uint32_t wm_linetime[3];
	bool enable_fbc_wm;
	enum intel_ddb_partitioning partitioning;
};

1711
struct g4x_pipe_wm {
1712
	uint16_t plane[I915_MAX_PLANES];
1713
	uint16_t fbc;
1714
};
1715

1716
struct g4x_sr_wm {
1717
	uint16_t plane;
1718
	uint16_t cursor;
1719
	uint16_t fbc;
1720 1721 1722 1723
};

struct vlv_wm_ddl_values {
	uint8_t plane[I915_MAX_PLANES];
1724
};
1725

1726
struct vlv_wm_values {
1727 1728
	struct g4x_pipe_wm pipe[3];
	struct g4x_sr_wm sr;
1729
	struct vlv_wm_ddl_values ddl[3];
1730 1731
	uint8_t level;
	bool cxsr;
1732 1733
};

1734 1735 1736 1737 1738 1739 1740 1741 1742
struct g4x_wm_values {
	struct g4x_pipe_wm pipe[2];
	struct g4x_sr_wm sr;
	struct g4x_sr_wm hpll;
	bool cxsr;
	bool hpll_en;
	bool fbc_en;
};

1743
struct skl_ddb_entry {
1744
	uint16_t start, end;	/* in number of blocks, 'end' is exclusive */
1745 1746 1747 1748
};

static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
{
1749
	return entry->end - entry->start;
1750 1751
}

1752 1753 1754 1755 1756 1757 1758 1759 1760
static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
				       const struct skl_ddb_entry *e2)
{
	if (e1->start == e2->start && e1->end == e2->end)
		return true;

	return false;
}

1761
struct skl_ddb_allocation {
1762
	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1763
	struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1764 1765
};

1766
struct skl_wm_values {
1767
	unsigned dirty_pipes;
1768
	struct skl_ddb_allocation ddb;
1769 1770 1771
};

struct skl_wm_level {
L
Lyude 已提交
1772 1773 1774
	bool plane_en;
	uint16_t plane_res_b;
	uint8_t plane_res_l;
1775 1776
};

1777
/*
1778 1779 1780 1781
 * This struct helps tracking the state needed for runtime PM, which puts the
 * device in PCI D3 state. Notice that when this happens, nothing on the
 * graphics device works, even register access, so we don't get interrupts nor
 * anything else.
1782
 *
1783 1784 1785
 * Every piece of our code that needs to actually touch the hardware needs to
 * either call intel_runtime_pm_get or call intel_display_power_get with the
 * appropriate power domain.
1786
 *
1787 1788
 * Our driver uses the autosuspend delay feature, which means we'll only really
 * suspend if we stay with zero refcount for a certain amount of time. The
1789
 * default value is currently very conservative (see intel_runtime_pm_enable), but
1790
 * it can be changed with the standard runtime PM files from sysfs.
1791 1792 1793 1794 1795
 *
 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
 * goes back to false exactly before we reenable the IRQs. We use this variable
 * to check if someone is trying to enable/disable IRQs while they're supposed
 * to be disabled. This shouldn't happen and we'll print some error messages in
1796
 * case it happens.
1797
 *
1798
 * For more, read the Documentation/power/runtime_pm.txt.
1799
 */
1800
struct i915_runtime_pm {
1801
	atomic_t wakeref_count;
1802
	bool suspended;
1803
	bool irqs_enabled;
1804 1805
};

1806 1807 1808 1809 1810
enum intel_pipe_crc_source {
	INTEL_PIPE_CRC_SOURCE_NONE,
	INTEL_PIPE_CRC_SOURCE_PLANE1,
	INTEL_PIPE_CRC_SOURCE_PLANE2,
	INTEL_PIPE_CRC_SOURCE_PF,
1811
	INTEL_PIPE_CRC_SOURCE_PIPE,
D
Daniel Vetter 已提交
1812 1813 1814 1815 1816
	/* TV/DP on pre-gen5/vlv can't use the pipe source. */
	INTEL_PIPE_CRC_SOURCE_TV,
	INTEL_PIPE_CRC_SOURCE_DP_B,
	INTEL_PIPE_CRC_SOURCE_DP_C,
	INTEL_PIPE_CRC_SOURCE_DP_D,
1817
	INTEL_PIPE_CRC_SOURCE_AUTO,
1818 1819 1820
	INTEL_PIPE_CRC_SOURCE_MAX,
};

1821
struct intel_pipe_crc_entry {
1822
	uint32_t frame;
1823 1824 1825
	uint32_t crc[5];
};

1826
#define INTEL_PIPE_CRC_ENTRIES_NR	128
1827
struct intel_pipe_crc {
1828 1829
	spinlock_t lock;
	bool opened;		/* exclusive access to the result file */
1830
	struct intel_pipe_crc_entry *entries;
1831
	enum intel_pipe_crc_source source;
1832
	int head, tail;
1833
	wait_queue_head_t wq;
T
Tomeu Vizoso 已提交
1834
	int skipped;
1835 1836
};

1837
struct i915_frontbuffer_tracking {
1838
	spinlock_t lock;
1839 1840 1841 1842 1843 1844 1845 1846 1847

	/*
	 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
	 * scheduled flips.
	 */
	unsigned busy_bits;
	unsigned flip_bits;
};

1848
struct i915_wa_reg {
1849
	i915_reg_t addr;
1850 1851 1852 1853 1854
	u32 value;
	/* bitmask representing WA bits */
	u32 mask;
};

1855 1856 1857 1858 1859 1860 1861
/*
 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
 * allowing it for RCS as we don't foresee any requirement of having
 * a whitelist for other engines. When it is really required for
 * other engines then the limit need to be increased.
 */
#define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1862 1863 1864 1865

struct i915_workarounds {
	struct i915_wa_reg reg[I915_MAX_WA_REGS];
	u32 count;
1866
	u32 hw_whitelist_count[I915_NUM_ENGINES];
1867 1868
};

1869 1870 1871 1872
struct i915_virtual_gpu {
	bool active;
};

1873 1874 1875 1876 1877 1878 1879
/* used in computing the new watermarks state */
struct intel_wm_config {
	unsigned int num_pipes_active;
	bool sprites_enabled;
	bool sprites_scaled;
};

1880 1881 1882 1883 1884
struct i915_oa_format {
	u32 format;
	int size;
};

1885 1886 1887 1888 1889
struct i915_oa_reg {
	i915_reg_t addr;
	u32 value;
};

1890 1891
struct i915_perf_stream;

1892 1893 1894
/**
 * struct i915_perf_stream_ops - the OPs to support a specific stream type
 */
1895
struct i915_perf_stream_ops {
1896 1897 1898 1899
	/**
	 * @enable: Enables the collection of HW samples, either in response to
	 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
	 * without `I915_PERF_FLAG_DISABLED`.
1900 1901 1902
	 */
	void (*enable)(struct i915_perf_stream *stream);

1903 1904 1905 1906
	/**
	 * @disable: Disables the collection of HW samples, either in response
	 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
	 * the stream.
1907 1908 1909
	 */
	void (*disable)(struct i915_perf_stream *stream);

1910 1911
	/**
	 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1912 1913 1914 1915 1916 1917
	 * once there is something ready to read() for the stream
	 */
	void (*poll_wait)(struct i915_perf_stream *stream,
			  struct file *file,
			  poll_table *wait);

1918 1919 1920
	/**
	 * @wait_unlocked: For handling a blocking read, wait until there is
	 * something to ready to read() for the stream. E.g. wait on the same
1921
	 * wait queue that would be passed to poll_wait().
1922 1923 1924
	 */
	int (*wait_unlocked)(struct i915_perf_stream *stream);

1925 1926 1927 1928 1929 1930 1931
	/**
	 * @read: Copy buffered metrics as records to userspace
	 * **buf**: the userspace, destination buffer
	 * **count**: the number of bytes to copy, requested by userspace
	 * **offset**: zero at the start of the read, updated as the read
	 * proceeds, it represents how many bytes have been copied so far and
	 * the buffer offset for copying the next record.
1932
	 *
1933 1934
	 * Copy as many buffered i915 perf samples and records for this stream
	 * to userspace as will fit in the given buffer.
1935
	 *
1936 1937
	 * Only write complete records; returning -%ENOSPC if there isn't room
	 * for a complete record.
1938
	 *
1939 1940 1941
	 * Return any error condition that results in a short read such as
	 * -%ENOSPC or -%EFAULT, even though these may be squashed before
	 * returning to userspace.
1942 1943 1944 1945 1946 1947
	 */
	int (*read)(struct i915_perf_stream *stream,
		    char __user *buf,
		    size_t count,
		    size_t *offset);

1948 1949
	/**
	 * @destroy: Cleanup any stream specific resources.
1950 1951 1952 1953 1954 1955
	 *
	 * The stream will always be disabled before this is called.
	 */
	void (*destroy)(struct i915_perf_stream *stream);
};

1956 1957 1958
/**
 * struct i915_perf_stream - state for a single open stream FD
 */
1959
struct i915_perf_stream {
1960 1961 1962
	/**
	 * @dev_priv: i915 drm device
	 */
1963 1964
	struct drm_i915_private *dev_priv;

1965 1966 1967
	/**
	 * @link: Links the stream into ``&drm_i915_private->streams``
	 */
1968 1969
	struct list_head link;

1970 1971 1972 1973 1974
	/**
	 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
	 * properties given when opening a stream, representing the contents
	 * of a single sample as read() by userspace.
	 */
1975
	u32 sample_flags;
1976 1977 1978 1979 1980 1981

	/**
	 * @sample_size: Considering the configured contents of a sample
	 * combined with the required header size, this is the total size
	 * of a single sample record.
	 */
1982
	int sample_size;
1983

1984 1985 1986 1987
	/**
	 * @ctx: %NULL if measuring system-wide across all contexts or a
	 * specific context that is being monitored.
	 */
1988
	struct i915_gem_context *ctx;
1989 1990 1991 1992 1993 1994

	/**
	 * @enabled: Whether the stream is currently enabled, considering
	 * whether the stream was opened in a disabled state and based
	 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
	 */
1995 1996
	bool enabled;

1997 1998 1999 2000
	/**
	 * @ops: The callbacks providing the implementation of this specific
	 * type of configured stream.
	 */
2001 2002 2003
	const struct i915_perf_stream_ops *ops;
};

2004 2005 2006
/**
 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
 */
2007
struct i915_oa_ops {
2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022
	/**
	 * @init_oa_buffer: Resets the head and tail pointers of the
	 * circular buffer for periodic OA reports.
	 *
	 * Called when first opening a stream for OA metrics, but also may be
	 * called in response to an OA buffer overflow or other error
	 * condition.
	 *
	 * Note it may be necessary to clear the full OA buffer here as part of
	 * maintaining the invariable that new reports must be written to
	 * zeroed memory for us to be able to reliable detect if an expected
	 * report has not yet landed in memory.  (At least on Haswell the OA
	 * buffer tail pointer is not synchronized with reports being visible
	 * to the CPU)
	 */
2023
	void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
2024 2025

	/**
2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036
	 * @select_metric_set: The auto generated code that checks whether a
	 * requested OA config is applicable to the system and if so sets up
	 * the mux, oa and flex eu register config pointers according to the
	 * current dev_priv->perf.oa.metrics_set.
	 */
	int (*select_metric_set)(struct drm_i915_private *dev_priv);

	/**
	 * @enable_metric_set: Selects and applies any MUX configuration to set
	 * up the Boolean and Custom (B/C) counters that are part of the
	 * counter reports being sampled. May apply system constraints such as
2037 2038
	 * disabling EU clock gating as required.
	 */
2039
	int (*enable_metric_set)(struct drm_i915_private *dev_priv);
2040 2041 2042 2043 2044

	/**
	 * @disable_metric_set: Remove system constraints associated with using
	 * the OA unit.
	 */
2045
	void (*disable_metric_set)(struct drm_i915_private *dev_priv);
2046 2047 2048 2049

	/**
	 * @oa_enable: Enable periodic sampling
	 */
2050
	void (*oa_enable)(struct drm_i915_private *dev_priv);
2051 2052 2053 2054

	/**
	 * @oa_disable: Disable periodic sampling
	 */
2055
	void (*oa_disable)(struct drm_i915_private *dev_priv);
2056 2057 2058 2059 2060

	/**
	 * @read: Copy data from the circular OA buffer into a given userspace
	 * buffer.
	 */
2061 2062 2063 2064
	int (*read)(struct i915_perf_stream *stream,
		    char __user *buf,
		    size_t count,
		    size_t *offset);
2065 2066

	/**
2067
	 * @oa_hw_tail_read: read the OA tail pointer register
2068
	 *
2069 2070 2071
	 * In particular this enables us to share all the fiddly code for
	 * handling the OA unit tail pointer race that affects multiple
	 * generations.
2072
	 */
2073
	u32 (*oa_hw_tail_read)(struct drm_i915_private *dev_priv);
2074 2075
};

2076 2077 2078 2079
struct intel_cdclk_state {
	unsigned int cdclk, vco, ref;
};

2080
struct drm_i915_private {
2081 2082
	struct drm_device drm;

2083
	struct kmem_cache *objects;
2084
	struct kmem_cache *vmas;
2085
	struct kmem_cache *requests;
2086
	struct kmem_cache *dependencies;
2087
	struct kmem_cache *priorities;
2088

2089
	const struct intel_device_info info;
2090 2091 2092

	void __iomem *regs;

2093
	struct intel_uncore uncore;
2094

2095 2096
	struct i915_virtual_gpu vgpu;

2097
	struct intel_gvt *gvt;
2098

2099
	struct intel_huc huc;
2100 2101
	struct intel_guc guc;

2102 2103
	struct intel_csr csr;

2104
	struct intel_gmbus gmbus[GMBUS_NUM_PINS];
2105

2106 2107 2108 2109 2110 2111 2112 2113 2114
	/** gmbus_mutex protects against concurrent usage of the single hw gmbus
	 * controller on different i2c buses. */
	struct mutex gmbus_mutex;

	/**
	 * Base address of the gmbus and gpio block.
	 */
	uint32_t gpio_mmio_base;

2115 2116 2117
	/* MMIO base address for MIPI regs */
	uint32_t mipi_mmio_base;

2118 2119
	uint32_t psr_mmio_base;

2120 2121
	uint32_t pps_mmio_base;

2122 2123
	wait_queue_head_t gmbus_wait_queue;

2124
	struct pci_dev *bridge_dev;
2125
	struct i915_gem_context *kernel_context;
2126
	struct intel_engine_cs *engine[I915_NUM_ENGINES];
2127
	struct i915_vma *semaphore;
2128

2129
	struct drm_dma_handle *status_page_dmah;
2130 2131 2132 2133 2134
	struct resource mch_res;

	/* protects the irq masks */
	spinlock_t irq_lock;

2135 2136 2137
	/* protects the mmio flip data */
	spinlock_t mmio_flip_lock;

2138 2139
	bool display_irqs_enabled;

2140 2141 2142
	/* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
	struct pm_qos_request pm_qos;

V
Ville Syrjälä 已提交
2143 2144
	/* Sideband mailbox protection */
	struct mutex sb_lock;
2145 2146

	/** Cached value of IMR to avoid reads in updating the bitfield */
2147 2148 2149 2150
	union {
		u32 irq_mask;
		u32 de_irq_mask[I915_MAX_PIPES];
	};
2151
	u32 gt_irq_mask;
2152 2153
	u32 pm_imr;
	u32 pm_ier;
2154
	u32 pm_rps_events;
2155
	u32 pm_guc_events;
2156
	u32 pipestat_irq_mask[I915_MAX_PIPES];
2157

2158
	struct i915_hotplug hotplug;
2159
	struct intel_fbc fbc;
2160
	struct i915_drrs drrs;
2161
	struct intel_opregion opregion;
2162
	struct intel_vbt_data vbt;
2163

2164 2165
	bool preserve_bios_swizzle;

2166 2167 2168
	/* overlay */
	struct intel_overlay *overlay;

2169
	/* backlight registers and fields in struct intel_panel */
2170
	struct mutex backlight_lock;
2171

2172 2173 2174
	/* LVDS info */
	bool no_aux_handshake;

V
Ville Syrjälä 已提交
2175 2176 2177
	/* protects panel power sequencer state */
	struct mutex pps_mutex;

2178 2179 2180 2181
	struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
	int num_fence_regs; /* 8 on pre-965, 16 otherwise */

	unsigned int fsb_freq, mem_freq, is_ddr3;
2182
	unsigned int skl_preferred_vco_freq;
2183
	unsigned int max_cdclk_freq;
2184

M
Mika Kahola 已提交
2185
	unsigned int max_dotclk_freq;
2186
	unsigned int rawclk_freq;
2187
	unsigned int hpll_freq;
2188
	unsigned int czclk_freq;
2189

2190
	struct {
2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204
		/*
		 * The current logical cdclk state.
		 * See intel_atomic_state.cdclk.logical
		 *
		 * For reading holding any crtc lock is sufficient,
		 * for writing must hold all of them.
		 */
		struct intel_cdclk_state logical;
		/*
		 * The current actual cdclk state.
		 * See intel_atomic_state.cdclk.actual
		 */
		struct intel_cdclk_state actual;
		/* The current hardware cdclk state */
2205 2206
		struct intel_cdclk_state hw;
	} cdclk;
2207

2208 2209 2210 2211 2212 2213 2214
	/**
	 * wq - Driver workqueue for GEM.
	 *
	 * NOTE: Work items scheduled here are not allowed to grab any modeset
	 * locks, for otherwise the flushing done in the pageflip code will
	 * result in deadlocks.
	 */
2215 2216 2217 2218 2219 2220 2221
	struct workqueue_struct *wq;

	/* Display functions */
	struct drm_i915_display_funcs display;

	/* PCH chipset type */
	enum intel_pch pch_type;
2222
	unsigned short pch_id;
2223 2224 2225

	unsigned long quirks;

2226 2227
	enum modeset_restore modeset_restore;
	struct mutex modeset_restore_lock;
2228
	struct drm_atomic_state *modeset_restore_state;
2229
	struct drm_modeset_acquire_ctx reset_ctx;
2230

2231
	struct list_head vm_list; /* Global list of all address spaces */
2232
	struct i915_ggtt ggtt; /* VM representing the global address space */
B
Ben Widawsky 已提交
2233

2234
	struct i915_gem_mm mm;
2235 2236
	DECLARE_HASHTABLE(mm_structs, 7);
	struct mutex mm_lock;
2237 2238 2239

	/* Kernel Modesetting */

2240 2241
	struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
	struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
2242 2243
	wait_queue_head_t pending_flip_queue;

2244 2245 2246 2247
#ifdef CONFIG_DEBUG_FS
	struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
#endif

2248
	/* dpll and cdclk state is protected by connection_mutex */
D
Daniel Vetter 已提交
2249 2250
	int num_shared_dpll;
	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
2251
	const struct intel_dpll_mgr *dpll_mgr;
2252

2253 2254 2255 2256 2257 2258 2259
	/*
	 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
	 * Must be global rather than per dpll, because on some platforms
	 * plls share registers.
	 */
	struct mutex dpll_lock;

2260 2261 2262
	unsigned int active_crtcs;
	unsigned int min_pixclk[I915_MAX_PIPES];

2263
	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
2264

2265
	struct i915_workarounds workarounds;
2266

2267 2268
	struct i915_frontbuffer_tracking fb_tracking;

2269 2270 2271 2272 2273
	struct intel_atomic_helper {
		struct llist_head free_list;
		struct work_struct free_work;
	} atomic_helper;

2274
	u16 orig_clock;
2275

2276
	bool mchbar_need_disable;
2277

2278 2279
	struct intel_l3_parity l3_parity;

B
Ben Widawsky 已提交
2280
	/* Cannot be determined by PCIID. You must always read a register. */
2281
	u32 edram_cap;
B
Ben Widawsky 已提交
2282

2283
	/* gen6+ rps state */
2284
	struct intel_gen6_power_mgmt rps;
2285

2286 2287
	/* ilk-only ips/rps state. Everything in here is protected by the global
	 * mchdev_lock in intel_pm.c */
2288
	struct intel_ilk_power_mgmt ips;
2289

2290
	struct i915_power_domains power_domains;
2291

R
Rodrigo Vivi 已提交
2292
	struct i915_psr psr;
2293

2294
	struct i915_gpu_error gpu_error;
2295

2296 2297
	struct drm_i915_gem_object *vlv_pctx;

2298
#ifdef CONFIG_DRM_FBDEV_EMULATION
2299 2300
	/* list of fbdev register on this device */
	struct intel_fbdev *fbdev;
2301
	struct work_struct fbdev_suspend_work;
2302
#endif
2303 2304

	struct drm_property *broadcast_rgb_property;
2305
	struct drm_property *force_audio_property;
2306

I
Imre Deak 已提交
2307
	/* hda/i915 audio component */
2308
	struct i915_audio_component *audio_component;
I
Imre Deak 已提交
2309
	bool audio_component_registered;
2310 2311 2312 2313 2314
	/**
	 * av_mutex - mutex for audio/video sync
	 *
	 */
	struct mutex av_mutex;
I
Imre Deak 已提交
2315

2316 2317 2318 2319 2320 2321 2322 2323 2324 2325
	struct {
		struct list_head list;

		/* The hw wants to have a stable context identifier for the
		 * lifetime of the context (for OA, PASID, faults, etc).
		 * This is limited in execlists to 21 bits.
		 */
		struct ida hw_ida;
#define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
	} contexts;
2326

2327
	u32 fdi_rx_config;
2328

2329
	/* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2330
	u32 chv_phy_control;
2331 2332 2333 2334 2335 2336
	/*
	 * Shadows for CHV DPLL_MD regs to keep the state
	 * checker somewhat working in the presence hardware
	 * crappiness (can't read out DPLL_MD for pipes B & C).
	 */
	u32 chv_dpll_md[I915_MAX_PIPES];
2337
	u32 bxt_phy_grc;
2338

2339
	u32 suspend_count;
2340
	bool suspended_to_idle;
2341
	struct i915_suspend_saved_registers regfile;
2342
	struct vlv_s0ix_state vlv_s0ix_state;
2343

2344
	enum {
2345 2346 2347 2348 2349
		I915_SAGV_UNKNOWN = 0,
		I915_SAGV_DISABLED,
		I915_SAGV_ENABLED,
		I915_SAGV_NOT_CONTROLLED
	} sagv_status;
2350

2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362
	struct {
		/*
		 * Raw watermark latency values:
		 * in 0.1us units for WM0,
		 * in 0.5us units for WM1+.
		 */
		/* primary */
		uint16_t pri_latency[5];
		/* sprite */
		uint16_t spr_latency[5];
		/* cursor */
		uint16_t cur_latency[5];
2363 2364 2365 2366 2367 2368
		/*
		 * Raw watermark memory latency values
		 * for SKL for all 8 levels
		 * in 1us units.
		 */
		uint16_t skl_latency[8];
2369 2370

		/* current hardware state */
2371 2372 2373
		union {
			struct ilk_wm_values hw;
			struct skl_wm_values skl_hw;
2374
			struct vlv_wm_values vlv;
2375
			struct g4x_wm_values g4x;
2376
		};
2377 2378

		uint8_t max_level;
2379 2380 2381 2382 2383 2384 2385

		/*
		 * Should be held around atomic WM register writing; also
		 * protects * intel_crtc->wm.active and
		 * cstate->wm.need_postvbl_update.
		 */
		struct mutex wm_mutex;
2386 2387 2388 2389 2390 2391 2392

		/*
		 * Set during HW readout of watermarks/DDB.  Some platforms
		 * need to know when we're still using BIOS-provided values
		 * (which we don't fully trust).
		 */
		bool distrust_bios_wm;
2393 2394
	} wm;

2395 2396
	struct i915_runtime_pm pm;

2397 2398
	struct {
		bool initialized;
2399

2400
		struct kobject *metrics_kobj;
2401
		struct ctl_table_header *sysctl_header;
2402

2403 2404
		struct mutex lock;
		struct list_head streams;
2405 2406

		struct {
2407 2408 2409 2410 2411 2412 2413 2414
			struct i915_perf_stream *exclusive_stream;

			u32 specific_ctx_id;

			struct hrtimer poll_check_timer;
			wait_queue_head_t poll_wq;
			bool pollin;

2415 2416 2417 2418 2419 2420
			/**
			 * For rate limiting any notifications of spurious
			 * invalid OA reports
			 */
			struct ratelimit_state spurious_report_rs;

2421 2422
			bool periodic;
			int period_exponent;
2423
			int timestamp_frequency;
2424 2425

			int metrics_set;
2426

2427 2428
			const struct i915_oa_reg *mux_regs[6];
			int mux_regs_lens[6];
2429 2430
			int n_mux_configs;

2431 2432
			const struct i915_oa_reg *b_counter_regs;
			int b_counter_regs_len;
2433 2434
			const struct i915_oa_reg *flex_regs;
			int flex_regs_len;
2435 2436 2437 2438

			struct {
				struct i915_vma *vma;
				u8 *vaddr;
2439
				u32 last_ctx_id;
2440 2441
				int format;
				int format_size;
2442

2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495
				/**
				 * Locks reads and writes to all head/tail state
				 *
				 * Consider: the head and tail pointer state
				 * needs to be read consistently from a hrtimer
				 * callback (atomic context) and read() fop
				 * (user context) with tail pointer updates
				 * happening in atomic context and head updates
				 * in user context and the (unlikely)
				 * possibility of read() errors needing to
				 * reset all head/tail state.
				 *
				 * Note: Contention or performance aren't
				 * currently a significant concern here
				 * considering the relatively low frequency of
				 * hrtimer callbacks (5ms period) and that
				 * reads typically only happen in response to a
				 * hrtimer event and likely complete before the
				 * next callback.
				 *
				 * Note: This lock is not held *while* reading
				 * and copying data to userspace so the value
				 * of head observed in htrimer callbacks won't
				 * represent any partial consumption of data.
				 */
				spinlock_t ptr_lock;

				/**
				 * One 'aging' tail pointer and one 'aged'
				 * tail pointer ready to used for reading.
				 *
				 * Initial values of 0xffffffff are invalid
				 * and imply that an update is required
				 * (and should be ignored by an attempted
				 * read)
				 */
				struct {
					u32 offset;
				} tails[2];

				/**
				 * Index for the aged tail ready to read()
				 * data up to.
				 */
				unsigned int aged_tail_idx;

				/**
				 * A monotonic timestamp for when the current
				 * aging tail pointer was read; used to
				 * determine when it is old enough to trust.
				 */
				u64 aging_timestamp;

2496 2497 2498 2499 2500 2501 2502 2503 2504 2505
				/**
				 * Although we can always read back the head
				 * pointer register, we prefer to avoid
				 * trusting the HW state, just to avoid any
				 * risk that some hardware condition could
				 * somehow bump the head pointer unpredictably
				 * and cause us to forward the wrong OA buffer
				 * data to userspace.
				 */
				u32 head;
2506 2507 2508
			} oa_buffer;

			u32 gen7_latched_oastatus1;
2509 2510 2511 2512 2513 2514 2515 2516 2517
			u32 ctx_oactxctrl_offset;
			u32 ctx_flexeu0_offset;

			/**
			 * The RPT_ID/reason field for Gen8+ includes a bit
			 * to determine if the CTX ID in the report is valid
			 * but the specific bit differs between Gen 8 and 9
			 */
			u32 gen8_valid_ctx_bit;
2518 2519 2520 2521

			struct i915_oa_ops ops;
			const struct i915_oa_format *oa_formats;
			int n_builtin_sets;
2522
		} oa;
2523 2524
	} perf;

2525 2526
	/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
	struct {
2527
		void (*resume)(struct drm_i915_private *);
2528
		void (*cleanup_engine)(struct intel_engine_cs *engine);
2529

2530 2531
		struct list_head timelines;
		struct i915_gem_timeline global_timeline;
2532
		u32 active_requests;
2533

2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559
		/**
		 * Is the GPU currently considered idle, or busy executing
		 * userspace requests? Whilst idle, we allow runtime power
		 * management to power down the hardware and display clocks.
		 * In order to reduce the effect on performance, there
		 * is a slight delay before we do so.
		 */
		bool awake;

		/**
		 * We leave the user IRQ off as much as possible,
		 * but this means that requests will finish and never
		 * be retired once the system goes idle. Set a timer to
		 * fire periodically while the ring is running. When it
		 * fires, go retire requests.
		 */
		struct delayed_work retire_work;

		/**
		 * When we detect an idle GPU, we want to turn on
		 * powersaving features. So once we see that there
		 * are no more requests outstanding and no more
		 * arrive within a small period of time, we fire
		 * off the idle_work.
		 */
		struct delayed_work idle_work;
2560 2561

		ktime_t last_init_time;
2562 2563
	} gt;

2564 2565 2566
	/* perform PHY state sanity checks? */
	bool chv_phy_assert[2];

M
Mahesh Kumar 已提交
2567 2568
	bool ipc_enabled;

2569 2570
	/* Used to save the pipe-to-encoder mapping for audio */
	struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2571

2572 2573 2574 2575 2576 2577
	/* necessary resource sharing with HDMI LPE audio driver. */
	struct {
		struct platform_device *platdev;
		int	irq;
	} lpe_audio;

2578 2579 2580 2581
	/*
	 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
	 * will be rejected. Instead look for a better place.
	 */
2582
};
L
Linus Torvalds 已提交
2583

2584 2585
static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
{
2586
	return container_of(dev, struct drm_i915_private, drm);
2587 2588
}

2589
static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
I
Imre Deak 已提交
2590
{
2591
	return to_i915(dev_get_drvdata(kdev));
I
Imre Deak 已提交
2592 2593
}

2594 2595 2596 2597 2598
static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
{
	return container_of(guc, struct drm_i915_private, guc);
}

A
Arkadiusz Hiler 已提交
2599 2600 2601 2602 2603
static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
{
	return container_of(huc, struct drm_i915_private, huc);
}

2604
/* Simple iterator over all initialised engines */
2605 2606 2607 2608 2609
#define for_each_engine(engine__, dev_priv__, id__) \
	for ((id__) = 0; \
	     (id__) < I915_NUM_ENGINES; \
	     (id__)++) \
		for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2610 2611

/* Iterator over subset of engines selected by mask */
2612 2613
#define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
	for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask;	\
2614
	     tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2615

2616 2617 2618 2619 2620 2621 2622
enum hdmi_force_audio {
	HDMI_AUDIO_OFF_DVI = -2,	/* no aux data for HDMI-DVI converter */
	HDMI_AUDIO_OFF,			/* force turn off HDMI audio */
	HDMI_AUDIO_AUTO,		/* trust EDID */
	HDMI_AUDIO_ON,			/* force turn on HDMI audio */
};

2623
#define I915_GTT_OFFSET_NONE ((u32)-1)
2624

2625 2626
/*
 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2627
 * considered to be the frontbuffer for the given plane interface-wise. This
2628 2629 2630 2631 2632
 * doesn't mean that the hw necessarily already scans it out, but that any
 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
 *
 * We have one bit per pipe and per scanout plane type.
 */
2633 2634
#define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2635 2636 2637
#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
	(1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
#define INTEL_FRONTBUFFER_CURSOR(pipe) \
2638 2639 2640
	(1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
#define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
	(1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2641
#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2642
	(1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2643
#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2644
	(0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2645

2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671
/*
 * Optimised SGL iterator for GEM objects
 */
static __always_inline struct sgt_iter {
	struct scatterlist *sgp;
	union {
		unsigned long pfn;
		dma_addr_t dma;
	};
	unsigned int curr;
	unsigned int max;
} __sgt_iter(struct scatterlist *sgl, bool dma) {
	struct sgt_iter s = { .sgp = sgl };

	if (s.sgp) {
		s.max = s.curr = s.sgp->offset;
		s.max += s.sgp->length;
		if (dma)
			s.dma = sg_dma_address(s.sgp);
		else
			s.pfn = page_to_pfn(sg_page(s.sgp));
	}

	return s;
}

2672 2673 2674 2675 2676 2677 2678 2679
static inline struct scatterlist *____sg_next(struct scatterlist *sg)
{
	++sg;
	if (unlikely(sg_is_chain(sg)))
		sg = sg_chain_ptr(sg);
	return sg;
}

2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693
/**
 * __sg_next - return the next scatterlist entry in a list
 * @sg:		The current sg entry
 *
 * Description:
 *   If the entry is the last, return NULL; otherwise, step to the next
 *   element in the array (@sg@+1). If that's a chain pointer, follow it;
 *   otherwise just return the pointer to the current element.
 **/
static inline struct scatterlist *__sg_next(struct scatterlist *sg)
{
#ifdef CONFIG_DEBUG_SG
	BUG_ON(sg->sg_magic != SG_MAGIC);
#endif
2694
	return sg_is_last(sg) ? NULL : ____sg_next(sg);
2695 2696
}

2697 2698 2699 2700 2701 2702 2703 2704 2705 2706
/**
 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
 * @__dmap:	DMA address (output)
 * @__iter:	'struct sgt_iter' (iterator state, internal)
 * @__sgt:	sg_table to iterate over (input)
 */
#define for_each_sgt_dma(__dmap, __iter, __sgt)				\
	for ((__iter) = __sgt_iter((__sgt)->sgl, true);			\
	     ((__dmap) = (__iter).dma + (__iter).curr);			\
	     (((__iter).curr += PAGE_SIZE) < (__iter).max) ||		\
2707
	     ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719

/**
 * for_each_sgt_page - iterate over the pages of the given sg_table
 * @__pp:	page pointer (output)
 * @__iter:	'struct sgt_iter' (iterator state, internal)
 * @__sgt:	sg_table to iterate over (input)
 */
#define for_each_sgt_page(__pp, __iter, __sgt)				\
	for ((__iter) = __sgt_iter((__sgt)->sgl, false);		\
	     ((__pp) = (__iter).pfn == 0 ? NULL :			\
	      pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
	     (((__iter).curr += PAGE_SIZE) < (__iter).max) ||		\
2720
	     ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2721

2722 2723 2724 2725 2726 2727 2728
static inline const struct intel_device_info *
intel_info(const struct drm_i915_private *dev_priv)
{
	return &dev_priv->info;
}

#define INTEL_INFO(dev_priv)	intel_info((dev_priv))
2729

2730
#define INTEL_GEN(dev_priv)	((dev_priv)->info.gen)
2731
#define INTEL_DEVID(dev_priv)	((dev_priv)->info.device_id)
2732

2733
#define REVID_FOREVER		0xff
2734
#define INTEL_REVID(dev_priv)	((dev_priv)->drm.pdev->revision)
2735 2736 2737 2738 2739 2740 2741

#define GEN_FOREVER (0)
/*
 * Returns true if Gen is in inclusive range [Start, End].
 *
 * Use GEN_FOREVER for unbound start and or end.
 */
2742
#define IS_GEN(dev_priv, s, e) ({ \
2743 2744 2745 2746 2747 2748 2749 2750 2751
	unsigned int __s = (s), __e = (e); \
	BUILD_BUG_ON(!__builtin_constant_p(s)); \
	BUILD_BUG_ON(!__builtin_constant_p(e)); \
	if ((__s) != GEN_FOREVER) \
		__s = (s) - 1; \
	if ((__e) == GEN_FOREVER) \
		__e = BITS_PER_LONG - 1; \
	else \
		__e = (e) - 1; \
2752
	!!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
2753 2754
})

2755 2756 2757 2758 2759 2760 2761 2762
/*
 * Return true if revision is in range [since,until] inclusive.
 *
 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
 */
#define IS_REVID(p, since, until) \
	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))

2763 2764
#define IS_I830(dev_priv)	((dev_priv)->info.platform == INTEL_I830)
#define IS_I845G(dev_priv)	((dev_priv)->info.platform == INTEL_I845G)
2765
#define IS_I85X(dev_priv)	((dev_priv)->info.platform == INTEL_I85X)
2766
#define IS_I865G(dev_priv)	((dev_priv)->info.platform == INTEL_I865G)
2767
#define IS_I915G(dev_priv)	((dev_priv)->info.platform == INTEL_I915G)
2768 2769
#define IS_I915GM(dev_priv)	((dev_priv)->info.platform == INTEL_I915GM)
#define IS_I945G(dev_priv)	((dev_priv)->info.platform == INTEL_I945G)
2770
#define IS_I945GM(dev_priv)	((dev_priv)->info.platform == INTEL_I945GM)
2771 2772
#define IS_I965G(dev_priv)	((dev_priv)->info.platform == INTEL_I965G)
#define IS_I965GM(dev_priv)	((dev_priv)->info.platform == INTEL_I965GM)
2773 2774 2775
#define IS_G45(dev_priv)	((dev_priv)->info.platform == INTEL_G45)
#define IS_GM45(dev_priv)	((dev_priv)->info.platform == INTEL_GM45)
#define IS_G4X(dev_priv)	(IS_G45(dev_priv) || IS_GM45(dev_priv))
2776 2777
#define IS_PINEVIEW_G(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa001)
#define IS_PINEVIEW_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa011)
2778
#define IS_PINEVIEW(dev_priv)	((dev_priv)->info.platform == INTEL_PINEVIEW)
2779
#define IS_G33(dev_priv)	((dev_priv)->info.platform == INTEL_G33)
2780
#define IS_IRONLAKE_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0046)
2781
#define IS_IVYBRIDGE(dev_priv)	((dev_priv)->info.platform == INTEL_IVYBRIDGE)
2782 2783 2784
#define IS_IVB_GT1(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0156 || \
				 INTEL_DEVID(dev_priv) == 0x0152 || \
				 INTEL_DEVID(dev_priv) == 0x015a)
2785 2786 2787 2788 2789 2790 2791 2792
#define IS_VALLEYVIEW(dev_priv)	((dev_priv)->info.platform == INTEL_VALLEYVIEW)
#define IS_CHERRYVIEW(dev_priv)	((dev_priv)->info.platform == INTEL_CHERRYVIEW)
#define IS_HASWELL(dev_priv)	((dev_priv)->info.platform == INTEL_HASWELL)
#define IS_BROADWELL(dev_priv)	((dev_priv)->info.platform == INTEL_BROADWELL)
#define IS_SKYLAKE(dev_priv)	((dev_priv)->info.platform == INTEL_SKYLAKE)
#define IS_BROXTON(dev_priv)	((dev_priv)->info.platform == INTEL_BROXTON)
#define IS_KABYLAKE(dev_priv)	((dev_priv)->info.platform == INTEL_KABYLAKE)
#define IS_GEMINILAKE(dev_priv)	((dev_priv)->info.platform == INTEL_GEMINILAKE)
2793
#define IS_COFFEELAKE(dev_priv)	((dev_priv)->info.platform == INTEL_COFFEELAKE)
2794
#define IS_CANNONLAKE(dev_priv)	((dev_priv)->info.platform == INTEL_CANNONLAKE)
2795
#define IS_MOBILE(dev_priv)	((dev_priv)->info.is_mobile)
2796 2797 2798 2799 2800 2801
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv)	(IS_BROADWELL(dev_priv) && \
				 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 ||	\
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xb ||	\
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
V
Ville Syrjälä 已提交
2802
/* ULX machines are also considered ULT. */
2803 2804 2805 2806 2807 2808 2809 2810
#define IS_BDW_ULX(dev_priv)	(IS_BROADWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
#define IS_BDW_GT3(dev_priv)	(IS_BROADWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
#define IS_HSW_ULT(dev_priv)	(IS_HASWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
#define IS_HSW_GT3(dev_priv)	(IS_HASWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2811
/* ULX machines are also considered ULT. */
2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828 2829
#define IS_HSW_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0A0E || \
				 INTEL_DEVID(dev_priv) == 0x0A1E)
#define IS_SKL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x1906 || \
				 INTEL_DEVID(dev_priv) == 0x1913 || \
				 INTEL_DEVID(dev_priv) == 0x1916 || \
				 INTEL_DEVID(dev_priv) == 0x1921 || \
				 INTEL_DEVID(dev_priv) == 0x1926)
#define IS_SKL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x190E || \
				 INTEL_DEVID(dev_priv) == 0x1915 || \
				 INTEL_DEVID(dev_priv) == 0x191E)
#define IS_KBL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x5906 || \
				 INTEL_DEVID(dev_priv) == 0x5913 || \
				 INTEL_DEVID(dev_priv) == 0x5916 || \
				 INTEL_DEVID(dev_priv) == 0x5921 || \
				 INTEL_DEVID(dev_priv) == 0x5926)
#define IS_KBL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x590E || \
				 INTEL_DEVID(dev_priv) == 0x5915 || \
				 INTEL_DEVID(dev_priv) == 0x591E)
2830 2831
#define IS_SKL_GT2(dev_priv)	(IS_SKYLAKE(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0010)
2832 2833 2834 2835
#define IS_SKL_GT3(dev_priv)	(IS_SKYLAKE(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
#define IS_SKL_GT4(dev_priv)	(IS_SKYLAKE(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
2836 2837 2838 2839
#define IS_KBL_GT2(dev_priv)	(IS_KABYLAKE(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0010)
#define IS_KBL_GT3(dev_priv)	(IS_KABYLAKE(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2840 2841
#define IS_CFL_ULT(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
2842

2843
#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2844

2845 2846 2847 2848 2849 2850
#define SKL_REVID_A0		0x0
#define SKL_REVID_B0		0x1
#define SKL_REVID_C0		0x2
#define SKL_REVID_D0		0x3
#define SKL_REVID_E0		0x4
#define SKL_REVID_F0		0x5
2851 2852
#define SKL_REVID_G0		0x6
#define SKL_REVID_H0		0x7
2853

2854 2855
#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))

2856
#define BXT_REVID_A0		0x0
2857
#define BXT_REVID_A1		0x1
2858
#define BXT_REVID_B0		0x3
2859
#define BXT_REVID_B_LAST	0x8
2860
#define BXT_REVID_C0		0x9
N
Nick Hoath 已提交
2861

2862 2863
#define IS_BXT_REVID(dev_priv, since, until) \
	(IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2864

M
Mika Kuoppala 已提交
2865 2866
#define KBL_REVID_A0		0x0
#define KBL_REVID_B0		0x1
2867 2868 2869
#define KBL_REVID_C0		0x2
#define KBL_REVID_D0		0x3
#define KBL_REVID_E0		0x4
M
Mika Kuoppala 已提交
2870

2871 2872
#define IS_KBL_REVID(dev_priv, since, until) \
	(IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
M
Mika Kuoppala 已提交
2873

2874 2875 2876 2877 2878 2879
#define GLK_REVID_A0		0x0
#define GLK_REVID_A1		0x1

#define IS_GLK_REVID(dev_priv, since, until) \
	(IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))

2880 2881 2882 2883 2884 2885
#define CNL_REVID_A0		0x0
#define CNL_REVID_B0		0x1

#define IS_CNL_REVID(p, since, until) \
	(IS_CANNONLAKE(p) && IS_REVID(p, since, until))

2886 2887 2888 2889 2890 2891
/*
 * The genX designation typically refers to the render engine, so render
 * capability related checks should use IS_GEN, while display and other checks
 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
 * chips, etc.).
 */
2892 2893 2894 2895 2896 2897 2898 2899
#define IS_GEN2(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(1)))
#define IS_GEN3(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(2)))
#define IS_GEN4(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(3)))
#define IS_GEN5(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(4)))
#define IS_GEN6(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(5)))
#define IS_GEN7(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(6)))
#define IS_GEN8(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(7)))
#define IS_GEN9(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(8)))
2900
#define IS_GEN10(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(9)))
2901

2902
#define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
2903 2904
#define IS_GEN9_LP(dev_priv)	(IS_GEN9(dev_priv) && IS_LP(dev_priv))
#define IS_GEN9_BC(dev_priv)	(IS_GEN9(dev_priv) && !IS_LP(dev_priv))
2905

2906 2907 2908 2909 2910 2911 2912 2913 2914
#define ENGINE_MASK(id)	BIT(id)
#define RENDER_RING	ENGINE_MASK(RCS)
#define BSD_RING	ENGINE_MASK(VCS)
#define BLT_RING	ENGINE_MASK(BCS)
#define VEBOX_RING	ENGINE_MASK(VECS)
#define BSD2_RING	ENGINE_MASK(VCS2)
#define ALL_ENGINES	(~0)

#define HAS_ENGINE(dev_priv, id) \
2915
	(!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2916 2917 2918 2919 2920 2921

#define HAS_BSD(dev_priv)	HAS_ENGINE(dev_priv, VCS)
#define HAS_BSD2(dev_priv)	HAS_ENGINE(dev_priv, VCS2)
#define HAS_BLT(dev_priv)	HAS_ENGINE(dev_priv, BCS)
#define HAS_VEBOX(dev_priv)	HAS_ENGINE(dev_priv, VECS)

2922 2923 2924
#define HAS_LLC(dev_priv)	((dev_priv)->info.has_llc)
#define HAS_SNOOP(dev_priv)	((dev_priv)->info.has_snoop)
#define HAS_EDRAM(dev_priv)	(!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2925 2926
#define HAS_WT(dev_priv)	((IS_HASWELL(dev_priv) || \
				 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2927

2928
#define HWS_NEEDS_PHYSICAL(dev_priv)	((dev_priv)->info.hws_needs_physical)
2929

2930 2931 2932 2933 2934 2935 2936 2937 2938
#define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
		((dev_priv)->info.has_logical_ring_contexts)
#define USES_PPGTT(dev_priv)		(i915.enable_ppgtt)
#define USES_FULL_PPGTT(dev_priv)	(i915.enable_ppgtt >= 2)
#define USES_FULL_48BIT_PPGTT(dev_priv)	(i915.enable_ppgtt == 3)

#define HAS_OVERLAY(dev_priv)		 ((dev_priv)->info.has_overlay)
#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
		((dev_priv)->info.overlay_needs_physical)
2939

2940
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
2941
#define HAS_BROKEN_CS_TLB(dev_priv)	(IS_I830(dev_priv) || IS_I845G(dev_priv))
2942 2943

/* WaRsDisableCoarsePowerGating:skl,bxt */
2944
#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2945
	(IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2946

2947 2948 2949 2950 2951 2952
/*
 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
 * even when in MSI mode. This results in spurious interrupt warnings if the
 * legacy irq no. is shared with another device. The kernel then disables that
 * interrupt source and so prevents the other device from working properly.
 */
2953 2954
#define HAS_AUX_IRQ(dev_priv)   ((dev_priv)->info.gen >= 5)
#define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
2955

2956 2957 2958
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 * rows, which changed the alignment requirements and fence programming.
 */
2959 2960 2961
#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
					 !(IS_I915G(dev_priv) || \
					 IS_I915GM(dev_priv)))
2962 2963
#define SUPPORTS_TV(dev_priv)		((dev_priv)->info.supports_tv)
#define I915_HAS_HOTPLUG(dev_priv)	((dev_priv)->info.has_hotplug)
2964

2965 2966 2967
#define HAS_FW_BLC(dev_priv) 	(INTEL_GEN(dev_priv) > 2)
#define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
#define HAS_FBC(dev_priv)	((dev_priv)->info.has_fbc)
2968
#define HAS_CUR_FBC(dev_priv)	(!HAS_GMCH_DISPLAY(dev_priv) && INTEL_INFO(dev_priv)->gen >= 7)
2969

2970
#define HAS_IPS(dev_priv)	(IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2971

2972
#define HAS_DP_MST(dev_priv)	((dev_priv)->info.has_dp_mst)
2973

2974 2975 2976 2977 2978
#define HAS_DDI(dev_priv)		 ((dev_priv)->info.has_ddi)
#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
#define HAS_PSR(dev_priv)		 ((dev_priv)->info.has_psr)
#define HAS_RC6(dev_priv)		 ((dev_priv)->info.has_rc6)
#define HAS_RC6p(dev_priv)		 ((dev_priv)->info.has_rc6p)
P
Paulo Zanoni 已提交
2979

2980
#define HAS_CSR(dev_priv)	((dev_priv)->info.has_csr)
2981

2982
#define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2983 2984
#define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)

2985 2986 2987 2988 2989
/*
 * For now, anything with a GuC requires uCode loading, and then supports
 * command submission once loaded. But these are logically independent
 * properties, so we have separate macros to test them.
 */
2990
#define HAS_GUC(dev_priv)	((dev_priv)->info.has_guc)
2991
#define HAS_GUC_CT(dev_priv)	((dev_priv)->info.has_guc_ct)
2992 2993
#define HAS_GUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
#define HAS_GUC_SCHED(dev_priv)	(HAS_GUC(dev_priv))
2994
#define HAS_HUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
2995

2996
#define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2997

2998
#define HAS_POOLED_EU(dev_priv)	((dev_priv)->info.has_pooled_eu)
2999

3000
#define INTEL_PCH_DEVICE_ID_MASK		0xff00
3001
#define INTEL_PCH_DEVICE_ID_MASK_EXT		0xff80
3002 3003 3004 3005 3006
#define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
#define INTEL_PCH_PPT_DEVICE_ID_TYPE		0x1e00
#define INTEL_PCH_LPT_DEVICE_ID_TYPE		0x8c00
#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE		0x9c00
3007 3008
#define INTEL_PCH_SPT_DEVICE_ID_TYPE		0xA100
#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE		0x9D00
3009
#define INTEL_PCH_KBP_DEVICE_ID_TYPE		0xA200
3010
#define INTEL_PCH_CNP_DEVICE_ID_TYPE		0xA300
3011
#define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE		0x9D80
3012
#define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
3013
#define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
3014
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
3015

3016
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
3017
#define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
3018 3019
#define HAS_PCH_CNP_LP(dev_priv) \
	((dev_priv)->pch_id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE)
3020 3021 3022
#define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
3023 3024 3025 3026
#define HAS_PCH_LPT_LP(dev_priv) \
	((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
#define HAS_PCH_LPT_H(dev_priv) \
	((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
3027 3028 3029 3030
#define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
#define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
3031

3032
#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
3033

3034
#define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
3035

3036
/* DPF == dynamic parity feature */
3037
#define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
3038 3039
#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
				 2 : HAS_L3_DPF(dev_priv))
3040

3041
#define GT_FREQUENCY_MULTIPLIER 50
A
Akash Goel 已提交
3042
#define GEN9_FREQ_SCALER 3
3043

3044 3045
#include "i915_trace.h"

3046
static inline bool intel_vtd_active(void)
3047 3048
{
#ifdef CONFIG_INTEL_IOMMU
3049
	if (intel_iommu_gfx_mapped)
3050 3051 3052 3053 3054
		return true;
#endif
	return false;
}

3055 3056 3057 3058 3059
static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
{
	return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
}

3060 3061 3062
static inline bool
intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
{
3063
	return IS_BROXTON(dev_priv) && intel_vtd_active();
3064 3065
}

3066
int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
3067
				int enable_ppgtt);
3068

3069 3070
bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);

3071
/* i915_drv.c */
3072 3073 3074 3075 3076 3077 3078
void __printf(3, 4)
__i915_printk(struct drm_i915_private *dev_priv, const char *level,
	      const char *fmt, ...);

#define i915_report_error(dev_priv, fmt, ...)				   \
	__i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)

3079
#ifdef CONFIG_COMPAT
D
Dave Airlie 已提交
3080 3081
extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
			      unsigned long arg);
3082 3083
#else
#define i915_compat_ioctl NULL
3084
#endif
3085 3086 3087 3088 3089
extern const struct dev_pm_ops i915_pm_ops;

extern int i915_driver_load(struct pci_dev *pdev,
			    const struct pci_device_id *ent);
extern void i915_driver_unload(struct drm_device *dev);
3090 3091
extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
3092
extern void i915_reset(struct drm_i915_private *dev_priv);
3093
extern int intel_guc_reset(struct drm_i915_private *dev_priv);
3094
extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
3095
extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
3096 3097 3098 3099
extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
3100
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
3101

3102
int intel_engines_init_mmio(struct drm_i915_private *dev_priv);
3103 3104
int intel_engines_init(struct drm_i915_private *dev_priv);

3105
/* intel_hotplug.c */
3106 3107
void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
			   u32 pin_mask, u32 long_mask);
3108 3109 3110
void intel_hpd_init(struct drm_i915_private *dev_priv);
void intel_hpd_init_work(struct drm_i915_private *dev_priv);
void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
3111
bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
3112 3113
bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
3114

L
Linus Torvalds 已提交
3115
/* i915_irq.c */
3116 3117 3118 3119 3120 3121 3122 3123 3124 3125 3126 3127 3128 3129 3130 3131 3132
static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
{
	unsigned long delay;

	if (unlikely(!i915.enable_hangcheck))
		return;

	/* Don't continually defer the hangcheck so that it is always run at
	 * least once after work has been scheduled on any ring. Otherwise,
	 * we will ignore a hung ring if a second ring is kept busy.
	 */

	delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
	queue_delayed_work(system_long_wq,
			   &dev_priv->gpu_error.hangcheck_work, delay);
}

3133
__printf(3, 4)
3134 3135
void i915_handle_error(struct drm_i915_private *dev_priv,
		       u32 engine_mask,
3136
		       const char *fmt, ...);
L
Linus Torvalds 已提交
3137

3138
extern void intel_irq_init(struct drm_i915_private *dev_priv);
3139
extern void intel_irq_fini(struct drm_i915_private *dev_priv);
3140 3141
int intel_irq_install(struct drm_i915_private *dev_priv);
void intel_irq_uninstall(struct drm_i915_private *dev_priv);
3142

3143 3144
static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
{
3145
	return dev_priv->gvt;
3146 3147
}

3148
static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
3149
{
3150
	return dev_priv->vgpu.active;
3151
}
3152

3153
void
3154
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3155
		     u32 status_mask);
3156 3157

void
3158
i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3159
		      u32 status_mask);
3160

3161 3162
void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
3163 3164 3165
void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
				   uint32_t mask,
				   uint32_t bits);
3166 3167 3168 3169 3170 3171 3172 3173 3174 3175 3176 3177 3178
void ilk_update_display_irq(struct drm_i915_private *dev_priv,
			    uint32_t interrupt_mask,
			    uint32_t enabled_irq_mask);
static inline void
ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, bits);
}
static inline void
ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, 0);
}
3179 3180 3181 3182 3183 3184 3185 3186 3187 3188 3189 3190 3191 3192
void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
			 enum pipe pipe,
			 uint32_t interrupt_mask,
			 uint32_t enabled_irq_mask);
static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
				       enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
}
static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
					enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
}
3193 3194 3195
void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
				  uint32_t interrupt_mask,
				  uint32_t enabled_irq_mask);
3196 3197 3198 3199 3200 3201 3202 3203 3204 3205 3206
static inline void
ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, bits);
}
static inline void
ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, 0);
}

3207 3208 3209 3210 3211 3212 3213 3214 3215
/* i915_gem.c */
int i915_gem_create_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3216 3217
int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3218 3219 3220 3221 3222 3223
int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
			     struct drm_file *file_priv);
int i915_gem_execbuffer(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
J
Jesse Barnes 已提交
3224 3225
int i915_gem_execbuffer2(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
3226 3227
int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
B
Ben Widawsky 已提交
3228 3229 3230 3231
int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
3232 3233
int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *file_priv);
3234 3235
int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
3236 3237 3238 3239
int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
3240 3241
int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
3242 3243
int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file);
3244 3245
int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
3246 3247
int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3248
void i915_gem_sanitize(struct drm_i915_private *i915);
3249 3250
int i915_gem_load_init(struct drm_i915_private *dev_priv);
void i915_gem_load_cleanup(struct drm_i915_private *dev_priv);
3251
void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3252
int i915_gem_freeze(struct drm_i915_private *dev_priv);
3253 3254
int i915_gem_freeze_late(struct drm_i915_private *dev_priv);

3255
void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
3256
void i915_gem_object_free(struct drm_i915_gem_object *obj);
3257 3258
void i915_gem_object_init(struct drm_i915_gem_object *obj,
			 const struct drm_i915_gem_object_ops *ops);
3259 3260 3261 3262 3263
struct drm_i915_gem_object *
i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
struct drm_i915_gem_object *
i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
				 const void *data, size_t size);
3264
void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
3265
void i915_gem_free_object(struct drm_gem_object *obj);
3266

3267 3268 3269 3270 3271 3272 3273 3274 3275 3276 3277 3278 3279
static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
{
	/* A single pass should suffice to release all the freed objects (along
	 * most call paths) , but be a little more paranoid in that freeing
	 * the objects does take a little amount of time, during which the rcu
	 * callbacks could have added new objects into the freed list, and
	 * armed the work again.
	 */
	do {
		rcu_barrier();
	} while (flush_work(&i915->mm.free_work));
}

C
Chris Wilson 已提交
3280
struct i915_vma * __must_check
3281 3282
i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
			 const struct i915_ggtt_view *view,
3283
			 u64 size,
3284 3285
			 u64 alignment,
			 u64 flags);
3286

3287
int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
3288
void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3289

3290 3291
void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);

C
Chris Wilson 已提交
3292
static inline int __sg_page_count(const struct scatterlist *sg)
3293
{
3294 3295
	return sg->length >> PAGE_SHIFT;
}
3296

3297 3298 3299
struct scatterlist *
i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
		       unsigned int n, unsigned int *offset);
3300

3301 3302 3303
struct page *
i915_gem_object_get_page(struct drm_i915_gem_object *obj,
			 unsigned int n);
3304

3305 3306 3307
struct page *
i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
			       unsigned int n);
3308

3309 3310 3311
dma_addr_t
i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
				unsigned long n);
3312

3313 3314
void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
				 struct sg_table *pages);
C
Chris Wilson 已提交
3315 3316 3317 3318 3319
int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);

static inline int __must_check
i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
{
3320
	might_lock(&obj->mm.lock);
C
Chris Wilson 已提交
3321

3322
	if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
C
Chris Wilson 已提交
3323 3324 3325 3326 3327 3328 3329
		return 0;

	return __i915_gem_object_get_pages(obj);
}

static inline void
__i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3330
{
C
Chris Wilson 已提交
3331 3332
	GEM_BUG_ON(!obj->mm.pages);

3333
	atomic_inc(&obj->mm.pages_pin_count);
C
Chris Wilson 已提交
3334 3335 3336 3337 3338
}

static inline bool
i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
{
3339
	return atomic_read(&obj->mm.pages_pin_count);
C
Chris Wilson 已提交
3340 3341 3342 3343 3344 3345 3346 3347
}

static inline void
__i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
{
	GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
	GEM_BUG_ON(!obj->mm.pages);

3348
	atomic_dec(&obj->mm.pages_pin_count);
3349
}
3350

3351 3352
static inline void
i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3353
{
C
Chris Wilson 已提交
3354
	__i915_gem_object_unpin_pages(obj);
3355 3356
}

3357 3358 3359 3360 3361 3362 3363
enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
	I915_MM_NORMAL = 0,
	I915_MM_SHRINKER
};

void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
				 enum i915_mm_subclass subclass);
3364
void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
C
Chris Wilson 已提交
3365

3366 3367 3368 3369 3370
enum i915_map_type {
	I915_MAP_WB = 0,
	I915_MAP_WC,
};

3371 3372
/**
 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3373 3374
 * @obj: the object to map into kernel address space
 * @type: the type of mapping, used to select pgprot_t
3375 3376 3377
 *
 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
 * pages and then returns a contiguous mapping of the backing storage into
3378 3379
 * the kernel address space. Based on the @type of mapping, the PTE will be
 * set to either WriteBack or WriteCombine (via pgprot_t).
3380
 *
3381 3382
 * The caller is responsible for calling i915_gem_object_unpin_map() when the
 * mapping is no longer required.
3383
 *
3384 3385
 * Returns the pointer through which to access the mapped object, or an
 * ERR_PTR() on error.
3386
 */
3387 3388
void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
					   enum i915_map_type type);
3389 3390 3391

/**
 * i915_gem_object_unpin_map - releases an earlier mapping
3392
 * @obj: the object to unmap
3393 3394 3395 3396 3397 3398 3399 3400 3401 3402 3403
 *
 * After pinning the object and mapping its pages, once you are finished
 * with your access, call i915_gem_object_unpin_map() to release the pin
 * upon the mapping. Once the pin count reaches zero, that mapping may be
 * removed.
 */
static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
{
	i915_gem_object_unpin_pages(obj);
}

3404 3405 3406 3407
int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
				    unsigned int *needs_clflush);
int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
				     unsigned int *needs_clflush);
3408 3409 3410
#define CLFLUSH_BEFORE	BIT(0)
#define CLFLUSH_AFTER	BIT(1)
#define CLFLUSH_FLAGS	(CLFLUSH_BEFORE | CLFLUSH_AFTER)
3411 3412 3413 3414 3415 3416 3417

static inline void
i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
{
	i915_gem_object_unpin_pages(obj);
}

3418
int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
B
Ben Widawsky 已提交
3419
void i915_vma_move_to_active(struct i915_vma *vma,
3420 3421
			     struct drm_i915_gem_request *req,
			     unsigned int flags);
3422 3423 3424
int i915_gem_dumb_create(struct drm_file *file_priv,
			 struct drm_device *dev,
			 struct drm_mode_create_dumb *args);
3425 3426
int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
		      uint32_t handle, uint64_t *offset);
3427
int i915_gem_mmap_gtt_version(void);
3428 3429 3430 3431 3432

void i915_gem_track_fb(struct drm_i915_gem_object *old,
		       struct drm_i915_gem_object *new,
		       unsigned frontbuffer_bits);

3433
int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3434

3435
struct drm_i915_gem_request *
3436
i915_gem_find_active_request(struct intel_engine_cs *engine);
3437

3438
void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3439

3440 3441 3442 3443 3444 3445
static inline bool i915_reset_backoff(struct i915_gpu_error *error)
{
	return unlikely(test_bit(I915_RESET_BACKOFF, &error->flags));
}

static inline bool i915_reset_handoff(struct i915_gpu_error *error)
3446
{
3447
	return unlikely(test_bit(I915_RESET_HANDOFF, &error->flags));
3448 3449
}

3450
static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3451
{
3452
	return unlikely(test_bit(I915_WEDGED, &error->flags));
3453 3454
}

3455
static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error *error)
3456
{
3457
	return i915_reset_backoff(error) | i915_terminally_wedged(error);
M
Mika Kuoppala 已提交
3458 3459 3460 3461
}

static inline u32 i915_reset_count(struct i915_gpu_error *error)
{
3462
	return READ_ONCE(error->reset_count);
3463
}
3464

3465
int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
3466
void i915_gem_reset(struct drm_i915_private *dev_priv);
3467
void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
3468
void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3469
bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
3470

3471
void i915_gem_init_mmio(struct drm_i915_private *i915);
3472 3473
int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3474
void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3475
void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3476 3477
int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
			   unsigned int flags);
3478 3479
int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
void i915_gem_resume(struct drm_i915_private *dev_priv);
3480
int i915_gem_fault(struct vm_fault *vmf);
3481 3482 3483 3484
int i915_gem_object_wait(struct drm_i915_gem_object *obj,
			 unsigned int flags,
			 long timeout,
			 struct intel_rps_client *rps);
3485 3486 3487 3488 3489
int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
				  unsigned int flags,
				  int priority);
#define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX

3490
int __must_check
3491 3492 3493
i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write);
int __must_check
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write);
3494
int __must_check
3495
i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
C
Chris Wilson 已提交
3496
struct i915_vma * __must_check
3497 3498
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
				     u32 alignment,
3499
				     const struct i915_ggtt_view *view);
C
Chris Wilson 已提交
3500
void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3501
int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3502
				int align);
3503
int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
3504
void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3505

3506 3507 3508
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
				    enum i915_cache_level cache_level);

3509 3510 3511 3512 3513 3514
struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
				struct dma_buf *dma_buf);

struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
				struct drm_gem_object *gem_obj, int flags);

3515 3516 3517 3518 3519 3520
static inline struct i915_hw_ppgtt *
i915_vm_to_ppgtt(struct i915_address_space *vm)
{
	return container_of(vm, struct i915_hw_ppgtt, base);
}

J
Joonas Lahtinen 已提交
3521
/* i915_gem_fence_reg.c */
3522 3523 3524
int __must_check i915_vma_get_fence(struct i915_vma *vma);
int __must_check i915_vma_put_fence(struct i915_vma *vma);

3525
void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
3526
void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3527

3528
void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3529 3530 3531 3532
void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
				       struct sg_table *pages);
void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
					 struct sg_table *pages);
3533

3534 3535 3536 3537 3538
static inline struct i915_gem_context *
i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
{
	struct i915_gem_context *ctx;

3539
	lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
3540 3541 3542 3543 3544 3545 3546 3547

	ctx = idr_find(&file_priv->context_idr, id);
	if (!ctx)
		return ERR_PTR(-ENOENT);

	return ctx;
}

3548 3549
static inline struct i915_gem_context *
i915_gem_context_get(struct i915_gem_context *ctx)
3550
{
3551
	kref_get(&ctx->ref);
3552
	return ctx;
3553 3554
}

3555
static inline void i915_gem_context_put(struct i915_gem_context *ctx)
3556
{
3557
	lockdep_assert_held(&ctx->i915->drm.struct_mutex);
3558
	kref_put(&ctx->ref, i915_gem_context_free);
3559 3560
}

3561 3562
static inline void i915_gem_context_put_unlocked(struct i915_gem_context *ctx)
{
3563 3564 3565 3566
	struct mutex *lock = &ctx->i915->drm.struct_mutex;

	if (kref_put_mutex(&ctx->ref, i915_gem_context_free, lock))
		mutex_unlock(lock);
3567 3568
}

C
Chris Wilson 已提交
3569 3570 3571 3572 3573 3574 3575 3576 3577 3578
static inline struct intel_timeline *
i915_gem_context_lookup_timeline(struct i915_gem_context *ctx,
				 struct intel_engine_cs *engine)
{
	struct i915_address_space *vm;

	vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base;
	return &vm->timeline.engine[engine->id];
}

3579 3580
int i915_perf_open_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file);
3581 3582 3583
void i915_oa_init_reg_state(struct intel_engine_cs *engine,
			    struct i915_gem_context *ctx,
			    uint32_t *reg_state);
3584

3585
/* i915_gem_evict.c */
3586
int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3587
					  u64 min_size, u64 alignment,
3588
					  unsigned cache_level,
3589
					  u64 start, u64 end,
3590
					  unsigned flags);
3591 3592 3593
int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
					 struct drm_mm_node *node,
					 unsigned int flags);
3594
int i915_gem_evict_vm(struct i915_address_space *vm);
3595

3596
/* belongs in i915_gem_gtt.h */
3597
static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3598
{
3599
	wmb();
3600
	if (INTEL_GEN(dev_priv) < 6)
3601 3602
		intel_gtt_chipset_flush();
}
3603

3604
/* i915_gem_stolen.c */
3605 3606 3607
int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
				struct drm_mm_node *node, u64 size,
				unsigned alignment);
3608 3609 3610 3611
int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
					 struct drm_mm_node *node, u64 size,
					 unsigned alignment, u64 start,
					 u64 end);
3612 3613
void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
				 struct drm_mm_node *node);
3614
int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3615
void i915_gem_cleanup_stolen(struct drm_device *dev);
3616
struct drm_i915_gem_object *
3617
i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, u32 size);
3618
struct drm_i915_gem_object *
3619
i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3620 3621 3622
					       u32 stolen_offset,
					       u32 gtt_offset,
					       u32 size);
3623

3624 3625 3626
/* i915_gem_internal.c */
struct drm_i915_gem_object *
i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3627
				phys_addr_t size);
3628

3629 3630
/* i915_gem_shrinker.c */
unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3631
			      unsigned long target,
3632 3633 3634 3635
			      unsigned flags);
#define I915_SHRINK_PURGEABLE 0x1
#define I915_SHRINK_UNBOUND 0x2
#define I915_SHRINK_BOUND 0x4
3636
#define I915_SHRINK_ACTIVE 0x8
3637
#define I915_SHRINK_VMAPS 0x10
3638 3639
unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3640
void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3641 3642


3643
/* i915_gem_tiling.c */
3644
static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3645
{
3646
	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3647 3648

	return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3649
		i915_gem_object_is_tiled(obj);
3650 3651
}

3652 3653 3654 3655 3656
u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
			unsigned int tiling, unsigned int stride);
u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
			     unsigned int tiling, unsigned int stride);

3657
/* i915_debugfs.c */
3658
#ifdef CONFIG_DEBUG_FS
3659
int i915_debugfs_register(struct drm_i915_private *dev_priv);
J
Jani Nikula 已提交
3660
int i915_debugfs_connector_add(struct drm_connector *connector);
3661
void intel_display_crc_init(struct drm_i915_private *dev_priv);
3662
#else
3663
static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3664 3665
static inline int i915_debugfs_connector_add(struct drm_connector *connector)
{ return 0; }
3666
static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3667
#endif
3668 3669

/* i915_gpu_error.c */
3670 3671
#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)

3672 3673
__printf(2, 3)
void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3674
int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3675
			    const struct i915_gpu_state *gpu);
3676
int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3677
			      struct drm_i915_private *i915,
3678 3679 3680 3681 3682 3683
			      size_t count, loff_t pos);
static inline void i915_error_state_buf_release(
	struct drm_i915_error_state_buf *eb)
{
	kfree(eb->buf);
}
3684 3685

struct i915_gpu_state *i915_capture_gpu_state(struct drm_i915_private *i915);
3686 3687
void i915_capture_error_state(struct drm_i915_private *dev_priv,
			      u32 engine_mask,
3688
			      const char *error_msg);
3689 3690 3691 3692 3693 3694 3695 3696 3697 3698 3699 3700 3701 3702 3703 3704 3705

static inline struct i915_gpu_state *
i915_gpu_state_get(struct i915_gpu_state *gpu)
{
	kref_get(&gpu->ref);
	return gpu;
}

void __i915_gpu_state_free(struct kref *kref);
static inline void i915_gpu_state_put(struct i915_gpu_state *gpu)
{
	if (gpu)
		kref_put(&gpu->ref, __i915_gpu_state_free);
}

struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915);
void i915_reset_error_state(struct drm_i915_private *i915);
3706

3707 3708 3709 3710 3711 3712 3713 3714
#else

static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
					    u32 engine_mask,
					    const char *error_msg)
{
}

3715 3716 3717 3718 3719 3720 3721
static inline struct i915_gpu_state *
i915_first_error_state(struct drm_i915_private *i915)
{
	return NULL;
}

static inline void i915_reset_error_state(struct drm_i915_private *i915)
3722 3723 3724 3725 3726
{
}

#endif

3727
const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3728

3729
/* i915_cmd_parser.c */
3730
int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3731
void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3732 3733 3734 3735 3736 3737 3738
void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
int intel_engine_cmd_parser(struct intel_engine_cs *engine,
			    struct drm_i915_gem_object *batch_obj,
			    struct drm_i915_gem_object *shadow_batch_obj,
			    u32 batch_start_offset,
			    u32 batch_len,
			    bool is_master);
3739

3740 3741 3742
/* i915_perf.c */
extern void i915_perf_init(struct drm_i915_private *dev_priv);
extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3743 3744
extern void i915_perf_register(struct drm_i915_private *dev_priv);
extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3745

3746
/* i915_suspend.c */
3747 3748
extern int i915_save_state(struct drm_i915_private *dev_priv);
extern int i915_restore_state(struct drm_i915_private *dev_priv);
3749

B
Ben Widawsky 已提交
3750
/* i915_sysfs.c */
D
David Weinehall 已提交
3751 3752
void i915_setup_sysfs(struct drm_i915_private *dev_priv);
void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
B
Ben Widawsky 已提交
3753

3754 3755 3756 3757
/* intel_lpe_audio.c */
int  intel_lpe_audio_init(struct drm_i915_private *dev_priv);
void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv);
void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv);
3758
void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
3759 3760
			    enum pipe pipe, enum port port,
			    const void *eld, int ls_clock, bool dp_output);
3761

3762
/* intel_i2c.c */
3763 3764
extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3765 3766
extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
				     unsigned int pin);
3767

3768 3769
extern struct i2c_adapter *
intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
C
Chris Wilson 已提交
3770 3771
extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3772
static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3773 3774 3775
{
	return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
}
3776
extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3777

3778
/* intel_bios.c */
3779
void intel_bios_init(struct drm_i915_private *dev_priv);
J
Jani Nikula 已提交
3780
bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3781
bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3782
bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3783
bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3784
bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3785
bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3786
bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3787 3788
bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
				     enum port port);
3789 3790 3791
bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
				enum port port);

3792

3793
/* intel_opregion.c */
3794
#ifdef CONFIG_ACPI
3795
extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3796 3797
extern void intel_opregion_register(struct drm_i915_private *dev_priv);
extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3798
extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3799 3800
extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
					 bool enable);
3801
extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3802
					 pci_power_t state);
3803
extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3804
#else
3805
static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3806 3807
static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
3808 3809 3810
static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
{
}
3811 3812 3813 3814 3815
static inline int
intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
{
	return 0;
}
3816
static inline int
3817
intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3818 3819 3820
{
	return 0;
}
3821
static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3822 3823 3824
{
	return -ENODEV;
}
3825
#endif
3826

J
Jesse Barnes 已提交
3827 3828 3829 3830 3831 3832 3833 3834 3835
/* intel_acpi.c */
#ifdef CONFIG_ACPI
extern void intel_register_dsm_handler(void);
extern void intel_unregister_dsm_handler(void);
#else
static inline void intel_register_dsm_handler(void) { return; }
static inline void intel_unregister_dsm_handler(void) { return; }
#endif /* CONFIG_ACPI */

3836 3837 3838 3839 3840 3841 3842
/* intel_device_info.c */
static inline struct intel_device_info *
mkwrite_device_info(struct drm_i915_private *dev_priv)
{
	return (struct intel_device_info *)&dev_priv->info;
}

3843
const char *intel_platform_name(enum intel_platform platform);
3844 3845 3846
void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
void intel_device_info_dump(struct drm_i915_private *dev_priv);

J
Jesse Barnes 已提交
3847
/* modesetting */
3848
extern void intel_modeset_init_hw(struct drm_device *dev);
3849
extern int intel_modeset_init(struct drm_device *dev);
3850
extern void intel_modeset_gem_init(struct drm_device *dev);
J
Jesse Barnes 已提交
3851
extern void intel_modeset_cleanup(struct drm_device *dev);
3852
extern int intel_connector_register(struct drm_connector *);
3853
extern void intel_connector_unregister(struct drm_connector *);
3854 3855
extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
				       bool state);
3856
extern void intel_display_resume(struct drm_device *dev);
3857 3858
extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3859
extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3860
extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3861
extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3862
extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3863
				  bool enable);
3864

B
Ben Widawsky 已提交
3865 3866
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file);
3867

3868
/* overlay */
3869 3870
extern struct intel_overlay_error_state *
intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3871 3872
extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
					    struct intel_overlay_error_state *error);
3873

3874 3875
extern struct intel_display_error_state *
intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3876
extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3877
					    struct intel_display_error_state *error);
3878

3879 3880
int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3881 3882
int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
		      u32 reply_mask, u32 reply, int timeout_base_ms);
3883 3884

/* intel_sideband.c */
3885
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3886
int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3887
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3888 3889
u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3890 3891 3892 3893
u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3894 3895
u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3896 3897
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3898 3899 3900 3901
u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
		   enum intel_sbi_destination destination);
void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
		     enum intel_sbi_destination destination);
3902 3903
u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3904

3905
/* intel_dpio_phy.c */
3906
void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3907
			     enum dpio_phy *phy, enum dpio_channel *ch);
3908 3909 3910
void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
				  enum port port, u32 margin, u32 scale,
				  u32 enable, u32 deemphasis);
3911 3912 3913 3914 3915 3916 3917 3918 3919 3920 3921 3922
void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
			    enum dpio_phy phy);
bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
			      enum dpio_phy phy);
uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
					     uint8_t lane_count);
void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
				     uint8_t lane_lat_optim_mask);
uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);

3923 3924 3925
void chv_set_phy_signal_level(struct intel_encoder *encoder,
			      u32 deemph_reg_value, u32 margin_reg_value,
			      bool uniq_trans_scale);
3926 3927
void chv_data_lane_soft_reset(struct intel_encoder *encoder,
			      bool reset);
3928
void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3929 3930
void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3931
void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3932

3933 3934 3935
void vlv_set_phy_signal_level(struct intel_encoder *encoder,
			      u32 demph_reg_value, u32 preemph_reg_value,
			      u32 uniqtranscale_reg_value, u32 tx3_demph);
3936
void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3937
void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3938
void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3939

3940 3941
int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3942 3943
u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
			   const i915_reg_t reg);
3944

3945 3946 3947 3948 3949 3950 3951 3952 3953 3954 3955 3956 3957
#define I915_READ8(reg)		dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
#define I915_WRITE8(reg, val)	dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)

#define I915_READ16(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
#define I915_WRITE16(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
#define I915_READ16_NOTRACE(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
#define I915_WRITE16_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)

#define I915_READ(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
#define I915_WRITE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
#define I915_READ_NOTRACE(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
#define I915_WRITE_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)

3958 3959 3960 3961
/* Be very careful with read/write 64-bit values. On 32-bit machines, they
 * will be implemented using 2 32-bit writes in an arbitrary order with
 * an arbitrary delay between them. This can cause the hardware to
 * act upon the intermediate value, possibly leading to corruption and
3962 3963 3964 3965 3966 3967 3968 3969 3970
 * machine death. For this reason we do not support I915_WRITE64, or
 * dev_priv->uncore.funcs.mmio_writeq.
 *
 * When reading a 64-bit value as two 32-bit values, the delay may cause
 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
 * occasionally a 64-bit register does not actualy support a full readq
 * and must be read using two 32-bit reads.
 *
 * You have been warned.
3971
 */
3972
#define I915_READ64(reg)	dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3973

3974
#define I915_READ64_2x32(lower_reg, upper_reg) ({			\
3975 3976
	u32 upper, lower, old_upper, loop = 0;				\
	upper = I915_READ(upper_reg);					\
3977
	do {								\
3978
		old_upper = upper;					\
3979
		lower = I915_READ(lower_reg);				\
3980 3981
		upper = I915_READ(upper_reg);				\
	} while (upper != old_upper && loop++ < 2);			\
3982
	(u64)upper << 32 | lower; })
3983

3984 3985 3986
#define POSTING_READ(reg)	(void)I915_READ_NOTRACE(reg)
#define POSTING_READ16(reg)	(void)I915_READ16_NOTRACE(reg)

3987
#define __raw_read(x, s) \
3988
static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
3989
					     i915_reg_t reg) \
3990
{ \
3991
	return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3992 3993 3994
}

#define __raw_write(x, s) \
3995
static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
3996
				       i915_reg_t reg, uint##x##_t val) \
3997
{ \
3998
	write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3999 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012
}
__raw_read(8, b)
__raw_read(16, w)
__raw_read(32, l)
__raw_read(64, q)

__raw_write(8, b)
__raw_write(16, w)
__raw_write(32, l)
__raw_write(64, q)

#undef __raw_read
#undef __raw_write

4013
/* These are untraced mmio-accessors that are only valid to be used inside
4014
 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
4015
 * controlled.
4016
 *
4017
 * Think twice, and think again, before using these.
4018 4019 4020 4021 4022 4023 4024 4025 4026 4027 4028 4029 4030 4031 4032 4033 4034 4035 4036 4037
 *
 * As an example, these accessors can possibly be used between:
 *
 * spin_lock_irq(&dev_priv->uncore.lock);
 * intel_uncore_forcewake_get__locked();
 *
 * and
 *
 * intel_uncore_forcewake_put__locked();
 * spin_unlock_irq(&dev_priv->uncore.lock);
 *
 *
 * Note: some registers may not need forcewake held, so
 * intel_uncore_forcewake_{get,put} can be omitted, see
 * intel_uncore_forcewake_for_reg().
 *
 * Certain architectures will die if the same cacheline is concurrently accessed
 * by different clients (e.g. on Ivybridge). Access to registers should
 * therefore generally be serialised, by either the dev_priv->uncore.lock or
 * a more localised lock guarding all access to that bank of registers.
4038
 */
4039 4040
#define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
4041
#define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
4042 4043
#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)

4044 4045 4046 4047
/* "Broadcast RGB" property */
#define INTEL_BROADCAST_RGB_AUTO 0
#define INTEL_BROADCAST_RGB_FULL 1
#define INTEL_BROADCAST_RGB_LIMITED 2
4048

4049
static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
4050
{
4051
	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4052
		return VLV_VGACNTRL;
4053
	else if (INTEL_GEN(dev_priv) >= 5)
4054
		return CPU_VGACNTRL;
4055 4056 4057 4058
	else
		return VGACNTRL;
}

4059 4060 4061 4062 4063 4064 4065
static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
{
	unsigned long j = msecs_to_jiffies(m);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

4066 4067 4068 4069 4070
static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
{
        return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
}

4071 4072 4073 4074 4075 4076 4077 4078
static inline unsigned long
timespec_to_jiffies_timeout(const struct timespec *value)
{
	unsigned long j = timespec_to_jiffies(value);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

4079 4080 4081 4082 4083 4084 4085 4086 4087
/*
 * If you need to wait X milliseconds between events A and B, but event B
 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
 * when event A happened, then just before event B you call this function and
 * pass the timestamp as the first argument, and X as the second argument.
 */
static inline void
wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
{
4088
	unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
4089 4090 4091 4092 4093 4094 4095 4096 4097 4098

	/*
	 * Don't re-read the value of "jiffies" every time since it may change
	 * behind our back and break the math.
	 */
	tmp_jiffies = jiffies;
	target_jiffies = timestamp_jiffies +
			 msecs_to_jiffies_timeout(to_wait_ms);

	if (time_after(target_jiffies, tmp_jiffies)) {
4099 4100 4101 4102
		remaining_jiffies = target_jiffies - tmp_jiffies;
		while (remaining_jiffies)
			remaining_jiffies =
			    schedule_timeout_uninterruptible(remaining_jiffies);
4103 4104
	}
}
4105 4106

static inline bool
4107
__i915_request_irq_complete(const struct drm_i915_gem_request *req)
4108
{
4109
	struct intel_engine_cs *engine = req->engine;
4110
	u32 seqno;
4111

4112 4113 4114 4115 4116 4117 4118 4119 4120
	/* Note that the engine may have wrapped around the seqno, and
	 * so our request->global_seqno will be ahead of the hardware,
	 * even though it completed the request before wrapping. We catch
	 * this by kicking all the waiters before resetting the seqno
	 * in hardware, and also signal the fence.
	 */
	if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &req->fence.flags))
		return true;

4121 4122 4123 4124 4125 4126 4127 4128 4129 4130
	/* The request was dequeued before we were awoken. We check after
	 * inspecting the hw to confirm that this was the same request
	 * that generated the HWS update. The memory barriers within
	 * the request execution are sufficient to ensure that a check
	 * after reading the value from hw matches this request.
	 */
	seqno = i915_gem_request_global_seqno(req);
	if (!seqno)
		return false;

4131 4132 4133
	/* Before we do the heavier coherent read of the seqno,
	 * check the value (hopefully) in the CPU cacheline.
	 */
4134
	if (__i915_gem_request_completed(req, seqno))
4135 4136
		return true;

4137 4138 4139 4140 4141 4142 4143 4144 4145 4146 4147
	/* Ensure our read of the seqno is coherent so that we
	 * do not "miss an interrupt" (i.e. if this is the last
	 * request and the seqno write from the GPU is not visible
	 * by the time the interrupt fires, we will see that the
	 * request is incomplete and go back to sleep awaiting
	 * another interrupt that will never come.)
	 *
	 * Strictly, we only need to do this once after an interrupt,
	 * but it is easier and safer to do it every time the waiter
	 * is woken.
	 */
4148
	if (engine->irq_seqno_barrier &&
4149
	    test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) {
4150
		struct intel_breadcrumbs *b = &engine->breadcrumbs;
4151

4152 4153 4154 4155 4156 4157 4158 4159 4160 4161 4162 4163
		/* The ordering of irq_posted versus applying the barrier
		 * is crucial. The clearing of the current irq_posted must
		 * be visible before we perform the barrier operation,
		 * such that if a subsequent interrupt arrives, irq_posted
		 * is reasserted and our task rewoken (which causes us to
		 * do another __i915_request_irq_complete() immediately
		 * and reapply the barrier). Conversely, if the clear
		 * occurs after the barrier, then an interrupt that arrived
		 * whilst we waited on the barrier would not trigger a
		 * barrier on the next pass, and the read may not see the
		 * seqno update.
		 */
4164
		engine->irq_seqno_barrier(engine);
4165 4166 4167 4168 4169 4170 4171

		/* If we consume the irq, but we are no longer the bottom-half,
		 * the real bottom-half may not have serialised their own
		 * seqno check with the irq-barrier (i.e. may have inspected
		 * the seqno before we believe it coherent since they see
		 * irq_posted == false but we are still running).
		 */
4172
		spin_lock_irq(&b->irq_lock);
4173
		if (b->irq_wait && b->irq_wait->tsk != current)
4174 4175 4176 4177 4178 4179
			/* Note that if the bottom-half is changed as we
			 * are sending the wake-up, the new bottom-half will
			 * be woken by whomever made the change. We only have
			 * to worry about when we steal the irq-posted for
			 * ourself.
			 */
4180
			wake_up_process(b->irq_wait->tsk);
4181
		spin_unlock_irq(&b->irq_lock);
4182

4183
		if (__i915_gem_request_completed(req, seqno))
4184 4185
			return true;
	}
4186 4187 4188 4189

	return false;
}

4190 4191 4192
void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);

4193 4194 4195 4196 4197 4198 4199 4200 4201 4202 4203 4204 4205 4206 4207 4208
/* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
 * perform the operation. To check beforehand, pass in the parameters to
 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
 * you only need to pass in the minor offsets, page-aligned pointers are
 * always valid.
 *
 * For just checking for SSE4.1, in the foreknowledge that the future use
 * will be correctly aligned, just use i915_has_memcpy_from_wc().
 */
#define i915_can_memcpy_from_wc(dst, src, len) \
	i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)

#define i915_has_memcpy_from_wc() \
	i915_memcpy_from_wc(NULL, NULL, 0)

4209 4210 4211 4212 4213
/* i915_mm.c */
int remap_io_mapping(struct vm_area_struct *vma,
		     unsigned long addr, unsigned long pfn, unsigned long size,
		     struct io_mapping *iomap);

4214 4215 4216 4217 4218 4219
static inline bool i915_gem_object_is_coherent(struct drm_i915_gem_object *obj)
{
	return (obj->cache_level != I915_CACHE_NONE ||
		HAS_LLC(to_i915(obj->base.dev)));
}

L
Linus Torvalds 已提交
4220
#endif