i915_drv.h 117.5 KB
Newer Older
L
Linus Torvalds 已提交
1 2
/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
 */
D
Dave Airlie 已提交
3
/*
4
 *
L
Linus Torvalds 已提交
5 6
 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
D
Dave Airlie 已提交
28
 */
L
Linus Torvalds 已提交
29 30 31 32

#ifndef _I915_DRV_H_
#define _I915_DRV_H_

33
#include <uapi/drm/i915_drm.h>
34
#include <uapi/drm/drm_fourcc.h>
35

36
#include <linux/io-mapping.h>
37
#include <linux/i2c.h>
38
#include <linux/i2c-algo-bit.h>
39
#include <linux/backlight.h>
40
#include <linux/hashtable.h>
41
#include <linux/intel-iommu.h>
42
#include <linux/kref.h>
43
#include <linux/pm_qos.h>
44
#include <linux/reservation.h>
45 46 47 48 49 50
#include <linux/shmem_fs.h>

#include <drm/drmP.h>
#include <drm/intel-gtt.h>
#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
#include <drm/drm_gem.h>
D
Daniel Vetter 已提交
51
#include <drm/drm_auth.h>
52 53 54 55 56

#include "i915_params.h"
#include "i915_reg.h"

#include "intel_bios.h"
57
#include "intel_dpll_mgr.h"
58
#include "intel_uc.h"
59 60 61
#include "intel_lrc.h"
#include "intel_ringbuffer.h"

62
#include "i915_gem.h"
J
Joonas Lahtinen 已提交
63 64
#include "i915_gem_fence_reg.h"
#include "i915_gem_object.h"
65 66
#include "i915_gem_gtt.h"
#include "i915_gem_render_state.h"
67
#include "i915_gem_request.h"
68
#include "i915_gem_timeline.h"
69

J
Joonas Lahtinen 已提交
70 71
#include "i915_vma.h"

72 73
#include "intel_gvt.h"

L
Linus Torvalds 已提交
74 75 76 77 78
/* General customization:
 */

#define DRIVER_NAME		"i915"
#define DRIVER_DESC		"Intel Graphics"
79 80
#define DRIVER_DATE		"20161205"
#define DRIVER_TIMESTAMP	1480926326
L
Linus Torvalds 已提交
81

82
#undef WARN_ON
83 84 85 86 87 88 89 90
/* Many gcc seem to no see through this and fall over :( */
#if 0
#define WARN_ON(x) ({ \
	bool __i915_warn_cond = (x); \
	if (__builtin_constant_p(__i915_warn_cond)) \
		BUILD_BUG_ON(__i915_warn_cond); \
	WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
#else
91
#define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
92 93
#endif

94
#undef WARN_ON_ONCE
95
#define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
96

97 98
#define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
			     (long) (x), __func__);
99

R
Rob Clark 已提交
100 101 102 103 104 105 106 107 108
/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
 * which may not necessarily be a user visible problem.  This will either
 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
 * enable distros and users to tailor their preferred amount of i915 abrt
 * spam.
 */
#define I915_STATE_WARN(condition, format...) ({			\
	int __ret_warn_on = !!(condition);				\
109 110
	if (unlikely(__ret_warn_on))					\
		if (!WARN(i915.verbose_state_checks, format))		\
R
Rob Clark 已提交
111 112 113 114
			DRM_ERROR(format);				\
	unlikely(__ret_warn_on);					\
})

115 116
#define I915_STATE_WARN_ON(x)						\
	I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
117

118 119 120 121
bool __i915_inject_load_failure(const char *func, int line);
#define i915_inject_load_failure() \
	__i915_inject_load_failure(__func__, __LINE__)

122 123 124 125 126
static inline const char *yesno(bool v)
{
	return v ? "yes" : "no";
}

127 128 129 130 131
static inline const char *onoff(bool v)
{
	return v ? "on" : "off";
}

132 133 134 135 136
static inline const char *enableddisabled(bool v)
{
	return v ? "enabled" : "disabled";
}

137
enum pipe {
138
	INVALID_PIPE = -1,
139 140
	PIPE_A = 0,
	PIPE_B,
141
	PIPE_C,
142 143
	_PIPE_EDP,
	I915_MAX_PIPES = _PIPE_EDP
144
};
145
#define pipe_name(p) ((p) + 'A')
146

P
Paulo Zanoni 已提交
147 148 149 150
enum transcoder {
	TRANSCODER_A = 0,
	TRANSCODER_B,
	TRANSCODER_C,
151
	TRANSCODER_EDP,
J
Jani Nikula 已提交
152 153
	TRANSCODER_DSI_A,
	TRANSCODER_DSI_C,
154
	I915_MAX_TRANSCODERS
P
Paulo Zanoni 已提交
155
};
156 157 158 159 160 161 162 163 164 165 166 167

static inline const char *transcoder_name(enum transcoder transcoder)
{
	switch (transcoder) {
	case TRANSCODER_A:
		return "A";
	case TRANSCODER_B:
		return "B";
	case TRANSCODER_C:
		return "C";
	case TRANSCODER_EDP:
		return "EDP";
J
Jani Nikula 已提交
168 169 170 171
	case TRANSCODER_DSI_A:
		return "DSI A";
	case TRANSCODER_DSI_C:
		return "DSI C";
172 173 174 175
	default:
		return "<invalid>";
	}
}
P
Paulo Zanoni 已提交
176

J
Jani Nikula 已提交
177 178 179 180 181
static inline bool transcoder_is_dsi(enum transcoder transcoder)
{
	return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
}

182
/*
183 184
 * Global legacy plane identifier. Valid only for primary/sprite
 * planes on pre-g4x, and only for primary planes on g4x+.
185
 */
186
enum plane {
187
	PLANE_A,
188
	PLANE_B,
189
	PLANE_C,
190
};
191
#define plane_name(p) ((p) + 'A')
192

193
#define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
194

195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212
/*
 * Per-pipe plane identifier.
 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
 * number of planes per CRTC.  Not all platforms really have this many planes,
 * which means some arrays of size I915_MAX_PLANES may have unused entries
 * between the topmost sprite plane and the cursor plane.
 *
 * This is expected to be passed to various register macros
 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
 */
enum plane_id {
	PLANE_PRIMARY,
	PLANE_SPRITE0,
	PLANE_SPRITE1,
	PLANE_CURSOR,
	I915_MAX_PLANES,
};

213 214 215 216
#define for_each_plane_id_on_crtc(__crtc, __p) \
	for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
		for_each_if ((__crtc)->plane_ids_mask & BIT(__p))

217
enum port {
218
	PORT_NONE = -1,
219 220 221 222 223 224 225 226 227
	PORT_A = 0,
	PORT_B,
	PORT_C,
	PORT_D,
	PORT_E,
	I915_MAX_PORTS
};
#define port_name(p) ((p) + 'A')

228
#define I915_NUM_PHYS_VLV 2
229 230 231 232 233 234 235 236

enum dpio_channel {
	DPIO_CH0,
	DPIO_CH1
};

enum dpio_phy {
	DPIO_PHY0,
237 238
	DPIO_PHY1,
	DPIO_PHY2,
239 240
};

241 242 243 244 245 246 247 248 249 250
enum intel_display_power_domain {
	POWER_DOMAIN_PIPE_A,
	POWER_DOMAIN_PIPE_B,
	POWER_DOMAIN_PIPE_C,
	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
	POWER_DOMAIN_TRANSCODER_A,
	POWER_DOMAIN_TRANSCODER_B,
	POWER_DOMAIN_TRANSCODER_C,
251
	POWER_DOMAIN_TRANSCODER_EDP,
J
Jani Nikula 已提交
252 253
	POWER_DOMAIN_TRANSCODER_DSI_A,
	POWER_DOMAIN_TRANSCODER_DSI_C,
254 255 256 257 258
	POWER_DOMAIN_PORT_DDI_A_LANES,
	POWER_DOMAIN_PORT_DDI_B_LANES,
	POWER_DOMAIN_PORT_DDI_C_LANES,
	POWER_DOMAIN_PORT_DDI_D_LANES,
	POWER_DOMAIN_PORT_DDI_E_LANES,
I
Imre Deak 已提交
259 260 261
	POWER_DOMAIN_PORT_DSI,
	POWER_DOMAIN_PORT_CRT,
	POWER_DOMAIN_PORT_OTHER,
V
Ville Syrjälä 已提交
262
	POWER_DOMAIN_VGA,
I
Imre Deak 已提交
263
	POWER_DOMAIN_AUDIO,
P
Paulo Zanoni 已提交
264
	POWER_DOMAIN_PLLS,
265 266 267 268
	POWER_DOMAIN_AUX_A,
	POWER_DOMAIN_AUX_B,
	POWER_DOMAIN_AUX_C,
	POWER_DOMAIN_AUX_D,
269
	POWER_DOMAIN_GMBUS,
270
	POWER_DOMAIN_MODESET,
271
	POWER_DOMAIN_INIT,
272 273

	POWER_DOMAIN_NUM,
274 275 276 277 278
};

#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
		((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
279 280 281
#define POWER_DOMAIN_TRANSCODER(tran) \
	((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
	 (tran) + POWER_DOMAIN_TRANSCODER_A)
282

283 284 285 286 287 288
enum hpd_pin {
	HPD_NONE = 0,
	HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
	HPD_CRT,
	HPD_SDVO_B,
	HPD_SDVO_C,
289
	HPD_PORT_A,
290 291 292
	HPD_PORT_B,
	HPD_PORT_C,
	HPD_PORT_D,
X
Xiong Zhang 已提交
293
	HPD_PORT_E,
294 295 296
	HPD_NUM_PINS
};

297 298 299
#define for_each_hpd_pin(__pin) \
	for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)

300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319
struct i915_hotplug {
	struct work_struct hotplug_work;

	struct {
		unsigned long last_jiffies;
		int count;
		enum {
			HPD_ENABLED = 0,
			HPD_DISABLED = 1,
			HPD_MARK_DISABLED = 2
		} state;
	} stats[HPD_NUM_PINS];
	u32 event_bits;
	struct delayed_work reenable_work;

	struct intel_digital_port *irq_port[I915_MAX_PORTS];
	u32 long_port_mask;
	u32 short_port_mask;
	struct work_struct dig_port_work;

320 321 322
	struct work_struct poll_init_work;
	bool poll_enabled;

323 324 325 326 327 328 329 330 331 332
	/*
	 * if we get a HPD irq from DP and a HPD irq from non-DP
	 * the non-DP HPD could block the workqueue on a mode config
	 * mutex getting, that userspace may have taken. However
	 * userspace is waiting on the DP workqueue to run which is
	 * blocked behind the non-DP one.
	 */
	struct workqueue_struct *dp_wq;
};

333 334 335 336 337 338
#define I915_GEM_GPU_DOMAINS \
	(I915_GEM_DOMAIN_RENDER | \
	 I915_GEM_DOMAIN_SAMPLER | \
	 I915_GEM_DOMAIN_COMMAND | \
	 I915_GEM_DOMAIN_INSTRUCTION | \
	 I915_GEM_DOMAIN_VERTEX)
339

340 341
#define for_each_pipe(__dev_priv, __p) \
	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
342 343 344
#define for_each_pipe_masked(__dev_priv, __p, __mask) \
	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
		for_each_if ((__mask) & (1 << (__p)))
345
#define for_each_universal_plane(__dev_priv, __pipe, __p)		\
346 347 348
	for ((__p) = 0;							\
	     (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1;	\
	     (__p)++)
349 350 351 352
#define for_each_sprite(__dev_priv, __p, __s)				\
	for ((__s) = 0;							\
	     (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)];	\
	     (__s)++)
353

354 355 356 357
#define for_each_port_masked(__port, __ports_mask) \
	for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)	\
		for_each_if ((__ports_mask) & (1 << (__port)))

358
#define for_each_crtc(dev, crtc) \
359
	list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
360

361 362
#define for_each_intel_plane(dev, intel_plane) \
	list_for_each_entry(intel_plane,			\
363
			    &(dev)->mode_config.plane_list,	\
364 365
			    base.head)

366
#define for_each_intel_plane_mask(dev, intel_plane, plane_mask)		\
367 368
	list_for_each_entry(intel_plane,				\
			    &(dev)->mode_config.plane_list,		\
369 370 371 372
			    base.head)					\
		for_each_if ((plane_mask) &				\
			     (1 << drm_plane_index(&intel_plane->base)))

373 374 375 376
#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)	\
	list_for_each_entry(intel_plane,				\
			    &(dev)->mode_config.plane_list,		\
			    base.head)					\
377
		for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
378

379 380 381 382
#define for_each_intel_crtc(dev, intel_crtc)				\
	list_for_each_entry(intel_crtc,					\
			    &(dev)->mode_config.crtc_list,		\
			    base.head)
383

384 385 386 387
#define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask)		\
	list_for_each_entry(intel_crtc,					\
			    &(dev)->mode_config.crtc_list,		\
			    base.head)					\
388 389
		for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))

390 391 392 393 394
#define for_each_intel_encoder(dev, intel_encoder)		\
	list_for_each_entry(intel_encoder,			\
			    &(dev)->mode_config.encoder_list,	\
			    base.head)

395 396
#define for_each_intel_connector(dev, intel_connector)		\
	list_for_each_entry(intel_connector,			\
397
			    &(dev)->mode_config.connector_list,	\
398 399
			    base.head)

400 401
#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
402
		for_each_if ((intel_encoder)->base.crtc == (__crtc))
403

404 405
#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
	list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
406
		for_each_if ((intel_connector)->base.encoder == (__encoder))
407

408 409
#define for_each_power_domain(domain, mask)				\
	for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)	\
410
		for_each_if ((1 << (domain)) & (mask))
411

412
struct drm_i915_private;
413
struct i915_mm_struct;
414
struct i915_mmu_object;
415

416 417 418 419 420 421 422
struct drm_i915_file_private {
	struct drm_i915_private *dev_priv;
	struct drm_file *file;

	struct {
		spinlock_t lock;
		struct list_head request_list;
423 424 425 426 427 428
/* 20ms is a fairly arbitrary limit (greater than the average frame time)
 * chosen to prevent the CPU getting more than a frame ahead of the GPU
 * (when using lax throttling for the frontbuffer). We also use it to
 * offer free GPU waitboosts for severely congested workloads.
 */
#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
429 430 431
	} mm;
	struct idr context_idr;

432 433 434 435
	struct intel_rps_client {
		struct list_head link;
		unsigned boosts;
	} rps;
436

437
	unsigned int bsd_engine;
438 439 440 441 442 443 444 445 446

/* Client can have a maximum of 3 contexts banned before
 * it is denied of creating new contexts. As one context
 * ban needs 4 consecutive hangs, and more if there is
 * progress in between, this is a last resort stop gap measure
 * to limit the badly behaving clients access to gpu.
 */
#define I915_MAX_CLIENT_CONTEXT_BANS 3
	int context_bans;
447 448
};

449 450 451 452 453 454 455 456 457 458 459 460 461
/* Used by dp and fdi links */
struct intel_link_m_n {
	uint32_t	tu;
	uint32_t	gmch_m;
	uint32_t	gmch_n;
	uint32_t	link_m;
	uint32_t	link_n;
};

void intel_link_compute_m_n(int bpp, int nlanes,
			    int pixel_clock, int link_clock,
			    struct intel_link_m_n *m_n);

L
Linus Torvalds 已提交
462 463 464
/* Interface history:
 *
 * 1.1: Original.
D
Dave Airlie 已提交
465 466
 * 1.2: Add Power Management
 * 1.3: Add vblank support
467
 * 1.4: Fix cmdbuffer path, add heap destroy
468
 * 1.5: Add vblank pipe configuration
=
=?utf-8?q?Michel_D=C3=A4nzer?= 已提交
469 470
 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 *      - Support vertical blank on secondary display pipe
L
Linus Torvalds 已提交
471 472
 */
#define DRIVER_MAJOR		1
=
=?utf-8?q?Michel_D=C3=A4nzer?= 已提交
473
#define DRIVER_MINOR		6
L
Linus Torvalds 已提交
474 475
#define DRIVER_PATCHLEVEL	0

476 477 478 479 480
struct opregion_header;
struct opregion_acpi;
struct opregion_swsci;
struct opregion_asle;

481
struct intel_opregion {
482 483 484
	struct opregion_header *header;
	struct opregion_acpi *acpi;
	struct opregion_swsci *swsci;
J
Jani Nikula 已提交
485 486
	u32 swsci_gbda_sub_functions;
	u32 swsci_sbcb_sub_functions;
487
	struct opregion_asle *asle;
488
	void *rvda;
489
	const void *vbt;
490
	u32 vbt_size;
491
	u32 *lid_state;
492
	struct work_struct asle_work;
493
};
494
#define OPREGION_SIZE            (8*1024)
495

496 497 498
struct intel_overlay;
struct intel_overlay_error_state;

499
struct sdvo_device_mapping {
C
Chris Wilson 已提交
500
	u8 initialized;
501 502 503
	u8 dvo_port;
	u8 slave_addr;
	u8 dvo_wiring;
C
Chris Wilson 已提交
504
	u8 i2c_pin;
505
	u8 ddc_pin;
506 507
};

508
struct intel_connector;
509
struct intel_encoder;
510
struct intel_atomic_state;
511
struct intel_crtc_state;
512
struct intel_initial_plane_config;
513
struct intel_crtc;
514 515
struct intel_limit;
struct dpll;
516

517
struct drm_i915_display_funcs {
518
	int (*get_display_clock_speed)(struct drm_i915_private *dev_priv);
519
	int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane);
520
	int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
521 522 523
	int (*compute_intermediate_wm)(struct drm_device *dev,
				       struct intel_crtc *intel_crtc,
				       struct intel_crtc_state *newstate);
524 525 526 527 528 529
	void (*initial_watermarks)(struct intel_atomic_state *state,
				   struct intel_crtc_state *cstate);
	void (*atomic_update_watermarks)(struct intel_atomic_state *state,
					 struct intel_crtc_state *cstate);
	void (*optimize_watermarks)(struct intel_atomic_state *state,
				    struct intel_crtc_state *cstate);
530
	int (*compute_global_watermarks)(struct drm_atomic_state *state);
531
	void (*update_wm)(struct intel_crtc *crtc);
532 533
	int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
	void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
534 535 536
	/* Returns the active state of the crtc, and if the crtc is active,
	 * fills out the pipe-config with the hw state. */
	bool (*get_pipe_config)(struct intel_crtc *,
537
				struct intel_crtc_state *);
538 539
	void (*get_initial_plane_config)(struct intel_crtc *,
					 struct intel_initial_plane_config *);
540 541
	int (*crtc_compute_clock)(struct intel_crtc *crtc,
				  struct intel_crtc_state *crtc_state);
542 543 544 545
	void (*crtc_enable)(struct intel_crtc_state *pipe_config,
			    struct drm_atomic_state *old_state);
	void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
			     struct drm_atomic_state *old_state);
546 547
	void (*update_crtcs)(struct drm_atomic_state *state,
			     unsigned int *crtc_vblank_mask);
548 549
	void (*audio_codec_enable)(struct drm_connector *connector,
				   struct intel_encoder *encoder,
550
				   const struct drm_display_mode *adjusted_mode);
551
	void (*audio_codec_disable)(struct intel_encoder *encoder);
552
	void (*fdi_link_train)(struct drm_crtc *crtc);
553
	void (*init_clock_gating)(struct drm_i915_private *dev_priv);
554 555 556 557 558
	int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
			  struct drm_framebuffer *fb,
			  struct drm_i915_gem_object *obj,
			  struct drm_i915_gem_request *req,
			  uint32_t flags);
559
	void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
560 561 562 563 564
	/* clock updates for mode set */
	/* cursor updates */
	/* render clock increase/decrease */
	/* display clock increase/decrease */
	/* pll clock increase/decrease */
565

566 567
	void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
	void (*load_luts)(struct drm_crtc_state *crtc_state);
568 569
};

570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586
enum forcewake_domain_id {
	FW_DOMAIN_ID_RENDER = 0,
	FW_DOMAIN_ID_BLITTER,
	FW_DOMAIN_ID_MEDIA,

	FW_DOMAIN_ID_COUNT
};

enum forcewake_domains {
	FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
	FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
	FORCEWAKE_MEDIA	= (1 << FW_DOMAIN_ID_MEDIA),
	FORCEWAKE_ALL = (FORCEWAKE_RENDER |
			 FORCEWAKE_BLITTER |
			 FORCEWAKE_MEDIA)
};

587 588 589
#define FW_REG_READ  (1)
#define FW_REG_WRITE (2)

590 591 592 593 594 595 596 597 598 599 600 601
enum decoupled_power_domain {
	GEN9_DECOUPLED_PD_BLITTER = 0,
	GEN9_DECOUPLED_PD_RENDER,
	GEN9_DECOUPLED_PD_MEDIA,
	GEN9_DECOUPLED_PD_ALL
};

enum decoupled_ops {
	GEN9_DECOUPLED_OP_WRITE = 0,
	GEN9_DECOUPLED_OP_READ
};

602 603 604 605
enum forcewake_domains
intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
			       i915_reg_t reg, unsigned int op);

606
struct intel_uncore_funcs {
607
	void (*force_wake_get)(struct drm_i915_private *dev_priv,
608
							enum forcewake_domains domains);
609
	void (*force_wake_put)(struct drm_i915_private *dev_priv,
610
							enum forcewake_domains domains);
611

612 613 614 615
	uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
	uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
	uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
	uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
616

617
	void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
618
				uint8_t val, bool trace);
619
	void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
620
				uint16_t val, bool trace);
621
	void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
622
				uint32_t val, bool trace);
623 624
};

625 626 627 628 629 630 631
struct intel_forcewake_range {
	u32 start;
	u32 end;

	enum forcewake_domains domains;
};

632 633 634
struct intel_uncore {
	spinlock_t lock; /** lock is also taken in irq contexts. */

635 636 637
	const struct intel_forcewake_range *fw_domains_table;
	unsigned int fw_domains_table_entries;

638 639 640
	struct intel_uncore_funcs funcs;

	unsigned fifo_count;
641

642
	enum forcewake_domains fw_domains;
643
	enum forcewake_domains fw_domains_active;
644 645 646

	struct intel_uncore_forcewake_domain {
		struct drm_i915_private *i915;
647
		enum forcewake_domain_id id;
648
		enum forcewake_domains mask;
649
		unsigned wake_count;
650
		struct hrtimer timer;
651
		i915_reg_t reg_set;
652 653
		u32 val_set;
		u32 val_clear;
654 655
		i915_reg_t reg_ack;
		i915_reg_t reg_post;
656
		u32 val_reset;
657
	} fw_domain[FW_DOMAIN_ID_COUNT];
658 659

	int unclaimed_mmio_check;
660 661 662
};

/* Iterate over initialised fw domains */
663 664 665 666 667 668 669 670
#define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
	for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
	     (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
	     (domain__)++) \
		for_each_if ((mask__) & (domain__)->mask)

#define for_each_fw_domain(domain__, dev_priv__) \
	for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
671

672 673 674 675
#define CSR_VERSION(major, minor)	((major) << 16 | (minor))
#define CSR_VERSION_MAJOR(version)	((version) >> 16)
#define CSR_VERSION_MINOR(version)	((version) & 0xffff)

676
struct intel_csr {
677
	struct work_struct work;
678
	const char *fw_path;
679
	uint32_t *dmc_payload;
680
	uint32_t dmc_fw_size;
681
	uint32_t version;
682
	uint32_t mmio_count;
683
	i915_reg_t mmioaddr[8];
684
	uint32_t mmiodata[8];
685
	uint32_t dc_state;
686
	uint32_t allowed_dc_mask;
687 688
};

689 690 691
#define DEV_INFO_FOR_EACH_FLAG(func) \
	func(is_mobile); \
	func(is_pineview); \
692
	func(is_lp); \
693
	func(is_alpha_support); \
694
	/* Keep has_* in alphabetical order */ \
695
	func(has_64bit_reloc); \
696
	func(has_aliasing_ppgtt); \
697
	func(has_csr); \
698
	func(has_ddi); \
699
	func(has_decoupled_mmio); \
700
	func(has_dp_mst); \
701 702
	func(has_fbc); \
	func(has_fpga_dbg); \
703 704
	func(has_full_ppgtt); \
	func(has_full_48bit_ppgtt); \
705 706 707 708
	func(has_gmbus_irq); \
	func(has_gmch_display); \
	func(has_guc); \
	func(has_hotplug); \
709 710
	func(has_hw_contexts); \
	func(has_l3_dpf); \
711
	func(has_llc); \
712 713 714 715 716 717 718 719 720
	func(has_logical_ring_contexts); \
	func(has_overlay); \
	func(has_pipe_cxsr); \
	func(has_pooled_eu); \
	func(has_psr); \
	func(has_rc6); \
	func(has_rc6p); \
	func(has_resource_streamer); \
	func(has_runtime_pm); \
721
	func(has_snoop); \
722 723 724
	func(cursor_needs_physical); \
	func(hws_needs_physical); \
	func(overlay_needs_physical); \
725
	func(supports_tv);
D
Daniel Vetter 已提交
726

727
struct sseu_dev_info {
728
	u8 slice_mask;
729
	u8 subslice_mask;
730 731
	u8 eu_total;
	u8 eu_per_subslice;
732 733 734 735 736 737
	u8 min_eu_in_pool;
	/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
	u8 subslice_7eu[3];
	u8 has_slice_pg:1;
	u8 has_subslice_pg:1;
	u8 has_eu_pg:1;
738 739
};

740 741 742 743 744
static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
{
	return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
}

745 746 747 748 749 750 751 752 753 754 755 756 757
/* Keep in gen based order, and chronological order within a gen */
enum intel_platform {
	INTEL_PLATFORM_UNINITIALIZED = 0,
	INTEL_I830,
	INTEL_I845G,
	INTEL_I85X,
	INTEL_I865G,
	INTEL_I915G,
	INTEL_I915GM,
	INTEL_I945G,
	INTEL_I945GM,
	INTEL_G33,
	INTEL_PINEVIEW,
758 759
	INTEL_I965G,
	INTEL_I965GM,
760 761
	INTEL_G45,
	INTEL_GM45,
762 763 764 765 766 767 768 769 770 771 772 773 774
	INTEL_IRONLAKE,
	INTEL_SANDYBRIDGE,
	INTEL_IVYBRIDGE,
	INTEL_VALLEYVIEW,
	INTEL_HASWELL,
	INTEL_BROADWELL,
	INTEL_CHERRYVIEW,
	INTEL_SKYLAKE,
	INTEL_BROXTON,
	INTEL_KABYLAKE,
	INTEL_GEMINILAKE,
};

775
struct intel_device_info {
776
	u32 display_mmio_offset;
777
	u16 device_id;
778
	u8 num_pipes;
779
	u8 num_sprites[I915_MAX_PIPES];
780
	u8 gen;
781
	u16 gen_mask;
782
	enum intel_platform platform;
783
	u8 ring_mask; /* Rings supported by the HW */
784
	u8 num_rings;
785 786 787
#define DEFINE_FLAG(name) u8 name:1
	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
#undef DEFINE_FLAG
788
	u16 ddb_size; /* in blocks */
789 790 791 792
	/* Register offsets for the various display pipes and transcoders */
	int pipe_offsets[I915_MAX_TRANSCODERS];
	int trans_offsets[I915_MAX_TRANSCODERS];
	int palette_offsets[I915_MAX_PIPES];
793
	int cursor_offsets[I915_MAX_PIPES];
794 795

	/* Slice/subslice/EU info */
796
	struct sseu_dev_info sseu;
797 798 799 800 801

	struct color_luts {
		u16 degamma_lut_size;
		u16 gamma_lut_size;
	} color;
802 803
};

804 805 806 807 808
struct intel_display_error_state;

struct drm_i915_error_state {
	struct kref ref;
	struct timeval time;
809 810
	struct timeval boottime;
	struct timeval uptime;
811

812 813
	struct drm_i915_private *i915;

814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837
	char error_msg[128];
	bool simulated;
	int iommu;
	u32 reset_count;
	u32 suspend_count;
	struct intel_device_info device_info;

	/* Generic register state */
	u32 eir;
	u32 pgtbl_er;
	u32 ier;
	u32 gtier[4];
	u32 ccid;
	u32 derrmr;
	u32 forcewake;
	u32 error; /* gen6+ */
	u32 err_int; /* gen7 */
	u32 fault_data0; /* gen8, gen9 */
	u32 fault_data1; /* gen8, gen9 */
	u32 done_reg;
	u32 gac_eco;
	u32 gam_ecochk;
	u32 gab_ctl;
	u32 gfx_mode;
838

839 840 841
	u64 fence[I915_MAX_NUM_FENCES];
	struct intel_overlay_error_state *overlay;
	struct intel_display_error_state *display;
842
	struct drm_i915_error_object *semaphore;
843
	struct drm_i915_error_object *guc_log;
844 845 846 847 848 849

	struct drm_i915_error_engine {
		int engine_id;
		/* Software tracked state */
		bool waiting;
		int num_waiters;
850 851
		unsigned long hangcheck_timestamp;
		bool hangcheck_stalled;
852 853 854 855
		enum intel_engine_hangcheck_action hangcheck_action;
		struct i915_address_space *vm;
		int num_requests;

856 857 858
		/* position of active request inside the ring */
		u32 rq_head, rq_post, rq_tail;

859 860 861 862 863 864 865 866 867 868 869
		/* our own tracking of ring head and tail */
		u32 cpu_ring_head;
		u32 cpu_ring_tail;

		u32 last_seqno;

		/* Register state */
		u32 start;
		u32 tail;
		u32 head;
		u32 ctl;
870
		u32 mode;
871 872 873 874 875 876 877 878 879 880 881 882 883
		u32 hws;
		u32 ipeir;
		u32 ipehr;
		u32 bbstate;
		u32 instpm;
		u32 instps;
		u32 seqno;
		u64 bbaddr;
		u64 acthd;
		u32 fault_reg;
		u64 faddr;
		u32 rc_psmi; /* sleep state */
		u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
884
		struct intel_instdone instdone;
885 886 887

		struct drm_i915_error_object {
			u64 gtt_offset;
888
			u64 gtt_size;
889 890
			int page_count;
			int unused;
891 892 893 894 895 896 897
			u32 *pages[0];
		} *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;

		struct drm_i915_error_object *wa_ctx;

		struct drm_i915_error_request {
			long jiffies;
898
			pid_t pid;
899
			u32 context;
900
			int ban_score;
901 902 903
			u32 seqno;
			u32 head;
			u32 tail;
904
		} *requests, execlist[2];
905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921

		struct drm_i915_error_waiter {
			char comm[TASK_COMM_LEN];
			pid_t pid;
			u32 seqno;
		} *waiters;

		struct {
			u32 gfx_mode;
			union {
				u64 pdp[4];
				u32 pp_dir_base;
			};
		} vm_info;

		pid_t pid;
		char comm[TASK_COMM_LEN];
922
		int context_bans;
923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943
	} engine[I915_NUM_ENGINES];

	struct drm_i915_error_buffer {
		u32 size;
		u32 name;
		u32 rseqno[I915_NUM_ENGINES], wseqno;
		u64 gtt_offset;
		u32 read_domains;
		u32 write_domain;
		s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
		u32 tiling:2;
		u32 dirty:1;
		u32 purgeable:1;
		u32 userptr:1;
		s32 engine:4;
		u32 cache_level:3;
	} *active_bo[I915_NUM_ENGINES], *pinned_bo;
	u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
	struct i915_address_space *active_vm[I915_NUM_ENGINES];
};

944 945
enum i915_cache_level {
	I915_CACHE_NONE = 0,
946 947 948 949 950
	I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
	I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
			      caches, eg sampler/render caches, and the
			      large Last-Level-Cache. LLC is coherent with
			      the CPU, but L3 is only visible to the GPU. */
951
	I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
952 953
};

954 955
#define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */

956
#define DEFAULT_CONTEXT_HANDLE 0
957

958
/**
959
 * struct i915_gem_context - as the name implies, represents a context.
960 961 962
 * @ref: reference count.
 * @user_handle: userspace tracking identity for this context.
 * @remap_slice: l3 row remapping information.
963 964
 * @flags: context specific flags:
 *         CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
965 966 967 968
 * @file_priv: filp associated with this context (NULL for global default
 *	       context).
 * @hang_stats: information about the role of this context in possible GPU
 *		hangs.
969
 * @ppgtt: virtual memory space used by this context.
970 971 972 973 974 975 976
 * @legacy_hw_ctx: render context backing object and whether it is correctly
 *                initialized (legacy ring submission mechanism only).
 * @link: link in the global list of contexts.
 *
 * Contexts are memory images used by the hardware to store copies of their
 * internal state.
 */
977
struct i915_gem_context {
978
	struct kref ref;
979
	struct drm_i915_private *i915;
980
	struct drm_i915_file_private *file_priv;
981
	struct i915_hw_ppgtt *ppgtt;
982
	struct pid *pid;
983
	const char *name;
984

985
	unsigned long flags;
986 987
#define CONTEXT_NO_ZEROMAP		BIT(0)
#define CONTEXT_NO_ERROR_CAPTURE	BIT(1)
988 989 990

	/* Unique identifier for this context, used by the hw for tracking */
	unsigned int hw_id;
991
	u32 user_handle;
992
	int priority; /* greater priorities are serviced first */
993

994 995
	u32 ggtt_alignment;

996
	struct intel_context {
997
		struct i915_vma *state;
998
		struct intel_ring *ring;
999
		uint32_t *lrc_reg_state;
1000 1001
		u64 lrc_desc;
		int pin_count;
1002
		bool initialised;
1003
	} engine[I915_NUM_ENGINES];
1004
	u32 ring_size;
1005
	u32 desc_template;
1006
	struct atomic_notifier_head status_notifier;
1007
	bool execlists_force_single_submission;
1008

1009
	struct list_head link;
1010 1011

	u8 remap_slice;
1012
	bool closed:1;
1013 1014 1015 1016 1017 1018 1019 1020 1021 1022
	bool bannable:1;
	bool banned:1;

	unsigned int guilty_count; /* guilty of a hang */
	unsigned int active_count; /* active during hang */

#define CONTEXT_SCORE_GUILTY		10
#define CONTEXT_SCORE_BAN_THRESHOLD	40
	/* Accumulated score of hangs caused by this context */
	int ban_score;
1023 1024
};

1025 1026 1027 1028 1029
enum fb_op_origin {
	ORIGIN_GTT,
	ORIGIN_CPU,
	ORIGIN_CS,
	ORIGIN_FLIP,
1030
	ORIGIN_DIRTYFB,
1031 1032
};

1033
struct intel_fbc {
P
Paulo Zanoni 已提交
1034 1035 1036
	/* This is always the inner lock when overlapping with struct_mutex and
	 * it's the outer lock when overlapping with stolen_lock. */
	struct mutex lock;
B
Ben Widawsky 已提交
1037
	unsigned threshold;
1038 1039
	unsigned int possible_framebuffer_bits;
	unsigned int busy_bits;
1040
	unsigned int visible_pipes_mask;
1041
	struct intel_crtc *crtc;
1042

1043
	struct drm_mm_node compressed_fb;
1044 1045
	struct drm_mm_node *compressed_llb;

1046 1047
	bool false_color;

1048
	bool enabled;
1049
	bool active;
1050

1051 1052 1053
	bool underrun_detected;
	struct work_struct underrun_work;

1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075
	struct intel_fbc_state_cache {
		struct {
			unsigned int mode_flags;
			uint32_t hsw_bdw_pixel_rate;
		} crtc;

		struct {
			unsigned int rotation;
			int src_w;
			int src_h;
			bool visible;
		} plane;

		struct {
			u64 ilk_ggtt_offset;
			uint32_t pixel_format;
			unsigned int stride;
			int fence_reg;
			unsigned int tiling_mode;
		} fb;
	} state_cache;

1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092
	struct intel_fbc_reg_params {
		struct {
			enum pipe pipe;
			enum plane plane;
			unsigned int fence_y_offset;
		} crtc;

		struct {
			u64 ggtt_offset;
			uint32_t pixel_format;
			unsigned int stride;
			int fence_reg;
		} fb;

		int cfb_size;
	} params;

1093
	struct intel_fbc_work {
1094
		bool scheduled;
1095
		u32 scheduled_vblank;
1096 1097
		struct work_struct work;
	} work;
1098

1099
	const char *no_fbc_reason;
1100 1101
};

1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116
/**
 * HIGH_RR is the highest eDP panel refresh rate read from EDID
 * LOW_RR is the lowest eDP panel refresh rate found from EDID
 * parsing for same resolution.
 */
enum drrs_refresh_rate_type {
	DRRS_HIGH_RR,
	DRRS_LOW_RR,
	DRRS_MAX_RR, /* RR count */
};

enum drrs_support_type {
	DRRS_NOT_SUPPORTED = 0,
	STATIC_DRRS_SUPPORT = 1,
	SEAMLESS_DRRS_SUPPORT = 2
1117 1118
};

1119
struct intel_dp;
1120 1121 1122 1123 1124 1125 1126 1127 1128
struct i915_drrs {
	struct mutex mutex;
	struct delayed_work work;
	struct intel_dp *dp;
	unsigned busy_frontbuffer_bits;
	enum drrs_refresh_rate_type refresh_rate_type;
	enum drrs_support_type type;
};

R
Rodrigo Vivi 已提交
1129
struct i915_psr {
1130
	struct mutex lock;
R
Rodrigo Vivi 已提交
1131 1132
	bool sink_support;
	bool source_ok;
1133
	struct intel_dp *enabled;
1134 1135
	bool active;
	struct delayed_work work;
1136
	unsigned busy_frontbuffer_bits;
1137 1138
	bool psr2_support;
	bool aux_frame_sync;
1139
	bool link_standby;
1140
};
1141

1142
enum intel_pch {
1143
	PCH_NONE = 0,	/* No PCH present */
1144 1145
	PCH_IBX,	/* Ibexpeak PCH */
	PCH_CPT,	/* Cougarpoint PCH */
1146
	PCH_LPT,	/* Lynxpoint PCH */
1147
	PCH_SPT,        /* Sunrisepoint PCH */
1148
	PCH_KBP,        /* Kabypoint PCH */
B
Ben Widawsky 已提交
1149
	PCH_NOP,
1150 1151
};

1152 1153 1154 1155 1156
enum intel_sbi_destination {
	SBI_ICLK,
	SBI_MPHY,
};

1157
#define QUIRK_PIPEA_FORCE (1<<0)
1158
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
1159
#define QUIRK_INVERT_BRIGHTNESS (1<<2)
1160
#define QUIRK_BACKLIGHT_PRESENT (1<<3)
1161
#define QUIRK_PIPEB_FORCE (1<<4)
1162
#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1163

1164
struct intel_fbdev;
1165
struct intel_fbc_work;
1166

1167 1168
struct intel_gmbus {
	struct i2c_adapter adapter;
1169
#define GMBUS_FORCE_BIT_RETRY (1U << 31)
1170
	u32 force_bit;
1171
	u32 reg0;
1172
	i915_reg_t gpio_reg;
1173
	struct i2c_algo_bit_data bit_algo;
1174 1175 1176
	struct drm_i915_private *dev_priv;
};

1177
struct i915_suspend_saved_registers {
1178
	u32 saveDSPARB;
J
Jesse Barnes 已提交
1179
	u32 saveFBC_CONTROL;
1180 1181
	u32 saveCACHE_MODE_0;
	u32 saveMI_ARB_STATE;
J
Jesse Barnes 已提交
1182 1183
	u32 saveSWF0[16];
	u32 saveSWF1[16];
1184
	u32 saveSWF3[3];
1185
	uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1186
	u32 savePCH_PORT_HOTPLUG;
1187
	u16 saveGCDGMBUS;
1188
};
1189

1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247
struct vlv_s0ix_state {
	/* GAM */
	u32 wr_watermark;
	u32 gfx_prio_ctrl;
	u32 arb_mode;
	u32 gfx_pend_tlb0;
	u32 gfx_pend_tlb1;
	u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
	u32 media_max_req_count;
	u32 gfx_max_req_count;
	u32 render_hwsp;
	u32 ecochk;
	u32 bsd_hwsp;
	u32 blt_hwsp;
	u32 tlb_rd_addr;

	/* MBC */
	u32 g3dctl;
	u32 gsckgctl;
	u32 mbctl;

	/* GCP */
	u32 ucgctl1;
	u32 ucgctl3;
	u32 rcgctl1;
	u32 rcgctl2;
	u32 rstctl;
	u32 misccpctl;

	/* GPM */
	u32 gfxpause;
	u32 rpdeuhwtc;
	u32 rpdeuc;
	u32 ecobus;
	u32 pwrdwnupctl;
	u32 rp_down_timeout;
	u32 rp_deucsw;
	u32 rcubmabdtmr;
	u32 rcedata;
	u32 spare2gh;

	/* Display 1 CZ domain */
	u32 gt_imr;
	u32 gt_ier;
	u32 pm_imr;
	u32 pm_ier;
	u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];

	/* GT SA CZ domain */
	u32 tilectl;
	u32 gt_fifoctl;
	u32 gtlc_wake_ctrl;
	u32 gtlc_survive;
	u32 pmwgicz;

	/* Display 2 CZ domain */
	u32 gu_ctl0;
	u32 gu_ctl1;
1248
	u32 pcbr;
1249 1250 1251
	u32 clock_gate_dis2;
};

1252 1253 1254 1255
struct intel_rps_ei {
	u32 cz_clock;
	u32 render_c0;
	u32 media_c0;
1256 1257
};

1258
struct intel_gen6_power_mgmt {
I
Imre Deak 已提交
1259 1260 1261 1262
	/*
	 * work, interrupts_enabled and pm_iir are protected by
	 * dev_priv->irq_lock
	 */
1263
	struct work_struct work;
I
Imre Deak 已提交
1264
	bool interrupts_enabled;
1265
	u32 pm_iir;
1266

1267
	/* PM interrupt bits that should never be masked */
1268 1269
	u32 pm_intr_keep;

1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284
	/* Frequencies are stored in potentially platform dependent multiples.
	 * In other words, *_freq needs to be multiplied by X to be interesting.
	 * Soft limits are those which are used for the dynamic reclocking done
	 * by the driver (raise frequencies under heavy loads, and lower for
	 * lighter loads). Hard limits are those imposed by the hardware.
	 *
	 * A distinction is made for overclocking, which is never enabled by
	 * default, and is considered to be above the hard limit if it's
	 * possible at all.
	 */
	u8 cur_freq;		/* Current frequency (cached, may not == HW) */
	u8 min_freq_softlimit;	/* Minimum frequency permitted by the driver */
	u8 max_freq_softlimit;	/* Max frequency permitted by the driver */
	u8 max_freq;		/* Maximum frequency, RP0 if not overclocking */
	u8 min_freq;		/* AKA RPn. Minimum frequency */
1285
	u8 boost_freq;		/* Frequency to request when wait boosting */
1286
	u8 idle_freq;		/* Frequency to request when we are idle */
1287 1288 1289
	u8 efficient_freq;	/* AKA RPe. Pre-determined balanced frequency */
	u8 rp1_freq;		/* "less than" RP0 power/freqency */
	u8 rp0_freq;		/* Non-overclocked max frequency. */
1290
	u16 gpll_ref_freq;	/* vlv/chv GPLL reference frequency */
1291

1292 1293 1294
	u8 up_threshold; /* Current %busy required to uplock */
	u8 down_threshold; /* Current %busy required to downclock */

1295 1296 1297
	int last_adj;
	enum { LOW_POWER, BETWEEN, HIGH_POWER } power;

1298 1299 1300 1301
	spinlock_t client_lock;
	struct list_head clients;
	bool client_boost;

1302
	bool enabled;
1303
	struct delayed_work autoenable_work;
1304
	unsigned boosts;
1305

1306 1307 1308
	/* manual wa residency calculations */
	struct intel_rps_ei up_ei, down_ei;

1309 1310
	/*
	 * Protects RPS/RC6 register access and PCU communication.
1311 1312 1313
	 * Must be taken after struct_mutex if nested. Note that
	 * this lock may be held for long periods of time when
	 * talking to hw - so only take it when talking to hw!
1314 1315
	 */
	struct mutex hw_lock;
1316 1317
};

D
Daniel Vetter 已提交
1318 1319 1320
/* defined intel_pm.c */
extern spinlock_t mchdev_lock;

1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331
struct intel_ilk_power_mgmt {
	u8 cur_delay;
	u8 min_delay;
	u8 max_delay;
	u8 fmax;
	u8 fstart;

	u64 last_count1;
	unsigned long last_time1;
	unsigned long chipset_power;
	u64 last_count2;
1332
	u64 last_time2;
1333 1334 1335 1336 1337 1338 1339
	unsigned long gfx_power;
	u8 corr;

	int c_m;
	int r_t;
};

1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369
struct drm_i915_private;
struct i915_power_well;

struct i915_power_well_ops {
	/*
	 * Synchronize the well's hw state to match the current sw state, for
	 * example enable/disable it based on the current refcount. Called
	 * during driver init and resume time, possibly after first calling
	 * the enable/disable handlers.
	 */
	void (*sync_hw)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/*
	 * Enable the well and resources that depend on it (for example
	 * interrupts located on the well). Called after the 0->1 refcount
	 * transition.
	 */
	void (*enable)(struct drm_i915_private *dev_priv,
		       struct i915_power_well *power_well);
	/*
	 * Disable the well and resources that depend on it. Called after
	 * the 1->0 refcount transition.
	 */
	void (*disable)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/* Returns the hw enabled state. */
	bool (*is_enabled)(struct drm_i915_private *dev_priv,
			   struct i915_power_well *power_well);
};

1370 1371
/* Power well structure for haswell */
struct i915_power_well {
1372
	const char *name;
1373
	bool always_on;
1374 1375
	/* power well enable/disable usage count */
	int count;
1376 1377
	/* cached hw enabled state */
	bool hw_enabled;
1378
	unsigned long domains;
1379 1380
	/* unique identifier for this power well */
	unsigned long id;
1381 1382 1383 1384 1385
	/*
	 * Arbitraty data associated with this power well. Platform and power
	 * well specific.
	 */
	unsigned long data;
1386
	const struct i915_power_well_ops *ops;
1387 1388
};

1389
struct i915_power_domains {
1390 1391 1392 1393 1394
	/*
	 * Power wells needed for initialization at driver init and suspend
	 * time are on. They are kept on until after the first modeset.
	 */
	bool init_power_on;
1395
	bool initializing;
1396
	int power_well_count;
1397

1398
	struct mutex lock;
1399
	int domain_use_count[POWER_DOMAIN_NUM];
1400
	struct i915_power_well *power_wells;
1401 1402
};

1403
#define MAX_L3_SLICES 2
1404
struct intel_l3_parity {
1405
	u32 *remap_info[MAX_L3_SLICES];
1406
	struct work_struct error_work;
1407
	int which_slice;
1408 1409
};

1410 1411 1412
struct i915_gem_mm {
	/** Memory allocator for GTT stolen memory */
	struct drm_mm stolen;
1413 1414 1415 1416
	/** Protects the usage of the GTT stolen memory allocator. This is
	 * always the inner lock when overlapping with struct_mutex. */
	struct mutex stolen_lock;

1417 1418 1419 1420 1421
	/** List of all objects in gtt_space. Used to restore gtt
	 * mappings on resume */
	struct list_head bound_list;
	/**
	 * List of objects which are not bound to the GTT (thus
1422 1423
	 * are idle and not used by the GPU). These objects may or may
	 * not actually have any pages attached.
1424 1425 1426
	 */
	struct list_head unbound_list;

1427 1428 1429 1430 1431
	/** List of all objects in gtt_space, currently mmaped by userspace.
	 * All objects within this list must also be on bound_list.
	 */
	struct list_head userfault_list;

1432 1433 1434 1435 1436 1437
	/**
	 * List of objects which are pending destruction.
	 */
	struct llist_head free_list;
	struct work_struct free_work;

1438 1439 1440 1441 1442 1443
	/** Usable portion of the GTT for GEM */
	unsigned long stolen_base; /* limited to low memory (32-bit) */

	/** PPGTT used for aliasing the PPGTT with the GTT */
	struct i915_hw_ppgtt *aliasing_ppgtt;

1444
	struct notifier_block oom_notifier;
1445
	struct notifier_block vmap_notifier;
1446
	struct shrinker shrinker;
1447 1448 1449 1450 1451 1452 1453 1454 1455 1456

	/** LRU list of objects with fence regs on them. */
	struct list_head fence_list;

	/**
	 * Are we in a non-interruptible section of code like
	 * modesetting?
	 */
	bool interruptible;

1457
	/* the indicator for dispatch video commands on two BSD rings */
1458
	atomic_t bsd_engine_dispatch_index;
1459

1460 1461 1462 1463 1464 1465
	/** Bit 6 swizzling required for X tiling */
	uint32_t bit_6_swizzle_x;
	/** Bit 6 swizzling required for Y tiling */
	uint32_t bit_6_swizzle_y;

	/* accounting, useful for userland debugging */
1466
	spinlock_t object_stat_lock;
1467
	u64 object_memory;
1468 1469 1470
	u32 object_count;
};

1471
struct drm_i915_error_state_buf {
1472
	struct drm_i915_private *i915;
1473 1474 1475 1476 1477 1478 1479 1480
	unsigned bytes;
	unsigned size;
	int err;
	u8 *buf;
	loff_t start;
	loff_t pos;
};

1481
struct i915_error_state_file_priv {
1482
	struct drm_i915_private *i915;
1483 1484 1485
	struct drm_i915_error_state *error;
};

1486 1487 1488
#define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
#define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */

1489 1490 1491
#define I915_ENGINE_DEAD_TIMEOUT  (4 * HZ)  /* Seqno, head and subunits dead */
#define I915_SEQNO_DEAD_TIMEOUT   (12 * HZ) /* Seqno dead with active head */

1492 1493 1494 1495
struct i915_gpu_error {
	/* For hangcheck timer */
#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1496

1497
	struct delayed_work hangcheck_work;
1498 1499 1500 1501 1502

	/* For reset and error_state handling. */
	spinlock_t lock;
	/* Protected by the above dev->gpu_error.lock. */
	struct drm_i915_error_state *first_error;
1503 1504 1505

	unsigned long missed_irq_rings;

1506
	/**
M
Mika Kuoppala 已提交
1507
	 * State variable controlling the reset flow and count
1508
	 *
M
Mika Kuoppala 已提交
1509
	 * This is a counter which gets incremented when reset is triggered,
1510 1511 1512 1513
	 *
	 * Before the reset commences, the I915_RESET_IN_PROGRESS bit is set
	 * meaning that any waiters holding onto the struct_mutex should
	 * relinquish the lock immediately in order for the reset to start.
M
Mika Kuoppala 已提交
1514 1515 1516 1517 1518 1519 1520 1521 1522
	 *
	 * If reset is not completed succesfully, the I915_WEDGE bit is
	 * set meaning that hardware is terminally sour and there is no
	 * recovery. All waiters on the reset_queue will be woken when
	 * that happens.
	 *
	 * This counter is used by the wait_seqno code to notice that reset
	 * event happened and it needs to restart the entire ioctl (since most
	 * likely the seqno it waited for won't ever signal anytime soon).
1523 1524 1525 1526
	 *
	 * This is important for lock-free wait paths, where no contended lock
	 * naturally enforces the correct ordering between the bail-out of the
	 * waiter and the gpu reset work code.
1527
	 */
1528
	unsigned long reset_count;
1529

1530 1531 1532
	unsigned long flags;
#define I915_RESET_IN_PROGRESS	0
#define I915_WEDGED		(BITS_PER_LONG - 1)
1533

1534 1535 1536 1537 1538 1539
	/**
	 * Waitqueue to signal when a hang is detected. Used to for waiters
	 * to release the struct_mutex for the reset to procede.
	 */
	wait_queue_head_t wait_queue;

1540 1541 1542 1543 1544
	/**
	 * Waitqueue to signal when the reset has completed. Used by clients
	 * that wait for dev_priv->mm.wedged to settle.
	 */
	wait_queue_head_t reset_queue;
1545

1546
	/* For missed irq/seqno simulation. */
1547
	unsigned long test_irq_rings;
1548 1549
};

1550 1551 1552 1553 1554 1555
enum modeset_restore {
	MODESET_ON_LID_OPEN,
	MODESET_DONE,
	MODESET_SUSPENDED,
};

1556 1557 1558 1559 1560
#define DP_AUX_A 0x40
#define DP_AUX_B 0x10
#define DP_AUX_C 0x20
#define DP_AUX_D 0x30

X
Xiong Zhang 已提交
1561 1562 1563 1564
#define DDC_PIN_B  0x05
#define DDC_PIN_C  0x04
#define DDC_PIN_D  0x06

1565
struct ddi_vbt_port_info {
1566 1567 1568 1569 1570 1571
	/*
	 * This is an index in the HDMI/DVI DDI buffer translation table.
	 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
	 * populate this field.
	 */
#define HDMI_LEVEL_SHIFT_UNKNOWN	0xff
1572
	uint8_t hdmi_level_shift;
1573 1574 1575 1576

	uint8_t supports_dvi:1;
	uint8_t supports_hdmi:1;
	uint8_t supports_dp:1;
1577 1578

	uint8_t alternate_aux_channel;
X
Xiong Zhang 已提交
1579
	uint8_t alternate_ddc_pin;
1580 1581 1582

	uint8_t dp_boost_level;
	uint8_t hdmi_boost_level;
1583 1584
};

R
Rodrigo Vivi 已提交
1585 1586 1587 1588 1589
enum psr_lines_to_wait {
	PSR_0_LINES_TO_WAIT = 0,
	PSR_1_LINE_TO_WAIT,
	PSR_4_LINES_TO_WAIT,
	PSR_8_LINES_TO_WAIT
1590 1591
};

1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603
struct intel_vbt_data {
	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */

	/* Feature bits */
	unsigned int int_tv_support:1;
	unsigned int lvds_dither:1;
	unsigned int lvds_vbt:1;
	unsigned int int_crt_support:1;
	unsigned int lvds_use_ssc:1;
	unsigned int display_clock_mode:1;
	unsigned int fdi_rx_polarity_inverted:1;
1604
	unsigned int panel_type:4;
1605 1606 1607
	int lvds_ssc_freq;
	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */

1608 1609
	enum drrs_support_type drrs_type;

1610 1611 1612 1613 1614
	struct {
		int rate;
		int lanes;
		int preemphasis;
		int vswing;
1615
		bool low_vswing;
1616 1617 1618 1619 1620
		bool initialized;
		bool support;
		int bpp;
		struct edp_power_seq pps;
	} edp;
1621

R
Rodrigo Vivi 已提交
1622 1623 1624 1625 1626 1627 1628 1629 1630
	struct {
		bool full_link;
		bool require_aux_wakeup;
		int idle_frames;
		enum psr_lines_to_wait lines_to_wait;
		int tp1_wakeup_time;
		int tp2_tp3_wakeup_time;
	} psr;

1631 1632
	struct {
		u16 pwm_freq_hz;
1633
		bool present;
1634
		bool active_low_pwm;
1635
		u8 min_brightness;	/* min_brightness/255 of max */
1636
		enum intel_backlight_type type;
1637 1638
	} backlight;

1639 1640 1641
	/* MIPI DSI */
	struct {
		u16 panel_id;
1642 1643 1644 1645 1646
		struct mipi_config *config;
		struct mipi_pps_data *pps;
		u8 seq_version;
		u32 size;
		u8 *data;
1647
		const u8 *sequence[MIPI_SEQ_MAX];
1648 1649
	} dsi;

1650 1651 1652
	int crt_ddc_pin;

	int child_dev_num;
1653
	union child_device_config *child_dev;
1654 1655

	struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1656
	struct sdvo_device_mapping sdvo_mappings[2];
1657 1658
};

1659 1660 1661 1662 1663
enum intel_ddb_partitioning {
	INTEL_DDB_PART_1_2,
	INTEL_DDB_PART_5_6, /* IVB+ */
};

1664 1665 1666 1667 1668 1669 1670 1671
struct intel_wm_level {
	bool enable;
	uint32_t pri_val;
	uint32_t spr_val;
	uint32_t cur_val;
	uint32_t fbc_val;
};

1672
struct ilk_wm_values {
1673 1674 1675 1676 1677 1678 1679 1680
	uint32_t wm_pipe[3];
	uint32_t wm_lp[3];
	uint32_t wm_lp_spr[3];
	uint32_t wm_linetime[3];
	bool enable_fbc_wm;
	enum intel_ddb_partitioning partitioning;
};

1681
struct vlv_pipe_wm {
1682
	uint16_t plane[I915_MAX_PLANES];
1683
};
1684

1685 1686
struct vlv_sr_wm {
	uint16_t plane;
1687 1688 1689 1690 1691
	uint16_t cursor;
};

struct vlv_wm_ddl_values {
	uint8_t plane[I915_MAX_PLANES];
1692
};
1693

1694 1695 1696
struct vlv_wm_values {
	struct vlv_pipe_wm pipe[3];
	struct vlv_sr_wm sr;
1697
	struct vlv_wm_ddl_values ddl[3];
1698 1699
	uint8_t level;
	bool cxsr;
1700 1701
};

1702
struct skl_ddb_entry {
1703
	uint16_t start, end;	/* in number of blocks, 'end' is exclusive */
1704 1705 1706 1707
};

static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
{
1708
	return entry->end - entry->start;
1709 1710
}

1711 1712 1713 1714 1715 1716 1717 1718 1719
static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
				       const struct skl_ddb_entry *e2)
{
	if (e1->start == e2->start && e1->end == e2->end)
		return true;

	return false;
}

1720
struct skl_ddb_allocation {
1721
	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1722
	struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1723 1724
};

1725
struct skl_wm_values {
1726
	unsigned dirty_pipes;
1727
	struct skl_ddb_allocation ddb;
1728 1729 1730
};

struct skl_wm_level {
L
Lyude 已提交
1731 1732 1733
	bool plane_en;
	uint16_t plane_res_b;
	uint8_t plane_res_l;
1734 1735
};

1736
/*
1737 1738 1739 1740
 * This struct helps tracking the state needed for runtime PM, which puts the
 * device in PCI D3 state. Notice that when this happens, nothing on the
 * graphics device works, even register access, so we don't get interrupts nor
 * anything else.
1741
 *
1742 1743 1744
 * Every piece of our code that needs to actually touch the hardware needs to
 * either call intel_runtime_pm_get or call intel_display_power_get with the
 * appropriate power domain.
1745
 *
1746 1747
 * Our driver uses the autosuspend delay feature, which means we'll only really
 * suspend if we stay with zero refcount for a certain amount of time. The
1748
 * default value is currently very conservative (see intel_runtime_pm_enable), but
1749
 * it can be changed with the standard runtime PM files from sysfs.
1750 1751 1752 1753 1754
 *
 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
 * goes back to false exactly before we reenable the IRQs. We use this variable
 * to check if someone is trying to enable/disable IRQs while they're supposed
 * to be disabled. This shouldn't happen and we'll print some error messages in
1755
 * case it happens.
1756
 *
1757
 * For more, read the Documentation/power/runtime_pm.txt.
1758
 */
1759
struct i915_runtime_pm {
1760
	atomic_t wakeref_count;
1761
	bool suspended;
1762
	bool irqs_enabled;
1763 1764
};

1765 1766 1767 1768 1769
enum intel_pipe_crc_source {
	INTEL_PIPE_CRC_SOURCE_NONE,
	INTEL_PIPE_CRC_SOURCE_PLANE1,
	INTEL_PIPE_CRC_SOURCE_PLANE2,
	INTEL_PIPE_CRC_SOURCE_PF,
1770
	INTEL_PIPE_CRC_SOURCE_PIPE,
D
Daniel Vetter 已提交
1771 1772 1773 1774 1775
	/* TV/DP on pre-gen5/vlv can't use the pipe source. */
	INTEL_PIPE_CRC_SOURCE_TV,
	INTEL_PIPE_CRC_SOURCE_DP_B,
	INTEL_PIPE_CRC_SOURCE_DP_C,
	INTEL_PIPE_CRC_SOURCE_DP_D,
1776
	INTEL_PIPE_CRC_SOURCE_AUTO,
1777 1778 1779
	INTEL_PIPE_CRC_SOURCE_MAX,
};

1780
struct intel_pipe_crc_entry {
1781
	uint32_t frame;
1782 1783 1784
	uint32_t crc[5];
};

1785
#define INTEL_PIPE_CRC_ENTRIES_NR	128
1786
struct intel_pipe_crc {
1787 1788
	spinlock_t lock;
	bool opened;		/* exclusive access to the result file */
1789
	struct intel_pipe_crc_entry *entries;
1790
	enum intel_pipe_crc_source source;
1791
	int head, tail;
1792
	wait_queue_head_t wq;
1793 1794
};

1795
struct i915_frontbuffer_tracking {
1796
	spinlock_t lock;
1797 1798 1799 1800 1801 1802 1803 1804 1805

	/*
	 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
	 * scheduled flips.
	 */
	unsigned busy_bits;
	unsigned flip_bits;
};

1806
struct i915_wa_reg {
1807
	i915_reg_t addr;
1808 1809 1810 1811 1812
	u32 value;
	/* bitmask representing WA bits */
	u32 mask;
};

1813 1814 1815 1816 1817 1818 1819
/*
 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
 * allowing it for RCS as we don't foresee any requirement of having
 * a whitelist for other engines. When it is really required for
 * other engines then the limit need to be increased.
 */
#define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1820 1821 1822 1823

struct i915_workarounds {
	struct i915_wa_reg reg[I915_MAX_WA_REGS];
	u32 count;
1824
	u32 hw_whitelist_count[I915_NUM_ENGINES];
1825 1826
};

1827 1828 1829 1830
struct i915_virtual_gpu {
	bool active;
};

1831 1832 1833 1834 1835 1836 1837
/* used in computing the new watermarks state */
struct intel_wm_config {
	unsigned int num_pipes_active;
	bool sprites_enabled;
	bool sprites_scaled;
};

1838 1839 1840 1841 1842
struct i915_oa_format {
	u32 format;
	int size;
};

1843 1844 1845 1846 1847
struct i915_oa_reg {
	i915_reg_t addr;
	u32 value;
};

1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871
struct i915_perf_stream;

struct i915_perf_stream_ops {
	/* Enables the collection of HW samples, either in response to
	 * I915_PERF_IOCTL_ENABLE or implicitly called when stream is
	 * opened without I915_PERF_FLAG_DISABLED.
	 */
	void (*enable)(struct i915_perf_stream *stream);

	/* Disables the collection of HW samples, either in response to
	 * I915_PERF_IOCTL_DISABLE or implicitly called before
	 * destroying the stream.
	 */
	void (*disable)(struct i915_perf_stream *stream);

	/* Call poll_wait, passing a wait queue that will be woken
	 * once there is something ready to read() for the stream
	 */
	void (*poll_wait)(struct i915_perf_stream *stream,
			  struct file *file,
			  poll_table *wait);

	/* For handling a blocking read, wait until there is something
	 * to ready to read() for the stream. E.g. wait on the same
1872
	 * wait queue that would be passed to poll_wait().
1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911
	 */
	int (*wait_unlocked)(struct i915_perf_stream *stream);

	/* read - Copy buffered metrics as records to userspace
	 * @buf: the userspace, destination buffer
	 * @count: the number of bytes to copy, requested by userspace
	 * @offset: zero at the start of the read, updated as the read
	 *          proceeds, it represents how many bytes have been
	 *          copied so far and the buffer offset for copying the
	 *          next record.
	 *
	 * Copy as many buffered i915 perf samples and records for
	 * this stream to userspace as will fit in the given buffer.
	 *
	 * Only write complete records; returning -ENOSPC if there
	 * isn't room for a complete record.
	 *
	 * Return any error condition that results in a short read
	 * such as -ENOSPC or -EFAULT, even though these may be
	 * squashed before returning to userspace.
	 */
	int (*read)(struct i915_perf_stream *stream,
		    char __user *buf,
		    size_t count,
		    size_t *offset);

	/* Cleanup any stream specific resources.
	 *
	 * The stream will always be disabled before this is called.
	 */
	void (*destroy)(struct i915_perf_stream *stream);
};

struct i915_perf_stream {
	struct drm_i915_private *dev_priv;

	struct list_head link;

	u32 sample_flags;
1912
	int sample_size;
1913 1914 1915 1916

	struct i915_gem_context *ctx;
	bool enabled;

1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933
	const struct i915_perf_stream_ops *ops;
};

struct i915_oa_ops {
	void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
	int (*enable_metric_set)(struct drm_i915_private *dev_priv);
	void (*disable_metric_set)(struct drm_i915_private *dev_priv);
	void (*oa_enable)(struct drm_i915_private *dev_priv);
	void (*oa_disable)(struct drm_i915_private *dev_priv);
	void (*update_oacontrol)(struct drm_i915_private *dev_priv);
	void (*update_hw_ctx_id_locked)(struct drm_i915_private *dev_priv,
					u32 ctx_id);
	int (*read)(struct i915_perf_stream *stream,
		    char __user *buf,
		    size_t count,
		    size_t *offset);
	bool (*oa_buffer_is_empty)(struct drm_i915_private *dev_priv);
1934 1935
};

1936
struct drm_i915_private {
1937 1938
	struct drm_device drm;

1939
	struct kmem_cache *objects;
1940
	struct kmem_cache *vmas;
1941
	struct kmem_cache *requests;
1942
	struct kmem_cache *dependencies;
1943

1944
	const struct intel_device_info info;
1945 1946 1947 1948 1949

	int relative_constants_mode;

	void __iomem *regs;

1950
	struct intel_uncore uncore;
1951

1952 1953
	struct i915_virtual_gpu vgpu;

1954
	struct intel_gvt *gvt;
1955

1956 1957
	struct intel_guc guc;

1958 1959
	struct intel_csr csr;

1960
	struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1961

1962 1963 1964 1965 1966 1967 1968 1969 1970
	/** gmbus_mutex protects against concurrent usage of the single hw gmbus
	 * controller on different i2c buses. */
	struct mutex gmbus_mutex;

	/**
	 * Base address of the gmbus and gpio block.
	 */
	uint32_t gpio_mmio_base;

1971 1972 1973
	/* MMIO base address for MIPI regs */
	uint32_t mipi_mmio_base;

1974 1975
	uint32_t psr_mmio_base;

1976 1977
	uint32_t pps_mmio_base;

1978 1979
	wait_queue_head_t gmbus_wait_queue;

1980
	struct pci_dev *bridge_dev;
1981
	struct i915_gem_context *kernel_context;
1982
	struct intel_engine_cs *engine[I915_NUM_ENGINES];
1983
	struct i915_vma *semaphore;
1984

1985
	struct drm_dma_handle *status_page_dmah;
1986 1987 1988 1989 1990
	struct resource mch_res;

	/* protects the irq masks */
	spinlock_t irq_lock;

1991 1992 1993
	/* protects the mmio flip data */
	spinlock_t mmio_flip_lock;

1994 1995
	bool display_irqs_enabled;

1996 1997 1998
	/* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
	struct pm_qos_request pm_qos;

V
Ville Syrjälä 已提交
1999 2000
	/* Sideband mailbox protection */
	struct mutex sb_lock;
2001 2002

	/** Cached value of IMR to avoid reads in updating the bitfield */
2003 2004 2005 2006
	union {
		u32 irq_mask;
		u32 de_irq_mask[I915_MAX_PIPES];
	};
2007
	u32 gt_irq_mask;
2008 2009
	u32 pm_imr;
	u32 pm_ier;
2010
	u32 pm_rps_events;
2011
	u32 pm_guc_events;
2012
	u32 pipestat_irq_mask[I915_MAX_PIPES];
2013

2014
	struct i915_hotplug hotplug;
2015
	struct intel_fbc fbc;
2016
	struct i915_drrs drrs;
2017
	struct intel_opregion opregion;
2018
	struct intel_vbt_data vbt;
2019

2020 2021
	bool preserve_bios_swizzle;

2022 2023 2024
	/* overlay */
	struct intel_overlay *overlay;

2025
	/* backlight registers and fields in struct intel_panel */
2026
	struct mutex backlight_lock;
2027

2028 2029 2030
	/* LVDS info */
	bool no_aux_handshake;

V
Ville Syrjälä 已提交
2031 2032 2033
	/* protects panel power sequencer state */
	struct mutex pps_mutex;

2034 2035 2036 2037
	struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
	int num_fence_regs; /* 8 on pre-965, 16 otherwise */

	unsigned int fsb_freq, mem_freq, is_ddr3;
2038
	unsigned int skl_preferred_vco_freq;
2039 2040 2041 2042 2043 2044 2045 2046
	unsigned int cdclk_freq, max_cdclk_freq;

	/*
	 * For reading holding any crtc lock is sufficient,
	 * for writing must hold all of them.
	 */
	unsigned int atomic_cdclk_freq;

M
Mika Kahola 已提交
2047
	unsigned int max_dotclk_freq;
2048
	unsigned int rawclk_freq;
2049
	unsigned int hpll_freq;
2050
	unsigned int czclk_freq;
2051

2052
	struct {
2053
		unsigned int vco, ref;
2054 2055
	} cdclk_pll;

2056 2057 2058 2059 2060 2061 2062
	/**
	 * wq - Driver workqueue for GEM.
	 *
	 * NOTE: Work items scheduled here are not allowed to grab any modeset
	 * locks, for otherwise the flushing done in the pageflip code will
	 * result in deadlocks.
	 */
2063 2064 2065 2066 2067 2068 2069
	struct workqueue_struct *wq;

	/* Display functions */
	struct drm_i915_display_funcs display;

	/* PCH chipset type */
	enum intel_pch pch_type;
2070
	unsigned short pch_id;
2071 2072 2073

	unsigned long quirks;

2074 2075
	enum modeset_restore modeset_restore;
	struct mutex modeset_restore_lock;
2076
	struct drm_atomic_state *modeset_restore_state;
2077
	struct drm_modeset_acquire_ctx reset_ctx;
2078

2079
	struct list_head vm_list; /* Global list of all address spaces */
2080
	struct i915_ggtt ggtt; /* VM representing the global address space */
B
Ben Widawsky 已提交
2081

2082
	struct i915_gem_mm mm;
2083 2084
	DECLARE_HASHTABLE(mm_structs, 7);
	struct mutex mm_lock;
2085

2086 2087 2088 2089 2090 2091 2092
	/* The hw wants to have a stable context identifier for the lifetime
	 * of the context (for OA, PASID, faults, etc). This is limited
	 * in execlists to 21 bits.
	 */
	struct ida context_hw_ida;
#define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */

2093 2094
	/* Kernel Modesetting */

2095 2096
	struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
	struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
2097 2098
	wait_queue_head_t pending_flip_queue;

2099 2100 2101 2102
#ifdef CONFIG_DEBUG_FS
	struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
#endif

2103
	/* dpll and cdclk state is protected by connection_mutex */
D
Daniel Vetter 已提交
2104 2105
	int num_shared_dpll;
	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
2106
	const struct intel_dpll_mgr *dpll_mgr;
2107

2108 2109 2110 2111 2112 2113 2114
	/*
	 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
	 * Must be global rather than per dpll, because on some platforms
	 * plls share registers.
	 */
	struct mutex dpll_lock;

2115 2116 2117
	unsigned int active_crtcs;
	unsigned int min_pixclk[I915_MAX_PIPES];

2118
	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
2119

2120
	struct i915_workarounds workarounds;
2121

2122 2123
	struct i915_frontbuffer_tracking fb_tracking;

2124
	u16 orig_clock;
2125

2126
	bool mchbar_need_disable;
2127

2128 2129
	struct intel_l3_parity l3_parity;

B
Ben Widawsky 已提交
2130
	/* Cannot be determined by PCIID. You must always read a register. */
2131
	u32 edram_cap;
B
Ben Widawsky 已提交
2132

2133
	/* gen6+ rps state */
2134
	struct intel_gen6_power_mgmt rps;
2135

2136 2137
	/* ilk-only ips/rps state. Everything in here is protected by the global
	 * mchdev_lock in intel_pm.c */
2138
	struct intel_ilk_power_mgmt ips;
2139

2140
	struct i915_power_domains power_domains;
2141

R
Rodrigo Vivi 已提交
2142
	struct i915_psr psr;
2143

2144
	struct i915_gpu_error gpu_error;
2145

2146 2147
	struct drm_i915_gem_object *vlv_pctx;

2148
#ifdef CONFIG_DRM_FBDEV_EMULATION
2149 2150
	/* list of fbdev register on this device */
	struct intel_fbdev *fbdev;
2151
	struct work_struct fbdev_suspend_work;
2152
#endif
2153 2154

	struct drm_property *broadcast_rgb_property;
2155
	struct drm_property *force_audio_property;
2156

I
Imre Deak 已提交
2157
	/* hda/i915 audio component */
2158
	struct i915_audio_component *audio_component;
I
Imre Deak 已提交
2159
	bool audio_component_registered;
2160 2161 2162 2163 2164
	/**
	 * av_mutex - mutex for audio/video sync
	 *
	 */
	struct mutex av_mutex;
I
Imre Deak 已提交
2165

2166
	uint32_t hw_context_size;
2167
	struct list_head context_list;
2168

2169
	u32 fdi_rx_config;
2170

2171
	/* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2172
	u32 chv_phy_control;
2173 2174 2175 2176 2177 2178
	/*
	 * Shadows for CHV DPLL_MD regs to keep the state
	 * checker somewhat working in the presence hardware
	 * crappiness (can't read out DPLL_MD for pipes B & C).
	 */
	u32 chv_dpll_md[I915_MAX_PIPES];
2179
	u32 bxt_phy_grc;
2180

2181
	u32 suspend_count;
2182
	bool suspended_to_idle;
2183
	struct i915_suspend_saved_registers regfile;
2184
	struct vlv_s0ix_state vlv_s0ix_state;
2185

2186
	enum {
2187 2188 2189 2190 2191
		I915_SAGV_UNKNOWN = 0,
		I915_SAGV_DISABLED,
		I915_SAGV_ENABLED,
		I915_SAGV_NOT_CONTROLLED
	} sagv_status;
2192

2193
	struct {
2194 2195 2196
		/* protects DSPARB registers on pre-g4x/vlv/chv */
		spinlock_t dsparb_lock;

2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207
		/*
		 * Raw watermark latency values:
		 * in 0.1us units for WM0,
		 * in 0.5us units for WM1+.
		 */
		/* primary */
		uint16_t pri_latency[5];
		/* sprite */
		uint16_t spr_latency[5];
		/* cursor */
		uint16_t cur_latency[5];
2208 2209 2210 2211 2212 2213
		/*
		 * Raw watermark memory latency values
		 * for SKL for all 8 levels
		 * in 1us units.
		 */
		uint16_t skl_latency[8];
2214 2215

		/* current hardware state */
2216 2217 2218
		union {
			struct ilk_wm_values hw;
			struct skl_wm_values skl_hw;
2219
			struct vlv_wm_values vlv;
2220
		};
2221 2222

		uint8_t max_level;
2223 2224 2225 2226 2227 2228 2229

		/*
		 * Should be held around atomic WM register writing; also
		 * protects * intel_crtc->wm.active and
		 * cstate->wm.need_postvbl_update.
		 */
		struct mutex wm_mutex;
2230 2231 2232 2233 2234 2235 2236

		/*
		 * Set during HW readout of watermarks/DDB.  Some platforms
		 * need to know when we're still using BIOS-provided values
		 * (which we don't fully trust).
		 */
		bool distrust_bios_wm;
2237 2238
	} wm;

2239 2240
	struct i915_runtime_pm pm;

2241 2242
	struct {
		bool initialized;
2243

2244
		struct kobject *metrics_kobj;
2245
		struct ctl_table_header *sysctl_header;
2246

2247 2248
		struct mutex lock;
		struct list_head streams;
2249

2250 2251
		spinlock_t hook_lock;

2252
		struct {
2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268
			struct i915_perf_stream *exclusive_stream;

			u32 specific_ctx_id;
			struct i915_vma *pinned_rcs_vma;

			struct hrtimer poll_check_timer;
			wait_queue_head_t poll_wq;
			bool pollin;

			bool periodic;
			int period_exponent;
			int timestamp_frequency;

			int tail_margin;

			int metrics_set;
2269 2270 2271 2272 2273

			const struct i915_oa_reg *mux_regs;
			int mux_regs_len;
			const struct i915_oa_reg *b_counter_regs;
			int b_counter_regs_len;
2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286

			struct {
				struct i915_vma *vma;
				u8 *vaddr;
				int format;
				int format_size;
			} oa_buffer;

			u32 gen7_latched_oastatus1;

			struct i915_oa_ops ops;
			const struct i915_oa_format *oa_formats;
			int n_builtin_sets;
2287
		} oa;
2288 2289
	} perf;

2290 2291
	/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
	struct {
2292
		void (*resume)(struct drm_i915_private *);
2293
		void (*cleanup_engine)(struct intel_engine_cs *engine);
2294

2295 2296
		struct list_head timelines;
		struct i915_gem_timeline global_timeline;
2297
		u32 active_requests;
2298

2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324
		/**
		 * Is the GPU currently considered idle, or busy executing
		 * userspace requests? Whilst idle, we allow runtime power
		 * management to power down the hardware and display clocks.
		 * In order to reduce the effect on performance, there
		 * is a slight delay before we do so.
		 */
		bool awake;

		/**
		 * We leave the user IRQ off as much as possible,
		 * but this means that requests will finish and never
		 * be retired once the system goes idle. Set a timer to
		 * fire periodically while the ring is running. When it
		 * fires, go retire requests.
		 */
		struct delayed_work retire_work;

		/**
		 * When we detect an idle GPU, we want to turn on
		 * powersaving features. So once we see that there
		 * are no more requests outstanding and no more
		 * arrive within a small period of time, we fire
		 * off the idle_work.
		 */
		struct delayed_work idle_work;
2325 2326

		ktime_t last_init_time;
2327 2328
	} gt;

2329 2330 2331
	/* perform PHY state sanity checks? */
	bool chv_phy_assert[2];

M
Mahesh Kumar 已提交
2332 2333
	bool ipc_enabled;

2334 2335
	/* Used to save the pipe-to-encoder mapping for audio */
	struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2336

2337 2338 2339 2340
	/*
	 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
	 * will be rejected. Instead look for a better place.
	 */
2341
};
L
Linus Torvalds 已提交
2342

2343 2344
static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
{
2345
	return container_of(dev, struct drm_i915_private, drm);
2346 2347
}

2348
static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
I
Imre Deak 已提交
2349
{
2350
	return to_i915(dev_get_drvdata(kdev));
I
Imre Deak 已提交
2351 2352
}

2353 2354 2355 2356 2357
static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
{
	return container_of(guc, struct drm_i915_private, guc);
}

2358
/* Simple iterator over all initialised engines */
2359 2360 2361 2362 2363
#define for_each_engine(engine__, dev_priv__, id__) \
	for ((id__) = 0; \
	     (id__) < I915_NUM_ENGINES; \
	     (id__)++) \
		for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2364

2365 2366 2367 2368 2369 2370
#define __mask_next_bit(mask) ({					\
	int __idx = ffs(mask) - 1;					\
	mask &= ~BIT(__idx);						\
	__idx;								\
})

2371
/* Iterator over subset of engines selected by mask */
2372 2373
#define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
	for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask;	\
2374
	     tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2375

2376 2377 2378 2379 2380 2381 2382
enum hdmi_force_audio {
	HDMI_AUDIO_OFF_DVI = -2,	/* no aux data for HDMI-DVI converter */
	HDMI_AUDIO_OFF,			/* force turn off HDMI audio */
	HDMI_AUDIO_AUTO,		/* trust EDID */
	HDMI_AUDIO_ON,			/* force turn on HDMI audio */
};

2383
#define I915_GTT_OFFSET_NONE ((u32)-1)
2384

2385 2386
/*
 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2387
 * considered to be the frontbuffer for the given plane interface-wise. This
2388 2389 2390 2391 2392
 * doesn't mean that the hw necessarily already scans it out, but that any
 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
 *
 * We have one bit per pipe and per scanout plane type.
 */
2393 2394
#define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2395 2396 2397
#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
	(1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
#define INTEL_FRONTBUFFER_CURSOR(pipe) \
2398 2399 2400
	(1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
#define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
	(1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2401
#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2402
	(1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2403
#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2404
	(0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2405

2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431
/*
 * Optimised SGL iterator for GEM objects
 */
static __always_inline struct sgt_iter {
	struct scatterlist *sgp;
	union {
		unsigned long pfn;
		dma_addr_t dma;
	};
	unsigned int curr;
	unsigned int max;
} __sgt_iter(struct scatterlist *sgl, bool dma) {
	struct sgt_iter s = { .sgp = sgl };

	if (s.sgp) {
		s.max = s.curr = s.sgp->offset;
		s.max += s.sgp->length;
		if (dma)
			s.dma = sg_dma_address(s.sgp);
		else
			s.pfn = page_to_pfn(sg_page(s.sgp));
	}

	return s;
}

2432 2433 2434 2435 2436 2437 2438 2439
static inline struct scatterlist *____sg_next(struct scatterlist *sg)
{
	++sg;
	if (unlikely(sg_is_chain(sg)))
		sg = sg_chain_ptr(sg);
	return sg;
}

2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453
/**
 * __sg_next - return the next scatterlist entry in a list
 * @sg:		The current sg entry
 *
 * Description:
 *   If the entry is the last, return NULL; otherwise, step to the next
 *   element in the array (@sg@+1). If that's a chain pointer, follow it;
 *   otherwise just return the pointer to the current element.
 **/
static inline struct scatterlist *__sg_next(struct scatterlist *sg)
{
#ifdef CONFIG_DEBUG_SG
	BUG_ON(sg->sg_magic != SG_MAGIC);
#endif
2454
	return sg_is_last(sg) ? NULL : ____sg_next(sg);
2455 2456
}

2457 2458 2459 2460 2461 2462 2463 2464 2465 2466
/**
 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
 * @__dmap:	DMA address (output)
 * @__iter:	'struct sgt_iter' (iterator state, internal)
 * @__sgt:	sg_table to iterate over (input)
 */
#define for_each_sgt_dma(__dmap, __iter, __sgt)				\
	for ((__iter) = __sgt_iter((__sgt)->sgl, true);			\
	     ((__dmap) = (__iter).dma + (__iter).curr);			\
	     (((__iter).curr += PAGE_SIZE) < (__iter).max) ||		\
2467
	     ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479

/**
 * for_each_sgt_page - iterate over the pages of the given sg_table
 * @__pp:	page pointer (output)
 * @__iter:	'struct sgt_iter' (iterator state, internal)
 * @__sgt:	sg_table to iterate over (input)
 */
#define for_each_sgt_page(__pp, __iter, __sgt)				\
	for ((__iter) = __sgt_iter((__sgt)->sgl, false);		\
	     ((__pp) = (__iter).pfn == 0 ? NULL :			\
	      pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
	     (((__iter).curr += PAGE_SIZE) < (__iter).max) ||		\
2480
	     ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2481

2482 2483 2484 2485 2486 2487 2488
static inline const struct intel_device_info *
intel_info(const struct drm_i915_private *dev_priv)
{
	return &dev_priv->info;
}

#define INTEL_INFO(dev_priv)	intel_info((dev_priv))
2489

2490
#define INTEL_GEN(dev_priv)	((dev_priv)->info.gen)
2491
#define INTEL_DEVID(dev_priv)	((dev_priv)->info.device_id)
2492

2493
#define REVID_FOREVER		0xff
2494
#define INTEL_REVID(dev_priv)	((dev_priv)->drm.pdev->revision)
2495 2496 2497 2498 2499 2500 2501

#define GEN_FOREVER (0)
/*
 * Returns true if Gen is in inclusive range [Start, End].
 *
 * Use GEN_FOREVER for unbound start and or end.
 */
2502
#define IS_GEN(dev_priv, s, e) ({ \
2503 2504 2505 2506 2507 2508 2509 2510 2511
	unsigned int __s = (s), __e = (e); \
	BUILD_BUG_ON(!__builtin_constant_p(s)); \
	BUILD_BUG_ON(!__builtin_constant_p(e)); \
	if ((__s) != GEN_FOREVER) \
		__s = (s) - 1; \
	if ((__e) == GEN_FOREVER) \
		__e = BITS_PER_LONG - 1; \
	else \
		__e = (e) - 1; \
2512
	!!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
2513 2514
})

2515 2516 2517 2518 2519 2520 2521 2522
/*
 * Return true if revision is in range [since,until] inclusive.
 *
 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
 */
#define IS_REVID(p, since, until) \
	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))

2523 2524
#define IS_I830(dev_priv)	((dev_priv)->info.platform == INTEL_I830)
#define IS_I845G(dev_priv)	((dev_priv)->info.platform == INTEL_I845G)
2525
#define IS_I85X(dev_priv)	((dev_priv)->info.platform == INTEL_I85X)
2526
#define IS_I865G(dev_priv)	((dev_priv)->info.platform == INTEL_I865G)
2527
#define IS_I915G(dev_priv)	((dev_priv)->info.platform == INTEL_I915G)
2528 2529
#define IS_I915GM(dev_priv)	((dev_priv)->info.platform == INTEL_I915GM)
#define IS_I945G(dev_priv)	((dev_priv)->info.platform == INTEL_I945G)
2530
#define IS_I945GM(dev_priv)	((dev_priv)->info.platform == INTEL_I945GM)
2531 2532
#define IS_I965G(dev_priv)	((dev_priv)->info.platform == INTEL_I965G)
#define IS_I965GM(dev_priv)	((dev_priv)->info.platform == INTEL_I965GM)
2533 2534 2535
#define IS_G45(dev_priv)	((dev_priv)->info.platform == INTEL_G45)
#define IS_GM45(dev_priv)	((dev_priv)->info.platform == INTEL_GM45)
#define IS_G4X(dev_priv)	(IS_G45(dev_priv) || IS_GM45(dev_priv))
2536 2537
#define IS_PINEVIEW_G(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa001)
#define IS_PINEVIEW_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa011)
2538
#define IS_PINEVIEW(dev_priv)	((dev_priv)->info.is_pineview)
2539
#define IS_G33(dev_priv)	((dev_priv)->info.platform == INTEL_G33)
2540
#define IS_IRONLAKE_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0046)
2541
#define IS_IVYBRIDGE(dev_priv)	((dev_priv)->info.platform == INTEL_IVYBRIDGE)
2542 2543 2544
#define IS_IVB_GT1(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0156 || \
				 INTEL_DEVID(dev_priv) == 0x0152 || \
				 INTEL_DEVID(dev_priv) == 0x015a)
2545 2546 2547 2548 2549 2550 2551 2552
#define IS_VALLEYVIEW(dev_priv)	((dev_priv)->info.platform == INTEL_VALLEYVIEW)
#define IS_CHERRYVIEW(dev_priv)	((dev_priv)->info.platform == INTEL_CHERRYVIEW)
#define IS_HASWELL(dev_priv)	((dev_priv)->info.platform == INTEL_HASWELL)
#define IS_BROADWELL(dev_priv)	((dev_priv)->info.platform == INTEL_BROADWELL)
#define IS_SKYLAKE(dev_priv)	((dev_priv)->info.platform == INTEL_SKYLAKE)
#define IS_BROXTON(dev_priv)	((dev_priv)->info.platform == INTEL_BROXTON)
#define IS_KABYLAKE(dev_priv)	((dev_priv)->info.platform == INTEL_KABYLAKE)
#define IS_GEMINILAKE(dev_priv)	((dev_priv)->info.platform == INTEL_GEMINILAKE)
2553
#define IS_MOBILE(dev_priv)	((dev_priv)->info.is_mobile)
2554 2555 2556 2557 2558 2559
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv)	(IS_BROADWELL(dev_priv) && \
				 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 ||	\
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xb ||	\
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
V
Ville Syrjälä 已提交
2560
/* ULX machines are also considered ULT. */
2561 2562 2563 2564 2565 2566 2567 2568
#define IS_BDW_ULX(dev_priv)	(IS_BROADWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
#define IS_BDW_GT3(dev_priv)	(IS_BROADWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
#define IS_HSW_ULT(dev_priv)	(IS_HASWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
#define IS_HSW_GT3(dev_priv)	(IS_HASWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2569
/* ULX machines are also considered ULT. */
2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591
#define IS_HSW_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0A0E || \
				 INTEL_DEVID(dev_priv) == 0x0A1E)
#define IS_SKL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x1906 || \
				 INTEL_DEVID(dev_priv) == 0x1913 || \
				 INTEL_DEVID(dev_priv) == 0x1916 || \
				 INTEL_DEVID(dev_priv) == 0x1921 || \
				 INTEL_DEVID(dev_priv) == 0x1926)
#define IS_SKL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x190E || \
				 INTEL_DEVID(dev_priv) == 0x1915 || \
				 INTEL_DEVID(dev_priv) == 0x191E)
#define IS_KBL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x5906 || \
				 INTEL_DEVID(dev_priv) == 0x5913 || \
				 INTEL_DEVID(dev_priv) == 0x5916 || \
				 INTEL_DEVID(dev_priv) == 0x5921 || \
				 INTEL_DEVID(dev_priv) == 0x5926)
#define IS_KBL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x590E || \
				 INTEL_DEVID(dev_priv) == 0x5915 || \
				 INTEL_DEVID(dev_priv) == 0x591E)
#define IS_SKL_GT3(dev_priv)	(IS_SKYLAKE(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
#define IS_SKL_GT4(dev_priv)	(IS_SKYLAKE(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
2592

2593
#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2594

2595 2596 2597 2598 2599 2600
#define SKL_REVID_A0		0x0
#define SKL_REVID_B0		0x1
#define SKL_REVID_C0		0x2
#define SKL_REVID_D0		0x3
#define SKL_REVID_E0		0x4
#define SKL_REVID_F0		0x5
2601 2602
#define SKL_REVID_G0		0x6
#define SKL_REVID_H0		0x7
2603

2604 2605
#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))

2606
#define BXT_REVID_A0		0x0
2607
#define BXT_REVID_A1		0x1
2608
#define BXT_REVID_B0		0x3
2609
#define BXT_REVID_B_LAST	0x8
2610
#define BXT_REVID_C0		0x9
N
Nick Hoath 已提交
2611

2612 2613
#define IS_BXT_REVID(dev_priv, since, until) \
	(IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2614

M
Mika Kuoppala 已提交
2615 2616
#define KBL_REVID_A0		0x0
#define KBL_REVID_B0		0x1
2617 2618 2619
#define KBL_REVID_C0		0x2
#define KBL_REVID_D0		0x3
#define KBL_REVID_E0		0x4
M
Mika Kuoppala 已提交
2620

2621 2622
#define IS_KBL_REVID(dev_priv, since, until) \
	(IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
M
Mika Kuoppala 已提交
2623

2624 2625 2626 2627 2628 2629
/*
 * The genX designation typically refers to the render engine, so render
 * capability related checks should use IS_GEN, while display and other checks
 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
 * chips, etc.).
 */
2630 2631 2632 2633 2634 2635 2636 2637
#define IS_GEN2(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(1)))
#define IS_GEN3(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(2)))
#define IS_GEN4(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(3)))
#define IS_GEN5(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(4)))
#define IS_GEN6(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(5)))
#define IS_GEN7(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(6)))
#define IS_GEN8(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(7)))
#define IS_GEN9(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(8)))
2638

2639 2640
#define IS_GEN9_LP(dev_priv)	(IS_GEN9(dev_priv) && INTEL_INFO(dev_priv)->is_lp)

2641 2642 2643 2644 2645 2646 2647 2648 2649
#define ENGINE_MASK(id)	BIT(id)
#define RENDER_RING	ENGINE_MASK(RCS)
#define BSD_RING	ENGINE_MASK(VCS)
#define BLT_RING	ENGINE_MASK(BCS)
#define VEBOX_RING	ENGINE_MASK(VECS)
#define BSD2_RING	ENGINE_MASK(VCS2)
#define ALL_ENGINES	(~0)

#define HAS_ENGINE(dev_priv, id) \
2650
	(!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2651 2652 2653 2654 2655 2656

#define HAS_BSD(dev_priv)	HAS_ENGINE(dev_priv, VCS)
#define HAS_BSD2(dev_priv)	HAS_ENGINE(dev_priv, VCS2)
#define HAS_BLT(dev_priv)	HAS_ENGINE(dev_priv, BCS)
#define HAS_VEBOX(dev_priv)	HAS_ENGINE(dev_priv, VECS)

2657 2658 2659
#define HAS_LLC(dev_priv)	((dev_priv)->info.has_llc)
#define HAS_SNOOP(dev_priv)	((dev_priv)->info.has_snoop)
#define HAS_EDRAM(dev_priv)	(!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2660 2661
#define HAS_WT(dev_priv)	((IS_HASWELL(dev_priv) || \
				 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2662

2663
#define HWS_NEEDS_PHYSICAL(dev_priv)	((dev_priv)->info.hws_needs_physical)
2664

2665 2666 2667 2668 2669 2670 2671 2672 2673 2674
#define HAS_HW_CONTEXTS(dev_priv)	    ((dev_priv)->info.has_hw_contexts)
#define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
		((dev_priv)->info.has_logical_ring_contexts)
#define USES_PPGTT(dev_priv)		(i915.enable_ppgtt)
#define USES_FULL_PPGTT(dev_priv)	(i915.enable_ppgtt >= 2)
#define USES_FULL_48BIT_PPGTT(dev_priv)	(i915.enable_ppgtt == 3)

#define HAS_OVERLAY(dev_priv)		 ((dev_priv)->info.has_overlay)
#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
		((dev_priv)->info.overlay_needs_physical)
2675

2676
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
2677
#define HAS_BROKEN_CS_TLB(dev_priv)	(IS_I830(dev_priv) || IS_I845G(dev_priv))
2678 2679

/* WaRsDisableCoarsePowerGating:skl,bxt */
2680 2681 2682 2683
#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
	(IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \
	 IS_SKL_GT3(dev_priv) || \
	 IS_SKL_GT4(dev_priv))
2684

2685 2686 2687 2688 2689 2690
/*
 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
 * even when in MSI mode. This results in spurious interrupt warnings if the
 * legacy irq no. is shared with another device. The kernel then disables that
 * interrupt source and so prevents the other device from working properly.
 */
2691 2692
#define HAS_AUX_IRQ(dev_priv)   ((dev_priv)->info.gen >= 5)
#define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
2693

2694 2695 2696
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 * rows, which changed the alignment requirements and fence programming.
 */
2697 2698 2699
#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
					 !(IS_I915G(dev_priv) || \
					 IS_I915GM(dev_priv)))
2700 2701
#define SUPPORTS_TV(dev_priv)		((dev_priv)->info.supports_tv)
#define I915_HAS_HOTPLUG(dev_priv)	((dev_priv)->info.has_hotplug)
2702

2703 2704 2705
#define HAS_FW_BLC(dev_priv) 	(INTEL_GEN(dev_priv) > 2)
#define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
#define HAS_FBC(dev_priv)	((dev_priv)->info.has_fbc)
2706

2707
#define HAS_IPS(dev_priv)	(IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2708

2709
#define HAS_DP_MST(dev_priv)	((dev_priv)->info.has_dp_mst)
2710

2711 2712 2713 2714 2715
#define HAS_DDI(dev_priv)		 ((dev_priv)->info.has_ddi)
#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
#define HAS_PSR(dev_priv)		 ((dev_priv)->info.has_psr)
#define HAS_RC6(dev_priv)		 ((dev_priv)->info.has_rc6)
#define HAS_RC6p(dev_priv)		 ((dev_priv)->info.has_rc6p)
P
Paulo Zanoni 已提交
2716

2717
#define HAS_CSR(dev_priv)	((dev_priv)->info.has_csr)
2718

2719
#define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2720 2721
#define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)

2722 2723 2724 2725 2726
/*
 * For now, anything with a GuC requires uCode loading, and then supports
 * command submission once loaded. But these are logically independent
 * properties, so we have separate macros to test them.
 */
2727 2728 2729
#define HAS_GUC(dev_priv)	((dev_priv)->info.has_guc)
#define HAS_GUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
#define HAS_GUC_SCHED(dev_priv)	(HAS_GUC(dev_priv))
2730

2731
#define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2732

2733
#define HAS_POOLED_EU(dev_priv)	((dev_priv)->info.has_pooled_eu)
2734

2735 2736 2737 2738 2739 2740
#define INTEL_PCH_DEVICE_ID_MASK		0xff00
#define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
#define INTEL_PCH_PPT_DEVICE_ID_TYPE		0x1e00
#define INTEL_PCH_LPT_DEVICE_ID_TYPE		0x8c00
#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE		0x9c00
2741 2742
#define INTEL_PCH_SPT_DEVICE_ID_TYPE		0xA100
#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE		0x9D00
2743
#define INTEL_PCH_KBP_DEVICE_ID_TYPE		0xA200
2744
#define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
2745
#define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
2746
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
2747

2748 2749 2750 2751
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
#define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2752 2753 2754 2755
#define HAS_PCH_LPT_LP(dev_priv) \
	((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
#define HAS_PCH_LPT_H(dev_priv) \
	((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2756 2757 2758 2759
#define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
#define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2760

2761
#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2762

2763 2764
#define HAS_LSPCON(dev_priv) (IS_GEN9(dev_priv))

2765
/* DPF == dynamic parity feature */
2766
#define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2767 2768
#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
				 2 : HAS_L3_DPF(dev_priv))
2769

2770
#define GT_FREQUENCY_MULTIPLIER 50
A
Akash Goel 已提交
2771
#define GEN9_FREQ_SCALER 3
2772

2773 2774
#define HAS_DECOUPLED_MMIO(dev_priv) (INTEL_INFO(dev_priv)->has_decoupled_mmio)

2775 2776
#include "i915_trace.h"

2777 2778 2779 2780 2781 2782 2783 2784 2785
static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
{
#ifdef CONFIG_INTEL_IOMMU
	if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped)
		return true;
#endif
	return false;
}

2786
int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2787
				int enable_ppgtt);
2788

2789 2790
bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);

2791
/* i915_drv.c */
2792 2793 2794 2795 2796 2797 2798
void __printf(3, 4)
__i915_printk(struct drm_i915_private *dev_priv, const char *level,
	      const char *fmt, ...);

#define i915_report_error(dev_priv, fmt, ...)				   \
	__i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)

2799
#ifdef CONFIG_COMPAT
D
Dave Airlie 已提交
2800 2801
extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
			      unsigned long arg);
2802 2803
#else
#define i915_compat_ioctl NULL
2804
#endif
2805 2806 2807 2808 2809
extern const struct dev_pm_ops i915_pm_ops;

extern int i915_driver_load(struct pci_dev *pdev,
			    const struct pci_device_id *ent);
extern void i915_driver_unload(struct drm_device *dev);
2810 2811
extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2812
extern void i915_reset(struct drm_i915_private *dev_priv);
2813
extern int intel_guc_reset(struct drm_i915_private *dev_priv);
2814
extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2815
extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
2816 2817 2818 2819
extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2820
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2821

2822
/* intel_hotplug.c */
2823 2824
void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
			   u32 pin_mask, u32 long_mask);
2825 2826 2827
void intel_hpd_init(struct drm_i915_private *dev_priv);
void intel_hpd_init_work(struct drm_i915_private *dev_priv);
void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2828
bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2829 2830
bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2831

L
Linus Torvalds 已提交
2832
/* i915_irq.c */
2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849
static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
{
	unsigned long delay;

	if (unlikely(!i915.enable_hangcheck))
		return;

	/* Don't continually defer the hangcheck so that it is always run at
	 * least once after work has been scheduled on any ring. Otherwise,
	 * we will ignore a hung ring if a second ring is kept busy.
	 */

	delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
	queue_delayed_work(system_long_wq,
			   &dev_priv->gpu_error.hangcheck_work, delay);
}

2850
__printf(3, 4)
2851 2852
void i915_handle_error(struct drm_i915_private *dev_priv,
		       u32 engine_mask,
2853
		       const char *fmt, ...);
L
Linus Torvalds 已提交
2854

2855
extern void intel_irq_init(struct drm_i915_private *dev_priv);
2856 2857
int intel_irq_install(struct drm_i915_private *dev_priv);
void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2858

2859 2860
extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
2861
					bool restore_forcewake);
2862
extern void intel_uncore_init(struct drm_i915_private *dev_priv);
2863
extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
2864
extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
2865 2866 2867
extern void intel_uncore_fini(struct drm_i915_private *dev_priv);
extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
					 bool restore);
2868
const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2869
void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2870
				enum forcewake_domains domains);
2871
void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2872
				enum forcewake_domains domains);
2873 2874 2875 2876 2877 2878 2879
/* Like above but the caller must manage the uncore.lock itself.
 * Must be used with I915_READ_FW and friends.
 */
void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
					enum forcewake_domains domains);
void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
					enum forcewake_domains domains);
2880 2881
u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);

2882
void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2883

2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894
int intel_wait_for_register(struct drm_i915_private *dev_priv,
			    i915_reg_t reg,
			    const u32 mask,
			    const u32 value,
			    const unsigned long timeout_ms);
int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
			       i915_reg_t reg,
			       const u32 mask,
			       const u32 value,
			       const unsigned long timeout_ms);

2895 2896
static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
{
2897
	return dev_priv->gvt;
2898 2899
}

2900
static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2901
{
2902
	return dev_priv->vgpu.active;
2903
}
2904

2905
void
2906
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2907
		     u32 status_mask);
2908 2909

void
2910
i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2911
		      u32 status_mask);
2912

2913 2914
void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2915 2916 2917
void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
				   uint32_t mask,
				   uint32_t bits);
2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930
void ilk_update_display_irq(struct drm_i915_private *dev_priv,
			    uint32_t interrupt_mask,
			    uint32_t enabled_irq_mask);
static inline void
ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, bits);
}
static inline void
ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, 0);
}
2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 2944
void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
			 enum pipe pipe,
			 uint32_t interrupt_mask,
			 uint32_t enabled_irq_mask);
static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
				       enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
}
static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
					enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
}
2945 2946 2947
void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
				  uint32_t interrupt_mask,
				  uint32_t enabled_irq_mask);
2948 2949 2950 2951 2952 2953 2954 2955 2956 2957 2958
static inline void
ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, bits);
}
static inline void
ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, 0);
}

2959 2960 2961 2962 2963 2964 2965 2966 2967
/* i915_gem.c */
int i915_gem_create_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2968 2969
int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2970 2971 2972 2973 2974 2975
int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
			     struct drm_file *file_priv);
int i915_gem_execbuffer(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
J
Jesse Barnes 已提交
2976 2977
int i915_gem_execbuffer2(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
2978 2979
int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
B
Ben Widawsky 已提交
2980 2981 2982 2983
int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
2984 2985
int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *file_priv);
2986 2987
int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
2988 2989 2990 2991
int i915_gem_set_tiling(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
int i915_gem_get_tiling(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2992
void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
2993 2994
int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file);
2995 2996
int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
2997 2998
int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2999 3000
int i915_gem_load_init(struct drm_i915_private *dev_priv);
void i915_gem_load_cleanup(struct drm_i915_private *dev_priv);
3001
void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3002
int i915_gem_freeze(struct drm_i915_private *dev_priv);
3003 3004
int i915_gem_freeze_late(struct drm_i915_private *dev_priv);

3005
void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
3006
void i915_gem_object_free(struct drm_i915_gem_object *obj);
3007 3008
void i915_gem_object_init(struct drm_i915_gem_object *obj,
			 const struct drm_i915_gem_object_ops *ops);
3009 3010 3011 3012 3013
struct drm_i915_gem_object *
i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
struct drm_i915_gem_object *
i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
				 const void *data, size_t size);
3014
void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
3015
void i915_gem_free_object(struct drm_gem_object *obj);
3016

C
Chris Wilson 已提交
3017
struct i915_vma * __must_check
3018 3019
i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
			 const struct i915_ggtt_view *view,
3020
			 u64 size,
3021 3022
			 u64 alignment,
			 u64 flags);
3023

3024
int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
3025
void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3026

3027 3028
void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);

C
Chris Wilson 已提交
3029
static inline int __sg_page_count(const struct scatterlist *sg)
3030
{
3031 3032
	return sg->length >> PAGE_SHIFT;
}
3033

3034 3035 3036
struct scatterlist *
i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
		       unsigned int n, unsigned int *offset);
3037

3038 3039 3040
struct page *
i915_gem_object_get_page(struct drm_i915_gem_object *obj,
			 unsigned int n);
3041

3042 3043 3044
struct page *
i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
			       unsigned int n);
3045

3046 3047 3048
dma_addr_t
i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
				unsigned long n);
3049

3050 3051
void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
				 struct sg_table *pages);
C
Chris Wilson 已提交
3052 3053 3054 3055 3056
int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);

static inline int __must_check
i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
{
3057
	might_lock(&obj->mm.lock);
C
Chris Wilson 已提交
3058

3059
	if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
C
Chris Wilson 已提交
3060 3061 3062 3063 3064 3065 3066
		return 0;

	return __i915_gem_object_get_pages(obj);
}

static inline void
__i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3067
{
C
Chris Wilson 已提交
3068 3069
	GEM_BUG_ON(!obj->mm.pages);

3070
	atomic_inc(&obj->mm.pages_pin_count);
C
Chris Wilson 已提交
3071 3072 3073 3074 3075
}

static inline bool
i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
{
3076
	return atomic_read(&obj->mm.pages_pin_count);
C
Chris Wilson 已提交
3077 3078 3079 3080 3081 3082 3083 3084
}

static inline void
__i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
{
	GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
	GEM_BUG_ON(!obj->mm.pages);

3085 3086
	atomic_dec(&obj->mm.pages_pin_count);
	GEM_BUG_ON(atomic_read(&obj->mm.pages_pin_count) < obj->bind_count);
3087
}
3088

3089 3090
static inline void
i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3091
{
C
Chris Wilson 已提交
3092
	__i915_gem_object_unpin_pages(obj);
3093 3094
}

3095 3096 3097 3098 3099 3100 3101
enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
	I915_MM_NORMAL = 0,
	I915_MM_SHRINKER
};

void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
				 enum i915_mm_subclass subclass);
3102
void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
C
Chris Wilson 已提交
3103

3104 3105 3106 3107 3108
enum i915_map_type {
	I915_MAP_WB = 0,
	I915_MAP_WC,
};

3109 3110 3111
/**
 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
 * @obj - the object to map into kernel address space
3112
 * @type - the type of mapping, used to select pgprot_t
3113 3114 3115
 *
 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
 * pages and then returns a contiguous mapping of the backing storage into
3116 3117
 * the kernel address space. Based on the @type of mapping, the PTE will be
 * set to either WriteBack or WriteCombine (via pgprot_t).
3118
 *
3119 3120
 * The caller is responsible for calling i915_gem_object_unpin_map() when the
 * mapping is no longer required.
3121
 *
3122 3123
 * Returns the pointer through which to access the mapped object, or an
 * ERR_PTR() on error.
3124
 */
3125 3126
void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
					   enum i915_map_type type);
3127 3128 3129 3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141

/**
 * i915_gem_object_unpin_map - releases an earlier mapping
 * @obj - the object to unmap
 *
 * After pinning the object and mapping its pages, once you are finished
 * with your access, call i915_gem_object_unpin_map() to release the pin
 * upon the mapping. Once the pin count reaches zero, that mapping may be
 * removed.
 */
static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
{
	i915_gem_object_unpin_pages(obj);
}

3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152 3153 3154 3155
int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
				    unsigned int *needs_clflush);
int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
				     unsigned int *needs_clflush);
#define CLFLUSH_BEFORE 0x1
#define CLFLUSH_AFTER 0x2
#define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)

static inline void
i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
{
	i915_gem_object_unpin_pages(obj);
}

3156
int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
B
Ben Widawsky 已提交
3157
void i915_vma_move_to_active(struct i915_vma *vma,
3158 3159
			     struct drm_i915_gem_request *req,
			     unsigned int flags);
3160 3161 3162
int i915_gem_dumb_create(struct drm_file *file_priv,
			 struct drm_device *dev,
			 struct drm_mode_create_dumb *args);
3163 3164
int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
		      uint32_t handle, uint64_t *offset);
3165
int i915_gem_mmap_gtt_version(void);
3166 3167 3168 3169 3170

void i915_gem_track_fb(struct drm_i915_gem_object *old,
		       struct drm_i915_gem_object *new,
		       unsigned frontbuffer_bits);

3171
int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3172

3173
struct drm_i915_gem_request *
3174
i915_gem_find_active_request(struct intel_engine_cs *engine);
3175

3176
void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3177

3178 3179
static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
{
3180
	return unlikely(test_bit(I915_RESET_IN_PROGRESS, &error->flags));
3181 3182
}

3183
static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3184
{
3185
	return unlikely(test_bit(I915_WEDGED, &error->flags));
3186 3187
}

3188
static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error)
3189
{
3190
	return i915_reset_in_progress(error) | i915_terminally_wedged(error);
M
Mika Kuoppala 已提交
3191 3192 3193 3194
}

static inline u32 i915_reset_count(struct i915_gpu_error *error)
{
3195
	return READ_ONCE(error->reset_count);
3196
}
3197

3198 3199
void i915_gem_reset(struct drm_i915_private *dev_priv);
void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3200
void i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3201 3202
int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3203
void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3204
void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3205
int __must_check i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3206
					unsigned int flags);
3207 3208
int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
void i915_gem_resume(struct drm_i915_private *dev_priv);
3209
int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3210 3211 3212 3213
int i915_gem_object_wait(struct drm_i915_gem_object *obj,
			 unsigned int flags,
			 long timeout,
			 struct intel_rps_client *rps);
3214 3215 3216 3217 3218
int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
				  unsigned int flags,
				  int priority);
#define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX

3219
int __must_check
3220 3221 3222
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
				  bool write);
int __must_check
3223
i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
C
Chris Wilson 已提交
3224
struct i915_vma * __must_check
3225 3226
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
				     u32 alignment,
3227
				     const struct i915_ggtt_view *view);
C
Chris Wilson 已提交
3228
void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3229
int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3230
				int align);
3231
int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3232
void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3233

3234 3235 3236
u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, u64 size,
			   int tiling_mode);
u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size,
3237
				int tiling_mode, bool fenced);
3238

3239 3240 3241
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
				    enum i915_cache_level cache_level);

3242 3243 3244 3245 3246 3247
struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
				struct dma_buf *dma_buf);

struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
				struct drm_gem_object *gem_obj, int flags);

3248
struct i915_vma *
3249
i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
C
Chris Wilson 已提交
3250 3251
		     struct i915_address_space *vm,
		     const struct i915_ggtt_view *view);
3252

3253 3254
struct i915_vma *
i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
C
Chris Wilson 已提交
3255 3256
				  struct i915_address_space *vm,
				  const struct i915_ggtt_view *view);
3257

3258 3259 3260 3261 3262 3263
static inline struct i915_hw_ppgtt *
i915_vm_to_ppgtt(struct i915_address_space *vm)
{
	return container_of(vm, struct i915_hw_ppgtt, base);
}

C
Chris Wilson 已提交
3264 3265 3266
static inline struct i915_vma *
i915_gem_object_to_ggtt(struct drm_i915_gem_object *obj,
			const struct i915_ggtt_view *view)
3267
{
C
Chris Wilson 已提交
3268
	return i915_gem_obj_to_vma(obj, &to_i915(obj->base.dev)->ggtt.base, view);
3269 3270
}

C
Chris Wilson 已提交
3271 3272 3273
static inline unsigned long
i915_gem_object_ggtt_offset(struct drm_i915_gem_object *o,
			    const struct i915_ggtt_view *view)
3274
{
3275
	return i915_ggtt_offset(i915_gem_object_to_ggtt(o, view));
3276
}
3277

J
Joonas Lahtinen 已提交
3278
/* i915_gem_fence_reg.c */
3279 3280 3281
int __must_check i915_vma_get_fence(struct i915_vma *vma);
int __must_check i915_vma_put_fence(struct i915_vma *vma);

3282
void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3283

3284
void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3285 3286 3287 3288
void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
				       struct sg_table *pages);
void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
					 struct sg_table *pages);
3289

3290
/* i915_gem_context.c */
3291
int __must_check i915_gem_context_init(struct drm_i915_private *dev_priv);
3292
void i915_gem_context_lost(struct drm_i915_private *dev_priv);
3293
void i915_gem_context_fini(struct drm_i915_private *dev_priv);
3294
int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3295
void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3296
int i915_switch_context(struct drm_i915_gem_request *req);
3297
int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv);
3298 3299 3300
struct i915_vma *
i915_gem_context_pin_legacy(struct i915_gem_context *ctx,
			    unsigned int flags);
3301
void i915_gem_context_free(struct kref *ctx_ref);
3302 3303
struct i915_gem_context *
i915_gem_context_create_gvt(struct drm_device *dev);
3304 3305 3306 3307 3308 3309

static inline struct i915_gem_context *
i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
{
	struct i915_gem_context *ctx;

3310
	lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
3311 3312 3313 3314 3315 3316 3317 3318

	ctx = idr_find(&file_priv->context_idr, id);
	if (!ctx)
		return ERR_PTR(-ENOENT);

	return ctx;
}

3319 3320
static inline struct i915_gem_context *
i915_gem_context_get(struct i915_gem_context *ctx)
3321
{
3322
	kref_get(&ctx->ref);
3323
	return ctx;
3324 3325
}

3326
static inline void i915_gem_context_put(struct i915_gem_context *ctx)
3327
{
3328
	lockdep_assert_held(&ctx->i915->drm.struct_mutex);
3329
	kref_put(&ctx->ref, i915_gem_context_free);
3330 3331
}

C
Chris Wilson 已提交
3332 3333 3334 3335 3336 3337 3338 3339 3340 3341
static inline struct intel_timeline *
i915_gem_context_lookup_timeline(struct i915_gem_context *ctx,
				 struct intel_engine_cs *engine)
{
	struct i915_address_space *vm;

	vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base;
	return &vm->timeline.engine[engine->id];
}

3342
static inline bool i915_gem_context_is_default(const struct i915_gem_context *c)
3343
{
3344
	return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3345 3346
}

3347 3348 3349 3350
int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
				  struct drm_file *file);
int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
				   struct drm_file *file);
3351 3352 3353 3354
int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
				    struct drm_file *file_priv);
int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
				    struct drm_file *file_priv);
3355 3356
int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data,
				       struct drm_file *file);
3357

3358 3359 3360
int i915_perf_open_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file);

3361
/* i915_gem_evict.c */
3362
int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3363
					  u64 min_size, u64 alignment,
3364
					  unsigned cache_level,
3365
					  u64 start, u64 end,
3366
					  unsigned flags);
3367 3368
int __must_check i915_gem_evict_for_vma(struct i915_vma *vma,
					unsigned int flags);
3369
int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3370

3371
/* belongs in i915_gem_gtt.h */
3372
static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3373
{
3374
	wmb();
3375
	if (INTEL_GEN(dev_priv) < 6)
3376 3377
		intel_gtt_chipset_flush();
}
3378

3379
/* i915_gem_stolen.c */
3380 3381 3382
int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
				struct drm_mm_node *node, u64 size,
				unsigned alignment);
3383 3384 3385 3386
int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
					 struct drm_mm_node *node, u64 size,
					 unsigned alignment, u64 start,
					 u64 end);
3387 3388
void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
				 struct drm_mm_node *node);
3389
int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3390
void i915_gem_cleanup_stolen(struct drm_device *dev);
3391
struct drm_i915_gem_object *
3392
i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, u32 size);
3393
struct drm_i915_gem_object *
3394
i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3395 3396 3397
					       u32 stolen_offset,
					       u32 gtt_offset,
					       u32 size);
3398

3399 3400 3401 3402 3403
/* i915_gem_internal.c */
struct drm_i915_gem_object *
i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
				unsigned int size);

3404 3405
/* i915_gem_shrinker.c */
unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3406
			      unsigned long target,
3407 3408 3409 3410
			      unsigned flags);
#define I915_SHRINK_PURGEABLE 0x1
#define I915_SHRINK_UNBOUND 0x2
#define I915_SHRINK_BOUND 0x4
3411
#define I915_SHRINK_ACTIVE 0x8
3412
#define I915_SHRINK_VMAPS 0x10
3413 3414
unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3415
void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3416 3417


3418
/* i915_gem_tiling.c */
3419
static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3420
{
3421
	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3422 3423

	return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3424
		i915_gem_object_is_tiled(obj);
3425 3426
}

3427
/* i915_debugfs.c */
3428
#ifdef CONFIG_DEBUG_FS
3429 3430
int i915_debugfs_register(struct drm_i915_private *dev_priv);
void i915_debugfs_unregister(struct drm_i915_private *dev_priv);
J
Jani Nikula 已提交
3431
int i915_debugfs_connector_add(struct drm_connector *connector);
3432
void intel_display_crc_init(struct drm_i915_private *dev_priv);
3433
#else
3434 3435
static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
static inline void i915_debugfs_unregister(struct drm_i915_private *dev_priv) {}
3436 3437
static inline int i915_debugfs_connector_add(struct drm_connector *connector)
{ return 0; }
3438
static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3439
#endif
3440 3441

/* i915_gpu_error.c */
3442 3443
#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)

3444 3445
__printf(2, 3)
void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3446 3447
int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
			    const struct i915_error_state_file_priv *error);
3448
int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3449
			      struct drm_i915_private *i915,
3450 3451 3452 3453 3454 3455
			      size_t count, loff_t pos);
static inline void i915_error_state_buf_release(
	struct drm_i915_error_state_buf *eb)
{
	kfree(eb->buf);
}
3456 3457
void i915_capture_error_state(struct drm_i915_private *dev_priv,
			      u32 engine_mask,
3458
			      const char *error_msg);
3459 3460 3461
void i915_error_state_get(struct drm_device *dev,
			  struct i915_error_state_file_priv *error_priv);
void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3462
void i915_destroy_error_state(struct drm_i915_private *dev_priv);
3463

3464 3465 3466 3467 3468 3469 3470 3471
#else

static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
					    u32 engine_mask,
					    const char *error_msg)
{
}

3472
static inline void i915_destroy_error_state(struct drm_i915_private *dev_priv)
3473 3474 3475 3476 3477
{
}

#endif

3478
const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3479

3480
/* i915_cmd_parser.c */
3481
int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3482
void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3483 3484 3485 3486 3487 3488 3489
void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
int intel_engine_cmd_parser(struct intel_engine_cs *engine,
			    struct drm_i915_gem_object *batch_obj,
			    struct drm_i915_gem_object *shadow_batch_obj,
			    u32 batch_start_offset,
			    u32 batch_len,
			    bool is_master);
3490

3491 3492 3493
/* i915_perf.c */
extern void i915_perf_init(struct drm_i915_private *dev_priv);
extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3494 3495
extern void i915_perf_register(struct drm_i915_private *dev_priv);
extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3496

3497
/* i915_suspend.c */
3498 3499
extern int i915_save_state(struct drm_i915_private *dev_priv);
extern int i915_restore_state(struct drm_i915_private *dev_priv);
3500

B
Ben Widawsky 已提交
3501
/* i915_sysfs.c */
D
David Weinehall 已提交
3502 3503
void i915_setup_sysfs(struct drm_i915_private *dev_priv);
void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
B
Ben Widawsky 已提交
3504

3505
/* intel_i2c.c */
3506 3507
extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3508 3509
extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
				     unsigned int pin);
3510

3511 3512
extern struct i2c_adapter *
intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
C
Chris Wilson 已提交
3513 3514
extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3515
static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3516 3517 3518
{
	return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
}
3519
extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3520

3521
/* intel_bios.c */
3522
int intel_bios_init(struct drm_i915_private *dev_priv);
J
Jani Nikula 已提交
3523
bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3524
bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3525
bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3526
bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3527
bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3528
bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3529
bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3530 3531
bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
				     enum port port);
3532 3533 3534
bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
				enum port port);

3535

3536
/* intel_opregion.c */
3537
#ifdef CONFIG_ACPI
3538
extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3539 3540
extern void intel_opregion_register(struct drm_i915_private *dev_priv);
extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3541
extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3542 3543
extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
					 bool enable);
3544
extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3545
					 pci_power_t state);
3546
extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3547
#else
3548
static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3549 3550
static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
3551 3552 3553
static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
{
}
3554 3555 3556 3557 3558
static inline int
intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
{
	return 0;
}
3559
static inline int
3560
intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3561 3562 3563
{
	return 0;
}
3564
static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3565 3566 3567
{
	return -ENODEV;
}
3568
#endif
3569

J
Jesse Barnes 已提交
3570 3571 3572 3573 3574 3575 3576 3577 3578
/* intel_acpi.c */
#ifdef CONFIG_ACPI
extern void intel_register_dsm_handler(void);
extern void intel_unregister_dsm_handler(void);
#else
static inline void intel_register_dsm_handler(void) { return; }
static inline void intel_unregister_dsm_handler(void) { return; }
#endif /* CONFIG_ACPI */

3579 3580 3581 3582 3583 3584 3585
/* intel_device_info.c */
static inline struct intel_device_info *
mkwrite_device_info(struct drm_i915_private *dev_priv)
{
	return (struct intel_device_info *)&dev_priv->info;
}

3586
const char *intel_platform_name(enum intel_platform platform);
3587 3588 3589
void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
void intel_device_info_dump(struct drm_i915_private *dev_priv);

J
Jesse Barnes 已提交
3590
/* modesetting */
3591
extern void intel_modeset_init_hw(struct drm_device *dev);
3592
extern int intel_modeset_init(struct drm_device *dev);
3593
extern void intel_modeset_gem_init(struct drm_device *dev);
J
Jesse Barnes 已提交
3594
extern void intel_modeset_cleanup(struct drm_device *dev);
3595
extern int intel_connector_register(struct drm_connector *);
3596
extern void intel_connector_unregister(struct drm_connector *);
3597 3598
extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
				       bool state);
3599
extern void intel_display_resume(struct drm_device *dev);
3600 3601
extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3602
extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3603
extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3604
extern void intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3605
extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3606
				  bool enable);
3607

B
Ben Widawsky 已提交
3608 3609
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file);
3610

3611
/* overlay */
3612 3613
extern struct intel_overlay_error_state *
intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3614 3615
extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
					    struct intel_overlay_error_state *error);
3616

3617 3618
extern struct intel_display_error_state *
intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3619
extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3620
					    struct drm_i915_private *dev_priv,
3621
					    struct intel_display_error_state *error);
3622

3623 3624
int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3625 3626

/* intel_sideband.c */
3627 3628
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3629
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3630 3631
u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3632 3633 3634 3635
u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3636 3637
u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3638 3639
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3640 3641 3642 3643
u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
		   enum intel_sbi_destination destination);
void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
		     enum intel_sbi_destination destination);
3644 3645
u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3646

3647
/* intel_dpio_phy.c */
3648
void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3649
			     enum dpio_phy *phy, enum dpio_channel *ch);
3650 3651 3652
void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
				  enum port port, u32 margin, u32 scale,
				  u32 enable, u32 deemphasis);
3653 3654 3655 3656 3657 3658 3659 3660 3661 3662 3663 3664
void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
			    enum dpio_phy phy);
bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
			      enum dpio_phy phy);
uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
					     uint8_t lane_count);
void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
				     uint8_t lane_lat_optim_mask);
uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);

3665 3666 3667
void chv_set_phy_signal_level(struct intel_encoder *encoder,
			      u32 deemph_reg_value, u32 margin_reg_value,
			      bool uniq_trans_scale);
3668 3669
void chv_data_lane_soft_reset(struct intel_encoder *encoder,
			      bool reset);
3670
void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3671 3672
void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3673
void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3674

3675 3676 3677
void vlv_set_phy_signal_level(struct intel_encoder *encoder,
			      u32 demph_reg_value, u32 preemph_reg_value,
			      u32 uniqtranscale_reg_value, u32 tx3_demph);
3678
void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3679
void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3680
void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3681

3682 3683
int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3684

3685 3686 3687 3688 3689 3690 3691 3692 3693 3694 3695 3696 3697
#define I915_READ8(reg)		dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
#define I915_WRITE8(reg, val)	dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)

#define I915_READ16(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
#define I915_WRITE16(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
#define I915_READ16_NOTRACE(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
#define I915_WRITE16_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)

#define I915_READ(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
#define I915_WRITE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
#define I915_READ_NOTRACE(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
#define I915_WRITE_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)

3698 3699 3700 3701
/* Be very careful with read/write 64-bit values. On 32-bit machines, they
 * will be implemented using 2 32-bit writes in an arbitrary order with
 * an arbitrary delay between them. This can cause the hardware to
 * act upon the intermediate value, possibly leading to corruption and
3702 3703 3704 3705 3706 3707 3708 3709 3710
 * machine death. For this reason we do not support I915_WRITE64, or
 * dev_priv->uncore.funcs.mmio_writeq.
 *
 * When reading a 64-bit value as two 32-bit values, the delay may cause
 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
 * occasionally a 64-bit register does not actualy support a full readq
 * and must be read using two 32-bit reads.
 *
 * You have been warned.
3711
 */
3712
#define I915_READ64(reg)	dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3713

3714
#define I915_READ64_2x32(lower_reg, upper_reg) ({			\
3715 3716
	u32 upper, lower, old_upper, loop = 0;				\
	upper = I915_READ(upper_reg);					\
3717
	do {								\
3718
		old_upper = upper;					\
3719
		lower = I915_READ(lower_reg);				\
3720 3721
		upper = I915_READ(upper_reg);				\
	} while (upper != old_upper && loop++ < 2);			\
3722
	(u64)upper << 32 | lower; })
3723

3724 3725 3726
#define POSTING_READ(reg)	(void)I915_READ_NOTRACE(reg)
#define POSTING_READ16(reg)	(void)I915_READ16_NOTRACE(reg)

3727 3728
#define __raw_read(x, s) \
static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3729
					     i915_reg_t reg) \
3730
{ \
3731
	return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3732 3733 3734 3735
}

#define __raw_write(x, s) \
static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3736
				       i915_reg_t reg, uint##x##_t val) \
3737
{ \
3738
	write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3739 3740 3741 3742 3743 3744 3745 3746 3747 3748 3749 3750 3751 3752
}
__raw_read(8, b)
__raw_read(16, w)
__raw_read(32, l)
__raw_read(64, q)

__raw_write(8, b)
__raw_write(16, w)
__raw_write(32, l)
__raw_write(64, q)

#undef __raw_read
#undef __raw_write

3753
/* These are untraced mmio-accessors that are only valid to be used inside
3754
 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3755
 * controlled.
3756
 *
3757
 * Think twice, and think again, before using these.
3758 3759 3760 3761 3762 3763 3764 3765 3766 3767 3768 3769 3770 3771 3772 3773 3774 3775 3776 3777
 *
 * As an example, these accessors can possibly be used between:
 *
 * spin_lock_irq(&dev_priv->uncore.lock);
 * intel_uncore_forcewake_get__locked();
 *
 * and
 *
 * intel_uncore_forcewake_put__locked();
 * spin_unlock_irq(&dev_priv->uncore.lock);
 *
 *
 * Note: some registers may not need forcewake held, so
 * intel_uncore_forcewake_{get,put} can be omitted, see
 * intel_uncore_forcewake_for_reg().
 *
 * Certain architectures will die if the same cacheline is concurrently accessed
 * by different clients (e.g. on Ivybridge). Access to registers should
 * therefore generally be serialised, by either the dev_priv->uncore.lock or
 * a more localised lock guarding all access to that bank of registers.
3778
 */
3779 3780
#define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3781
#define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3782 3783
#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)

3784 3785 3786 3787
/* "Broadcast RGB" property */
#define INTEL_BROADCAST_RGB_AUTO 0
#define INTEL_BROADCAST_RGB_FULL 1
#define INTEL_BROADCAST_RGB_LIMITED 2
3788

3789
static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
3790
{
3791
	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3792
		return VLV_VGACNTRL;
3793
	else if (INTEL_GEN(dev_priv) >= 5)
3794
		return CPU_VGACNTRL;
3795 3796 3797 3798
	else
		return VGACNTRL;
}

3799 3800 3801 3802 3803 3804 3805
static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
{
	unsigned long j = msecs_to_jiffies(m);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

3806 3807 3808 3809 3810
static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
{
        return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
}

3811 3812 3813 3814 3815 3816 3817 3818
static inline unsigned long
timespec_to_jiffies_timeout(const struct timespec *value)
{
	unsigned long j = timespec_to_jiffies(value);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

3819 3820 3821 3822 3823 3824 3825 3826 3827
/*
 * If you need to wait X milliseconds between events A and B, but event B
 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
 * when event A happened, then just before event B you call this function and
 * pass the timestamp as the first argument, and X as the second argument.
 */
static inline void
wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
{
3828
	unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3829 3830 3831 3832 3833 3834 3835 3836 3837 3838

	/*
	 * Don't re-read the value of "jiffies" every time since it may change
	 * behind our back and break the math.
	 */
	tmp_jiffies = jiffies;
	target_jiffies = timestamp_jiffies +
			 msecs_to_jiffies_timeout(to_wait_ms);

	if (time_after(target_jiffies, tmp_jiffies)) {
3839 3840 3841 3842
		remaining_jiffies = target_jiffies - tmp_jiffies;
		while (remaining_jiffies)
			remaining_jiffies =
			    schedule_timeout_uninterruptible(remaining_jiffies);
3843 3844
	}
}
3845 3846 3847

static inline bool
__i915_request_irq_complete(struct drm_i915_gem_request *req)
3848
{
3849 3850
	struct intel_engine_cs *engine = req->engine;

3851 3852 3853
	/* Before we do the heavier coherent read of the seqno,
	 * check the value (hopefully) in the CPU cacheline.
	 */
3854
	if (__i915_gem_request_completed(req))
3855 3856
		return true;

3857 3858 3859 3860 3861 3862 3863 3864 3865 3866 3867
	/* Ensure our read of the seqno is coherent so that we
	 * do not "miss an interrupt" (i.e. if this is the last
	 * request and the seqno write from the GPU is not visible
	 * by the time the interrupt fires, we will see that the
	 * request is incomplete and go back to sleep awaiting
	 * another interrupt that will never come.)
	 *
	 * Strictly, we only need to do this once after an interrupt,
	 * but it is easier and safer to do it every time the waiter
	 * is woken.
	 */
3868
	if (engine->irq_seqno_barrier &&
3869
	    rcu_access_pointer(engine->breadcrumbs.irq_seqno_bh) == current &&
3870
	    cmpxchg_relaxed(&engine->breadcrumbs.irq_posted, 1, 0)) {
3871 3872
		struct task_struct *tsk;

3873 3874 3875 3876 3877 3878 3879 3880 3881 3882 3883 3884
		/* The ordering of irq_posted versus applying the barrier
		 * is crucial. The clearing of the current irq_posted must
		 * be visible before we perform the barrier operation,
		 * such that if a subsequent interrupt arrives, irq_posted
		 * is reasserted and our task rewoken (which causes us to
		 * do another __i915_request_irq_complete() immediately
		 * and reapply the barrier). Conversely, if the clear
		 * occurs after the barrier, then an interrupt that arrived
		 * whilst we waited on the barrier would not trigger a
		 * barrier on the next pass, and the read may not see the
		 * seqno update.
		 */
3885
		engine->irq_seqno_barrier(engine);
3886 3887 3888 3889 3890 3891 3892 3893

		/* If we consume the irq, but we are no longer the bottom-half,
		 * the real bottom-half may not have serialised their own
		 * seqno check with the irq-barrier (i.e. may have inspected
		 * the seqno before we believe it coherent since they see
		 * irq_posted == false but we are still running).
		 */
		rcu_read_lock();
3894
		tsk = rcu_dereference(engine->breadcrumbs.irq_seqno_bh);
3895 3896 3897 3898 3899 3900 3901 3902 3903 3904
		if (tsk && tsk != current)
			/* Note that if the bottom-half is changed as we
			 * are sending the wake-up, the new bottom-half will
			 * be woken by whomever made the change. We only have
			 * to worry about when we steal the irq-posted for
			 * ourself.
			 */
			wake_up_process(tsk);
		rcu_read_unlock();

3905
		if (__i915_gem_request_completed(req))
3906 3907
			return true;
	}
3908 3909 3910 3911

	return false;
}

3912 3913 3914
void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);

3915 3916 3917 3918 3919
/* i915_mm.c */
int remap_io_mapping(struct vm_area_struct *vma,
		     unsigned long addr, unsigned long pfn, unsigned long size,
		     struct io_mapping *iomap);

3920 3921 3922 3923 3924
#define ptr_mask_bits(ptr) ({						\
	unsigned long __v = (unsigned long)(ptr);			\
	(typeof(ptr))(__v & PAGE_MASK);					\
})

3925 3926 3927 3928 3929 3930 3931 3932 3933
#define ptr_unpack_bits(ptr, bits) ({					\
	unsigned long __v = (unsigned long)(ptr);			\
	(bits) = __v & ~PAGE_MASK;					\
	(typeof(ptr))(__v & PAGE_MASK);					\
})

#define ptr_pack_bits(ptr, bits)					\
	((typeof(ptr))((unsigned long)(ptr) | (bits)))

3934 3935 3936 3937 3938 3939
#define fetch_and_zero(ptr) ({						\
	typeof(*ptr) __T = *(ptr);					\
	*(ptr) = (typeof(*ptr))0;					\
	__T;								\
})

L
Linus Torvalds 已提交
3940
#endif