i915_drv.h 117.1 KB
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/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
 */
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/*
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 *
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#ifndef _I915_DRV_H_
#define _I915_DRV_H_

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#include <uapi/drm/i915_drm.h>
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#include <uapi/drm/drm_fourcc.h>
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#include <linux/io-mapping.h>
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include <linux/backlight.h>
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#include <linux/hashtable.h>
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#include <linux/intel-iommu.h>
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#include <linux/kref.h>
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#include <linux/pm_qos.h>
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#include <linux/shmem_fs.h>

#include <drm/drmP.h>
#include <drm/intel-gtt.h>
#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
#include <drm/drm_gem.h>
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#include <drm/drm_auth.h>
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#include "i915_params.h"
#include "i915_reg.h"

#include "intel_bios.h"
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#include "intel_dpll_mgr.h"
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#include "intel_guc.h"
#include "intel_lrc.h"
#include "intel_ringbuffer.h"

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#include "i915_gem.h"
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#include "i915_gem_gtt.h"
#include "i915_gem_render_state.h"
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#include "i915_gem_request.h"
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#include "intel_gvt.h"

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/* General customization:
 */

#define DRIVER_NAME		"i915"
#define DRIVER_DESC		"Intel Graphics"
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#define DRIVER_DATE		"20160725"
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#undef WARN_ON
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/* Many gcc seem to no see through this and fall over :( */
#if 0
#define WARN_ON(x) ({ \
	bool __i915_warn_cond = (x); \
	if (__builtin_constant_p(__i915_warn_cond)) \
		BUILD_BUG_ON(__i915_warn_cond); \
	WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
#else
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#define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
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#endif

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#undef WARN_ON_ONCE
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#define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
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#define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
			     (long) (x), __func__);
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/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
 * which may not necessarily be a user visible problem.  This will either
 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
 * enable distros and users to tailor their preferred amount of i915 abrt
 * spam.
 */
#define I915_STATE_WARN(condition, format...) ({			\
	int __ret_warn_on = !!(condition);				\
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	if (unlikely(__ret_warn_on))					\
		if (!WARN(i915.verbose_state_checks, format))		\
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			DRM_ERROR(format);				\
	unlikely(__ret_warn_on);					\
})

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#define I915_STATE_WARN_ON(x)						\
	I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
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bool __i915_inject_load_failure(const char *func, int line);
#define i915_inject_load_failure() \
	__i915_inject_load_failure(__func__, __LINE__)

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static inline const char *yesno(bool v)
{
	return v ? "yes" : "no";
}

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static inline const char *onoff(bool v)
{
	return v ? "on" : "off";
}

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enum pipe {
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	INVALID_PIPE = -1,
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	PIPE_A = 0,
	PIPE_B,
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	PIPE_C,
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	_PIPE_EDP,
	I915_MAX_PIPES = _PIPE_EDP
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};
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#define pipe_name(p) ((p) + 'A')
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enum transcoder {
	TRANSCODER_A = 0,
	TRANSCODER_B,
	TRANSCODER_C,
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	TRANSCODER_EDP,
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	TRANSCODER_DSI_A,
	TRANSCODER_DSI_C,
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	I915_MAX_TRANSCODERS
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};
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static inline const char *transcoder_name(enum transcoder transcoder)
{
	switch (transcoder) {
	case TRANSCODER_A:
		return "A";
	case TRANSCODER_B:
		return "B";
	case TRANSCODER_C:
		return "C";
	case TRANSCODER_EDP:
		return "EDP";
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	case TRANSCODER_DSI_A:
		return "DSI A";
	case TRANSCODER_DSI_C:
		return "DSI C";
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	default:
		return "<invalid>";
	}
}
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static inline bool transcoder_is_dsi(enum transcoder transcoder)
{
	return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
}

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/*
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 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
 * number of planes per CRTC.  Not all platforms really have this many planes,
 * which means some arrays of size I915_MAX_PLANES may have unused entries
 * between the topmost sprite plane and the cursor plane.
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 */
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enum plane {
	PLANE_A = 0,
	PLANE_B,
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	PLANE_C,
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	PLANE_CURSOR,
	I915_MAX_PLANES,
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};
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#define plane_name(p) ((p) + 'A')
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#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
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enum port {
	PORT_A = 0,
	PORT_B,
	PORT_C,
	PORT_D,
	PORT_E,
	I915_MAX_PORTS
};
#define port_name(p) ((p) + 'A')

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#define I915_NUM_PHYS_VLV 2
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enum dpio_channel {
	DPIO_CH0,
	DPIO_CH1
};

enum dpio_phy {
	DPIO_PHY0,
	DPIO_PHY1
};

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enum intel_display_power_domain {
	POWER_DOMAIN_PIPE_A,
	POWER_DOMAIN_PIPE_B,
	POWER_DOMAIN_PIPE_C,
	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
	POWER_DOMAIN_TRANSCODER_A,
	POWER_DOMAIN_TRANSCODER_B,
	POWER_DOMAIN_TRANSCODER_C,
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	POWER_DOMAIN_TRANSCODER_EDP,
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	POWER_DOMAIN_TRANSCODER_DSI_A,
	POWER_DOMAIN_TRANSCODER_DSI_C,
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	POWER_DOMAIN_PORT_DDI_A_LANES,
	POWER_DOMAIN_PORT_DDI_B_LANES,
	POWER_DOMAIN_PORT_DDI_C_LANES,
	POWER_DOMAIN_PORT_DDI_D_LANES,
	POWER_DOMAIN_PORT_DDI_E_LANES,
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	POWER_DOMAIN_PORT_DSI,
	POWER_DOMAIN_PORT_CRT,
	POWER_DOMAIN_PORT_OTHER,
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	POWER_DOMAIN_VGA,
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	POWER_DOMAIN_AUDIO,
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	POWER_DOMAIN_PLLS,
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	POWER_DOMAIN_AUX_A,
	POWER_DOMAIN_AUX_B,
	POWER_DOMAIN_AUX_C,
	POWER_DOMAIN_AUX_D,
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	POWER_DOMAIN_GMBUS,
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	POWER_DOMAIN_MODESET,
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	POWER_DOMAIN_INIT,
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	POWER_DOMAIN_NUM,
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};

#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
		((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
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#define POWER_DOMAIN_TRANSCODER(tran) \
	((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
	 (tran) + POWER_DOMAIN_TRANSCODER_A)
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enum hpd_pin {
	HPD_NONE = 0,
	HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
	HPD_CRT,
	HPD_SDVO_B,
	HPD_SDVO_C,
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	HPD_PORT_A,
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	HPD_PORT_B,
	HPD_PORT_C,
	HPD_PORT_D,
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	HPD_PORT_E,
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	HPD_NUM_PINS
};

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#define for_each_hpd_pin(__pin) \
	for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)

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struct i915_hotplug {
	struct work_struct hotplug_work;

	struct {
		unsigned long last_jiffies;
		int count;
		enum {
			HPD_ENABLED = 0,
			HPD_DISABLED = 1,
			HPD_MARK_DISABLED = 2
		} state;
	} stats[HPD_NUM_PINS];
	u32 event_bits;
	struct delayed_work reenable_work;

	struct intel_digital_port *irq_port[I915_MAX_PORTS];
	u32 long_port_mask;
	u32 short_port_mask;
	struct work_struct dig_port_work;

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	struct work_struct poll_init_work;
	bool poll_enabled;

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	/*
	 * if we get a HPD irq from DP and a HPD irq from non-DP
	 * the non-DP HPD could block the workqueue on a mode config
	 * mutex getting, that userspace may have taken. However
	 * userspace is waiting on the DP workqueue to run which is
	 * blocked behind the non-DP one.
	 */
	struct workqueue_struct *dp_wq;
};

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#define I915_GEM_GPU_DOMAINS \
	(I915_GEM_DOMAIN_RENDER | \
	 I915_GEM_DOMAIN_SAMPLER | \
	 I915_GEM_DOMAIN_COMMAND | \
	 I915_GEM_DOMAIN_INSTRUCTION | \
	 I915_GEM_DOMAIN_VERTEX)
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#define for_each_pipe(__dev_priv, __p) \
	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
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#define for_each_pipe_masked(__dev_priv, __p, __mask) \
	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
		for_each_if ((__mask) & (1 << (__p)))
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#define for_each_plane(__dev_priv, __pipe, __p)				\
	for ((__p) = 0;							\
	     (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1;	\
	     (__p)++)
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#define for_each_sprite(__dev_priv, __p, __s)				\
	for ((__s) = 0;							\
	     (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)];	\
	     (__s)++)
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#define for_each_port_masked(__port, __ports_mask) \
	for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)	\
		for_each_if ((__ports_mask) & (1 << (__port)))

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#define for_each_crtc(dev, crtc) \
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	list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
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#define for_each_intel_plane(dev, intel_plane) \
	list_for_each_entry(intel_plane,			\
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			    &(dev)->mode_config.plane_list,	\
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			    base.head)

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#define for_each_intel_plane_mask(dev, intel_plane, plane_mask)		\
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	list_for_each_entry(intel_plane,				\
			    &(dev)->mode_config.plane_list,		\
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			    base.head)					\
		for_each_if ((plane_mask) &				\
			     (1 << drm_plane_index(&intel_plane->base)))

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#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)	\
	list_for_each_entry(intel_plane,				\
			    &(dev)->mode_config.plane_list,		\
			    base.head)					\
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		for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
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#define for_each_intel_crtc(dev, intel_crtc)				\
	list_for_each_entry(intel_crtc,					\
			    &(dev)->mode_config.crtc_list,		\
			    base.head)
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#define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask)		\
	list_for_each_entry(intel_crtc,					\
			    &(dev)->mode_config.crtc_list,		\
			    base.head)					\
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		for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))

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#define for_each_intel_encoder(dev, intel_encoder)		\
	list_for_each_entry(intel_encoder,			\
			    &(dev)->mode_config.encoder_list,	\
			    base.head)

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#define for_each_intel_connector(dev, intel_connector)		\
	list_for_each_entry(intel_connector,			\
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			    &(dev)->mode_config.connector_list,	\
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			    base.head)

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#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
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		for_each_if ((intel_encoder)->base.crtc == (__crtc))
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#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
	list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
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		for_each_if ((intel_connector)->base.encoder == (__encoder))
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#define for_each_power_domain(domain, mask)				\
	for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)	\
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		for_each_if ((1 << (domain)) & (mask))
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struct drm_i915_private;
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struct i915_mm_struct;
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struct i915_mmu_object;
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struct drm_i915_file_private {
	struct drm_i915_private *dev_priv;
	struct drm_file *file;

	struct {
		spinlock_t lock;
		struct list_head request_list;
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/* 20ms is a fairly arbitrary limit (greater than the average frame time)
 * chosen to prevent the CPU getting more than a frame ahead of the GPU
 * (when using lax throttling for the frontbuffer). We also use it to
 * offer free GPU waitboosts for severely congested workloads.
 */
#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
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	} mm;
	struct idr context_idr;

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	struct intel_rps_client {
		struct list_head link;
		unsigned boosts;
	} rps;
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	unsigned int bsd_engine;
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};

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/* Used by dp and fdi links */
struct intel_link_m_n {
	uint32_t	tu;
	uint32_t	gmch_m;
	uint32_t	gmch_n;
	uint32_t	link_m;
	uint32_t	link_n;
};

void intel_link_compute_m_n(int bpp, int nlanes,
			    int pixel_clock, int link_clock,
			    struct intel_link_m_n *m_n);

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/* Interface history:
 *
 * 1.1: Original.
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 * 1.2: Add Power Management
 * 1.3: Add vblank support
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 * 1.4: Fix cmdbuffer path, add heap destroy
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 * 1.5: Add vblank pipe configuration
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 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 *      - Support vertical blank on secondary display pipe
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 */
#define DRIVER_MAJOR		1
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#define DRIVER_MINOR		6
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#define DRIVER_PATCHLEVEL	0

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struct opregion_header;
struct opregion_acpi;
struct opregion_swsci;
struct opregion_asle;

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struct intel_opregion {
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	struct opregion_header *header;
	struct opregion_acpi *acpi;
	struct opregion_swsci *swsci;
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	u32 swsci_gbda_sub_functions;
	u32 swsci_sbcb_sub_functions;
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	struct opregion_asle *asle;
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	void *rvda;
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	const void *vbt;
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	u32 vbt_size;
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	u32 *lid_state;
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	struct work_struct asle_work;
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};
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#define OPREGION_SIZE            (8*1024)
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struct intel_overlay;
struct intel_overlay_error_state;

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#define I915_FENCE_REG_NONE -1
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#define I915_MAX_NUM_FENCES 32
/* 32 fences + sign bit for FENCE_REG_NONE */
#define I915_MAX_NUM_FENCE_BITS 6
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struct drm_i915_fence_reg {
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	struct list_head lru_list;
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	struct drm_i915_gem_object *obj;
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	int pin_count;
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};
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struct sdvo_device_mapping {
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	u8 initialized;
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	u8 dvo_port;
	u8 slave_addr;
	u8 dvo_wiring;
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	u8 i2c_pin;
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	u8 ddc_pin;
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};

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struct intel_display_error_state;

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struct drm_i915_error_state {
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	struct kref ref;
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	struct timeval time;

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	char error_msg[128];
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	bool simulated;
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	int iommu;
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	u32 reset_count;
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	u32 suspend_count;
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	/* Generic register state */
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	u32 eir;
	u32 pgtbl_er;
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	u32 ier;
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	u32 gtier[4];
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	u32 ccid;
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	u32 derrmr;
	u32 forcewake;
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	u32 error; /* gen6+ */
	u32 err_int; /* gen7 */
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	u32 fault_data0; /* gen8, gen9 */
	u32 fault_data1; /* gen8, gen9 */
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	u32 done_reg;
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	u32 gac_eco;
	u32 gam_ecochk;
	u32 gab_ctl;
	u32 gfx_mode;
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	u32 extra_instdone[I915_NUM_INSTDONE_REG];
	u64 fence[I915_MAX_NUM_FENCES];
	struct intel_overlay_error_state *overlay;
	struct intel_display_error_state *display;
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	struct drm_i915_error_object *semaphore_obj;
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	struct drm_i915_error_engine {
		int engine_id;
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		/* Software tracked state */
		bool waiting;
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		int num_waiters;
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		int hangcheck_score;
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		enum intel_engine_hangcheck_action hangcheck_action;
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		int num_requests;

		/* our own tracking of ring head and tail */
		u32 cpu_ring_head;
		u32 cpu_ring_tail;

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		u32 last_seqno;
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		u32 semaphore_seqno[I915_NUM_ENGINES - 1];
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		/* Register state */
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		u32 start;
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		u32 tail;
		u32 head;
		u32 ctl;
		u32 hws;
		u32 ipeir;
		u32 ipehr;
		u32 instdone;
		u32 bbstate;
		u32 instpm;
		u32 instps;
		u32 seqno;
		u64 bbaddr;
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		u64 acthd;
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		u32 fault_reg;
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		u64 faddr;
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		u32 rc_psmi; /* sleep state */
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		u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
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		struct drm_i915_error_object {
			int page_count;
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			u64 gtt_offset;
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			u32 *pages[0];
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		} *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
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		struct drm_i915_error_object *wa_ctx;

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		struct drm_i915_error_request {
			long jiffies;
			u32 seqno;
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			u32 tail;
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		} *requests;
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		struct drm_i915_error_waiter {
			char comm[TASK_COMM_LEN];
			pid_t pid;
			u32 seqno;
		} *waiters;

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		struct {
			u32 gfx_mode;
			union {
				u64 pdp[4];
				u32 pp_dir_base;
			};
		} vm_info;
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		pid_t pid;
		char comm[TASK_COMM_LEN];
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	} engine[I915_NUM_ENGINES];
580

581
	struct drm_i915_error_buffer {
582
		u32 size;
583
		u32 name;
584
		u32 rseqno[I915_NUM_ENGINES], wseqno;
585
		u64 gtt_offset;
586 587
		u32 read_domains;
		u32 write_domain;
588
		s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
589 590 591 592
		s32 pinned:2;
		u32 tiling:2;
		u32 dirty:1;
		u32 purgeable:1;
593
		u32 userptr:1;
594
		s32 engine:4;
595
		u32 cache_level:3;
596
	} **active_bo, **pinned_bo;
597

598
	u32 *active_bo_count, *pinned_bo_count;
599
	u32 vm_count;
600 601
};

602
struct intel_connector;
603
struct intel_encoder;
604
struct intel_crtc_state;
605
struct intel_initial_plane_config;
606
struct intel_crtc;
607 608
struct intel_limit;
struct dpll;
609

610 611 612
struct drm_i915_display_funcs {
	int (*get_display_clock_speed)(struct drm_device *dev);
	int (*get_fifo_size)(struct drm_device *dev, int plane);
613
	int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
614 615 616 617 618
	int (*compute_intermediate_wm)(struct drm_device *dev,
				       struct intel_crtc *intel_crtc,
				       struct intel_crtc_state *newstate);
	void (*initial_watermarks)(struct intel_crtc_state *cstate);
	void (*optimize_watermarks)(struct intel_crtc_state *cstate);
619
	int (*compute_global_watermarks)(struct drm_atomic_state *state);
620
	void (*update_wm)(struct drm_crtc *crtc);
621 622
	int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
	void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
623 624 625
	/* Returns the active state of the crtc, and if the crtc is active,
	 * fills out the pipe-config with the hw state. */
	bool (*get_pipe_config)(struct intel_crtc *,
626
				struct intel_crtc_state *);
627 628
	void (*get_initial_plane_config)(struct intel_crtc *,
					 struct intel_initial_plane_config *);
629 630
	int (*crtc_compute_clock)(struct intel_crtc *crtc,
				  struct intel_crtc_state *crtc_state);
631 632
	void (*crtc_enable)(struct drm_crtc *crtc);
	void (*crtc_disable)(struct drm_crtc *crtc);
633 634
	void (*audio_codec_enable)(struct drm_connector *connector,
				   struct intel_encoder *encoder,
635
				   const struct drm_display_mode *adjusted_mode);
636
	void (*audio_codec_disable)(struct intel_encoder *encoder);
637
	void (*fdi_link_train)(struct drm_crtc *crtc);
638
	void (*init_clock_gating)(struct drm_device *dev);
639 640 641 642 643
	int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
			  struct drm_framebuffer *fb,
			  struct drm_i915_gem_object *obj,
			  struct drm_i915_gem_request *req,
			  uint32_t flags);
644
	void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
645 646 647 648 649
	/* clock updates for mode set */
	/* cursor updates */
	/* render clock increase/decrease */
	/* display clock increase/decrease */
	/* pll clock increase/decrease */
650

651 652
	void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
	void (*load_luts)(struct drm_crtc_state *crtc_state);
653 654
};

655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671
enum forcewake_domain_id {
	FW_DOMAIN_ID_RENDER = 0,
	FW_DOMAIN_ID_BLITTER,
	FW_DOMAIN_ID_MEDIA,

	FW_DOMAIN_ID_COUNT
};

enum forcewake_domains {
	FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
	FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
	FORCEWAKE_MEDIA	= (1 << FW_DOMAIN_ID_MEDIA),
	FORCEWAKE_ALL = (FORCEWAKE_RENDER |
			 FORCEWAKE_BLITTER |
			 FORCEWAKE_MEDIA)
};

672 673 674 675 676 677 678
#define FW_REG_READ  (1)
#define FW_REG_WRITE (2)

enum forcewake_domains
intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
			       i915_reg_t reg, unsigned int op);

679
struct intel_uncore_funcs {
680
	void (*force_wake_get)(struct drm_i915_private *dev_priv,
681
							enum forcewake_domains domains);
682
	void (*force_wake_put)(struct drm_i915_private *dev_priv,
683
							enum forcewake_domains domains);
684

685 686 687 688
	uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
	uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
	uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
	uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
689

690
	void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
691
				uint8_t val, bool trace);
692
	void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
693
				uint16_t val, bool trace);
694
	void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
695
				uint32_t val, bool trace);
696
	void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r,
697
				uint64_t val, bool trace);
698 699
};

700 701 702 703 704 705
struct intel_uncore {
	spinlock_t lock; /** lock is also taken in irq contexts. */

	struct intel_uncore_funcs funcs;

	unsigned fifo_count;
706
	enum forcewake_domains fw_domains;
707 708 709

	struct intel_uncore_forcewake_domain {
		struct drm_i915_private *i915;
710
		enum forcewake_domain_id id;
711
		enum forcewake_domains mask;
712
		unsigned wake_count;
713
		struct hrtimer timer;
714
		i915_reg_t reg_set;
715 716
		u32 val_set;
		u32 val_clear;
717 718
		i915_reg_t reg_ack;
		i915_reg_t reg_post;
719
		u32 val_reset;
720
	} fw_domain[FW_DOMAIN_ID_COUNT];
721 722

	int unclaimed_mmio_check;
723 724 725
};

/* Iterate over initialised fw domains */
726 727 728 729 730 731 732 733
#define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
	for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
	     (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
	     (domain__)++) \
		for_each_if ((mask__) & (domain__)->mask)

#define for_each_fw_domain(domain__, dev_priv__) \
	for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
734

735 736 737 738
#define CSR_VERSION(major, minor)	((major) << 16 | (minor))
#define CSR_VERSION_MAJOR(version)	((version) >> 16)
#define CSR_VERSION_MINOR(version)	((version) & 0xffff)

739
struct intel_csr {
740
	struct work_struct work;
741
	const char *fw_path;
742
	uint32_t *dmc_payload;
743
	uint32_t dmc_fw_size;
744
	uint32_t version;
745
	uint32_t mmio_count;
746
	i915_reg_t mmioaddr[8];
747
	uint32_t mmiodata[8];
748
	uint32_t dc_state;
749
	uint32_t allowed_dc_mask;
750 751
};

752 753 754 755 756 757 758 759 760 761 762 763 764
#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
	func(is_mobile) sep \
	func(is_i85x) sep \
	func(is_i915g) sep \
	func(is_i945gm) sep \
	func(is_g33) sep \
	func(need_gfx_hws) sep \
	func(is_g4x) sep \
	func(is_pineview) sep \
	func(is_broadwater) sep \
	func(is_crestline) sep \
	func(is_ivybridge) sep \
	func(is_valleyview) sep \
765
	func(is_cherryview) sep \
766
	func(is_haswell) sep \
767
	func(is_broadwell) sep \
768
	func(is_skylake) sep \
769
	func(is_broxton) sep \
770
	func(is_kabylake) sep \
771
	func(is_preliminary) sep \
772 773 774 775 776 777 778
	func(has_fbc) sep \
	func(has_pipe_cxsr) sep \
	func(has_hotplug) sep \
	func(cursor_needs_physical) sep \
	func(has_overlay) sep \
	func(overlay_needs_physical) sep \
	func(supports_tv) sep \
779
	func(has_llc) sep \
780
	func(has_snoop) sep \
781
	func(has_ddi) sep \
782 783
	func(has_fpga_dbg) sep \
	func(has_pooled_eu)
D
Daniel Vetter 已提交
784

785 786
#define DEFINE_FLAG(name) u8 name:1
#define SEP_SEMICOLON ;
D
Daniel Vetter 已提交
787

788
struct intel_device_info {
789
	u32 display_mmio_offset;
790
	u16 device_id;
791
	u8 num_pipes;
792
	u8 num_sprites[I915_MAX_PIPES];
793
	u8 gen;
794
	u16 gen_mask;
795
	u8 ring_mask; /* Rings supported by the HW */
796
	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
797 798 799 800
	/* Register offsets for the various display pipes and transcoders */
	int pipe_offsets[I915_MAX_TRANSCODERS];
	int trans_offsets[I915_MAX_TRANSCODERS];
	int palette_offsets[I915_MAX_PIPES];
801
	int cursor_offsets[I915_MAX_PIPES];
802 803 804 805 806 807 808

	/* Slice/subslice/EU info */
	u8 slice_total;
	u8 subslice_total;
	u8 subslice_per_slice;
	u8 eu_total;
	u8 eu_per_subslice;
809
	u8 min_eu_in_pool;
810 811
	/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
	u8 subslice_7eu[3];
812 813 814
	u8 has_slice_pg:1;
	u8 has_subslice_pg:1;
	u8 has_eu_pg:1;
815 816 817 818 819

	struct color_luts {
		u16 degamma_lut_size;
		u16 gamma_lut_size;
	} color;
820 821
};

822 823 824
#undef DEFINE_FLAG
#undef SEP_SEMICOLON

825 826
enum i915_cache_level {
	I915_CACHE_NONE = 0,
827 828 829 830 831
	I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
	I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
			      caches, eg sampler/render caches, and the
			      large Last-Level-Cache. LLC is coherent with
			      the CPU, but L3 is only visible to the GPU. */
832
	I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
833 834
};

835 836 837 838 839 840
struct i915_ctx_hang_stats {
	/* This context had batch pending when hang was declared */
	unsigned batch_pending;

	/* This context had batch active when hang was declared */
	unsigned batch_active;
841 842 843 844

	/* Time when this context was last blamed for a GPU reset */
	unsigned long guilty_ts;

845 846 847 848 849
	/* If the contexts causes a second GPU hang within this time,
	 * it is permanently banned from submitting any more work.
	 */
	unsigned long ban_period_seconds;

850 851
	/* This context is banned to submit more work */
	bool banned;
852
};
853 854

/* This must match up with the value previously used for execbuf2.rsvd1. */
855
#define DEFAULT_CONTEXT_HANDLE 0
856

857
/**
858
 * struct i915_gem_context - as the name implies, represents a context.
859 860 861
 * @ref: reference count.
 * @user_handle: userspace tracking identity for this context.
 * @remap_slice: l3 row remapping information.
862 863
 * @flags: context specific flags:
 *         CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
864 865 866 867
 * @file_priv: filp associated with this context (NULL for global default
 *	       context).
 * @hang_stats: information about the role of this context in possible GPU
 *		hangs.
868
 * @ppgtt: virtual memory space used by this context.
869 870 871 872 873 874 875
 * @legacy_hw_ctx: render context backing object and whether it is correctly
 *                initialized (legacy ring submission mechanism only).
 * @link: link in the global list of contexts.
 *
 * Contexts are memory images used by the hardware to store copies of their
 * internal state.
 */
876
struct i915_gem_context {
877
	struct kref ref;
878
	struct drm_i915_private *i915;
879
	struct drm_i915_file_private *file_priv;
880
	struct i915_hw_ppgtt *ppgtt;
881

882 883
	struct i915_ctx_hang_stats hang_stats;

884
	/* Unique identifier for this context, used by the hw for tracking */
885
	unsigned long flags;
886 887
#define CONTEXT_NO_ZEROMAP		BIT(0)
#define CONTEXT_NO_ERROR_CAPTURE	BIT(1)
888
	unsigned hw_id;
889
	u32 user_handle;
890

891 892
	u32 ggtt_alignment;

893
	struct intel_context {
894
		struct drm_i915_gem_object *state;
895
		struct intel_ring *ring;
896
		struct i915_vma *lrc_vma;
897
		uint32_t *lrc_reg_state;
898 899
		u64 lrc_desc;
		int pin_count;
900
		bool initialised;
901
	} engine[I915_NUM_ENGINES];
902
	u32 ring_size;
903
	u32 desc_template;
904
	struct atomic_notifier_head status_notifier;
905
	bool execlists_force_single_submission;
906

907
	struct list_head link;
908 909

	u8 remap_slice;
910 911
};

912 913 914 915 916
enum fb_op_origin {
	ORIGIN_GTT,
	ORIGIN_CPU,
	ORIGIN_CS,
	ORIGIN_FLIP,
917
	ORIGIN_DIRTYFB,
918 919
};

920
struct intel_fbc {
P
Paulo Zanoni 已提交
921 922 923
	/* This is always the inner lock when overlapping with struct_mutex and
	 * it's the outer lock when overlapping with stolen_lock. */
	struct mutex lock;
B
Ben Widawsky 已提交
924
	unsigned threshold;
925 926
	unsigned int possible_framebuffer_bits;
	unsigned int busy_bits;
927
	unsigned int visible_pipes_mask;
928
	struct intel_crtc *crtc;
929

930
	struct drm_mm_node compressed_fb;
931 932
	struct drm_mm_node *compressed_llb;

933 934
	bool false_color;

935
	bool enabled;
936
	bool active;
937

938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959
	struct intel_fbc_state_cache {
		struct {
			unsigned int mode_flags;
			uint32_t hsw_bdw_pixel_rate;
		} crtc;

		struct {
			unsigned int rotation;
			int src_w;
			int src_h;
			bool visible;
		} plane;

		struct {
			u64 ilk_ggtt_offset;
			uint32_t pixel_format;
			unsigned int stride;
			int fence_reg;
			unsigned int tiling_mode;
		} fb;
	} state_cache;

960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976
	struct intel_fbc_reg_params {
		struct {
			enum pipe pipe;
			enum plane plane;
			unsigned int fence_y_offset;
		} crtc;

		struct {
			u64 ggtt_offset;
			uint32_t pixel_format;
			unsigned int stride;
			int fence_reg;
		} fb;

		int cfb_size;
	} params;

977
	struct intel_fbc_work {
978
		bool scheduled;
979
		u32 scheduled_vblank;
980 981
		struct work_struct work;
	} work;
982

983
	const char *no_fbc_reason;
984 985
};

986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000
/**
 * HIGH_RR is the highest eDP panel refresh rate read from EDID
 * LOW_RR is the lowest eDP panel refresh rate found from EDID
 * parsing for same resolution.
 */
enum drrs_refresh_rate_type {
	DRRS_HIGH_RR,
	DRRS_LOW_RR,
	DRRS_MAX_RR, /* RR count */
};

enum drrs_support_type {
	DRRS_NOT_SUPPORTED = 0,
	STATIC_DRRS_SUPPORT = 1,
	SEAMLESS_DRRS_SUPPORT = 2
1001 1002
};

1003
struct intel_dp;
1004 1005 1006 1007 1008 1009 1010 1011 1012
struct i915_drrs {
	struct mutex mutex;
	struct delayed_work work;
	struct intel_dp *dp;
	unsigned busy_frontbuffer_bits;
	enum drrs_refresh_rate_type refresh_rate_type;
	enum drrs_support_type type;
};

R
Rodrigo Vivi 已提交
1013
struct i915_psr {
1014
	struct mutex lock;
R
Rodrigo Vivi 已提交
1015 1016
	bool sink_support;
	bool source_ok;
1017
	struct intel_dp *enabled;
1018 1019
	bool active;
	struct delayed_work work;
1020
	unsigned busy_frontbuffer_bits;
1021 1022
	bool psr2_support;
	bool aux_frame_sync;
1023
	bool link_standby;
1024
};
1025

1026
enum intel_pch {
1027
	PCH_NONE = 0,	/* No PCH present */
1028 1029
	PCH_IBX,	/* Ibexpeak PCH */
	PCH_CPT,	/* Cougarpoint PCH */
1030
	PCH_LPT,	/* Lynxpoint PCH */
1031
	PCH_SPT,        /* Sunrisepoint PCH */
1032
	PCH_KBP,        /* Kabypoint PCH */
B
Ben Widawsky 已提交
1033
	PCH_NOP,
1034 1035
};

1036 1037 1038 1039 1040
enum intel_sbi_destination {
	SBI_ICLK,
	SBI_MPHY,
};

1041
#define QUIRK_PIPEA_FORCE (1<<0)
1042
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
1043
#define QUIRK_INVERT_BRIGHTNESS (1<<2)
1044
#define QUIRK_BACKLIGHT_PRESENT (1<<3)
1045
#define QUIRK_PIPEB_FORCE (1<<4)
1046
#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1047

1048
struct intel_fbdev;
1049
struct intel_fbc_work;
1050

1051 1052
struct intel_gmbus {
	struct i2c_adapter adapter;
1053
#define GMBUS_FORCE_BIT_RETRY (1U << 31)
1054
	u32 force_bit;
1055
	u32 reg0;
1056
	i915_reg_t gpio_reg;
1057
	struct i2c_algo_bit_data bit_algo;
1058 1059 1060
	struct drm_i915_private *dev_priv;
};

1061
struct i915_suspend_saved_registers {
1062
	u32 saveDSPARB;
J
Jesse Barnes 已提交
1063
	u32 saveLVDS;
1064 1065
	u32 savePP_ON_DELAYS;
	u32 savePP_OFF_DELAYS;
J
Jesse Barnes 已提交
1066 1067 1068
	u32 savePP_ON;
	u32 savePP_OFF;
	u32 savePP_CONTROL;
1069
	u32 savePP_DIVISOR;
J
Jesse Barnes 已提交
1070
	u32 saveFBC_CONTROL;
1071 1072
	u32 saveCACHE_MODE_0;
	u32 saveMI_ARB_STATE;
J
Jesse Barnes 已提交
1073 1074
	u32 saveSWF0[16];
	u32 saveSWF1[16];
1075
	u32 saveSWF3[3];
1076
	uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1077
	u32 savePCH_PORT_HOTPLUG;
1078
	u16 saveGCDGMBUS;
1079
};
1080

1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138
struct vlv_s0ix_state {
	/* GAM */
	u32 wr_watermark;
	u32 gfx_prio_ctrl;
	u32 arb_mode;
	u32 gfx_pend_tlb0;
	u32 gfx_pend_tlb1;
	u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
	u32 media_max_req_count;
	u32 gfx_max_req_count;
	u32 render_hwsp;
	u32 ecochk;
	u32 bsd_hwsp;
	u32 blt_hwsp;
	u32 tlb_rd_addr;

	/* MBC */
	u32 g3dctl;
	u32 gsckgctl;
	u32 mbctl;

	/* GCP */
	u32 ucgctl1;
	u32 ucgctl3;
	u32 rcgctl1;
	u32 rcgctl2;
	u32 rstctl;
	u32 misccpctl;

	/* GPM */
	u32 gfxpause;
	u32 rpdeuhwtc;
	u32 rpdeuc;
	u32 ecobus;
	u32 pwrdwnupctl;
	u32 rp_down_timeout;
	u32 rp_deucsw;
	u32 rcubmabdtmr;
	u32 rcedata;
	u32 spare2gh;

	/* Display 1 CZ domain */
	u32 gt_imr;
	u32 gt_ier;
	u32 pm_imr;
	u32 pm_ier;
	u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];

	/* GT SA CZ domain */
	u32 tilectl;
	u32 gt_fifoctl;
	u32 gtlc_wake_ctrl;
	u32 gtlc_survive;
	u32 pmwgicz;

	/* Display 2 CZ domain */
	u32 gu_ctl0;
	u32 gu_ctl1;
1139
	u32 pcbr;
1140 1141 1142
	u32 clock_gate_dis2;
};

1143 1144 1145 1146
struct intel_rps_ei {
	u32 cz_clock;
	u32 render_c0;
	u32 media_c0;
1147 1148
};

1149
struct intel_gen6_power_mgmt {
I
Imre Deak 已提交
1150 1151 1152 1153
	/*
	 * work, interrupts_enabled and pm_iir are protected by
	 * dev_priv->irq_lock
	 */
1154
	struct work_struct work;
I
Imre Deak 已提交
1155
	bool interrupts_enabled;
1156
	u32 pm_iir;
1157

1158 1159
	u32 pm_intr_keep;

1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174
	/* Frequencies are stored in potentially platform dependent multiples.
	 * In other words, *_freq needs to be multiplied by X to be interesting.
	 * Soft limits are those which are used for the dynamic reclocking done
	 * by the driver (raise frequencies under heavy loads, and lower for
	 * lighter loads). Hard limits are those imposed by the hardware.
	 *
	 * A distinction is made for overclocking, which is never enabled by
	 * default, and is considered to be above the hard limit if it's
	 * possible at all.
	 */
	u8 cur_freq;		/* Current frequency (cached, may not == HW) */
	u8 min_freq_softlimit;	/* Minimum frequency permitted by the driver */
	u8 max_freq_softlimit;	/* Max frequency permitted by the driver */
	u8 max_freq;		/* Maximum frequency, RP0 if not overclocking */
	u8 min_freq;		/* AKA RPn. Minimum frequency */
1175
	u8 boost_freq;		/* Frequency to request when wait boosting */
1176
	u8 idle_freq;		/* Frequency to request when we are idle */
1177 1178 1179
	u8 efficient_freq;	/* AKA RPe. Pre-determined balanced frequency */
	u8 rp1_freq;		/* "less than" RP0 power/freqency */
	u8 rp0_freq;		/* Non-overclocked max frequency. */
1180
	u16 gpll_ref_freq;	/* vlv/chv GPLL reference frequency */
1181

1182 1183 1184
	u8 up_threshold; /* Current %busy required to uplock */
	u8 down_threshold; /* Current %busy required to downclock */

1185 1186 1187
	int last_adj;
	enum { LOW_POWER, BETWEEN, HIGH_POWER } power;

1188 1189 1190 1191
	spinlock_t client_lock;
	struct list_head clients;
	bool client_boost;

1192
	bool enabled;
1193
	struct delayed_work autoenable_work;
1194
	unsigned boosts;
1195

1196 1197 1198
	/* manual wa residency calculations */
	struct intel_rps_ei up_ei, down_ei;

1199 1200
	/*
	 * Protects RPS/RC6 register access and PCU communication.
1201 1202 1203
	 * Must be taken after struct_mutex if nested. Note that
	 * this lock may be held for long periods of time when
	 * talking to hw - so only take it when talking to hw!
1204 1205
	 */
	struct mutex hw_lock;
1206 1207
};

D
Daniel Vetter 已提交
1208 1209 1210
/* defined intel_pm.c */
extern spinlock_t mchdev_lock;

1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221
struct intel_ilk_power_mgmt {
	u8 cur_delay;
	u8 min_delay;
	u8 max_delay;
	u8 fmax;
	u8 fstart;

	u64 last_count1;
	unsigned long last_time1;
	unsigned long chipset_power;
	u64 last_count2;
1222
	u64 last_time2;
1223 1224 1225 1226 1227 1228 1229
	unsigned long gfx_power;
	u8 corr;

	int c_m;
	int r_t;
};

1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259
struct drm_i915_private;
struct i915_power_well;

struct i915_power_well_ops {
	/*
	 * Synchronize the well's hw state to match the current sw state, for
	 * example enable/disable it based on the current refcount. Called
	 * during driver init and resume time, possibly after first calling
	 * the enable/disable handlers.
	 */
	void (*sync_hw)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/*
	 * Enable the well and resources that depend on it (for example
	 * interrupts located on the well). Called after the 0->1 refcount
	 * transition.
	 */
	void (*enable)(struct drm_i915_private *dev_priv,
		       struct i915_power_well *power_well);
	/*
	 * Disable the well and resources that depend on it. Called after
	 * the 1->0 refcount transition.
	 */
	void (*disable)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/* Returns the hw enabled state. */
	bool (*is_enabled)(struct drm_i915_private *dev_priv,
			   struct i915_power_well *power_well);
};

1260 1261
/* Power well structure for haswell */
struct i915_power_well {
1262
	const char *name;
1263
	bool always_on;
1264 1265
	/* power well enable/disable usage count */
	int count;
1266 1267
	/* cached hw enabled state */
	bool hw_enabled;
1268
	unsigned long domains;
1269
	unsigned long data;
1270
	const struct i915_power_well_ops *ops;
1271 1272
};

1273
struct i915_power_domains {
1274 1275 1276 1277 1278
	/*
	 * Power wells needed for initialization at driver init and suspend
	 * time are on. They are kept on until after the first modeset.
	 */
	bool init_power_on;
1279
	bool initializing;
1280
	int power_well_count;
1281

1282
	struct mutex lock;
1283
	int domain_use_count[POWER_DOMAIN_NUM];
1284
	struct i915_power_well *power_wells;
1285 1286
};

1287
#define MAX_L3_SLICES 2
1288
struct intel_l3_parity {
1289
	u32 *remap_info[MAX_L3_SLICES];
1290
	struct work_struct error_work;
1291
	int which_slice;
1292 1293
};

1294 1295 1296
struct i915_gem_mm {
	/** Memory allocator for GTT stolen memory */
	struct drm_mm stolen;
1297 1298 1299 1300
	/** Protects the usage of the GTT stolen memory allocator. This is
	 * always the inner lock when overlapping with struct_mutex. */
	struct mutex stolen_lock;

1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316
	/** List of all objects in gtt_space. Used to restore gtt
	 * mappings on resume */
	struct list_head bound_list;
	/**
	 * List of objects which are not bound to the GTT (thus
	 * are idle and not used by the GPU) but still have
	 * (presumably uncached) pages still attached.
	 */
	struct list_head unbound_list;

	/** Usable portion of the GTT for GEM */
	unsigned long stolen_base; /* limited to low memory (32-bit) */

	/** PPGTT used for aliasing the PPGTT with the GTT */
	struct i915_hw_ppgtt *aliasing_ppgtt;

1317
	struct notifier_block oom_notifier;
1318
	struct notifier_block vmap_notifier;
1319
	struct shrinker shrinker;
1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330
	bool shrinker_no_lock_stealing;

	/** LRU list of objects with fence regs on them. */
	struct list_head fence_list;

	/**
	 * Are we in a non-interruptible section of code like
	 * modesetting?
	 */
	bool interruptible;

1331
	/* the indicator for dispatch video commands on two BSD rings */
1332
	unsigned int bsd_engine_dispatch_index;
1333

1334 1335 1336 1337 1338 1339
	/** Bit 6 swizzling required for X tiling */
	uint32_t bit_6_swizzle_x;
	/** Bit 6 swizzling required for Y tiling */
	uint32_t bit_6_swizzle_y;

	/* accounting, useful for userland debugging */
1340
	spinlock_t object_stat_lock;
1341 1342 1343 1344
	size_t object_memory;
	u32 object_count;
};

1345
struct drm_i915_error_state_buf {
1346
	struct drm_i915_private *i915;
1347 1348 1349 1350 1351 1352 1353 1354
	unsigned bytes;
	unsigned size;
	int err;
	u8 *buf;
	loff_t start;
	loff_t pos;
};

1355 1356 1357 1358 1359
struct i915_error_state_file_priv {
	struct drm_device *dev;
	struct drm_i915_error_state *error;
};

1360 1361 1362 1363
struct i915_gpu_error {
	/* For hangcheck timer */
#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1364 1365 1366
	/* Hang gpu twice in this window and your context gets banned */
#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)

1367
	struct delayed_work hangcheck_work;
1368 1369 1370 1371 1372

	/* For reset and error_state handling. */
	spinlock_t lock;
	/* Protected by the above dev->gpu_error.lock. */
	struct drm_i915_error_state *first_error;
1373 1374 1375

	unsigned long missed_irq_rings;

1376
	/**
M
Mika Kuoppala 已提交
1377
	 * State variable controlling the reset flow and count
1378
	 *
M
Mika Kuoppala 已提交
1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391
	 * This is a counter which gets incremented when reset is triggered,
	 * and again when reset has been handled. So odd values (lowest bit set)
	 * means that reset is in progress and even values that
	 * (reset_counter >> 1):th reset was successfully completed.
	 *
	 * If reset is not completed succesfully, the I915_WEDGE bit is
	 * set meaning that hardware is terminally sour and there is no
	 * recovery. All waiters on the reset_queue will be woken when
	 * that happens.
	 *
	 * This counter is used by the wait_seqno code to notice that reset
	 * event happened and it needs to restart the entire ioctl (since most
	 * likely the seqno it waited for won't ever signal anytime soon).
1392 1393 1394 1395
	 *
	 * This is important for lock-free wait paths, where no contended lock
	 * naturally enforces the correct ordering between the bail-out of the
	 * waiter and the gpu reset work code.
1396 1397 1398 1399
	 */
	atomic_t reset_counter;

#define I915_RESET_IN_PROGRESS_FLAG	1
M
Mika Kuoppala 已提交
1400
#define I915_WEDGED			(1 << 31)
1401

1402 1403 1404 1405 1406 1407
	/**
	 * Waitqueue to signal when a hang is detected. Used to for waiters
	 * to release the struct_mutex for the reset to procede.
	 */
	wait_queue_head_t wait_queue;

1408 1409 1410 1411 1412
	/**
	 * Waitqueue to signal when the reset has completed. Used by clients
	 * that wait for dev_priv->mm.wedged to settle.
	 */
	wait_queue_head_t reset_queue;
1413

1414
	/* For missed irq/seqno simulation. */
1415
	unsigned long test_irq_rings;
1416 1417
};

1418 1419 1420 1421 1422 1423
enum modeset_restore {
	MODESET_ON_LID_OPEN,
	MODESET_DONE,
	MODESET_SUSPENDED,
};

1424 1425 1426 1427 1428
#define DP_AUX_A 0x40
#define DP_AUX_B 0x10
#define DP_AUX_C 0x20
#define DP_AUX_D 0x30

X
Xiong Zhang 已提交
1429 1430 1431 1432
#define DDC_PIN_B  0x05
#define DDC_PIN_C  0x04
#define DDC_PIN_D  0x06

1433
struct ddi_vbt_port_info {
1434 1435 1436 1437 1438 1439
	/*
	 * This is an index in the HDMI/DVI DDI buffer translation table.
	 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
	 * populate this field.
	 */
#define HDMI_LEVEL_SHIFT_UNKNOWN	0xff
1440
	uint8_t hdmi_level_shift;
1441 1442 1443 1444

	uint8_t supports_dvi:1;
	uint8_t supports_hdmi:1;
	uint8_t supports_dp:1;
1445 1446

	uint8_t alternate_aux_channel;
X
Xiong Zhang 已提交
1447
	uint8_t alternate_ddc_pin;
1448 1449 1450

	uint8_t dp_boost_level;
	uint8_t hdmi_boost_level;
1451 1452
};

R
Rodrigo Vivi 已提交
1453 1454 1455 1456 1457
enum psr_lines_to_wait {
	PSR_0_LINES_TO_WAIT = 0,
	PSR_1_LINE_TO_WAIT,
	PSR_4_LINES_TO_WAIT,
	PSR_8_LINES_TO_WAIT
1458 1459
};

1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471
struct intel_vbt_data {
	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */

	/* Feature bits */
	unsigned int int_tv_support:1;
	unsigned int lvds_dither:1;
	unsigned int lvds_vbt:1;
	unsigned int int_crt_support:1;
	unsigned int lvds_use_ssc:1;
	unsigned int display_clock_mode:1;
	unsigned int fdi_rx_polarity_inverted:1;
1472
	unsigned int panel_type:4;
1473 1474 1475
	int lvds_ssc_freq;
	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */

1476 1477
	enum drrs_support_type drrs_type;

1478 1479 1480 1481 1482
	struct {
		int rate;
		int lanes;
		int preemphasis;
		int vswing;
1483
		bool low_vswing;
1484 1485 1486 1487 1488
		bool initialized;
		bool support;
		int bpp;
		struct edp_power_seq pps;
	} edp;
1489

R
Rodrigo Vivi 已提交
1490 1491 1492 1493 1494 1495 1496 1497 1498
	struct {
		bool full_link;
		bool require_aux_wakeup;
		int idle_frames;
		enum psr_lines_to_wait lines_to_wait;
		int tp1_wakeup_time;
		int tp2_tp3_wakeup_time;
	} psr;

1499 1500
	struct {
		u16 pwm_freq_hz;
1501
		bool present;
1502
		bool active_low_pwm;
1503
		u8 min_brightness;	/* min_brightness/255 of max */
1504
		enum intel_backlight_type type;
1505 1506
	} backlight;

1507 1508 1509
	/* MIPI DSI */
	struct {
		u16 panel_id;
1510 1511 1512 1513 1514
		struct mipi_config *config;
		struct mipi_pps_data *pps;
		u8 seq_version;
		u32 size;
		u8 *data;
1515
		const u8 *sequence[MIPI_SEQ_MAX];
1516 1517
	} dsi;

1518 1519 1520
	int crt_ddc_pin;

	int child_dev_num;
1521
	union child_device_config *child_dev;
1522 1523

	struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1524
	struct sdvo_device_mapping sdvo_mappings[2];
1525 1526
};

1527 1528 1529 1530 1531
enum intel_ddb_partitioning {
	INTEL_DDB_PART_1_2,
	INTEL_DDB_PART_5_6, /* IVB+ */
};

1532 1533 1534 1535 1536 1537 1538 1539
struct intel_wm_level {
	bool enable;
	uint32_t pri_val;
	uint32_t spr_val;
	uint32_t cur_val;
	uint32_t fbc_val;
};

1540
struct ilk_wm_values {
1541 1542 1543 1544 1545 1546 1547 1548
	uint32_t wm_pipe[3];
	uint32_t wm_lp[3];
	uint32_t wm_lp_spr[3];
	uint32_t wm_linetime[3];
	bool enable_fbc_wm;
	enum intel_ddb_partitioning partitioning;
};

1549 1550 1551 1552 1553
struct vlv_pipe_wm {
	uint16_t primary;
	uint16_t sprite[2];
	uint8_t cursor;
};
1554

1555 1556 1557 1558
struct vlv_sr_wm {
	uint16_t plane;
	uint8_t cursor;
};
1559

1560 1561 1562
struct vlv_wm_values {
	struct vlv_pipe_wm pipe[3];
	struct vlv_sr_wm sr;
1563 1564 1565 1566 1567
	struct {
		uint8_t cursor;
		uint8_t sprite[2];
		uint8_t primary;
	} ddl[3];
1568 1569
	uint8_t level;
	bool cxsr;
1570 1571
};

1572
struct skl_ddb_entry {
1573
	uint16_t start, end;	/* in number of blocks, 'end' is exclusive */
1574 1575 1576 1577
};

static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
{
1578
	return entry->end - entry->start;
1579 1580
}

1581 1582 1583 1584 1585 1586 1587 1588 1589
static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
				       const struct skl_ddb_entry *e2)
{
	if (e1->start == e2->start && e1->end == e2->end)
		return true;

	return false;
}

1590
struct skl_ddb_allocation {
1591
	struct skl_ddb_entry pipe[I915_MAX_PIPES];
1592
	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1593
	struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1594 1595
};

1596
struct skl_wm_values {
1597
	unsigned dirty_pipes;
1598
	struct skl_ddb_allocation ddb;
1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609
	uint32_t wm_linetime[I915_MAX_PIPES];
	uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
	uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
};

struct skl_wm_level {
	bool plane_en[I915_MAX_PLANES];
	uint16_t plane_res_b[I915_MAX_PLANES];
	uint8_t plane_res_l[I915_MAX_PLANES];
};

1610
/*
1611 1612 1613 1614
 * This struct helps tracking the state needed for runtime PM, which puts the
 * device in PCI D3 state. Notice that when this happens, nothing on the
 * graphics device works, even register access, so we don't get interrupts nor
 * anything else.
1615
 *
1616 1617 1618
 * Every piece of our code that needs to actually touch the hardware needs to
 * either call intel_runtime_pm_get or call intel_display_power_get with the
 * appropriate power domain.
1619
 *
1620 1621
 * Our driver uses the autosuspend delay feature, which means we'll only really
 * suspend if we stay with zero refcount for a certain amount of time. The
1622
 * default value is currently very conservative (see intel_runtime_pm_enable), but
1623
 * it can be changed with the standard runtime PM files from sysfs.
1624 1625 1626 1627 1628
 *
 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
 * goes back to false exactly before we reenable the IRQs. We use this variable
 * to check if someone is trying to enable/disable IRQs while they're supposed
 * to be disabled. This shouldn't happen and we'll print some error messages in
1629
 * case it happens.
1630
 *
1631
 * For more, read the Documentation/power/runtime_pm.txt.
1632
 */
1633
struct i915_runtime_pm {
1634
	atomic_t wakeref_count;
1635
	atomic_t atomic_seq;
1636
	bool suspended;
1637
	bool irqs_enabled;
1638 1639
};

1640 1641 1642 1643 1644
enum intel_pipe_crc_source {
	INTEL_PIPE_CRC_SOURCE_NONE,
	INTEL_PIPE_CRC_SOURCE_PLANE1,
	INTEL_PIPE_CRC_SOURCE_PLANE2,
	INTEL_PIPE_CRC_SOURCE_PF,
1645
	INTEL_PIPE_CRC_SOURCE_PIPE,
D
Daniel Vetter 已提交
1646 1647 1648 1649 1650
	/* TV/DP on pre-gen5/vlv can't use the pipe source. */
	INTEL_PIPE_CRC_SOURCE_TV,
	INTEL_PIPE_CRC_SOURCE_DP_B,
	INTEL_PIPE_CRC_SOURCE_DP_C,
	INTEL_PIPE_CRC_SOURCE_DP_D,
1651
	INTEL_PIPE_CRC_SOURCE_AUTO,
1652 1653 1654
	INTEL_PIPE_CRC_SOURCE_MAX,
};

1655
struct intel_pipe_crc_entry {
1656
	uint32_t frame;
1657 1658 1659
	uint32_t crc[5];
};

1660
#define INTEL_PIPE_CRC_ENTRIES_NR	128
1661
struct intel_pipe_crc {
1662 1663
	spinlock_t lock;
	bool opened;		/* exclusive access to the result file */
1664
	struct intel_pipe_crc_entry *entries;
1665
	enum intel_pipe_crc_source source;
1666
	int head, tail;
1667
	wait_queue_head_t wq;
1668 1669
};

1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680
struct i915_frontbuffer_tracking {
	struct mutex lock;

	/*
	 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
	 * scheduled flips.
	 */
	unsigned busy_bits;
	unsigned flip_bits;
};

1681
struct i915_wa_reg {
1682
	i915_reg_t addr;
1683 1684 1685 1686 1687
	u32 value;
	/* bitmask representing WA bits */
	u32 mask;
};

1688 1689 1690 1691 1692 1693 1694
/*
 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
 * allowing it for RCS as we don't foresee any requirement of having
 * a whitelist for other engines. When it is really required for
 * other engines then the limit need to be increased.
 */
#define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1695 1696 1697 1698

struct i915_workarounds {
	struct i915_wa_reg reg[I915_MAX_WA_REGS];
	u32 count;
1699
	u32 hw_whitelist_count[I915_NUM_ENGINES];
1700 1701
};

1702 1703 1704 1705
struct i915_virtual_gpu {
	bool active;
};

1706 1707 1708 1709 1710 1711 1712
/* used in computing the new watermarks state */
struct intel_wm_config {
	unsigned int num_pipes_active;
	bool sprites_enabled;
	bool sprites_scaled;
};

1713
struct drm_i915_private {
1714 1715
	struct drm_device drm;

1716
	struct kmem_cache *objects;
1717
	struct kmem_cache *vmas;
1718
	struct kmem_cache *requests;
1719

1720
	const struct intel_device_info info;
1721 1722 1723 1724 1725

	int relative_constants_mode;

	void __iomem *regs;

1726
	struct intel_uncore uncore;
1727

1728 1729
	struct i915_virtual_gpu vgpu;

1730 1731
	struct intel_gvt gvt;

1732 1733
	struct intel_guc guc;

1734 1735
	struct intel_csr csr;

1736
	struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1737

1738 1739 1740 1741 1742 1743 1744 1745 1746
	/** gmbus_mutex protects against concurrent usage of the single hw gmbus
	 * controller on different i2c buses. */
	struct mutex gmbus_mutex;

	/**
	 * Base address of the gmbus and gpio block.
	 */
	uint32_t gpio_mmio_base;

1747 1748 1749
	/* MMIO base address for MIPI regs */
	uint32_t mipi_mmio_base;

1750 1751
	uint32_t psr_mmio_base;

1752 1753
	wait_queue_head_t gmbus_wait_queue;

1754
	struct pci_dev *bridge_dev;
1755
	struct i915_gem_context *kernel_context;
1756
	struct intel_engine_cs engine[I915_NUM_ENGINES];
1757
	struct drm_i915_gem_object *semaphore_obj;
1758
	u32 next_seqno;
1759

1760
	struct drm_dma_handle *status_page_dmah;
1761 1762 1763 1764 1765
	struct resource mch_res;

	/* protects the irq masks */
	spinlock_t irq_lock;

1766 1767 1768
	/* protects the mmio flip data */
	spinlock_t mmio_flip_lock;

1769 1770
	bool display_irqs_enabled;

1771 1772 1773
	/* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
	struct pm_qos_request pm_qos;

V
Ville Syrjälä 已提交
1774 1775
	/* Sideband mailbox protection */
	struct mutex sb_lock;
1776 1777

	/** Cached value of IMR to avoid reads in updating the bitfield */
1778 1779 1780 1781
	union {
		u32 irq_mask;
		u32 de_irq_mask[I915_MAX_PIPES];
	};
1782
	u32 gt_irq_mask;
1783
	u32 pm_irq_mask;
1784
	u32 pm_rps_events;
1785
	u32 pipestat_irq_mask[I915_MAX_PIPES];
1786

1787
	struct i915_hotplug hotplug;
1788
	struct intel_fbc fbc;
1789
	struct i915_drrs drrs;
1790
	struct intel_opregion opregion;
1791
	struct intel_vbt_data vbt;
1792

1793 1794
	bool preserve_bios_swizzle;

1795 1796 1797
	/* overlay */
	struct intel_overlay *overlay;

1798
	/* backlight registers and fields in struct intel_panel */
1799
	struct mutex backlight_lock;
1800

1801 1802 1803
	/* LVDS info */
	bool no_aux_handshake;

V
Ville Syrjälä 已提交
1804 1805 1806
	/* protects panel power sequencer state */
	struct mutex pps_mutex;

1807 1808 1809 1810
	struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
	int num_fence_regs; /* 8 on pre-965, 16 otherwise */

	unsigned int fsb_freq, mem_freq, is_ddr3;
1811
	unsigned int skl_preferred_vco_freq;
1812
	unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
M
Mika Kahola 已提交
1813
	unsigned int max_dotclk_freq;
1814
	unsigned int rawclk_freq;
1815
	unsigned int hpll_freq;
1816
	unsigned int czclk_freq;
1817

1818
	struct {
1819
		unsigned int vco, ref;
1820 1821
	} cdclk_pll;

1822 1823 1824 1825 1826 1827 1828
	/**
	 * wq - Driver workqueue for GEM.
	 *
	 * NOTE: Work items scheduled here are not allowed to grab any modeset
	 * locks, for otherwise the flushing done in the pageflip code will
	 * result in deadlocks.
	 */
1829 1830 1831 1832 1833 1834 1835
	struct workqueue_struct *wq;

	/* Display functions */
	struct drm_i915_display_funcs display;

	/* PCH chipset type */
	enum intel_pch pch_type;
1836
	unsigned short pch_id;
1837 1838 1839

	unsigned long quirks;

1840 1841
	enum modeset_restore modeset_restore;
	struct mutex modeset_restore_lock;
1842
	struct drm_atomic_state *modeset_restore_state;
1843

1844
	struct list_head vm_list; /* Global list of all address spaces */
1845
	struct i915_ggtt ggtt; /* VM representing the global address space */
B
Ben Widawsky 已提交
1846

1847
	struct i915_gem_mm mm;
1848 1849
	DECLARE_HASHTABLE(mm_structs, 7);
	struct mutex mm_lock;
1850

1851 1852 1853 1854 1855 1856 1857
	/* The hw wants to have a stable context identifier for the lifetime
	 * of the context (for OA, PASID, faults, etc). This is limited
	 * in execlists to 21 bits.
	 */
	struct ida context_hw_ida;
#define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */

1858 1859
	/* Kernel Modesetting */

1860 1861
	struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
	struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1862 1863
	wait_queue_head_t pending_flip_queue;

1864 1865 1866 1867
#ifdef CONFIG_DEBUG_FS
	struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
#endif

1868
	/* dpll and cdclk state is protected by connection_mutex */
D
Daniel Vetter 已提交
1869 1870
	int num_shared_dpll;
	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1871
	const struct intel_dpll_mgr *dpll_mgr;
1872

1873 1874 1875 1876 1877 1878 1879
	/*
	 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
	 * Must be global rather than per dpll, because on some platforms
	 * plls share registers.
	 */
	struct mutex dpll_lock;

1880 1881 1882
	unsigned int active_crtcs;
	unsigned int min_pixclk[I915_MAX_PIPES];

1883
	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1884

1885
	struct i915_workarounds workarounds;
1886

1887 1888
	struct i915_frontbuffer_tracking fb_tracking;

1889
	u16 orig_clock;
1890

1891
	bool mchbar_need_disable;
1892

1893 1894
	struct intel_l3_parity l3_parity;

B
Ben Widawsky 已提交
1895
	/* Cannot be determined by PCIID. You must always read a register. */
1896
	u32 edram_cap;
B
Ben Widawsky 已提交
1897

1898
	/* gen6+ rps state */
1899
	struct intel_gen6_power_mgmt rps;
1900

1901 1902
	/* ilk-only ips/rps state. Everything in here is protected by the global
	 * mchdev_lock in intel_pm.c */
1903
	struct intel_ilk_power_mgmt ips;
1904

1905
	struct i915_power_domains power_domains;
1906

R
Rodrigo Vivi 已提交
1907
	struct i915_psr psr;
1908

1909
	struct i915_gpu_error gpu_error;
1910

1911 1912
	struct drm_i915_gem_object *vlv_pctx;

1913
#ifdef CONFIG_DRM_FBDEV_EMULATION
1914 1915
	/* list of fbdev register on this device */
	struct intel_fbdev *fbdev;
1916
	struct work_struct fbdev_suspend_work;
1917
#endif
1918 1919

	struct drm_property *broadcast_rgb_property;
1920
	struct drm_property *force_audio_property;
1921

I
Imre Deak 已提交
1922
	/* hda/i915 audio component */
1923
	struct i915_audio_component *audio_component;
I
Imre Deak 已提交
1924
	bool audio_component_registered;
1925 1926 1927 1928 1929
	/**
	 * av_mutex - mutex for audio/video sync
	 *
	 */
	struct mutex av_mutex;
I
Imre Deak 已提交
1930

1931
	uint32_t hw_context_size;
1932
	struct list_head context_list;
1933

1934
	u32 fdi_rx_config;
1935

1936
	/* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1937
	u32 chv_phy_control;
1938 1939 1940 1941 1942 1943
	/*
	 * Shadows for CHV DPLL_MD regs to keep the state
	 * checker somewhat working in the presence hardware
	 * crappiness (can't read out DPLL_MD for pipes B & C).
	 */
	u32 chv_dpll_md[I915_MAX_PIPES];
1944
	u32 bxt_phy_grc;
1945

1946
	u32 suspend_count;
1947
	bool suspended_to_idle;
1948
	struct i915_suspend_saved_registers regfile;
1949
	struct vlv_s0ix_state vlv_s0ix_state;
1950

1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962
	struct {
		/*
		 * Raw watermark latency values:
		 * in 0.1us units for WM0,
		 * in 0.5us units for WM1+.
		 */
		/* primary */
		uint16_t pri_latency[5];
		/* sprite */
		uint16_t spr_latency[5];
		/* cursor */
		uint16_t cur_latency[5];
1963 1964 1965 1966 1967 1968
		/*
		 * Raw watermark memory latency values
		 * for SKL for all 8 levels
		 * in 1us units.
		 */
		uint16_t skl_latency[8];
1969

1970 1971 1972 1973 1974 1975 1976
		/*
		 * The skl_wm_values structure is a bit too big for stack
		 * allocation, so we keep the staging struct where we store
		 * intermediate results here instead.
		 */
		struct skl_wm_values skl_results;

1977
		/* current hardware state */
1978 1979 1980
		union {
			struct ilk_wm_values hw;
			struct skl_wm_values skl_hw;
1981
			struct vlv_wm_values vlv;
1982
		};
1983 1984

		uint8_t max_level;
1985 1986 1987 1988 1989 1990 1991

		/*
		 * Should be held around atomic WM register writing; also
		 * protects * intel_crtc->wm.active and
		 * cstate->wm.need_postvbl_update.
		 */
		struct mutex wm_mutex;
1992 1993 1994 1995 1996 1997 1998

		/*
		 * Set during HW readout of watermarks/DDB.  Some platforms
		 * need to know when we're still using BIOS-provided values
		 * (which we don't fully trust).
		 */
		bool distrust_bios_wm;
1999 2000
	} wm;

2001 2002
	struct i915_runtime_pm pm;

2003 2004
	/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
	struct {
2005 2006
		void (*cleanup_engine)(struct intel_engine_cs *engine);
		void (*stop_engine)(struct intel_engine_cs *engine);
2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034

		/**
		 * Is the GPU currently considered idle, or busy executing
		 * userspace requests? Whilst idle, we allow runtime power
		 * management to power down the hardware and display clocks.
		 * In order to reduce the effect on performance, there
		 * is a slight delay before we do so.
		 */
		unsigned int active_engines;
		bool awake;

		/**
		 * We leave the user IRQ off as much as possible,
		 * but this means that requests will finish and never
		 * be retired once the system goes idle. Set a timer to
		 * fire periodically while the ring is running. When it
		 * fires, go retire requests.
		 */
		struct delayed_work retire_work;

		/**
		 * When we detect an idle GPU, we want to turn on
		 * powersaving features. So once we see that there
		 * are no more requests outstanding and no more
		 * arrive within a small period of time, we fire
		 * off the idle_work.
		 */
		struct delayed_work idle_work;
2035 2036
	} gt;

2037 2038 2039
	/* perform PHY state sanity checks? */
	bool chv_phy_assert[2];

2040 2041
	struct intel_encoder *dig_port_map[I915_MAX_PORTS];

2042 2043 2044 2045
	/*
	 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
	 * will be rejected. Instead look for a better place.
	 */
2046
};
L
Linus Torvalds 已提交
2047

2048 2049
static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
{
2050
	return container_of(dev, struct drm_i915_private, drm);
2051 2052
}

I
Imre Deak 已提交
2053 2054 2055 2056 2057
static inline struct drm_i915_private *dev_to_i915(struct device *dev)
{
	return to_i915(dev_get_drvdata(dev));
}

2058 2059 2060 2061 2062
static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
{
	return container_of(guc, struct drm_i915_private, guc);
}

2063 2064 2065 2066 2067 2068
/* Simple iterator over all initialised engines */
#define for_each_engine(engine__, dev_priv__) \
	for ((engine__) = &(dev_priv__)->engine[0]; \
	     (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
	     (engine__)++) \
		for_each_if (intel_engine_initialized(engine__))
2069

2070 2071 2072 2073 2074 2075 2076 2077 2078
/* Iterator with engine_id */
#define for_each_engine_id(engine__, dev_priv__, id__) \
	for ((engine__) = &(dev_priv__)->engine[0], (id__) = 0; \
	     (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
	     (engine__)++) \
		for_each_if (((id__) = (engine__)->id, \
			      intel_engine_initialized(engine__)))

/* Iterator over subset of engines selected by mask */
2079
#define for_each_engine_masked(engine__, dev_priv__, mask__) \
2080 2081 2082 2083 2084
	for ((engine__) = &(dev_priv__)->engine[0]; \
	     (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
	     (engine__)++) \
		for_each_if (((mask__) & intel_engine_flag(engine__)) && \
			     intel_engine_initialized(engine__))
2085

2086 2087 2088 2089 2090 2091 2092
enum hdmi_force_audio {
	HDMI_AUDIO_OFF_DVI = -2,	/* no aux data for HDMI-DVI converter */
	HDMI_AUDIO_OFF,			/* force turn off HDMI audio */
	HDMI_AUDIO_AUTO,		/* trust EDID */
	HDMI_AUDIO_ON,			/* force turn on HDMI audio */
};

2093
#define I915_GTT_OFFSET_NONE ((u32)-1)
2094

2095
struct drm_i915_gem_object_ops {
2096 2097 2098
	unsigned int flags;
#define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1

2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113
	/* Interface between the GEM object and its backing storage.
	 * get_pages() is called once prior to the use of the associated set
	 * of pages before to binding them into the GTT, and put_pages() is
	 * called after we no longer need them. As we expect there to be
	 * associated cost with migrating pages between the backing storage
	 * and making them available for the GPU (e.g. clflush), we may hold
	 * onto the pages after they are no longer referenced by the GPU
	 * in case they may be used again shortly (for example migrating the
	 * pages to a different memory domain within the GTT). put_pages()
	 * will therefore most likely be called when the object itself is
	 * being released or under memory pressure (where we attempt to
	 * reap pages for the shrinker).
	 */
	int (*get_pages)(struct drm_i915_gem_object *);
	void (*put_pages)(struct drm_i915_gem_object *);
2114

2115 2116
	int (*dmabuf_export)(struct drm_i915_gem_object *);
	void (*release)(struct drm_i915_gem_object *);
2117 2118
};

2119 2120
/*
 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2121
 * considered to be the frontbuffer for the given plane interface-wise. This
2122 2123 2124 2125 2126
 * doesn't mean that the hw necessarily already scans it out, but that any
 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
 *
 * We have one bit per pipe and per scanout plane type.
 */
2127 2128
#define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2129 2130 2131 2132 2133
#define INTEL_FRONTBUFFER_BITS \
	(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
	(1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
#define INTEL_FRONTBUFFER_CURSOR(pipe) \
2134 2135 2136
	(1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
#define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
	(1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2137
#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2138
	(1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2139
#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2140
	(0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2141

2142
struct drm_i915_gem_object {
2143
	struct drm_gem_object base;
2144

2145 2146
	const struct drm_i915_gem_object_ops *ops;

B
Ben Widawsky 已提交
2147 2148 2149
	/** List of VMAs backed by this object */
	struct list_head vma_list;

2150 2151
	/** Stolen memory for this object, instead of being backed by shmem. */
	struct drm_mm_node *stolen;
2152
	struct list_head global_list;
2153

2154 2155
	/** Used in execbuf to temporarily hold a ref */
	struct list_head obj_exec_link;
2156

2157
	struct list_head batch_pool_link;
2158

2159
	/**
2160 2161 2162
	 * This is set if the object is on the active lists (has pending
	 * rendering and so a non-zero seqno), and is not set if it i s on
	 * inactive (ready to be unbound) list.
2163
	 */
2164
	unsigned int active:I915_NUM_ENGINES;
2165 2166 2167 2168 2169

	/**
	 * This is set if the object has been written to since last bound
	 * to the GTT
	 */
2170
	unsigned int dirty:1;
2171 2172 2173 2174 2175 2176

	/**
	 * Fence register bits (if any) for this object.  Will be set
	 * as needed when mapped into the GTT.
	 * Protected by dev->struct_mutex.
	 */
2177
	signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2178 2179 2180 2181

	/**
	 * Advice: are the backing pages purgeable?
	 */
2182
	unsigned int madv:2;
2183 2184 2185 2186

	/**
	 * Current tiling mode for the object.
	 */
2187
	unsigned int tiling_mode:2;
2188 2189 2190 2191 2192 2193 2194 2195
	/**
	 * Whether the tiling parameters for the currently associated fence
	 * register have changed. Note that for the purposes of tracking
	 * tiling changes we also treat the unfenced register, the register
	 * slot that the object occupies whilst it executes a fenced
	 * command (such as BLT on gen2/3), as a "fence".
	 */
	unsigned int fence_dirty:1;
2196

2197 2198 2199 2200
	/**
	 * Is the object at the current location in the gtt mappable and
	 * fenceable? Used to avoid costly recalculations.
	 */
2201
	unsigned int map_and_fenceable:1;
2202

2203 2204 2205 2206 2207
	/**
	 * Whether the current gtt mapping needs to be mappable (and isn't just
	 * mappable by accident). Track pin and fault separate for a more
	 * accurate mappable working set.
	 */
2208
	unsigned int fault_mappable:1;
2209

2210 2211 2212 2213 2214
	/*
	 * Is the object to be mapped as read-only to the GPU
	 * Only honoured if hardware has relevant pte bit
	 */
	unsigned long gt_ro:1;
2215
	unsigned int cache_level:3;
2216
	unsigned int cache_dirty:1;
2217

2218 2219
	unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;

2220
	unsigned int has_wc_mmap;
2221 2222
	/** Count of VMA actually bound by this object */
	unsigned int bind_count;
2223 2224
	unsigned int pin_display;

2225
	struct sg_table *pages;
2226
	int pages_pin_count;
2227 2228 2229 2230
	struct get_page {
		struct scatterlist *sg;
		int last;
	} get_page;
2231
	void *mapping;
2232

2233 2234 2235 2236 2237 2238 2239 2240 2241
	/** Breadcrumb of last rendering to the buffer.
	 * There can only be one writer, but we allow for multiple readers.
	 * If there is a writer that necessarily implies that all other
	 * read requests are complete - but we may only be lazily clearing
	 * the read requests. A read request is naturally the most recent
	 * request on a ring, so we may have two different write and read
	 * requests on one ring where the write request is older than the
	 * read request. This allows for the CPU to read from an active
	 * buffer by only waiting for the write to complete.
2242 2243 2244 2245
	 */
	struct i915_gem_active last_read[I915_NUM_ENGINES];
	struct i915_gem_active last_write;
	struct i915_gem_active last_fence;
2246

2247
	/** Current tiling stride for the object, if it's tiled. */
2248
	uint32_t stride;
2249

2250 2251 2252
	/** References from framebuffers, locks out tiling changes. */
	unsigned long framebuffer_references;

2253
	/** Record of address bit 17 of each page at last unbind. */
2254
	unsigned long *bit_17;
2255

2256
	union {
2257 2258 2259
		/** for phy allocated objects */
		struct drm_dma_handle *phys_handle;

2260 2261 2262 2263 2264 2265
		struct i915_gem_userptr {
			uintptr_t ptr;
			unsigned read_only :1;
			unsigned workers :4;
#define I915_GEM_USERPTR_MAX_WORKERS 15

2266 2267
			struct i915_mm_struct *mm;
			struct i915_mmu_object *mmu_object;
2268 2269 2270 2271
			struct work_struct *work;
		} userptr;
	};
};
2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290

static inline struct drm_i915_gem_object *
to_intel_bo(struct drm_gem_object *gem)
{
	/* Assert that to_intel_bo(NULL) == NULL */
	BUILD_BUG_ON(offsetof(struct drm_i915_gem_object, base));

	return container_of(gem, struct drm_i915_gem_object, base);
}

static inline struct drm_i915_gem_object *
i915_gem_object_lookup(struct drm_file *file, u32 handle)
{
	return to_intel_bo(drm_gem_object_lookup(file, handle));
}

__deprecated
extern struct drm_gem_object *
drm_gem_object_lookup(struct drm_file *file, u32 handle);
2291

2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302
__attribute__((nonnull))
static inline struct drm_i915_gem_object *
i915_gem_object_get(struct drm_i915_gem_object *obj)
{
	drm_gem_object_reference(&obj->base);
	return obj;
}

__deprecated
extern void drm_gem_object_reference(struct drm_gem_object *);

2303 2304 2305 2306 2307 2308 2309 2310 2311 2312
__attribute__((nonnull))
static inline void
i915_gem_object_put(struct drm_i915_gem_object *obj)
{
	drm_gem_object_unreference(&obj->base);
}

__deprecated
extern void drm_gem_object_unreference(struct drm_gem_object *);

2313 2314 2315 2316 2317 2318 2319 2320 2321 2322
__attribute__((nonnull))
static inline void
i915_gem_object_put_unlocked(struct drm_i915_gem_object *obj)
{
	drm_gem_object_unreference_unlocked(&obj->base);
}

__deprecated
extern void drm_gem_object_unreference_unlocked(struct drm_gem_object *);

2323 2324 2325 2326 2327 2328
static inline bool
i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj)
{
	return obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE;
}

2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354
/*
 * Optimised SGL iterator for GEM objects
 */
static __always_inline struct sgt_iter {
	struct scatterlist *sgp;
	union {
		unsigned long pfn;
		dma_addr_t dma;
	};
	unsigned int curr;
	unsigned int max;
} __sgt_iter(struct scatterlist *sgl, bool dma) {
	struct sgt_iter s = { .sgp = sgl };

	if (s.sgp) {
		s.max = s.curr = s.sgp->offset;
		s.max += s.sgp->length;
		if (dma)
			s.dma = sg_dma_address(s.sgp);
		else
			s.pfn = page_to_pfn(sg_page(s.sgp));
	}

	return s;
}

2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373
/**
 * __sg_next - return the next scatterlist entry in a list
 * @sg:		The current sg entry
 *
 * Description:
 *   If the entry is the last, return NULL; otherwise, step to the next
 *   element in the array (@sg@+1). If that's a chain pointer, follow it;
 *   otherwise just return the pointer to the current element.
 **/
static inline struct scatterlist *__sg_next(struct scatterlist *sg)
{
#ifdef CONFIG_DEBUG_SG
	BUG_ON(sg->sg_magic != SG_MAGIC);
#endif
	return sg_is_last(sg) ? NULL :
		likely(!sg_is_chain(++sg)) ? sg :
		sg_chain_ptr(sg);
}

2374 2375 2376 2377 2378 2379 2380 2381 2382 2383
/**
 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
 * @__dmap:	DMA address (output)
 * @__iter:	'struct sgt_iter' (iterator state, internal)
 * @__sgt:	sg_table to iterate over (input)
 */
#define for_each_sgt_dma(__dmap, __iter, __sgt)				\
	for ((__iter) = __sgt_iter((__sgt)->sgl, true);			\
	     ((__dmap) = (__iter).dma + (__iter).curr);			\
	     (((__iter).curr += PAGE_SIZE) < (__iter).max) ||		\
2384
	     ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396

/**
 * for_each_sgt_page - iterate over the pages of the given sg_table
 * @__pp:	page pointer (output)
 * @__iter:	'struct sgt_iter' (iterator state, internal)
 * @__sgt:	sg_table to iterate over (input)
 */
#define for_each_sgt_page(__pp, __iter, __sgt)				\
	for ((__iter) = __sgt_iter((__sgt)->sgl, false);		\
	     ((__pp) = (__iter).pfn == 0 ? NULL :			\
	      pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
	     (((__iter).curr += PAGE_SIZE) < (__iter).max) ||		\
2397
	     ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2398

2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450
/*
 * A command that requires special handling by the command parser.
 */
struct drm_i915_cmd_descriptor {
	/*
	 * Flags describing how the command parser processes the command.
	 *
	 * CMD_DESC_FIXED: The command has a fixed length if this is set,
	 *                 a length mask if not set
	 * CMD_DESC_SKIP: The command is allowed but does not follow the
	 *                standard length encoding for the opcode range in
	 *                which it falls
	 * CMD_DESC_REJECT: The command is never allowed
	 * CMD_DESC_REGISTER: The command should be checked against the
	 *                    register whitelist for the appropriate ring
	 * CMD_DESC_MASTER: The command is allowed if the submitting process
	 *                  is the DRM master
	 */
	u32 flags;
#define CMD_DESC_FIXED    (1<<0)
#define CMD_DESC_SKIP     (1<<1)
#define CMD_DESC_REJECT   (1<<2)
#define CMD_DESC_REGISTER (1<<3)
#define CMD_DESC_BITMASK  (1<<4)
#define CMD_DESC_MASTER   (1<<5)

	/*
	 * The command's unique identification bits and the bitmask to get them.
	 * This isn't strictly the opcode field as defined in the spec and may
	 * also include type, subtype, and/or subop fields.
	 */
	struct {
		u32 value;
		u32 mask;
	} cmd;

	/*
	 * The command's length. The command is either fixed length (i.e. does
	 * not include a length field) or has a length field mask. The flag
	 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
	 * a length mask. All command entries in a command table must include
	 * length information.
	 */
	union {
		u32 fixed;
		u32 mask;
	} length;

	/*
	 * Describes where to find a register address in the command to check
	 * against the ring's register whitelist. Only valid if flags has the
	 * CMD_DESC_REGISTER bit set.
2451 2452 2453 2454
	 *
	 * A non-zero step value implies that the command may access multiple
	 * registers in sequence (e.g. LRI), in that case step gives the
	 * distance in dwords between individual offset fields.
2455 2456 2457 2458
	 */
	struct {
		u32 offset;
		u32 mask;
2459
		u32 step;
2460 2461 2462 2463 2464 2465 2466 2467 2468
	} reg;

#define MAX_CMD_DESC_BITMASKS 3
	/*
	 * Describes command checks where a particular dword is masked and
	 * compared against an expected value. If the command does not match
	 * the expected value, the parser rejects it. Only valid if flags has
	 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
	 * are valid.
2469 2470 2471 2472
	 *
	 * If the check specifies a non-zero condition_mask then the parser
	 * only performs the check when the bits specified by condition_mask
	 * are non-zero.
2473 2474 2475 2476 2477
	 */
	struct {
		u32 offset;
		u32 mask;
		u32 expected;
2478 2479
		u32 condition_offset;
		u32 condition_mask;
2480 2481 2482 2483 2484 2485
	} bits[MAX_CMD_DESC_BITMASKS];
};

/*
 * A table of commands requiring special handling by the command parser.
 *
2486 2487 2488
 * Each engine has an array of tables. Each table consists of an array of
 * command descriptors, which must be sorted with command opcodes in
 * ascending order.
2489 2490 2491 2492 2493 2494
 */
struct drm_i915_cmd_table {
	const struct drm_i915_cmd_descriptor *table;
	int count;
};

C
Chris Wilson 已提交
2495
/* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2496 2497 2498 2499 2500 2501 2502 2503 2504 2505
#define __I915__(p) ({ \
	struct drm_i915_private *__p; \
	if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
		__p = (struct drm_i915_private *)p; \
	else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
		__p = to_i915((struct drm_device *)p); \
	else \
		BUILD_BUG(); \
	__p; \
})
C
Chris Wilson 已提交
2506
#define INTEL_INFO(p) 	(&__I915__(p)->info)
2507
#define INTEL_GEN(p)	(INTEL_INFO(p)->gen)
2508
#define INTEL_DEVID(p)	(INTEL_INFO(p)->device_id)
2509

2510
#define REVID_FOREVER		0xff
2511
#define INTEL_REVID(p)	(__I915__(p)->drm.pdev->revision)
2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531

#define GEN_FOREVER (0)
/*
 * Returns true if Gen is in inclusive range [Start, End].
 *
 * Use GEN_FOREVER for unbound start and or end.
 */
#define IS_GEN(p, s, e) ({ \
	unsigned int __s = (s), __e = (e); \
	BUILD_BUG_ON(!__builtin_constant_p(s)); \
	BUILD_BUG_ON(!__builtin_constant_p(e)); \
	if ((__s) != GEN_FOREVER) \
		__s = (s) - 1; \
	if ((__e) == GEN_FOREVER) \
		__e = BITS_PER_LONG - 1; \
	else \
		__e = (e) - 1; \
	!!(INTEL_INFO(p)->gen_mask & GENMASK((__e), (__s))); \
})

2532 2533 2534 2535 2536 2537 2538 2539
/*
 * Return true if revision is in range [since,until] inclusive.
 *
 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
 */
#define IS_REVID(p, since, until) \
	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))

2540 2541
#define IS_I830(dev)		(INTEL_DEVID(dev) == 0x3577)
#define IS_845G(dev)		(INTEL_DEVID(dev) == 0x2562)
2542
#define IS_I85X(dev)		(INTEL_INFO(dev)->is_i85x)
2543
#define IS_I865G(dev)		(INTEL_DEVID(dev) == 0x2572)
2544
#define IS_I915G(dev)		(INTEL_INFO(dev)->is_i915g)
2545 2546
#define IS_I915GM(dev)		(INTEL_DEVID(dev) == 0x2592)
#define IS_I945G(dev)		(INTEL_DEVID(dev) == 0x2772)
2547 2548 2549
#define IS_I945GM(dev)		(INTEL_INFO(dev)->is_i945gm)
#define IS_BROADWATER(dev)	(INTEL_INFO(dev)->is_broadwater)
#define IS_CRESTLINE(dev)	(INTEL_INFO(dev)->is_crestline)
2550
#define IS_GM45(dev)		(INTEL_DEVID(dev) == 0x2A42)
2551
#define IS_G4X(dev)		(INTEL_INFO(dev)->is_g4x)
2552 2553
#define IS_PINEVIEW_G(dev)	(INTEL_DEVID(dev) == 0xa001)
#define IS_PINEVIEW_M(dev)	(INTEL_DEVID(dev) == 0xa011)
2554 2555
#define IS_PINEVIEW(dev)	(INTEL_INFO(dev)->is_pineview)
#define IS_G33(dev)		(INTEL_INFO(dev)->is_g33)
2556
#define IS_IRONLAKE_M(dev)	(INTEL_DEVID(dev) == 0x0046)
2557
#define IS_IVYBRIDGE(dev)	(INTEL_INFO(dev)->is_ivybridge)
2558 2559 2560
#define IS_IVB_GT1(dev)		(INTEL_DEVID(dev) == 0x0156 || \
				 INTEL_DEVID(dev) == 0x0152 || \
				 INTEL_DEVID(dev) == 0x015a)
2561
#define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)
2562
#define IS_CHERRYVIEW(dev)	(INTEL_INFO(dev)->is_cherryview)
2563
#define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
2564
#define IS_BROADWELL(dev)	(INTEL_INFO(dev)->is_broadwell)
2565
#define IS_SKYLAKE(dev)	(INTEL_INFO(dev)->is_skylake)
2566
#define IS_BROXTON(dev)		(INTEL_INFO(dev)->is_broxton)
2567
#define IS_KABYLAKE(dev)	(INTEL_INFO(dev)->is_kabylake)
2568
#define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
2569
#define IS_HSW_EARLY_SDV(dev)	(IS_HASWELL(dev) && \
2570
				 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
B
Ben Widawsky 已提交
2571
#define IS_BDW_ULT(dev)		(IS_BROADWELL(dev) && \
2572
				 ((INTEL_DEVID(dev) & 0xf) == 0x6 ||	\
2573
				 (INTEL_DEVID(dev) & 0xf) == 0xb ||	\
2574
				 (INTEL_DEVID(dev) & 0xf) == 0xe))
V
Ville Syrjälä 已提交
2575 2576 2577
/* ULX machines are also considered ULT. */
#define IS_BDW_ULX(dev)		(IS_BROADWELL(dev) && \
				 (INTEL_DEVID(dev) & 0xf) == 0xe)
R
Rodrigo Vivi 已提交
2578 2579
#define IS_BDW_GT3(dev)		(IS_BROADWELL(dev) && \
				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
B
Ben Widawsky 已提交
2580
#define IS_HSW_ULT(dev)		(IS_HASWELL(dev) && \
2581
				 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2582
#define IS_HSW_GT3(dev)		(IS_HASWELL(dev) && \
2583
				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2584
/* ULX machines are also considered ULT. */
2585 2586
#define IS_HSW_ULX(dev)		(INTEL_DEVID(dev) == 0x0A0E || \
				 INTEL_DEVID(dev) == 0x0A1E)
2587 2588 2589 2590 2591 2592 2593 2594
#define IS_SKL_ULT(dev)		(INTEL_DEVID(dev) == 0x1906 || \
				 INTEL_DEVID(dev) == 0x1913 || \
				 INTEL_DEVID(dev) == 0x1916 || \
				 INTEL_DEVID(dev) == 0x1921 || \
				 INTEL_DEVID(dev) == 0x1926)
#define IS_SKL_ULX(dev)		(INTEL_DEVID(dev) == 0x190E || \
				 INTEL_DEVID(dev) == 0x1915 || \
				 INTEL_DEVID(dev) == 0x191E)
2595 2596 2597 2598 2599 2600 2601 2602
#define IS_KBL_ULT(dev)		(INTEL_DEVID(dev) == 0x5906 || \
				 INTEL_DEVID(dev) == 0x5913 || \
				 INTEL_DEVID(dev) == 0x5916 || \
				 INTEL_DEVID(dev) == 0x5921 || \
				 INTEL_DEVID(dev) == 0x5926)
#define IS_KBL_ULX(dev)		(INTEL_DEVID(dev) == 0x590E || \
				 INTEL_DEVID(dev) == 0x5915 || \
				 INTEL_DEVID(dev) == 0x591E)
2603 2604 2605 2606 2607
#define IS_SKL_GT3(dev)		(IS_SKYLAKE(dev) && \
				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
#define IS_SKL_GT4(dev)		(IS_SKYLAKE(dev) && \
				 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)

2608
#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2609

2610 2611 2612 2613 2614 2615
#define SKL_REVID_A0		0x0
#define SKL_REVID_B0		0x1
#define SKL_REVID_C0		0x2
#define SKL_REVID_D0		0x3
#define SKL_REVID_E0		0x4
#define SKL_REVID_F0		0x5
2616 2617
#define SKL_REVID_G0		0x6
#define SKL_REVID_H0		0x7
2618

2619 2620
#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))

2621
#define BXT_REVID_A0		0x0
2622
#define BXT_REVID_A1		0x1
2623 2624
#define BXT_REVID_B0		0x3
#define BXT_REVID_C0		0x9
N
Nick Hoath 已提交
2625

2626 2627
#define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))

M
Mika Kuoppala 已提交
2628 2629
#define KBL_REVID_A0		0x0
#define KBL_REVID_B0		0x1
2630 2631 2632
#define KBL_REVID_C0		0x2
#define KBL_REVID_D0		0x3
#define KBL_REVID_E0		0x4
M
Mika Kuoppala 已提交
2633 2634 2635 2636

#define IS_KBL_REVID(p, since, until) \
	(IS_KABYLAKE(p) && IS_REVID(p, since, until))

2637 2638 2639 2640 2641 2642
/*
 * The genX designation typically refers to the render engine, so render
 * capability related checks should use IS_GEN, while display and other checks
 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
 * chips, etc.).
 */
2643 2644 2645 2646 2647 2648 2649 2650
#define IS_GEN2(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(1)))
#define IS_GEN3(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(2)))
#define IS_GEN4(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(3)))
#define IS_GEN5(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(4)))
#define IS_GEN6(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(5)))
#define IS_GEN7(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(6)))
#define IS_GEN8(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(7)))
#define IS_GEN9(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(8)))
2651

2652 2653 2654 2655 2656 2657 2658 2659 2660
#define ENGINE_MASK(id)	BIT(id)
#define RENDER_RING	ENGINE_MASK(RCS)
#define BSD_RING	ENGINE_MASK(VCS)
#define BLT_RING	ENGINE_MASK(BCS)
#define VEBOX_RING	ENGINE_MASK(VECS)
#define BSD2_RING	ENGINE_MASK(VCS2)
#define ALL_ENGINES	(~0)

#define HAS_ENGINE(dev_priv, id) \
2661
	(!!(INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id)))
2662 2663 2664 2665 2666 2667

#define HAS_BSD(dev_priv)	HAS_ENGINE(dev_priv, VCS)
#define HAS_BSD2(dev_priv)	HAS_ENGINE(dev_priv, VCS2)
#define HAS_BLT(dev_priv)	HAS_ENGINE(dev_priv, BCS)
#define HAS_VEBOX(dev_priv)	HAS_ENGINE(dev_priv, VECS)

2668
#define HAS_LLC(dev)		(INTEL_INFO(dev)->has_llc)
2669
#define HAS_SNOOP(dev)		(INTEL_INFO(dev)->has_snoop)
2670
#define HAS_EDRAM(dev)		(!!(__I915__(dev)->edram_cap & EDRAM_ENABLED))
2671
#define HAS_WT(dev)		((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2672
				 HAS_EDRAM(dev))
2673 2674
#define I915_NEED_GFX_HWS(dev)	(INTEL_INFO(dev)->need_gfx_hws)

2675
#define HAS_HW_CONTEXTS(dev)	(INTEL_INFO(dev)->gen >= 6)
2676
#define HAS_LOGICAL_RING_CONTEXTS(dev)	(INTEL_INFO(dev)->gen >= 8)
2677
#define USES_PPGTT(dev)		(i915.enable_ppgtt)
2678 2679
#define USES_FULL_PPGTT(dev)	(i915.enable_ppgtt >= 2)
#define USES_FULL_48BIT_PPGTT(dev)	(i915.enable_ppgtt == 3)
2680

2681
#define HAS_OVERLAY(dev)		(INTEL_INFO(dev)->has_overlay)
2682 2683
#define OVERLAY_NEEDS_PHYSICAL(dev)	(INTEL_INFO(dev)->overlay_needs_physical)

2684 2685
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
#define HAS_BROKEN_CS_TLB(dev)		(IS_I830(dev) || IS_845G(dev))
2686 2687

/* WaRsDisableCoarsePowerGating:skl,bxt */
2688 2689 2690 2691
#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
	(IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \
	 IS_SKL_GT3(dev_priv) || \
	 IS_SKL_GT4(dev_priv))
2692

2693 2694 2695 2696 2697 2698 2699 2700
/*
 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
 * even when in MSI mode. This results in spurious interrupt warnings if the
 * legacy irq no. is shared with another device. The kernel then disables that
 * interrupt source and so prevents the other device from working properly.
 */
#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2701

2702 2703 2704 2705 2706 2707 2708 2709 2710 2711
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 * rows, which changed the alignment requirements and fence programming.
 */
#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
						      IS_I915GM(dev)))
#define SUPPORTS_TV(dev)		(INTEL_INFO(dev)->supports_tv)
#define I915_HAS_HOTPLUG(dev)		 (INTEL_INFO(dev)->has_hotplug)

#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2712
#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2713

2714
#define HAS_IPS(dev)		(IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2715

2716 2717 2718
#define HAS_DP_MST(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev) || \
				 INTEL_INFO(dev)->gen >= 9)

2719
#define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)
2720
#define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
2721
#define HAS_PSR(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2722
				 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2723
				 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2724
#define HAS_RUNTIME_PM(dev)	(IS_GEN6(dev) || IS_HASWELL(dev) || \
S
Suketu Shah 已提交
2725
				 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2726
				 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
I
Imre Deak 已提交
2727
				 IS_KABYLAKE(dev) || IS_BROXTON(dev))
2728
#define HAS_RC6(dev)		(INTEL_INFO(dev)->gen >= 6)
2729
#define HAS_RC6p(dev)		(IS_GEN6(dev) || IS_IVYBRIDGE(dev))
P
Paulo Zanoni 已提交
2730

2731
#define HAS_CSR(dev)	(IS_GEN9(dev))
2732

2733 2734 2735 2736 2737
/*
 * For now, anything with a GuC requires uCode loading, and then supports
 * command submission once loaded. But these are logically independent
 * properties, so we have separate macros to test them.
 */
2738
#define HAS_GUC(dev)		(IS_GEN9(dev))
2739 2740
#define HAS_GUC_UCODE(dev)	(HAS_GUC(dev))
#define HAS_GUC_SCHED(dev)	(HAS_GUC(dev))
2741

2742 2743 2744
#define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
				    INTEL_INFO(dev)->gen >= 8)

2745
#define HAS_CORE_RING_FREQ(dev)	(INTEL_INFO(dev)->gen >= 6 && \
2746 2747
				 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
				 !IS_BROXTON(dev))
2748

2749 2750
#define HAS_POOLED_EU(dev)	(INTEL_INFO(dev)->has_pooled_eu)

2751 2752 2753 2754 2755 2756
#define INTEL_PCH_DEVICE_ID_MASK		0xff00
#define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
#define INTEL_PCH_PPT_DEVICE_ID_TYPE		0x1e00
#define INTEL_PCH_LPT_DEVICE_ID_TYPE		0x8c00
#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE		0x9c00
2757 2758
#define INTEL_PCH_SPT_DEVICE_ID_TYPE		0xA100
#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE		0x9D00
2759
#define INTEL_PCH_KBP_DEVICE_ID_TYPE		0xA200
2760
#define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
2761
#define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
2762
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
2763

2764
#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2765
#define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP)
2766
#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2767
#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2768
#define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
V
Ville Syrjälä 已提交
2769
#define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2770 2771
#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
B
Ben Widawsky 已提交
2772
#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2773
#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2774

2775 2776
#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
			       IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2777

2778 2779 2780
/* DPF == dynamic parity feature */
#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2781

2782
#define GT_FREQUENCY_MULTIPLIER 50
A
Akash Goel 已提交
2783
#define GEN9_FREQ_SCALER 3
2784

2785 2786
#include "i915_trace.h"

2787 2788 2789 2790 2791 2792 2793 2794 2795
static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
{
#ifdef CONFIG_INTEL_IOMMU
	if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped)
		return true;
#endif
	return false;
}

2796 2797
extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
extern int i915_resume_switcheroo(struct drm_device *dev);
2798

2799 2800
int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
			       	int enable_ppgtt);
2801

2802 2803
bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);

2804
/* i915_drv.c */
2805 2806 2807 2808 2809 2810 2811
void __printf(3, 4)
__i915_printk(struct drm_i915_private *dev_priv, const char *level,
	      const char *fmt, ...);

#define i915_report_error(dev_priv, fmt, ...)				   \
	__i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)

2812
#ifdef CONFIG_COMPAT
D
Dave Airlie 已提交
2813 2814
extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
			      unsigned long arg);
2815
#endif
2816 2817
extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2818
extern int i915_reset(struct drm_i915_private *dev_priv);
2819
extern int intel_guc_reset(struct drm_i915_private *dev_priv);
2820
extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2821 2822 2823 2824
extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2825
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2826

2827
/* intel_hotplug.c */
2828 2829
void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
			   u32 pin_mask, u32 long_mask);
2830 2831 2832
void intel_hpd_init(struct drm_i915_private *dev_priv);
void intel_hpd_init_work(struct drm_i915_private *dev_priv);
void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2833
bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2834 2835
bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2836

L
Linus Torvalds 已提交
2837
/* i915_irq.c */
2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854
static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
{
	unsigned long delay;

	if (unlikely(!i915.enable_hangcheck))
		return;

	/* Don't continually defer the hangcheck so that it is always run at
	 * least once after work has been scheduled on any ring. Otherwise,
	 * we will ignore a hung ring if a second ring is kept busy.
	 */

	delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
	queue_delayed_work(system_long_wq,
			   &dev_priv->gpu_error.hangcheck_work, delay);
}

2855
__printf(3, 4)
2856 2857
void i915_handle_error(struct drm_i915_private *dev_priv,
		       u32 engine_mask,
2858
		       const char *fmt, ...);
L
Linus Torvalds 已提交
2859

2860
extern void intel_irq_init(struct drm_i915_private *dev_priv);
2861 2862
int intel_irq_install(struct drm_i915_private *dev_priv);
void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2863

2864 2865
extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
2866
					bool restore_forcewake);
2867
extern void intel_uncore_init(struct drm_i915_private *dev_priv);
2868
extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
2869
extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
2870 2871 2872
extern void intel_uncore_fini(struct drm_i915_private *dev_priv);
extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
					 bool restore);
2873
const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2874
void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2875
				enum forcewake_domains domains);
2876
void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2877
				enum forcewake_domains domains);
2878 2879 2880 2881 2882 2883 2884
/* Like above but the caller must manage the uncore.lock itself.
 * Must be used with I915_READ_FW and friends.
 */
void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
					enum forcewake_domains domains);
void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
					enum forcewake_domains domains);
2885 2886
u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);

2887
void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2888

2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899
int intel_wait_for_register(struct drm_i915_private *dev_priv,
			    i915_reg_t reg,
			    const u32 mask,
			    const u32 value,
			    const unsigned long timeout_ms);
int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
			       i915_reg_t reg,
			       const u32 mask,
			       const u32 value,
			       const unsigned long timeout_ms);

2900 2901 2902 2903 2904
static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
{
	return dev_priv->gvt.initialized;
}

2905
static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2906
{
2907
	return dev_priv->vgpu.active;
2908
}
2909

2910
void
2911
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2912
		     u32 status_mask);
2913 2914

void
2915
i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2916
		      u32 status_mask);
2917

2918 2919
void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2920 2921 2922
void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
				   uint32_t mask,
				   uint32_t bits);
2923 2924 2925 2926 2927 2928 2929 2930 2931 2932 2933 2934 2935
void ilk_update_display_irq(struct drm_i915_private *dev_priv,
			    uint32_t interrupt_mask,
			    uint32_t enabled_irq_mask);
static inline void
ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, bits);
}
static inline void
ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, 0);
}
2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947 2948 2949
void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
			 enum pipe pipe,
			 uint32_t interrupt_mask,
			 uint32_t enabled_irq_mask);
static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
				       enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
}
static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
					enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
}
2950 2951 2952
void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
				  uint32_t interrupt_mask,
				  uint32_t enabled_irq_mask);
2953 2954 2955 2956 2957 2958 2959 2960 2961 2962 2963
static inline void
ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, bits);
}
static inline void
ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, 0);
}

2964 2965 2966 2967 2968 2969 2970 2971 2972
/* i915_gem.c */
int i915_gem_create_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2973 2974
int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2975 2976 2977 2978 2979 2980
int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
			     struct drm_file *file_priv);
int i915_gem_execbuffer(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
J
Jesse Barnes 已提交
2981 2982
int i915_gem_execbuffer2(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
2983 2984
int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
B
Ben Widawsky 已提交
2985 2986 2987 2988
int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
2989 2990
int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *file_priv);
2991 2992
int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
2993 2994 2995 2996
int i915_gem_set_tiling(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
int i915_gem_get_tiling(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2997
void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
2998 2999
int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file);
3000 3001
int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
3002 3003
int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3004 3005
void i915_gem_load_init(struct drm_device *dev);
void i915_gem_load_cleanup(struct drm_device *dev);
3006
void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3007 3008
int i915_gem_freeze_late(struct drm_i915_private *dev_priv);

3009 3010
void *i915_gem_object_alloc(struct drm_device *dev);
void i915_gem_object_free(struct drm_i915_gem_object *obj);
3011 3012
void i915_gem_object_init(struct drm_i915_gem_object *obj,
			 const struct drm_i915_gem_object_ops *ops);
3013
struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev,
3014
						  size_t size);
3015 3016
struct drm_i915_gem_object *i915_gem_object_create_from_data(
		struct drm_device *dev, const void *data, size_t size);
3017
void i915_gem_free_object(struct drm_gem_object *obj);
B
Ben Widawsky 已提交
3018
void i915_gem_vma_destroy(struct i915_vma *vma);
3019

3020 3021 3022 3023 3024 3025 3026
/* Flags used by pin/bind&friends. */
#define PIN_MAPPABLE	(1<<0)
#define PIN_NONBLOCK	(1<<1)
#define PIN_GLOBAL	(1<<2)
#define PIN_OFFSET_BIAS	(1<<3)
#define PIN_USER	(1<<4)
#define PIN_UPDATE	(1<<5)
3027 3028
#define PIN_ZONE_4G	(1<<6)
#define PIN_HIGH	(1<<7)
3029
#define PIN_OFFSET_FIXED	(1<<8)
3030
#define PIN_OFFSET_MASK (~4095)
3031 3032 3033 3034 3035 3036 3037 3038 3039 3040
int __must_check
i915_gem_object_pin(struct drm_i915_gem_object *obj,
		    struct i915_address_space *vm,
		    uint32_t alignment,
		    uint64_t flags);
int __must_check
i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
			 const struct i915_ggtt_view *view,
			 uint32_t alignment,
			 uint64_t flags);
3041 3042 3043

int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
		  u32 flags);
3044
void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
3045
int __must_check i915_vma_unbind(struct i915_vma *vma);
3046 3047 3048 3049 3050
/*
 * BEWARE: Do not use the function below unless you can _absolutely_
 * _guarantee_ VMA in question is _not in use_ anywhere.
 */
int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
3051 3052

int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
3053
int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
3054
void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
3055
void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3056

3057 3058 3059
int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
				    int *needs_clflush);

3060
int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
3061 3062

static inline int __sg_page_count(struct scatterlist *sg)
3063
{
3064 3065
	return sg->length >> PAGE_SHIFT;
}
3066

3067 3068 3069
struct page *
i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n);

3070 3071 3072 3073 3074 3075 3076 3077 3078 3079 3080 3081 3082 3083 3084 3085 3086
static inline dma_addr_t
i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, int n)
{
	if (n < obj->get_page.last) {
		obj->get_page.sg = obj->pages->sgl;
		obj->get_page.last = 0;
	}

	while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
		obj->get_page.last += __sg_page_count(obj->get_page.sg++);
		if (unlikely(sg_is_chain(obj->get_page.sg)))
			obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
	}

	return sg_dma_address(obj->get_page.sg) + ((n - obj->get_page.last) << PAGE_SHIFT);
}

3087 3088
static inline struct page *
i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
3089
{
3090 3091
	if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
		return NULL;
3092

3093 3094 3095 3096
	if (n < obj->get_page.last) {
		obj->get_page.sg = obj->pages->sgl;
		obj->get_page.last = 0;
	}
3097

3098 3099 3100 3101 3102
	while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
		obj->get_page.last += __sg_page_count(obj->get_page.sg++);
		if (unlikely(sg_is_chain(obj->get_page.sg)))
			obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
	}
3103

3104
	return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
3105
}
3106

3107 3108 3109 3110 3111
static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
{
	BUG_ON(obj->pages == NULL);
	obj->pages_pin_count++;
}
3112

3113 3114 3115 3116 3117 3118
static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
{
	BUG_ON(obj->pages_pin_count == 0);
	obj->pages_pin_count--;
}

3119 3120 3121 3122 3123 3124 3125 3126
/**
 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
 * @obj - the object to map into kernel address space
 *
 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
 * pages and then returns a contiguous mapping of the backing storage into
 * the kernel address space.
 *
3127 3128
 * The caller must hold the struct_mutex, and is responsible for calling
 * i915_gem_object_unpin_map() when the mapping is no longer required.
3129
 *
3130 3131
 * Returns the pointer through which to access the mapped object, or an
 * ERR_PTR() on error.
3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150 3151
 */
void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj);

/**
 * i915_gem_object_unpin_map - releases an earlier mapping
 * @obj - the object to unmap
 *
 * After pinning the object and mapping its pages, once you are finished
 * with your access, call i915_gem_object_unpin_map() to release the pin
 * upon the mapping. Once the pin count reaches zero, that mapping may be
 * removed.
 *
 * The caller must hold the struct_mutex.
 */
static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
{
	lockdep_assert_held(&obj->base.dev->struct_mutex);
	i915_gem_object_unpin_pages(obj);
}

3152
int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3153
int i915_gem_object_sync(struct drm_i915_gem_object *obj,
3154
			 struct drm_i915_gem_request *to);
B
Ben Widawsky 已提交
3155
void i915_vma_move_to_active(struct i915_vma *vma,
3156 3157
			     struct drm_i915_gem_request *req,
			     unsigned int flags);
3158 3159 3160
int i915_gem_dumb_create(struct drm_file *file_priv,
			 struct drm_device *dev,
			 struct drm_mode_create_dumb *args);
3161 3162
int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
		      uint32_t handle, uint64_t *offset);
3163 3164 3165 3166 3167

void i915_gem_track_fb(struct drm_i915_gem_object *old,
		       struct drm_i915_gem_object *new,
		       unsigned frontbuffer_bits);

3168
int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
3169

3170
struct drm_i915_gem_request *
3171
i915_gem_find_active_request(struct intel_engine_cs *engine);
3172

3173
void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3174
void i915_gem_retire_requests_ring(struct intel_engine_cs *engine);
3175

3176 3177 3178 3179 3180 3181 3182 3183 3184 3185 3186 3187 3188 3189 3190 3191 3192 3193 3194 3195
static inline u32 i915_reset_counter(struct i915_gpu_error *error)
{
	return atomic_read(&error->reset_counter);
}

static inline bool __i915_reset_in_progress(u32 reset)
{
	return unlikely(reset & I915_RESET_IN_PROGRESS_FLAG);
}

static inline bool __i915_reset_in_progress_or_wedged(u32 reset)
{
	return unlikely(reset & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
}

static inline bool __i915_terminally_wedged(u32 reset)
{
	return unlikely(reset & I915_WEDGED);
}

3196 3197
static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
{
3198 3199 3200 3201 3202 3203
	return __i915_reset_in_progress(i915_reset_counter(error));
}

static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error)
{
	return __i915_reset_in_progress_or_wedged(i915_reset_counter(error));
3204 3205 3206 3207
}

static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
{
3208
	return __i915_terminally_wedged(i915_reset_counter(error));
M
Mika Kuoppala 已提交
3209 3210 3211 3212
}

static inline u32 i915_reset_count(struct i915_gpu_error *error)
{
3213
	return ((i915_reset_counter(error) & ~I915_WEDGED) + 1) / 2;
3214
}
3215

3216
void i915_gem_reset(struct drm_device *dev);
3217
bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3218
int __must_check i915_gem_init(struct drm_device *dev);
3219 3220
int __must_check i915_gem_init_hw(struct drm_device *dev);
void i915_gem_init_swizzling(struct drm_device *dev);
3221
void i915_gem_cleanup_engines(struct drm_device *dev);
3222
int __must_check i915_gem_wait_for_idle(struct drm_i915_private *dev_priv);
3223
int __must_check i915_gem_suspend(struct drm_device *dev);
3224
void i915_gem_resume(struct drm_device *dev);
3225
int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3226
int __must_check
3227 3228 3229
i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
			       bool readonly);
int __must_check
3230 3231 3232
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
				  bool write);
int __must_check
3233 3234
i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
int __must_check
3235 3236
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
				     u32 alignment,
3237 3238 3239
				     const struct i915_ggtt_view *view);
void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
					      const struct i915_ggtt_view *view);
3240
int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3241
				int align);
3242
int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3243
void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3244

3245 3246
uint32_t
i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
3247
uint32_t
3248 3249
i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
			    int tiling_mode, bool fenced);
3250

3251 3252 3253
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
				    enum i915_cache_level cache_level);

3254 3255 3256 3257 3258 3259
struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
				struct dma_buf *dma_buf);

struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
				struct drm_gem_object *gem_obj, int flags);

3260 3261 3262 3263 3264
u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
				  const struct i915_ggtt_view *view);
u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
			struct i915_address_space *vm);
static inline u64
3265
i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
3266
{
3267
	return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
3268
}
3269 3270

bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
3271
				  const struct i915_ggtt_view *view);
3272
bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
3273
			struct i915_address_space *vm);
3274 3275

struct i915_vma *
3276 3277 3278 3279 3280
i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
		    struct i915_address_space *vm);
struct i915_vma *
i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
			  const struct i915_ggtt_view *view);
3281

3282 3283
struct i915_vma *
i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3284 3285 3286 3287
				  struct i915_address_space *vm);
struct i915_vma *
i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
				       const struct i915_ggtt_view *view);
3288

3289 3290 3291 3292
static inline struct i915_vma *
i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
{
	return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
B
Ben Widawsky 已提交
3293
}
3294
bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
3295

3296
/* Some GGTT VM helpers */
3297 3298 3299 3300 3301 3302
static inline struct i915_hw_ppgtt *
i915_vm_to_ppgtt(struct i915_address_space *vm)
{
	return container_of(vm, struct i915_hw_ppgtt, base);
}

3303 3304
static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
{
3305
	return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
3306 3307
}

3308 3309
unsigned long
i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj);
B
Ben Widawsky 已提交
3310 3311 3312 3313

static inline int __must_check
i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
		      uint32_t alignment,
3314
		      unsigned flags)
B
Ben Widawsky 已提交
3315
{
3316 3317 3318 3319
	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
	struct i915_ggtt *ggtt = &dev_priv->ggtt;

	return i915_gem_object_pin(obj, &ggtt->base,
3320
				   alignment, flags | PIN_GLOBAL);
B
Ben Widawsky 已提交
3321
}
3322

3323 3324 3325 3326 3327 3328 3329
void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
				     const struct i915_ggtt_view *view);
static inline void
i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
{
	i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
}
3330

3331 3332 3333 3334 3335 3336 3337 3338 3339
/* i915_gem_fence.c */
int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);

bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);

void i915_gem_restore_fences(struct drm_device *dev);

3340 3341 3342 3343
void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);

3344
/* i915_gem_context.c */
3345
int __must_check i915_gem_context_init(struct drm_device *dev);
3346
void i915_gem_context_lost(struct drm_i915_private *dev_priv);
3347
void i915_gem_context_fini(struct drm_device *dev);
3348
void i915_gem_context_reset(struct drm_device *dev);
3349
int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3350
void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3351
int i915_switch_context(struct drm_i915_gem_request *req);
3352
int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv);
3353
void i915_gem_context_free(struct kref *ctx_ref);
3354 3355
struct drm_i915_gem_object *
i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3356 3357
struct i915_gem_context *
i915_gem_context_create_gvt(struct drm_device *dev);
3358 3359 3360 3361 3362 3363

static inline struct i915_gem_context *
i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
{
	struct i915_gem_context *ctx;

3364
	lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
3365 3366 3367 3368 3369 3370 3371 3372

	ctx = idr_find(&file_priv->context_idr, id);
	if (!ctx)
		return ERR_PTR(-ENOENT);

	return ctx;
}

3373 3374
static inline struct i915_gem_context *
i915_gem_context_get(struct i915_gem_context *ctx)
3375
{
3376
	kref_get(&ctx->ref);
3377
	return ctx;
3378 3379
}

3380
static inline void i915_gem_context_put(struct i915_gem_context *ctx)
3381
{
3382
	lockdep_assert_held(&ctx->i915->drm.struct_mutex);
3383
	kref_put(&ctx->ref, i915_gem_context_free);
3384 3385
}

3386
static inline bool i915_gem_context_is_default(const struct i915_gem_context *c)
3387
{
3388
	return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3389 3390
}

3391 3392 3393 3394
int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
				  struct drm_file *file);
int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
				   struct drm_file *file);
3395 3396 3397 3398
int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
				    struct drm_file *file_priv);
int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
				    struct drm_file *file_priv);
3399 3400
int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data,
				       struct drm_file *file);
3401

3402 3403 3404 3405 3406 3407
/* i915_gem_evict.c */
int __must_check i915_gem_evict_something(struct drm_device *dev,
					  struct i915_address_space *vm,
					  int min_size,
					  unsigned alignment,
					  unsigned cache_level,
3408 3409
					  unsigned long start,
					  unsigned long end,
3410
					  unsigned flags);
3411
int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
3412
int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3413

3414
/* belongs in i915_gem_gtt.h */
3415
static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3416
{
3417
	if (INTEL_GEN(dev_priv) < 6)
3418 3419
		intel_gtt_chipset_flush();
}
3420

3421
/* i915_gem_stolen.c */
3422 3423 3424
int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
				struct drm_mm_node *node, u64 size,
				unsigned alignment);
3425 3426 3427 3428
int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
					 struct drm_mm_node *node, u64 size,
					 unsigned alignment, u64 start,
					 u64 end);
3429 3430
void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
				 struct drm_mm_node *node);
3431 3432
int i915_gem_init_stolen(struct drm_device *dev);
void i915_gem_cleanup_stolen(struct drm_device *dev);
3433 3434
struct drm_i915_gem_object *
i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3435 3436 3437 3438 3439
struct drm_i915_gem_object *
i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
					       u32 stolen_offset,
					       u32 gtt_offset,
					       u32 size);
3440

3441 3442
/* i915_gem_shrinker.c */
unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3443
			      unsigned long target,
3444 3445 3446 3447
			      unsigned flags);
#define I915_SHRINK_PURGEABLE 0x1
#define I915_SHRINK_UNBOUND 0x2
#define I915_SHRINK_BOUND 0x4
3448
#define I915_SHRINK_ACTIVE 0x8
3449
#define I915_SHRINK_VMAPS 0x10
3450 3451
unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3452
void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3453 3454


3455
/* i915_gem_tiling.c */
3456
static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3457
{
3458
	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3459 3460 3461 3462 3463

	return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
		obj->tiling_mode != I915_TILING_NONE;
}

3464
/* i915_debugfs.c */
3465
#ifdef CONFIG_DEBUG_FS
3466 3467
int i915_debugfs_register(struct drm_i915_private *dev_priv);
void i915_debugfs_unregister(struct drm_i915_private *dev_priv);
J
Jani Nikula 已提交
3468
int i915_debugfs_connector_add(struct drm_connector *connector);
3469 3470
void intel_display_crc_init(struct drm_device *dev);
#else
3471 3472
static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
static inline void i915_debugfs_unregister(struct drm_i915_private *dev_priv) {}
3473 3474
static inline int i915_debugfs_connector_add(struct drm_connector *connector)
{ return 0; }
3475
static inline void intel_display_crc_init(struct drm_device *dev) {}
3476
#endif
3477 3478

/* i915_gpu_error.c */
3479 3480
__printf(2, 3)
void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3481 3482
int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
			    const struct i915_error_state_file_priv *error);
3483
int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3484
			      struct drm_i915_private *i915,
3485 3486 3487 3488 3489 3490
			      size_t count, loff_t pos);
static inline void i915_error_state_buf_release(
	struct drm_i915_error_state_buf *eb)
{
	kfree(eb->buf);
}
3491 3492
void i915_capture_error_state(struct drm_i915_private *dev_priv,
			      u32 engine_mask,
3493
			      const char *error_msg);
3494 3495 3496 3497 3498
void i915_error_state_get(struct drm_device *dev,
			  struct i915_error_state_file_priv *error_priv);
void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
void i915_destroy_error_state(struct drm_device *dev);

3499
void i915_get_extra_instdone(struct drm_i915_private *dev_priv, uint32_t *instdone);
3500
const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3501

3502
/* i915_cmd_parser.c */
3503
int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3504 3505 3506 3507 3508 3509 3510 3511 3512
int intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
bool intel_engine_needs_cmd_parser(struct intel_engine_cs *engine);
int intel_engine_cmd_parser(struct intel_engine_cs *engine,
			    struct drm_i915_gem_object *batch_obj,
			    struct drm_i915_gem_object *shadow_batch_obj,
			    u32 batch_start_offset,
			    u32 batch_len,
			    bool is_master);
3513

3514 3515 3516
/* i915_suspend.c */
extern int i915_save_state(struct drm_device *dev);
extern int i915_restore_state(struct drm_device *dev);
3517

B
Ben Widawsky 已提交
3518 3519 3520 3521
/* i915_sysfs.c */
void i915_setup_sysfs(struct drm_device *dev_priv);
void i915_teardown_sysfs(struct drm_device *dev_priv);

3522 3523 3524
/* intel_i2c.c */
extern int intel_setup_gmbus(struct drm_device *dev);
extern void intel_teardown_gmbus(struct drm_device *dev);
3525 3526
extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
				     unsigned int pin);
3527

3528 3529
extern struct i2c_adapter *
intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
C
Chris Wilson 已提交
3530 3531
extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3532
static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3533 3534 3535
{
	return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
}
3536 3537
extern void intel_i2c_reset(struct drm_device *dev);

3538
/* intel_bios.c */
3539
int intel_bios_init(struct drm_i915_private *dev_priv);
J
Jani Nikula 已提交
3540
bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3541
bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3542
bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3543
bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3544
bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3545
bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3546
bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3547 3548
bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
				     enum port port);
3549

3550
/* intel_opregion.c */
3551
#ifdef CONFIG_ACPI
3552
extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3553 3554
extern void intel_opregion_register(struct drm_i915_private *dev_priv);
extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3555
extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3556 3557
extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
					 bool enable);
3558
extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3559
					 pci_power_t state);
3560
extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3561
#else
3562
static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3563 3564
static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
3565 3566 3567
static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
{
}
3568 3569 3570 3571 3572
static inline int
intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
{
	return 0;
}
3573
static inline int
3574
intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3575 3576 3577
{
	return 0;
}
3578
static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3579 3580 3581
{
	return -ENODEV;
}
3582
#endif
3583

J
Jesse Barnes 已提交
3584 3585 3586 3587 3588 3589 3590 3591 3592
/* intel_acpi.c */
#ifdef CONFIG_ACPI
extern void intel_register_dsm_handler(void);
extern void intel_unregister_dsm_handler(void);
#else
static inline void intel_register_dsm_handler(void) { return; }
static inline void intel_unregister_dsm_handler(void) { return; }
#endif /* CONFIG_ACPI */

3593 3594 3595 3596 3597 3598 3599 3600 3601 3602
/* intel_device_info.c */
static inline struct intel_device_info *
mkwrite_device_info(struct drm_i915_private *dev_priv)
{
	return (struct intel_device_info *)&dev_priv->info;
}

void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
void intel_device_info_dump(struct drm_i915_private *dev_priv);

J
Jesse Barnes 已提交
3603
/* modesetting */
3604
extern void intel_modeset_init_hw(struct drm_device *dev);
J
Jesse Barnes 已提交
3605
extern void intel_modeset_init(struct drm_device *dev);
3606
extern void intel_modeset_gem_init(struct drm_device *dev);
J
Jesse Barnes 已提交
3607
extern void intel_modeset_cleanup(struct drm_device *dev);
3608
extern int intel_connector_register(struct drm_connector *);
3609
extern void intel_connector_unregister(struct drm_connector *);
3610
extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3611
extern void intel_display_resume(struct drm_device *dev);
3612
extern void i915_redisable_vga(struct drm_device *dev);
3613
extern void i915_redisable_vga_power_on(struct drm_device *dev);
3614
extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
P
Paulo Zanoni 已提交
3615
extern void intel_init_pch_refclk(struct drm_device *dev);
3616
extern void intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3617 3618
extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
				  bool enable);
3619

B
Ben Widawsky 已提交
3620 3621
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file);
3622

3623
/* overlay */
3624 3625
extern struct intel_overlay_error_state *
intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3626 3627
extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
					    struct intel_overlay_error_state *error);
3628

3629 3630
extern struct intel_display_error_state *
intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3631
extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3632 3633
					    struct drm_device *dev,
					    struct intel_display_error_state *error);
3634

3635 3636
int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3637 3638

/* intel_sideband.c */
3639 3640
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3641
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3642 3643
u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3644 3645 3646 3647
u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3648 3649
u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3650 3651
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3652 3653 3654 3655
u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
		   enum intel_sbi_destination destination);
void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
		     enum intel_sbi_destination destination);
3656 3657
u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3658

3659 3660 3661 3662
/* intel_dpio_phy.c */
void chv_set_phy_signal_level(struct intel_encoder *encoder,
			      u32 deemph_reg_value, u32 margin_reg_value,
			      bool uniq_trans_scale);
3663 3664
void chv_data_lane_soft_reset(struct intel_encoder *encoder,
			      bool reset);
3665
void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3666 3667
void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3668
void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3669

3670 3671 3672
void vlv_set_phy_signal_level(struct intel_encoder *encoder,
			      u32 demph_reg_value, u32 preemph_reg_value,
			      u32 uniqtranscale_reg_value, u32 tx3_demph);
3673
void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3674
void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3675
void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3676

3677 3678
int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3679

3680 3681 3682 3683 3684 3685 3686 3687 3688 3689 3690 3691 3692
#define I915_READ8(reg)		dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
#define I915_WRITE8(reg, val)	dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)

#define I915_READ16(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
#define I915_WRITE16(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
#define I915_READ16_NOTRACE(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
#define I915_WRITE16_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)

#define I915_READ(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
#define I915_WRITE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
#define I915_READ_NOTRACE(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
#define I915_WRITE_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)

3693 3694 3695 3696 3697 3698
/* Be very careful with read/write 64-bit values. On 32-bit machines, they
 * will be implemented using 2 32-bit writes in an arbitrary order with
 * an arbitrary delay between them. This can cause the hardware to
 * act upon the intermediate value, possibly leading to corruption and
 * machine death. You have been warned.
 */
3699 3700
#define I915_WRITE64(reg, val)	dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
#define I915_READ64(reg)	dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3701

3702
#define I915_READ64_2x32(lower_reg, upper_reg) ({			\
3703 3704
	u32 upper, lower, old_upper, loop = 0;				\
	upper = I915_READ(upper_reg);					\
3705
	do {								\
3706
		old_upper = upper;					\
3707
		lower = I915_READ(lower_reg);				\
3708 3709
		upper = I915_READ(upper_reg);				\
	} while (upper != old_upper && loop++ < 2);			\
3710
	(u64)upper << 32 | lower; })
3711

3712 3713 3714
#define POSTING_READ(reg)	(void)I915_READ_NOTRACE(reg)
#define POSTING_READ16(reg)	(void)I915_READ16_NOTRACE(reg)

3715 3716
#define __raw_read(x, s) \
static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3717
					     i915_reg_t reg) \
3718
{ \
3719
	return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3720 3721 3722 3723
}

#define __raw_write(x, s) \
static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3724
				       i915_reg_t reg, uint##x##_t val) \
3725
{ \
3726
	write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3727 3728 3729 3730 3731 3732 3733 3734 3735 3736 3737 3738 3739 3740
}
__raw_read(8, b)
__raw_read(16, w)
__raw_read(32, l)
__raw_read(64, q)

__raw_write(8, b)
__raw_write(16, w)
__raw_write(32, l)
__raw_write(64, q)

#undef __raw_read
#undef __raw_write

3741 3742 3743 3744 3745 3746 3747
/* These are untraced mmio-accessors that are only valid to be used inside
 * criticial sections inside IRQ handlers where forcewake is explicitly
 * controlled.
 * Think twice, and think again, before using these.
 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
 * intel_uncore_forcewake_irqunlock().
 */
3748 3749
#define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3750
#define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3751 3752
#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)

3753 3754 3755 3756
/* "Broadcast RGB" property */
#define INTEL_BROADCAST_RGB_AUTO 0
#define INTEL_BROADCAST_RGB_FULL 1
#define INTEL_BROADCAST_RGB_LIMITED 2
3757

3758
static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
3759
{
3760
	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
3761
		return VLV_VGACNTRL;
3762 3763
	else if (INTEL_INFO(dev)->gen >= 5)
		return CPU_VGACNTRL;
3764 3765 3766 3767
	else
		return VGACNTRL;
}

3768 3769 3770 3771 3772 3773 3774
static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
{
	unsigned long j = msecs_to_jiffies(m);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

3775 3776 3777 3778 3779
static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
{
        return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
}

3780 3781 3782 3783 3784 3785 3786 3787
static inline unsigned long
timespec_to_jiffies_timeout(const struct timespec *value)
{
	unsigned long j = timespec_to_jiffies(value);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

3788 3789 3790 3791 3792 3793 3794 3795 3796
/*
 * If you need to wait X milliseconds between events A and B, but event B
 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
 * when event A happened, then just before event B you call this function and
 * pass the timestamp as the first argument, and X as the second argument.
 */
static inline void
wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
{
3797
	unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3798 3799 3800 3801 3802 3803 3804 3805 3806 3807

	/*
	 * Don't re-read the value of "jiffies" every time since it may change
	 * behind our back and break the math.
	 */
	tmp_jiffies = jiffies;
	target_jiffies = timestamp_jiffies +
			 msecs_to_jiffies_timeout(to_wait_ms);

	if (time_after(target_jiffies, tmp_jiffies)) {
3808 3809 3810 3811
		remaining_jiffies = target_jiffies - tmp_jiffies;
		while (remaining_jiffies)
			remaining_jiffies =
			    schedule_timeout_uninterruptible(remaining_jiffies);
3812 3813
	}
}
3814 3815
static inline bool __i915_request_irq_complete(struct drm_i915_gem_request *req)
{
3816 3817
	struct intel_engine_cs *engine = req->engine;

3818 3819 3820 3821 3822 3823
	/* Before we do the heavier coherent read of the seqno,
	 * check the value (hopefully) in the CPU cacheline.
	 */
	if (i915_gem_request_completed(req))
		return true;

3824 3825 3826 3827 3828 3829 3830 3831 3832 3833 3834
	/* Ensure our read of the seqno is coherent so that we
	 * do not "miss an interrupt" (i.e. if this is the last
	 * request and the seqno write from the GPU is not visible
	 * by the time the interrupt fires, we will see that the
	 * request is incomplete and go back to sleep awaiting
	 * another interrupt that will never come.)
	 *
	 * Strictly, we only need to do this once after an interrupt,
	 * but it is easier and safer to do it every time the waiter
	 * is woken.
	 */
3835
	if (engine->irq_seqno_barrier &&
3836 3837
	    READ_ONCE(engine->breadcrumbs.irq_seqno_bh) == current &&
	    cmpxchg_relaxed(&engine->breadcrumbs.irq_posted, 1, 0)) {
3838 3839
		struct task_struct *tsk;

3840 3841 3842 3843 3844 3845 3846 3847 3848 3849 3850 3851
		/* The ordering of irq_posted versus applying the barrier
		 * is crucial. The clearing of the current irq_posted must
		 * be visible before we perform the barrier operation,
		 * such that if a subsequent interrupt arrives, irq_posted
		 * is reasserted and our task rewoken (which causes us to
		 * do another __i915_request_irq_complete() immediately
		 * and reapply the barrier). Conversely, if the clear
		 * occurs after the barrier, then an interrupt that arrived
		 * whilst we waited on the barrier would not trigger a
		 * barrier on the next pass, and the read may not see the
		 * seqno update.
		 */
3852
		engine->irq_seqno_barrier(engine);
3853 3854 3855 3856 3857 3858 3859 3860

		/* If we consume the irq, but we are no longer the bottom-half,
		 * the real bottom-half may not have serialised their own
		 * seqno check with the irq-barrier (i.e. may have inspected
		 * the seqno before we believe it coherent since they see
		 * irq_posted == false but we are still running).
		 */
		rcu_read_lock();
3861
		tsk = READ_ONCE(engine->breadcrumbs.irq_seqno_bh);
3862 3863 3864 3865 3866 3867 3868 3869 3870 3871
		if (tsk && tsk != current)
			/* Note that if the bottom-half is changed as we
			 * are sending the wake-up, the new bottom-half will
			 * be woken by whomever made the change. We only have
			 * to worry about when we steal the irq-posted for
			 * ourself.
			 */
			wake_up_process(tsk);
		rcu_read_unlock();

3872 3873 3874
		if (i915_gem_request_completed(req))
			return true;
	}
3875 3876 3877 3878 3879 3880 3881 3882 3883 3884 3885 3886 3887 3888 3889

	/* We need to check whether any gpu reset happened in between
	 * the request being submitted and now. If a reset has occurred,
	 * the seqno will have been advance past ours and our request
	 * is complete. If we are in the process of handling a reset,
	 * the request is effectively complete as the rendering will
	 * be discarded, but we need to return in order to drop the
	 * struct_mutex.
	 */
	if (i915_reset_in_progress(&req->i915->gpu_error))
		return true;

	return false;
}

L
Linus Torvalds 已提交
3890
#endif