hw.c 95.0 KB
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/*
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 * Copyright (c) 2008-2009 Atheros Communications Inc.
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 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <linux/io.h>
#include <asm/unaligned.h>

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#include "hw.h"
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#include "hw-ops.h"
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#include "rc.h"
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#include "initvals.h"

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#define ATH9K_CLOCK_RATE_CCK		22
#define ATH9K_CLOCK_RATE_5GHZ_OFDM	40
#define ATH9K_CLOCK_RATE_2GHZ_OFDM	44
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static void ar9002_hw_attach_ops(struct ath_hw *ah);
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static void ar9003_hw_attach_ops(struct ath_hw *ah);
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static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
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MODULE_AUTHOR("Atheros Communications");
MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
MODULE_LICENSE("Dual BSD/GPL");

static int __init ath9k_init(void)
{
	return 0;
}
module_init(ath9k_init);

static void __exit ath9k_exit(void)
{
	return;
}
module_exit(ath9k_exit);

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/* Private hardware callbacks */

static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
{
	ath9k_hw_private_ops(ah)->init_cal_settings(ah);
}

static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
{
	ath9k_hw_private_ops(ah)->init_mode_regs(ah);
}

static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
{
	struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);

	return priv_ops->macversion_supported(ah->hw_version.macVersion);
}

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static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
					struct ath9k_channel *chan)
{
	return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
}

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/********************/
/* Helper Functions */
/********************/
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static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
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{
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	struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
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	if (!ah->curchan) /* should really check for CCK instead */
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		return usecs *ATH9K_CLOCK_RATE_CCK;
	if (conf->channel->band == IEEE80211_BAND_2GHZ)
		return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
	return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
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}

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static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
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{
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	struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
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	if (conf_is_ht40(conf))
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		return ath9k_hw_mac_clks(ah, usecs) * 2;
	else
		return ath9k_hw_mac_clks(ah, usecs);
}
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bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
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{
	int i;

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	BUG_ON(timeout < AH_TIME_QUANTUM);

	for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
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		if ((REG_READ(ah, reg) & mask) == val)
			return true;

		udelay(AH_TIME_QUANTUM);
	}
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	ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
		  "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
		  timeout, reg, REG_READ(ah, reg), mask, val);
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	return false;
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}
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EXPORT_SYMBOL(ath9k_hw_wait);
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u32 ath9k_hw_reverse_bits(u32 val, u32 n)
{
	u32 retval;
	int i;

	for (i = 0, retval = 0; i < n; i++) {
		retval = (retval << 1) | (val & 1);
		val >>= 1;
	}
	return retval;
}

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bool ath9k_get_channel_edges(struct ath_hw *ah,
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			     u16 flags, u16 *low,
			     u16 *high)
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{
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	struct ath9k_hw_capabilities *pCap = &ah->caps;
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	if (flags & CHANNEL_5GHZ) {
		*low = pCap->low_5ghz_chan;
		*high = pCap->high_5ghz_chan;
		return true;
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	}
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	if ((flags & CHANNEL_2GHZ)) {
		*low = pCap->low_2ghz_chan;
		*high = pCap->high_2ghz_chan;
		return true;
	}
	return false;
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}

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u16 ath9k_hw_computetxtime(struct ath_hw *ah,
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			   u8 phy, int kbps,
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			   u32 frameLen, u16 rateix,
			   bool shortPreamble)
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{
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	u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
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	if (kbps == 0)
		return 0;
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	switch (phy) {
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	case WLAN_RC_PHY_CCK:
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		phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
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		if (shortPreamble)
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			phyTime >>= 1;
		numBits = frameLen << 3;
		txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
		break;
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	case WLAN_RC_PHY_OFDM:
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		if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
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			bitsPerSymbol =	(kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
			numBits = OFDM_PLCP_BITS + (frameLen << 3);
			numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
			txTime = OFDM_SIFS_TIME_QUARTER
				+ OFDM_PREAMBLE_TIME_QUARTER
				+ (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
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		} else if (ah->curchan &&
			   IS_CHAN_HALF_RATE(ah->curchan)) {
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			bitsPerSymbol =	(kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
			numBits = OFDM_PLCP_BITS + (frameLen << 3);
			numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
			txTime = OFDM_SIFS_TIME_HALF +
				OFDM_PREAMBLE_TIME_HALF
				+ (numSymbols * OFDM_SYMBOL_TIME_HALF);
		} else {
			bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
			numBits = OFDM_PLCP_BITS + (frameLen << 3);
			numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
			txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
				+ (numSymbols * OFDM_SYMBOL_TIME);
		}
		break;
	default:
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		ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
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			  "Unknown phy %u (rate ix %u)\n", phy, rateix);
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		txTime = 0;
		break;
	}
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	return txTime;
}
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EXPORT_SYMBOL(ath9k_hw_computetxtime);
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void ath9k_hw_get_channel_centers(struct ath_hw *ah,
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				  struct ath9k_channel *chan,
				  struct chan_centers *centers)
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{
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	int8_t extoff;
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	if (!IS_CHAN_HT40(chan)) {
		centers->ctl_center = centers->ext_center =
			centers->synth_center = chan->channel;
		return;
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	}

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	if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
	    (chan->chanmode == CHANNEL_G_HT40PLUS)) {
		centers->synth_center =
			chan->channel + HT40_CHANNEL_CENTER_SHIFT;
		extoff = 1;
	} else {
		centers->synth_center =
			chan->channel - HT40_CHANNEL_CENTER_SHIFT;
		extoff = -1;
	}
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	centers->ctl_center =
		centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
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	/* 25 MHz spacing is supported by hw but not on upper layers */
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	centers->ext_center =
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		centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
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}

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/******************/
/* Chip Revisions */
/******************/

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static void ath9k_hw_read_revisions(struct ath_hw *ah)
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{
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	u32 val;
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	val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
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	if (val == 0xFF) {
		val = REG_READ(ah, AR_SREV);
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		ah->hw_version.macVersion =
			(val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
		ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
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		ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
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	} else {
		if (!AR_SREV_9100(ah))
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			ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
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		ah->hw_version.macRev = val & AR_SREV_REVISION;
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		if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
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			ah->is_pciexpress = true;
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	}
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}

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static int ath9k_hw_get_radiorev(struct ath_hw *ah)
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{
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	u32 val;
	int i;
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	REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
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	for (i = 0; i < 8; i++)
		REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
	val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
	val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
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	return ath9k_hw_reverse_bits(val, 8);
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}

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/************************************/
/* HW Attach, Detach, Init Routines */
/************************************/

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static void ath9k_hw_disablepcie(struct ath_hw *ah)
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{
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	if (AR_SREV_9100(ah))
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		return;
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	REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
	REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
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	REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
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}

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/* This should work for all families including legacy */
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static bool ath9k_hw_chip_test(struct ath_hw *ah)
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{
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	struct ath_common *common = ath9k_hw_common(ah);
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	u32 regAddr[2] = { AR_STA_ID0 };
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	u32 regHold[2];
	u32 patternData[4] = { 0x55555555,
			       0xaaaaaaaa,
			       0x66666666,
			       0x99999999 };
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	int i, j, loop_max;
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	if (!AR_SREV_9300_20_OR_LATER(ah)) {
		loop_max = 2;
		regAddr[1] = AR_PHY_BASE + (8 << 2);
	} else
		loop_max = 1;

	for (i = 0; i < loop_max; i++) {
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		u32 addr = regAddr[i];
		u32 wrData, rdData;
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		regHold[i] = REG_READ(ah, addr);
		for (j = 0; j < 0x100; j++) {
			wrData = (j << 16) | j;
			REG_WRITE(ah, addr, wrData);
			rdData = REG_READ(ah, addr);
			if (rdData != wrData) {
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				ath_print(common, ATH_DBG_FATAL,
					  "address test failed "
					  "addr: 0x%08x - wr:0x%08x != "
					  "rd:0x%08x\n",
					  addr, wrData, rdData);
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				return false;
			}
		}
		for (j = 0; j < 4; j++) {
			wrData = patternData[j];
			REG_WRITE(ah, addr, wrData);
			rdData = REG_READ(ah, addr);
			if (wrData != rdData) {
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				ath_print(common, ATH_DBG_FATAL,
					  "address test failed "
					  "addr: 0x%08x - wr:0x%08x != "
					  "rd:0x%08x\n",
					  addr, wrData, rdData);
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				return false;
			}
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		}
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		REG_WRITE(ah, regAddr[i], regHold[i]);
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	}
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	udelay(100);
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	return true;
}

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static void ath9k_hw_init_config(struct ath_hw *ah)
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{
	int i;
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	ah->config.dma_beacon_response_time = 2;
	ah->config.sw_beacon_response_time = 10;
	ah->config.additional_swba_backoff = 0;
	ah->config.ack_6mb = 0x0;
	ah->config.cwm_ignore_extcca = 0;
	ah->config.pcie_powersave_enable = 0;
	ah->config.pcie_clock_req = 0;
	ah->config.pcie_waen = 0;
	ah->config.analog_shiftreg = 1;
	ah->config.ofdm_trig_low = 200;
	ah->config.ofdm_trig_high = 500;
	ah->config.cck_trig_high = 200;
	ah->config.cck_trig_low = 100;
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	/*
	 * For now ANI is disabled for AR9003, it is still
	 * being tested.
	 */
	if (!AR_SREV_9300_20_OR_LATER(ah))
		ah->config.enable_ani = 1;
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	for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
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		ah->config.spurchans[i][0] = AR_NO_SPUR;
		ah->config.spurchans[i][1] = AR_NO_SPUR;
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	}

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	if (ah->hw_version.devid != AR2427_DEVID_PCIE)
		ah->config.ht_enable = 1;
	else
		ah->config.ht_enable = 0;

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	ah->config.rx_intr_mitigation = true;
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	/*
	 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
	 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
	 * This means we use it for all AR5416 devices, and the few
	 * minor PCI AR9280 devices out there.
	 *
	 * Serialization is required because these devices do not handle
	 * well the case of two concurrent reads/writes due to the latency
	 * involved. During one read/write another read/write can be issued
	 * on another CPU while the previous read/write may still be working
	 * on our hardware, if we hit this case the hardware poops in a loop.
	 * We prevent this by serializing reads and writes.
	 *
	 * This issue is not present on PCI-Express devices or pre-AR5416
	 * devices (legacy, 802.11abg).
	 */
	if (num_possible_cpus() > 1)
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		ah->config.serialize_regmode = SER_REG_MODE_AUTO;
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}

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static void ath9k_hw_init_defaults(struct ath_hw *ah)
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{
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	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);

	regulatory->country_code = CTRY_DEFAULT;
	regulatory->power_limit = MAX_RATE_POWER;
	regulatory->tp_scale = ATH9K_TP_SCALE_MAX;

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	ah->hw_version.magic = AR5416_MAGIC;
	ah->hw_version.subvendorid = 0;
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	ah->ah_flags = 0;
	if (!AR_SREV_9100(ah))
		ah->ah_flags = AH_USE_EEPROM;

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	ah->atim_window = 0;
	ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
	ah->beacon_interval = 100;
	ah->enable_32kHz_clock = DONT_USE_32KHZ;
	ah->slottime = (u32) -1;
	ah->globaltxtimeout = (u32) -1;
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	ah->power_mode = ATH9K_PM_UNDEFINED;
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}

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static int ath9k_hw_rf_claim(struct ath_hw *ah)
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{
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	u32 val;

	REG_WRITE(ah, AR_PHY(0), 0x00000007);

	val = ath9k_hw_get_radiorev(ah);
	switch (val & AR_RADIO_SREV_MAJOR) {
	case 0:
		val = AR_RAD5133_SREV_MAJOR;
		break;
	case AR_RAD5133_SREV_MAJOR:
	case AR_RAD5122_SREV_MAJOR:
	case AR_RAD2133_SREV_MAJOR:
	case AR_RAD2122_SREV_MAJOR:
		break;
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	default:
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		ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
			  "Radio Chip Rev 0x%02X not supported\n",
			  val & AR_RADIO_SREV_MAJOR);
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		return -EOPNOTSUPP;
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	}

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	ah->hw_version.analog5GhzRev = val;
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	return 0;
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}

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static int ath9k_hw_init_macaddr(struct ath_hw *ah)
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{
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	struct ath_common *common = ath9k_hw_common(ah);
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	u32 sum;
	int i;
	u16 eeval;

	sum = 0;
	for (i = 0; i < 3; i++) {
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		eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
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		sum += eeval;
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		common->macaddr[2 * i] = eeval >> 8;
		common->macaddr[2 * i + 1] = eeval & 0xff;
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	}
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	if (sum == 0 || sum == 0xffff * 3)
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		return -EADDRNOTAVAIL;

	return 0;
}

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static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
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{
	u32 rxgain_type;

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	if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
		rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
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		if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
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			INIT_INI_ARRAY(&ah->iniModesRxGain,
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			ar9280Modes_backoff_13db_rxgain_9280_2,
			ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
		else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
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			INIT_INI_ARRAY(&ah->iniModesRxGain,
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			ar9280Modes_backoff_23db_rxgain_9280_2,
			ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
		else
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			INIT_INI_ARRAY(&ah->iniModesRxGain,
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			ar9280Modes_original_rxgain_9280_2,
			ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
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	} else {
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		INIT_INI_ARRAY(&ah->iniModesRxGain,
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			ar9280Modes_original_rxgain_9280_2,
			ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
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	}
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}

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static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
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{
	u32 txgain_type;

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	if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
		txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
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		if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
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			INIT_INI_ARRAY(&ah->iniModesTxGain,
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			ar9280Modes_high_power_tx_gain_9280_2,
			ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
		else
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			INIT_INI_ARRAY(&ah->iniModesTxGain,
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			ar9280Modes_original_tx_gain_9280_2,
			ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
526
	} else {
527
		INIT_INI_ARRAY(&ah->iniModesTxGain,
528 529
		ar9280Modes_original_tx_gain_9280_2,
		ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
530
	}
531 532
}

533
static int ath9k_hw_post_init(struct ath_hw *ah)
534
{
S
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535
	int ecode;
536

S
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537 538 539 540
	if (!AR_SREV_9271(ah)) {
		if (!ath9k_hw_chip_test(ah))
			return -ENODEV;
	}
541

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542 543
	ecode = ath9k_hw_rf_claim(ah);
	if (ecode != 0)
544 545
		return ecode;

546
	ecode = ath9k_hw_eeprom_init(ah);
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547 548
	if (ecode != 0)
		return ecode;
549

550 551 552 553
	ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
		  "Eeprom VER: %d, REV: %d\n",
		  ah->eep_ops->get_eeprom_ver(ah),
		  ah->eep_ops->get_eeprom_rev(ah));
554

555 556 557 558 559 560
	ecode = ath9k_hw_rf_alloc_ext_banks(ah);
	if (ecode) {
		ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
			  "Failed allocating banks for "
			  "external radio\n");
		return ecode;
561
	}
562

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563 564
	if (!AR_SREV_9100(ah)) {
		ath9k_hw_ani_setup(ah);
565
		ath9k_hw_ani_init(ah);
566 567 568 569 570
	}

	return 0;
}

571
static bool ar9002_hw_macversion_supported(u32 macversion)
572 573 574 575 576 577 578 579 580
{
	switch (macversion) {
	case AR_SREV_VERSION_5416_PCI:
	case AR_SREV_VERSION_5416_PCIE:
	case AR_SREV_VERSION_9160:
	case AR_SREV_VERSION_9100:
	case AR_SREV_VERSION_9280:
	case AR_SREV_VERSION_9285:
	case AR_SREV_VERSION_9287:
581
	case AR_SREV_VERSION_9271:
582
		return true;
583 584 585 586 587 588
	default:
		break;
	}
	return false;
}

589 590 591 592 593 594 595 596 597 598 599
static bool ar9003_hw_macversion_supported(u32 macversion)
{
	switch (macversion) {
	case AR_SREV_VERSION_9300:
		return true;
	default:
		break;
	}
	return false;
}

600
static void ar9002_hw_init_cal_settings(struct ath_hw *ah)
601
{
S
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602 603
	if (AR_SREV_9160_10_OR_LATER(ah)) {
		if (AR_SREV_9280_10_OR_LATER(ah)) {
604 605
			ah->iq_caldata.calData = &iq_cal_single_sample;
			ah->adcgain_caldata.calData =
S
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606
				&adc_gain_cal_single_sample;
607
			ah->adcdc_caldata.calData =
S
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608
				&adc_dc_cal_single_sample;
609
			ah->adcdc_calinitdata.calData =
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610 611
				&adc_init_dc_cal;
		} else {
612 613
			ah->iq_caldata.calData = &iq_cal_multi_sample;
			ah->adcgain_caldata.calData =
S
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614
				&adc_gain_cal_multi_sample;
615
			ah->adcdc_caldata.calData =
S
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616
				&adc_dc_cal_multi_sample;
617
			ah->adcdc_calinitdata.calData =
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618 619
				&adc_init_dc_cal;
		}
620
		ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
S
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621
	}
622
}
623

624
static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
625
{
626
	if (AR_SREV_9271(ah)) {
627 628 629 630
		INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
			       ARRAY_SIZE(ar9271Modes_9271), 6);
		INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
			       ARRAY_SIZE(ar9271Common_9271), 2);
631 632 633 634 635 636
		INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271,
			       ar9271Common_normal_cck_fir_coeff_9271,
			       ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2);
		INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271,
			       ar9271Common_japan_2484_cck_fir_coeff_9271,
			       ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2);
637 638 639
		INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
			       ar9271Modes_9271_1_0_only,
			       ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
640 641 642 643 644 645 646 647
		INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
			       ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6);
		INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
			       ar9271Modes_high_power_tx_gain_9271,
			       ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6);
		INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
			       ar9271Modes_normal_power_tx_gain_9271,
			       ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6);
648 649 650
		return;
	}

651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680
	if (AR_SREV_9287_11_OR_LATER(ah)) {
		INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
				ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
		INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
				ARRAY_SIZE(ar9287Common_9287_1_1), 2);
		if (ah->config.pcie_clock_req)
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
			ar9287PciePhy_clkreq_off_L1_9287_1_1,
			ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
		else
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
			ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
			ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
					2);
	} else if (AR_SREV_9287_10_OR_LATER(ah)) {
		INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
				ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
		INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
				ARRAY_SIZE(ar9287Common_9287_1_0), 2);

		if (ah->config.pcie_clock_req)
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
			ar9287PciePhy_clkreq_off_L1_9287_1_0,
			ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
		else
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
			ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
			ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
				  2);
	} else if (AR_SREV_9285_12_OR_LATER(ah)) {
681

682

683
		INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
684
			       ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
685
		INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
686 687
			       ARRAY_SIZE(ar9285Common_9285_1_2), 2);

688 689
		if (ah->config.pcie_clock_req) {
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
690 691 692
			ar9285PciePhy_clkreq_off_L1_9285_1_2,
			ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
		} else {
693
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
694 695 696 697 698
			ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
			ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
				  2);
		}
	} else if (AR_SREV_9285_10_OR_LATER(ah)) {
699
		INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
700
			       ARRAY_SIZE(ar9285Modes_9285), 6);
701
		INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
702 703
			       ARRAY_SIZE(ar9285Common_9285), 2);

704 705
		if (ah->config.pcie_clock_req) {
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
706 707 708
			ar9285PciePhy_clkreq_off_L1_9285,
			ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
		} else {
709
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
710 711 712 713
			ar9285PciePhy_clkreq_always_on_L1_9285,
			ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
		}
	} else if (AR_SREV_9280_20_OR_LATER(ah)) {
714
		INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
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715
			       ARRAY_SIZE(ar9280Modes_9280_2), 6);
716
		INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
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717
			       ARRAY_SIZE(ar9280Common_9280_2), 2);
718

719 720
		if (ah->config.pcie_clock_req) {
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
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721 722 723
			       ar9280PciePhy_clkreq_off_L1_9280,
			       ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
		} else {
724
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
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725 726 727
			       ar9280PciePhy_clkreq_always_on_L1_9280,
			       ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
		}
728
		INIT_INI_ARRAY(&ah->iniModesAdditional,
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729 730 731
			       ar9280Modes_fast_clock_9280_2,
			       ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
	} else if (AR_SREV_9280_10_OR_LATER(ah)) {
732
		INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
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733
			       ARRAY_SIZE(ar9280Modes_9280), 6);
734
		INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
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735 736
			       ARRAY_SIZE(ar9280Common_9280), 2);
	} else if (AR_SREV_9160_10_OR_LATER(ah)) {
737
		INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
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738
			       ARRAY_SIZE(ar5416Modes_9160), 6);
739
		INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
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740
			       ARRAY_SIZE(ar5416Common_9160), 2);
741
		INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
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742
			       ARRAY_SIZE(ar5416Bank0_9160), 2);
743
		INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
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744
			       ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
745
		INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
S
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746
			       ARRAY_SIZE(ar5416Bank1_9160), 2);
747
		INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
S
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748
			       ARRAY_SIZE(ar5416Bank2_9160), 2);
749
		INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
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750
			       ARRAY_SIZE(ar5416Bank3_9160), 3);
751
		INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
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752
			       ARRAY_SIZE(ar5416Bank6_9160), 3);
753
		INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
S
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754
			       ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
755
		INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
S
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756 757
			       ARRAY_SIZE(ar5416Bank7_9160), 2);
		if (AR_SREV_9160_11(ah)) {
758
			INIT_INI_ARRAY(&ah->iniAddac,
S
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759 760 761
				       ar5416Addac_91601_1,
				       ARRAY_SIZE(ar5416Addac_91601_1), 2);
		} else {
762
			INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
S
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763 764 765
				       ARRAY_SIZE(ar5416Addac_9160), 2);
		}
	} else if (AR_SREV_9100_OR_LATER(ah)) {
766
		INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
S
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767
			       ARRAY_SIZE(ar5416Modes_9100), 6);
768
		INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
S
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769
			       ARRAY_SIZE(ar5416Common_9100), 2);
770
		INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
S
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771
			       ARRAY_SIZE(ar5416Bank0_9100), 2);
772
		INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
S
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773
			       ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
774
		INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
S
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775
			       ARRAY_SIZE(ar5416Bank1_9100), 2);
776
		INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
S
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777
			       ARRAY_SIZE(ar5416Bank2_9100), 2);
778
		INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
S
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779
			       ARRAY_SIZE(ar5416Bank3_9100), 3);
780
		INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
S
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781
			       ARRAY_SIZE(ar5416Bank6_9100), 3);
782
		INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
S
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783
			       ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
784
		INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
S
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785
			       ARRAY_SIZE(ar5416Bank7_9100), 2);
786
		INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
S
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787 788
			       ARRAY_SIZE(ar5416Addac_9100), 2);
	} else {
789
		INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
S
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790
			       ARRAY_SIZE(ar5416Modes), 6);
791
		INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
S
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792
			       ARRAY_SIZE(ar5416Common), 2);
793
		INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
S
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794
			       ARRAY_SIZE(ar5416Bank0), 2);
795
		INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
S
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796
			       ARRAY_SIZE(ar5416BB_RfGain), 3);
797
		INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
S
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798
			       ARRAY_SIZE(ar5416Bank1), 2);
799
		INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
S
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800
			       ARRAY_SIZE(ar5416Bank2), 2);
801
		INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
S
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802
			       ARRAY_SIZE(ar5416Bank3), 3);
803
		INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
S
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804
			       ARRAY_SIZE(ar5416Bank6), 3);
805
		INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
S
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806
			       ARRAY_SIZE(ar5416Bank6TPC), 3);
807
		INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
S
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808
			       ARRAY_SIZE(ar5416Bank7), 2);
809
		INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
S
Sujith 已提交
810
			       ARRAY_SIZE(ar5416Addac), 2);
811
	}
812
}
813

814 815
static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
{
816
	if (AR_SREV_9287_11_OR_LATER(ah))
817 818 819 820 821 822 823 824 825 826
		INIT_INI_ARRAY(&ah->iniModesRxGain,
		ar9287Modes_rx_gain_9287_1_1,
		ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
	else if (AR_SREV_9287_10(ah))
		INIT_INI_ARRAY(&ah->iniModesRxGain,
		ar9287Modes_rx_gain_9287_1_0,
		ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
	else if (AR_SREV_9280_20(ah))
		ath9k_hw_init_rxgain_ini(ah);

827
	if (AR_SREV_9287_11_OR_LATER(ah)) {
828 829 830 831 832 833 834 835 836 837
		INIT_INI_ARRAY(&ah->iniModesTxGain,
		ar9287Modes_tx_gain_9287_1_1,
		ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
	} else if (AR_SREV_9287_10(ah)) {
		INIT_INI_ARRAY(&ah->iniModesTxGain,
		ar9287Modes_tx_gain_9287_1_0,
		ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
	} else if (AR_SREV_9280_20(ah)) {
		ath9k_hw_init_txgain_ini(ah);
	} else if (AR_SREV_9285_12_OR_LATER(ah)) {
838 839 840 841
		u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);

		/* txgain table */
		if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
842 843 844 845 846 847 848 849 850 851 852
			if (AR_SREV_9285E_20(ah)) {
				INIT_INI_ARRAY(&ah->iniModesTxGain,
				ar9285Modes_XE2_0_high_power,
				ARRAY_SIZE(
				  ar9285Modes_XE2_0_high_power), 6);
			} else {
				INIT_INI_ARRAY(&ah->iniModesTxGain,
				ar9285Modes_high_power_tx_gain_9285_1_2,
				ARRAY_SIZE(
				  ar9285Modes_high_power_tx_gain_9285_1_2), 6);
			}
853
		} else {
854 855 856 857 858 859 860 861 862 863 864
			if (AR_SREV_9285E_20(ah)) {
				INIT_INI_ARRAY(&ah->iniModesTxGain,
				ar9285Modes_XE2_0_normal_power,
				ARRAY_SIZE(
				  ar9285Modes_XE2_0_normal_power), 6);
			} else {
				INIT_INI_ARRAY(&ah->iniModesTxGain,
				ar9285Modes_original_tx_gain_9285_1_2,
				ARRAY_SIZE(
				  ar9285Modes_original_tx_gain_9285_1_2), 6);
			}
865 866
		}
	}
867
}
868

869
static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah)
870
{
871 872
	struct base_eep_header *pBase = &(ah->eeprom.def.baseEepHeader);
	struct ath_common *common = ath9k_hw_common(ah);
873

874 875 876 877
	ah->need_an_top2_fixup = (ah->hw_version.devid == AR9280_DEVID_PCI) &&
				 (ah->eep_map != EEP_MAP_4KBITS) &&
				 ((pBase->version & 0xff) > 0x0a) &&
				 (pBase->pwdclkind == 0);
878

879 880 881
	if (ah->need_an_top2_fixup)
		ath_print(common, ATH_DBG_EEPROM,
			  "needs fixup for AR_AN_TOP2 register\n");
882 883
}

884 885 886 887 888 889 890 891
static void ath9k_hw_attach_ops(struct ath_hw *ah)
{
	if (AR_SREV_9300_20_OR_LATER(ah))
		ar9003_hw_attach_ops(ah);
	else
		ar9002_hw_attach_ops(ah);
}

892 893
/* Called for all hardware families */
static int __ath9k_hw_init(struct ath_hw *ah)
894
{
895
	struct ath_common *common = ath9k_hw_common(ah);
896
	int r = 0;
897

898 899
	if (ah->hw_version.devid == AR5416_AR9100_DEVID)
		ah->hw_version.macVersion = AR_SREV_VERSION_9100;
900 901

	if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
902 903
		ath_print(common, ATH_DBG_FATAL,
			  "Couldn't reset chip\n");
904
		return -EIO;
905 906
	}

907 908 909
	ath9k_hw_init_defaults(ah);
	ath9k_hw_init_config(ah);

910
	ath9k_hw_attach_ops(ah);
911

912
	if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
913
		ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
914
		return -EIO;
915 916 917 918 919 920 921 922 923 924 925 926 927
	}

	if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
		if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
		    (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
			ah->config.serialize_regmode =
				SER_REG_MODE_ON;
		} else {
			ah->config.serialize_regmode =
				SER_REG_MODE_OFF;
		}
	}

928
	ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
929 930
		ah->config.serialize_regmode);

931 932 933 934 935
	if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
		ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
	else
		ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;

936
	if (!ath9k_hw_macversion_supported(ah)) {
937 938 939 940
		ath_print(common, ATH_DBG_FATAL,
			  "Mac Chip Rev 0x%02x.%x is not supported by "
			  "this driver\n", ah->hw_version.macVersion,
			  ah->hw_version.macRev);
941
		return -EOPNOTSUPP;
942 943 944 945 946 947 948
	}

	if (AR_SREV_9100(ah)) {
		ah->iq_caldata.calData = &iq_cal_multi_sample;
		ah->supp_cals = IQ_MISMATCH_CAL;
		ah->is_pciexpress = false;
	}
949 950 951 952

	if (AR_SREV_9271(ah))
		ah->is_pciexpress = false;

953 954 955 956
	ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
	ath9k_hw_init_cal_settings(ah);

	ah->ani_function = ATH9K_ANI_ALL;
957
	if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
958 959 960 961 962
		ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;

	ath9k_hw_init_mode_regs(ah);

	if (ah->is_pciexpress)
V
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963
		ath9k_hw_configpcipowersave(ah, 0, 0);
964 965 966
	else
		ath9k_hw_disablepcie(ah);

S
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967 968 969 970 971 972 973 974 975 976
	/* Support for Japan ch.14 (2484) spread */
	if (AR_SREV_9287_11_OR_LATER(ah)) {
		INIT_INI_ARRAY(&ah->iniCckfirNormal,
		       ar9287Common_normal_cck_fir_coeff_92871_1,
		       ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
		INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
		       ar9287Common_japan_2484_cck_fir_coeff_92871_1,
		       ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
	}

977
	r = ath9k_hw_post_init(ah);
978
	if (r)
979
		return r;
980 981

	ath9k_hw_init_mode_gain_regs(ah);
982 983 984 985
	r = ath9k_hw_fill_cap_info(ah);
	if (r)
		return r;

986
	ath9k_hw_init_eeprom_fix(ah);
987

988 989
	r = ath9k_hw_init_macaddr(ah);
	if (r) {
990 991
		ath_print(common, ATH_DBG_FATAL,
			  "Failed to initialize MAC address\n");
992
		return r;
993 994
	}

995
	if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
996
		ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
S
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997
	else
998
		ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
999

S
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1000
	ath9k_init_nfcal_hist_buffer(ah);
1001

1002 1003
	common->state = ATH_HW_INITIALIZED;

1004
	return 0;
1005 1006
}

1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020
int ath9k_hw_init(struct ath_hw *ah)
{
	int ret;
	struct ath_common *common = ath9k_hw_common(ah);

	/* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
	switch (ah->hw_version.devid) {
	case AR5416_DEVID_PCI:
	case AR5416_DEVID_PCIE:
	case AR5416_AR9100_DEVID:
	case AR9160_DEVID_PCI:
	case AR9280_DEVID_PCI:
	case AR9280_DEVID_PCIE:
	case AR9285_DEVID_PCIE:
1021 1022
	case AR9287_DEVID_PCI:
	case AR9287_DEVID_PCIE:
1023
	case AR2427_DEVID_PCIE:
1024
	case AR9300_DEVID_PCIE:
1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046
		break;
	default:
		if (common->bus_ops->ath_bus_type == ATH_USB)
			break;
		ath_print(common, ATH_DBG_FATAL,
			  "Hardware device ID 0x%04x not supported\n",
			  ah->hw_version.devid);
		return -EOPNOTSUPP;
	}

	ret = __ath9k_hw_init(ah);
	if (ret) {
		ath_print(common, ATH_DBG_FATAL,
			  "Unable to initialize hardware; "
			  "initialization status: %d\n", ret);
		return ret;
	}

	return 0;
}
EXPORT_SYMBOL(ath9k_hw_init);

1047
static void ath9k_hw_init_qos(struct ath_hw *ah)
1048
{
S
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1049 1050
	REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
	REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
1051

S
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1052 1053 1054 1055 1056 1057 1058 1059 1060 1061
	REG_WRITE(ah, AR_QOS_NO_ACK,
		  SM(2, AR_QOS_NO_ACK_TWO_BIT) |
		  SM(5, AR_QOS_NO_ACK_BIT_OFF) |
		  SM(0, AR_QOS_NO_ACK_BYTE_OFF));

	REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
	REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
	REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
	REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
	REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1062 1063
}

1064
static void ath9k_hw_init_pll(struct ath_hw *ah,
S
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1065
			      struct ath9k_channel *chan)
1066
{
1067
	u32 pll = ath9k_hw_compute_pll_control(ah, chan);
1068

1069
	REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1070

1071 1072
	/* Switch the core clock for ar9271 to 117Mhz */
	if (AR_SREV_9271(ah)) {
1073 1074
		udelay(500);
		REG_WRITE(ah, 0x50040, 0x304);
1075 1076
	}

S
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1077 1078 1079
	udelay(RTC_PLL_SETTLE_DELAY);

	REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1080 1081
}

1082
static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1083
					  enum nl80211_iftype opmode)
1084
{
1085
	u32 imr_reg = AR_IMR_TXERR |
S
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1086 1087 1088 1089
		AR_IMR_TXURN |
		AR_IMR_RXERR |
		AR_IMR_RXORN |
		AR_IMR_BCNMISC;
1090

S
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1091
	if (ah->config.rx_intr_mitigation)
1092
		imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1093
	else
1094
		imr_reg |= AR_IMR_RXOK;
1095

1096
	imr_reg |= AR_IMR_TXOK;
1097

1098
	if (opmode == NL80211_IFTYPE_AP)
1099
		imr_reg |= AR_IMR_MIB;
1100

1101
	REG_WRITE(ah, AR_IMR, imr_reg);
1102 1103
	ah->imrs2_reg |= AR_IMR_S2_GTT;
	REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
1104

S
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1105 1106 1107 1108 1109
	if (!AR_SREV_9100(ah)) {
		REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
		REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
		REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
	}
1110 1111
}

1112
static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
1113
{
1114 1115 1116
	u32 val = ath9k_hw_mac_to_clks(ah, us);
	val = min(val, (u32) 0xFFFF);
	REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
1117 1118
}

1119
static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1120
{
1121 1122 1123 1124 1125 1126 1127 1128 1129 1130
	u32 val = ath9k_hw_mac_to_clks(ah, us);
	val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
	REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
}

static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
{
	u32 val = ath9k_hw_mac_to_clks(ah, us);
	val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
	REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
1131
}
S
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1132

1133
static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1134 1135
{
	if (tu > 0xFFFF) {
1136 1137
		ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
			  "bad global tx timeout %u\n", tu);
1138
		ah->globaltxtimeout = (u32) -1;
1139 1140 1141
		return false;
	} else {
		REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1142
		ah->globaltxtimeout = tu;
1143 1144 1145 1146
		return true;
	}
}

1147
void ath9k_hw_init_global_settings(struct ath_hw *ah)
1148
{
1149 1150
	struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
	int acktimeout;
1151
	int slottime;
1152 1153
	int sifstime;

1154 1155
	ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
		  ah->misc_mode);
1156

1157
	if (ah->misc_mode != 0)
S
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1158
		REG_WRITE(ah, AR_PCU_MISC,
1159
			  REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1160 1161 1162 1163 1164 1165

	if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
		sifstime = 16;
	else
		sifstime = 10;

1166 1167 1168
	/* As defined by IEEE 802.11-2007 17.3.8.6 */
	slottime = ah->slottime + 3 * ah->coverage_class;
	acktimeout = slottime + sifstime;
1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179

	/*
	 * Workaround for early ACK timeouts, add an offset to match the
	 * initval's 64us ack timeout value.
	 * This was initially only meant to work around an issue with delayed
	 * BA frames in some implementations, but it has been found to fix ACK
	 * timeout issues in other cases as well.
	 */
	if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
		acktimeout += 64 - sifstime - ah->slottime;

1180
	ath9k_hw_setslottime(ah, slottime);
1181 1182
	ath9k_hw_set_ack_timeout(ah, acktimeout);
	ath9k_hw_set_cts_timeout(ah, acktimeout);
1183 1184
	if (ah->globaltxtimeout != (u32) -1)
		ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
S
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1185
}
1186
EXPORT_SYMBOL(ath9k_hw_init_global_settings);
S
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1187

S
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1188
void ath9k_hw_deinit(struct ath_hw *ah)
S
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1189
{
1190 1191
	struct ath_common *common = ath9k_hw_common(ah);

S
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1192
	if (common->state < ATH_HW_INITIALIZED)
1193 1194
		goto free_hw;

S
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1195
	if (!AR_SREV_9100(ah))
1196
		ath9k_hw_ani_disable(ah);
S
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1197

1198
	ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1199 1200

free_hw:
1201
	ath9k_hw_rf_free_ext_banks(ah);
S
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1202
}
S
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1203
EXPORT_SYMBOL(ath9k_hw_deinit);
S
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1204 1205 1206 1207 1208

/*******/
/* INI */
/*******/

1209
u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222
{
	u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);

	if (IS_CHAN_B(chan))
		ctl |= CTL_11B;
	else if (IS_CHAN_G(chan))
		ctl |= CTL_11G;
	else
		ctl |= CTL_11A;

	return ctl;
}

S
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1223 1224 1225 1226
/****************************************/
/* Reset and Channel Switching Routines */
/****************************************/

1227
static inline void ath9k_hw_set_dma(struct ath_hw *ah)
S
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1228 1229 1230
{
	u32 regval;

1231 1232 1233
	/*
	 * set AHB_MODE not to do cacheline prefetches
	*/
S
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1234 1235 1236
	regval = REG_READ(ah, AR_AHB_MODE);
	REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);

1237 1238 1239
	/*
	 * let mac dma reads be in 128 byte chunks
	 */
S
Sujith 已提交
1240 1241 1242
	regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
	REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);

1243 1244 1245 1246 1247
	/*
	 * Restore TX Trigger Level to its pre-reset value.
	 * The initial value depends on whether aggregation is enabled, and is
	 * adjusted whenever underruns are detected.
	 */
1248
	REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
S
Sujith 已提交
1249

1250 1251 1252
	/*
	 * let mac dma writes be in 128 byte chunks
	 */
S
Sujith 已提交
1253 1254 1255
	regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
	REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);

1256 1257 1258
	/*
	 * Setup receive FIFO threshold to hold off TX activities
	 */
S
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1259 1260
	REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);

1261 1262 1263 1264
	/*
	 * reduce the number of usable entries in PCU TXBUF to avoid
	 * wrap around issues.
	 */
S
Sujith 已提交
1265
	if (AR_SREV_9285(ah)) {
1266 1267 1268 1269
		/* For AR9285 the number of Fifos are reduced to half.
		 * So set the usable tx buf size also to half to
		 * avoid data/delimiter underruns
		 */
S
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1270 1271
		REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
			  AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1272
	} else if (!AR_SREV_9271(ah)) {
S
Sujith 已提交
1273 1274 1275 1276 1277
		REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
			  AR_PCU_TXBUF_CTRL_USABLE_SIZE);
	}
}

1278
static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
S
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1279 1280 1281 1282 1283 1284
{
	u32 val;

	val = REG_READ(ah, AR_STA_ID1);
	val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
	switch (opmode) {
1285
	case NL80211_IFTYPE_AP:
S
Sujith 已提交
1286 1287 1288
		REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
			  | AR_STA_ID1_KSRCH_MODE);
		REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1289
		break;
1290
	case NL80211_IFTYPE_ADHOC:
1291
	case NL80211_IFTYPE_MESH_POINT:
S
Sujith 已提交
1292 1293 1294
		REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
			  | AR_STA_ID1_KSRCH_MODE);
		REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1295
		break;
1296 1297
	case NL80211_IFTYPE_STATION:
	case NL80211_IFTYPE_MONITOR:
S
Sujith 已提交
1298
		REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1299
		break;
S
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1300 1301 1302
	}
}

1303 1304
void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
				   u32 *coef_mantissa, u32 *coef_exponent)
S
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1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319
{
	u32 coef_exp, coef_man;

	for (coef_exp = 31; coef_exp > 0; coef_exp--)
		if ((coef_scaled >> coef_exp) & 0x1)
			break;

	coef_exp = 14 - (coef_exp - COEF_SCALE_S);

	coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));

	*coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
	*coef_exponent = coef_exp - 16;
}

1320
static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
S
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1321 1322 1323 1324
{
	u32 rst_flags;
	u32 tmpReg;

1325 1326 1327 1328 1329 1330 1331 1332
	if (AR_SREV_9100(ah)) {
		u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
		val &= ~AR_RTC_DERIVED_CLK_PERIOD;
		val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
		REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
		(void)REG_READ(ah, AR_RTC_DERIVED_CLK);
	}

S
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1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343
	REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
		  AR_RTC_FORCE_WAKE_ON_INT);

	if (AR_SREV_9100(ah)) {
		rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
			AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
	} else {
		tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
		if (tmpReg &
		    (AR_INTR_SYNC_LOCAL_TIMEOUT |
		     AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1344
			u32 val;
S
Sujith 已提交
1345
			REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1346 1347 1348 1349 1350 1351 1352

			val = AR_RC_HOSTIF;
			if (!AR_SREV_9300_20_OR_LATER(ah))
				val |= AR_RC_AHB;
			REG_WRITE(ah, AR_RC, val);

		} else if (!AR_SREV_9300_20_OR_LATER(ah))
S
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1353 1354 1355 1356 1357 1358 1359
			REG_WRITE(ah, AR_RC, AR_RC_AHB);

		rst_flags = AR_RTC_RC_MAC_WARM;
		if (type == ATH9K_RESET_COLD)
			rst_flags |= AR_RTC_RC_MAC_COLD;
	}

1360
	REG_WRITE(ah, AR_RTC_RC, rst_flags);
S
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1361 1362
	udelay(50);

1363
	REG_WRITE(ah, AR_RTC_RC, 0);
S
Sujith 已提交
1364
	if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1365 1366
		ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
			  "RTC stuck in MAC reset\n");
S
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1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378
		return false;
	}

	if (!AR_SREV_9100(ah))
		REG_WRITE(ah, AR_RC, 0);

	if (AR_SREV_9100(ah))
		udelay(50);

	return true;
}

1379
static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
S
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1380 1381 1382 1383
{
	REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
		  AR_RTC_FORCE_WAKE_ON_INT);

1384
	if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1385 1386
		REG_WRITE(ah, AR_RC, AR_RC_AHB);

1387
	REG_WRITE(ah, AR_RTC_RESET, 0);
1388
	udelay(2);
1389 1390 1391 1392

	if (!AR_SREV_9100(ah))
		REG_WRITE(ah, AR_RC, 0);

1393
	REG_WRITE(ah, AR_RTC_RESET, 1);
S
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1394 1395 1396 1397

	if (!ath9k_hw_wait(ah,
			   AR_RTC_STATUS,
			   AR_RTC_STATUS_M,
S
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1398 1399
			   AR_RTC_STATUS_ON,
			   AH_WAIT_TIMEOUT)) {
1400 1401
		ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
			  "RTC not waking up\n");
S
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1402
		return false;
1403 1404
	}

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1405 1406 1407 1408 1409
	ath9k_hw_read_revisions(ah);

	return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
}

1410
static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
S
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1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423
{
	REG_WRITE(ah, AR_RTC_FORCE_WAKE,
		  AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);

	switch (type) {
	case ATH9K_RESET_POWER_ON:
		return ath9k_hw_set_reset_power_on(ah);
	case ATH9K_RESET_WARM:
	case ATH9K_RESET_COLD:
		return ath9k_hw_set_reset(ah, type);
	default:
		return false;
	}
1424 1425
}

1426
static bool ath9k_hw_chip_reset(struct ath_hw *ah,
S
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1427
				struct ath9k_channel *chan)
1428
{
1429
	if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1430 1431 1432
		if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
			return false;
	} else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
S
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1433
		return false;
1434

1435
	if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
S
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1436
		return false;
1437

1438
	ah->chip_fullsleep = false;
S
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1439 1440
	ath9k_hw_init_pll(ah, chan);
	ath9k_hw_set_rfmode(ah, chan);
1441

S
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1442
	return true;
1443 1444
}

1445
static bool ath9k_hw_channel_change(struct ath_hw *ah,
L
Luis R. Rodriguez 已提交
1446
				    struct ath9k_channel *chan)
1447
{
1448
	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1449
	struct ath_common *common = ath9k_hw_common(ah);
1450
	struct ieee80211_channel *channel = chan->chan;
1451
	u32 qnum;
1452
	int r;
1453 1454 1455

	for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
		if (ath9k_hw_numtxpending(ah, qnum)) {
1456 1457 1458
			ath_print(common, ATH_DBG_QUEUE,
				  "Transmit frames pending on "
				  "queue %d\n", qnum);
1459 1460 1461 1462
			return false;
		}
	}

1463
	if (!ath9k_hw_rfbus_req(ah)) {
1464 1465
		ath_print(common, ATH_DBG_FATAL,
			  "Could not kill baseband RX\n");
1466 1467 1468
		return false;
	}

1469
	ath9k_hw_set_channel_regs(ah, chan);
1470

1471
	r = ath9k_hw_rf_set_freq(ah, chan);
1472 1473 1474 1475
	if (r) {
		ath_print(common, ATH_DBG_FATAL,
			  "Failed to set channel\n");
		return false;
1476 1477
	}

1478
	ah->eep_ops->set_txpower(ah, chan,
1479
			     ath9k_regd_get_ctl(regulatory, chan),
S
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1480 1481 1482
			     channel->max_antenna_gain * 2,
			     channel->max_power * 2,
			     min((u32) MAX_RATE_POWER,
1483
			     (u32) regulatory->power_limit));
1484

1485
	ath9k_hw_rfbus_done(ah);
1486

S
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1487 1488 1489
	if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
		ath9k_hw_set_delta_slope(ah, chan);

1490
	ath9k_hw_spur_mitigate_freq(ah, chan);
S
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1491 1492 1493 1494 1495 1496 1497

	if (!chan->oneTimeCalsDone)
		chan->oneTimeCalsDone = true;

	return true;
}

1498
int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1499
		    bool bChannelChange)
1500
{
1501
	struct ath_common *common = ath9k_hw_common(ah);
1502
	u32 saveLedState;
1503
	struct ath9k_channel *curchan = ah->curchan;
1504 1505
	u32 saveDefAntenna;
	u32 macStaId1;
S
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1506
	u64 tsf = 0;
1507
	int i, r;
1508

1509 1510
	ah->txchainmask = common->tx_chainmask;
	ah->rxchainmask = common->rx_chainmask;
1511

1512
	if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1513
		return -EIO;
1514

1515
	if (curchan && !ah->chip_fullsleep)
1516 1517 1518
		ath9k_hw_getnf(ah, curchan);

	if (bChannelChange &&
1519 1520 1521
	    (ah->chip_fullsleep != true) &&
	    (ah->curchan != NULL) &&
	    (chan->channel != ah->curchan->channel) &&
1522
	    ((chan->channelFlags & CHANNEL_ALL) ==
1523
	     (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1524 1525
	     !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
	     IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
1526

L
Luis R. Rodriguez 已提交
1527
		if (ath9k_hw_channel_change(ah, chan)) {
1528
			ath9k_hw_loadnf(ah, ah->curchan);
1529
			ath9k_hw_start_nfcal(ah);
1530
			return 0;
1531 1532 1533 1534 1535 1536 1537 1538 1539
		}
	}

	saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
	if (saveDefAntenna == 0)
		saveDefAntenna = 1;

	macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;

S
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1540 1541 1542 1543
	/* For chips on which RTC reset is done, save TSF before it gets cleared */
	if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
		tsf = ath9k_hw_gettsf64(ah);

1544 1545 1546 1547 1548 1549
	saveLedState = REG_READ(ah, AR_CFG_LED) &
		(AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
		 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);

	ath9k_hw_mark_phy_inactive(ah);

1550
	/* Only required on the first reset */
1551 1552 1553 1554 1555 1556 1557
	if (AR_SREV_9271(ah) && ah->htc_reset_init) {
		REG_WRITE(ah,
			  AR9271_RESET_POWER_DOWN_CONTROL,
			  AR9271_RADIO_RF_RST);
		udelay(50);
	}

1558
	if (!ath9k_hw_chip_reset(ah, chan)) {
1559
		ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1560
		return -EINVAL;
1561 1562
	}

1563
	/* Only required on the first reset */
1564 1565 1566 1567 1568 1569 1570 1571
	if (AR_SREV_9271(ah) && ah->htc_reset_init) {
		ah->htc_reset_init = false;
		REG_WRITE(ah,
			  AR9271_RESET_POWER_DOWN_CONTROL,
			  AR9271_GATE_MAC_CTL);
		udelay(50);
	}

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1572 1573 1574 1575
	/* Restore TSF */
	if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
		ath9k_hw_settsf64(ah, tsf);

1576 1577
	if (AR_SREV_9280_10_OR_LATER(ah))
		REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1578

L
Luis R. Rodriguez 已提交
1579
	r = ath9k_hw_process_ini(ah, chan);
1580 1581
	if (r)
		return r;
1582

1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599
	/* Setup MFP options for CCMP */
	if (AR_SREV_9280_20_OR_LATER(ah)) {
		/* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
		 * frames when constructing CCMP AAD. */
		REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
			      0xc7ff);
		ah->sw_mgmt_crypto = false;
	} else if (AR_SREV_9160_10_OR_LATER(ah)) {
		/* Disable hardware crypto for management frames */
		REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
			    AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
		REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
			    AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
		ah->sw_mgmt_crypto = true;
	} else
		ah->sw_mgmt_crypto = true;

1600 1601 1602
	if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
		ath9k_hw_set_delta_slope(ah, chan);

1603
	ath9k_hw_spur_mitigate_freq(ah, chan);
1604
	ah->eep_ops->set_board_values(ah, chan);
1605

1606 1607
	REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
	REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1608 1609
		  | macStaId1
		  | AR_STA_ID1_RTS_USE_DEF
1610
		  | (ah->config.
1611
		     ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1612 1613
		  | ah->sta_id1_defaults);
	ath9k_hw_set_operating_mode(ah, ah->opmode);
1614

1615
	ath_hw_setbssidmask(common);
1616 1617 1618

	REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);

1619
	ath9k_hw_write_associd(ah);
1620 1621 1622 1623 1624

	REG_WRITE(ah, AR_ISR, ~0);

	REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);

1625
	r = ath9k_hw_rf_set_freq(ah, chan);
1626 1627
	if (r)
		return r;
1628 1629 1630 1631

	for (i = 0; i < AR_NUM_DCU; i++)
		REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);

1632 1633
	ah->intr_txqs = 0;
	for (i = 0; i < ah->caps.total_queues; i++)
1634 1635
		ath9k_hw_resettxqueue(ah, i);

1636
	ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1637 1638
	ath9k_hw_init_qos(ah);

1639
	if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1640
		ath9k_enable_rfkill(ah);
J
Johannes Berg 已提交
1641

1642
	ath9k_hw_init_global_settings(ah);
1643

1644
	if (AR_SREV_9287_12_OR_LATER(ah)) {
1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659
		REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
			  AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
		REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
			  AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
		REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
			  AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);

		REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
		REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);

		REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
			    AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
		REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
			      AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
	}
1660
	if (AR_SREV_9287_12_OR_LATER(ah)) {
1661 1662 1663 1664
		REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
				AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
	}

1665 1666 1667 1668 1669 1670 1671
	REG_WRITE(ah, AR_STA_ID1,
		  REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);

	ath9k_hw_set_dma(ah);

	REG_WRITE(ah, AR_OBS, 8);

S
Sujith 已提交
1672
	if (ah->config.rx_intr_mitigation) {
1673 1674 1675 1676 1677 1678
		REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
		REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
	}

	ath9k_hw_init_bb(ah, chan);

1679
	if (!ath9k_hw_init_cal(ah, chan))
1680
		return -EIO;
1681

1682
	ath9k_hw_restore_chainmask(ah);
1683 1684
	REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);

1685 1686 1687
	/*
	 * For big endian systems turn on swapping for descriptors
	 */
1688 1689 1690 1691
	if (AR_SREV_9100(ah)) {
		u32 mask;
		mask = REG_READ(ah, AR_CFG);
		if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1692
			ath_print(common, ATH_DBG_RESET,
S
Sujith 已提交
1693
				"CFG Byte Swap Set 0x%x\n", mask);
1694 1695 1696 1697
		} else {
			mask =
				INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
			REG_WRITE(ah, AR_CFG, mask);
1698
			ath_print(common, ATH_DBG_RESET,
S
Sujith 已提交
1699
				"Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1700 1701
		}
	} else {
1702 1703 1704
		/* Configure AR9271 target WLAN */
                if (AR_SREV_9271(ah))
			REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1705
#ifdef __BIG_ENDIAN
1706 1707
                else
			REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1708 1709 1710
#endif
	}

1711
	if (ah->btcoex_hw.enabled)
1712 1713
		ath9k_hw_btcoex_enable(ah);

1714
	return 0;
1715
}
1716
EXPORT_SYMBOL(ath9k_hw_reset);
1717

S
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1718 1719 1720
/************************/
/* Key Cache Management */
/************************/
1721

1722
bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
1723
{
S
Sujith 已提交
1724
	u32 keyType;
1725

1726
	if (entry >= ah->caps.keycache_size) {
1727 1728
		ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
			  "keychache entry %u out of range\n", entry);
1729 1730 1731
		return false;
	}

S
Sujith 已提交
1732
	keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
1733

S
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1734 1735 1736 1737 1738 1739 1740 1741
	REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
	REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
	REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
	REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
	REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
	REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
	REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
	REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
1742

S
Sujith 已提交
1743 1744
	if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
		u16 micentry = entry + 64;
1745

S
Sujith 已提交
1746 1747 1748 1749
		REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
		REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
		REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
		REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1750 1751 1752 1753 1754

	}

	return true;
}
1755
EXPORT_SYMBOL(ath9k_hw_keyreset);
1756

1757
bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
1758
{
S
Sujith 已提交
1759
	u32 macHi, macLo;
1760

1761
	if (entry >= ah->caps.keycache_size) {
1762 1763
		ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
			  "keychache entry %u out of range\n", entry);
S
Sujith 已提交
1764
		return false;
1765 1766
	}

S
Sujith 已提交
1767 1768 1769 1770 1771 1772 1773 1774 1775
	if (mac != NULL) {
		macHi = (mac[5] << 8) | mac[4];
		macLo = (mac[3] << 24) |
			(mac[2] << 16) |
			(mac[1] << 8) |
			mac[0];
		macLo >>= 1;
		macLo |= (macHi & 1) << 31;
		macHi >>= 1;
1776
	} else {
S
Sujith 已提交
1777
		macLo = macHi = 0;
1778
	}
S
Sujith 已提交
1779 1780
	REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
	REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
1781

S
Sujith 已提交
1782
	return true;
1783
}
1784
EXPORT_SYMBOL(ath9k_hw_keysetmac);
1785

1786
bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
S
Sujith 已提交
1787
				 const struct ath9k_keyval *k,
J
Jouni Malinen 已提交
1788
				 const u8 *mac)
1789
{
1790
	const struct ath9k_hw_capabilities *pCap = &ah->caps;
1791
	struct ath_common *common = ath9k_hw_common(ah);
S
Sujith 已提交
1792 1793
	u32 key0, key1, key2, key3, key4;
	u32 keyType;
1794

S
Sujith 已提交
1795
	if (entry >= pCap->keycache_size) {
1796 1797
		ath_print(common, ATH_DBG_FATAL,
			  "keycache entry %u out of range\n", entry);
S
Sujith 已提交
1798
		return false;
1799 1800
	}

S
Sujith 已提交
1801 1802 1803 1804 1805 1806
	switch (k->kv_type) {
	case ATH9K_CIPHER_AES_OCB:
		keyType = AR_KEYTABLE_TYPE_AES;
		break;
	case ATH9K_CIPHER_AES_CCM:
		if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
1807 1808 1809
			ath_print(common, ATH_DBG_ANY,
				  "AES-CCM not supported by mac rev 0x%x\n",
				  ah->hw_version.macRev);
S
Sujith 已提交
1810 1811 1812 1813 1814 1815 1816 1817
			return false;
		}
		keyType = AR_KEYTABLE_TYPE_CCM;
		break;
	case ATH9K_CIPHER_TKIP:
		keyType = AR_KEYTABLE_TYPE_TKIP;
		if (ATH9K_IS_MIC_ENABLED(ah)
		    && entry + 64 >= pCap->keycache_size) {
1818 1819
			ath_print(common, ATH_DBG_ANY,
				  "entry %u inappropriate for TKIP\n", entry);
S
Sujith 已提交
1820 1821 1822 1823
			return false;
		}
		break;
	case ATH9K_CIPHER_WEP:
1824
		if (k->kv_len < WLAN_KEY_LEN_WEP40) {
1825 1826
			ath_print(common, ATH_DBG_ANY,
				  "WEP key length %u too small\n", k->kv_len);
S
Sujith 已提交
1827 1828
			return false;
		}
1829
		if (k->kv_len <= WLAN_KEY_LEN_WEP40)
S
Sujith 已提交
1830
			keyType = AR_KEYTABLE_TYPE_40;
1831
		else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
S
Sujith 已提交
1832 1833 1834 1835 1836 1837 1838 1839
			keyType = AR_KEYTABLE_TYPE_104;
		else
			keyType = AR_KEYTABLE_TYPE_128;
		break;
	case ATH9K_CIPHER_CLR:
		keyType = AR_KEYTABLE_TYPE_CLR;
		break;
	default:
1840 1841
		ath_print(common, ATH_DBG_FATAL,
			  "cipher %u not supported\n", k->kv_type);
S
Sujith 已提交
1842
		return false;
1843 1844
	}

J
Jouni Malinen 已提交
1845 1846 1847 1848 1849
	key0 = get_unaligned_le32(k->kv_val + 0);
	key1 = get_unaligned_le16(k->kv_val + 4);
	key2 = get_unaligned_le32(k->kv_val + 6);
	key3 = get_unaligned_le16(k->kv_val + 10);
	key4 = get_unaligned_le32(k->kv_val + 12);
1850
	if (k->kv_len <= WLAN_KEY_LEN_WEP104)
S
Sujith 已提交
1851
		key4 &= 0xff;
1852

1853 1854 1855 1856 1857 1858 1859
	/*
	 * Note: Key cache registers access special memory area that requires
	 * two 32-bit writes to actually update the values in the internal
	 * memory. Consequently, the exact order and pairs used here must be
	 * maintained.
	 */

S
Sujith 已提交
1860 1861
	if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
		u16 micentry = entry + 64;
1862

1863 1864 1865 1866 1867 1868
		/*
		 * Write inverted key[47:0] first to avoid Michael MIC errors
		 * on frames that could be sent or received at the same time.
		 * The correct key will be written in the end once everything
		 * else is ready.
		 */
S
Sujith 已提交
1869 1870
		REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
		REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
1871 1872

		/* Write key[95:48] */
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1873 1874
		REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
		REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1875 1876

		/* Write key[127:96] and key type */
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1877 1878
		REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
		REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1879 1880

		/* Write MAC address for the entry */
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1881
		(void) ath9k_hw_keysetmac(ah, entry, mac);
1882

1883
		if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895
			/*
			 * TKIP uses two key cache entries:
			 * Michael MIC TX/RX keys in the same key cache entry
			 * (idx = main index + 64):
			 * key0 [31:0] = RX key [31:0]
			 * key1 [15:0] = TX key [31:16]
			 * key1 [31:16] = reserved
			 * key2 [31:0] = RX key [63:32]
			 * key3 [15:0] = TX key [15:0]
			 * key3 [31:16] = reserved
			 * key4 [31:0] = TX key [63:32]
			 */
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1896
			u32 mic0, mic1, mic2, mic3, mic4;
1897

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1898 1899 1900 1901 1902
			mic0 = get_unaligned_le32(k->kv_mic + 0);
			mic2 = get_unaligned_le32(k->kv_mic + 4);
			mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
			mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
			mic4 = get_unaligned_le32(k->kv_txmic + 4);
1903 1904

			/* Write RX[31:0] and TX[31:16] */
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1905 1906
			REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
			REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
1907 1908

			/* Write RX[63:32] and TX[15:0] */
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1909 1910
			REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
			REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
1911 1912

			/* Write TX[63:32] and keyType(reserved) */
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1913 1914 1915
			REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
			REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
				  AR_KEYTABLE_TYPE_CLR);
1916

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1917
		} else {
1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933
			/*
			 * TKIP uses four key cache entries (two for group
			 * keys):
			 * Michael MIC TX/RX keys are in different key cache
			 * entries (idx = main index + 64 for TX and
			 * main index + 32 + 96 for RX):
			 * key0 [31:0] = TX/RX MIC key [31:0]
			 * key1 [31:0] = reserved
			 * key2 [31:0] = TX/RX MIC key [63:32]
			 * key3 [31:0] = reserved
			 * key4 [31:0] = reserved
			 *
			 * Upper layer code will call this function separately
			 * for TX and RX keys when these registers offsets are
			 * used.
			 */
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1934
			u32 mic0, mic2;
1935

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1936 1937
			mic0 = get_unaligned_le32(k->kv_mic + 0);
			mic2 = get_unaligned_le32(k->kv_mic + 4);
1938 1939

			/* Write MIC key[31:0] */
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1940 1941
			REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
			REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1942 1943

			/* Write MIC key[63:32] */
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1944 1945
			REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
			REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1946 1947

			/* Write TX[63:32] and keyType(reserved) */
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1948 1949 1950 1951
			REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
			REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
				  AR_KEYTABLE_TYPE_CLR);
		}
1952 1953

		/* MAC address registers are reserved for the MIC entry */
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1954 1955
		REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
		REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
1956 1957 1958 1959 1960 1961

		/*
		 * Write the correct (un-inverted) key[47:0] last to enable
		 * TKIP now that all other registers are set with correct
		 * values.
		 */
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1962 1963 1964
		REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
		REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
	} else {
1965
		/* Write key[47:0] */
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1966 1967
		REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
		REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1968 1969

		/* Write key[95:48] */
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1970 1971
		REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
		REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1972 1973

		/* Write key[127:96] and key type */
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1974 1975
		REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
		REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1976

1977
		/* Write MAC address for the entry */
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1978 1979
		(void) ath9k_hw_keysetmac(ah, entry, mac);
	}
1980 1981 1982

	return true;
}
1983
EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
1984

1985
bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
1986
{
1987
	if (entry < ah->caps.keycache_size) {
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1988 1989 1990 1991 1992
		u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
		if (val & AR_KEYTABLE_VALID)
			return true;
	}
	return false;
1993
}
1994
EXPORT_SYMBOL(ath9k_hw_keyisvalid);
1995

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1996 1997 1998 1999
/******************************/
/* Power Management (Chipset) */
/******************************/

2000 2001 2002 2003
/*
 * Notify Power Mgt is disabled in self-generated frames.
 * If requested, force chip to sleep.
 */
2004
static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2005
{
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2006 2007
	REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
	if (setChip) {
2008 2009 2010 2011
		/*
		 * Clear the RTC force wake bit to allow the
		 * mac to go to sleep.
		 */
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2012 2013
		REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
			    AR_RTC_FORCE_WAKE_EN);
2014
		if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
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2015
			REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2016

2017
		/* Shutdown chip. Active low */
2018
		if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
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2019 2020
			REG_CLR_BIT(ah, (AR_RTC_RESET),
				    AR_RTC_RESET_EN);
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2021
	}
2022 2023
}

2024 2025 2026 2027 2028
/*
 * Notify Power Management is enabled in self-generating
 * frames. If request, set power mode of chip to
 * auto/normal.  Duration in units of 128us (1/8 TU).
 */
2029
static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2030
{
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2031 2032
	REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
	if (setChip) {
2033
		struct ath9k_hw_capabilities *pCap = &ah->caps;
2034

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2035
		if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2036
			/* Set WakeOnInterrupt bit; clear ForceWake bit */
S
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2037 2038 2039
			REG_WRITE(ah, AR_RTC_FORCE_WAKE,
				  AR_RTC_FORCE_WAKE_ON_INT);
		} else {
2040 2041 2042 2043
			/*
			 * Clear the RTC force wake bit to allow the
			 * mac to go to sleep.
			 */
S
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2044 2045
			REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
				    AR_RTC_FORCE_WAKE_EN);
2046 2047 2048 2049
		}
	}
}

2050
static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2051
{
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2052 2053
	u32 val;
	int i;
2054

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2055 2056 2057 2058 2059 2060 2061
	if (setChip) {
		if ((REG_READ(ah, AR_RTC_STATUS) &
		     AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
			if (ath9k_hw_set_reset_reg(ah,
					   ATH9K_RESET_POWER_ON) != true) {
				return false;
			}
2062 2063
			if (!AR_SREV_9300_20_OR_LATER(ah))
				ath9k_hw_init_pll(ah, NULL);
S
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2064 2065 2066 2067
		}
		if (AR_SREV_9100(ah))
			REG_SET_BIT(ah, AR_RTC_RESET,
				    AR_RTC_RESET_EN);
2068

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2069 2070 2071
		REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
			    AR_RTC_FORCE_WAKE_EN);
		udelay(50);
2072

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2073 2074 2075 2076 2077 2078 2079
		for (i = POWER_UP_TIME / 50; i > 0; i--) {
			val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
			if (val == AR_RTC_STATUS_ON)
				break;
			udelay(50);
			REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
				    AR_RTC_FORCE_WAKE_EN);
2080
		}
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2081
		if (i == 0) {
2082 2083 2084
			ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
				  "Failed to wakeup in %uus\n",
				  POWER_UP_TIME / 20);
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2085
			return false;
2086 2087 2088
		}
	}

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2089
	REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2090

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2091
	return true;
2092 2093
}

2094
bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2095
{
2096
	struct ath_common *common = ath9k_hw_common(ah);
2097
	int status = true, setChip = true;
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2098 2099 2100 2101 2102 2103 2104
	static const char *modes[] = {
		"AWAKE",
		"FULL-SLEEP",
		"NETWORK SLEEP",
		"UNDEFINED"
	};

2105 2106 2107
	if (ah->power_mode == mode)
		return status;

2108 2109
	ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
		  modes[ah->power_mode], modes[mode]);
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2110 2111 2112 2113 2114 2115 2116

	switch (mode) {
	case ATH9K_PM_AWAKE:
		status = ath9k_hw_set_power_awake(ah, setChip);
		break;
	case ATH9K_PM_FULL_SLEEP:
		ath9k_set_power_sleep(ah, setChip);
2117
		ah->chip_fullsleep = true;
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2118 2119 2120 2121
		break;
	case ATH9K_PM_NETWORK_SLEEP:
		ath9k_set_power_network_sleep(ah, setChip);
		break;
2122
	default:
2123 2124
		ath_print(common, ATH_DBG_FATAL,
			  "Unknown power mode %u\n", mode);
2125 2126
		return false;
	}
2127
	ah->power_mode = mode;
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2128 2129

	return status;
2130
}
2131
EXPORT_SYMBOL(ath9k_hw_setpower);
2132

2133 2134 2135 2136 2137 2138 2139 2140 2141
/*
 * Helper for ASPM support.
 *
 * Disable PLL when in L0s as well as receiver clock when in L1.
 * This power saving option must be enabled through the SerDes.
 *
 * Programming the SerDes must go through the same 288 bit serial shift
 * register as the other analog registers.  Hence the 9 writes.
 */
2142 2143 2144
static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
					 int restore,
					 int power_off)
2145
{
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2146
	u8 i;
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2147
	u32 val;
2148

2149
	if (ah->is_pciexpress != true)
S
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2150
		return;
2151

2152
	/* Do not touch SerDes registers */
2153
	if (ah->config.pcie_powersave_enable == 2)
S
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2154 2155
		return;

2156
	/* Nothing to do on restore for 11N */
V
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2157 2158 2159 2160 2161
	if (!restore) {
		if (AR_SREV_9280_20_OR_LATER(ah)) {
			/*
			 * AR9280 2.0 or later chips use SerDes values from the
			 * initvals.h initialized depending on chipset during
2162
			 * __ath9k_hw_init()
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2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182
			 */
			for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
				REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
					  INI_RA(&ah->iniPcieSerdes, i, 1));
			}
		} else if (AR_SREV_9280(ah) &&
			   (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
			REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
			REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);

			/* RX shut off when elecidle is asserted */
			REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
			REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
			REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);

			/* Shut off CLKREQ active in L1 */
			if (ah->config.pcie_clock_req)
				REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
			else
				REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
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2183

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2184 2185 2186
			REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
			REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
			REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
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2187

V
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2188 2189
			/* Load the new settings */
			REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
S
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2190

V
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2191 2192 2193
		} else {
			REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
			REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
S
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2194

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2195 2196 2197 2198
			/* RX shut off when elecidle is asserted */
			REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
			REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
			REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
S
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2199

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2200 2201 2202 2203 2204
			/*
			 * Ignore ah->ah_config.pcie_clock_req setting for
			 * pre-AR9280 11n
			 */
			REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2205

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2206 2207 2208
			REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
			REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
			REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2209

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2210 2211 2212
			/* Load the new settings */
			REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
		}
2213

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2214
		udelay(1000);
2215

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2216 2217
		/* set bit 19 to allow forcing of pcie core into L1 state */
		REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2218

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2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240
		/* Several PCIe massages to ensure proper behaviour */
		if (ah->config.pcie_waen) {
			val = ah->config.pcie_waen;
			if (!power_off)
				val &= (~AR_WA_D3_L1_DISABLE);
		} else {
			if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
			    AR_SREV_9287(ah)) {
				val = AR9285_WA_DEFAULT;
				if (!power_off)
					val &= (~AR_WA_D3_L1_DISABLE);
			} else if (AR_SREV_9280(ah)) {
				/*
				 * On AR9280 chips bit 22 of 0x4004 needs to be
				 * set otherwise card may disappear.
				 */
				val = AR9280_WA_DEFAULT;
				if (!power_off)
					val &= (~AR_WA_D3_L1_DISABLE);
			} else
				val = AR_WA_DEFAULT;
		}
2241

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2242 2243
		REG_WRITE(ah, AR_WA, val);
	}
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2244

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2245
	if (power_off) {
2246
		/*
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2247 2248 2249 2250
		 * Set PCIe workaround bits
		 * bit 14 in WA register (disable L1) should only
		 * be set when device enters D3 and be cleared
		 * when device comes back to D0.
2251
		 */
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2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263
		if (ah->config.pcie_waen) {
			if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
				REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
		} else {
			if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
			      AR_SREV_9287(ah)) &&
			     (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
			    (AR_SREV_9280(ah) &&
			     (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
				REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
			}
		}
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2264
	}
2265 2266
}

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2267 2268 2269 2270
/**********************/
/* Interrupt Handling */
/**********************/

2271
bool ath9k_hw_intrpend(struct ath_hw *ah)
2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288
{
	u32 host_isr;

	if (AR_SREV_9100(ah))
		return true;

	host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
	if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
		return true;

	host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
	if ((host_isr & AR_INTR_SYNC_DEFAULT)
	    && (host_isr != AR_INTR_SPURIOUS))
		return true;

	return false;
}
2289
EXPORT_SYMBOL(ath9k_hw_intrpend);
2290

2291
bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2292 2293 2294
{
	u32 isr = 0;
	u32 mask2 = 0;
2295
	struct ath9k_hw_capabilities *pCap = &ah->caps;
2296 2297
	u32 sync_cause = 0;
	bool fatal_int = false;
2298
	struct ath_common *common = ath9k_hw_common(ah);
2299 2300 2301 2302 2303 2304 2305 2306 2307

	if (!AR_SREV_9100(ah)) {
		if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
			if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
			    == AR_RTC_STATUS_ON) {
				isr = REG_READ(ah, AR_ISR);
			}
		}

S
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2308 2309
		sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
			AR_INTR_SYNC_DEFAULT;
2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335

		*masked = 0;

		if (!isr && !sync_cause)
			return false;
	} else {
		*masked = 0;
		isr = REG_READ(ah, AR_ISR);
	}

	if (isr) {
		if (isr & AR_ISR_BCNMISC) {
			u32 isr2;
			isr2 = REG_READ(ah, AR_ISR_S2);
			if (isr2 & AR_ISR_S2_TIM)
				mask2 |= ATH9K_INT_TIM;
			if (isr2 & AR_ISR_S2_DTIM)
				mask2 |= ATH9K_INT_DTIM;
			if (isr2 & AR_ISR_S2_DTIMSYNC)
				mask2 |= ATH9K_INT_DTIMSYNC;
			if (isr2 & (AR_ISR_S2_CABEND))
				mask2 |= ATH9K_INT_CABEND;
			if (isr2 & AR_ISR_S2_GTT)
				mask2 |= ATH9K_INT_GTT;
			if (isr2 & AR_ISR_S2_CST)
				mask2 |= ATH9K_INT_CST;
2336 2337
			if (isr2 & AR_ISR_S2_TSFOOR)
				mask2 |= ATH9K_INT_TSFOOR;
2338 2339 2340 2341 2342 2343 2344 2345 2346 2347
		}

		isr = REG_READ(ah, AR_ISR_RAC);
		if (isr == 0xffffffff) {
			*masked = 0;
			return false;
		}

		*masked = isr & ATH9K_INT_COMMON;

S
Sujith 已提交
2348
		if (ah->config.rx_intr_mitigation) {
2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362
			if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
				*masked |= ATH9K_INT_RX;
		}

		if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
			*masked |= ATH9K_INT_RX;
		if (isr &
		    (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
		     AR_ISR_TXEOL)) {
			u32 s0_s, s1_s;

			*masked |= ATH9K_INT_TX;

			s0_s = REG_READ(ah, AR_ISR_S0_S);
2363 2364
			ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
			ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2365 2366

			s1_s = REG_READ(ah, AR_ISR_S1_S);
2367 2368
			ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
			ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2369 2370 2371
		}

		if (isr & AR_ISR_RXORN) {
2372 2373
			ath_print(common, ATH_DBG_INTERRUPT,
				  "receive FIFO overrun interrupt\n");
2374 2375 2376
		}

		if (!AR_SREV_9100(ah)) {
2377
			if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2378 2379 2380 2381 2382 2383 2384 2385
				u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
				if (isr5 & AR_ISR_S5_TIM_TIMER)
					*masked |= ATH9K_INT_TIM_TIMER;
			}
		}

		*masked |= mask2;
	}
S
Sujith 已提交
2386

2387 2388
	if (AR_SREV_9100(ah))
		return true;
S
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2389

2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406
	if (isr & AR_ISR_GENTMR) {
		u32 s5_s;

		s5_s = REG_READ(ah, AR_ISR_S5_S);
		if (isr & AR_ISR_GENTMR) {
			ah->intr_gen_timer_trigger =
				MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);

			ah->intr_gen_timer_thresh =
				MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);

			if (ah->intr_gen_timer_trigger)
				*masked |= ATH9K_INT_GENTIMER;

		}
	}

2407 2408 2409 2410 2411 2412 2413 2414
	if (sync_cause) {
		fatal_int =
			(sync_cause &
			 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
			? true : false;

		if (fatal_int) {
			if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2415 2416
				ath_print(common, ATH_DBG_ANY,
					  "received PCI FATAL interrupt\n");
2417 2418
			}
			if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2419 2420
				ath_print(common, ATH_DBG_ANY,
					  "received PCI PERR interrupt\n");
2421
			}
2422
			*masked |= ATH9K_INT_FATAL;
2423 2424
		}
		if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2425 2426
			ath_print(common, ATH_DBG_INTERRUPT,
				  "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2427 2428 2429 2430 2431
			REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
			REG_WRITE(ah, AR_RC, 0);
			*masked |= ATH9K_INT_FATAL;
		}
		if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2432 2433
			ath_print(common, ATH_DBG_INTERRUPT,
				  "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2434 2435 2436 2437 2438
		}

		REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
		(void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
	}
S
Sujith 已提交
2439

2440 2441
	return true;
}
2442
EXPORT_SYMBOL(ath9k_hw_getisr);
2443

2444
enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2445
{
2446
	enum ath9k_int omask = ah->imask;
2447
	u32 mask, mask2;
2448
	struct ath9k_hw_capabilities *pCap = &ah->caps;
2449
	struct ath_common *common = ath9k_hw_common(ah);
2450

2451
	ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2452 2453

	if (omask & ATH9K_INT_GLOBAL) {
2454
		ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469
		REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
		(void) REG_READ(ah, AR_IER);
		if (!AR_SREV_9100(ah)) {
			REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
			(void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);

			REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
			(void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
		}
	}

	mask = ints & ATH9K_INT_COMMON;
	mask2 = 0;

	if (ints & ATH9K_INT_TX) {
2470
		if (ah->txok_interrupt_mask)
2471
			mask |= AR_IMR_TXOK;
2472
		if (ah->txdesc_interrupt_mask)
2473
			mask |= AR_IMR_TXDESC;
2474
		if (ah->txerr_interrupt_mask)
2475
			mask |= AR_IMR_TXERR;
2476
		if (ah->txeol_interrupt_mask)
2477 2478 2479 2480
			mask |= AR_IMR_TXEOL;
	}
	if (ints & ATH9K_INT_RX) {
		mask |= AR_IMR_RXERR;
S
Sujith 已提交
2481
		if (ah->config.rx_intr_mitigation)
2482 2483 2484
			mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
		else
			mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2485
		if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497
			mask |= AR_IMR_GENTMR;
	}

	if (ints & (ATH9K_INT_BMISC)) {
		mask |= AR_IMR_BCNMISC;
		if (ints & ATH9K_INT_TIM)
			mask2 |= AR_IMR_S2_TIM;
		if (ints & ATH9K_INT_DTIM)
			mask2 |= AR_IMR_S2_DTIM;
		if (ints & ATH9K_INT_DTIMSYNC)
			mask2 |= AR_IMR_S2_DTIMSYNC;
		if (ints & ATH9K_INT_CABEND)
2498 2499 2500
			mask2 |= AR_IMR_S2_CABEND;
		if (ints & ATH9K_INT_TSFOOR)
			mask2 |= AR_IMR_S2_TSFOOR;
2501 2502 2503 2504 2505 2506 2507 2508 2509 2510
	}

	if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
		mask |= AR_IMR_BCNMISC;
		if (ints & ATH9K_INT_GTT)
			mask2 |= AR_IMR_S2_GTT;
		if (ints & ATH9K_INT_CST)
			mask2 |= AR_IMR_S2_CST;
	}

2511
	ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
2512
	REG_WRITE(ah, AR_IMR, mask);
2513 2514 2515 2516 2517
	ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
			   AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
			   AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
	ah->imrs2_reg |= mask2;
	REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
2518

2519
	if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2520 2521 2522 2523 2524 2525 2526
		if (ints & ATH9K_INT_TIM_TIMER)
			REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
		else
			REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
	}

	if (ints & ATH9K_INT_GLOBAL) {
2527
		ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539
		REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
		if (!AR_SREV_9100(ah)) {
			REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
				  AR_INTR_MAC_IRQ);
			REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);


			REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
				  AR_INTR_SYNC_DEFAULT);
			REG_WRITE(ah, AR_INTR_SYNC_MASK,
				  AR_INTR_SYNC_DEFAULT);
		}
2540 2541
		ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
			  REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
2542 2543 2544 2545
	}

	return omask;
}
2546
EXPORT_SYMBOL(ath9k_hw_set_interrupts);
2547

S
Sujith 已提交
2548 2549 2550 2551
/*******************/
/* Beacon Handling */
/*******************/

2552
void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2553 2554 2555
{
	int flags = 0;

2556
	ah->beacon_interval = beacon_period;
2557

2558
	switch (ah->opmode) {
2559 2560
	case NL80211_IFTYPE_STATION:
	case NL80211_IFTYPE_MONITOR:
2561 2562 2563 2564 2565
		REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
		REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
		REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
		flags |= AR_TBTT_TIMER_EN;
		break;
2566
	case NL80211_IFTYPE_ADHOC:
2567
	case NL80211_IFTYPE_MESH_POINT:
2568 2569 2570 2571
		REG_SET_BIT(ah, AR_TXCFG,
			    AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
		REG_WRITE(ah, AR_NEXT_NDP_TIMER,
			  TU_TO_USEC(next_beacon +
2572 2573
				     (ah->atim_window ? ah->
				      atim_window : 1)));
2574
		flags |= AR_NDP_TIMER_EN;
2575
	case NL80211_IFTYPE_AP:
2576 2577 2578
		REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
		REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
			  TU_TO_USEC(next_beacon -
2579
				     ah->config.
2580
				     dma_beacon_response_time));
2581 2582
		REG_WRITE(ah, AR_NEXT_SWBA,
			  TU_TO_USEC(next_beacon -
2583
				     ah->config.
2584
				     sw_beacon_response_time));
2585 2586 2587
		flags |=
			AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
		break;
2588
	default:
2589 2590 2591
		ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
			  "%s: unsupported opmode: %d\n",
			  __func__, ah->opmode);
2592 2593
		return;
		break;
2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607
	}

	REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
	REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
	REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
	REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));

	beacon_period &= ~ATH9K_BEACON_ENA;
	if (beacon_period & ATH9K_BEACON_RESET_TSF) {
		ath9k_hw_reset_tsf(ah);
	}

	REG_SET_BIT(ah, AR_TIMER_MODE, flags);
}
2608
EXPORT_SYMBOL(ath9k_hw_beaconinit);
2609

2610
void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
S
Sujith 已提交
2611
				    const struct ath9k_beacon_state *bs)
2612 2613
{
	u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2614
	struct ath9k_hw_capabilities *pCap = &ah->caps;
2615
	struct ath_common *common = ath9k_hw_common(ah);
2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640

	REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));

	REG_WRITE(ah, AR_BEACON_PERIOD,
		  TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
	REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
		  TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));

	REG_RMW_FIELD(ah, AR_RSSI_THR,
		      AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);

	beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;

	if (bs->bs_sleepduration > beaconintval)
		beaconintval = bs->bs_sleepduration;

	dtimperiod = bs->bs_dtimperiod;
	if (bs->bs_sleepduration > dtimperiod)
		dtimperiod = bs->bs_sleepduration;

	if (beaconintval == dtimperiod)
		nextTbtt = bs->bs_nextdtim;
	else
		nextTbtt = bs->bs_nexttbtt;

2641 2642 2643 2644
	ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
	ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
	ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
	ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
2645

S
Sujith 已提交
2646 2647 2648
	REG_WRITE(ah, AR_NEXT_DTIM,
		  TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
	REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
2649

S
Sujith 已提交
2650 2651 2652
	REG_WRITE(ah, AR_SLEEP1,
		  SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
		  | AR_SLEEP1_ASSUME_DTIM);
2653

S
Sujith 已提交
2654 2655 2656 2657
	if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
		beacontimeout = (BEACON_TIMEOUT_VAL << 3);
	else
		beacontimeout = MIN_BEACON_TIMEOUT_VAL;
2658

S
Sujith 已提交
2659 2660
	REG_WRITE(ah, AR_SLEEP2,
		  SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2661

S
Sujith 已提交
2662 2663
	REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
	REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
2664

S
Sujith 已提交
2665 2666 2667
	REG_SET_BIT(ah, AR_TIMER_MODE,
		    AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
		    AR_DTIM_TIMER_EN);
2668

2669 2670
	/* TSF Out of Range Threshold */
	REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2671
}
2672
EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2673

S
Sujith 已提交
2674 2675 2676 2677
/*******************/
/* HW Capabilities */
/*******************/

2678
int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2679
{
2680
	struct ath9k_hw_capabilities *pCap = &ah->caps;
2681
	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2682
	struct ath_common *common = ath9k_hw_common(ah);
2683
	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
2684

S
Sujith 已提交
2685
	u16 capField = 0, eeval;
2686

S
Sujith 已提交
2687
	eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2688
	regulatory->current_rd = eeval;
2689

S
Sujith 已提交
2690
	eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
2691 2692
	if (AR_SREV_9285_10_OR_LATER(ah))
		eeval |= AR9285_RDEXT_DEFAULT;
2693
	regulatory->current_rd_ext = eeval;
2694

S
Sujith 已提交
2695
	capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
S
Sujith 已提交
2696

2697
	if (ah->opmode != NL80211_IFTYPE_AP &&
2698
	    ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2699 2700 2701 2702 2703
		if (regulatory->current_rd == 0x64 ||
		    regulatory->current_rd == 0x65)
			regulatory->current_rd += 5;
		else if (regulatory->current_rd == 0x41)
			regulatory->current_rd = 0x43;
2704 2705
		ath_print(common, ATH_DBG_REGULATORY,
			  "regdomain mapped to 0x%x\n", regulatory->current_rd);
S
Sujith 已提交
2706
	}
2707

S
Sujith 已提交
2708
	eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2709 2710 2711 2712 2713 2714
	if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
		ath_print(common, ATH_DBG_FATAL,
			  "no band has been marked as supported in EEPROM.\n");
		return -EINVAL;
	}

S
Sujith 已提交
2715
	bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
2716

S
Sujith 已提交
2717 2718
	if (eeval & AR5416_OPFLAGS_11A) {
		set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2719
		if (ah->config.ht_enable) {
S
Sujith 已提交
2720 2721 2722 2723 2724 2725 2726 2727 2728
			if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
				set_bit(ATH9K_MODE_11NA_HT20,
					pCap->wireless_modes);
			if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
				set_bit(ATH9K_MODE_11NA_HT40PLUS,
					pCap->wireless_modes);
				set_bit(ATH9K_MODE_11NA_HT40MINUS,
					pCap->wireless_modes);
			}
2729 2730 2731
		}
	}

S
Sujith 已提交
2732 2733
	if (eeval & AR5416_OPFLAGS_11G) {
		set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2734
		if (ah->config.ht_enable) {
S
Sujith 已提交
2735 2736 2737 2738 2739 2740 2741 2742 2743 2744
			if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
				set_bit(ATH9K_MODE_11NG_HT20,
					pCap->wireless_modes);
			if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
				set_bit(ATH9K_MODE_11NG_HT40PLUS,
					pCap->wireless_modes);
				set_bit(ATH9K_MODE_11NG_HT40MINUS,
					pCap->wireless_modes);
			}
		}
2745
	}
S
Sujith 已提交
2746

S
Sujith 已提交
2747
	pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2748 2749 2750 2751
	/*
	 * For AR9271 we will temporarilly uses the rx chainmax as read from
	 * the EEPROM.
	 */
2752
	if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2753 2754 2755
	    !(eeval & AR5416_OPFLAGS_11A) &&
	    !(AR_SREV_9271(ah)))
		/* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2756 2757
		pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
	else
2758
		/* Use rx_chainmask from EEPROM. */
2759
		pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2760

2761
	if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2762
		ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2763

S
Sujith 已提交
2764 2765
	pCap->low_2ghz_chan = 2312;
	pCap->high_2ghz_chan = 2732;
2766

S
Sujith 已提交
2767 2768
	pCap->low_5ghz_chan = 4920;
	pCap->high_5ghz_chan = 6100;
2769

S
Sujith 已提交
2770 2771 2772
	pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
	pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
	pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
2773

S
Sujith 已提交
2774 2775 2776
	pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
	pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
	pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
2777

2778
	if (ah->config.ht_enable)
S
Sujith 已提交
2779 2780 2781
		pCap->hw_caps |= ATH9K_HW_CAP_HT;
	else
		pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2782

S
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2783 2784 2785 2786
	pCap->hw_caps |= ATH9K_HW_CAP_GTT;
	pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
	pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
	pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
2787

S
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2788 2789 2790 2791 2792
	if (capField & AR_EEPROM_EEPCAP_MAXQCU)
		pCap->total_queues =
			MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
	else
		pCap->total_queues = ATH9K_NUM_TX_QUEUES;
2793

S
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2794 2795 2796 2797 2798
	if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
		pCap->keycache_size =
			1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
	else
		pCap->keycache_size = AR_KEYTABLE_SIZE;
2799

S
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2800
	pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
2801 2802 2803 2804 2805

	if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
		pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
	else
		pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
2806

2807 2808 2809
	if (AR_SREV_9271(ah))
		pCap->num_gpio_pins = AR9271_NUM_GPIO;
	else if (AR_SREV_9285_10_OR_LATER(ah))
2810 2811
		pCap->num_gpio_pins = AR9285_NUM_GPIO;
	else if (AR_SREV_9280_10_OR_LATER(ah))
S
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2812 2813 2814
		pCap->num_gpio_pins = AR928X_NUM_GPIO;
	else
		pCap->num_gpio_pins = AR_NUM_GPIO;
2815

S
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2816 2817 2818 2819 2820
	if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
		pCap->hw_caps |= ATH9K_HW_CAP_CST;
		pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
	} else {
		pCap->rts_aggr_limit = (8 * 1024);
2821 2822
	}

S
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2823 2824
	pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;

2825
#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2826 2827 2828 2829 2830 2831
	ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
	if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
		ah->rfkill_gpio =
			MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
		ah->rfkill_polarity =
			MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
S
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2832 2833

		pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2834
	}
S
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2835
#endif
2836 2837 2838 2839
	if (AR_SREV_9271(ah))
		pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
	else
		pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2840

2841
	if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
S
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2842 2843 2844
		pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
	else
		pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2845

2846
	if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
S
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2847 2848 2849 2850 2851
		pCap->reg_cap =
			AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
			AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
			AR_EEPROM_EEREGCAP_EN_KK_U2 |
			AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
2852
	} else {
S
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2853 2854 2855
		pCap->reg_cap =
			AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
			AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
2856 2857
	}

2858 2859 2860 2861
	/* Advertise midband for AR5416 with FCC midband set in eeprom */
	if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
	    AR_SREV_5416(ah))
		pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
S
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2862 2863

	pCap->num_antcfg_5ghz =
S
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2864
		ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
S
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2865
	pCap->num_antcfg_2ghz =
S
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2866
		ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
2867

2868
	if (AR_SREV_9280_10_OR_LATER(ah) &&
2869
	    ath9k_hw_btcoex_supported(ah)) {
2870 2871
		btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
		btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
2872

2873
		if (AR_SREV_9285(ah)) {
2874 2875
			btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
			btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
2876
		} else {
2877
			btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
2878
		}
2879
	} else {
2880
		btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
2881
	}
2882

2883
	if (AR_SREV_9300_20_OR_LATER(ah)) {
2884
		pCap->hw_caps |= ATH9K_HW_CAP_EDMA;
2885 2886 2887 2888
		pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
		pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
		pCap->rx_status_len = sizeof(struct ar9003_rxs);
	}
2889

2890
	return 0;
2891 2892
}

2893
bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
S
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2894
			    u32 capability, u32 *result)
2895
{
2896
	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
S
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2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914
	switch (type) {
	case ATH9K_CAP_CIPHER:
		switch (capability) {
		case ATH9K_CIPHER_AES_CCM:
		case ATH9K_CIPHER_AES_OCB:
		case ATH9K_CIPHER_TKIP:
		case ATH9K_CIPHER_WEP:
		case ATH9K_CIPHER_MIC:
		case ATH9K_CIPHER_CLR:
			return true;
		default:
			return false;
		}
	case ATH9K_CAP_TKIP_MIC:
		switch (capability) {
		case 0:
			return true;
		case 1:
2915
			return (ah->sta_id1_defaults &
S
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2916 2917 2918 2919
				AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
			false;
		}
	case ATH9K_CAP_TKIP_SPLIT:
2920
		return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
S
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2921 2922 2923 2924 2925 2926 2927 2928 2929
			false : true;
	case ATH9K_CAP_MCAST_KEYSRCH:
		switch (capability) {
		case 0:
			return true;
		case 1:
			if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
				return false;
			} else {
2930
				return (ah->sta_id1_defaults &
S
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2931 2932 2933 2934 2935 2936 2937 2938 2939 2940
					AR_STA_ID1_MCAST_KSRCH) ? true :
					false;
			}
		}
		return false;
	case ATH9K_CAP_TXPOW:
		switch (capability) {
		case 0:
			return 0;
		case 1:
2941
			*result = regulatory->power_limit;
S
Sujith 已提交
2942 2943
			return 0;
		case 2:
2944
			*result = regulatory->max_power_level;
S
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2945 2946
			return 0;
		case 3:
2947
			*result = regulatory->tp_scale;
S
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2948 2949 2950
			return 0;
		}
		return false;
2951 2952 2953 2954
	case ATH9K_CAP_DS:
		return (AR_SREV_9280_20_OR_LATER(ah) &&
			(ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
			? false : true;
S
Sujith 已提交
2955 2956
	default:
		return false;
2957 2958
	}
}
2959
EXPORT_SYMBOL(ath9k_hw_getcapability);
2960

2961
bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
S
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2962
			    u32 capability, u32 setting, int *status)
2963
{
S
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2964 2965 2966
	switch (type) {
	case ATH9K_CAP_TKIP_MIC:
		if (setting)
2967
			ah->sta_id1_defaults |=
S
Sujith 已提交
2968 2969
				AR_STA_ID1_CRPT_MIC_ENABLE;
		else
2970
			ah->sta_id1_defaults &=
S
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2971 2972 2973 2974
				~AR_STA_ID1_CRPT_MIC_ENABLE;
		return true;
	case ATH9K_CAP_MCAST_KEYSRCH:
		if (setting)
2975
			ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
S
Sujith 已提交
2976
		else
2977
			ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
S
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2978 2979 2980
		return true;
	default:
		return false;
2981 2982
	}
}
2983
EXPORT_SYMBOL(ath9k_hw_setcapability);
2984

S
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2985 2986 2987
/****************************/
/* GPIO / RFKILL / Antennae */
/****************************/
2988

2989
static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
S
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2990 2991 2992 2993
					 u32 gpio, u32 type)
{
	int addr;
	u32 gpio_shift, tmp;
2994

S
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2995 2996 2997 2998 2999 3000
	if (gpio > 11)
		addr = AR_GPIO_OUTPUT_MUX3;
	else if (gpio > 5)
		addr = AR_GPIO_OUTPUT_MUX2;
	else
		addr = AR_GPIO_OUTPUT_MUX1;
3001

S
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3002
	gpio_shift = (gpio % 6) * 5;
3003

S
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3004 3005 3006 3007
	if (AR_SREV_9280_20_OR_LATER(ah)
	    || (addr != AR_GPIO_OUTPUT_MUX1)) {
		REG_RMW(ah, addr, (type << gpio_shift),
			(0x1f << gpio_shift));
3008
	} else {
S
Sujith 已提交
3009 3010 3011 3012 3013
		tmp = REG_READ(ah, addr);
		tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
		tmp &= ~(0x1f << gpio_shift);
		tmp |= (type << gpio_shift);
		REG_WRITE(ah, addr, tmp);
3014 3015 3016
	}
}

3017
void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3018
{
S
Sujith 已提交
3019
	u32 gpio_shift;
3020

3021
	BUG_ON(gpio >= ah->caps.num_gpio_pins);
3022

S
Sujith 已提交
3023
	gpio_shift = gpio << 1;
3024

S
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3025 3026 3027 3028
	REG_RMW(ah,
		AR_GPIO_OE_OUT,
		(AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
		(AR_GPIO_OE_OUT_DRV << gpio_shift));
3029
}
3030
EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
3031

3032
u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3033
{
3034 3035 3036
#define MS_REG_READ(x, y) \
	(MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))

3037
	if (gpio >= ah->caps.num_gpio_pins)
S
Sujith 已提交
3038
		return 0xffffffff;
3039

3040 3041 3042
	if (AR_SREV_9300_20_OR_LATER(ah))
		return MS_REG_READ(AR9300, gpio) != 0;
	else if (AR_SREV_9271(ah))
3043 3044
		return MS_REG_READ(AR9271, gpio) != 0;
	else if (AR_SREV_9287_10_OR_LATER(ah))
3045 3046
		return MS_REG_READ(AR9287, gpio) != 0;
	else if (AR_SREV_9285_10_OR_LATER(ah))
3047 3048 3049 3050 3051
		return MS_REG_READ(AR9285, gpio) != 0;
	else if (AR_SREV_9280_10_OR_LATER(ah))
		return MS_REG_READ(AR928X, gpio) != 0;
	else
		return MS_REG_READ(AR, gpio) != 0;
3052
}
3053
EXPORT_SYMBOL(ath9k_hw_gpio_get);
3054

3055
void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
S
Sujith 已提交
3056
			 u32 ah_signal_type)
3057
{
S
Sujith 已提交
3058
	u32 gpio_shift;
3059

S
Sujith 已提交
3060
	ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3061

S
Sujith 已提交
3062
	gpio_shift = 2 * gpio;
3063

S
Sujith 已提交
3064 3065 3066 3067
	REG_RMW(ah,
		AR_GPIO_OE_OUT,
		(AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
		(AR_GPIO_OE_OUT_DRV << gpio_shift));
3068
}
3069
EXPORT_SYMBOL(ath9k_hw_cfg_output);
3070

3071
void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3072
{
3073 3074 3075
	if (AR_SREV_9271(ah))
		val = ~val;

S
Sujith 已提交
3076 3077
	REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
		AR_GPIO_BIT(gpio));
3078
}
3079
EXPORT_SYMBOL(ath9k_hw_set_gpio);
3080

3081
u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3082
{
S
Sujith 已提交
3083
	return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3084
}
3085
EXPORT_SYMBOL(ath9k_hw_getdefantenna);
3086

3087
void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3088
{
S
Sujith 已提交
3089
	REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3090
}
3091
EXPORT_SYMBOL(ath9k_hw_setantenna);
3092

S
Sujith 已提交
3093 3094 3095 3096
/*********************/
/* General Operation */
/*********************/

3097
u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3098
{
S
Sujith 已提交
3099 3100
	u32 bits = REG_READ(ah, AR_RX_FILTER);
	u32 phybits = REG_READ(ah, AR_PHY_ERR);
3101

S
Sujith 已提交
3102 3103 3104 3105
	if (phybits & AR_PHY_ERR_RADAR)
		bits |= ATH9K_RX_FILTER_PHYRADAR;
	if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
		bits |= ATH9K_RX_FILTER_PHYERR;
S
Sujith 已提交
3106

S
Sujith 已提交
3107
	return bits;
3108
}
3109
EXPORT_SYMBOL(ath9k_hw_getrxfilter);
3110

3111
void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3112
{
S
Sujith 已提交
3113
	u32 phybits;
3114

S
Sujith 已提交
3115 3116
	REG_WRITE(ah, AR_RX_FILTER, bits);

S
Sujith 已提交
3117 3118 3119 3120 3121 3122
	phybits = 0;
	if (bits & ATH9K_RX_FILTER_PHYRADAR)
		phybits |= AR_PHY_ERR_RADAR;
	if (bits & ATH9K_RX_FILTER_PHYERR)
		phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
	REG_WRITE(ah, AR_PHY_ERR, phybits);
3123

S
Sujith 已提交
3124 3125 3126 3127 3128 3129 3130
	if (phybits)
		REG_WRITE(ah, AR_RXCFG,
			  REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
	else
		REG_WRITE(ah, AR_RXCFG,
			  REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
}
3131
EXPORT_SYMBOL(ath9k_hw_setrxfilter);
3132

3133
bool ath9k_hw_phy_disable(struct ath_hw *ah)
S
Sujith 已提交
3134
{
3135 3136 3137 3138 3139
	if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
		return false;

	ath9k_hw_init_pll(ah, NULL);
	return true;
S
Sujith 已提交
3140
}
3141
EXPORT_SYMBOL(ath9k_hw_phy_disable);
3142

3143
bool ath9k_hw_disable(struct ath_hw *ah)
S
Sujith 已提交
3144
{
3145
	if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
S
Sujith 已提交
3146
		return false;
3147

3148 3149 3150 3151 3152
	if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
		return false;

	ath9k_hw_init_pll(ah, NULL);
	return true;
3153
}
3154
EXPORT_SYMBOL(ath9k_hw_disable);
3155

3156
void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3157
{
3158
	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3159
	struct ath9k_channel *chan = ah->curchan;
3160
	struct ieee80211_channel *channel = chan->chan;
3161

3162
	regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
3163

3164
	ah->eep_ops->set_txpower(ah, chan,
3165
				 ath9k_regd_get_ctl(regulatory, chan),
3166 3167 3168
				 channel->max_antenna_gain * 2,
				 channel->max_power * 2,
				 min((u32) MAX_RATE_POWER,
3169
				 (u32) regulatory->power_limit));
3170
}
3171
EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
3172

3173
void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3174
{
3175
	memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
3176
}
3177
EXPORT_SYMBOL(ath9k_hw_setmac);
3178

3179
void ath9k_hw_setopmode(struct ath_hw *ah)
3180
{
3181
	ath9k_hw_set_operating_mode(ah, ah->opmode);
3182
}
3183
EXPORT_SYMBOL(ath9k_hw_setopmode);
3184

3185
void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3186
{
S
Sujith 已提交
3187 3188
	REG_WRITE(ah, AR_MCAST_FIL0, filter0);
	REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3189
}
3190
EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
3191

3192
void ath9k_hw_write_associd(struct ath_hw *ah)
3193
{
3194 3195 3196 3197 3198
	struct ath_common *common = ath9k_hw_common(ah);

	REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
	REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
		  ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3199
}
3200
EXPORT_SYMBOL(ath9k_hw_write_associd);
3201

3202
u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3203
{
S
Sujith 已提交
3204
	u64 tsf;
3205

S
Sujith 已提交
3206 3207
	tsf = REG_READ(ah, AR_TSF_U32);
	tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3208

S
Sujith 已提交
3209 3210
	return tsf;
}
3211
EXPORT_SYMBOL(ath9k_hw_gettsf64);
3212

3213
void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3214 3215
{
	REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
A
Alina Friedrichsen 已提交
3216
	REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3217
}
3218
EXPORT_SYMBOL(ath9k_hw_settsf64);
3219

3220
void ath9k_hw_reset_tsf(struct ath_hw *ah)
S
Sujith 已提交
3221
{
3222 3223
	if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
			   AH_TSF_WRITE_TIMEOUT))
3224 3225
		ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
			  "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3226

S
Sujith 已提交
3227 3228
	REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
}
3229
EXPORT_SYMBOL(ath9k_hw_reset_tsf);
3230

S
Sujith 已提交
3231
void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
S
Sujith 已提交
3232 3233
{
	if (setting)
3234
		ah->misc_mode |= AR_PCU_TX_ADD_TSF;
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	else
3236
		ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
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}
3238
EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
3239

3240 3241 3242 3243 3244 3245 3246 3247 3248 3249 3250 3251 3252 3253 3254
/*
 *  Extend 15-bit time stamp from rx descriptor to
 *  a full 64-bit TSF using the current h/w TSF.
*/
u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
{
	u64 tsf;

	tsf = ath9k_hw_gettsf64(ah);
	if ((tsf & 0x7fff) < rstamp)
		tsf -= 0x8000;
	return (tsf & ~0x7fff) | rstamp;
}
EXPORT_SYMBOL(ath9k_hw_extend_tsf);

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void ath9k_hw_set11nmac2040(struct ath_hw *ah)
S
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3256
{
L
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3257
	struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
S
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3258 3259
	u32 macmode;

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3260
	if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
S
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3261 3262 3263
		macmode = AR_2040_JOINED_RX_CLEAR;
	else
		macmode = 0;
3264

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3265
	REG_WRITE(ah, AR_2040_MODE, macmode);
3266
}
3267 3268 3269 3270 3271 3272 3273 3274 3275 3276 3277 3278 3279 3280 3281 3282 3283 3284 3285 3286 3287 3288 3289 3290 3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305 3306 3307 3308 3309 3310 3311 3312

/* HW Generic timers configuration */

static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
{
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
	{AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
				AR_NDP2_TIMER_MODE, 0x0002},
	{AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
				AR_NDP2_TIMER_MODE, 0x0004},
	{AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
				AR_NDP2_TIMER_MODE, 0x0008},
	{AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
				AR_NDP2_TIMER_MODE, 0x0010},
	{AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
				AR_NDP2_TIMER_MODE, 0x0020},
	{AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
				AR_NDP2_TIMER_MODE, 0x0040},
	{AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
				AR_NDP2_TIMER_MODE, 0x0080}
};

/* HW generic timer primitives */

/* compute and clear index of rightmost 1 */
static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
{
	u32 b;

	b = *mask;
	b &= (0-b);
	*mask &= ~b;
	b *= debruijn32;
	b >>= 27;

	return timer_table->gen_timer_index[b];
}

3313
u32 ath9k_hw_gettsf32(struct ath_hw *ah)
3314 3315 3316
{
	return REG_READ(ah, AR_TSF_L32);
}
3317
EXPORT_SYMBOL(ath9k_hw_gettsf32);
3318 3319 3320 3321 3322 3323 3324 3325 3326 3327 3328 3329 3330

struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
					  void (*trigger)(void *),
					  void (*overflow)(void *),
					  void *arg,
					  u8 timer_index)
{
	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
	struct ath_gen_timer *timer;

	timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);

	if (timer == NULL) {
3331 3332 3333
		ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
			  "Failed to allocate memory"
			  "for hw timer[%d]\n", timer_index);
3334 3335 3336 3337 3338 3339 3340 3341 3342 3343 3344 3345
		return NULL;
	}

	/* allocate a hardware generic timer slot */
	timer_table->timers[timer_index] = timer;
	timer->index = timer_index;
	timer->trigger = trigger;
	timer->overflow = overflow;
	timer->arg = arg;

	return timer;
}
3346
EXPORT_SYMBOL(ath_gen_timer_alloc);
3347

3348 3349 3350 3351
void ath9k_hw_gen_timer_start(struct ath_hw *ah,
			      struct ath_gen_timer *timer,
			      u32 timer_next,
			      u32 timer_period)
3352 3353 3354 3355 3356 3357 3358 3359 3360 3361
{
	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
	u32 tsf;

	BUG_ON(!timer_period);

	set_bit(timer->index, &timer_table->timer_mask.timer_bits);

	tsf = ath9k_hw_gettsf32(ah);

3362 3363 3364
	ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
		  "curent tsf %x period %x"
		  "timer_next %x\n", tsf, timer_period, timer_next);
3365 3366 3367 3368 3369 3370 3371 3372 3373 3374 3375 3376 3377 3378 3379 3380 3381 3382 3383 3384 3385 3386 3387

	/*
	 * Pull timer_next forward if the current TSF already passed it
	 * because of software latency
	 */
	if (timer_next < tsf)
		timer_next = tsf + timer_period;

	/*
	 * Program generic timer registers
	 */
	REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
		 timer_next);
	REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
		  timer_period);
	REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
		    gen_tmr_configuration[timer->index].mode_mask);

	/* Enable both trigger and thresh interrupt masks */
	REG_SET_BIT(ah, AR_IMR_S5,
		(SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
		SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
}
3388
EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3389

3390
void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3391 3392 3393 3394 3395 3396 3397 3398 3399 3400 3401 3402 3403 3404 3405 3406 3407 3408 3409
{
	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;

	if ((timer->index < AR_FIRST_NDP_TIMER) ||
		(timer->index >= ATH_MAX_GEN_TIMER)) {
		return;
	}

	/* Clear generic timer enable bits. */
	REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
			gen_tmr_configuration[timer->index].mode_mask);

	/* Disable both trigger and thresh interrupt masks */
	REG_CLR_BIT(ah, AR_IMR_S5,
		(SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
		SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));

	clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
}
3410
EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3411 3412 3413 3414 3415 3416 3417 3418 3419

void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
{
	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;

	/* free the hardware generic timer slot */
	timer_table->timers[timer->index] = NULL;
	kfree(timer);
}
3420
EXPORT_SYMBOL(ath_gen_timer_free);
3421 3422 3423 3424 3425 3426 3427 3428

/*
 * Generic Timer Interrupts handling
 */
void ath_gen_timer_isr(struct ath_hw *ah)
{
	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
	struct ath_gen_timer *timer;
3429
	struct ath_common *common = ath9k_hw_common(ah);
3430 3431 3432 3433 3434 3435 3436 3437 3438 3439 3440 3441 3442 3443
	u32 trigger_mask, thresh_mask, index;

	/* get hardware generic timer interrupt status */
	trigger_mask = ah->intr_gen_timer_trigger;
	thresh_mask = ah->intr_gen_timer_thresh;
	trigger_mask &= timer_table->timer_mask.val;
	thresh_mask &= timer_table->timer_mask.val;

	trigger_mask &= ~thresh_mask;

	while (thresh_mask) {
		index = rightmost_index(timer_table, &thresh_mask);
		timer = timer_table->timers[index];
		BUG_ON(!timer);
3444 3445
		ath_print(common, ATH_DBG_HWTIMER,
			  "TSF overflow for Gen timer %d\n", index);
3446 3447 3448 3449 3450 3451 3452
		timer->overflow(timer->arg);
	}

	while (trigger_mask) {
		index = rightmost_index(timer_table, &trigger_mask);
		timer = timer_table->timers[index];
		BUG_ON(!timer);
3453 3454
		ath_print(common, ATH_DBG_HWTIMER,
			  "Gen timer[%d] trigger\n", index);
3455 3456 3457
		timer->trigger(timer->arg);
	}
}
3458
EXPORT_SYMBOL(ath_gen_timer_isr);
3459

3460 3461 3462 3463 3464 3465 3466 3467 3468 3469
/********/
/* HTC  */
/********/

void ath9k_hw_htc_resetinit(struct ath_hw *ah)
{
	ah->htc_reset_init = true;
}
EXPORT_SYMBOL(ath9k_hw_htc_resetinit);

3470 3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481
static struct {
	u32 version;
	const char * name;
} ath_mac_bb_names[] = {
	/* Devices with external radios */
	{ AR_SREV_VERSION_5416_PCI,	"5416" },
	{ AR_SREV_VERSION_5416_PCIE,	"5418" },
	{ AR_SREV_VERSION_9100,		"9100" },
	{ AR_SREV_VERSION_9160,		"9160" },
	/* Single-chip solutions */
	{ AR_SREV_VERSION_9280,		"9280" },
	{ AR_SREV_VERSION_9285,		"9285" },
3482 3483
	{ AR_SREV_VERSION_9287,         "9287" },
	{ AR_SREV_VERSION_9271,         "9271" },
3484 3485 3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498 3499 3500
};

/* For devices with external radios */
static struct {
	u16 version;
	const char * name;
} ath_rf_names[] = {
	{ 0,				"5133" },
	{ AR_RAD5133_SREV_MAJOR,	"5133" },
	{ AR_RAD5122_SREV_MAJOR,	"5122" },
	{ AR_RAD2133_SREV_MAJOR,	"2133" },
	{ AR_RAD2122_SREV_MAJOR,	"2122" }
};

/*
 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
 */
3501
static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3502 3503 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517
{
	int i;

	for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
		if (ath_mac_bb_names[i].version == mac_bb_version) {
			return ath_mac_bb_names[i].name;
		}
	}

	return "????";
}

/*
 * Return the RF name. "????" is returned if the RF is unknown.
 * Used for devices with external radios.
 */
3518
static const char *ath9k_hw_rf_name(u16 rf_version)
3519 3520 3521 3522 3523 3524 3525 3526 3527 3528 3529
{
	int i;

	for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
		if (ath_rf_names[i].version == rf_version) {
			return ath_rf_names[i].name;
		}
	}

	return "????";
}
3530 3531 3532 3533 3534 3535 3536 3537 3538 3539 3540 3541 3542 3543 3544 3545 3546 3547 3548 3549 3550 3551 3552 3553 3554

void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
{
	int used;

	/* chipsets >= AR9280 are single-chip */
	if (AR_SREV_9280_10_OR_LATER(ah)) {
		used = snprintf(hw_name, len,
			       "Atheros AR%s Rev:%x",
			       ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
			       ah->hw_version.macRev);
	}
	else {
		used = snprintf(hw_name, len,
			       "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
			       ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
			       ah->hw_version.macRev,
			       ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
						AR_RADIO_SREV_MAJOR)),
			       ah->hw_version.phyRev);
	}

	hw_name[used] = '\0';
}
EXPORT_SYMBOL(ath9k_hw_name);
3555 3556 3557 3558 3559 3560 3561 3562 3563 3564 3565 3566

/* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */
static void ar9002_hw_attach_ops(struct ath_hw *ah)
{
	struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
	struct ath_hw_ops *ops = ath9k_hw_ops(ah);

	priv_ops->init_cal_settings = ar9002_hw_init_cal_settings;
	priv_ops->init_mode_regs = ar9002_hw_init_mode_regs;
	priv_ops->macversion_supported = ar9002_hw_macversion_supported;

	ops->config_pci_powersave = ar9002_hw_configpcipowersave;
3567

3568
	ar5008_hw_attach_phy_ops(ah);
3569 3570
	if (AR_SREV_9280_10_OR_LATER(ah))
		ar9002_hw_attach_phy_ops(ah);
3571 3572

	ar9002_hw_attach_mac_ops(ah);
3573 3574 3575 3576 3577
}

/* Sets up the AR9003 hardware familiy callbacks */
static void ar9003_hw_attach_ops(struct ath_hw *ah)
{
3578 3579 3580 3581
	struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);

	priv_ops->macversion_supported = ar9003_hw_macversion_supported;

3582
	ar9003_hw_attach_phy_ops(ah);
3583 3584

	ar9003_hw_attach_mac_ops(ah);
3585
}