hw.c 113.6 KB
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/*
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 * Copyright (c) 2008-2009 Atheros Communications Inc.
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 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <linux/io.h>
#include <asm/unaligned.h>

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#include "hw.h"
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#include "rc.h"
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#include "initvals.h"

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#define ATH9K_CLOCK_RATE_CCK		22
#define ATH9K_CLOCK_RATE_5GHZ_OFDM	40
#define ATH9K_CLOCK_RATE_2GHZ_OFDM	44
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static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
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static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
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static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
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			      struct ar5416_eeprom_def *pEepData,
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			      u32 reg, u32 value);
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static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
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/********************/
/* Helper Functions */
/********************/
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static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
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{
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	struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
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	if (!ah->curchan) /* should really check for CCK instead */
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		return clks / ATH9K_CLOCK_RATE_CCK;
	if (conf->channel->band == IEEE80211_BAND_2GHZ)
		return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
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	return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
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}
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static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
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{
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	struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
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	if (conf_is_ht40(conf))
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		return ath9k_hw_mac_usec(ah, clks) / 2;
	else
		return ath9k_hw_mac_usec(ah, clks);
}
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static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
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{
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	struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
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	if (!ah->curchan) /* should really check for CCK instead */
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		return usecs *ATH9K_CLOCK_RATE_CCK;
	if (conf->channel->band == IEEE80211_BAND_2GHZ)
		return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
	return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
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}

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static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
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{
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	struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
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	if (conf_is_ht40(conf))
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		return ath9k_hw_mac_clks(ah, usecs) * 2;
	else
		return ath9k_hw_mac_clks(ah, usecs);
}
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bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
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{
	int i;

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	BUG_ON(timeout < AH_TIME_QUANTUM);

	for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
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		if ((REG_READ(ah, reg) & mask) == val)
			return true;

		udelay(AH_TIME_QUANTUM);
	}
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	ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
		  "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
		  timeout, reg, REG_READ(ah, reg), mask, val);
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	return false;
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}

u32 ath9k_hw_reverse_bits(u32 val, u32 n)
{
	u32 retval;
	int i;

	for (i = 0, retval = 0; i < n; i++) {
		retval = (retval << 1) | (val & 1);
		val >>= 1;
	}
	return retval;
}

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bool ath9k_get_channel_edges(struct ath_hw *ah,
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			     u16 flags, u16 *low,
			     u16 *high)
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{
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	struct ath9k_hw_capabilities *pCap = &ah->caps;
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	if (flags & CHANNEL_5GHZ) {
		*low = pCap->low_5ghz_chan;
		*high = pCap->high_5ghz_chan;
		return true;
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	}
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	if ((flags & CHANNEL_2GHZ)) {
		*low = pCap->low_2ghz_chan;
		*high = pCap->high_2ghz_chan;
		return true;
	}
	return false;
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}

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u16 ath9k_hw_computetxtime(struct ath_hw *ah,
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			   const struct ath_rate_table *rates,
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			   u32 frameLen, u16 rateix,
			   bool shortPreamble)
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{
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	u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
	u32 kbps;
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	kbps = rates->info[rateix].ratekbps;
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	if (kbps == 0)
		return 0;
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	switch (rates->info[rateix].phy) {
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	case WLAN_RC_PHY_CCK:
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		phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
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		if (shortPreamble && rates->info[rateix].short_preamble)
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			phyTime >>= 1;
		numBits = frameLen << 3;
		txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
		break;
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	case WLAN_RC_PHY_OFDM:
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		if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
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			bitsPerSymbol =	(kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
			numBits = OFDM_PLCP_BITS + (frameLen << 3);
			numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
			txTime = OFDM_SIFS_TIME_QUARTER
				+ OFDM_PREAMBLE_TIME_QUARTER
				+ (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
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		} else if (ah->curchan &&
			   IS_CHAN_HALF_RATE(ah->curchan)) {
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			bitsPerSymbol =	(kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
			numBits = OFDM_PLCP_BITS + (frameLen << 3);
			numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
			txTime = OFDM_SIFS_TIME_HALF +
				OFDM_PREAMBLE_TIME_HALF
				+ (numSymbols * OFDM_SYMBOL_TIME_HALF);
		} else {
			bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
			numBits = OFDM_PLCP_BITS + (frameLen << 3);
			numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
			txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
				+ (numSymbols * OFDM_SYMBOL_TIME);
		}
		break;
	default:
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		ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
			  "Unknown phy %u (rate ix %u)\n",
			  rates->info[rateix].phy, rateix);
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		txTime = 0;
		break;
	}
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	return txTime;
}
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void ath9k_hw_get_channel_centers(struct ath_hw *ah,
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				  struct ath9k_channel *chan,
				  struct chan_centers *centers)
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{
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	int8_t extoff;
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	if (!IS_CHAN_HT40(chan)) {
		centers->ctl_center = centers->ext_center =
			centers->synth_center = chan->channel;
		return;
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	}

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	if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
	    (chan->chanmode == CHANNEL_G_HT40PLUS)) {
		centers->synth_center =
			chan->channel + HT40_CHANNEL_CENTER_SHIFT;
		extoff = 1;
	} else {
		centers->synth_center =
			chan->channel - HT40_CHANNEL_CENTER_SHIFT;
		extoff = -1;
	}
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	centers->ctl_center =
		centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
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	/* 25 MHz spacing is supported by hw but not on upper layers */
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	centers->ext_center =
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		centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
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}

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/******************/
/* Chip Revisions */
/******************/

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static void ath9k_hw_read_revisions(struct ath_hw *ah)
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{
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	u32 val;
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	val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
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	if (val == 0xFF) {
		val = REG_READ(ah, AR_SREV);
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		ah->hw_version.macVersion =
			(val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
		ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
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		ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
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	} else {
		if (!AR_SREV_9100(ah))
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			ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
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		ah->hw_version.macRev = val & AR_SREV_REVISION;
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		if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
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			ah->is_pciexpress = true;
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	}
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}

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static int ath9k_hw_get_radiorev(struct ath_hw *ah)
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{
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	u32 val;
	int i;
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	REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
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	for (i = 0; i < 8; i++)
		REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
	val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
	val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
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	return ath9k_hw_reverse_bits(val, 8);
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}

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/************************************/
/* HW Attach, Detach, Init Routines */
/************************************/

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static void ath9k_hw_disablepcie(struct ath_hw *ah)
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{
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	if (AR_SREV_9100(ah))
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		return;
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	REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
	REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
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	REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
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}

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static bool ath9k_hw_chip_test(struct ath_hw *ah)
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{
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	struct ath_common *common = ath9k_hw_common(ah);
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	u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
	u32 regHold[2];
	u32 patternData[4] = { 0x55555555,
			       0xaaaaaaaa,
			       0x66666666,
			       0x99999999 };
	int i, j;
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	for (i = 0; i < 2; i++) {
		u32 addr = regAddr[i];
		u32 wrData, rdData;
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		regHold[i] = REG_READ(ah, addr);
		for (j = 0; j < 0x100; j++) {
			wrData = (j << 16) | j;
			REG_WRITE(ah, addr, wrData);
			rdData = REG_READ(ah, addr);
			if (rdData != wrData) {
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				ath_print(common, ATH_DBG_FATAL,
					  "address test failed "
					  "addr: 0x%08x - wr:0x%08x != "
					  "rd:0x%08x\n",
					  addr, wrData, rdData);
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				return false;
			}
		}
		for (j = 0; j < 4; j++) {
			wrData = patternData[j];
			REG_WRITE(ah, addr, wrData);
			rdData = REG_READ(ah, addr);
			if (wrData != rdData) {
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				ath_print(common, ATH_DBG_FATAL,
					  "address test failed "
					  "addr: 0x%08x - wr:0x%08x != "
					  "rd:0x%08x\n",
					  addr, wrData, rdData);
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				return false;
			}
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		}
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		REG_WRITE(ah, regAddr[i], regHold[i]);
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	}
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	udelay(100);
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	return true;
}

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static const char *ath9k_hw_devname(u16 devid)
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{
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	switch (devid) {
	case AR5416_DEVID_PCI:
		return "Atheros 5416";
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	case AR5416_DEVID_PCIE:
		return "Atheros 5418";
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	case AR9160_DEVID_PCI:
		return "Atheros 9160";
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	case AR5416_AR9100_DEVID:
		return "Atheros 9100";
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	case AR9280_DEVID_PCI:
	case AR9280_DEVID_PCIE:
		return "Atheros 9280";
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	case AR9285_DEVID_PCIE:
		return "Atheros 9285";
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	case AR5416_DEVID_AR9287_PCI:
	case AR5416_DEVID_AR9287_PCIE:
		return "Atheros 9287";
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	}

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	return NULL;
}
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static void ath9k_hw_init_config(struct ath_hw *ah)
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{
	int i;
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	ah->config.dma_beacon_response_time = 2;
	ah->config.sw_beacon_response_time = 10;
	ah->config.additional_swba_backoff = 0;
	ah->config.ack_6mb = 0x0;
	ah->config.cwm_ignore_extcca = 0;
	ah->config.pcie_powersave_enable = 0;
	ah->config.pcie_clock_req = 0;
	ah->config.pcie_waen = 0;
	ah->config.analog_shiftreg = 1;
	ah->config.ht_enable = 1;
	ah->config.ofdm_trig_low = 200;
	ah->config.ofdm_trig_high = 500;
	ah->config.cck_trig_high = 200;
	ah->config.cck_trig_low = 100;
	ah->config.enable_ani = 1;
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	ah->config.diversity_control = ATH9K_ANT_VARIABLE;
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	ah->config.antenna_switch_swap = 0;
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	for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
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		ah->config.spurchans[i][0] = AR_NO_SPUR;
		ah->config.spurchans[i][1] = AR_NO_SPUR;
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	}

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	ah->config.intr_mitigation = true;
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	/*
	 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
	 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
	 * This means we use it for all AR5416 devices, and the few
	 * minor PCI AR9280 devices out there.
	 *
	 * Serialization is required because these devices do not handle
	 * well the case of two concurrent reads/writes due to the latency
	 * involved. During one read/write another read/write can be issued
	 * on another CPU while the previous read/write may still be working
	 * on our hardware, if we hit this case the hardware poops in a loop.
	 * We prevent this by serializing reads and writes.
	 *
	 * This issue is not present on PCI-Express devices or pre-AR5416
	 * devices (legacy, 802.11abg).
	 */
	if (num_possible_cpus() > 1)
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		ah->config.serialize_regmode = SER_REG_MODE_AUTO;
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}

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static void ath9k_hw_init_defaults(struct ath_hw *ah)
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{
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	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);

	regulatory->country_code = CTRY_DEFAULT;
	regulatory->power_limit = MAX_RATE_POWER;
	regulatory->tp_scale = ATH9K_TP_SCALE_MAX;

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	ah->hw_version.magic = AR5416_MAGIC;
	ah->hw_version.subvendorid = 0;
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	ah->ah_flags = 0;
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	if (ah->hw_version.devid == AR5416_AR9100_DEVID)
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		ah->hw_version.macVersion = AR_SREV_VERSION_9100;
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	if (!AR_SREV_9100(ah))
		ah->ah_flags = AH_USE_EEPROM;

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	ah->atim_window = 0;
	ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
	ah->beacon_interval = 100;
	ah->enable_32kHz_clock = DONT_USE_32KHZ;
	ah->slottime = (u32) -1;
	ah->acktimeout = (u32) -1;
	ah->ctstimeout = (u32) -1;
	ah->globaltxtimeout = (u32) -1;

	ah->gbeacon_rate = 0;
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	ah->power_mode = ATH9K_PM_UNDEFINED;
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}

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static int ath9k_hw_rfattach(struct ath_hw *ah)
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{
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	bool rfStatus = false;
	int ecode = 0;
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	rfStatus = ath9k_hw_init_rf(ah, &ecode);
	if (!rfStatus) {
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		ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
			  "RF setup failed, status: %u\n", ecode);
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		return ecode;
	}
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	return 0;
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}

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static int ath9k_hw_rf_claim(struct ath_hw *ah)
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{
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	u32 val;

	REG_WRITE(ah, AR_PHY(0), 0x00000007);

	val = ath9k_hw_get_radiorev(ah);
	switch (val & AR_RADIO_SREV_MAJOR) {
	case 0:
		val = AR_RAD5133_SREV_MAJOR;
		break;
	case AR_RAD5133_SREV_MAJOR:
	case AR_RAD5122_SREV_MAJOR:
	case AR_RAD2133_SREV_MAJOR:
	case AR_RAD2122_SREV_MAJOR:
		break;
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	default:
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		ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
			  "Radio Chip Rev 0x%02X not supported\n",
			  val & AR_RADIO_SREV_MAJOR);
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		return -EOPNOTSUPP;
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	}

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	ah->hw_version.analog5GhzRev = val;
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	return 0;
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}

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static int ath9k_hw_init_macaddr(struct ath_hw *ah)
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{
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	struct ath_common *common = ath9k_hw_common(ah);
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	u32 sum;
	int i;
	u16 eeval;

	sum = 0;
	for (i = 0; i < 3; i++) {
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		eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
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		sum += eeval;
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		common->macaddr[2 * i] = eeval >> 8;
		common->macaddr[2 * i + 1] = eeval & 0xff;
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	}
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	if (sum == 0 || sum == 0xffff * 3)
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		return -EADDRNOTAVAIL;

	return 0;
}

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static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
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{
	u32 rxgain_type;

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	if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
		rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
506 507

		if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
508
			INIT_INI_ARRAY(&ah->iniModesRxGain,
509 510 511
			ar9280Modes_backoff_13db_rxgain_9280_2,
			ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
		else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
512
			INIT_INI_ARRAY(&ah->iniModesRxGain,
513 514 515
			ar9280Modes_backoff_23db_rxgain_9280_2,
			ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
		else
516
			INIT_INI_ARRAY(&ah->iniModesRxGain,
517 518
			ar9280Modes_original_rxgain_9280_2,
			ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
519
	} else {
520
		INIT_INI_ARRAY(&ah->iniModesRxGain,
521 522
			ar9280Modes_original_rxgain_9280_2,
			ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
523
	}
524 525
}

526
static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
527 528 529
{
	u32 txgain_type;

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530 531
	if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
		txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
532 533

		if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
534
			INIT_INI_ARRAY(&ah->iniModesTxGain,
535 536 537
			ar9280Modes_high_power_tx_gain_9280_2,
			ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
		else
538
			INIT_INI_ARRAY(&ah->iniModesTxGain,
539 540
			ar9280Modes_original_tx_gain_9280_2,
			ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
541
	} else {
542
		INIT_INI_ARRAY(&ah->iniModesTxGain,
543 544
		ar9280Modes_original_tx_gain_9280_2,
		ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
545
	}
546 547
}

548
static int ath9k_hw_post_init(struct ath_hw *ah)
549
{
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550
	int ecode;
551

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552
	if (!ath9k_hw_chip_test(ah))
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553
		return -ENODEV;
554

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555 556
	ecode = ath9k_hw_rf_claim(ah);
	if (ecode != 0)
557 558
		return ecode;

559
	ecode = ath9k_hw_eeprom_init(ah);
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560 561
	if (ecode != 0)
		return ecode;
562

563 564 565 566
	ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
		  "Eeprom VER: %d, REV: %d\n",
		  ah->eep_ops->get_eeprom_ver(ah),
		  ah->eep_ops->get_eeprom_rev(ah));
567

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568 569 570
	ecode = ath9k_hw_rfattach(ah);
	if (ecode != 0)
		return ecode;
571

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572 573
	if (!AR_SREV_9100(ah)) {
		ath9k_hw_ani_setup(ah);
574
		ath9k_hw_ani_init(ah);
575 576 577 578 579
	}

	return 0;
}

580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598
static bool ath9k_hw_devid_supported(u16 devid)
{
	switch (devid) {
	case AR5416_DEVID_PCI:
	case AR5416_DEVID_PCIE:
	case AR5416_AR9100_DEVID:
	case AR9160_DEVID_PCI:
	case AR9280_DEVID_PCI:
	case AR9280_DEVID_PCIE:
	case AR9285_DEVID_PCIE:
	case AR5416_DEVID_AR9287_PCI:
	case AR5416_DEVID_AR9287_PCIE:
		return true;
	default:
		break;
	}
	return false;
}

599 600 601 602 603 604 605 606 607 608 609
static bool ath9k_hw_macversion_supported(u32 macversion)
{
	switch (macversion) {
	case AR_SREV_VERSION_5416_PCI:
	case AR_SREV_VERSION_5416_PCIE:
	case AR_SREV_VERSION_9160:
	case AR_SREV_VERSION_9100:
	case AR_SREV_VERSION_9280:
	case AR_SREV_VERSION_9285:
	case AR_SREV_VERSION_9287:
		return true;
610 611
	/* Not yet */
	case AR_SREV_VERSION_9271:
612 613 614 615 616 617
	default:
		break;
	}
	return false;
}

618
static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
619
{
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620 621
	if (AR_SREV_9160_10_OR_LATER(ah)) {
		if (AR_SREV_9280_10_OR_LATER(ah)) {
622 623
			ah->iq_caldata.calData = &iq_cal_single_sample;
			ah->adcgain_caldata.calData =
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				&adc_gain_cal_single_sample;
625
			ah->adcdc_caldata.calData =
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626
				&adc_dc_cal_single_sample;
627
			ah->adcdc_calinitdata.calData =
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628 629
				&adc_init_dc_cal;
		} else {
630 631
			ah->iq_caldata.calData = &iq_cal_multi_sample;
			ah->adcgain_caldata.calData =
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632
				&adc_gain_cal_multi_sample;
633
			ah->adcdc_caldata.calData =
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634
				&adc_dc_cal_multi_sample;
635
			ah->adcdc_calinitdata.calData =
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636 637
				&adc_init_dc_cal;
		}
638
		ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
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639
	}
640
}
641

642 643
static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
{
644 645 646 647 648 649 650 651
	if (AR_SREV_9271(ah)) {
		INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271_1_0,
			       ARRAY_SIZE(ar9271Modes_9271_1_0), 6);
		INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271_1_0,
			       ARRAY_SIZE(ar9271Common_9271_1_0), 2);
		return;
	}

652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681
	if (AR_SREV_9287_11_OR_LATER(ah)) {
		INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
				ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
		INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
				ARRAY_SIZE(ar9287Common_9287_1_1), 2);
		if (ah->config.pcie_clock_req)
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
			ar9287PciePhy_clkreq_off_L1_9287_1_1,
			ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
		else
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
			ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
			ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
					2);
	} else if (AR_SREV_9287_10_OR_LATER(ah)) {
		INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
				ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
		INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
				ARRAY_SIZE(ar9287Common_9287_1_0), 2);

		if (ah->config.pcie_clock_req)
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
			ar9287PciePhy_clkreq_off_L1_9287_1_0,
			ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
		else
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
			ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
			ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
				  2);
	} else if (AR_SREV_9285_12_OR_LATER(ah)) {
682

683

684
		INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
685
			       ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
686
		INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
687 688
			       ARRAY_SIZE(ar9285Common_9285_1_2), 2);

689 690
		if (ah->config.pcie_clock_req) {
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
691 692 693
			ar9285PciePhy_clkreq_off_L1_9285_1_2,
			ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
		} else {
694
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
695 696 697 698 699
			ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
			ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
				  2);
		}
	} else if (AR_SREV_9285_10_OR_LATER(ah)) {
700
		INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
701
			       ARRAY_SIZE(ar9285Modes_9285), 6);
702
		INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
703 704
			       ARRAY_SIZE(ar9285Common_9285), 2);

705 706
		if (ah->config.pcie_clock_req) {
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
707 708 709
			ar9285PciePhy_clkreq_off_L1_9285,
			ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
		} else {
710
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
711 712 713 714
			ar9285PciePhy_clkreq_always_on_L1_9285,
			ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
		}
	} else if (AR_SREV_9280_20_OR_LATER(ah)) {
715
		INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
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			       ARRAY_SIZE(ar9280Modes_9280_2), 6);
717
		INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
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			       ARRAY_SIZE(ar9280Common_9280_2), 2);
719

720 721
		if (ah->config.pcie_clock_req) {
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
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			       ar9280PciePhy_clkreq_off_L1_9280,
			       ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
		} else {
725
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
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			       ar9280PciePhy_clkreq_always_on_L1_9280,
			       ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
		}
729
		INIT_INI_ARRAY(&ah->iniModesAdditional,
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			       ar9280Modes_fast_clock_9280_2,
			       ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
	} else if (AR_SREV_9280_10_OR_LATER(ah)) {
733
		INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
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			       ARRAY_SIZE(ar9280Modes_9280), 6);
735
		INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
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736 737
			       ARRAY_SIZE(ar9280Common_9280), 2);
	} else if (AR_SREV_9160_10_OR_LATER(ah)) {
738
		INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
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739
			       ARRAY_SIZE(ar5416Modes_9160), 6);
740
		INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
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741
			       ARRAY_SIZE(ar5416Common_9160), 2);
742
		INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
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			       ARRAY_SIZE(ar5416Bank0_9160), 2);
744
		INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
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745
			       ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
746
		INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
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747
			       ARRAY_SIZE(ar5416Bank1_9160), 2);
748
		INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
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749
			       ARRAY_SIZE(ar5416Bank2_9160), 2);
750
		INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
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751
			       ARRAY_SIZE(ar5416Bank3_9160), 3);
752
		INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
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753
			       ARRAY_SIZE(ar5416Bank6_9160), 3);
754
		INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
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755
			       ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
756
		INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
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757 758
			       ARRAY_SIZE(ar5416Bank7_9160), 2);
		if (AR_SREV_9160_11(ah)) {
759
			INIT_INI_ARRAY(&ah->iniAddac,
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760 761 762
				       ar5416Addac_91601_1,
				       ARRAY_SIZE(ar5416Addac_91601_1), 2);
		} else {
763
			INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
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764 765 766
				       ARRAY_SIZE(ar5416Addac_9160), 2);
		}
	} else if (AR_SREV_9100_OR_LATER(ah)) {
767
		INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
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768
			       ARRAY_SIZE(ar5416Modes_9100), 6);
769
		INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
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770
			       ARRAY_SIZE(ar5416Common_9100), 2);
771
		INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
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772
			       ARRAY_SIZE(ar5416Bank0_9100), 2);
773
		INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
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774
			       ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
775
		INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
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776
			       ARRAY_SIZE(ar5416Bank1_9100), 2);
777
		INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
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778
			       ARRAY_SIZE(ar5416Bank2_9100), 2);
779
		INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
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780
			       ARRAY_SIZE(ar5416Bank3_9100), 3);
781
		INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
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782
			       ARRAY_SIZE(ar5416Bank6_9100), 3);
783
		INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
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784
			       ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
785
		INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
S
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786
			       ARRAY_SIZE(ar5416Bank7_9100), 2);
787
		INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
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788 789
			       ARRAY_SIZE(ar5416Addac_9100), 2);
	} else {
790
		INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
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791
			       ARRAY_SIZE(ar5416Modes), 6);
792
		INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
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793
			       ARRAY_SIZE(ar5416Common), 2);
794
		INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
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795
			       ARRAY_SIZE(ar5416Bank0), 2);
796
		INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
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797
			       ARRAY_SIZE(ar5416BB_RfGain), 3);
798
		INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
S
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799
			       ARRAY_SIZE(ar5416Bank1), 2);
800
		INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
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801
			       ARRAY_SIZE(ar5416Bank2), 2);
802
		INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
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803
			       ARRAY_SIZE(ar5416Bank3), 3);
804
		INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
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805
			       ARRAY_SIZE(ar5416Bank6), 3);
806
		INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
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807
			       ARRAY_SIZE(ar5416Bank6TPC), 3);
808
		INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
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809
			       ARRAY_SIZE(ar5416Bank7), 2);
810
		INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
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811
			       ARRAY_SIZE(ar5416Addac), 2);
812
	}
813
}
814

815 816
static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
{
817
	if (AR_SREV_9287_11_OR_LATER(ah))
818 819 820 821 822 823 824 825 826 827
		INIT_INI_ARRAY(&ah->iniModesRxGain,
		ar9287Modes_rx_gain_9287_1_1,
		ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
	else if (AR_SREV_9287_10(ah))
		INIT_INI_ARRAY(&ah->iniModesRxGain,
		ar9287Modes_rx_gain_9287_1_0,
		ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
	else if (AR_SREV_9280_20(ah))
		ath9k_hw_init_rxgain_ini(ah);

828
	if (AR_SREV_9287_11_OR_LATER(ah)) {
829 830 831 832 833 834 835 836 837 838
		INIT_INI_ARRAY(&ah->iniModesTxGain,
		ar9287Modes_tx_gain_9287_1_1,
		ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
	} else if (AR_SREV_9287_10(ah)) {
		INIT_INI_ARRAY(&ah->iniModesTxGain,
		ar9287Modes_tx_gain_9287_1_0,
		ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
	} else if (AR_SREV_9280_20(ah)) {
		ath9k_hw_init_txgain_ini(ah);
	} else if (AR_SREV_9285_12_OR_LATER(ah)) {
839 840 841 842 843 844 845 846 847 848 849 850 851 852
		u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);

		/* txgain table */
		if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
			INIT_INI_ARRAY(&ah->iniModesTxGain,
			ar9285Modes_high_power_tx_gain_9285_1_2,
			ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
		} else {
			INIT_INI_ARRAY(&ah->iniModesTxGain,
			ar9285Modes_original_tx_gain_9285_1_2,
			ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
		}

	}
853
}
854

855 856 857
static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah)
{
	u32 i, j;
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858 859 860 861 862

	if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
	    test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {

		/* EEPROM Fixup */
863 864
		for (i = 0; i < ah->iniModes.ia_rows; i++) {
			u32 reg = INI_RA(&ah->iniModes, i, 0);
865

866 867
			for (j = 1; j < ah->iniModes.ia_columns; j++) {
				u32 val = INI_RA(&ah->iniModes, i, j);
868

869
				INI_RA(&ah->iniModes, i, j) =
870
					ath9k_hw_ini_fixup(ah,
871
							   &ah->eeprom.def,
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872 873
							   reg, val);
			}
874
		}
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875
	}
876 877
}

878
int ath9k_hw_init(struct ath_hw *ah)
879
{
880
	struct ath_common *common = ath9k_hw_common(ah);
881
	int r = 0;
882

883 884
	if (!ath9k_hw_devid_supported(ah->hw_version.devid))
		return -EOPNOTSUPP;
885 886 887 888 889

	ath9k_hw_init_defaults(ah);
	ath9k_hw_init_config(ah);

	if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
890 891
		ath_print(common, ATH_DBG_FATAL,
			  "Couldn't reset chip\n");
892
		return -EIO;
893 894
	}

895
	if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
896
		ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
897
		return -EIO;
898 899 900 901 902 903 904 905 906 907 908 909 910
	}

	if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
		if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
		    (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
			ah->config.serialize_regmode =
				SER_REG_MODE_ON;
		} else {
			ah->config.serialize_regmode =
				SER_REG_MODE_OFF;
		}
	}

911
	ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
912 913 914
		ah->config.serialize_regmode);

	if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
915 916 917 918
		ath_print(common, ATH_DBG_FATAL,
			  "Mac Chip Rev 0x%02x.%x is not supported by "
			  "this driver\n", ah->hw_version.macVersion,
			  ah->hw_version.macRev);
919
		return -EOPNOTSUPP;
920 921 922 923 924 925 926
	}

	if (AR_SREV_9100(ah)) {
		ah->iq_caldata.calData = &iq_cal_multi_sample;
		ah->supp_cals = IQ_MISMATCH_CAL;
		ah->is_pciexpress = false;
	}
927 928 929 930

	if (AR_SREV_9271(ah))
		ah->is_pciexpress = false;

931 932 933 934 935 936 937 938 939 940 941
	ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);

	ath9k_hw_init_cal_settings(ah);

	ah->ani_function = ATH9K_ANI_ALL;
	if (AR_SREV_9280_10_OR_LATER(ah))
		ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;

	ath9k_hw_init_mode_regs(ah);

	if (ah->is_pciexpress)
V
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		ath9k_hw_configpcipowersave(ah, 0, 0);
943 944 945
	else
		ath9k_hw_disablepcie(ah);

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946 947 948 949 950 951 952 953 954 955
	/* Support for Japan ch.14 (2484) spread */
	if (AR_SREV_9287_11_OR_LATER(ah)) {
		INIT_INI_ARRAY(&ah->iniCckfirNormal,
		       ar9287Common_normal_cck_fir_coeff_92871_1,
		       ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
		INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
		       ar9287Common_japan_2484_cck_fir_coeff_92871_1,
		       ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
	}

956
	r = ath9k_hw_post_init(ah);
957
	if (r)
958
		return r;
959 960 961 962

	ath9k_hw_init_mode_gain_regs(ah);
	ath9k_hw_fill_cap_info(ah);
	ath9k_hw_init_11a_eeprom_fix(ah);
963

964 965
	r = ath9k_hw_init_macaddr(ah);
	if (r) {
966 967
		ath_print(common, ATH_DBG_FATAL,
			  "Failed to initialize MAC address\n");
968
		return r;
969 970
	}

971
	if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
972
		ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
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	else
974
		ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
975

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976
	ath9k_init_nfcal_hist_buffer(ah);
977

978
	return 0;
979 980
}

981
static void ath9k_hw_init_bb(struct ath_hw *ah,
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982
			     struct ath9k_channel *chan)
983
{
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984
	u32 synthDelay;
985

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986
	synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
987
	if (IS_CHAN_B(chan))
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988 989 990
		synthDelay = (4 * synthDelay) / 22;
	else
		synthDelay /= 10;
991

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992
	REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
993

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994
	udelay(synthDelay + BASE_ACTIVATE_DELAY);
995 996
}

997
static void ath9k_hw_init_qos(struct ath_hw *ah)
998
{
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	REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
	REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
1001

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1002 1003 1004 1005 1006 1007 1008 1009 1010 1011
	REG_WRITE(ah, AR_QOS_NO_ACK,
		  SM(2, AR_QOS_NO_ACK_TWO_BIT) |
		  SM(5, AR_QOS_NO_ACK_BIT_OFF) |
		  SM(0, AR_QOS_NO_ACK_BYTE_OFF));

	REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
	REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
	REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
	REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
	REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1012 1013
}

1014
static void ath9k_hw_init_pll(struct ath_hw *ah,
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1015
			      struct ath9k_channel *chan)
1016
{
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1017
	u32 pll;
1018

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1019 1020 1021
	if (AR_SREV_9100(ah)) {
		if (chan && IS_CHAN_5GHZ(chan))
			pll = 0x1450;
1022
		else
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1023 1024 1025 1026
			pll = 0x1458;
	} else {
		if (AR_SREV_9280_10_OR_LATER(ah)) {
			pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1027

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1028 1029 1030 1031
			if (chan && IS_CHAN_HALF_RATE(chan))
				pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
			else if (chan && IS_CHAN_QUARTER_RATE(chan))
				pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1032

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1033 1034
			if (chan && IS_CHAN_5GHZ(chan)) {
				pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1035 1036


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1037 1038 1039 1040 1041 1042 1043 1044 1045 1046
				if (AR_SREV_9280_20(ah)) {
					if (((chan->channel % 20) == 0)
					    || ((chan->channel % 10) == 0))
						pll = 0x2850;
					else
						pll = 0x142c;
				}
			} else {
				pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
			}
1047

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1048
		} else if (AR_SREV_9160_10_OR_LATER(ah)) {
1049

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1050
			pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1051

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1052 1053 1054 1055
			if (chan && IS_CHAN_HALF_RATE(chan))
				pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
			else if (chan && IS_CHAN_QUARTER_RATE(chan))
				pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1056

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1057 1058 1059 1060 1061 1062
			if (chan && IS_CHAN_5GHZ(chan))
				pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
			else
				pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
		} else {
			pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1063

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1064 1065 1066 1067
			if (chan && IS_CHAN_HALF_RATE(chan))
				pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
			else if (chan && IS_CHAN_QUARTER_RATE(chan))
				pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1068

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1069 1070 1071 1072 1073 1074
			if (chan && IS_CHAN_5GHZ(chan))
				pll |= SM(0xa, AR_RTC_PLL_DIV);
			else
				pll |= SM(0xb, AR_RTC_PLL_DIV);
		}
	}
1075
	REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1076

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1077 1078 1079
	udelay(RTC_PLL_SETTLE_DELAY);

	REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1080 1081
}

1082
static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1083 1084 1085
{
	int rx_chainmask, tx_chainmask;

1086 1087
	rx_chainmask = ah->rxchainmask;
	tx_chainmask = ah->txchainmask;
1088 1089 1090 1091 1092 1093

	switch (rx_chainmask) {
	case 0x5:
		REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
			    AR_PHY_SWAP_ALT_CHAIN);
	case 0x3:
1094
		if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118
			REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
			REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
			break;
		}
	case 0x1:
	case 0x2:
	case 0x7:
		REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
		REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
		break;
	default:
		break;
	}

	REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
	if (tx_chainmask == 0x5) {
		REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
			    AR_PHY_SWAP_ALT_CHAIN);
	}
	if (AR_SREV_9100(ah))
		REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
			  REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
}

1119
static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1120
					  enum nl80211_iftype opmode)
1121
{
1122
	ah->mask_reg = AR_IMR_TXERR |
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1123 1124 1125 1126
		AR_IMR_TXURN |
		AR_IMR_RXERR |
		AR_IMR_RXORN |
		AR_IMR_BCNMISC;
1127

1128
	if (ah->config.intr_mitigation)
1129
		ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1130
	else
1131
		ah->mask_reg |= AR_IMR_RXOK;
1132

1133
	ah->mask_reg |= AR_IMR_TXOK;
1134

1135
	if (opmode == NL80211_IFTYPE_AP)
1136
		ah->mask_reg |= AR_IMR_MIB;
1137

1138
	REG_WRITE(ah, AR_IMR, ah->mask_reg);
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1139
	REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1140

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1141 1142 1143 1144 1145
	if (!AR_SREV_9100(ah)) {
		REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
		REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
		REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
	}
1146 1147
}

1148
static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1149 1150
{
	if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1151 1152
		ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
			  "bad ack timeout %u\n", us);
1153
		ah->acktimeout = (u32) -1;
1154 1155 1156 1157
		return false;
	} else {
		REG_RMW_FIELD(ah, AR_TIME_OUT,
			      AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1158
		ah->acktimeout = us;
1159 1160 1161 1162
		return true;
	}
}

1163
static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1164 1165
{
	if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1166 1167
		ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
			  "bad cts timeout %u\n", us);
1168
		ah->ctstimeout = (u32) -1;
1169 1170 1171 1172
		return false;
	} else {
		REG_RMW_FIELD(ah, AR_TIME_OUT,
			      AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1173
		ah->ctstimeout = us;
1174 1175 1176
		return true;
	}
}
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1177

1178
static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1179 1180
{
	if (tu > 0xFFFF) {
1181 1182
		ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
			  "bad global tx timeout %u\n", tu);
1183
		ah->globaltxtimeout = (u32) -1;
1184 1185 1186
		return false;
	} else {
		REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1187
		ah->globaltxtimeout = tu;
1188 1189 1190 1191
		return true;
	}
}

1192
static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1193
{
1194 1195
	ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
		  ah->misc_mode);
1196

1197
	if (ah->misc_mode != 0)
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		REG_WRITE(ah, AR_PCU_MISC,
1199 1200 1201 1202 1203 1204 1205 1206 1207
			  REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
	if (ah->slottime != (u32) -1)
		ath9k_hw_setslottime(ah, ah->slottime);
	if (ah->acktimeout != (u32) -1)
		ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
	if (ah->ctstimeout != (u32) -1)
		ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
	if (ah->globaltxtimeout != (u32) -1)
		ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
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1208 1209 1210 1211 1212 1213 1214 1215
}

const char *ath9k_hw_probe(u16 vendorid, u16 devid)
{
	return vendorid == ATHEROS_VENDOR_ID ?
		ath9k_hw_devname(devid) : NULL;
}

1216
void ath9k_hw_detach(struct ath_hw *ah)
S
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1217 1218
{
	if (!AR_SREV_9100(ah))
1219
		ath9k_hw_ani_disable(ah);
S
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1220

1221
	ath9k_hw_rf_free(ah);
1222
	ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
S
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1223
	kfree(ah);
1224
	ah = NULL;
S
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1225 1226 1227 1228 1229 1230
}

/*******/
/* INI */
/*******/

1231
static void ath9k_hw_override_ini(struct ath_hw *ah,
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1232 1233
				  struct ath9k_channel *chan)
{
1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254
	u32 val;

	if (AR_SREV_9271(ah)) {
		/*
		 * Enable spectral scan to solution for issues with stuck
		 * beacons on AR9271 1.0. The beacon stuck issue is not seeon on
		 * AR9271 1.1
		 */
		if (AR_SREV_9271_10(ah)) {
			val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) | AR_PHY_SPECTRAL_SCAN_ENABLE;
			REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
		}
		else if (AR_SREV_9271_11(ah))
			/*
			 * change AR_PHY_RF_CTL3 setting to fix MAC issue
			 * present on AR9271 1.1
			 */
			REG_WRITE(ah, AR_PHY_RF_CTL3, 0x3a020001);
		return;
	}

1255 1256 1257 1258 1259 1260 1261
	/*
	 * Set the RX_ABORT and RX_DIS and clear if off only after
	 * RXE is set for MAC. This prevents frames with corrupted
	 * descriptor status.
	 */
	REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));

1262 1263 1264 1265 1266 1267 1268 1269 1270
	if (AR_SREV_9280_10_OR_LATER(ah)) {
		val = REG_READ(ah, AR_PCU_MISC_MODE2) &
			       (~AR_PCU_MISC_MODE2_HWWAR1);

		if (AR_SREV_9287_10_OR_LATER(ah))
			val = val & (~AR_PCU_MISC_MODE2_HWWAR2);

		REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
	}
1271

1272
	if (!AR_SREV_5416_20_OR_LATER(ah) ||
S
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1273 1274
	    AR_SREV_9280_10_OR_LATER(ah))
		return;
1275 1276 1277 1278
	/*
	 * Disable BB clock gating
	 * Necessary to avoid issues on AR5416 2.0
	 */
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1279
	REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1280 1281
}

1282
static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1283
			      struct ar5416_eeprom_def *pEepData,
S
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1284
			      u32 reg, u32 value)
1285
{
S
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1286
	struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1287
	struct ath_common *common = ath9k_hw_common(ah);
1288

1289
	switch (ah->hw_version.devid) {
S
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1290 1291
	case AR9280_DEVID_PCI:
		if (reg == 0x7894) {
1292
			ath_print(common, ATH_DBG_EEPROM,
S
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1293 1294 1295 1296
				"ini VAL: %x  EEPROM: %x\n", value,
				(pBase->version & 0xff));

			if ((pBase->version & 0xff) > 0x0a) {
1297 1298 1299
				ath_print(common, ATH_DBG_EEPROM,
					  "PWDCLKIND: %d\n",
					  pBase->pwdclkind);
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1300 1301 1302 1303
				value &= ~AR_AN_TOP2_PWDCLKIND;
				value |= AR_AN_TOP2_PWDCLKIND &
					(pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
			} else {
1304 1305
				ath_print(common, ATH_DBG_EEPROM,
					  "PWDCLKIND Earlier Rev\n");
S
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1306 1307
			}

1308 1309
			ath_print(common, ATH_DBG_EEPROM,
				  "final ini VAL: %x\n", value);
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1310 1311 1312 1313 1314
		}
		break;
	}

	return value;
1315 1316
}

1317
static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1318 1319 1320
			      struct ar5416_eeprom_def *pEepData,
			      u32 reg, u32 value)
{
1321
	if (ah->eep_map == EEP_MAP_4KBITS)
1322 1323 1324 1325 1326
		return value;
	else
		return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
}

1327 1328 1329 1330
static void ath9k_olc_init(struct ath_hw *ah)
{
	u32 i;

1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345
	if (OLC_FOR_AR9287_10_LATER) {
		REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
				AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
		ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
				AR9287_AN_TXPC0_TXPCMODE,
				AR9287_AN_TXPC0_TXPCMODE_S,
				AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
		udelay(100);
	} else {
		for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
			ah->originalGain[i] =
				MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
						AR_PHY_TX_GAIN);
		ah->PDADCdelta = 0;
	}
1346 1347
}

1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362
static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
			      struct ath9k_channel *chan)
{
	u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);

	if (IS_CHAN_B(chan))
		ctl |= CTL_11B;
	else if (IS_CHAN_G(chan))
		ctl |= CTL_11G;
	else
		ctl |= CTL_11A;

	return ctl;
}

1363
static int ath9k_hw_process_ini(struct ath_hw *ah,
L
Luis R. Rodriguez 已提交
1364
				struct ath9k_channel *chan)
1365
{
1366
	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1367
	int i, regWrites = 0;
1368
	struct ieee80211_channel *channel = chan->chan;
1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399
	u32 modesIndex, freqIndex;

	switch (chan->chanmode) {
	case CHANNEL_A:
	case CHANNEL_A_HT20:
		modesIndex = 1;
		freqIndex = 1;
		break;
	case CHANNEL_A_HT40PLUS:
	case CHANNEL_A_HT40MINUS:
		modesIndex = 2;
		freqIndex = 1;
		break;
	case CHANNEL_G:
	case CHANNEL_G_HT20:
	case CHANNEL_B:
		modesIndex = 4;
		freqIndex = 2;
		break;
	case CHANNEL_G_HT40PLUS:
	case CHANNEL_G_HT40MINUS:
		modesIndex = 3;
		freqIndex = 2;
		break;

	default:
		return -EINVAL;
	}

	REG_WRITE(ah, AR_PHY(0), 0x00000007);
	REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
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	ah->eep_ops->set_addac(ah, chan);
1401

1402
	if (AR_SREV_5416_22_OR_LATER(ah)) {
1403
		REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1404 1405 1406
	} else {
		struct ar5416IniArray temp;
		u32 addacSize =
1407 1408
			sizeof(u32) * ah->iniAddac.ia_rows *
			ah->iniAddac.ia_columns;
1409

1410 1411
		memcpy(ah->addac5416_21,
		       ah->iniAddac.ia_array, addacSize);
1412

1413
		(ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1414

1415 1416 1417
		temp.ia_array = ah->addac5416_21;
		temp.ia_columns = ah->iniAddac.ia_columns;
		temp.ia_rows = ah->iniAddac.ia_rows;
1418 1419
		REG_WRITE_ARRAY(&temp, 1, regWrites);
	}
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1421 1422
	REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);

1423 1424 1425
	for (i = 0; i < ah->iniModes.ia_rows; i++) {
		u32 reg = INI_RA(&ah->iniModes, i, 0);
		u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1426 1427 1428 1429

		REG_WRITE(ah, reg, val);

		if (reg >= 0x7800 && reg < 0x78a0
1430
		    && ah->config.analog_shiftreg) {
1431 1432 1433 1434 1435 1436
			udelay(100);
		}

		DO_DELAY(regWrites);
	}

1437
	if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1438
		REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1439

1440 1441
	if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
	    AR_SREV_9287_10_OR_LATER(ah))
1442
		REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1443

1444 1445 1446
	for (i = 0; i < ah->iniCommon.ia_rows; i++) {
		u32 reg = INI_RA(&ah->iniCommon, i, 0);
		u32 val = INI_RA(&ah->iniCommon, i, 1);
1447 1448 1449 1450

		REG_WRITE(ah, reg, val);

		if (reg >= 0x7800 && reg < 0x78a0
1451
		    && ah->config.analog_shiftreg) {
1452 1453 1454 1455 1456 1457 1458 1459 1460
			udelay(100);
		}

		DO_DELAY(regWrites);
	}

	ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);

	if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1461
		REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1462 1463 1464 1465
				regWrites);
	}

	ath9k_hw_override_ini(ah, chan);
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	ath9k_hw_set_regs(ah, chan);
1467 1468
	ath9k_hw_init_chain_masks(ah);

1469 1470 1471
	if (OLC_FOR_AR9280_20_LATER)
		ath9k_olc_init(ah);

1472
	ah->eep_ops->set_txpower(ah, chan,
1473
				 ath9k_regd_get_ctl(regulatory, chan),
1474 1475 1476
				 channel->max_antenna_gain * 2,
				 channel->max_power * 2,
				 min((u32) MAX_RATE_POWER,
1477
				 (u32) regulatory->power_limit));
1478 1479

	if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1480 1481
		ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
			  "ar5416SetRfRegs failed\n");
1482 1483 1484 1485 1486 1487
		return -EIO;
	}

	return 0;
}

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/****************************************/
/* Reset and Channel Switching Routines */
/****************************************/

1492
static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1493
{
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	u32 rfMode = 0;

	if (chan == NULL)
		return;

	rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
		? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;

	if (!AR_SREV_9280_10_OR_LATER(ah))
		rfMode |= (IS_CHAN_5GHZ(chan)) ?
			AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;

	if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
		rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);

	REG_WRITE(ah, AR_PHY_MODE, rfMode);
}

1512
static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
S
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{
	REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
}

1517
static inline void ath9k_hw_set_dma(struct ath_hw *ah)
S
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{
	u32 regval;

1521 1522 1523
	/*
	 * set AHB_MODE not to do cacheline prefetches
	*/
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	regval = REG_READ(ah, AR_AHB_MODE);
	REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);

1527 1528 1529
	/*
	 * let mac dma reads be in 128 byte chunks
	 */
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	regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
	REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);

1533 1534 1535 1536 1537
	/*
	 * Restore TX Trigger Level to its pre-reset value.
	 * The initial value depends on whether aggregation is enabled, and is
	 * adjusted whenever underruns are detected.
	 */
1538
	REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
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1539

1540 1541 1542
	/*
	 * let mac dma writes be in 128 byte chunks
	 */
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1543 1544 1545
	regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
	REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);

1546 1547 1548
	/*
	 * Setup receive FIFO threshold to hold off TX activities
	 */
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1549 1550
	REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);

1551 1552 1553 1554
	/*
	 * reduce the number of usable entries in PCU TXBUF to avoid
	 * wrap around issues.
	 */
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	if (AR_SREV_9285(ah)) {
1556 1557 1558 1559
		/* For AR9285 the number of Fifos are reduced to half.
		 * So set the usable tx buf size also to half to
		 * avoid data/delimiter underruns
		 */
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1560 1561
		REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
			  AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1562
	} else if (!AR_SREV_9271(ah)) {
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		REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
			  AR_PCU_TXBUF_CTRL_USABLE_SIZE);
	}
}

1568
static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
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1569 1570 1571 1572 1573 1574
{
	u32 val;

	val = REG_READ(ah, AR_STA_ID1);
	val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
	switch (opmode) {
1575
	case NL80211_IFTYPE_AP:
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		REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
			  | AR_STA_ID1_KSRCH_MODE);
		REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1579
		break;
1580
	case NL80211_IFTYPE_ADHOC:
1581
	case NL80211_IFTYPE_MESH_POINT:
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1582 1583 1584
		REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
			  | AR_STA_ID1_KSRCH_MODE);
		REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1585
		break;
1586 1587
	case NL80211_IFTYPE_STATION:
	case NL80211_IFTYPE_MONITOR:
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		REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1589
		break;
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1590 1591 1592
	}
}

1593
static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
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1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611
						 u32 coef_scaled,
						 u32 *coef_mantissa,
						 u32 *coef_exponent)
{
	u32 coef_exp, coef_man;

	for (coef_exp = 31; coef_exp > 0; coef_exp--)
		if ((coef_scaled >> coef_exp) & 0x1)
			break;

	coef_exp = 14 - (coef_exp - COEF_SCALE_S);

	coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));

	*coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
	*coef_exponent = coef_exp - 16;
}

1612
static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
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				     struct ath9k_channel *chan)
{
	u32 coef_scaled, ds_coef_exp, ds_coef_man;
	u32 clockMhzScaled = 0x64000000;
	struct chan_centers centers;

	if (IS_CHAN_HALF_RATE(chan))
		clockMhzScaled = clockMhzScaled >> 1;
	else if (IS_CHAN_QUARTER_RATE(chan))
		clockMhzScaled = clockMhzScaled >> 2;

	ath9k_hw_get_channel_centers(ah, chan, &centers);
	coef_scaled = clockMhzScaled / centers.synth_center;

	ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
				      &ds_coef_exp);

	REG_RMW_FIELD(ah, AR_PHY_TIMING3,
		      AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
	REG_RMW_FIELD(ah, AR_PHY_TIMING3,
		      AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);

	coef_scaled = (9 * coef_scaled) / 10;

	ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
				      &ds_coef_exp);

	REG_RMW_FIELD(ah, AR_PHY_HALFGI,
		      AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
	REG_RMW_FIELD(ah, AR_PHY_HALFGI,
		      AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
}

1646
static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
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{
	u32 rst_flags;
	u32 tmpReg;

1651 1652 1653 1654 1655 1656 1657 1658
	if (AR_SREV_9100(ah)) {
		u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
		val &= ~AR_RTC_DERIVED_CLK_PERIOD;
		val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
		REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
		(void)REG_READ(ah, AR_RTC_DERIVED_CLK);
	}

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1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680
	REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
		  AR_RTC_FORCE_WAKE_ON_INT);

	if (AR_SREV_9100(ah)) {
		rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
			AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
	} else {
		tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
		if (tmpReg &
		    (AR_INTR_SYNC_LOCAL_TIMEOUT |
		     AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
			REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
			REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
		} else {
			REG_WRITE(ah, AR_RC, AR_RC_AHB);
		}

		rst_flags = AR_RTC_RC_MAC_WARM;
		if (type == ATH9K_RESET_COLD)
			rst_flags |= AR_RTC_RC_MAC_COLD;
	}

1681
	REG_WRITE(ah, AR_RTC_RC, rst_flags);
S
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1682 1683
	udelay(50);

1684
	REG_WRITE(ah, AR_RTC_RC, 0);
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1685
	if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1686 1687
		ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
			  "RTC stuck in MAC reset\n");
S
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1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701
		return false;
	}

	if (!AR_SREV_9100(ah))
		REG_WRITE(ah, AR_RC, 0);

	ath9k_hw_init_pll(ah, NULL);

	if (AR_SREV_9100(ah))
		udelay(50);

	return true;
}

1702
static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
S
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1703 1704 1705 1706
{
	REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
		  AR_RTC_FORCE_WAKE_ON_INT);

1707 1708 1709
	if (!AR_SREV_9100(ah))
		REG_WRITE(ah, AR_RC, AR_RC_AHB);

1710
	REG_WRITE(ah, AR_RTC_RESET, 0);
1711
	udelay(2);
1712 1713 1714 1715

	if (!AR_SREV_9100(ah))
		REG_WRITE(ah, AR_RC, 0);

1716
	REG_WRITE(ah, AR_RTC_RESET, 1);
S
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1717 1718 1719 1720

	if (!ath9k_hw_wait(ah,
			   AR_RTC_STATUS,
			   AR_RTC_STATUS_M,
S
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1721 1722
			   AR_RTC_STATUS_ON,
			   AH_WAIT_TIMEOUT)) {
1723 1724
		ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
			  "RTC not waking up\n");
S
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1725
		return false;
1726 1727
	}

S
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1728 1729 1730 1731 1732
	ath9k_hw_read_revisions(ah);

	return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
}

1733
static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
S
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1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746
{
	REG_WRITE(ah, AR_RTC_FORCE_WAKE,
		  AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);

	switch (type) {
	case ATH9K_RESET_POWER_ON:
		return ath9k_hw_set_reset_power_on(ah);
	case ATH9K_RESET_WARM:
	case ATH9K_RESET_COLD:
		return ath9k_hw_set_reset(ah, type);
	default:
		return false;
	}
1747 1748
}

L
Luis R. Rodriguez 已提交
1749
static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
1750
{
S
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1751
	u32 phymode;
1752
	u32 enableDacFifo = 0;
1753

1754 1755 1756 1757
	if (AR_SREV_9285_10_OR_LATER(ah))
		enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
					 AR_PHY_FC_ENABLE_DAC_FIFO);

S
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1758
	phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1759
		| AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
S
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1760 1761 1762

	if (IS_CHAN_HT40(chan)) {
		phymode |= AR_PHY_FC_DYN2040_EN;
1763

S
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1764 1765 1766
		if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
		    (chan->chanmode == CHANNEL_G_HT40PLUS))
			phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1767 1768

	}
S
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1769 1770
	REG_WRITE(ah, AR_PHY_TURBO, phymode);

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Luis R. Rodriguez 已提交
1771
	ath9k_hw_set11nmac2040(ah);
1772

S
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1773 1774
	REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
	REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1775 1776
}

1777
static bool ath9k_hw_chip_reset(struct ath_hw *ah,
S
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1778
				struct ath9k_channel *chan)
1779
{
1780
	if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1781 1782 1783
		if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
			return false;
	} else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
S
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1784
		return false;
1785

1786
	if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
S
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1787
		return false;
1788

1789
	ah->chip_fullsleep = false;
S
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1790 1791
	ath9k_hw_init_pll(ah, chan);
	ath9k_hw_set_rfmode(ah, chan);
1792

S
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1793
	return true;
1794 1795
}

1796
static bool ath9k_hw_channel_change(struct ath_hw *ah,
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Luis R. Rodriguez 已提交
1797
				    struct ath9k_channel *chan)
1798
{
1799
	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1800
	struct ath_common *common = ath9k_hw_common(ah);
1801
	struct ieee80211_channel *channel = chan->chan;
1802 1803 1804 1805
	u32 synthDelay, qnum;

	for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
		if (ath9k_hw_numtxpending(ah, qnum)) {
1806 1807 1808
			ath_print(common, ATH_DBG_QUEUE,
				  "Transmit frames pending on "
				  "queue %d\n", qnum);
1809 1810 1811 1812 1813 1814
			return false;
		}
	}

	REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
	if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
S
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1815
			   AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1816 1817
		ath_print(common, ATH_DBG_FATAL,
			  "Could not kill baseband RX\n");
1818 1819 1820
		return false;
	}

L
Luis R. Rodriguez 已提交
1821
	ath9k_hw_set_regs(ah, chan);
1822 1823

	if (AR_SREV_9280_10_OR_LATER(ah)) {
1824
		ath9k_hw_ar9280_set_channel(ah, chan);
1825 1826
	} else {
		if (!(ath9k_hw_set_channel(ah, chan))) {
1827 1828
			ath_print(common, ATH_DBG_FATAL,
				  "Failed to set channel\n");
1829 1830 1831 1832
			return false;
		}
	}

1833
	ah->eep_ops->set_txpower(ah, chan,
1834
			     ath9k_regd_get_ctl(regulatory, chan),
S
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1835 1836 1837
			     channel->max_antenna_gain * 2,
			     channel->max_power * 2,
			     min((u32) MAX_RATE_POWER,
1838
			     (u32) regulatory->power_limit));
1839 1840

	synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1841
	if (IS_CHAN_B(chan))
1842 1843 1844 1845 1846 1847 1848 1849
		synthDelay = (4 * synthDelay) / 22;
	else
		synthDelay /= 10;

	udelay(synthDelay + BASE_ACTIVATE_DELAY);

	REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);

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1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863
	if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
		ath9k_hw_set_delta_slope(ah, chan);

	if (AR_SREV_9280_10_OR_LATER(ah))
		ath9k_hw_9280_spur_mitigate(ah, chan);
	else
		ath9k_hw_spur_mitigate(ah, chan);

	if (!chan->oneTimeCalsDone)
		chan->oneTimeCalsDone = true;

	return true;
}

1864
static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
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{
	int bb_spur = AR_NO_SPUR;
	int freq;
	int bin, cur_bin;
	int bb_spur_off, spur_subchannel_sd;
	int spur_freq_sd;
	int spur_delta_phase;
	int denominator;
	int upper, lower, cur_vit_mask;
	int tmp, newVal;
	int i;
	int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
			  AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
	};
	int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
			 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
	};
	int inc[4] = { 0, 100, 0, 0 };
	struct chan_centers centers;

	int8_t mask_m[123];
	int8_t mask_p[123];
	int8_t mask_amt;
	int tmp_mask;
	int cur_bb_spur;
	bool is2GHz = IS_CHAN_2GHZ(chan);

	memset(&mask_m, 0, sizeof(int8_t) * 123);
	memset(&mask_p, 0, sizeof(int8_t) * 123);

	ath9k_hw_get_channel_centers(ah, chan, &centers);
	freq = centers.synth_center;

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	ah->config.spurmode = SPUR_ENABLE_EEPROM;
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	for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
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		cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
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		if (is2GHz)
			cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
		else
			cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;

		if (AR_NO_SPUR == cur_bb_spur)
			break;
		cur_bb_spur = cur_bb_spur - freq;

		if (IS_CHAN_HT40(chan)) {
			if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
			    (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
				bb_spur = cur_bb_spur;
				break;
			}
		} else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
			   (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
			bb_spur = cur_bb_spur;
			break;
		}
	}

	if (AR_NO_SPUR == bb_spur) {
		REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
			    AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
		return;
	} else {
		REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
			    AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
	}

	bin = bb_spur * 320;

	tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));

	newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
			AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
			AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
			AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
	REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);

	newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
		  AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
		  AR_PHY_SPUR_REG_MASK_RATE_SELECT |
		  AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
		  SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
	REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);

	if (IS_CHAN_HT40(chan)) {
		if (bb_spur < 0) {
			spur_subchannel_sd = 1;
			bb_spur_off = bb_spur + 10;
		} else {
			spur_subchannel_sd = 0;
			bb_spur_off = bb_spur - 10;
		}
	} else {
		spur_subchannel_sd = 0;
		bb_spur_off = bb_spur;
	}

	if (IS_CHAN_HT40(chan))
		spur_delta_phase =
			((bb_spur * 262144) /
			 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
	else
		spur_delta_phase =
			((bb_spur * 524288) /
			 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;

	denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
	spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;

	newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
		  SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
		  SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
	REG_WRITE(ah, AR_PHY_TIMING11, newVal);

	newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
	REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);

	cur_bin = -6000;
	upper = bin + 100;
	lower = bin - 100;

	for (i = 0; i < 4; i++) {
		int pilot_mask = 0;
		int chan_mask = 0;
		int bp = 0;
		for (bp = 0; bp < 30; bp++) {
			if ((cur_bin > lower) && (cur_bin < upper)) {
				pilot_mask = pilot_mask | 0x1 << bp;
				chan_mask = chan_mask | 0x1 << bp;
			}
			cur_bin += 100;
		}
		cur_bin += inc[i];
		REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
		REG_WRITE(ah, chan_mask_reg[i], chan_mask);
	}

	cur_vit_mask = 6100;
	upper = bin + 120;
	lower = bin - 120;

	for (i = 0; i < 123; i++) {
		if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {

			/* workaround for gcc bug #37014 */
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			volatile int tmp_v = abs(cur_vit_mask - bin);
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			if (tmp_v < 75)
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				mask_amt = 1;
			else
				mask_amt = 0;
			if (cur_vit_mask < 0)
				mask_m[abs(cur_vit_mask / 100)] = mask_amt;
			else
				mask_p[cur_vit_mask / 100] = mask_amt;
		}
		cur_vit_mask -= 100;
	}

	tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
		| (mask_m[48] << 26) | (mask_m[49] << 24)
		| (mask_m[50] << 22) | (mask_m[51] << 20)
		| (mask_m[52] << 18) | (mask_m[53] << 16)
		| (mask_m[54] << 14) | (mask_m[55] << 12)
		| (mask_m[56] << 10) | (mask_m[57] << 8)
		| (mask_m[58] << 6) | (mask_m[59] << 4)
		| (mask_m[60] << 2) | (mask_m[61] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
	REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);

	tmp_mask = (mask_m[31] << 28)
		| (mask_m[32] << 26) | (mask_m[33] << 24)
		| (mask_m[34] << 22) | (mask_m[35] << 20)
		| (mask_m[36] << 18) | (mask_m[37] << 16)
		| (mask_m[48] << 14) | (mask_m[39] << 12)
		| (mask_m[40] << 10) | (mask_m[41] << 8)
		| (mask_m[42] << 6) | (mask_m[43] << 4)
		| (mask_m[44] << 2) | (mask_m[45] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);

	tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
		| (mask_m[18] << 26) | (mask_m[18] << 24)
		| (mask_m[20] << 22) | (mask_m[20] << 20)
		| (mask_m[22] << 18) | (mask_m[22] << 16)
		| (mask_m[24] << 14) | (mask_m[24] << 12)
		| (mask_m[25] << 10) | (mask_m[26] << 8)
		| (mask_m[27] << 6) | (mask_m[28] << 4)
		| (mask_m[29] << 2) | (mask_m[30] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);

	tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
		| (mask_m[2] << 26) | (mask_m[3] << 24)
		| (mask_m[4] << 22) | (mask_m[5] << 20)
		| (mask_m[6] << 18) | (mask_m[7] << 16)
		| (mask_m[8] << 14) | (mask_m[9] << 12)
		| (mask_m[10] << 10) | (mask_m[11] << 8)
		| (mask_m[12] << 6) | (mask_m[13] << 4)
		| (mask_m[14] << 2) | (mask_m[15] << 0);
	REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);

	tmp_mask = (mask_p[15] << 28)
		| (mask_p[14] << 26) | (mask_p[13] << 24)
		| (mask_p[12] << 22) | (mask_p[11] << 20)
		| (mask_p[10] << 18) | (mask_p[9] << 16)
		| (mask_p[8] << 14) | (mask_p[7] << 12)
		| (mask_p[6] << 10) | (mask_p[5] << 8)
		| (mask_p[4] << 6) | (mask_p[3] << 4)
		| (mask_p[2] << 2) | (mask_p[1] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
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	tmp_mask = (mask_p[30] << 28)
		| (mask_p[29] << 26) | (mask_p[28] << 24)
		| (mask_p[27] << 22) | (mask_p[26] << 20)
		| (mask_p[25] << 18) | (mask_p[24] << 16)
		| (mask_p[23] << 14) | (mask_p[22] << 12)
		| (mask_p[21] << 10) | (mask_p[20] << 8)
		| (mask_p[19] << 6) | (mask_p[18] << 4)
		| (mask_p[17] << 2) | (mask_p[16] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
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	tmp_mask = (mask_p[45] << 28)
		| (mask_p[44] << 26) | (mask_p[43] << 24)
		| (mask_p[42] << 22) | (mask_p[41] << 20)
		| (mask_p[40] << 18) | (mask_p[39] << 16)
		| (mask_p[38] << 14) | (mask_p[37] << 12)
		| (mask_p[36] << 10) | (mask_p[35] << 8)
		| (mask_p[34] << 6) | (mask_p[33] << 4)
		| (mask_p[32] << 2) | (mask_p[31] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
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	tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
		| (mask_p[59] << 26) | (mask_p[58] << 24)
		| (mask_p[57] << 22) | (mask_p[56] << 20)
		| (mask_p[55] << 18) | (mask_p[54] << 16)
		| (mask_p[53] << 14) | (mask_p[52] << 12)
		| (mask_p[51] << 10) | (mask_p[50] << 8)
		| (mask_p[49] << 6) | (mask_p[48] << 4)
		| (mask_p[47] << 2) | (mask_p[46] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
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}

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static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
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{
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	int bb_spur = AR_NO_SPUR;
	int bin, cur_bin;
	int spur_freq_sd;
	int spur_delta_phase;
	int denominator;
	int upper, lower, cur_vit_mask;
	int tmp, new;
	int i;
	int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
			  AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
	};
	int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
			 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
	};
	int inc[4] = { 0, 100, 0, 0 };
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	int8_t mask_m[123];
	int8_t mask_p[123];
	int8_t mask_amt;
	int tmp_mask;
	int cur_bb_spur;
	bool is2GHz = IS_CHAN_2GHZ(chan);
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	memset(&mask_m, 0, sizeof(int8_t) * 123);
	memset(&mask_p, 0, sizeof(int8_t) * 123);
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	for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
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		cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
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		if (AR_NO_SPUR == cur_bb_spur)
			break;
		cur_bb_spur = cur_bb_spur - (chan->channel * 10);
		if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
			bb_spur = cur_bb_spur;
			break;
		}
	}
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	if (AR_NO_SPUR == bb_spur)
		return;
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	bin = bb_spur * 32;
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	tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
	new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
		     AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
		     AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
		     AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
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	REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
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	new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
	       AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
	       AR_PHY_SPUR_REG_MASK_RATE_SELECT |
	       AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
	       SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
	REG_WRITE(ah, AR_PHY_SPUR_REG, new);
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	spur_delta_phase = ((bb_spur * 524288) / 100) &
		AR_PHY_TIMING11_SPUR_DELTA_PHASE;
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	denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
	spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
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	new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
	       SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
	       SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
	REG_WRITE(ah, AR_PHY_TIMING11, new);
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	cur_bin = -6000;
	upper = bin + 100;
	lower = bin - 100;
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	for (i = 0; i < 4; i++) {
		int pilot_mask = 0;
		int chan_mask = 0;
		int bp = 0;
		for (bp = 0; bp < 30; bp++) {
			if ((cur_bin > lower) && (cur_bin < upper)) {
				pilot_mask = pilot_mask | 0x1 << bp;
				chan_mask = chan_mask | 0x1 << bp;
			}
			cur_bin += 100;
		}
		cur_bin += inc[i];
		REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
		REG_WRITE(ah, chan_mask_reg[i], chan_mask);
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	}

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	cur_vit_mask = 6100;
	upper = bin + 120;
	lower = bin - 120;
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	for (i = 0; i < 123; i++) {
		if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
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			/* workaround for gcc bug #37014 */
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			volatile int tmp_v = abs(cur_vit_mask - bin);
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			if (tmp_v < 75)
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				mask_amt = 1;
			else
				mask_amt = 0;
			if (cur_vit_mask < 0)
				mask_m[abs(cur_vit_mask / 100)] = mask_amt;
			else
				mask_p[cur_vit_mask / 100] = mask_amt;
		}
		cur_vit_mask -= 100;
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	}

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	tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
		| (mask_m[48] << 26) | (mask_m[49] << 24)
		| (mask_m[50] << 22) | (mask_m[51] << 20)
		| (mask_m[52] << 18) | (mask_m[53] << 16)
		| (mask_m[54] << 14) | (mask_m[55] << 12)
		| (mask_m[56] << 10) | (mask_m[57] << 8)
		| (mask_m[58] << 6) | (mask_m[59] << 4)
		| (mask_m[60] << 2) | (mask_m[61] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
	REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
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	tmp_mask = (mask_m[31] << 28)
		| (mask_m[32] << 26) | (mask_m[33] << 24)
		| (mask_m[34] << 22) | (mask_m[35] << 20)
		| (mask_m[36] << 18) | (mask_m[37] << 16)
		| (mask_m[48] << 14) | (mask_m[39] << 12)
		| (mask_m[40] << 10) | (mask_m[41] << 8)
		| (mask_m[42] << 6) | (mask_m[43] << 4)
		| (mask_m[44] << 2) | (mask_m[45] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
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	tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
		| (mask_m[18] << 26) | (mask_m[18] << 24)
		| (mask_m[20] << 22) | (mask_m[20] << 20)
		| (mask_m[22] << 18) | (mask_m[22] << 16)
		| (mask_m[24] << 14) | (mask_m[24] << 12)
		| (mask_m[25] << 10) | (mask_m[26] << 8)
		| (mask_m[27] << 6) | (mask_m[28] << 4)
		| (mask_m[29] << 2) | (mask_m[30] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
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	tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
		| (mask_m[2] << 26) | (mask_m[3] << 24)
		| (mask_m[4] << 22) | (mask_m[5] << 20)
		| (mask_m[6] << 18) | (mask_m[7] << 16)
		| (mask_m[8] << 14) | (mask_m[9] << 12)
		| (mask_m[10] << 10) | (mask_m[11] << 8)
		| (mask_m[12] << 6) | (mask_m[13] << 4)
		| (mask_m[14] << 2) | (mask_m[15] << 0);
	REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
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	tmp_mask = (mask_p[15] << 28)
		| (mask_p[14] << 26) | (mask_p[13] << 24)
		| (mask_p[12] << 22) | (mask_p[11] << 20)
		| (mask_p[10] << 18) | (mask_p[9] << 16)
		| (mask_p[8] << 14) | (mask_p[7] << 12)
		| (mask_p[6] << 10) | (mask_p[5] << 8)
		| (mask_p[4] << 6) | (mask_p[3] << 4)
		| (mask_p[2] << 2) | (mask_p[1] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2280

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2281 2282 2283 2284 2285 2286 2287 2288 2289 2290
	tmp_mask = (mask_p[30] << 28)
		| (mask_p[29] << 26) | (mask_p[28] << 24)
		| (mask_p[27] << 22) | (mask_p[26] << 20)
		| (mask_p[25] << 18) | (mask_p[24] << 16)
		| (mask_p[23] << 14) | (mask_p[22] << 12)
		| (mask_p[21] << 10) | (mask_p[20] << 8)
		| (mask_p[19] << 6) | (mask_p[18] << 4)
		| (mask_p[17] << 2) | (mask_p[16] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2291

S
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2292 2293 2294 2295 2296 2297 2298 2299 2300 2301
	tmp_mask = (mask_p[45] << 28)
		| (mask_p[44] << 26) | (mask_p[43] << 24)
		| (mask_p[42] << 22) | (mask_p[41] << 20)
		| (mask_p[40] << 18) | (mask_p[39] << 16)
		| (mask_p[38] << 14) | (mask_p[37] << 12)
		| (mask_p[36] << 10) | (mask_p[35] << 8)
		| (mask_p[34] << 6) | (mask_p[33] << 4)
		| (mask_p[32] << 2) | (mask_p[31] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2302

S
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2303 2304 2305 2306 2307 2308 2309 2310 2311 2312
	tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
		| (mask_p[59] << 26) | (mask_p[58] << 24)
		| (mask_p[57] << 22) | (mask_p[56] << 20)
		| (mask_p[55] << 18) | (mask_p[54] << 16)
		| (mask_p[53] << 14) | (mask_p[52] << 12)
		| (mask_p[51] << 10) | (mask_p[50] << 8)
		| (mask_p[49] << 6) | (mask_p[48] << 4)
		| (mask_p[47] << 2) | (mask_p[46] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2313 2314
}

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Johannes Berg 已提交
2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326
static void ath9k_enable_rfkill(struct ath_hw *ah)
{
	REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
		    AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);

	REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
		    AR_GPIO_INPUT_MUX2_RFSILENT);

	ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
	REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
}

2327
int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2328
		    bool bChannelChange)
2329
{
2330
	struct ath_common *common = ath9k_hw_common(ah);
2331
	u32 saveLedState;
2332
	struct ath9k_channel *curchan = ah->curchan;
2333 2334
	u32 saveDefAntenna;
	u32 macStaId1;
S
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2335
	u64 tsf = 0;
2336
	int i, rx_chainmask, r;
2337

2338 2339
	ah->txchainmask = common->tx_chainmask;
	ah->rxchainmask = common->rx_chainmask;
2340

2341
	if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2342
		return -EIO;
2343

2344
	if (curchan && !ah->chip_fullsleep)
2345 2346 2347
		ath9k_hw_getnf(ah, curchan);

	if (bChannelChange &&
2348 2349 2350
	    (ah->chip_fullsleep != true) &&
	    (ah->curchan != NULL) &&
	    (chan->channel != ah->curchan->channel) &&
2351
	    ((chan->channelFlags & CHANNEL_ALL) ==
2352
	     (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2353 2354
	     !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
	     IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
2355

L
Luis R. Rodriguez 已提交
2356
		if (ath9k_hw_channel_change(ah, chan)) {
2357
			ath9k_hw_loadnf(ah, ah->curchan);
2358
			ath9k_hw_start_nfcal(ah);
2359
			return 0;
2360 2361 2362 2363 2364 2365 2366 2367 2368
		}
	}

	saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
	if (saveDefAntenna == 0)
		saveDefAntenna = 1;

	macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;

S
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2369 2370 2371 2372
	/* For chips on which RTC reset is done, save TSF before it gets cleared */
	if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
		tsf = ath9k_hw_gettsf64(ah);

2373 2374 2375 2376 2377 2378
	saveLedState = REG_READ(ah, AR_CFG_LED) &
		(AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
		 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);

	ath9k_hw_mark_phy_inactive(ah);

2379 2380 2381 2382 2383 2384 2385
	if (AR_SREV_9271(ah) && ah->htc_reset_init) {
		REG_WRITE(ah,
			  AR9271_RESET_POWER_DOWN_CONTROL,
			  AR9271_RADIO_RF_RST);
		udelay(50);
	}

2386
	if (!ath9k_hw_chip_reset(ah, chan)) {
2387
		ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
2388
		return -EINVAL;
2389 2390
	}

2391 2392 2393 2394 2395 2396 2397 2398
	if (AR_SREV_9271(ah) && ah->htc_reset_init) {
		ah->htc_reset_init = false;
		REG_WRITE(ah,
			  AR9271_RESET_POWER_DOWN_CONTROL,
			  AR9271_GATE_MAC_CTL);
		udelay(50);
	}

S
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2399 2400 2401 2402
	/* Restore TSF */
	if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
		ath9k_hw_settsf64(ah, tsf);

2403 2404
	if (AR_SREV_9280_10_OR_LATER(ah))
		REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2405

2406
	if (AR_SREV_9287_12_OR_LATER(ah)) {
2407 2408 2409 2410 2411 2412 2413 2414 2415
		/* Enable ASYNC FIFO */
		REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
				AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
		REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
		REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
				AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
		REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
				AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
	}
L
Luis R. Rodriguez 已提交
2416
	r = ath9k_hw_process_ini(ah, chan);
2417 2418
	if (r)
		return r;
2419

2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436
	/* Setup MFP options for CCMP */
	if (AR_SREV_9280_20_OR_LATER(ah)) {
		/* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
		 * frames when constructing CCMP AAD. */
		REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
			      0xc7ff);
		ah->sw_mgmt_crypto = false;
	} else if (AR_SREV_9160_10_OR_LATER(ah)) {
		/* Disable hardware crypto for management frames */
		REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
			    AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
		REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
			    AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
		ah->sw_mgmt_crypto = true;
	} else
		ah->sw_mgmt_crypto = true;

2437 2438 2439 2440 2441 2442 2443 2444
	if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
		ath9k_hw_set_delta_slope(ah, chan);

	if (AR_SREV_9280_10_OR_LATER(ah))
		ath9k_hw_9280_spur_mitigate(ah, chan);
	else
		ath9k_hw_spur_mitigate(ah, chan);

2445
	ah->eep_ops->set_board_values(ah, chan);
2446 2447 2448

	ath9k_hw_decrease_chain_power(ah, chan);

2449 2450
	REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
	REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
2451 2452
		  | macStaId1
		  | AR_STA_ID1_RTS_USE_DEF
2453
		  | (ah->config.
2454
		     ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2455 2456
		  | ah->sta_id1_defaults);
	ath9k_hw_set_operating_mode(ah, ah->opmode);
2457

2458
	ath_hw_setbssidmask(common);
2459 2460 2461

	REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);

2462
	ath9k_hw_write_associd(ah);
2463 2464 2465 2466 2467

	REG_WRITE(ah, AR_ISR, ~0);

	REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);

2468 2469 2470
	if (AR_SREV_9280_10_OR_LATER(ah))
		ath9k_hw_ar9280_set_channel(ah, chan);
	else
2471 2472
		if (!(ath9k_hw_set_channel(ah, chan)))
			return -EIO;
2473 2474 2475 2476

	for (i = 0; i < AR_NUM_DCU; i++)
		REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);

2477 2478
	ah->intr_txqs = 0;
	for (i = 0; i < ah->caps.total_queues; i++)
2479 2480
		ath9k_hw_resettxqueue(ah, i);

2481
	ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2482 2483
	ath9k_hw_init_qos(ah);

2484
	if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2485
		ath9k_enable_rfkill(ah);
J
Johannes Berg 已提交
2486

2487 2488
	ath9k_hw_init_user_settings(ah);

2489
	if (AR_SREV_9287_12_OR_LATER(ah)) {
2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504
		REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
			  AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
		REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
			  AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
		REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
			  AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);

		REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
		REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);

		REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
			    AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
		REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
			      AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
	}
2505
	if (AR_SREV_9287_12_OR_LATER(ah)) {
2506 2507 2508 2509
		REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
				AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
	}

2510 2511 2512 2513 2514 2515 2516
	REG_WRITE(ah, AR_STA_ID1,
		  REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);

	ath9k_hw_set_dma(ah);

	REG_WRITE(ah, AR_OBS, 8);

2517
	if (ah->config.intr_mitigation) {
2518 2519 2520 2521 2522 2523
		REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
		REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
	}

	ath9k_hw_init_bb(ah, chan);

2524
	if (!ath9k_hw_init_cal(ah, chan))
2525
		return -EIO;
2526

2527
	rx_chainmask = ah->rxchainmask;
2528 2529 2530 2531 2532 2533 2534
	if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
		REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
		REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
	}

	REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);

2535 2536 2537
	/*
	 * For big endian systems turn on swapping for descriptors
	 */
2538 2539 2540 2541
	if (AR_SREV_9100(ah)) {
		u32 mask;
		mask = REG_READ(ah, AR_CFG);
		if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2542
			ath_print(common, ATH_DBG_RESET,
S
Sujith 已提交
2543
				"CFG Byte Swap Set 0x%x\n", mask);
2544 2545 2546 2547
		} else {
			mask =
				INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
			REG_WRITE(ah, AR_CFG, mask);
2548
			ath_print(common, ATH_DBG_RESET,
S
Sujith 已提交
2549
				"Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2550 2551
		}
	} else {
2552 2553 2554
		/* Configure AR9271 target WLAN */
                if (AR_SREV_9271(ah))
			REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
2555
#ifdef __BIG_ENDIAN
2556 2557
                else
			REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2558 2559 2560
#endif
	}

2561
	if (ah->btcoex_hw.enabled)
2562 2563
		ath9k_hw_btcoex_enable(ah);

2564
	return 0;
2565 2566
}

S
Sujith 已提交
2567 2568 2569
/************************/
/* Key Cache Management */
/************************/
2570

2571
bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2572
{
S
Sujith 已提交
2573
	u32 keyType;
2574

2575
	if (entry >= ah->caps.keycache_size) {
2576 2577
		ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
			  "keychache entry %u out of range\n", entry);
2578 2579 2580
		return false;
	}

S
Sujith 已提交
2581
	keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2582

S
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2583 2584 2585 2586 2587 2588 2589 2590
	REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
	REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
	REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
	REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
	REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
	REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
	REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
	REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2591

S
Sujith 已提交
2592 2593
	if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
		u16 micentry = entry + 64;
2594

S
Sujith 已提交
2595 2596 2597 2598
		REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
		REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
		REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
		REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2599 2600 2601 2602 2603 2604

	}

	return true;
}

2605
bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2606
{
S
Sujith 已提交
2607
	u32 macHi, macLo;
2608

2609
	if (entry >= ah->caps.keycache_size) {
2610 2611
		ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
			  "keychache entry %u out of range\n", entry);
S
Sujith 已提交
2612
		return false;
2613 2614
	}

S
Sujith 已提交
2615 2616 2617 2618 2619 2620 2621 2622 2623
	if (mac != NULL) {
		macHi = (mac[5] << 8) | mac[4];
		macLo = (mac[3] << 24) |
			(mac[2] << 16) |
			(mac[1] << 8) |
			mac[0];
		macLo >>= 1;
		macLo |= (macHi & 1) << 31;
		macHi >>= 1;
2624
	} else {
S
Sujith 已提交
2625
		macLo = macHi = 0;
2626
	}
S
Sujith 已提交
2627 2628
	REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
	REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2629

S
Sujith 已提交
2630
	return true;
2631 2632
}

2633
bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
S
Sujith 已提交
2634
				 const struct ath9k_keyval *k,
J
Jouni Malinen 已提交
2635
				 const u8 *mac)
2636
{
2637
	const struct ath9k_hw_capabilities *pCap = &ah->caps;
2638
	struct ath_common *common = ath9k_hw_common(ah);
S
Sujith 已提交
2639 2640
	u32 key0, key1, key2, key3, key4;
	u32 keyType;
2641

S
Sujith 已提交
2642
	if (entry >= pCap->keycache_size) {
2643 2644
		ath_print(common, ATH_DBG_FATAL,
			  "keycache entry %u out of range\n", entry);
S
Sujith 已提交
2645
		return false;
2646 2647
	}

S
Sujith 已提交
2648 2649 2650 2651 2652 2653
	switch (k->kv_type) {
	case ATH9K_CIPHER_AES_OCB:
		keyType = AR_KEYTABLE_TYPE_AES;
		break;
	case ATH9K_CIPHER_AES_CCM:
		if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2654 2655 2656
			ath_print(common, ATH_DBG_ANY,
				  "AES-CCM not supported by mac rev 0x%x\n",
				  ah->hw_version.macRev);
S
Sujith 已提交
2657 2658 2659 2660 2661 2662 2663 2664
			return false;
		}
		keyType = AR_KEYTABLE_TYPE_CCM;
		break;
	case ATH9K_CIPHER_TKIP:
		keyType = AR_KEYTABLE_TYPE_TKIP;
		if (ATH9K_IS_MIC_ENABLED(ah)
		    && entry + 64 >= pCap->keycache_size) {
2665 2666
			ath_print(common, ATH_DBG_ANY,
				  "entry %u inappropriate for TKIP\n", entry);
S
Sujith 已提交
2667 2668 2669 2670
			return false;
		}
		break;
	case ATH9K_CIPHER_WEP:
2671
		if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2672 2673
			ath_print(common, ATH_DBG_ANY,
				  "WEP key length %u too small\n", k->kv_len);
S
Sujith 已提交
2674 2675
			return false;
		}
2676
		if (k->kv_len <= WLAN_KEY_LEN_WEP40)
S
Sujith 已提交
2677
			keyType = AR_KEYTABLE_TYPE_40;
2678
		else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
S
Sujith 已提交
2679 2680 2681 2682 2683 2684 2685 2686
			keyType = AR_KEYTABLE_TYPE_104;
		else
			keyType = AR_KEYTABLE_TYPE_128;
		break;
	case ATH9K_CIPHER_CLR:
		keyType = AR_KEYTABLE_TYPE_CLR;
		break;
	default:
2687 2688
		ath_print(common, ATH_DBG_FATAL,
			  "cipher %u not supported\n", k->kv_type);
S
Sujith 已提交
2689
		return false;
2690 2691
	}

J
Jouni Malinen 已提交
2692 2693 2694 2695 2696
	key0 = get_unaligned_le32(k->kv_val + 0);
	key1 = get_unaligned_le16(k->kv_val + 4);
	key2 = get_unaligned_le32(k->kv_val + 6);
	key3 = get_unaligned_le16(k->kv_val + 10);
	key4 = get_unaligned_le32(k->kv_val + 12);
2697
	if (k->kv_len <= WLAN_KEY_LEN_WEP104)
S
Sujith 已提交
2698
		key4 &= 0xff;
2699

2700 2701 2702 2703 2704 2705 2706
	/*
	 * Note: Key cache registers access special memory area that requires
	 * two 32-bit writes to actually update the values in the internal
	 * memory. Consequently, the exact order and pairs used here must be
	 * maintained.
	 */

S
Sujith 已提交
2707 2708
	if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
		u16 micentry = entry + 64;
2709

2710 2711 2712 2713 2714 2715
		/*
		 * Write inverted key[47:0] first to avoid Michael MIC errors
		 * on frames that could be sent or received at the same time.
		 * The correct key will be written in the end once everything
		 * else is ready.
		 */
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2716 2717
		REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
		REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2718 2719

		/* Write key[95:48] */
S
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2720 2721
		REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
		REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2722 2723

		/* Write key[127:96] and key type */
S
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2724 2725
		REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
		REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2726 2727

		/* Write MAC address for the entry */
S
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2728
		(void) ath9k_hw_keysetmac(ah, entry, mac);
2729

2730
		if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742
			/*
			 * TKIP uses two key cache entries:
			 * Michael MIC TX/RX keys in the same key cache entry
			 * (idx = main index + 64):
			 * key0 [31:0] = RX key [31:0]
			 * key1 [15:0] = TX key [31:16]
			 * key1 [31:16] = reserved
			 * key2 [31:0] = RX key [63:32]
			 * key3 [15:0] = TX key [15:0]
			 * key3 [31:16] = reserved
			 * key4 [31:0] = TX key [63:32]
			 */
S
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2743
			u32 mic0, mic1, mic2, mic3, mic4;
2744

S
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2745 2746 2747 2748 2749
			mic0 = get_unaligned_le32(k->kv_mic + 0);
			mic2 = get_unaligned_le32(k->kv_mic + 4);
			mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
			mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
			mic4 = get_unaligned_le32(k->kv_txmic + 4);
2750 2751

			/* Write RX[31:0] and TX[31:16] */
S
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2752 2753
			REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
			REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2754 2755

			/* Write RX[63:32] and TX[15:0] */
S
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2756 2757
			REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
			REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2758 2759

			/* Write TX[63:32] and keyType(reserved) */
S
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2760 2761 2762
			REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
			REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
				  AR_KEYTABLE_TYPE_CLR);
2763

S
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2764
		} else {
2765 2766 2767 2768 2769 2770 2771 2772 2773 2774 2775 2776 2777 2778 2779 2780
			/*
			 * TKIP uses four key cache entries (two for group
			 * keys):
			 * Michael MIC TX/RX keys are in different key cache
			 * entries (idx = main index + 64 for TX and
			 * main index + 32 + 96 for RX):
			 * key0 [31:0] = TX/RX MIC key [31:0]
			 * key1 [31:0] = reserved
			 * key2 [31:0] = TX/RX MIC key [63:32]
			 * key3 [31:0] = reserved
			 * key4 [31:0] = reserved
			 *
			 * Upper layer code will call this function separately
			 * for TX and RX keys when these registers offsets are
			 * used.
			 */
S
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2781
			u32 mic0, mic2;
2782

S
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2783 2784
			mic0 = get_unaligned_le32(k->kv_mic + 0);
			mic2 = get_unaligned_le32(k->kv_mic + 4);
2785 2786

			/* Write MIC key[31:0] */
S
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2787 2788
			REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
			REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2789 2790

			/* Write MIC key[63:32] */
S
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2791 2792
			REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
			REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2793 2794

			/* Write TX[63:32] and keyType(reserved) */
S
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2795 2796 2797 2798
			REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
			REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
				  AR_KEYTABLE_TYPE_CLR);
		}
2799 2800

		/* MAC address registers are reserved for the MIC entry */
S
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2801 2802
		REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
		REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2803 2804 2805 2806 2807 2808

		/*
		 * Write the correct (un-inverted) key[47:0] last to enable
		 * TKIP now that all other registers are set with correct
		 * values.
		 */
S
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2809 2810 2811
		REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
		REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
	} else {
2812
		/* Write key[47:0] */
S
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2813 2814
		REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
		REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2815 2816

		/* Write key[95:48] */
S
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2817 2818
		REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
		REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2819 2820

		/* Write key[127:96] and key type */
S
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2821 2822
		REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
		REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2823

2824
		/* Write MAC address for the entry */
S
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2825 2826
		(void) ath9k_hw_keysetmac(ah, entry, mac);
	}
2827 2828 2829 2830

	return true;
}

2831
bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2832
{
2833
	if (entry < ah->caps.keycache_size) {
S
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2834 2835 2836 2837 2838
		u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
		if (val & AR_KEYTABLE_VALID)
			return true;
	}
	return false;
2839 2840
}

S
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2841 2842 2843 2844
/******************************/
/* Power Management (Chipset) */
/******************************/

2845
static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2846
{
S
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2847 2848 2849 2850 2851 2852
	REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
	if (setChip) {
		REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
			    AR_RTC_FORCE_WAKE_EN);
		if (!AR_SREV_9100(ah))
			REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2853

2854
		REG_CLR_BIT(ah, (AR_RTC_RESET),
S
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2855 2856
			    AR_RTC_RESET_EN);
	}
2857 2858
}

2859
static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2860
{
S
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2861 2862
	REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
	if (setChip) {
2863
		struct ath9k_hw_capabilities *pCap = &ah->caps;
2864

S
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2865 2866 2867 2868 2869 2870
		if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
			REG_WRITE(ah, AR_RTC_FORCE_WAKE,
				  AR_RTC_FORCE_WAKE_ON_INT);
		} else {
			REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
				    AR_RTC_FORCE_WAKE_EN);
2871 2872 2873 2874
		}
	}
}

2875
static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2876
{
S
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2877 2878
	u32 val;
	int i;
2879

S
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2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890
	if (setChip) {
		if ((REG_READ(ah, AR_RTC_STATUS) &
		     AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
			if (ath9k_hw_set_reset_reg(ah,
					   ATH9K_RESET_POWER_ON) != true) {
				return false;
			}
		}
		if (AR_SREV_9100(ah))
			REG_SET_BIT(ah, AR_RTC_RESET,
				    AR_RTC_RESET_EN);
2891

S
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2892 2893 2894
		REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
			    AR_RTC_FORCE_WAKE_EN);
		udelay(50);
2895

S
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2896 2897 2898 2899 2900 2901 2902
		for (i = POWER_UP_TIME / 50; i > 0; i--) {
			val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
			if (val == AR_RTC_STATUS_ON)
				break;
			udelay(50);
			REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
				    AR_RTC_FORCE_WAKE_EN);
2903
		}
S
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2904
		if (i == 0) {
2905 2906 2907
			ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
				  "Failed to wakeup in %uus\n",
				  POWER_UP_TIME / 20);
S
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2908
			return false;
2909 2910 2911
		}
	}

S
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2912
	REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2913

S
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2914
	return true;
2915 2916
}

2917
bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2918
{
2919
	struct ath_common *common = ath9k_hw_common(ah);
2920
	int status = true, setChip = true;
S
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2921 2922 2923 2924 2925 2926 2927
	static const char *modes[] = {
		"AWAKE",
		"FULL-SLEEP",
		"NETWORK SLEEP",
		"UNDEFINED"
	};

2928 2929 2930
	if (ah->power_mode == mode)
		return status;

2931 2932
	ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
		  modes[ah->power_mode], modes[mode]);
S
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2933 2934 2935 2936 2937 2938 2939

	switch (mode) {
	case ATH9K_PM_AWAKE:
		status = ath9k_hw_set_power_awake(ah, setChip);
		break;
	case ATH9K_PM_FULL_SLEEP:
		ath9k_set_power_sleep(ah, setChip);
2940
		ah->chip_fullsleep = true;
S
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2941 2942 2943 2944
		break;
	case ATH9K_PM_NETWORK_SLEEP:
		ath9k_set_power_network_sleep(ah, setChip);
		break;
2945
	default:
2946 2947
		ath_print(common, ATH_DBG_FATAL,
			  "Unknown power mode %u\n", mode);
2948 2949
		return false;
	}
2950
	ah->power_mode = mode;
S
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2951 2952

	return status;
2953 2954
}

2955 2956 2957 2958 2959 2960 2961 2962 2963
/*
 * Helper for ASPM support.
 *
 * Disable PLL when in L0s as well as receiver clock when in L1.
 * This power saving option must be enabled through the SerDes.
 *
 * Programming the SerDes must go through the same 288 bit serial shift
 * register as the other analog registers.  Hence the 9 writes.
 */
V
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2964
void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
2965
{
S
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2966
	u8 i;
V
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2967
	u32 val;
2968

2969
	if (ah->is_pciexpress != true)
S
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2970
		return;
2971

2972
	/* Do not touch SerDes registers */
2973
	if (ah->config.pcie_powersave_enable == 2)
S
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2974 2975
		return;

2976
	/* Nothing to do on restore for 11N */
V
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2977 2978 2979 2980 2981 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991 2992 2993 2994 2995 2996 2997 2998 2999 3000 3001 3002
	if (!restore) {
		if (AR_SREV_9280_20_OR_LATER(ah)) {
			/*
			 * AR9280 2.0 or later chips use SerDes values from the
			 * initvals.h initialized depending on chipset during
			 * ath9k_hw_init()
			 */
			for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
				REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
					  INI_RA(&ah->iniPcieSerdes, i, 1));
			}
		} else if (AR_SREV_9280(ah) &&
			   (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
			REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
			REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);

			/* RX shut off when elecidle is asserted */
			REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
			REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
			REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);

			/* Shut off CLKREQ active in L1 */
			if (ah->config.pcie_clock_req)
				REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
			else
				REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
S
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3003

V
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3004 3005 3006
			REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
			REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
			REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
S
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3007

V
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3008 3009
			/* Load the new settings */
			REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
S
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3010

V
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3011 3012 3013
		} else {
			REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
			REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
S
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3014

V
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3015 3016 3017 3018
			/* RX shut off when elecidle is asserted */
			REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
			REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
			REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
S
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3019

V
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3020 3021 3022 3023 3024
			/*
			 * Ignore ah->ah_config.pcie_clock_req setting for
			 * pre-AR9280 11n
			 */
			REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
3025

V
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3026 3027 3028
			REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
			REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
			REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
3029

V
Vivek Natarajan 已提交
3030 3031 3032
			/* Load the new settings */
			REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
		}
3033

V
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3034
		udelay(1000);
3035

V
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3036 3037
		/* set bit 19 to allow forcing of pcie core into L1 state */
		REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
3038

V
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3039 3040 3041 3042 3043 3044 3045 3046 3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057 3058 3059 3060
		/* Several PCIe massages to ensure proper behaviour */
		if (ah->config.pcie_waen) {
			val = ah->config.pcie_waen;
			if (!power_off)
				val &= (~AR_WA_D3_L1_DISABLE);
		} else {
			if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
			    AR_SREV_9287(ah)) {
				val = AR9285_WA_DEFAULT;
				if (!power_off)
					val &= (~AR_WA_D3_L1_DISABLE);
			} else if (AR_SREV_9280(ah)) {
				/*
				 * On AR9280 chips bit 22 of 0x4004 needs to be
				 * set otherwise card may disappear.
				 */
				val = AR9280_WA_DEFAULT;
				if (!power_off)
					val &= (~AR_WA_D3_L1_DISABLE);
			} else
				val = AR_WA_DEFAULT;
		}
3061

V
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3062 3063
		REG_WRITE(ah, AR_WA, val);
	}
S
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3064

V
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3065
	if (power_off) {
3066
		/*
V
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3067 3068 3069 3070
		 * Set PCIe workaround bits
		 * bit 14 in WA register (disable L1) should only
		 * be set when device enters D3 and be cleared
		 * when device comes back to D0.
3071
		 */
V
Vivek Natarajan 已提交
3072 3073 3074 3075 3076 3077 3078 3079 3080 3081 3082 3083
		if (ah->config.pcie_waen) {
			if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
				REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
		} else {
			if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
			      AR_SREV_9287(ah)) &&
			     (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
			    (AR_SREV_9280(ah) &&
			     (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
				REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
			}
		}
S
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3084
	}
3085 3086
}

S
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3087 3088 3089 3090
/**********************/
/* Interrupt Handling */
/**********************/

3091
bool ath9k_hw_intrpend(struct ath_hw *ah)
3092 3093 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103 3104 3105 3106 3107 3108 3109
{
	u32 host_isr;

	if (AR_SREV_9100(ah))
		return true;

	host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
	if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
		return true;

	host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
	if ((host_isr & AR_INTR_SYNC_DEFAULT)
	    && (host_isr != AR_INTR_SPURIOUS))
		return true;

	return false;
}

3110
bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3111 3112 3113
{
	u32 isr = 0;
	u32 mask2 = 0;
3114
	struct ath9k_hw_capabilities *pCap = &ah->caps;
3115 3116
	u32 sync_cause = 0;
	bool fatal_int = false;
3117
	struct ath_common *common = ath9k_hw_common(ah);
3118 3119 3120 3121 3122 3123 3124 3125 3126

	if (!AR_SREV_9100(ah)) {
		if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
			if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
			    == AR_RTC_STATUS_ON) {
				isr = REG_READ(ah, AR_ISR);
			}
		}

S
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3127 3128
		sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
			AR_INTR_SYNC_DEFAULT;
3129 3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152 3153 3154

		*masked = 0;

		if (!isr && !sync_cause)
			return false;
	} else {
		*masked = 0;
		isr = REG_READ(ah, AR_ISR);
	}

	if (isr) {
		if (isr & AR_ISR_BCNMISC) {
			u32 isr2;
			isr2 = REG_READ(ah, AR_ISR_S2);
			if (isr2 & AR_ISR_S2_TIM)
				mask2 |= ATH9K_INT_TIM;
			if (isr2 & AR_ISR_S2_DTIM)
				mask2 |= ATH9K_INT_DTIM;
			if (isr2 & AR_ISR_S2_DTIMSYNC)
				mask2 |= ATH9K_INT_DTIMSYNC;
			if (isr2 & (AR_ISR_S2_CABEND))
				mask2 |= ATH9K_INT_CABEND;
			if (isr2 & AR_ISR_S2_GTT)
				mask2 |= ATH9K_INT_GTT;
			if (isr2 & AR_ISR_S2_CST)
				mask2 |= ATH9K_INT_CST;
3155 3156
			if (isr2 & AR_ISR_S2_TSFOOR)
				mask2 |= ATH9K_INT_TSFOOR;
3157 3158 3159 3160 3161 3162 3163 3164 3165 3166
		}

		isr = REG_READ(ah, AR_ISR_RAC);
		if (isr == 0xffffffff) {
			*masked = 0;
			return false;
		}

		*masked = isr & ATH9K_INT_COMMON;

3167
		if (ah->config.intr_mitigation) {
3168 3169 3170 3171 3172 3173 3174 3175 3176 3177 3178 3179 3180 3181
			if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
				*masked |= ATH9K_INT_RX;
		}

		if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
			*masked |= ATH9K_INT_RX;
		if (isr &
		    (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
		     AR_ISR_TXEOL)) {
			u32 s0_s, s1_s;

			*masked |= ATH9K_INT_TX;

			s0_s = REG_READ(ah, AR_ISR_S0_S);
3182 3183
			ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
			ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
3184 3185

			s1_s = REG_READ(ah, AR_ISR_S1_S);
3186 3187
			ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
			ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
3188 3189 3190
		}

		if (isr & AR_ISR_RXORN) {
3191 3192
			ath_print(common, ATH_DBG_INTERRUPT,
				  "receive FIFO overrun interrupt\n");
3193 3194 3195
		}

		if (!AR_SREV_9100(ah)) {
3196
			if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3197 3198 3199 3200 3201 3202 3203 3204
				u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
				if (isr5 & AR_ISR_S5_TIM_TIMER)
					*masked |= ATH9K_INT_TIM_TIMER;
			}
		}

		*masked |= mask2;
	}
S
Sujith 已提交
3205

3206 3207
	if (AR_SREV_9100(ah))
		return true;
S
Sujith 已提交
3208

3209 3210 3211 3212 3213 3214 3215 3216 3217 3218 3219 3220 3221 3222 3223 3224 3225
	if (isr & AR_ISR_GENTMR) {
		u32 s5_s;

		s5_s = REG_READ(ah, AR_ISR_S5_S);
		if (isr & AR_ISR_GENTMR) {
			ah->intr_gen_timer_trigger =
				MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);

			ah->intr_gen_timer_thresh =
				MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);

			if (ah->intr_gen_timer_trigger)
				*masked |= ATH9K_INT_GENTIMER;

		}
	}

3226 3227 3228 3229 3230 3231 3232 3233
	if (sync_cause) {
		fatal_int =
			(sync_cause &
			 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
			? true : false;

		if (fatal_int) {
			if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
3234 3235
				ath_print(common, ATH_DBG_ANY,
					  "received PCI FATAL interrupt\n");
3236 3237
			}
			if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
3238 3239
				ath_print(common, ATH_DBG_ANY,
					  "received PCI PERR interrupt\n");
3240
			}
3241
			*masked |= ATH9K_INT_FATAL;
3242 3243
		}
		if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
3244 3245
			ath_print(common, ATH_DBG_INTERRUPT,
				  "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
3246 3247 3248 3249 3250
			REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
			REG_WRITE(ah, AR_RC, 0);
			*masked |= ATH9K_INT_FATAL;
		}
		if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3251 3252
			ath_print(common, ATH_DBG_INTERRUPT,
				  "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3253 3254 3255 3256 3257
		}

		REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
		(void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
	}
S
Sujith 已提交
3258

3259 3260 3261
	return true;
}

3262
enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3263
{
3264
	u32 omask = ah->mask_reg;
3265
	u32 mask, mask2;
3266
	struct ath9k_hw_capabilities *pCap = &ah->caps;
3267
	struct ath_common *common = ath9k_hw_common(ah);
3268

3269
	ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3270 3271

	if (omask & ATH9K_INT_GLOBAL) {
3272
		ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
3273 3274 3275 3276 3277 3278 3279 3280 3281 3282 3283 3284 3285 3286 3287
		REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
		(void) REG_READ(ah, AR_IER);
		if (!AR_SREV_9100(ah)) {
			REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
			(void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);

			REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
			(void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
		}
	}

	mask = ints & ATH9K_INT_COMMON;
	mask2 = 0;

	if (ints & ATH9K_INT_TX) {
3288
		if (ah->txok_interrupt_mask)
3289
			mask |= AR_IMR_TXOK;
3290
		if (ah->txdesc_interrupt_mask)
3291
			mask |= AR_IMR_TXDESC;
3292
		if (ah->txerr_interrupt_mask)
3293
			mask |= AR_IMR_TXERR;
3294
		if (ah->txeol_interrupt_mask)
3295 3296 3297 3298
			mask |= AR_IMR_TXEOL;
	}
	if (ints & ATH9K_INT_RX) {
		mask |= AR_IMR_RXERR;
3299
		if (ah->config.intr_mitigation)
3300 3301 3302
			mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
		else
			mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3303
		if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3304 3305 3306 3307 3308 3309 3310 3311 3312 3313 3314 3315
			mask |= AR_IMR_GENTMR;
	}

	if (ints & (ATH9K_INT_BMISC)) {
		mask |= AR_IMR_BCNMISC;
		if (ints & ATH9K_INT_TIM)
			mask2 |= AR_IMR_S2_TIM;
		if (ints & ATH9K_INT_DTIM)
			mask2 |= AR_IMR_S2_DTIM;
		if (ints & ATH9K_INT_DTIMSYNC)
			mask2 |= AR_IMR_S2_DTIMSYNC;
		if (ints & ATH9K_INT_CABEND)
3316 3317 3318
			mask2 |= AR_IMR_S2_CABEND;
		if (ints & ATH9K_INT_TSFOOR)
			mask2 |= AR_IMR_S2_TSFOOR;
3319 3320 3321 3322 3323 3324 3325 3326 3327 3328
	}

	if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
		mask |= AR_IMR_BCNMISC;
		if (ints & ATH9K_INT_GTT)
			mask2 |= AR_IMR_S2_GTT;
		if (ints & ATH9K_INT_CST)
			mask2 |= AR_IMR_S2_CST;
	}

3329
	ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3330 3331 3332 3333 3334 3335 3336 3337 3338
	REG_WRITE(ah, AR_IMR, mask);
	mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
					   AR_IMR_S2_DTIM |
					   AR_IMR_S2_DTIMSYNC |
					   AR_IMR_S2_CABEND |
					   AR_IMR_S2_CABTO |
					   AR_IMR_S2_TSFOOR |
					   AR_IMR_S2_GTT | AR_IMR_S2_CST);
	REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3339
	ah->mask_reg = ints;
3340

3341
	if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3342 3343 3344 3345 3346 3347 3348
		if (ints & ATH9K_INT_TIM_TIMER)
			REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
		else
			REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
	}

	if (ints & ATH9K_INT_GLOBAL) {
3349
		ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
3350 3351 3352 3353 3354 3355 3356 3357 3358 3359 3360 3361
		REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
		if (!AR_SREV_9100(ah)) {
			REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
				  AR_INTR_MAC_IRQ);
			REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);


			REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
				  AR_INTR_SYNC_DEFAULT);
			REG_WRITE(ah, AR_INTR_SYNC_MASK,
				  AR_INTR_SYNC_DEFAULT);
		}
3362 3363
		ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
			  REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3364 3365 3366 3367 3368
	}

	return omask;
}

S
Sujith 已提交
3369 3370 3371 3372
/*******************/
/* Beacon Handling */
/*******************/

3373
void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3374 3375 3376
{
	int flags = 0;

3377
	ah->beacon_interval = beacon_period;
3378

3379
	switch (ah->opmode) {
3380 3381
	case NL80211_IFTYPE_STATION:
	case NL80211_IFTYPE_MONITOR:
3382 3383 3384 3385 3386
		REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
		REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
		REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
		flags |= AR_TBTT_TIMER_EN;
		break;
3387
	case NL80211_IFTYPE_ADHOC:
3388
	case NL80211_IFTYPE_MESH_POINT:
3389 3390 3391 3392
		REG_SET_BIT(ah, AR_TXCFG,
			    AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
		REG_WRITE(ah, AR_NEXT_NDP_TIMER,
			  TU_TO_USEC(next_beacon +
3393 3394
				     (ah->atim_window ? ah->
				      atim_window : 1)));
3395
		flags |= AR_NDP_TIMER_EN;
3396
	case NL80211_IFTYPE_AP:
3397 3398 3399
		REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
		REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
			  TU_TO_USEC(next_beacon -
3400
				     ah->config.
3401
				     dma_beacon_response_time));
3402 3403
		REG_WRITE(ah, AR_NEXT_SWBA,
			  TU_TO_USEC(next_beacon -
3404
				     ah->config.
3405
				     sw_beacon_response_time));
3406 3407 3408
		flags |=
			AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
		break;
3409
	default:
3410 3411 3412
		ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
			  "%s: unsupported opmode: %d\n",
			  __func__, ah->opmode);
3413 3414
		return;
		break;
3415 3416 3417 3418 3419 3420 3421 3422 3423 3424 3425 3426 3427 3428 3429 3430
	}

	REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
	REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
	REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
	REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));

	beacon_period &= ~ATH9K_BEACON_ENA;
	if (beacon_period & ATH9K_BEACON_RESET_TSF) {
		beacon_period &= ~ATH9K_BEACON_RESET_TSF;
		ath9k_hw_reset_tsf(ah);
	}

	REG_SET_BIT(ah, AR_TIMER_MODE, flags);
}

3431
void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
S
Sujith 已提交
3432
				    const struct ath9k_beacon_state *bs)
3433 3434
{
	u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3435
	struct ath9k_hw_capabilities *pCap = &ah->caps;
3436
	struct ath_common *common = ath9k_hw_common(ah);
3437 3438 3439 3440 3441 3442 3443 3444 3445 3446 3447 3448 3449 3450 3451 3452 3453 3454 3455 3456 3457 3458 3459 3460 3461

	REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));

	REG_WRITE(ah, AR_BEACON_PERIOD,
		  TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
	REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
		  TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));

	REG_RMW_FIELD(ah, AR_RSSI_THR,
		      AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);

	beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;

	if (bs->bs_sleepduration > beaconintval)
		beaconintval = bs->bs_sleepduration;

	dtimperiod = bs->bs_dtimperiod;
	if (bs->bs_sleepduration > dtimperiod)
		dtimperiod = bs->bs_sleepduration;

	if (beaconintval == dtimperiod)
		nextTbtt = bs->bs_nextdtim;
	else
		nextTbtt = bs->bs_nexttbtt;

3462 3463 3464 3465
	ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
	ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
	ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
	ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3466

S
Sujith 已提交
3467 3468 3469
	REG_WRITE(ah, AR_NEXT_DTIM,
		  TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
	REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3470

S
Sujith 已提交
3471 3472 3473
	REG_WRITE(ah, AR_SLEEP1,
		  SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
		  | AR_SLEEP1_ASSUME_DTIM);
3474

S
Sujith 已提交
3475 3476 3477 3478
	if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
		beacontimeout = (BEACON_TIMEOUT_VAL << 3);
	else
		beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3479

S
Sujith 已提交
3480 3481
	REG_WRITE(ah, AR_SLEEP2,
		  SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3482

S
Sujith 已提交
3483 3484
	REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
	REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3485

S
Sujith 已提交
3486 3487 3488
	REG_SET_BIT(ah, AR_TIMER_MODE,
		    AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
		    AR_DTIM_TIMER_EN);
3489

3490 3491
	/* TSF Out of Range Threshold */
	REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3492 3493
}

S
Sujith 已提交
3494 3495 3496 3497
/*******************/
/* HW Capabilities */
/*******************/

3498
void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3499
{
3500
	struct ath9k_hw_capabilities *pCap = &ah->caps;
3501
	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3502
	struct ath_common *common = ath9k_hw_common(ah);
3503
	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
3504

S
Sujith 已提交
3505
	u16 capField = 0, eeval;
3506

S
Sujith 已提交
3507
	eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3508
	regulatory->current_rd = eeval;
3509

S
Sujith 已提交
3510
	eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3511 3512
	if (AR_SREV_9285_10_OR_LATER(ah))
		eeval |= AR9285_RDEXT_DEFAULT;
3513
	regulatory->current_rd_ext = eeval;
3514

S
Sujith 已提交
3515
	capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
S
Sujith 已提交
3516

3517
	if (ah->opmode != NL80211_IFTYPE_AP &&
3518
	    ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3519 3520 3521 3522 3523
		if (regulatory->current_rd == 0x64 ||
		    regulatory->current_rd == 0x65)
			regulatory->current_rd += 5;
		else if (regulatory->current_rd == 0x41)
			regulatory->current_rd = 0x43;
3524 3525
		ath_print(common, ATH_DBG_REGULATORY,
			  "regdomain mapped to 0x%x\n", regulatory->current_rd);
S
Sujith 已提交
3526
	}
3527

S
Sujith 已提交
3528
	eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
S
Sujith 已提交
3529
	bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3530

S
Sujith 已提交
3531 3532
	if (eeval & AR5416_OPFLAGS_11A) {
		set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3533
		if (ah->config.ht_enable) {
S
Sujith 已提交
3534 3535 3536 3537 3538 3539 3540 3541 3542
			if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
				set_bit(ATH9K_MODE_11NA_HT20,
					pCap->wireless_modes);
			if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
				set_bit(ATH9K_MODE_11NA_HT40PLUS,
					pCap->wireless_modes);
				set_bit(ATH9K_MODE_11NA_HT40MINUS,
					pCap->wireless_modes);
			}
3543 3544 3545
		}
	}

S
Sujith 已提交
3546 3547
	if (eeval & AR5416_OPFLAGS_11G) {
		set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3548
		if (ah->config.ht_enable) {
S
Sujith 已提交
3549 3550 3551 3552 3553 3554 3555 3556 3557 3558
			if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
				set_bit(ATH9K_MODE_11NG_HT20,
					pCap->wireless_modes);
			if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
				set_bit(ATH9K_MODE_11NG_HT40PLUS,
					pCap->wireless_modes);
				set_bit(ATH9K_MODE_11NG_HT40MINUS,
					pCap->wireless_modes);
			}
		}
3559
	}
S
Sujith 已提交
3560

S
Sujith 已提交
3561
	pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3562 3563 3564 3565
	/*
	 * For AR9271 we will temporarilly uses the rx chainmax as read from
	 * the EEPROM.
	 */
3566
	if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3567 3568 3569
	    !(eeval & AR5416_OPFLAGS_11A) &&
	    !(AR_SREV_9271(ah)))
		/* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
3570 3571
		pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
	else
3572
		/* Use rx_chainmask from EEPROM. */
3573
		pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3574

3575
	if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3576
		ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3577

S
Sujith 已提交
3578 3579
	pCap->low_2ghz_chan = 2312;
	pCap->high_2ghz_chan = 2732;
3580

S
Sujith 已提交
3581 3582
	pCap->low_5ghz_chan = 4920;
	pCap->high_5ghz_chan = 6100;
3583

S
Sujith 已提交
3584 3585 3586
	pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
	pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
	pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3587

S
Sujith 已提交
3588 3589 3590
	pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
	pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
	pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3591

3592
	if (ah->config.ht_enable)
S
Sujith 已提交
3593 3594 3595
		pCap->hw_caps |= ATH9K_HW_CAP_HT;
	else
		pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3596

S
Sujith 已提交
3597 3598 3599 3600
	pCap->hw_caps |= ATH9K_HW_CAP_GTT;
	pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
	pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
	pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3601

S
Sujith 已提交
3602 3603 3604 3605 3606
	if (capField & AR_EEPROM_EEPCAP_MAXQCU)
		pCap->total_queues =
			MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
	else
		pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3607

S
Sujith 已提交
3608 3609 3610 3611 3612
	if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
		pCap->keycache_size =
			1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
	else
		pCap->keycache_size = AR_KEYTABLE_SIZE;
3613

S
Sujith 已提交
3614 3615
	pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
	pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3616

3617 3618 3619
	if (AR_SREV_9285_10_OR_LATER(ah))
		pCap->num_gpio_pins = AR9285_NUM_GPIO;
	else if (AR_SREV_9280_10_OR_LATER(ah))
S
Sujith 已提交
3620 3621 3622
		pCap->num_gpio_pins = AR928X_NUM_GPIO;
	else
		pCap->num_gpio_pins = AR_NUM_GPIO;
3623

S
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3624 3625 3626 3627 3628
	if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
		pCap->hw_caps |= ATH9K_HW_CAP_CST;
		pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
	} else {
		pCap->rts_aggr_limit = (8 * 1024);
3629 3630
	}

S
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3631 3632
	pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;

3633
#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3634 3635 3636 3637 3638 3639
	ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
	if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
		ah->rfkill_gpio =
			MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
		ah->rfkill_polarity =
			MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
S
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3640 3641

		pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3642
	}
S
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3643
#endif
3644

3645
	pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3646

3647
	if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
S
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3648 3649 3650
		pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
	else
		pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3651

3652
	if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
S
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3653 3654 3655 3656 3657
		pCap->reg_cap =
			AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
			AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
			AR_EEPROM_EEREGCAP_EN_KK_U2 |
			AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3658
	} else {
S
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3659 3660 3661
		pCap->reg_cap =
			AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
			AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3662 3663
	}

S
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3664 3665 3666
	pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;

	pCap->num_antcfg_5ghz =
S
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3667
		ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
S
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3668
	pCap->num_antcfg_2ghz =
S
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3669
		ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3670

3671
	if (AR_SREV_9280_10_OR_LATER(ah) &&
3672
	    ath9k_hw_btcoex_supported(ah)) {
3673 3674
		btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
		btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
3675

3676
		if (AR_SREV_9285(ah)) {
3677 3678
			btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
			btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
3679
		} else {
3680
			btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
3681
		}
3682
	} else {
3683
		btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
3684
	}
3685 3686
}

3687
bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
S
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3688
			    u32 capability, u32 *result)
3689
{
3690
	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
S
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3691 3692 3693 3694 3695 3696 3697 3698 3699 3700 3701 3702 3703 3704 3705 3706 3707 3708
	switch (type) {
	case ATH9K_CAP_CIPHER:
		switch (capability) {
		case ATH9K_CIPHER_AES_CCM:
		case ATH9K_CIPHER_AES_OCB:
		case ATH9K_CIPHER_TKIP:
		case ATH9K_CIPHER_WEP:
		case ATH9K_CIPHER_MIC:
		case ATH9K_CIPHER_CLR:
			return true;
		default:
			return false;
		}
	case ATH9K_CAP_TKIP_MIC:
		switch (capability) {
		case 0:
			return true;
		case 1:
3709
			return (ah->sta_id1_defaults &
S
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3710 3711 3712 3713
				AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
			false;
		}
	case ATH9K_CAP_TKIP_SPLIT:
3714
		return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
S
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3715 3716 3717 3718 3719 3720 3721 3722 3723 3724 3725 3726 3727
			false : true;
	case ATH9K_CAP_DIVERSITY:
		return (REG_READ(ah, AR_PHY_CCK_DETECT) &
			AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
			true : false;
	case ATH9K_CAP_MCAST_KEYSRCH:
		switch (capability) {
		case 0:
			return true;
		case 1:
			if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
				return false;
			} else {
3728
				return (ah->sta_id1_defaults &
S
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3729 3730 3731 3732 3733 3734 3735 3736 3737 3738
					AR_STA_ID1_MCAST_KSRCH) ? true :
					false;
			}
		}
		return false;
	case ATH9K_CAP_TXPOW:
		switch (capability) {
		case 0:
			return 0;
		case 1:
3739
			*result = regulatory->power_limit;
S
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3740 3741
			return 0;
		case 2:
3742
			*result = regulatory->max_power_level;
S
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3743 3744
			return 0;
		case 3:
3745
			*result = regulatory->tp_scale;
S
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3746 3747 3748
			return 0;
		}
		return false;
3749 3750 3751 3752
	case ATH9K_CAP_DS:
		return (AR_SREV_9280_20_OR_LATER(ah) &&
			(ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
			? false : true;
S
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3753 3754
	default:
		return false;
3755 3756 3757
	}
}

3758
bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
S
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3759
			    u32 capability, u32 setting, int *status)
3760
{
S
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3761
	u32 v;
3762

S
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3763 3764 3765
	switch (type) {
	case ATH9K_CAP_TKIP_MIC:
		if (setting)
3766
			ah->sta_id1_defaults |=
S
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3767 3768
				AR_STA_ID1_CRPT_MIC_ENABLE;
		else
3769
			ah->sta_id1_defaults &=
S
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3770 3771 3772 3773 3774 3775 3776 3777 3778 3779 3780 3781
				~AR_STA_ID1_CRPT_MIC_ENABLE;
		return true;
	case ATH9K_CAP_DIVERSITY:
		v = REG_READ(ah, AR_PHY_CCK_DETECT);
		if (setting)
			v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
		else
			v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
		REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
		return true;
	case ATH9K_CAP_MCAST_KEYSRCH:
		if (setting)
3782
			ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
S
Sujith 已提交
3783
		else
3784
			ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
S
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3785 3786 3787
		return true;
	default:
		return false;
3788 3789 3790
	}
}

S
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3791 3792 3793
/****************************/
/* GPIO / RFKILL / Antennae */
/****************************/
3794

3795
static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
S
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3796 3797 3798 3799
					 u32 gpio, u32 type)
{
	int addr;
	u32 gpio_shift, tmp;
3800

S
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3801 3802 3803 3804 3805 3806
	if (gpio > 11)
		addr = AR_GPIO_OUTPUT_MUX3;
	else if (gpio > 5)
		addr = AR_GPIO_OUTPUT_MUX2;
	else
		addr = AR_GPIO_OUTPUT_MUX1;
3807

S
Sujith 已提交
3808
	gpio_shift = (gpio % 6) * 5;
3809

S
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3810 3811 3812 3813
	if (AR_SREV_9280_20_OR_LATER(ah)
	    || (addr != AR_GPIO_OUTPUT_MUX1)) {
		REG_RMW(ah, addr, (type << gpio_shift),
			(0x1f << gpio_shift));
3814
	} else {
S
Sujith 已提交
3815 3816 3817 3818 3819
		tmp = REG_READ(ah, addr);
		tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
		tmp &= ~(0x1f << gpio_shift);
		tmp |= (type << gpio_shift);
		REG_WRITE(ah, addr, tmp);
3820 3821 3822
	}
}

3823
void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3824
{
S
Sujith 已提交
3825
	u32 gpio_shift;
3826

3827
	BUG_ON(gpio >= ah->caps.num_gpio_pins);
3828

S
Sujith 已提交
3829
	gpio_shift = gpio << 1;
3830

S
Sujith 已提交
3831 3832 3833 3834
	REG_RMW(ah,
		AR_GPIO_OE_OUT,
		(AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
		(AR_GPIO_OE_OUT_DRV << gpio_shift));
3835 3836
}

3837
u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3838
{
3839 3840 3841
#define MS_REG_READ(x, y) \
	(MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))

3842
	if (gpio >= ah->caps.num_gpio_pins)
S
Sujith 已提交
3843
		return 0xffffffff;
3844

3845 3846 3847
	if (AR_SREV_9287_10_OR_LATER(ah))
		return MS_REG_READ(AR9287, gpio) != 0;
	else if (AR_SREV_9285_10_OR_LATER(ah))
3848 3849 3850 3851 3852
		return MS_REG_READ(AR9285, gpio) != 0;
	else if (AR_SREV_9280_10_OR_LATER(ah))
		return MS_REG_READ(AR928X, gpio) != 0;
	else
		return MS_REG_READ(AR, gpio) != 0;
3853 3854
}

3855
void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
S
Sujith 已提交
3856
			 u32 ah_signal_type)
3857
{
S
Sujith 已提交
3858
	u32 gpio_shift;
3859

S
Sujith 已提交
3860
	ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3861

S
Sujith 已提交
3862
	gpio_shift = 2 * gpio;
3863

S
Sujith 已提交
3864 3865 3866 3867
	REG_RMW(ah,
		AR_GPIO_OE_OUT,
		(AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
		(AR_GPIO_OE_OUT_DRV << gpio_shift));
3868 3869
}

3870
void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3871
{
S
Sujith 已提交
3872 3873
	REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
		AR_GPIO_BIT(gpio));
3874 3875
}

3876
u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3877
{
S
Sujith 已提交
3878
	return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3879 3880
}

3881
void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3882
{
S
Sujith 已提交
3883
	REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3884 3885
}

3886
bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
S
Sujith 已提交
3887 3888 3889 3890 3891
			       enum ath9k_ant_setting settings,
			       struct ath9k_channel *chan,
			       u8 *tx_chainmask,
			       u8 *rx_chainmask,
			       u8 *antenna_cfgd)
3892
{
S
Sujith 已提交
3893
	static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3894

S
Sujith 已提交
3895 3896
	if (AR_SREV_9280(ah)) {
		if (!tx_chainmask_cfg) {
3897

S
Sujith 已提交
3898 3899 3900
			tx_chainmask_cfg = *tx_chainmask;
			rx_chainmask_cfg = *rx_chainmask;
		}
3901

S
Sujith 已提交
3902 3903 3904 3905 3906 3907 3908
		switch (settings) {
		case ATH9K_ANT_FIXED_A:
			*tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
			*rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
			*antenna_cfgd = true;
			break;
		case ATH9K_ANT_FIXED_B:
3909
			if (ah->caps.tx_chainmask >
S
Sujith 已提交
3910 3911 3912 3913 3914 3915 3916 3917 3918 3919 3920 3921 3922 3923 3924
			    ATH9K_ANTENNA1_CHAINMASK) {
				*tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
			}
			*rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
			*antenna_cfgd = true;
			break;
		case ATH9K_ANT_VARIABLE:
			*tx_chainmask = tx_chainmask_cfg;
			*rx_chainmask = rx_chainmask_cfg;
			*antenna_cfgd = true;
			break;
		default:
			break;
		}
	} else {
S
Sujith 已提交
3925
		ah->config.diversity_control = settings;
3926 3927
	}

S
Sujith 已提交
3928
	return true;
3929 3930
}

S
Sujith 已提交
3931 3932 3933 3934
/*********************/
/* General Operation */
/*********************/

3935
u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3936
{
S
Sujith 已提交
3937 3938
	u32 bits = REG_READ(ah, AR_RX_FILTER);
	u32 phybits = REG_READ(ah, AR_PHY_ERR);
3939

S
Sujith 已提交
3940 3941 3942 3943
	if (phybits & AR_PHY_ERR_RADAR)
		bits |= ATH9K_RX_FILTER_PHYRADAR;
	if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
		bits |= ATH9K_RX_FILTER_PHYERR;
S
Sujith 已提交
3944

S
Sujith 已提交
3945
	return bits;
3946 3947
}

3948
void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3949
{
S
Sujith 已提交
3950
	u32 phybits;
3951

S
Sujith 已提交
3952 3953
	REG_WRITE(ah, AR_RX_FILTER, bits);

S
Sujith 已提交
3954 3955 3956 3957 3958 3959
	phybits = 0;
	if (bits & ATH9K_RX_FILTER_PHYRADAR)
		phybits |= AR_PHY_ERR_RADAR;
	if (bits & ATH9K_RX_FILTER_PHYERR)
		phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
	REG_WRITE(ah, AR_PHY_ERR, phybits);
3960

S
Sujith 已提交
3961 3962 3963 3964 3965 3966 3967
	if (phybits)
		REG_WRITE(ah, AR_RXCFG,
			  REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
	else
		REG_WRITE(ah, AR_RXCFG,
			  REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
}
3968

3969
bool ath9k_hw_phy_disable(struct ath_hw *ah)
S
Sujith 已提交
3970 3971 3972
{
	return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
}
3973

3974
bool ath9k_hw_disable(struct ath_hw *ah)
S
Sujith 已提交
3975
{
3976
	if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
S
Sujith 已提交
3977
		return false;
3978

S
Sujith 已提交
3979
	return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3980 3981
}

3982
void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3983
{
3984
	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3985
	struct ath9k_channel *chan = ah->curchan;
3986
	struct ieee80211_channel *channel = chan->chan;
3987

3988
	regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
3989

3990
	ah->eep_ops->set_txpower(ah, chan,
3991
				 ath9k_regd_get_ctl(regulatory, chan),
3992 3993 3994
				 channel->max_antenna_gain * 2,
				 channel->max_power * 2,
				 min((u32) MAX_RATE_POWER,
3995
				 (u32) regulatory->power_limit));
3996 3997
}

3998
void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3999
{
4000
	memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
4001 4002
}

4003
void ath9k_hw_setopmode(struct ath_hw *ah)
4004
{
4005
	ath9k_hw_set_operating_mode(ah, ah->opmode);
4006 4007
}

4008
void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
4009
{
S
Sujith 已提交
4010 4011
	REG_WRITE(ah, AR_MCAST_FIL0, filter0);
	REG_WRITE(ah, AR_MCAST_FIL1, filter1);
4012 4013
}

4014
void ath9k_hw_write_associd(struct ath_hw *ah)
4015
{
4016 4017 4018 4019 4020
	struct ath_common *common = ath9k_hw_common(ah);

	REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
	REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
		  ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
4021 4022
}

4023
u64 ath9k_hw_gettsf64(struct ath_hw *ah)
4024
{
S
Sujith 已提交
4025
	u64 tsf;
4026

S
Sujith 已提交
4027 4028
	tsf = REG_READ(ah, AR_TSF_U32);
	tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
4029

S
Sujith 已提交
4030 4031
	return tsf;
}
4032

4033
void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
4034 4035
{
	REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
A
Alina Friedrichsen 已提交
4036
	REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
4037 4038
}

4039
void ath9k_hw_reset_tsf(struct ath_hw *ah)
S
Sujith 已提交
4040
{
4041 4042
	if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
			   AH_TSF_WRITE_TIMEOUT))
4043 4044
		ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
			  "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
4045

S
Sujith 已提交
4046 4047
	REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
}
4048

S
Sujith 已提交
4049
void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
S
Sujith 已提交
4050 4051
{
	if (setting)
4052
		ah->misc_mode |= AR_PCU_TX_ADD_TSF;
S
Sujith 已提交
4053
	else
4054
		ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
S
Sujith 已提交
4055
}
4056

4057
bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
S
Sujith 已提交
4058 4059
{
	if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
4060 4061
		ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
			  "bad slot time %u\n", us);
4062
		ah->slottime = (u32) -1;
S
Sujith 已提交
4063 4064 4065
		return false;
	} else {
		REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
4066
		ah->slottime = us;
S
Sujith 已提交
4067
		return true;
4068
	}
S
Sujith 已提交
4069 4070
}

L
Luis R. Rodriguez 已提交
4071
void ath9k_hw_set11nmac2040(struct ath_hw *ah)
S
Sujith 已提交
4072
{
L
Luis R. Rodriguez 已提交
4073
	struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
S
Sujith 已提交
4074 4075
	u32 macmode;

L
Luis R. Rodriguez 已提交
4076
	if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
S
Sujith 已提交
4077 4078 4079
		macmode = AR_2040_JOINED_RX_CLEAR;
	else
		macmode = 0;
4080

S
Sujith 已提交
4081
	REG_WRITE(ah, AR_2040_MODE, macmode);
4082
}
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/* HW Generic timers configuration */

static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
{
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
	{AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
				AR_NDP2_TIMER_MODE, 0x0002},
	{AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
				AR_NDP2_TIMER_MODE, 0x0004},
	{AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
				AR_NDP2_TIMER_MODE, 0x0008},
	{AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
				AR_NDP2_TIMER_MODE, 0x0010},
	{AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
				AR_NDP2_TIMER_MODE, 0x0020},
	{AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
				AR_NDP2_TIMER_MODE, 0x0040},
	{AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
				AR_NDP2_TIMER_MODE, 0x0080}
};

/* HW generic timer primitives */

/* compute and clear index of rightmost 1 */
static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
{
	u32 b;

	b = *mask;
	b &= (0-b);
	*mask &= ~b;
	b *= debruijn32;
	b >>= 27;

	return timer_table->gen_timer_index[b];
}

4129
u32 ath9k_hw_gettsf32(struct ath_hw *ah)
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{
	return REG_READ(ah, AR_TSF_L32);
}

struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
					  void (*trigger)(void *),
					  void (*overflow)(void *),
					  void *arg,
					  u8 timer_index)
{
	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
	struct ath_gen_timer *timer;

	timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);

	if (timer == NULL) {
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		ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
			  "Failed to allocate memory"
			  "for hw timer[%d]\n", timer_index);
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		return NULL;
	}

	/* allocate a hardware generic timer slot */
	timer_table->timers[timer_index] = timer;
	timer->index = timer_index;
	timer->trigger = trigger;
	timer->overflow = overflow;
	timer->arg = arg;

	return timer;
}

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void ath9k_hw_gen_timer_start(struct ath_hw *ah,
			      struct ath_gen_timer *timer,
			      u32 timer_next,
			      u32 timer_period)
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{
	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
	u32 tsf;

	BUG_ON(!timer_period);

	set_bit(timer->index, &timer_table->timer_mask.timer_bits);

	tsf = ath9k_hw_gettsf32(ah);

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	ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
		  "curent tsf %x period %x"
		  "timer_next %x\n", tsf, timer_period, timer_next);
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	/*
	 * Pull timer_next forward if the current TSF already passed it
	 * because of software latency
	 */
	if (timer_next < tsf)
		timer_next = tsf + timer_period;

	/*
	 * Program generic timer registers
	 */
	REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
		 timer_next);
	REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
		  timer_period);
	REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
		    gen_tmr_configuration[timer->index].mode_mask);

	/* Enable both trigger and thresh interrupt masks */
	REG_SET_BIT(ah, AR_IMR_S5,
		(SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
		SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
}

4203
void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
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{
	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;

	if ((timer->index < AR_FIRST_NDP_TIMER) ||
		(timer->index >= ATH_MAX_GEN_TIMER)) {
		return;
	}

	/* Clear generic timer enable bits. */
	REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
			gen_tmr_configuration[timer->index].mode_mask);

	/* Disable both trigger and thresh interrupt masks */
	REG_CLR_BIT(ah, AR_IMR_S5,
		(SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
		SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));

	clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
}

void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
{
	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;

	/* free the hardware generic timer slot */
	timer_table->timers[timer->index] = NULL;
	kfree(timer);
}

/*
 * Generic Timer Interrupts handling
 */
void ath_gen_timer_isr(struct ath_hw *ah)
{
	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
	struct ath_gen_timer *timer;
4240
	struct ath_common *common = ath9k_hw_common(ah);
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	u32 trigger_mask, thresh_mask, index;

	/* get hardware generic timer interrupt status */
	trigger_mask = ah->intr_gen_timer_trigger;
	thresh_mask = ah->intr_gen_timer_thresh;
	trigger_mask &= timer_table->timer_mask.val;
	thresh_mask &= timer_table->timer_mask.val;

	trigger_mask &= ~thresh_mask;

	while (thresh_mask) {
		index = rightmost_index(timer_table, &thresh_mask);
		timer = timer_table->timers[index];
		BUG_ON(!timer);
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		ath_print(common, ATH_DBG_HWTIMER,
			  "TSF overflow for Gen timer %d\n", index);
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		timer->overflow(timer->arg);
	}

	while (trigger_mask) {
		index = rightmost_index(timer_table, &trigger_mask);
		timer = timer_table->timers[index];
		BUG_ON(!timer);
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		ath_print(common, ATH_DBG_HWTIMER,
			  "Gen timer[%d] trigger\n", index);
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		timer->trigger(timer->arg);
	}
}