hw.c 119.1 KB
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/*
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 * Copyright (c) 2008-2009 Atheros Communications Inc.
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 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <linux/io.h>
#include <asm/unaligned.h>

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#include "hw.h"
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#include "rc.h"
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#include "initvals.h"

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#define ATH9K_CLOCK_RATE_CCK		22
#define ATH9K_CLOCK_RATE_5GHZ_OFDM	40
#define ATH9K_CLOCK_RATE_2GHZ_OFDM	44
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static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
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static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
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static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
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			      struct ar5416_eeprom_def *pEepData,
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			      u32 reg, u32 value);
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static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
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MODULE_AUTHOR("Atheros Communications");
MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
MODULE_LICENSE("Dual BSD/GPL");

static int __init ath9k_init(void)
{
	return 0;
}
module_init(ath9k_init);

static void __exit ath9k_exit(void)
{
	return;
}
module_exit(ath9k_exit);

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/********************/
/* Helper Functions */
/********************/
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static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
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{
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	struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
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	if (!ah->curchan) /* should really check for CCK instead */
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		return clks / ATH9K_CLOCK_RATE_CCK;
	if (conf->channel->band == IEEE80211_BAND_2GHZ)
		return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
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	return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
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}
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static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
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{
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	struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
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	if (conf_is_ht40(conf))
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		return ath9k_hw_mac_usec(ah, clks) / 2;
	else
		return ath9k_hw_mac_usec(ah, clks);
}
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static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
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{
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	struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
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	if (!ah->curchan) /* should really check for CCK instead */
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		return usecs *ATH9K_CLOCK_RATE_CCK;
	if (conf->channel->band == IEEE80211_BAND_2GHZ)
		return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
	return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
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}

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static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
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{
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	struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
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	if (conf_is_ht40(conf))
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		return ath9k_hw_mac_clks(ah, usecs) * 2;
	else
		return ath9k_hw_mac_clks(ah, usecs);
}
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bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
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{
	int i;

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	BUG_ON(timeout < AH_TIME_QUANTUM);

	for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
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		if ((REG_READ(ah, reg) & mask) == val)
			return true;

		udelay(AH_TIME_QUANTUM);
	}
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	ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
		  "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
		  timeout, reg, REG_READ(ah, reg), mask, val);
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	return false;
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}
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EXPORT_SYMBOL(ath9k_hw_wait);
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u32 ath9k_hw_reverse_bits(u32 val, u32 n)
{
	u32 retval;
	int i;

	for (i = 0, retval = 0; i < n; i++) {
		retval = (retval << 1) | (val & 1);
		val >>= 1;
	}
	return retval;
}

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bool ath9k_get_channel_edges(struct ath_hw *ah,
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			     u16 flags, u16 *low,
			     u16 *high)
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{
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	struct ath9k_hw_capabilities *pCap = &ah->caps;
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	if (flags & CHANNEL_5GHZ) {
		*low = pCap->low_5ghz_chan;
		*high = pCap->high_5ghz_chan;
		return true;
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	}
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	if ((flags & CHANNEL_2GHZ)) {
		*low = pCap->low_2ghz_chan;
		*high = pCap->high_2ghz_chan;
		return true;
	}
	return false;
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}

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u16 ath9k_hw_computetxtime(struct ath_hw *ah,
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			   const struct ath_rate_table *rates,
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			   u32 frameLen, u16 rateix,
			   bool shortPreamble)
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{
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	u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
	u32 kbps;
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	kbps = rates->info[rateix].ratekbps;
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	if (kbps == 0)
		return 0;
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	switch (rates->info[rateix].phy) {
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	case WLAN_RC_PHY_CCK:
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		phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
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		if (shortPreamble && rates->info[rateix].short_preamble)
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			phyTime >>= 1;
		numBits = frameLen << 3;
		txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
		break;
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	case WLAN_RC_PHY_OFDM:
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		if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
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			bitsPerSymbol =	(kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
			numBits = OFDM_PLCP_BITS + (frameLen << 3);
			numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
			txTime = OFDM_SIFS_TIME_QUARTER
				+ OFDM_PREAMBLE_TIME_QUARTER
				+ (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
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		} else if (ah->curchan &&
			   IS_CHAN_HALF_RATE(ah->curchan)) {
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			bitsPerSymbol =	(kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
			numBits = OFDM_PLCP_BITS + (frameLen << 3);
			numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
			txTime = OFDM_SIFS_TIME_HALF +
				OFDM_PREAMBLE_TIME_HALF
				+ (numSymbols * OFDM_SYMBOL_TIME_HALF);
		} else {
			bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
			numBits = OFDM_PLCP_BITS + (frameLen << 3);
			numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
			txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
				+ (numSymbols * OFDM_SYMBOL_TIME);
		}
		break;
	default:
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		ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
			  "Unknown phy %u (rate ix %u)\n",
			  rates->info[rateix].phy, rateix);
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		txTime = 0;
		break;
	}
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	return txTime;
}
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EXPORT_SYMBOL(ath9k_hw_computetxtime);
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void ath9k_hw_get_channel_centers(struct ath_hw *ah,
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				  struct ath9k_channel *chan,
				  struct chan_centers *centers)
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{
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	int8_t extoff;
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	if (!IS_CHAN_HT40(chan)) {
		centers->ctl_center = centers->ext_center =
			centers->synth_center = chan->channel;
		return;
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	}

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	if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
	    (chan->chanmode == CHANNEL_G_HT40PLUS)) {
		centers->synth_center =
			chan->channel + HT40_CHANNEL_CENTER_SHIFT;
		extoff = 1;
	} else {
		centers->synth_center =
			chan->channel - HT40_CHANNEL_CENTER_SHIFT;
		extoff = -1;
	}
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	centers->ctl_center =
		centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
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	/* 25 MHz spacing is supported by hw but not on upper layers */
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	centers->ext_center =
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		centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
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}

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/******************/
/* Chip Revisions */
/******************/

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static void ath9k_hw_read_revisions(struct ath_hw *ah)
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{
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	u32 val;
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	val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
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	if (val == 0xFF) {
		val = REG_READ(ah, AR_SREV);
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		ah->hw_version.macVersion =
			(val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
		ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
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		ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
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	} else {
		if (!AR_SREV_9100(ah))
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			ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
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		ah->hw_version.macRev = val & AR_SREV_REVISION;
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		if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
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			ah->is_pciexpress = true;
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	}
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}

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static int ath9k_hw_get_radiorev(struct ath_hw *ah)
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{
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	u32 val;
	int i;
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	REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
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	for (i = 0; i < 8; i++)
		REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
	val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
	val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
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	return ath9k_hw_reverse_bits(val, 8);
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}

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/************************************/
/* HW Attach, Detach, Init Routines */
/************************************/

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static void ath9k_hw_disablepcie(struct ath_hw *ah)
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{
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	if (AR_SREV_9100(ah))
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		return;
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	REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
	REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
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	REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
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}

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static bool ath9k_hw_chip_test(struct ath_hw *ah)
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{
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	struct ath_common *common = ath9k_hw_common(ah);
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	u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
	u32 regHold[2];
	u32 patternData[4] = { 0x55555555,
			       0xaaaaaaaa,
			       0x66666666,
			       0x99999999 };
	int i, j;
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	for (i = 0; i < 2; i++) {
		u32 addr = regAddr[i];
		u32 wrData, rdData;
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		regHold[i] = REG_READ(ah, addr);
		for (j = 0; j < 0x100; j++) {
			wrData = (j << 16) | j;
			REG_WRITE(ah, addr, wrData);
			rdData = REG_READ(ah, addr);
			if (rdData != wrData) {
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				ath_print(common, ATH_DBG_FATAL,
					  "address test failed "
					  "addr: 0x%08x - wr:0x%08x != "
					  "rd:0x%08x\n",
					  addr, wrData, rdData);
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				return false;
			}
		}
		for (j = 0; j < 4; j++) {
			wrData = patternData[j];
			REG_WRITE(ah, addr, wrData);
			rdData = REG_READ(ah, addr);
			if (wrData != rdData) {
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				ath_print(common, ATH_DBG_FATAL,
					  "address test failed "
					  "addr: 0x%08x - wr:0x%08x != "
					  "rd:0x%08x\n",
					  addr, wrData, rdData);
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				return false;
			}
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		}
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		REG_WRITE(ah, regAddr[i], regHold[i]);
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	}
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	udelay(100);
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	return true;
}

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static const char *ath9k_hw_devname(u16 devid)
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{
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	switch (devid) {
	case AR5416_DEVID_PCI:
		return "Atheros 5416";
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	case AR5416_DEVID_PCIE:
		return "Atheros 5418";
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	case AR9160_DEVID_PCI:
		return "Atheros 9160";
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	case AR5416_AR9100_DEVID:
		return "Atheros 9100";
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	case AR9280_DEVID_PCI:
	case AR9280_DEVID_PCIE:
		return "Atheros 9280";
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	case AR9285_DEVID_PCIE:
		return "Atheros 9285";
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	case AR5416_DEVID_AR9287_PCI:
	case AR5416_DEVID_AR9287_PCIE:
		return "Atheros 9287";
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	}

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	return NULL;
}
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static void ath9k_hw_init_config(struct ath_hw *ah)
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{
	int i;
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	ah->config.dma_beacon_response_time = 2;
	ah->config.sw_beacon_response_time = 10;
	ah->config.additional_swba_backoff = 0;
	ah->config.ack_6mb = 0x0;
	ah->config.cwm_ignore_extcca = 0;
	ah->config.pcie_powersave_enable = 0;
	ah->config.pcie_clock_req = 0;
	ah->config.pcie_waen = 0;
	ah->config.analog_shiftreg = 1;
	ah->config.ht_enable = 1;
	ah->config.ofdm_trig_low = 200;
	ah->config.ofdm_trig_high = 500;
	ah->config.cck_trig_high = 200;
	ah->config.cck_trig_low = 100;
	ah->config.enable_ani = 1;
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	ah->config.diversity_control = ATH9K_ANT_VARIABLE;
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	ah->config.antenna_switch_swap = 0;
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	for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
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		ah->config.spurchans[i][0] = AR_NO_SPUR;
		ah->config.spurchans[i][1] = AR_NO_SPUR;
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	}

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	ah->config.intr_mitigation = true;
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	/*
	 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
	 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
	 * This means we use it for all AR5416 devices, and the few
	 * minor PCI AR9280 devices out there.
	 *
	 * Serialization is required because these devices do not handle
	 * well the case of two concurrent reads/writes due to the latency
	 * involved. During one read/write another read/write can be issued
	 * on another CPU while the previous read/write may still be working
	 * on our hardware, if we hit this case the hardware poops in a loop.
	 * We prevent this by serializing reads and writes.
	 *
	 * This issue is not present on PCI-Express devices or pre-AR5416
	 * devices (legacy, 802.11abg).
	 */
	if (num_possible_cpus() > 1)
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		ah->config.serialize_regmode = SER_REG_MODE_AUTO;
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}
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EXPORT_SYMBOL(ath9k_hw_init);
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static void ath9k_hw_init_defaults(struct ath_hw *ah)
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{
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	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);

	regulatory->country_code = CTRY_DEFAULT;
	regulatory->power_limit = MAX_RATE_POWER;
	regulatory->tp_scale = ATH9K_TP_SCALE_MAX;

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	ah->hw_version.magic = AR5416_MAGIC;
	ah->hw_version.subvendorid = 0;
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	ah->ah_flags = 0;
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	if (ah->hw_version.devid == AR5416_AR9100_DEVID)
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		ah->hw_version.macVersion = AR_SREV_VERSION_9100;
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	if (!AR_SREV_9100(ah))
		ah->ah_flags = AH_USE_EEPROM;

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	ah->atim_window = 0;
	ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
	ah->beacon_interval = 100;
	ah->enable_32kHz_clock = DONT_USE_32KHZ;
	ah->slottime = (u32) -1;
	ah->acktimeout = (u32) -1;
	ah->ctstimeout = (u32) -1;
	ah->globaltxtimeout = (u32) -1;

	ah->gbeacon_rate = 0;
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	ah->power_mode = ATH9K_PM_UNDEFINED;
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}

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static int ath9k_hw_rf_claim(struct ath_hw *ah)
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{
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	u32 val;

	REG_WRITE(ah, AR_PHY(0), 0x00000007);

	val = ath9k_hw_get_radiorev(ah);
	switch (val & AR_RADIO_SREV_MAJOR) {
	case 0:
		val = AR_RAD5133_SREV_MAJOR;
		break;
	case AR_RAD5133_SREV_MAJOR:
	case AR_RAD5122_SREV_MAJOR:
	case AR_RAD2133_SREV_MAJOR:
	case AR_RAD2122_SREV_MAJOR:
		break;
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	default:
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		ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
			  "Radio Chip Rev 0x%02X not supported\n",
			  val & AR_RADIO_SREV_MAJOR);
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		return -EOPNOTSUPP;
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	}

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	ah->hw_version.analog5GhzRev = val;
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	return 0;
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}

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static int ath9k_hw_init_macaddr(struct ath_hw *ah)
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{
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	struct ath_common *common = ath9k_hw_common(ah);
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	u32 sum;
	int i;
	u16 eeval;

	sum = 0;
	for (i = 0; i < 3; i++) {
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		eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
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		sum += eeval;
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		common->macaddr[2 * i] = eeval >> 8;
		common->macaddr[2 * i + 1] = eeval & 0xff;
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	}
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	if (sum == 0 || sum == 0xffff * 3)
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		return -EADDRNOTAVAIL;

	return 0;
}

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static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
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{
	u32 rxgain_type;

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	if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
		rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
511 512

		if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
513
			INIT_INI_ARRAY(&ah->iniModesRxGain,
514 515 516
			ar9280Modes_backoff_13db_rxgain_9280_2,
			ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
		else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
517
			INIT_INI_ARRAY(&ah->iniModesRxGain,
518 519 520
			ar9280Modes_backoff_23db_rxgain_9280_2,
			ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
		else
521
			INIT_INI_ARRAY(&ah->iniModesRxGain,
522 523
			ar9280Modes_original_rxgain_9280_2,
			ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
524
	} else {
525
		INIT_INI_ARRAY(&ah->iniModesRxGain,
526 527
			ar9280Modes_original_rxgain_9280_2,
			ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
528
	}
529 530
}

531
static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
532 533 534
{
	u32 txgain_type;

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535 536
	if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
		txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
537 538

		if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
539
			INIT_INI_ARRAY(&ah->iniModesTxGain,
540 541 542
			ar9280Modes_high_power_tx_gain_9280_2,
			ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
		else
543
			INIT_INI_ARRAY(&ah->iniModesTxGain,
544 545
			ar9280Modes_original_tx_gain_9280_2,
			ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
546
	} else {
547
		INIT_INI_ARRAY(&ah->iniModesTxGain,
548 549
		ar9280Modes_original_tx_gain_9280_2,
		ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
550
	}
551 552
}

553
static int ath9k_hw_post_init(struct ath_hw *ah)
554
{
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555
	int ecode;
556

S
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557
	if (!ath9k_hw_chip_test(ah))
S
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558
		return -ENODEV;
559

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560 561
	ecode = ath9k_hw_rf_claim(ah);
	if (ecode != 0)
562 563
		return ecode;

564
	ecode = ath9k_hw_eeprom_init(ah);
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565 566
	if (ecode != 0)
		return ecode;
567

568 569 570 571
	ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
		  "Eeprom VER: %d, REV: %d\n",
		  ah->eep_ops->get_eeprom_ver(ah),
		  ah->eep_ops->get_eeprom_rev(ah));
572

573 574 575 576 577 578 579 580 581
        if (!AR_SREV_9280_10_OR_LATER(ah)) {
		ecode = ath9k_hw_rf_alloc_ext_banks(ah);
		if (ecode) {
			ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
				  "Failed allocating banks for "
				  "external radio\n");
			return ecode;
		}
	}
582

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583 584
	if (!AR_SREV_9100(ah)) {
		ath9k_hw_ani_setup(ah);
585
		ath9k_hw_ani_init(ah);
586 587 588 589 590
	}

	return 0;
}

591 592 593 594 595 596 597 598 599 600 601 602
static bool ath9k_hw_devid_supported(u16 devid)
{
	switch (devid) {
	case AR5416_DEVID_PCI:
	case AR5416_DEVID_PCIE:
	case AR5416_AR9100_DEVID:
	case AR9160_DEVID_PCI:
	case AR9280_DEVID_PCI:
	case AR9280_DEVID_PCIE:
	case AR9285_DEVID_PCIE:
	case AR5416_DEVID_AR9287_PCI:
	case AR5416_DEVID_AR9287_PCIE:
603
	case AR9271_USB:
604 605 606 607 608 609 610
		return true;
	default:
		break;
	}
	return false;
}

611 612 613 614 615 616 617 618 619 620
static bool ath9k_hw_macversion_supported(u32 macversion)
{
	switch (macversion) {
	case AR_SREV_VERSION_5416_PCI:
	case AR_SREV_VERSION_5416_PCIE:
	case AR_SREV_VERSION_9160:
	case AR_SREV_VERSION_9100:
	case AR_SREV_VERSION_9280:
	case AR_SREV_VERSION_9285:
	case AR_SREV_VERSION_9287:
621
	case AR_SREV_VERSION_9271:
622
		return true;
623 624 625 626 627 628
	default:
		break;
	}
	return false;
}

629
static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
630
{
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631 632
	if (AR_SREV_9160_10_OR_LATER(ah)) {
		if (AR_SREV_9280_10_OR_LATER(ah)) {
633 634
			ah->iq_caldata.calData = &iq_cal_single_sample;
			ah->adcgain_caldata.calData =
S
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635
				&adc_gain_cal_single_sample;
636
			ah->adcdc_caldata.calData =
S
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637
				&adc_dc_cal_single_sample;
638
			ah->adcdc_calinitdata.calData =
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639 640
				&adc_init_dc_cal;
		} else {
641 642
			ah->iq_caldata.calData = &iq_cal_multi_sample;
			ah->adcgain_caldata.calData =
S
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643
				&adc_gain_cal_multi_sample;
644
			ah->adcdc_caldata.calData =
S
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645
				&adc_dc_cal_multi_sample;
646
			ah->adcdc_calinitdata.calData =
S
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647 648
				&adc_init_dc_cal;
		}
649
		ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
S
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650
	}
651
}
652

653 654
static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
{
655
	if (AR_SREV_9271(ah)) {
656 657 658 659 660 661 662
		INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
			       ARRAY_SIZE(ar9271Modes_9271), 6);
		INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
			       ARRAY_SIZE(ar9271Common_9271), 2);
		INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
			       ar9271Modes_9271_1_0_only,
			       ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
663 664 665
		return;
	}

666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695
	if (AR_SREV_9287_11_OR_LATER(ah)) {
		INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
				ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
		INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
				ARRAY_SIZE(ar9287Common_9287_1_1), 2);
		if (ah->config.pcie_clock_req)
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
			ar9287PciePhy_clkreq_off_L1_9287_1_1,
			ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
		else
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
			ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
			ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
					2);
	} else if (AR_SREV_9287_10_OR_LATER(ah)) {
		INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
				ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
		INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
				ARRAY_SIZE(ar9287Common_9287_1_0), 2);

		if (ah->config.pcie_clock_req)
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
			ar9287PciePhy_clkreq_off_L1_9287_1_0,
			ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
		else
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
			ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
			ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
				  2);
	} else if (AR_SREV_9285_12_OR_LATER(ah)) {
696

697

698
		INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
699
			       ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
700
		INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
701 702
			       ARRAY_SIZE(ar9285Common_9285_1_2), 2);

703 704
		if (ah->config.pcie_clock_req) {
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
705 706 707
			ar9285PciePhy_clkreq_off_L1_9285_1_2,
			ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
		} else {
708
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
709 710 711 712 713
			ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
			ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
				  2);
		}
	} else if (AR_SREV_9285_10_OR_LATER(ah)) {
714
		INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
715
			       ARRAY_SIZE(ar9285Modes_9285), 6);
716
		INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
717 718
			       ARRAY_SIZE(ar9285Common_9285), 2);

719 720
		if (ah->config.pcie_clock_req) {
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
721 722 723
			ar9285PciePhy_clkreq_off_L1_9285,
			ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
		} else {
724
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
725 726 727 728
			ar9285PciePhy_clkreq_always_on_L1_9285,
			ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
		}
	} else if (AR_SREV_9280_20_OR_LATER(ah)) {
729
		INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
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730
			       ARRAY_SIZE(ar9280Modes_9280_2), 6);
731
		INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
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732
			       ARRAY_SIZE(ar9280Common_9280_2), 2);
733

734 735
		if (ah->config.pcie_clock_req) {
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
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			       ar9280PciePhy_clkreq_off_L1_9280,
			       ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
		} else {
739
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
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740 741 742
			       ar9280PciePhy_clkreq_always_on_L1_9280,
			       ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
		}
743
		INIT_INI_ARRAY(&ah->iniModesAdditional,
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744 745 746
			       ar9280Modes_fast_clock_9280_2,
			       ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
	} else if (AR_SREV_9280_10_OR_LATER(ah)) {
747
		INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
S
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748
			       ARRAY_SIZE(ar9280Modes_9280), 6);
749
		INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
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750 751
			       ARRAY_SIZE(ar9280Common_9280), 2);
	} else if (AR_SREV_9160_10_OR_LATER(ah)) {
752
		INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
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753
			       ARRAY_SIZE(ar5416Modes_9160), 6);
754
		INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
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755
			       ARRAY_SIZE(ar5416Common_9160), 2);
756
		INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
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757
			       ARRAY_SIZE(ar5416Bank0_9160), 2);
758
		INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
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759
			       ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
760
		INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
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761
			       ARRAY_SIZE(ar5416Bank1_9160), 2);
762
		INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
S
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763
			       ARRAY_SIZE(ar5416Bank2_9160), 2);
764
		INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
S
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765
			       ARRAY_SIZE(ar5416Bank3_9160), 3);
766
		INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
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767
			       ARRAY_SIZE(ar5416Bank6_9160), 3);
768
		INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
S
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769
			       ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
770
		INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
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771 772
			       ARRAY_SIZE(ar5416Bank7_9160), 2);
		if (AR_SREV_9160_11(ah)) {
773
			INIT_INI_ARRAY(&ah->iniAddac,
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774 775 776
				       ar5416Addac_91601_1,
				       ARRAY_SIZE(ar5416Addac_91601_1), 2);
		} else {
777
			INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
S
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778 779 780
				       ARRAY_SIZE(ar5416Addac_9160), 2);
		}
	} else if (AR_SREV_9100_OR_LATER(ah)) {
781
		INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
S
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782
			       ARRAY_SIZE(ar5416Modes_9100), 6);
783
		INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
S
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784
			       ARRAY_SIZE(ar5416Common_9100), 2);
785
		INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
S
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786
			       ARRAY_SIZE(ar5416Bank0_9100), 2);
787
		INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
S
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788
			       ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
789
		INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
S
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790
			       ARRAY_SIZE(ar5416Bank1_9100), 2);
791
		INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
S
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792
			       ARRAY_SIZE(ar5416Bank2_9100), 2);
793
		INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
S
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794
			       ARRAY_SIZE(ar5416Bank3_9100), 3);
795
		INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
S
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796
			       ARRAY_SIZE(ar5416Bank6_9100), 3);
797
		INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
S
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798
			       ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
799
		INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
S
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800
			       ARRAY_SIZE(ar5416Bank7_9100), 2);
801
		INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
S
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802 803
			       ARRAY_SIZE(ar5416Addac_9100), 2);
	} else {
804
		INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
S
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805
			       ARRAY_SIZE(ar5416Modes), 6);
806
		INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
S
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807
			       ARRAY_SIZE(ar5416Common), 2);
808
		INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
S
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809
			       ARRAY_SIZE(ar5416Bank0), 2);
810
		INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
S
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811
			       ARRAY_SIZE(ar5416BB_RfGain), 3);
812
		INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
S
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813
			       ARRAY_SIZE(ar5416Bank1), 2);
814
		INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
S
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815
			       ARRAY_SIZE(ar5416Bank2), 2);
816
		INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
S
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817
			       ARRAY_SIZE(ar5416Bank3), 3);
818
		INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
S
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819
			       ARRAY_SIZE(ar5416Bank6), 3);
820
		INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
S
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821
			       ARRAY_SIZE(ar5416Bank6TPC), 3);
822
		INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
S
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823
			       ARRAY_SIZE(ar5416Bank7), 2);
824
		INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
S
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825
			       ARRAY_SIZE(ar5416Addac), 2);
826
	}
827
}
828

829 830
static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
{
831
	if (AR_SREV_9287_11_OR_LATER(ah))
832 833 834 835 836 837 838 839 840 841
		INIT_INI_ARRAY(&ah->iniModesRxGain,
		ar9287Modes_rx_gain_9287_1_1,
		ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
	else if (AR_SREV_9287_10(ah))
		INIT_INI_ARRAY(&ah->iniModesRxGain,
		ar9287Modes_rx_gain_9287_1_0,
		ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
	else if (AR_SREV_9280_20(ah))
		ath9k_hw_init_rxgain_ini(ah);

842
	if (AR_SREV_9287_11_OR_LATER(ah)) {
843 844 845 846 847 848 849 850 851 852
		INIT_INI_ARRAY(&ah->iniModesTxGain,
		ar9287Modes_tx_gain_9287_1_1,
		ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
	} else if (AR_SREV_9287_10(ah)) {
		INIT_INI_ARRAY(&ah->iniModesTxGain,
		ar9287Modes_tx_gain_9287_1_0,
		ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
	} else if (AR_SREV_9280_20(ah)) {
		ath9k_hw_init_txgain_ini(ah);
	} else if (AR_SREV_9285_12_OR_LATER(ah)) {
853 854 855 856 857 858 859 860 861 862 863 864 865 866
		u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);

		/* txgain table */
		if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
			INIT_INI_ARRAY(&ah->iniModesTxGain,
			ar9285Modes_high_power_tx_gain_9285_1_2,
			ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
		} else {
			INIT_INI_ARRAY(&ah->iniModesTxGain,
			ar9285Modes_original_tx_gain_9285_1_2,
			ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
		}

	}
867
}
868

869 870 871
static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah)
{
	u32 i, j;
S
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872 873 874 875 876

	if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
	    test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {

		/* EEPROM Fixup */
877 878
		for (i = 0; i < ah->iniModes.ia_rows; i++) {
			u32 reg = INI_RA(&ah->iniModes, i, 0);
879

880 881
			for (j = 1; j < ah->iniModes.ia_columns; j++) {
				u32 val = INI_RA(&ah->iniModes, i, j);
882

883
				INI_RA(&ah->iniModes, i, j) =
884
					ath9k_hw_ini_fixup(ah,
885
							   &ah->eeprom.def,
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886 887
							   reg, val);
			}
888
		}
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889
	}
890 891
}

892
int ath9k_hw_init(struct ath_hw *ah)
893
{
894
	struct ath_common *common = ath9k_hw_common(ah);
895
	int r = 0;
896

897 898 899 900
	if (!ath9k_hw_devid_supported(ah->hw_version.devid)) {
		ath_print(common, ATH_DBG_FATAL,
			  "Unsupported device ID: 0x%0x\n",
			  ah->hw_version.devid);
901
		return -EOPNOTSUPP;
902
	}
903 904 905 906 907

	ath9k_hw_init_defaults(ah);
	ath9k_hw_init_config(ah);

	if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
908 909
		ath_print(common, ATH_DBG_FATAL,
			  "Couldn't reset chip\n");
910
		return -EIO;
911 912
	}

913
	if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
914
		ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
915
		return -EIO;
916 917 918 919 920 921 922 923 924 925 926 927 928
	}

	if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
		if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
		    (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
			ah->config.serialize_regmode =
				SER_REG_MODE_ON;
		} else {
			ah->config.serialize_regmode =
				SER_REG_MODE_OFF;
		}
	}

929
	ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
930 931 932
		ah->config.serialize_regmode);

	if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
933 934 935 936
		ath_print(common, ATH_DBG_FATAL,
			  "Mac Chip Rev 0x%02x.%x is not supported by "
			  "this driver\n", ah->hw_version.macVersion,
			  ah->hw_version.macRev);
937
		return -EOPNOTSUPP;
938 939 940 941 942 943 944
	}

	if (AR_SREV_9100(ah)) {
		ah->iq_caldata.calData = &iq_cal_multi_sample;
		ah->supp_cals = IQ_MISMATCH_CAL;
		ah->is_pciexpress = false;
	}
945 946 947 948

	if (AR_SREV_9271(ah))
		ah->is_pciexpress = false;

949 950 951 952 953 954 955 956 957 958 959
	ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);

	ath9k_hw_init_cal_settings(ah);

	ah->ani_function = ATH9K_ANI_ALL;
	if (AR_SREV_9280_10_OR_LATER(ah))
		ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;

	ath9k_hw_init_mode_regs(ah);

	if (ah->is_pciexpress)
V
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960
		ath9k_hw_configpcipowersave(ah, 0, 0);
961 962 963
	else
		ath9k_hw_disablepcie(ah);

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964 965 966 967 968 969 970 971 972 973
	/* Support for Japan ch.14 (2484) spread */
	if (AR_SREV_9287_11_OR_LATER(ah)) {
		INIT_INI_ARRAY(&ah->iniCckfirNormal,
		       ar9287Common_normal_cck_fir_coeff_92871_1,
		       ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
		INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
		       ar9287Common_japan_2484_cck_fir_coeff_92871_1,
		       ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
	}

974
	r = ath9k_hw_post_init(ah);
975
	if (r)
976
		return r;
977 978 979 980

	ath9k_hw_init_mode_gain_regs(ah);
	ath9k_hw_fill_cap_info(ah);
	ath9k_hw_init_11a_eeprom_fix(ah);
981

982 983
	r = ath9k_hw_init_macaddr(ah);
	if (r) {
984 985
		ath_print(common, ATH_DBG_FATAL,
			  "Failed to initialize MAC address\n");
986
		return r;
987 988
	}

989
	if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
990
		ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
S
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991
	else
992
		ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
993

S
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994
	ath9k_init_nfcal_hist_buffer(ah);
995

996 997
	common->state = ATH_HW_INITIALIZED;

998
	return 0;
999 1000
}

1001
static void ath9k_hw_init_bb(struct ath_hw *ah,
S
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1002
			     struct ath9k_channel *chan)
1003
{
S
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1004
	u32 synthDelay;
1005

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1006
	synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1007
	if (IS_CHAN_B(chan))
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1008 1009 1010
		synthDelay = (4 * synthDelay) / 22;
	else
		synthDelay /= 10;
1011

S
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1012
	REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
1013

S
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1014
	udelay(synthDelay + BASE_ACTIVATE_DELAY);
1015 1016
}

1017
static void ath9k_hw_init_qos(struct ath_hw *ah)
1018
{
S
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1019 1020
	REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
	REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
1021

S
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1022 1023 1024 1025 1026 1027 1028 1029 1030 1031
	REG_WRITE(ah, AR_QOS_NO_ACK,
		  SM(2, AR_QOS_NO_ACK_TWO_BIT) |
		  SM(5, AR_QOS_NO_ACK_BIT_OFF) |
		  SM(0, AR_QOS_NO_ACK_BYTE_OFF));

	REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
	REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
	REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
	REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
	REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1032 1033
}

1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049
static void ath9k_hw_change_target_baud(struct ath_hw *ah, u32 freq, u32 baud)
{
	u32 lcr;
	u32 baud_divider = freq * 1000 * 1000 / 16 / baud;

	lcr = REG_READ(ah , 0x5100c);
	lcr |= 0x80;

	REG_WRITE(ah, 0x5100c, lcr);
	REG_WRITE(ah, 0x51004, (baud_divider >> 8));
	REG_WRITE(ah, 0x51000, (baud_divider & 0xff));

	lcr &= ~0x80;
	REG_WRITE(ah, 0x5100c, lcr);
}

1050
static void ath9k_hw_init_pll(struct ath_hw *ah,
S
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1051
			      struct ath9k_channel *chan)
1052
{
S
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1053
	u32 pll;
1054

S
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1055 1056 1057
	if (AR_SREV_9100(ah)) {
		if (chan && IS_CHAN_5GHZ(chan))
			pll = 0x1450;
1058
		else
S
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1059 1060 1061 1062
			pll = 0x1458;
	} else {
		if (AR_SREV_9280_10_OR_LATER(ah)) {
			pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1063

S
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1064 1065 1066 1067
			if (chan && IS_CHAN_HALF_RATE(chan))
				pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
			else if (chan && IS_CHAN_QUARTER_RATE(chan))
				pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1068

S
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1069 1070
			if (chan && IS_CHAN_5GHZ(chan)) {
				pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1071 1072


S
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1073 1074 1075 1076 1077 1078 1079 1080 1081 1082
				if (AR_SREV_9280_20(ah)) {
					if (((chan->channel % 20) == 0)
					    || ((chan->channel % 10) == 0))
						pll = 0x2850;
					else
						pll = 0x142c;
				}
			} else {
				pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
			}
1083

S
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1084
		} else if (AR_SREV_9160_10_OR_LATER(ah)) {
1085

S
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1086
			pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1087

S
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1088 1089 1090 1091
			if (chan && IS_CHAN_HALF_RATE(chan))
				pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
			else if (chan && IS_CHAN_QUARTER_RATE(chan))
				pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1092

S
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1093 1094 1095 1096 1097 1098
			if (chan && IS_CHAN_5GHZ(chan))
				pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
			else
				pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
		} else {
			pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1099

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1100 1101 1102 1103
			if (chan && IS_CHAN_HALF_RATE(chan))
				pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
			else if (chan && IS_CHAN_QUARTER_RATE(chan))
				pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1104

S
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1105 1106 1107 1108 1109 1110
			if (chan && IS_CHAN_5GHZ(chan))
				pll |= SM(0xa, AR_RTC_PLL_DIV);
			else
				pll |= SM(0xb, AR_RTC_PLL_DIV);
		}
	}
1111
	REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1112

1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132
	/* Switch the core clock for ar9271 to 117Mhz */
	if (AR_SREV_9271(ah)) {
		if ((pll == 0x142c) || (pll == 0x2850) ) {
			udelay(500);
			/* set CLKOBS to output AHB clock */
			REG_WRITE(ah, 0x7020, 0xe);
			/*
			 * 0x304: 117Mhz, ahb_ratio: 1x1
			 * 0x306: 40Mhz, ahb_ratio: 1x1
			 */
			REG_WRITE(ah, 0x50040, 0x304);
			/*
			 * makes adjustments for the baud dividor to keep the
			 * targetted baud rate based on the used core clock.
			 */
			ath9k_hw_change_target_baud(ah, AR9271_CORE_CLOCK,
						    AR9271_TARGET_BAUD_RATE);
		}
	}

S
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1133 1134 1135
	udelay(RTC_PLL_SETTLE_DELAY);

	REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1136 1137
}

1138
static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1139 1140 1141
{
	int rx_chainmask, tx_chainmask;

1142 1143
	rx_chainmask = ah->rxchainmask;
	tx_chainmask = ah->txchainmask;
1144 1145 1146 1147 1148 1149

	switch (rx_chainmask) {
	case 0x5:
		REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
			    AR_PHY_SWAP_ALT_CHAIN);
	case 0x3:
1150
		if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174
			REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
			REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
			break;
		}
	case 0x1:
	case 0x2:
	case 0x7:
		REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
		REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
		break;
	default:
		break;
	}

	REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
	if (tx_chainmask == 0x5) {
		REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
			    AR_PHY_SWAP_ALT_CHAIN);
	}
	if (AR_SREV_9100(ah))
		REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
			  REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
}

1175
static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1176
					  enum nl80211_iftype opmode)
1177
{
1178
	ah->mask_reg = AR_IMR_TXERR |
S
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1179 1180 1181 1182
		AR_IMR_TXURN |
		AR_IMR_RXERR |
		AR_IMR_RXORN |
		AR_IMR_BCNMISC;
1183

1184
	if (ah->config.intr_mitigation)
1185
		ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1186
	else
1187
		ah->mask_reg |= AR_IMR_RXOK;
1188

1189
	ah->mask_reg |= AR_IMR_TXOK;
1190

1191
	if (opmode == NL80211_IFTYPE_AP)
1192
		ah->mask_reg |= AR_IMR_MIB;
1193

1194
	REG_WRITE(ah, AR_IMR, ah->mask_reg);
S
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1195
	REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1196

S
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1197 1198 1199 1200 1201
	if (!AR_SREV_9100(ah)) {
		REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
		REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
		REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
	}
1202 1203
}

1204
static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1205 1206
{
	if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1207 1208
		ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
			  "bad ack timeout %u\n", us);
1209
		ah->acktimeout = (u32) -1;
1210 1211 1212 1213
		return false;
	} else {
		REG_RMW_FIELD(ah, AR_TIME_OUT,
			      AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1214
		ah->acktimeout = us;
1215 1216 1217 1218
		return true;
	}
}

1219
static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1220 1221
{
	if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1222 1223
		ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
			  "bad cts timeout %u\n", us);
1224
		ah->ctstimeout = (u32) -1;
1225 1226 1227 1228
		return false;
	} else {
		REG_RMW_FIELD(ah, AR_TIME_OUT,
			      AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1229
		ah->ctstimeout = us;
1230 1231 1232
		return true;
	}
}
S
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1233

1234
static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1235 1236
{
	if (tu > 0xFFFF) {
1237 1238
		ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
			  "bad global tx timeout %u\n", tu);
1239
		ah->globaltxtimeout = (u32) -1;
1240 1241 1242
		return false;
	} else {
		REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1243
		ah->globaltxtimeout = tu;
1244 1245 1246 1247
		return true;
	}
}

1248
static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1249
{
1250 1251
	ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
		  ah->misc_mode);
1252

1253
	if (ah->misc_mode != 0)
S
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1254
		REG_WRITE(ah, AR_PCU_MISC,
1255 1256 1257 1258 1259 1260 1261 1262 1263
			  REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
	if (ah->slottime != (u32) -1)
		ath9k_hw_setslottime(ah, ah->slottime);
	if (ah->acktimeout != (u32) -1)
		ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
	if (ah->ctstimeout != (u32) -1)
		ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
	if (ah->globaltxtimeout != (u32) -1)
		ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
S
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1264 1265 1266 1267 1268 1269 1270 1271
}

const char *ath9k_hw_probe(u16 vendorid, u16 devid)
{
	return vendorid == ATHEROS_VENDOR_ID ?
		ath9k_hw_devname(devid) : NULL;
}

1272
void ath9k_hw_detach(struct ath_hw *ah)
S
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1273
{
1274 1275 1276 1277 1278
	struct ath_common *common = ath9k_hw_common(ah);

	if (common->state <= ATH_HW_INITIALIZED)
		goto free_hw;

S
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1279
	if (!AR_SREV_9100(ah))
1280
		ath9k_hw_ani_disable(ah);
S
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1281

1282
	ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1283 1284

free_hw:
1285 1286
	if (!AR_SREV_9280_10_OR_LATER(ah))
		ath9k_hw_rf_free_ext_banks(ah);
S
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1287
	kfree(ah);
1288
	ah = NULL;
S
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1289
}
1290
EXPORT_SYMBOL(ath9k_hw_detach);
S
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1291 1292 1293 1294 1295

/*******/
/* INI */
/*******/

1296
static void ath9k_hw_override_ini(struct ath_hw *ah,
S
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1297 1298
				  struct ath9k_channel *chan)
{
1299 1300 1301 1302 1303 1304 1305 1306 1307
	u32 val;

	if (AR_SREV_9271(ah)) {
		/*
		 * Enable spectral scan to solution for issues with stuck
		 * beacons on AR9271 1.0. The beacon stuck issue is not seeon on
		 * AR9271 1.1
		 */
		if (AR_SREV_9271_10(ah)) {
1308 1309
			val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) |
			      AR_PHY_SPECTRAL_SCAN_ENABLE;
1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320
			REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
		}
		else if (AR_SREV_9271_11(ah))
			/*
			 * change AR_PHY_RF_CTL3 setting to fix MAC issue
			 * present on AR9271 1.1
			 */
			REG_WRITE(ah, AR_PHY_RF_CTL3, 0x3a020001);
		return;
	}

1321 1322 1323 1324 1325 1326 1327
	/*
	 * Set the RX_ABORT and RX_DIS and clear if off only after
	 * RXE is set for MAC. This prevents frames with corrupted
	 * descriptor status.
	 */
	REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));

1328 1329 1330 1331 1332 1333 1334 1335 1336
	if (AR_SREV_9280_10_OR_LATER(ah)) {
		val = REG_READ(ah, AR_PCU_MISC_MODE2) &
			       (~AR_PCU_MISC_MODE2_HWWAR1);

		if (AR_SREV_9287_10_OR_LATER(ah))
			val = val & (~AR_PCU_MISC_MODE2_HWWAR2);

		REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
	}
1337

1338
	if (!AR_SREV_5416_20_OR_LATER(ah) ||
S
Sujith 已提交
1339 1340
	    AR_SREV_9280_10_OR_LATER(ah))
		return;
1341 1342 1343 1344
	/*
	 * Disable BB clock gating
	 * Necessary to avoid issues on AR5416 2.0
	 */
S
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1345
	REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1346 1347
}

1348
static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1349
			      struct ar5416_eeprom_def *pEepData,
S
Sujith 已提交
1350
			      u32 reg, u32 value)
1351
{
S
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1352
	struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1353
	struct ath_common *common = ath9k_hw_common(ah);
1354

1355
	switch (ah->hw_version.devid) {
S
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1356 1357
	case AR9280_DEVID_PCI:
		if (reg == 0x7894) {
1358
			ath_print(common, ATH_DBG_EEPROM,
S
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1359 1360 1361 1362
				"ini VAL: %x  EEPROM: %x\n", value,
				(pBase->version & 0xff));

			if ((pBase->version & 0xff) > 0x0a) {
1363 1364 1365
				ath_print(common, ATH_DBG_EEPROM,
					  "PWDCLKIND: %d\n",
					  pBase->pwdclkind);
S
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1366 1367 1368 1369
				value &= ~AR_AN_TOP2_PWDCLKIND;
				value |= AR_AN_TOP2_PWDCLKIND &
					(pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
			} else {
1370 1371
				ath_print(common, ATH_DBG_EEPROM,
					  "PWDCLKIND Earlier Rev\n");
S
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1372 1373
			}

1374 1375
			ath_print(common, ATH_DBG_EEPROM,
				  "final ini VAL: %x\n", value);
S
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1376 1377 1378 1379 1380
		}
		break;
	}

	return value;
1381 1382
}

1383
static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1384 1385 1386
			      struct ar5416_eeprom_def *pEepData,
			      u32 reg, u32 value)
{
1387
	if (ah->eep_map == EEP_MAP_4KBITS)
1388 1389 1390 1391 1392
		return value;
	else
		return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
}

1393 1394 1395 1396
static void ath9k_olc_init(struct ath_hw *ah)
{
	u32 i;

1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411
	if (OLC_FOR_AR9287_10_LATER) {
		REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
				AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
		ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
				AR9287_AN_TXPC0_TXPCMODE,
				AR9287_AN_TXPC0_TXPCMODE_S,
				AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
		udelay(100);
	} else {
		for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
			ah->originalGain[i] =
				MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
						AR_PHY_TX_GAIN);
		ah->PDADCdelta = 0;
	}
1412 1413
}

1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428
static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
			      struct ath9k_channel *chan)
{
	u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);

	if (IS_CHAN_B(chan))
		ctl |= CTL_11B;
	else if (IS_CHAN_G(chan))
		ctl |= CTL_11G;
	else
		ctl |= CTL_11A;

	return ctl;
}

1429
static int ath9k_hw_process_ini(struct ath_hw *ah,
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				struct ath9k_channel *chan)
1431
{
1432
	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1433
	int i, regWrites = 0;
1434
	struct ieee80211_channel *channel = chan->chan;
1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465
	u32 modesIndex, freqIndex;

	switch (chan->chanmode) {
	case CHANNEL_A:
	case CHANNEL_A_HT20:
		modesIndex = 1;
		freqIndex = 1;
		break;
	case CHANNEL_A_HT40PLUS:
	case CHANNEL_A_HT40MINUS:
		modesIndex = 2;
		freqIndex = 1;
		break;
	case CHANNEL_G:
	case CHANNEL_G_HT20:
	case CHANNEL_B:
		modesIndex = 4;
		freqIndex = 2;
		break;
	case CHANNEL_G_HT40PLUS:
	case CHANNEL_G_HT40MINUS:
		modesIndex = 3;
		freqIndex = 2;
		break;

	default:
		return -EINVAL;
	}

	REG_WRITE(ah, AR_PHY(0), 0x00000007);
	REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
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	ah->eep_ops->set_addac(ah, chan);
1467

1468
	if (AR_SREV_5416_22_OR_LATER(ah)) {
1469
		REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1470 1471 1472
	} else {
		struct ar5416IniArray temp;
		u32 addacSize =
1473 1474
			sizeof(u32) * ah->iniAddac.ia_rows *
			ah->iniAddac.ia_columns;
1475

1476 1477
		memcpy(ah->addac5416_21,
		       ah->iniAddac.ia_array, addacSize);
1478

1479
		(ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1480

1481 1482 1483
		temp.ia_array = ah->addac5416_21;
		temp.ia_columns = ah->iniAddac.ia_columns;
		temp.ia_rows = ah->iniAddac.ia_rows;
1484 1485
		REG_WRITE_ARRAY(&temp, 1, regWrites);
	}
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1487 1488
	REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);

1489 1490 1491
	for (i = 0; i < ah->iniModes.ia_rows; i++) {
		u32 reg = INI_RA(&ah->iniModes, i, 0);
		u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1492 1493 1494 1495

		REG_WRITE(ah, reg, val);

		if (reg >= 0x7800 && reg < 0x78a0
1496
		    && ah->config.analog_shiftreg) {
1497 1498 1499 1500 1501 1502
			udelay(100);
		}

		DO_DELAY(regWrites);
	}

1503
	if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1504
		REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1505

1506 1507
	if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
	    AR_SREV_9287_10_OR_LATER(ah))
1508
		REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1509

1510 1511 1512
	for (i = 0; i < ah->iniCommon.ia_rows; i++) {
		u32 reg = INI_RA(&ah->iniCommon, i, 0);
		u32 val = INI_RA(&ah->iniCommon, i, 1);
1513 1514 1515 1516

		REG_WRITE(ah, reg, val);

		if (reg >= 0x7800 && reg < 0x78a0
1517
		    && ah->config.analog_shiftreg) {
1518 1519 1520 1521 1522 1523 1524 1525
			udelay(100);
		}

		DO_DELAY(regWrites);
	}

	ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);

1526 1527 1528 1529
	if (AR_SREV_9271_10(ah))
		REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
				modesIndex, regWrites);

1530
	if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1531
		REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1532 1533 1534 1535
				regWrites);
	}

	ath9k_hw_override_ini(ah, chan);
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	ath9k_hw_set_regs(ah, chan);
1537 1538
	ath9k_hw_init_chain_masks(ah);

1539 1540 1541
	if (OLC_FOR_AR9280_20_LATER)
		ath9k_olc_init(ah);

1542
	ah->eep_ops->set_txpower(ah, chan,
1543
				 ath9k_regd_get_ctl(regulatory, chan),
1544 1545 1546
				 channel->max_antenna_gain * 2,
				 channel->max_power * 2,
				 min((u32) MAX_RATE_POWER,
1547
				 (u32) regulatory->power_limit));
1548 1549

	if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1550 1551
		ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
			  "ar5416SetRfRegs failed\n");
1552 1553 1554 1555 1556 1557
		return -EIO;
	}

	return 0;
}

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/****************************************/
/* Reset and Channel Switching Routines */
/****************************************/

1562
static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1563
{
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1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581
	u32 rfMode = 0;

	if (chan == NULL)
		return;

	rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
		? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;

	if (!AR_SREV_9280_10_OR_LATER(ah))
		rfMode |= (IS_CHAN_5GHZ(chan)) ?
			AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;

	if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
		rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);

	REG_WRITE(ah, AR_PHY_MODE, rfMode);
}

1582
static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
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1583 1584 1585 1586
{
	REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
}

1587
static inline void ath9k_hw_set_dma(struct ath_hw *ah)
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1588 1589 1590
{
	u32 regval;

1591 1592 1593
	/*
	 * set AHB_MODE not to do cacheline prefetches
	*/
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1594 1595 1596
	regval = REG_READ(ah, AR_AHB_MODE);
	REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);

1597 1598 1599
	/*
	 * let mac dma reads be in 128 byte chunks
	 */
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	regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
	REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);

1603 1604 1605 1606 1607
	/*
	 * Restore TX Trigger Level to its pre-reset value.
	 * The initial value depends on whether aggregation is enabled, and is
	 * adjusted whenever underruns are detected.
	 */
1608
	REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
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1609

1610 1611 1612
	/*
	 * let mac dma writes be in 128 byte chunks
	 */
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	regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
	REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);

1616 1617 1618
	/*
	 * Setup receive FIFO threshold to hold off TX activities
	 */
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	REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);

1621 1622 1623 1624
	/*
	 * reduce the number of usable entries in PCU TXBUF to avoid
	 * wrap around issues.
	 */
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1625
	if (AR_SREV_9285(ah)) {
1626 1627 1628 1629
		/* For AR9285 the number of Fifos are reduced to half.
		 * So set the usable tx buf size also to half to
		 * avoid data/delimiter underruns
		 */
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1630 1631
		REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
			  AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1632
	} else if (!AR_SREV_9271(ah)) {
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1633 1634 1635 1636 1637
		REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
			  AR_PCU_TXBUF_CTRL_USABLE_SIZE);
	}
}

1638
static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
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1639 1640 1641 1642 1643 1644
{
	u32 val;

	val = REG_READ(ah, AR_STA_ID1);
	val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
	switch (opmode) {
1645
	case NL80211_IFTYPE_AP:
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		REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
			  | AR_STA_ID1_KSRCH_MODE);
		REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1649
		break;
1650
	case NL80211_IFTYPE_ADHOC:
1651
	case NL80211_IFTYPE_MESH_POINT:
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1652 1653 1654
		REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
			  | AR_STA_ID1_KSRCH_MODE);
		REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1655
		break;
1656 1657
	case NL80211_IFTYPE_STATION:
	case NL80211_IFTYPE_MONITOR:
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1658
		REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1659
		break;
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1660 1661 1662
	}
}

1663
static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
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1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681
						 u32 coef_scaled,
						 u32 *coef_mantissa,
						 u32 *coef_exponent)
{
	u32 coef_exp, coef_man;

	for (coef_exp = 31; coef_exp > 0; coef_exp--)
		if ((coef_scaled >> coef_exp) & 0x1)
			break;

	coef_exp = 14 - (coef_exp - COEF_SCALE_S);

	coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));

	*coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
	*coef_exponent = coef_exp - 16;
}

1682
static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
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1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715
				     struct ath9k_channel *chan)
{
	u32 coef_scaled, ds_coef_exp, ds_coef_man;
	u32 clockMhzScaled = 0x64000000;
	struct chan_centers centers;

	if (IS_CHAN_HALF_RATE(chan))
		clockMhzScaled = clockMhzScaled >> 1;
	else if (IS_CHAN_QUARTER_RATE(chan))
		clockMhzScaled = clockMhzScaled >> 2;

	ath9k_hw_get_channel_centers(ah, chan, &centers);
	coef_scaled = clockMhzScaled / centers.synth_center;

	ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
				      &ds_coef_exp);

	REG_RMW_FIELD(ah, AR_PHY_TIMING3,
		      AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
	REG_RMW_FIELD(ah, AR_PHY_TIMING3,
		      AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);

	coef_scaled = (9 * coef_scaled) / 10;

	ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
				      &ds_coef_exp);

	REG_RMW_FIELD(ah, AR_PHY_HALFGI,
		      AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
	REG_RMW_FIELD(ah, AR_PHY_HALFGI,
		      AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
}

1716
static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
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1717 1718 1719 1720
{
	u32 rst_flags;
	u32 tmpReg;

1721 1722 1723 1724 1725 1726 1727 1728
	if (AR_SREV_9100(ah)) {
		u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
		val &= ~AR_RTC_DERIVED_CLK_PERIOD;
		val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
		REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
		(void)REG_READ(ah, AR_RTC_DERIVED_CLK);
	}

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1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750
	REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
		  AR_RTC_FORCE_WAKE_ON_INT);

	if (AR_SREV_9100(ah)) {
		rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
			AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
	} else {
		tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
		if (tmpReg &
		    (AR_INTR_SYNC_LOCAL_TIMEOUT |
		     AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
			REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
			REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
		} else {
			REG_WRITE(ah, AR_RC, AR_RC_AHB);
		}

		rst_flags = AR_RTC_RC_MAC_WARM;
		if (type == ATH9K_RESET_COLD)
			rst_flags |= AR_RTC_RC_MAC_COLD;
	}

1751
	REG_WRITE(ah, AR_RTC_RC, rst_flags);
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1752 1753
	udelay(50);

1754
	REG_WRITE(ah, AR_RTC_RC, 0);
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1755
	if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1756 1757
		ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
			  "RTC stuck in MAC reset\n");
S
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1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769
		return false;
	}

	if (!AR_SREV_9100(ah))
		REG_WRITE(ah, AR_RC, 0);

	if (AR_SREV_9100(ah))
		udelay(50);

	return true;
}

1770
static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
S
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1771 1772 1773 1774
{
	REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
		  AR_RTC_FORCE_WAKE_ON_INT);

1775 1776 1777
	if (!AR_SREV_9100(ah))
		REG_WRITE(ah, AR_RC, AR_RC_AHB);

1778
	REG_WRITE(ah, AR_RTC_RESET, 0);
1779
	udelay(2);
1780 1781 1782 1783

	if (!AR_SREV_9100(ah))
		REG_WRITE(ah, AR_RC, 0);

1784
	REG_WRITE(ah, AR_RTC_RESET, 1);
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1785 1786 1787 1788

	if (!ath9k_hw_wait(ah,
			   AR_RTC_STATUS,
			   AR_RTC_STATUS_M,
S
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1789 1790
			   AR_RTC_STATUS_ON,
			   AH_WAIT_TIMEOUT)) {
1791 1792
		ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
			  "RTC not waking up\n");
S
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1793
		return false;
1794 1795
	}

S
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1796 1797 1798 1799 1800
	ath9k_hw_read_revisions(ah);

	return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
}

1801
static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
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1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814
{
	REG_WRITE(ah, AR_RTC_FORCE_WAKE,
		  AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);

	switch (type) {
	case ATH9K_RESET_POWER_ON:
		return ath9k_hw_set_reset_power_on(ah);
	case ATH9K_RESET_WARM:
	case ATH9K_RESET_COLD:
		return ath9k_hw_set_reset(ah, type);
	default:
		return false;
	}
1815 1816
}

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1817
static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
1818
{
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1819
	u32 phymode;
1820
	u32 enableDacFifo = 0;
1821

1822 1823 1824 1825
	if (AR_SREV_9285_10_OR_LATER(ah))
		enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
					 AR_PHY_FC_ENABLE_DAC_FIFO);

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1826
	phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1827
		| AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
S
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1828 1829 1830

	if (IS_CHAN_HT40(chan)) {
		phymode |= AR_PHY_FC_DYN2040_EN;
1831

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1832 1833 1834
		if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
		    (chan->chanmode == CHANNEL_G_HT40PLUS))
			phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1835 1836

	}
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1837 1838
	REG_WRITE(ah, AR_PHY_TURBO, phymode);

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1839
	ath9k_hw_set11nmac2040(ah);
1840

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1841 1842
	REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
	REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1843 1844
}

1845
static bool ath9k_hw_chip_reset(struct ath_hw *ah,
S
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1846
				struct ath9k_channel *chan)
1847
{
1848
	if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1849 1850 1851
		if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
			return false;
	} else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
S
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1852
		return false;
1853

1854
	if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
S
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1855
		return false;
1856

1857
	ah->chip_fullsleep = false;
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1858 1859
	ath9k_hw_init_pll(ah, chan);
	ath9k_hw_set_rfmode(ah, chan);
1860

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1861
	return true;
1862 1863
}

1864
static bool ath9k_hw_channel_change(struct ath_hw *ah,
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1865
				    struct ath9k_channel *chan)
1866
{
1867
	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1868
	struct ath_common *common = ath9k_hw_common(ah);
1869
	struct ieee80211_channel *channel = chan->chan;
1870 1871 1872 1873
	u32 synthDelay, qnum;

	for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
		if (ath9k_hw_numtxpending(ah, qnum)) {
1874 1875 1876
			ath_print(common, ATH_DBG_QUEUE,
				  "Transmit frames pending on "
				  "queue %d\n", qnum);
1877 1878 1879 1880 1881 1882
			return false;
		}
	}

	REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
	if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
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			   AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1884 1885
		ath_print(common, ATH_DBG_FATAL,
			  "Could not kill baseband RX\n");
1886 1887 1888
		return false;
	}

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	ath9k_hw_set_regs(ah, chan);
1890 1891

	if (AR_SREV_9280_10_OR_LATER(ah)) {
1892
		ath9k_hw_ar9280_set_channel(ah, chan);
1893 1894
	} else {
		if (!(ath9k_hw_set_channel(ah, chan))) {
1895 1896
			ath_print(common, ATH_DBG_FATAL,
				  "Failed to set channel\n");
1897 1898 1899 1900
			return false;
		}
	}

1901
	ah->eep_ops->set_txpower(ah, chan,
1902
			     ath9k_regd_get_ctl(regulatory, chan),
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			     channel->max_antenna_gain * 2,
			     channel->max_power * 2,
			     min((u32) MAX_RATE_POWER,
1906
			     (u32) regulatory->power_limit));
1907 1908

	synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1909
	if (IS_CHAN_B(chan))
1910 1911 1912 1913 1914 1915 1916 1917
		synthDelay = (4 * synthDelay) / 22;
	else
		synthDelay /= 10;

	udelay(synthDelay + BASE_ACTIVATE_DELAY);

	REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);

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	if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
		ath9k_hw_set_delta_slope(ah, chan);

	if (AR_SREV_9280_10_OR_LATER(ah))
		ath9k_hw_9280_spur_mitigate(ah, chan);
	else
		ath9k_hw_spur_mitigate(ah, chan);

	if (!chan->oneTimeCalsDone)
		chan->oneTimeCalsDone = true;

	return true;
}

1932
static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
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{
	int bb_spur = AR_NO_SPUR;
	int freq;
	int bin, cur_bin;
	int bb_spur_off, spur_subchannel_sd;
	int spur_freq_sd;
	int spur_delta_phase;
	int denominator;
	int upper, lower, cur_vit_mask;
	int tmp, newVal;
	int i;
	int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
			  AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
	};
	int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
			 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
	};
	int inc[4] = { 0, 100, 0, 0 };
	struct chan_centers centers;

	int8_t mask_m[123];
	int8_t mask_p[123];
	int8_t mask_amt;
	int tmp_mask;
	int cur_bb_spur;
	bool is2GHz = IS_CHAN_2GHZ(chan);

	memset(&mask_m, 0, sizeof(int8_t) * 123);
	memset(&mask_p, 0, sizeof(int8_t) * 123);

	ath9k_hw_get_channel_centers(ah, chan, &centers);
	freq = centers.synth_center;

1966
	ah->config.spurmode = SPUR_ENABLE_EEPROM;
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	for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
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		cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
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		if (is2GHz)
			cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
		else
			cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;

		if (AR_NO_SPUR == cur_bb_spur)
			break;
		cur_bb_spur = cur_bb_spur - freq;

		if (IS_CHAN_HT40(chan)) {
			if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
			    (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
				bb_spur = cur_bb_spur;
				break;
			}
		} else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
			   (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
			bb_spur = cur_bb_spur;
			break;
		}
	}

	if (AR_NO_SPUR == bb_spur) {
		REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
			    AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
		return;
	} else {
		REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
			    AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
	}

	bin = bb_spur * 320;

	tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));

	newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
			AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
			AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
			AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
	REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);

	newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
		  AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
		  AR_PHY_SPUR_REG_MASK_RATE_SELECT |
		  AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
		  SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
	REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);

	if (IS_CHAN_HT40(chan)) {
		if (bb_spur < 0) {
			spur_subchannel_sd = 1;
			bb_spur_off = bb_spur + 10;
		} else {
			spur_subchannel_sd = 0;
			bb_spur_off = bb_spur - 10;
		}
	} else {
		spur_subchannel_sd = 0;
		bb_spur_off = bb_spur;
	}

	if (IS_CHAN_HT40(chan))
		spur_delta_phase =
			((bb_spur * 262144) /
			 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
	else
		spur_delta_phase =
			((bb_spur * 524288) /
			 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;

	denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
	spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;

	newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
		  SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
		  SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
	REG_WRITE(ah, AR_PHY_TIMING11, newVal);

	newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
	REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);

	cur_bin = -6000;
	upper = bin + 100;
	lower = bin - 100;

	for (i = 0; i < 4; i++) {
		int pilot_mask = 0;
		int chan_mask = 0;
		int bp = 0;
		for (bp = 0; bp < 30; bp++) {
			if ((cur_bin > lower) && (cur_bin < upper)) {
				pilot_mask = pilot_mask | 0x1 << bp;
				chan_mask = chan_mask | 0x1 << bp;
			}
			cur_bin += 100;
		}
		cur_bin += inc[i];
		REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
		REG_WRITE(ah, chan_mask_reg[i], chan_mask);
	}

	cur_vit_mask = 6100;
	upper = bin + 120;
	lower = bin - 120;

	for (i = 0; i < 123; i++) {
		if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {

			/* workaround for gcc bug #37014 */
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			volatile int tmp_v = abs(cur_vit_mask - bin);
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			if (tmp_v < 75)
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				mask_amt = 1;
			else
				mask_amt = 0;
			if (cur_vit_mask < 0)
				mask_m[abs(cur_vit_mask / 100)] = mask_amt;
			else
				mask_p[cur_vit_mask / 100] = mask_amt;
		}
		cur_vit_mask -= 100;
	}

	tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
		| (mask_m[48] << 26) | (mask_m[49] << 24)
		| (mask_m[50] << 22) | (mask_m[51] << 20)
		| (mask_m[52] << 18) | (mask_m[53] << 16)
		| (mask_m[54] << 14) | (mask_m[55] << 12)
		| (mask_m[56] << 10) | (mask_m[57] << 8)
		| (mask_m[58] << 6) | (mask_m[59] << 4)
		| (mask_m[60] << 2) | (mask_m[61] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
	REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);

	tmp_mask = (mask_m[31] << 28)
		| (mask_m[32] << 26) | (mask_m[33] << 24)
		| (mask_m[34] << 22) | (mask_m[35] << 20)
		| (mask_m[36] << 18) | (mask_m[37] << 16)
		| (mask_m[48] << 14) | (mask_m[39] << 12)
		| (mask_m[40] << 10) | (mask_m[41] << 8)
		| (mask_m[42] << 6) | (mask_m[43] << 4)
		| (mask_m[44] << 2) | (mask_m[45] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);

	tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
		| (mask_m[18] << 26) | (mask_m[18] << 24)
		| (mask_m[20] << 22) | (mask_m[20] << 20)
		| (mask_m[22] << 18) | (mask_m[22] << 16)
		| (mask_m[24] << 14) | (mask_m[24] << 12)
		| (mask_m[25] << 10) | (mask_m[26] << 8)
		| (mask_m[27] << 6) | (mask_m[28] << 4)
		| (mask_m[29] << 2) | (mask_m[30] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);

	tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
		| (mask_m[2] << 26) | (mask_m[3] << 24)
		| (mask_m[4] << 22) | (mask_m[5] << 20)
		| (mask_m[6] << 18) | (mask_m[7] << 16)
		| (mask_m[8] << 14) | (mask_m[9] << 12)
		| (mask_m[10] << 10) | (mask_m[11] << 8)
		| (mask_m[12] << 6) | (mask_m[13] << 4)
		| (mask_m[14] << 2) | (mask_m[15] << 0);
	REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);

	tmp_mask = (mask_p[15] << 28)
		| (mask_p[14] << 26) | (mask_p[13] << 24)
		| (mask_p[12] << 22) | (mask_p[11] << 20)
		| (mask_p[10] << 18) | (mask_p[9] << 16)
		| (mask_p[8] << 14) | (mask_p[7] << 12)
		| (mask_p[6] << 10) | (mask_p[5] << 8)
		| (mask_p[4] << 6) | (mask_p[3] << 4)
		| (mask_p[2] << 2) | (mask_p[1] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
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	tmp_mask = (mask_p[30] << 28)
		| (mask_p[29] << 26) | (mask_p[28] << 24)
		| (mask_p[27] << 22) | (mask_p[26] << 20)
		| (mask_p[25] << 18) | (mask_p[24] << 16)
		| (mask_p[23] << 14) | (mask_p[22] << 12)
		| (mask_p[21] << 10) | (mask_p[20] << 8)
		| (mask_p[19] << 6) | (mask_p[18] << 4)
		| (mask_p[17] << 2) | (mask_p[16] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
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	tmp_mask = (mask_p[45] << 28)
		| (mask_p[44] << 26) | (mask_p[43] << 24)
		| (mask_p[42] << 22) | (mask_p[41] << 20)
		| (mask_p[40] << 18) | (mask_p[39] << 16)
		| (mask_p[38] << 14) | (mask_p[37] << 12)
		| (mask_p[36] << 10) | (mask_p[35] << 8)
		| (mask_p[34] << 6) | (mask_p[33] << 4)
		| (mask_p[32] << 2) | (mask_p[31] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
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	tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
		| (mask_p[59] << 26) | (mask_p[58] << 24)
		| (mask_p[57] << 22) | (mask_p[56] << 20)
		| (mask_p[55] << 18) | (mask_p[54] << 16)
		| (mask_p[53] << 14) | (mask_p[52] << 12)
		| (mask_p[51] << 10) | (mask_p[50] << 8)
		| (mask_p[49] << 6) | (mask_p[48] << 4)
		| (mask_p[47] << 2) | (mask_p[46] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2180 2181
}

2182
static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
2183
{
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	int bb_spur = AR_NO_SPUR;
	int bin, cur_bin;
	int spur_freq_sd;
	int spur_delta_phase;
	int denominator;
	int upper, lower, cur_vit_mask;
	int tmp, new;
	int i;
	int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
			  AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
	};
	int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
			 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
	};
	int inc[4] = { 0, 100, 0, 0 };
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	int8_t mask_m[123];
	int8_t mask_p[123];
	int8_t mask_amt;
	int tmp_mask;
	int cur_bb_spur;
	bool is2GHz = IS_CHAN_2GHZ(chan);
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	memset(&mask_m, 0, sizeof(int8_t) * 123);
	memset(&mask_p, 0, sizeof(int8_t) * 123);
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	for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
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		cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
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		if (AR_NO_SPUR == cur_bb_spur)
			break;
		cur_bb_spur = cur_bb_spur - (chan->channel * 10);
		if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
			bb_spur = cur_bb_spur;
			break;
		}
	}
2220

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	if (AR_NO_SPUR == bb_spur)
		return;
2223

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	bin = bb_spur * 32;
2225

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	tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
	new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
		     AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
		     AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
		     AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
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	REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
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	new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
	       AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
	       AR_PHY_SPUR_REG_MASK_RATE_SELECT |
	       AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
	       SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
	REG_WRITE(ah, AR_PHY_SPUR_REG, new);
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	spur_delta_phase = ((bb_spur * 524288) / 100) &
		AR_PHY_TIMING11_SPUR_DELTA_PHASE;
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	denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
	spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
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	new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
	       SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
	       SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
	REG_WRITE(ah, AR_PHY_TIMING11, new);
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	cur_bin = -6000;
	upper = bin + 100;
	lower = bin - 100;
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	for (i = 0; i < 4; i++) {
		int pilot_mask = 0;
		int chan_mask = 0;
		int bp = 0;
		for (bp = 0; bp < 30; bp++) {
			if ((cur_bin > lower) && (cur_bin < upper)) {
				pilot_mask = pilot_mask | 0x1 << bp;
				chan_mask = chan_mask | 0x1 << bp;
			}
			cur_bin += 100;
		}
		cur_bin += inc[i];
		REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
		REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2270 2271
	}

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	cur_vit_mask = 6100;
	upper = bin + 120;
	lower = bin - 120;
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	for (i = 0; i < 123; i++) {
		if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
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			/* workaround for gcc bug #37014 */
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			volatile int tmp_v = abs(cur_vit_mask - bin);
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			if (tmp_v < 75)
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				mask_amt = 1;
			else
				mask_amt = 0;
			if (cur_vit_mask < 0)
				mask_m[abs(cur_vit_mask / 100)] = mask_amt;
			else
				mask_p[cur_vit_mask / 100] = mask_amt;
		}
		cur_vit_mask -= 100;
2292 2293
	}

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	tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
		| (mask_m[48] << 26) | (mask_m[49] << 24)
		| (mask_m[50] << 22) | (mask_m[51] << 20)
		| (mask_m[52] << 18) | (mask_m[53] << 16)
		| (mask_m[54] << 14) | (mask_m[55] << 12)
		| (mask_m[56] << 10) | (mask_m[57] << 8)
		| (mask_m[58] << 6) | (mask_m[59] << 4)
		| (mask_m[60] << 2) | (mask_m[61] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
	REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
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2305 2306 2307 2308 2309 2310 2311 2312 2313 2314
	tmp_mask = (mask_m[31] << 28)
		| (mask_m[32] << 26) | (mask_m[33] << 24)
		| (mask_m[34] << 22) | (mask_m[35] << 20)
		| (mask_m[36] << 18) | (mask_m[37] << 16)
		| (mask_m[48] << 14) | (mask_m[39] << 12)
		| (mask_m[40] << 10) | (mask_m[41] << 8)
		| (mask_m[42] << 6) | (mask_m[43] << 4)
		| (mask_m[44] << 2) | (mask_m[45] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2315

S
Sujith 已提交
2316 2317 2318 2319 2320 2321 2322 2323 2324 2325
	tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
		| (mask_m[18] << 26) | (mask_m[18] << 24)
		| (mask_m[20] << 22) | (mask_m[20] << 20)
		| (mask_m[22] << 18) | (mask_m[22] << 16)
		| (mask_m[24] << 14) | (mask_m[24] << 12)
		| (mask_m[25] << 10) | (mask_m[26] << 8)
		| (mask_m[27] << 6) | (mask_m[28] << 4)
		| (mask_m[29] << 2) | (mask_m[30] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2326

S
Sujith 已提交
2327 2328 2329 2330 2331 2332 2333 2334 2335 2336
	tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
		| (mask_m[2] << 26) | (mask_m[3] << 24)
		| (mask_m[4] << 22) | (mask_m[5] << 20)
		| (mask_m[6] << 18) | (mask_m[7] << 16)
		| (mask_m[8] << 14) | (mask_m[9] << 12)
		| (mask_m[10] << 10) | (mask_m[11] << 8)
		| (mask_m[12] << 6) | (mask_m[13] << 4)
		| (mask_m[14] << 2) | (mask_m[15] << 0);
	REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2337

S
Sujith 已提交
2338 2339 2340 2341 2342 2343 2344 2345 2346 2347
	tmp_mask = (mask_p[15] << 28)
		| (mask_p[14] << 26) | (mask_p[13] << 24)
		| (mask_p[12] << 22) | (mask_p[11] << 20)
		| (mask_p[10] << 18) | (mask_p[9] << 16)
		| (mask_p[8] << 14) | (mask_p[7] << 12)
		| (mask_p[6] << 10) | (mask_p[5] << 8)
		| (mask_p[4] << 6) | (mask_p[3] << 4)
		| (mask_p[2] << 2) | (mask_p[1] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2348

S
Sujith 已提交
2349 2350 2351 2352 2353 2354 2355 2356 2357 2358
	tmp_mask = (mask_p[30] << 28)
		| (mask_p[29] << 26) | (mask_p[28] << 24)
		| (mask_p[27] << 22) | (mask_p[26] << 20)
		| (mask_p[25] << 18) | (mask_p[24] << 16)
		| (mask_p[23] << 14) | (mask_p[22] << 12)
		| (mask_p[21] << 10) | (mask_p[20] << 8)
		| (mask_p[19] << 6) | (mask_p[18] << 4)
		| (mask_p[17] << 2) | (mask_p[16] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2359

S
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2360 2361 2362 2363 2364 2365 2366 2367 2368 2369
	tmp_mask = (mask_p[45] << 28)
		| (mask_p[44] << 26) | (mask_p[43] << 24)
		| (mask_p[42] << 22) | (mask_p[41] << 20)
		| (mask_p[40] << 18) | (mask_p[39] << 16)
		| (mask_p[38] << 14) | (mask_p[37] << 12)
		| (mask_p[36] << 10) | (mask_p[35] << 8)
		| (mask_p[34] << 6) | (mask_p[33] << 4)
		| (mask_p[32] << 2) | (mask_p[31] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2370

S
Sujith 已提交
2371 2372 2373 2374 2375 2376 2377 2378 2379 2380
	tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
		| (mask_p[59] << 26) | (mask_p[58] << 24)
		| (mask_p[57] << 22) | (mask_p[56] << 20)
		| (mask_p[55] << 18) | (mask_p[54] << 16)
		| (mask_p[53] << 14) | (mask_p[52] << 12)
		| (mask_p[51] << 10) | (mask_p[50] << 8)
		| (mask_p[49] << 6) | (mask_p[48] << 4)
		| (mask_p[47] << 2) | (mask_p[46] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2381 2382
}

J
Johannes Berg 已提交
2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394
static void ath9k_enable_rfkill(struct ath_hw *ah)
{
	REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
		    AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);

	REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
		    AR_GPIO_INPUT_MUX2_RFSILENT);

	ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
	REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
}

2395
int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2396
		    bool bChannelChange)
2397
{
2398
	struct ath_common *common = ath9k_hw_common(ah);
2399
	u32 saveLedState;
2400
	struct ath9k_channel *curchan = ah->curchan;
2401 2402
	u32 saveDefAntenna;
	u32 macStaId1;
S
Sujith 已提交
2403
	u64 tsf = 0;
2404
	int i, rx_chainmask, r;
2405

2406 2407
	ah->txchainmask = common->tx_chainmask;
	ah->rxchainmask = common->rx_chainmask;
2408

2409
	if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2410
		return -EIO;
2411

2412
	if (curchan && !ah->chip_fullsleep)
2413 2414 2415
		ath9k_hw_getnf(ah, curchan);

	if (bChannelChange &&
2416 2417 2418
	    (ah->chip_fullsleep != true) &&
	    (ah->curchan != NULL) &&
	    (chan->channel != ah->curchan->channel) &&
2419
	    ((chan->channelFlags & CHANNEL_ALL) ==
2420
	     (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2421 2422
	     !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
	     IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
2423

L
Luis R. Rodriguez 已提交
2424
		if (ath9k_hw_channel_change(ah, chan)) {
2425
			ath9k_hw_loadnf(ah, ah->curchan);
2426
			ath9k_hw_start_nfcal(ah);
2427
			return 0;
2428 2429 2430 2431 2432 2433 2434 2435 2436
		}
	}

	saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
	if (saveDefAntenna == 0)
		saveDefAntenna = 1;

	macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;

S
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2437 2438 2439 2440
	/* For chips on which RTC reset is done, save TSF before it gets cleared */
	if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
		tsf = ath9k_hw_gettsf64(ah);

2441 2442 2443 2444 2445 2446
	saveLedState = REG_READ(ah, AR_CFG_LED) &
		(AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
		 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);

	ath9k_hw_mark_phy_inactive(ah);

2447 2448 2449 2450 2451 2452 2453
	if (AR_SREV_9271(ah) && ah->htc_reset_init) {
		REG_WRITE(ah,
			  AR9271_RESET_POWER_DOWN_CONTROL,
			  AR9271_RADIO_RF_RST);
		udelay(50);
	}

2454
	if (!ath9k_hw_chip_reset(ah, chan)) {
2455
		ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
2456
		return -EINVAL;
2457 2458
	}

2459 2460 2461 2462 2463 2464 2465 2466
	if (AR_SREV_9271(ah) && ah->htc_reset_init) {
		ah->htc_reset_init = false;
		REG_WRITE(ah,
			  AR9271_RESET_POWER_DOWN_CONTROL,
			  AR9271_GATE_MAC_CTL);
		udelay(50);
	}

S
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2467 2468 2469 2470
	/* Restore TSF */
	if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
		ath9k_hw_settsf64(ah, tsf);

2471 2472
	if (AR_SREV_9280_10_OR_LATER(ah))
		REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2473

2474
	if (AR_SREV_9287_12_OR_LATER(ah)) {
2475 2476 2477 2478 2479 2480 2481 2482 2483
		/* Enable ASYNC FIFO */
		REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
				AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
		REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
		REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
				AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
		REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
				AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
	}
L
Luis R. Rodriguez 已提交
2484
	r = ath9k_hw_process_ini(ah, chan);
2485 2486
	if (r)
		return r;
2487

2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504
	/* Setup MFP options for CCMP */
	if (AR_SREV_9280_20_OR_LATER(ah)) {
		/* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
		 * frames when constructing CCMP AAD. */
		REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
			      0xc7ff);
		ah->sw_mgmt_crypto = false;
	} else if (AR_SREV_9160_10_OR_LATER(ah)) {
		/* Disable hardware crypto for management frames */
		REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
			    AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
		REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
			    AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
		ah->sw_mgmt_crypto = true;
	} else
		ah->sw_mgmt_crypto = true;

2505 2506 2507 2508 2509 2510 2511 2512
	if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
		ath9k_hw_set_delta_slope(ah, chan);

	if (AR_SREV_9280_10_OR_LATER(ah))
		ath9k_hw_9280_spur_mitigate(ah, chan);
	else
		ath9k_hw_spur_mitigate(ah, chan);

2513
	ah->eep_ops->set_board_values(ah, chan);
2514 2515 2516

	ath9k_hw_decrease_chain_power(ah, chan);

2517 2518
	REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
	REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
2519 2520
		  | macStaId1
		  | AR_STA_ID1_RTS_USE_DEF
2521
		  | (ah->config.
2522
		     ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2523 2524
		  | ah->sta_id1_defaults);
	ath9k_hw_set_operating_mode(ah, ah->opmode);
2525

2526
	ath_hw_setbssidmask(common);
2527 2528 2529

	REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);

2530
	ath9k_hw_write_associd(ah);
2531 2532 2533 2534 2535

	REG_WRITE(ah, AR_ISR, ~0);

	REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);

2536 2537 2538
	if (AR_SREV_9280_10_OR_LATER(ah))
		ath9k_hw_ar9280_set_channel(ah, chan);
	else
2539 2540
		if (!(ath9k_hw_set_channel(ah, chan)))
			return -EIO;
2541 2542 2543 2544

	for (i = 0; i < AR_NUM_DCU; i++)
		REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);

2545 2546
	ah->intr_txqs = 0;
	for (i = 0; i < ah->caps.total_queues; i++)
2547 2548
		ath9k_hw_resettxqueue(ah, i);

2549
	ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2550 2551
	ath9k_hw_init_qos(ah);

2552
	if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2553
		ath9k_enable_rfkill(ah);
J
Johannes Berg 已提交
2554

2555 2556
	ath9k_hw_init_user_settings(ah);

2557
	if (AR_SREV_9287_12_OR_LATER(ah)) {
2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572
		REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
			  AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
		REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
			  AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
		REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
			  AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);

		REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
		REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);

		REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
			    AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
		REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
			      AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
	}
2573
	if (AR_SREV_9287_12_OR_LATER(ah)) {
2574 2575 2576 2577
		REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
				AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
	}

2578 2579 2580 2581 2582 2583 2584
	REG_WRITE(ah, AR_STA_ID1,
		  REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);

	ath9k_hw_set_dma(ah);

	REG_WRITE(ah, AR_OBS, 8);

2585
	if (ah->config.intr_mitigation) {
2586 2587 2588 2589 2590 2591
		REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
		REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
	}

	ath9k_hw_init_bb(ah, chan);

2592
	if (!ath9k_hw_init_cal(ah, chan))
2593
		return -EIO;
2594

2595
	rx_chainmask = ah->rxchainmask;
2596 2597 2598 2599 2600 2601 2602
	if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
		REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
		REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
	}

	REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);

2603 2604 2605
	/*
	 * For big endian systems turn on swapping for descriptors
	 */
2606 2607 2608 2609
	if (AR_SREV_9100(ah)) {
		u32 mask;
		mask = REG_READ(ah, AR_CFG);
		if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2610
			ath_print(common, ATH_DBG_RESET,
S
Sujith 已提交
2611
				"CFG Byte Swap Set 0x%x\n", mask);
2612 2613 2614 2615
		} else {
			mask =
				INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
			REG_WRITE(ah, AR_CFG, mask);
2616
			ath_print(common, ATH_DBG_RESET,
S
Sujith 已提交
2617
				"Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2618 2619
		}
	} else {
2620 2621 2622
		/* Configure AR9271 target WLAN */
                if (AR_SREV_9271(ah))
			REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
2623
#ifdef __BIG_ENDIAN
2624 2625
                else
			REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2626 2627 2628
#endif
	}

2629
	if (ah->btcoex_hw.enabled)
2630 2631
		ath9k_hw_btcoex_enable(ah);

2632
	return 0;
2633
}
2634
EXPORT_SYMBOL(ath9k_hw_reset);
2635

S
Sujith 已提交
2636 2637 2638
/************************/
/* Key Cache Management */
/************************/
2639

2640
bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2641
{
S
Sujith 已提交
2642
	u32 keyType;
2643

2644
	if (entry >= ah->caps.keycache_size) {
2645 2646
		ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
			  "keychache entry %u out of range\n", entry);
2647 2648 2649
		return false;
	}

S
Sujith 已提交
2650
	keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2651

S
Sujith 已提交
2652 2653 2654 2655 2656 2657 2658 2659
	REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
	REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
	REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
	REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
	REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
	REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
	REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
	REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2660

S
Sujith 已提交
2661 2662
	if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
		u16 micentry = entry + 64;
2663

S
Sujith 已提交
2664 2665 2666 2667
		REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
		REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
		REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
		REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2668 2669 2670 2671 2672

	}

	return true;
}
2673
EXPORT_SYMBOL(ath9k_hw_keyreset);
2674

2675
bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2676
{
S
Sujith 已提交
2677
	u32 macHi, macLo;
2678

2679
	if (entry >= ah->caps.keycache_size) {
2680 2681
		ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
			  "keychache entry %u out of range\n", entry);
S
Sujith 已提交
2682
		return false;
2683 2684
	}

S
Sujith 已提交
2685 2686 2687 2688 2689 2690 2691 2692 2693
	if (mac != NULL) {
		macHi = (mac[5] << 8) | mac[4];
		macLo = (mac[3] << 24) |
			(mac[2] << 16) |
			(mac[1] << 8) |
			mac[0];
		macLo >>= 1;
		macLo |= (macHi & 1) << 31;
		macHi >>= 1;
2694
	} else {
S
Sujith 已提交
2695
		macLo = macHi = 0;
2696
	}
S
Sujith 已提交
2697 2698
	REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
	REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2699

S
Sujith 已提交
2700
	return true;
2701
}
2702
EXPORT_SYMBOL(ath9k_hw_keysetmac);
2703

2704
bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
S
Sujith 已提交
2705
				 const struct ath9k_keyval *k,
J
Jouni Malinen 已提交
2706
				 const u8 *mac)
2707
{
2708
	const struct ath9k_hw_capabilities *pCap = &ah->caps;
2709
	struct ath_common *common = ath9k_hw_common(ah);
S
Sujith 已提交
2710 2711
	u32 key0, key1, key2, key3, key4;
	u32 keyType;
2712

S
Sujith 已提交
2713
	if (entry >= pCap->keycache_size) {
2714 2715
		ath_print(common, ATH_DBG_FATAL,
			  "keycache entry %u out of range\n", entry);
S
Sujith 已提交
2716
		return false;
2717 2718
	}

S
Sujith 已提交
2719 2720 2721 2722 2723 2724
	switch (k->kv_type) {
	case ATH9K_CIPHER_AES_OCB:
		keyType = AR_KEYTABLE_TYPE_AES;
		break;
	case ATH9K_CIPHER_AES_CCM:
		if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2725 2726 2727
			ath_print(common, ATH_DBG_ANY,
				  "AES-CCM not supported by mac rev 0x%x\n",
				  ah->hw_version.macRev);
S
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2728 2729 2730 2731 2732 2733 2734 2735
			return false;
		}
		keyType = AR_KEYTABLE_TYPE_CCM;
		break;
	case ATH9K_CIPHER_TKIP:
		keyType = AR_KEYTABLE_TYPE_TKIP;
		if (ATH9K_IS_MIC_ENABLED(ah)
		    && entry + 64 >= pCap->keycache_size) {
2736 2737
			ath_print(common, ATH_DBG_ANY,
				  "entry %u inappropriate for TKIP\n", entry);
S
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2738 2739 2740 2741
			return false;
		}
		break;
	case ATH9K_CIPHER_WEP:
2742
		if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2743 2744
			ath_print(common, ATH_DBG_ANY,
				  "WEP key length %u too small\n", k->kv_len);
S
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2745 2746
			return false;
		}
2747
		if (k->kv_len <= WLAN_KEY_LEN_WEP40)
S
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2748
			keyType = AR_KEYTABLE_TYPE_40;
2749
		else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
S
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2750 2751 2752 2753 2754 2755 2756 2757
			keyType = AR_KEYTABLE_TYPE_104;
		else
			keyType = AR_KEYTABLE_TYPE_128;
		break;
	case ATH9K_CIPHER_CLR:
		keyType = AR_KEYTABLE_TYPE_CLR;
		break;
	default:
2758 2759
		ath_print(common, ATH_DBG_FATAL,
			  "cipher %u not supported\n", k->kv_type);
S
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2760
		return false;
2761 2762
	}

J
Jouni Malinen 已提交
2763 2764 2765 2766 2767
	key0 = get_unaligned_le32(k->kv_val + 0);
	key1 = get_unaligned_le16(k->kv_val + 4);
	key2 = get_unaligned_le32(k->kv_val + 6);
	key3 = get_unaligned_le16(k->kv_val + 10);
	key4 = get_unaligned_le32(k->kv_val + 12);
2768
	if (k->kv_len <= WLAN_KEY_LEN_WEP104)
S
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2769
		key4 &= 0xff;
2770

2771 2772 2773 2774 2775 2776 2777
	/*
	 * Note: Key cache registers access special memory area that requires
	 * two 32-bit writes to actually update the values in the internal
	 * memory. Consequently, the exact order and pairs used here must be
	 * maintained.
	 */

S
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2778 2779
	if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
		u16 micentry = entry + 64;
2780

2781 2782 2783 2784 2785 2786
		/*
		 * Write inverted key[47:0] first to avoid Michael MIC errors
		 * on frames that could be sent or received at the same time.
		 * The correct key will be written in the end once everything
		 * else is ready.
		 */
S
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2787 2788
		REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
		REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2789 2790

		/* Write key[95:48] */
S
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2791 2792
		REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
		REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2793 2794

		/* Write key[127:96] and key type */
S
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2795 2796
		REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
		REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2797 2798

		/* Write MAC address for the entry */
S
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2799
		(void) ath9k_hw_keysetmac(ah, entry, mac);
2800

2801
		if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813
			/*
			 * TKIP uses two key cache entries:
			 * Michael MIC TX/RX keys in the same key cache entry
			 * (idx = main index + 64):
			 * key0 [31:0] = RX key [31:0]
			 * key1 [15:0] = TX key [31:16]
			 * key1 [31:16] = reserved
			 * key2 [31:0] = RX key [63:32]
			 * key3 [15:0] = TX key [15:0]
			 * key3 [31:16] = reserved
			 * key4 [31:0] = TX key [63:32]
			 */
S
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2814
			u32 mic0, mic1, mic2, mic3, mic4;
2815

S
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2816 2817 2818 2819 2820
			mic0 = get_unaligned_le32(k->kv_mic + 0);
			mic2 = get_unaligned_le32(k->kv_mic + 4);
			mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
			mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
			mic4 = get_unaligned_le32(k->kv_txmic + 4);
2821 2822

			/* Write RX[31:0] and TX[31:16] */
S
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2823 2824
			REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
			REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2825 2826

			/* Write RX[63:32] and TX[15:0] */
S
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2827 2828
			REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
			REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2829 2830

			/* Write TX[63:32] and keyType(reserved) */
S
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2831 2832 2833
			REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
			REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
				  AR_KEYTABLE_TYPE_CLR);
2834

S
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2835
		} else {
2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851
			/*
			 * TKIP uses four key cache entries (two for group
			 * keys):
			 * Michael MIC TX/RX keys are in different key cache
			 * entries (idx = main index + 64 for TX and
			 * main index + 32 + 96 for RX):
			 * key0 [31:0] = TX/RX MIC key [31:0]
			 * key1 [31:0] = reserved
			 * key2 [31:0] = TX/RX MIC key [63:32]
			 * key3 [31:0] = reserved
			 * key4 [31:0] = reserved
			 *
			 * Upper layer code will call this function separately
			 * for TX and RX keys when these registers offsets are
			 * used.
			 */
S
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2852
			u32 mic0, mic2;
2853

S
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2854 2855
			mic0 = get_unaligned_le32(k->kv_mic + 0);
			mic2 = get_unaligned_le32(k->kv_mic + 4);
2856 2857

			/* Write MIC key[31:0] */
S
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2858 2859
			REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
			REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2860 2861

			/* Write MIC key[63:32] */
S
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2862 2863
			REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
			REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2864 2865

			/* Write TX[63:32] and keyType(reserved) */
S
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2866 2867 2868 2869
			REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
			REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
				  AR_KEYTABLE_TYPE_CLR);
		}
2870 2871

		/* MAC address registers are reserved for the MIC entry */
S
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2872 2873
		REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
		REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2874 2875 2876 2877 2878 2879

		/*
		 * Write the correct (un-inverted) key[47:0] last to enable
		 * TKIP now that all other registers are set with correct
		 * values.
		 */
S
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2880 2881 2882
		REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
		REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
	} else {
2883
		/* Write key[47:0] */
S
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2884 2885
		REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
		REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2886 2887

		/* Write key[95:48] */
S
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2888 2889
		REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
		REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2890 2891

		/* Write key[127:96] and key type */
S
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2892 2893
		REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
		REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2894

2895
		/* Write MAC address for the entry */
S
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2896 2897
		(void) ath9k_hw_keysetmac(ah, entry, mac);
	}
2898 2899 2900

	return true;
}
2901
EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
2902

2903
bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2904
{
2905
	if (entry < ah->caps.keycache_size) {
S
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2906 2907 2908 2909 2910
		u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
		if (val & AR_KEYTABLE_VALID)
			return true;
	}
	return false;
2911
}
2912
EXPORT_SYMBOL(ath9k_hw_keyisvalid);
2913

S
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2914 2915 2916 2917
/******************************/
/* Power Management (Chipset) */
/******************************/

2918
static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2919
{
S
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2920 2921 2922 2923 2924 2925
	REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
	if (setChip) {
		REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
			    AR_RTC_FORCE_WAKE_EN);
		if (!AR_SREV_9100(ah))
			REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2926

S
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2927 2928 2929
		if(!AR_SREV_5416(ah))
			REG_CLR_BIT(ah, (AR_RTC_RESET),
				    AR_RTC_RESET_EN);
S
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2930
	}
2931 2932
}

2933
static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2934
{
S
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2935 2936
	REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
	if (setChip) {
2937
		struct ath9k_hw_capabilities *pCap = &ah->caps;
2938

S
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2939 2940 2941 2942 2943 2944
		if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
			REG_WRITE(ah, AR_RTC_FORCE_WAKE,
				  AR_RTC_FORCE_WAKE_ON_INT);
		} else {
			REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
				    AR_RTC_FORCE_WAKE_EN);
2945 2946 2947 2948
		}
	}
}

2949
static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2950
{
S
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2951 2952
	u32 val;
	int i;
2953

S
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2954 2955 2956 2957 2958 2959 2960
	if (setChip) {
		if ((REG_READ(ah, AR_RTC_STATUS) &
		     AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
			if (ath9k_hw_set_reset_reg(ah,
					   ATH9K_RESET_POWER_ON) != true) {
				return false;
			}
2961
			ath9k_hw_init_pll(ah, NULL);
S
Sujith 已提交
2962 2963 2964 2965
		}
		if (AR_SREV_9100(ah))
			REG_SET_BIT(ah, AR_RTC_RESET,
				    AR_RTC_RESET_EN);
2966

S
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2967 2968 2969
		REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
			    AR_RTC_FORCE_WAKE_EN);
		udelay(50);
2970

S
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2971 2972 2973 2974 2975 2976 2977
		for (i = POWER_UP_TIME / 50; i > 0; i--) {
			val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
			if (val == AR_RTC_STATUS_ON)
				break;
			udelay(50);
			REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
				    AR_RTC_FORCE_WAKE_EN);
2978
		}
S
Sujith 已提交
2979
		if (i == 0) {
2980 2981 2982
			ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
				  "Failed to wakeup in %uus\n",
				  POWER_UP_TIME / 20);
S
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2983
			return false;
2984 2985 2986
		}
	}

S
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2987
	REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2988

S
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2989
	return true;
2990 2991
}

2992
bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2993
{
2994
	struct ath_common *common = ath9k_hw_common(ah);
2995
	int status = true, setChip = true;
S
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2996 2997 2998 2999 3000 3001 3002
	static const char *modes[] = {
		"AWAKE",
		"FULL-SLEEP",
		"NETWORK SLEEP",
		"UNDEFINED"
	};

3003 3004 3005
	if (ah->power_mode == mode)
		return status;

3006 3007
	ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
		  modes[ah->power_mode], modes[mode]);
S
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3008 3009 3010 3011 3012 3013 3014

	switch (mode) {
	case ATH9K_PM_AWAKE:
		status = ath9k_hw_set_power_awake(ah, setChip);
		break;
	case ATH9K_PM_FULL_SLEEP:
		ath9k_set_power_sleep(ah, setChip);
3015
		ah->chip_fullsleep = true;
S
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3016 3017 3018 3019
		break;
	case ATH9K_PM_NETWORK_SLEEP:
		ath9k_set_power_network_sleep(ah, setChip);
		break;
3020
	default:
3021 3022
		ath_print(common, ATH_DBG_FATAL,
			  "Unknown power mode %u\n", mode);
3023 3024
		return false;
	}
3025
	ah->power_mode = mode;
S
Sujith 已提交
3026 3027

	return status;
3028
}
3029
EXPORT_SYMBOL(ath9k_hw_setpower);
3030

3031 3032 3033 3034 3035 3036 3037 3038 3039
/*
 * Helper for ASPM support.
 *
 * Disable PLL when in L0s as well as receiver clock when in L1.
 * This power saving option must be enabled through the SerDes.
 *
 * Programming the SerDes must go through the same 288 bit serial shift
 * register as the other analog registers.  Hence the 9 writes.
 */
V
Vivek Natarajan 已提交
3040
void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
3041
{
S
Sujith 已提交
3042
	u8 i;
V
Vivek Natarajan 已提交
3043
	u32 val;
3044

3045
	if (ah->is_pciexpress != true)
S
Sujith 已提交
3046
		return;
3047

3048
	/* Do not touch SerDes registers */
3049
	if (ah->config.pcie_powersave_enable == 2)
S
Sujith 已提交
3050 3051
		return;

3052
	/* Nothing to do on restore for 11N */
V
Vivek Natarajan 已提交
3053 3054 3055 3056 3057 3058 3059 3060 3061 3062 3063 3064 3065 3066 3067 3068 3069 3070 3071 3072 3073 3074 3075 3076 3077 3078
	if (!restore) {
		if (AR_SREV_9280_20_OR_LATER(ah)) {
			/*
			 * AR9280 2.0 or later chips use SerDes values from the
			 * initvals.h initialized depending on chipset during
			 * ath9k_hw_init()
			 */
			for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
				REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
					  INI_RA(&ah->iniPcieSerdes, i, 1));
			}
		} else if (AR_SREV_9280(ah) &&
			   (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
			REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
			REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);

			/* RX shut off when elecidle is asserted */
			REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
			REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
			REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);

			/* Shut off CLKREQ active in L1 */
			if (ah->config.pcie_clock_req)
				REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
			else
				REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
S
Sujith 已提交
3079

V
Vivek Natarajan 已提交
3080 3081 3082
			REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
			REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
			REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
S
Sujith 已提交
3083

V
Vivek Natarajan 已提交
3084 3085
			/* Load the new settings */
			REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
S
Sujith 已提交
3086

V
Vivek Natarajan 已提交
3087 3088 3089
		} else {
			REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
			REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
S
Sujith 已提交
3090

V
Vivek Natarajan 已提交
3091 3092 3093 3094
			/* RX shut off when elecidle is asserted */
			REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
			REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
			REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
S
Sujith 已提交
3095

V
Vivek Natarajan 已提交
3096 3097 3098 3099 3100
			/*
			 * Ignore ah->ah_config.pcie_clock_req setting for
			 * pre-AR9280 11n
			 */
			REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
3101

V
Vivek Natarajan 已提交
3102 3103 3104
			REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
			REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
			REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
3105

V
Vivek Natarajan 已提交
3106 3107 3108
			/* Load the new settings */
			REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
		}
3109

V
Vivek Natarajan 已提交
3110
		udelay(1000);
3111

V
Vivek Natarajan 已提交
3112 3113
		/* set bit 19 to allow forcing of pcie core into L1 state */
		REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
3114

V
Vivek Natarajan 已提交
3115 3116 3117 3118 3119 3120 3121 3122 3123 3124 3125 3126 3127 3128 3129 3130 3131 3132 3133 3134 3135 3136
		/* Several PCIe massages to ensure proper behaviour */
		if (ah->config.pcie_waen) {
			val = ah->config.pcie_waen;
			if (!power_off)
				val &= (~AR_WA_D3_L1_DISABLE);
		} else {
			if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
			    AR_SREV_9287(ah)) {
				val = AR9285_WA_DEFAULT;
				if (!power_off)
					val &= (~AR_WA_D3_L1_DISABLE);
			} else if (AR_SREV_9280(ah)) {
				/*
				 * On AR9280 chips bit 22 of 0x4004 needs to be
				 * set otherwise card may disappear.
				 */
				val = AR9280_WA_DEFAULT;
				if (!power_off)
					val &= (~AR_WA_D3_L1_DISABLE);
			} else
				val = AR_WA_DEFAULT;
		}
3137

V
Vivek Natarajan 已提交
3138 3139
		REG_WRITE(ah, AR_WA, val);
	}
S
Sujith 已提交
3140

V
Vivek Natarajan 已提交
3141
	if (power_off) {
3142
		/*
V
Vivek Natarajan 已提交
3143 3144 3145 3146
		 * Set PCIe workaround bits
		 * bit 14 in WA register (disable L1) should only
		 * be set when device enters D3 and be cleared
		 * when device comes back to D0.
3147
		 */
V
Vivek Natarajan 已提交
3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159
		if (ah->config.pcie_waen) {
			if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
				REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
		} else {
			if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
			      AR_SREV_9287(ah)) &&
			     (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
			    (AR_SREV_9280(ah) &&
			     (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
				REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
			}
		}
S
Sujith 已提交
3160
	}
3161
}
3162
EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
3163

S
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3164 3165 3166 3167
/**********************/
/* Interrupt Handling */
/**********************/

3168
bool ath9k_hw_intrpend(struct ath_hw *ah)
3169 3170 3171 3172 3173 3174 3175 3176 3177 3178 3179 3180 3181 3182 3183 3184 3185
{
	u32 host_isr;

	if (AR_SREV_9100(ah))
		return true;

	host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
	if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
		return true;

	host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
	if ((host_isr & AR_INTR_SYNC_DEFAULT)
	    && (host_isr != AR_INTR_SPURIOUS))
		return true;

	return false;
}
3186
EXPORT_SYMBOL(ath9k_hw_intrpend);
3187

3188
bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3189 3190 3191
{
	u32 isr = 0;
	u32 mask2 = 0;
3192
	struct ath9k_hw_capabilities *pCap = &ah->caps;
3193 3194
	u32 sync_cause = 0;
	bool fatal_int = false;
3195
	struct ath_common *common = ath9k_hw_common(ah);
3196 3197 3198 3199 3200 3201 3202 3203 3204

	if (!AR_SREV_9100(ah)) {
		if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
			if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
			    == AR_RTC_STATUS_ON) {
				isr = REG_READ(ah, AR_ISR);
			}
		}

S
Sujith 已提交
3205 3206
		sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
			AR_INTR_SYNC_DEFAULT;
3207 3208 3209 3210 3211 3212 3213 3214 3215 3216 3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232

		*masked = 0;

		if (!isr && !sync_cause)
			return false;
	} else {
		*masked = 0;
		isr = REG_READ(ah, AR_ISR);
	}

	if (isr) {
		if (isr & AR_ISR_BCNMISC) {
			u32 isr2;
			isr2 = REG_READ(ah, AR_ISR_S2);
			if (isr2 & AR_ISR_S2_TIM)
				mask2 |= ATH9K_INT_TIM;
			if (isr2 & AR_ISR_S2_DTIM)
				mask2 |= ATH9K_INT_DTIM;
			if (isr2 & AR_ISR_S2_DTIMSYNC)
				mask2 |= ATH9K_INT_DTIMSYNC;
			if (isr2 & (AR_ISR_S2_CABEND))
				mask2 |= ATH9K_INT_CABEND;
			if (isr2 & AR_ISR_S2_GTT)
				mask2 |= ATH9K_INT_GTT;
			if (isr2 & AR_ISR_S2_CST)
				mask2 |= ATH9K_INT_CST;
3233 3234
			if (isr2 & AR_ISR_S2_TSFOOR)
				mask2 |= ATH9K_INT_TSFOOR;
3235 3236 3237 3238 3239 3240 3241 3242 3243 3244
		}

		isr = REG_READ(ah, AR_ISR_RAC);
		if (isr == 0xffffffff) {
			*masked = 0;
			return false;
		}

		*masked = isr & ATH9K_INT_COMMON;

3245
		if (ah->config.intr_mitigation) {
3246 3247 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259
			if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
				*masked |= ATH9K_INT_RX;
		}

		if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
			*masked |= ATH9K_INT_RX;
		if (isr &
		    (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
		     AR_ISR_TXEOL)) {
			u32 s0_s, s1_s;

			*masked |= ATH9K_INT_TX;

			s0_s = REG_READ(ah, AR_ISR_S0_S);
3260 3261
			ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
			ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
3262 3263

			s1_s = REG_READ(ah, AR_ISR_S1_S);
3264 3265
			ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
			ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
3266 3267 3268
		}

		if (isr & AR_ISR_RXORN) {
3269 3270
			ath_print(common, ATH_DBG_INTERRUPT,
				  "receive FIFO overrun interrupt\n");
3271 3272 3273
		}

		if (!AR_SREV_9100(ah)) {
3274
			if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3275 3276 3277 3278 3279 3280 3281 3282
				u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
				if (isr5 & AR_ISR_S5_TIM_TIMER)
					*masked |= ATH9K_INT_TIM_TIMER;
			}
		}

		*masked |= mask2;
	}
S
Sujith 已提交
3283

3284 3285
	if (AR_SREV_9100(ah))
		return true;
S
Sujith 已提交
3286

3287 3288 3289 3290 3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301 3302 3303
	if (isr & AR_ISR_GENTMR) {
		u32 s5_s;

		s5_s = REG_READ(ah, AR_ISR_S5_S);
		if (isr & AR_ISR_GENTMR) {
			ah->intr_gen_timer_trigger =
				MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);

			ah->intr_gen_timer_thresh =
				MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);

			if (ah->intr_gen_timer_trigger)
				*masked |= ATH9K_INT_GENTIMER;

		}
	}

3304 3305 3306 3307 3308 3309 3310 3311
	if (sync_cause) {
		fatal_int =
			(sync_cause &
			 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
			? true : false;

		if (fatal_int) {
			if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
3312 3313
				ath_print(common, ATH_DBG_ANY,
					  "received PCI FATAL interrupt\n");
3314 3315
			}
			if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
3316 3317
				ath_print(common, ATH_DBG_ANY,
					  "received PCI PERR interrupt\n");
3318
			}
3319
			*masked |= ATH9K_INT_FATAL;
3320 3321
		}
		if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
3322 3323
			ath_print(common, ATH_DBG_INTERRUPT,
				  "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
3324 3325 3326 3327 3328
			REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
			REG_WRITE(ah, AR_RC, 0);
			*masked |= ATH9K_INT_FATAL;
		}
		if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3329 3330
			ath_print(common, ATH_DBG_INTERRUPT,
				  "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3331 3332 3333 3334 3335
		}

		REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
		(void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
	}
S
Sujith 已提交
3336

3337 3338
	return true;
}
3339
EXPORT_SYMBOL(ath9k_hw_getisr);
3340

3341
enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3342
{
3343
	u32 omask = ah->mask_reg;
3344
	u32 mask, mask2;
3345
	struct ath9k_hw_capabilities *pCap = &ah->caps;
3346
	struct ath_common *common = ath9k_hw_common(ah);
3347

3348
	ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3349 3350

	if (omask & ATH9K_INT_GLOBAL) {
3351
		ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
3352 3353 3354 3355 3356 3357 3358 3359 3360 3361 3362 3363 3364 3365 3366
		REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
		(void) REG_READ(ah, AR_IER);
		if (!AR_SREV_9100(ah)) {
			REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
			(void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);

			REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
			(void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
		}
	}

	mask = ints & ATH9K_INT_COMMON;
	mask2 = 0;

	if (ints & ATH9K_INT_TX) {
3367
		if (ah->txok_interrupt_mask)
3368
			mask |= AR_IMR_TXOK;
3369
		if (ah->txdesc_interrupt_mask)
3370
			mask |= AR_IMR_TXDESC;
3371
		if (ah->txerr_interrupt_mask)
3372
			mask |= AR_IMR_TXERR;
3373
		if (ah->txeol_interrupt_mask)
3374 3375 3376 3377
			mask |= AR_IMR_TXEOL;
	}
	if (ints & ATH9K_INT_RX) {
		mask |= AR_IMR_RXERR;
3378
		if (ah->config.intr_mitigation)
3379 3380 3381
			mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
		else
			mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3382
		if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3383 3384 3385 3386 3387 3388 3389 3390 3391 3392 3393 3394
			mask |= AR_IMR_GENTMR;
	}

	if (ints & (ATH9K_INT_BMISC)) {
		mask |= AR_IMR_BCNMISC;
		if (ints & ATH9K_INT_TIM)
			mask2 |= AR_IMR_S2_TIM;
		if (ints & ATH9K_INT_DTIM)
			mask2 |= AR_IMR_S2_DTIM;
		if (ints & ATH9K_INT_DTIMSYNC)
			mask2 |= AR_IMR_S2_DTIMSYNC;
		if (ints & ATH9K_INT_CABEND)
3395 3396 3397
			mask2 |= AR_IMR_S2_CABEND;
		if (ints & ATH9K_INT_TSFOOR)
			mask2 |= AR_IMR_S2_TSFOOR;
3398 3399 3400 3401 3402 3403 3404 3405 3406 3407
	}

	if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
		mask |= AR_IMR_BCNMISC;
		if (ints & ATH9K_INT_GTT)
			mask2 |= AR_IMR_S2_GTT;
		if (ints & ATH9K_INT_CST)
			mask2 |= AR_IMR_S2_CST;
	}

3408
	ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3409 3410 3411 3412 3413 3414 3415 3416 3417
	REG_WRITE(ah, AR_IMR, mask);
	mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
					   AR_IMR_S2_DTIM |
					   AR_IMR_S2_DTIMSYNC |
					   AR_IMR_S2_CABEND |
					   AR_IMR_S2_CABTO |
					   AR_IMR_S2_TSFOOR |
					   AR_IMR_S2_GTT | AR_IMR_S2_CST);
	REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3418
	ah->mask_reg = ints;
3419

3420
	if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3421 3422 3423 3424 3425 3426 3427
		if (ints & ATH9K_INT_TIM_TIMER)
			REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
		else
			REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
	}

	if (ints & ATH9K_INT_GLOBAL) {
3428
		ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
3429 3430 3431 3432 3433 3434 3435 3436 3437 3438 3439 3440
		REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
		if (!AR_SREV_9100(ah)) {
			REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
				  AR_INTR_MAC_IRQ);
			REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);


			REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
				  AR_INTR_SYNC_DEFAULT);
			REG_WRITE(ah, AR_INTR_SYNC_MASK,
				  AR_INTR_SYNC_DEFAULT);
		}
3441 3442
		ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
			  REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3443 3444 3445 3446
	}

	return omask;
}
3447
EXPORT_SYMBOL(ath9k_hw_set_interrupts);
3448

S
Sujith 已提交
3449 3450 3451 3452
/*******************/
/* Beacon Handling */
/*******************/

3453
void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3454 3455 3456
{
	int flags = 0;

3457
	ah->beacon_interval = beacon_period;
3458

3459
	switch (ah->opmode) {
3460 3461
	case NL80211_IFTYPE_STATION:
	case NL80211_IFTYPE_MONITOR:
3462 3463 3464 3465 3466
		REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
		REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
		REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
		flags |= AR_TBTT_TIMER_EN;
		break;
3467
	case NL80211_IFTYPE_ADHOC:
3468
	case NL80211_IFTYPE_MESH_POINT:
3469 3470 3471 3472
		REG_SET_BIT(ah, AR_TXCFG,
			    AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
		REG_WRITE(ah, AR_NEXT_NDP_TIMER,
			  TU_TO_USEC(next_beacon +
3473 3474
				     (ah->atim_window ? ah->
				      atim_window : 1)));
3475
		flags |= AR_NDP_TIMER_EN;
3476
	case NL80211_IFTYPE_AP:
3477 3478 3479
		REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
		REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
			  TU_TO_USEC(next_beacon -
3480
				     ah->config.
3481
				     dma_beacon_response_time));
3482 3483
		REG_WRITE(ah, AR_NEXT_SWBA,
			  TU_TO_USEC(next_beacon -
3484
				     ah->config.
3485
				     sw_beacon_response_time));
3486 3487 3488
		flags |=
			AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
		break;
3489
	default:
3490 3491 3492
		ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
			  "%s: unsupported opmode: %d\n",
			  __func__, ah->opmode);
3493 3494
		return;
		break;
3495 3496 3497 3498 3499 3500 3501 3502 3503 3504 3505 3506 3507 3508
	}

	REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
	REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
	REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
	REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));

	beacon_period &= ~ATH9K_BEACON_ENA;
	if (beacon_period & ATH9K_BEACON_RESET_TSF) {
		ath9k_hw_reset_tsf(ah);
	}

	REG_SET_BIT(ah, AR_TIMER_MODE, flags);
}
3509
EXPORT_SYMBOL(ath9k_hw_beaconinit);
3510

3511
void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
S
Sujith 已提交
3512
				    const struct ath9k_beacon_state *bs)
3513 3514
{
	u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3515
	struct ath9k_hw_capabilities *pCap = &ah->caps;
3516
	struct ath_common *common = ath9k_hw_common(ah);
3517 3518 3519 3520 3521 3522 3523 3524 3525 3526 3527 3528 3529 3530 3531 3532 3533 3534 3535 3536 3537 3538 3539 3540 3541

	REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));

	REG_WRITE(ah, AR_BEACON_PERIOD,
		  TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
	REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
		  TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));

	REG_RMW_FIELD(ah, AR_RSSI_THR,
		      AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);

	beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;

	if (bs->bs_sleepduration > beaconintval)
		beaconintval = bs->bs_sleepduration;

	dtimperiod = bs->bs_dtimperiod;
	if (bs->bs_sleepduration > dtimperiod)
		dtimperiod = bs->bs_sleepduration;

	if (beaconintval == dtimperiod)
		nextTbtt = bs->bs_nextdtim;
	else
		nextTbtt = bs->bs_nexttbtt;

3542 3543 3544 3545
	ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
	ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
	ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
	ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3546

S
Sujith 已提交
3547 3548 3549
	REG_WRITE(ah, AR_NEXT_DTIM,
		  TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
	REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3550

S
Sujith 已提交
3551 3552 3553
	REG_WRITE(ah, AR_SLEEP1,
		  SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
		  | AR_SLEEP1_ASSUME_DTIM);
3554

S
Sujith 已提交
3555 3556 3557 3558
	if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
		beacontimeout = (BEACON_TIMEOUT_VAL << 3);
	else
		beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3559

S
Sujith 已提交
3560 3561
	REG_WRITE(ah, AR_SLEEP2,
		  SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3562

S
Sujith 已提交
3563 3564
	REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
	REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3565

S
Sujith 已提交
3566 3567 3568
	REG_SET_BIT(ah, AR_TIMER_MODE,
		    AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
		    AR_DTIM_TIMER_EN);
3569

3570 3571
	/* TSF Out of Range Threshold */
	REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3572
}
3573
EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
3574

S
Sujith 已提交
3575 3576 3577 3578
/*******************/
/* HW Capabilities */
/*******************/

3579
void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3580
{
3581
	struct ath9k_hw_capabilities *pCap = &ah->caps;
3582
	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3583
	struct ath_common *common = ath9k_hw_common(ah);
3584
	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
3585

S
Sujith 已提交
3586
	u16 capField = 0, eeval;
3587

S
Sujith 已提交
3588
	eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3589
	regulatory->current_rd = eeval;
3590

S
Sujith 已提交
3591
	eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3592 3593
	if (AR_SREV_9285_10_OR_LATER(ah))
		eeval |= AR9285_RDEXT_DEFAULT;
3594
	regulatory->current_rd_ext = eeval;
3595

S
Sujith 已提交
3596
	capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
S
Sujith 已提交
3597

3598
	if (ah->opmode != NL80211_IFTYPE_AP &&
3599
	    ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3600 3601 3602 3603 3604
		if (regulatory->current_rd == 0x64 ||
		    regulatory->current_rd == 0x65)
			regulatory->current_rd += 5;
		else if (regulatory->current_rd == 0x41)
			regulatory->current_rd = 0x43;
3605 3606
		ath_print(common, ATH_DBG_REGULATORY,
			  "regdomain mapped to 0x%x\n", regulatory->current_rd);
S
Sujith 已提交
3607
	}
3608

S
Sujith 已提交
3609
	eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
S
Sujith 已提交
3610
	bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3611

S
Sujith 已提交
3612 3613
	if (eeval & AR5416_OPFLAGS_11A) {
		set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3614
		if (ah->config.ht_enable) {
S
Sujith 已提交
3615 3616 3617 3618 3619 3620 3621 3622 3623
			if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
				set_bit(ATH9K_MODE_11NA_HT20,
					pCap->wireless_modes);
			if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
				set_bit(ATH9K_MODE_11NA_HT40PLUS,
					pCap->wireless_modes);
				set_bit(ATH9K_MODE_11NA_HT40MINUS,
					pCap->wireless_modes);
			}
3624 3625 3626
		}
	}

S
Sujith 已提交
3627 3628
	if (eeval & AR5416_OPFLAGS_11G) {
		set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3629
		if (ah->config.ht_enable) {
S
Sujith 已提交
3630 3631 3632 3633 3634 3635 3636 3637 3638 3639
			if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
				set_bit(ATH9K_MODE_11NG_HT20,
					pCap->wireless_modes);
			if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
				set_bit(ATH9K_MODE_11NG_HT40PLUS,
					pCap->wireless_modes);
				set_bit(ATH9K_MODE_11NG_HT40MINUS,
					pCap->wireless_modes);
			}
		}
3640
	}
S
Sujith 已提交
3641

S
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3642
	pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3643 3644 3645 3646
	/*
	 * For AR9271 we will temporarilly uses the rx chainmax as read from
	 * the EEPROM.
	 */
3647
	if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3648 3649 3650
	    !(eeval & AR5416_OPFLAGS_11A) &&
	    !(AR_SREV_9271(ah)))
		/* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
3651 3652
		pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
	else
3653
		/* Use rx_chainmask from EEPROM. */
3654
		pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3655

3656
	if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3657
		ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3658

S
Sujith 已提交
3659 3660
	pCap->low_2ghz_chan = 2312;
	pCap->high_2ghz_chan = 2732;
3661

S
Sujith 已提交
3662 3663
	pCap->low_5ghz_chan = 4920;
	pCap->high_5ghz_chan = 6100;
3664

S
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3665 3666 3667
	pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
	pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
	pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3668

S
Sujith 已提交
3669 3670 3671
	pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
	pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
	pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3672

3673
	if (ah->config.ht_enable)
S
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3674 3675 3676
		pCap->hw_caps |= ATH9K_HW_CAP_HT;
	else
		pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3677

S
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3678 3679 3680 3681
	pCap->hw_caps |= ATH9K_HW_CAP_GTT;
	pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
	pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
	pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3682

S
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3683 3684 3685 3686 3687
	if (capField & AR_EEPROM_EEPCAP_MAXQCU)
		pCap->total_queues =
			MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
	else
		pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3688

S
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3689 3690 3691 3692 3693
	if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
		pCap->keycache_size =
			1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
	else
		pCap->keycache_size = AR_KEYTABLE_SIZE;
3694

S
Sujith 已提交
3695 3696
	pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
	pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3697

3698 3699 3700
	if (AR_SREV_9285_10_OR_LATER(ah))
		pCap->num_gpio_pins = AR9285_NUM_GPIO;
	else if (AR_SREV_9280_10_OR_LATER(ah))
S
Sujith 已提交
3701 3702 3703
		pCap->num_gpio_pins = AR928X_NUM_GPIO;
	else
		pCap->num_gpio_pins = AR_NUM_GPIO;
3704

S
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3705 3706 3707 3708 3709
	if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
		pCap->hw_caps |= ATH9K_HW_CAP_CST;
		pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
	} else {
		pCap->rts_aggr_limit = (8 * 1024);
3710 3711
	}

S
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3712 3713
	pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;

3714
#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3715 3716 3717 3718 3719 3720
	ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
	if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
		ah->rfkill_gpio =
			MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
		ah->rfkill_polarity =
			MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
S
Sujith 已提交
3721 3722

		pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3723
	}
S
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3724
#endif
3725

3726
	pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3727

3728
	if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
S
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3729 3730 3731
		pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
	else
		pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3732

3733
	if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
S
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3734 3735 3736 3737 3738
		pCap->reg_cap =
			AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
			AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
			AR_EEPROM_EEREGCAP_EN_KK_U2 |
			AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3739
	} else {
S
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3740 3741 3742
		pCap->reg_cap =
			AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
			AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3743 3744
	}

3745 3746 3747 3748
	/* Advertise midband for AR5416 with FCC midband set in eeprom */
	if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
	    AR_SREV_5416(ah))
		pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
S
Sujith 已提交
3749 3750

	pCap->num_antcfg_5ghz =
S
Sujith 已提交
3751
		ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
S
Sujith 已提交
3752
	pCap->num_antcfg_2ghz =
S
Sujith 已提交
3753
		ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3754

3755
	if (AR_SREV_9280_10_OR_LATER(ah) &&
3756
	    ath9k_hw_btcoex_supported(ah)) {
3757 3758
		btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
		btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
3759

3760
		if (AR_SREV_9285(ah)) {
3761 3762
			btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
			btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
3763
		} else {
3764
			btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
3765
		}
3766
	} else {
3767
		btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
3768
	}
3769 3770
}

3771
bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
S
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3772
			    u32 capability, u32 *result)
3773
{
3774
	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
S
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3775 3776 3777 3778 3779 3780 3781 3782 3783 3784 3785 3786 3787 3788 3789 3790 3791 3792
	switch (type) {
	case ATH9K_CAP_CIPHER:
		switch (capability) {
		case ATH9K_CIPHER_AES_CCM:
		case ATH9K_CIPHER_AES_OCB:
		case ATH9K_CIPHER_TKIP:
		case ATH9K_CIPHER_WEP:
		case ATH9K_CIPHER_MIC:
		case ATH9K_CIPHER_CLR:
			return true;
		default:
			return false;
		}
	case ATH9K_CAP_TKIP_MIC:
		switch (capability) {
		case 0:
			return true;
		case 1:
3793
			return (ah->sta_id1_defaults &
S
Sujith 已提交
3794 3795 3796 3797
				AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
			false;
		}
	case ATH9K_CAP_TKIP_SPLIT:
3798
		return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
S
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3799 3800 3801 3802 3803 3804 3805 3806 3807 3808 3809 3810 3811
			false : true;
	case ATH9K_CAP_DIVERSITY:
		return (REG_READ(ah, AR_PHY_CCK_DETECT) &
			AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
			true : false;
	case ATH9K_CAP_MCAST_KEYSRCH:
		switch (capability) {
		case 0:
			return true;
		case 1:
			if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
				return false;
			} else {
3812
				return (ah->sta_id1_defaults &
S
Sujith 已提交
3813 3814 3815 3816 3817 3818 3819 3820 3821 3822
					AR_STA_ID1_MCAST_KSRCH) ? true :
					false;
			}
		}
		return false;
	case ATH9K_CAP_TXPOW:
		switch (capability) {
		case 0:
			return 0;
		case 1:
3823
			*result = regulatory->power_limit;
S
Sujith 已提交
3824 3825
			return 0;
		case 2:
3826
			*result = regulatory->max_power_level;
S
Sujith 已提交
3827 3828
			return 0;
		case 3:
3829
			*result = regulatory->tp_scale;
S
Sujith 已提交
3830 3831 3832
			return 0;
		}
		return false;
3833 3834 3835 3836
	case ATH9K_CAP_DS:
		return (AR_SREV_9280_20_OR_LATER(ah) &&
			(ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
			? false : true;
S
Sujith 已提交
3837 3838
	default:
		return false;
3839 3840
	}
}
3841
EXPORT_SYMBOL(ath9k_hw_getcapability);
3842

3843
bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
S
Sujith 已提交
3844
			    u32 capability, u32 setting, int *status)
3845
{
S
Sujith 已提交
3846
	u32 v;
3847

S
Sujith 已提交
3848 3849 3850
	switch (type) {
	case ATH9K_CAP_TKIP_MIC:
		if (setting)
3851
			ah->sta_id1_defaults |=
S
Sujith 已提交
3852 3853
				AR_STA_ID1_CRPT_MIC_ENABLE;
		else
3854
			ah->sta_id1_defaults &=
S
Sujith 已提交
3855 3856 3857 3858 3859 3860 3861 3862 3863 3864 3865 3866
				~AR_STA_ID1_CRPT_MIC_ENABLE;
		return true;
	case ATH9K_CAP_DIVERSITY:
		v = REG_READ(ah, AR_PHY_CCK_DETECT);
		if (setting)
			v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
		else
			v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
		REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
		return true;
	case ATH9K_CAP_MCAST_KEYSRCH:
		if (setting)
3867
			ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
S
Sujith 已提交
3868
		else
3869
			ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
S
Sujith 已提交
3870 3871 3872
		return true;
	default:
		return false;
3873 3874
	}
}
3875
EXPORT_SYMBOL(ath9k_hw_setcapability);
3876

S
Sujith 已提交
3877 3878 3879
/****************************/
/* GPIO / RFKILL / Antennae */
/****************************/
3880

3881
static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
S
Sujith 已提交
3882 3883 3884 3885
					 u32 gpio, u32 type)
{
	int addr;
	u32 gpio_shift, tmp;
3886

S
Sujith 已提交
3887 3888 3889 3890 3891 3892
	if (gpio > 11)
		addr = AR_GPIO_OUTPUT_MUX3;
	else if (gpio > 5)
		addr = AR_GPIO_OUTPUT_MUX2;
	else
		addr = AR_GPIO_OUTPUT_MUX1;
3893

S
Sujith 已提交
3894
	gpio_shift = (gpio % 6) * 5;
3895

S
Sujith 已提交
3896 3897 3898 3899
	if (AR_SREV_9280_20_OR_LATER(ah)
	    || (addr != AR_GPIO_OUTPUT_MUX1)) {
		REG_RMW(ah, addr, (type << gpio_shift),
			(0x1f << gpio_shift));
3900
	} else {
S
Sujith 已提交
3901 3902 3903 3904 3905
		tmp = REG_READ(ah, addr);
		tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
		tmp &= ~(0x1f << gpio_shift);
		tmp |= (type << gpio_shift);
		REG_WRITE(ah, addr, tmp);
3906 3907 3908
	}
}

3909
void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3910
{
S
Sujith 已提交
3911
	u32 gpio_shift;
3912

3913
	BUG_ON(gpio >= ah->caps.num_gpio_pins);
3914

S
Sujith 已提交
3915
	gpio_shift = gpio << 1;
3916

S
Sujith 已提交
3917 3918 3919 3920
	REG_RMW(ah,
		AR_GPIO_OE_OUT,
		(AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
		(AR_GPIO_OE_OUT_DRV << gpio_shift));
3921
}
3922
EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
3923

3924
u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3925
{
3926 3927 3928
#define MS_REG_READ(x, y) \
	(MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))

3929
	if (gpio >= ah->caps.num_gpio_pins)
S
Sujith 已提交
3930
		return 0xffffffff;
3931

3932 3933 3934
	if (AR_SREV_9287_10_OR_LATER(ah))
		return MS_REG_READ(AR9287, gpio) != 0;
	else if (AR_SREV_9285_10_OR_LATER(ah))
3935 3936 3937 3938 3939
		return MS_REG_READ(AR9285, gpio) != 0;
	else if (AR_SREV_9280_10_OR_LATER(ah))
		return MS_REG_READ(AR928X, gpio) != 0;
	else
		return MS_REG_READ(AR, gpio) != 0;
3940
}
3941
EXPORT_SYMBOL(ath9k_hw_gpio_get);
3942

3943
void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
S
Sujith 已提交
3944
			 u32 ah_signal_type)
3945
{
S
Sujith 已提交
3946
	u32 gpio_shift;
3947

S
Sujith 已提交
3948
	ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3949

S
Sujith 已提交
3950
	gpio_shift = 2 * gpio;
3951

S
Sujith 已提交
3952 3953 3954 3955
	REG_RMW(ah,
		AR_GPIO_OE_OUT,
		(AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
		(AR_GPIO_OE_OUT_DRV << gpio_shift));
3956
}
3957
EXPORT_SYMBOL(ath9k_hw_cfg_output);
3958

3959
void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3960
{
S
Sujith 已提交
3961 3962
	REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
		AR_GPIO_BIT(gpio));
3963
}
3964
EXPORT_SYMBOL(ath9k_hw_set_gpio);
3965

3966
u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3967
{
S
Sujith 已提交
3968
	return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3969
}
3970
EXPORT_SYMBOL(ath9k_hw_getdefantenna);
3971

3972
void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3973
{
S
Sujith 已提交
3974
	REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3975
}
3976
EXPORT_SYMBOL(ath9k_hw_setantenna);
3977

3978
bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
S
Sujith 已提交
3979 3980 3981 3982 3983
			       enum ath9k_ant_setting settings,
			       struct ath9k_channel *chan,
			       u8 *tx_chainmask,
			       u8 *rx_chainmask,
			       u8 *antenna_cfgd)
3984
{
S
Sujith 已提交
3985
	static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3986

S
Sujith 已提交
3987 3988
	if (AR_SREV_9280(ah)) {
		if (!tx_chainmask_cfg) {
3989

S
Sujith 已提交
3990 3991 3992
			tx_chainmask_cfg = *tx_chainmask;
			rx_chainmask_cfg = *rx_chainmask;
		}
3993

S
Sujith 已提交
3994 3995 3996 3997 3998 3999 4000
		switch (settings) {
		case ATH9K_ANT_FIXED_A:
			*tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
			*rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
			*antenna_cfgd = true;
			break;
		case ATH9K_ANT_FIXED_B:
4001
			if (ah->caps.tx_chainmask >
S
Sujith 已提交
4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012 4013 4014 4015 4016
			    ATH9K_ANTENNA1_CHAINMASK) {
				*tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
			}
			*rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
			*antenna_cfgd = true;
			break;
		case ATH9K_ANT_VARIABLE:
			*tx_chainmask = tx_chainmask_cfg;
			*rx_chainmask = rx_chainmask_cfg;
			*antenna_cfgd = true;
			break;
		default:
			break;
		}
	} else {
S
Sujith 已提交
4017
		ah->config.diversity_control = settings;
4018 4019
	}

S
Sujith 已提交
4020
	return true;
4021 4022
}

S
Sujith 已提交
4023 4024 4025 4026
/*********************/
/* General Operation */
/*********************/

4027
u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
4028
{
S
Sujith 已提交
4029 4030
	u32 bits = REG_READ(ah, AR_RX_FILTER);
	u32 phybits = REG_READ(ah, AR_PHY_ERR);
4031

S
Sujith 已提交
4032 4033 4034 4035
	if (phybits & AR_PHY_ERR_RADAR)
		bits |= ATH9K_RX_FILTER_PHYRADAR;
	if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
		bits |= ATH9K_RX_FILTER_PHYERR;
S
Sujith 已提交
4036

S
Sujith 已提交
4037
	return bits;
4038
}
4039
EXPORT_SYMBOL(ath9k_hw_getrxfilter);
4040

4041
void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
4042
{
S
Sujith 已提交
4043
	u32 phybits;
4044

S
Sujith 已提交
4045 4046
	REG_WRITE(ah, AR_RX_FILTER, bits);

S
Sujith 已提交
4047 4048 4049 4050 4051 4052
	phybits = 0;
	if (bits & ATH9K_RX_FILTER_PHYRADAR)
		phybits |= AR_PHY_ERR_RADAR;
	if (bits & ATH9K_RX_FILTER_PHYERR)
		phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
	REG_WRITE(ah, AR_PHY_ERR, phybits);
4053

S
Sujith 已提交
4054 4055 4056 4057 4058 4059 4060
	if (phybits)
		REG_WRITE(ah, AR_RXCFG,
			  REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
	else
		REG_WRITE(ah, AR_RXCFG,
			  REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
}
4061
EXPORT_SYMBOL(ath9k_hw_setrxfilter);
4062

4063
bool ath9k_hw_phy_disable(struct ath_hw *ah)
S
Sujith 已提交
4064
{
4065 4066 4067 4068 4069
	if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
		return false;

	ath9k_hw_init_pll(ah, NULL);
	return true;
S
Sujith 已提交
4070
}
4071
EXPORT_SYMBOL(ath9k_hw_phy_disable);
4072

4073
bool ath9k_hw_disable(struct ath_hw *ah)
S
Sujith 已提交
4074
{
4075
	if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
S
Sujith 已提交
4076
		return false;
4077

4078 4079 4080 4081 4082
	if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
		return false;

	ath9k_hw_init_pll(ah, NULL);
	return true;
4083
}
4084
EXPORT_SYMBOL(ath9k_hw_disable);
4085

4086
void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
4087
{
4088
	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4089
	struct ath9k_channel *chan = ah->curchan;
4090
	struct ieee80211_channel *channel = chan->chan;
4091

4092
	regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
4093

4094
	ah->eep_ops->set_txpower(ah, chan,
4095
				 ath9k_regd_get_ctl(regulatory, chan),
4096 4097 4098
				 channel->max_antenna_gain * 2,
				 channel->max_power * 2,
				 min((u32) MAX_RATE_POWER,
4099
				 (u32) regulatory->power_limit));
4100
}
4101
EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
4102

4103
void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
4104
{
4105
	memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
4106
}
4107
EXPORT_SYMBOL(ath9k_hw_setmac);
4108

4109
void ath9k_hw_setopmode(struct ath_hw *ah)
4110
{
4111
	ath9k_hw_set_operating_mode(ah, ah->opmode);
4112
}
4113
EXPORT_SYMBOL(ath9k_hw_setopmode);
4114

4115
void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
4116
{
S
Sujith 已提交
4117 4118
	REG_WRITE(ah, AR_MCAST_FIL0, filter0);
	REG_WRITE(ah, AR_MCAST_FIL1, filter1);
4119
}
4120
EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
4121

4122
void ath9k_hw_write_associd(struct ath_hw *ah)
4123
{
4124 4125 4126 4127 4128
	struct ath_common *common = ath9k_hw_common(ah);

	REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
	REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
		  ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
4129
}
4130
EXPORT_SYMBOL(ath9k_hw_write_associd);
4131

4132
u64 ath9k_hw_gettsf64(struct ath_hw *ah)
4133
{
S
Sujith 已提交
4134
	u64 tsf;
4135

S
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4136 4137
	tsf = REG_READ(ah, AR_TSF_U32);
	tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
4138

S
Sujith 已提交
4139 4140
	return tsf;
}
4141
EXPORT_SYMBOL(ath9k_hw_gettsf64);
4142

4143
void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
4144 4145
{
	REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
A
Alina Friedrichsen 已提交
4146
	REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
4147
}
4148
EXPORT_SYMBOL(ath9k_hw_settsf64);
4149

4150
void ath9k_hw_reset_tsf(struct ath_hw *ah)
S
Sujith 已提交
4151
{
4152 4153
	if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
			   AH_TSF_WRITE_TIMEOUT))
4154 4155
		ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
			  "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
4156

S
Sujith 已提交
4157 4158
	REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
}
4159
EXPORT_SYMBOL(ath9k_hw_reset_tsf);
4160

S
Sujith 已提交
4161
void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
S
Sujith 已提交
4162 4163
{
	if (setting)
4164
		ah->misc_mode |= AR_PCU_TX_ADD_TSF;
S
Sujith 已提交
4165
	else
4166
		ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
S
Sujith 已提交
4167
}
4168
EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
4169

4170
bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
S
Sujith 已提交
4171 4172
{
	if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
4173 4174
		ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
			  "bad slot time %u\n", us);
4175
		ah->slottime = (u32) -1;
S
Sujith 已提交
4176 4177 4178
		return false;
	} else {
		REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
4179
		ah->slottime = us;
S
Sujith 已提交
4180
		return true;
4181
	}
S
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4182
}
4183
EXPORT_SYMBOL(ath9k_hw_setslottime);
S
Sujith 已提交
4184

L
Luis R. Rodriguez 已提交
4185
void ath9k_hw_set11nmac2040(struct ath_hw *ah)
S
Sujith 已提交
4186
{
L
Luis R. Rodriguez 已提交
4187
	struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
S
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4188 4189
	u32 macmode;

L
Luis R. Rodriguez 已提交
4190
	if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
S
Sujith 已提交
4191 4192 4193
		macmode = AR_2040_JOINED_RX_CLEAR;
	else
		macmode = 0;
4194

S
Sujith 已提交
4195
	REG_WRITE(ah, AR_2040_MODE, macmode);
4196
}
4197 4198 4199 4200 4201 4202 4203 4204 4205 4206 4207 4208 4209 4210 4211 4212 4213 4214 4215 4216 4217 4218 4219 4220 4221 4222 4223 4224 4225 4226 4227 4228 4229 4230 4231 4232 4233 4234 4235 4236 4237 4238 4239 4240 4241 4242

/* HW Generic timers configuration */

static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
{
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
	{AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
				AR_NDP2_TIMER_MODE, 0x0002},
	{AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
				AR_NDP2_TIMER_MODE, 0x0004},
	{AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
				AR_NDP2_TIMER_MODE, 0x0008},
	{AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
				AR_NDP2_TIMER_MODE, 0x0010},
	{AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
				AR_NDP2_TIMER_MODE, 0x0020},
	{AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
				AR_NDP2_TIMER_MODE, 0x0040},
	{AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
				AR_NDP2_TIMER_MODE, 0x0080}
};

/* HW generic timer primitives */

/* compute and clear index of rightmost 1 */
static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
{
	u32 b;

	b = *mask;
	b &= (0-b);
	*mask &= ~b;
	b *= debruijn32;
	b >>= 27;

	return timer_table->gen_timer_index[b];
}

4243
u32 ath9k_hw_gettsf32(struct ath_hw *ah)
4244 4245 4246
{
	return REG_READ(ah, AR_TSF_L32);
}
4247
EXPORT_SYMBOL(ath9k_hw_gettsf32);
4248 4249 4250 4251 4252 4253 4254 4255 4256 4257 4258 4259 4260

struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
					  void (*trigger)(void *),
					  void (*overflow)(void *),
					  void *arg,
					  u8 timer_index)
{
	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
	struct ath_gen_timer *timer;

	timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);

	if (timer == NULL) {
4261 4262 4263
		ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
			  "Failed to allocate memory"
			  "for hw timer[%d]\n", timer_index);
4264 4265 4266 4267 4268 4269 4270 4271 4272 4273 4274 4275
		return NULL;
	}

	/* allocate a hardware generic timer slot */
	timer_table->timers[timer_index] = timer;
	timer->index = timer_index;
	timer->trigger = trigger;
	timer->overflow = overflow;
	timer->arg = arg;

	return timer;
}
4276
EXPORT_SYMBOL(ath_gen_timer_alloc);
4277

4278 4279 4280 4281
void ath9k_hw_gen_timer_start(struct ath_hw *ah,
			      struct ath_gen_timer *timer,
			      u32 timer_next,
			      u32 timer_period)
4282 4283 4284 4285 4286 4287 4288 4289 4290 4291
{
	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
	u32 tsf;

	BUG_ON(!timer_period);

	set_bit(timer->index, &timer_table->timer_mask.timer_bits);

	tsf = ath9k_hw_gettsf32(ah);

4292 4293 4294
	ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
		  "curent tsf %x period %x"
		  "timer_next %x\n", tsf, timer_period, timer_next);
4295 4296 4297 4298 4299 4300 4301 4302 4303 4304 4305 4306 4307 4308 4309 4310 4311 4312 4313 4314 4315 4316 4317

	/*
	 * Pull timer_next forward if the current TSF already passed it
	 * because of software latency
	 */
	if (timer_next < tsf)
		timer_next = tsf + timer_period;

	/*
	 * Program generic timer registers
	 */
	REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
		 timer_next);
	REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
		  timer_period);
	REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
		    gen_tmr_configuration[timer->index].mode_mask);

	/* Enable both trigger and thresh interrupt masks */
	REG_SET_BIT(ah, AR_IMR_S5,
		(SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
		SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
}
4318
EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
4319

4320
void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
4321 4322 4323 4324 4325 4326 4327 4328 4329 4330 4331 4332 4333 4334 4335 4336 4337 4338 4339
{
	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;

	if ((timer->index < AR_FIRST_NDP_TIMER) ||
		(timer->index >= ATH_MAX_GEN_TIMER)) {
		return;
	}

	/* Clear generic timer enable bits. */
	REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
			gen_tmr_configuration[timer->index].mode_mask);

	/* Disable both trigger and thresh interrupt masks */
	REG_CLR_BIT(ah, AR_IMR_S5,
		(SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
		SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));

	clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
}
4340
EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
4341 4342 4343 4344 4345 4346 4347 4348 4349

void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
{
	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;

	/* free the hardware generic timer slot */
	timer_table->timers[timer->index] = NULL;
	kfree(timer);
}
4350
EXPORT_SYMBOL(ath_gen_timer_free);
4351 4352 4353 4354 4355 4356 4357 4358

/*
 * Generic Timer Interrupts handling
 */
void ath_gen_timer_isr(struct ath_hw *ah)
{
	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
	struct ath_gen_timer *timer;
4359
	struct ath_common *common = ath9k_hw_common(ah);
4360 4361 4362 4363 4364 4365 4366 4367 4368 4369 4370 4371 4372 4373
	u32 trigger_mask, thresh_mask, index;

	/* get hardware generic timer interrupt status */
	trigger_mask = ah->intr_gen_timer_trigger;
	thresh_mask = ah->intr_gen_timer_thresh;
	trigger_mask &= timer_table->timer_mask.val;
	thresh_mask &= timer_table->timer_mask.val;

	trigger_mask &= ~thresh_mask;

	while (thresh_mask) {
		index = rightmost_index(timer_table, &thresh_mask);
		timer = timer_table->timers[index];
		BUG_ON(!timer);
4374 4375
		ath_print(common, ATH_DBG_HWTIMER,
			  "TSF overflow for Gen timer %d\n", index);
4376 4377 4378 4379 4380 4381 4382
		timer->overflow(timer->arg);
	}

	while (trigger_mask) {
		index = rightmost_index(timer_table, &trigger_mask);
		timer = timer_table->timers[index];
		BUG_ON(!timer);
4383 4384
		ath_print(common, ATH_DBG_HWTIMER,
			  "Gen timer[%d] trigger\n", index);
4385 4386 4387
		timer->trigger(timer->arg);
	}
}
4388
EXPORT_SYMBOL(ath_gen_timer_isr);
4389 4390 4391 4392 4393 4394 4395 4396 4397 4398 4399 4400 4401

static struct {
	u32 version;
	const char * name;
} ath_mac_bb_names[] = {
	/* Devices with external radios */
	{ AR_SREV_VERSION_5416_PCI,	"5416" },
	{ AR_SREV_VERSION_5416_PCIE,	"5418" },
	{ AR_SREV_VERSION_9100,		"9100" },
	{ AR_SREV_VERSION_9160,		"9160" },
	/* Single-chip solutions */
	{ AR_SREV_VERSION_9280,		"9280" },
	{ AR_SREV_VERSION_9285,		"9285" },
4402 4403
	{ AR_SREV_VERSION_9287,         "9287" },
	{ AR_SREV_VERSION_9271,         "9271" },
4404 4405 4406 4407 4408 4409 4410 4411 4412 4413 4414 4415 4416 4417 4418 4419 4420
};

/* For devices with external radios */
static struct {
	u16 version;
	const char * name;
} ath_rf_names[] = {
	{ 0,				"5133" },
	{ AR_RAD5133_SREV_MAJOR,	"5133" },
	{ AR_RAD5122_SREV_MAJOR,	"5122" },
	{ AR_RAD2133_SREV_MAJOR,	"2133" },
	{ AR_RAD2122_SREV_MAJOR,	"2122" }
};

/*
 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
 */
4421
static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
4422 4423 4424 4425 4426 4427 4428 4429 4430 4431 4432 4433 4434 4435 4436 4437
{
	int i;

	for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
		if (ath_mac_bb_names[i].version == mac_bb_version) {
			return ath_mac_bb_names[i].name;
		}
	}

	return "????";
}

/*
 * Return the RF name. "????" is returned if the RF is unknown.
 * Used for devices with external radios.
 */
4438
static const char *ath9k_hw_rf_name(u16 rf_version)
4439 4440 4441 4442 4443 4444 4445 4446 4447 4448 4449
{
	int i;

	for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
		if (ath_rf_names[i].version == rf_version) {
			return ath_rf_names[i].name;
		}
	}

	return "????";
}
4450 4451 4452 4453 4454 4455 4456 4457 4458 4459 4460 4461 4462 4463 4464 4465 4466 4467 4468 4469 4470 4471 4472 4473 4474

void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
{
	int used;

	/* chipsets >= AR9280 are single-chip */
	if (AR_SREV_9280_10_OR_LATER(ah)) {
		used = snprintf(hw_name, len,
			       "Atheros AR%s Rev:%x",
			       ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
			       ah->hw_version.macRev);
	}
	else {
		used = snprintf(hw_name, len,
			       "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
			       ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
			       ah->hw_version.macRev,
			       ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
						AR_RADIO_SREV_MAJOR)),
			       ah->hw_version.phyRev);
	}

	hw_name[used] = '\0';
}
EXPORT_SYMBOL(ath9k_hw_name);