intel_hdmi.c 66.2 KB
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/*
 * Copyright 2006 Dave Airlie <airlied@linux.ie>
 * Copyright © 2006-2009 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt <eric@anholt.net>
 *	Jesse Barnes <jesse.barnes@intel.com>
 */

#include <linux/i2c.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/hdmi.h>
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#include <drm/drmP.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
#include <drm/drm_edid.h>
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#include "intel_drv.h"
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#include <drm/i915_drm.h>
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#include "i915_drv.h"

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static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
{
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	return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
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}

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static void
assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
{
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	struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
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	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t enabled_bits;

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	enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
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	WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
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	     "HDMI port enabled, expecting disabled\n");
}

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struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
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{
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	struct intel_digital_port *intel_dig_port =
		container_of(encoder, struct intel_digital_port, base.base);
	return &intel_dig_port->hdmi;
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}

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static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
{
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	return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
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}

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static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
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{
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	switch (type) {
	case HDMI_INFOFRAME_TYPE_AVI:
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		return VIDEO_DIP_SELECT_AVI;
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	case HDMI_INFOFRAME_TYPE_SPD:
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		return VIDEO_DIP_SELECT_SPD;
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	case HDMI_INFOFRAME_TYPE_VENDOR:
		return VIDEO_DIP_SELECT_VENDOR;
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	default:
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		DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
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		return 0;
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	}
}

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static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
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{
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	switch (type) {
	case HDMI_INFOFRAME_TYPE_AVI:
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		return VIDEO_DIP_ENABLE_AVI;
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	case HDMI_INFOFRAME_TYPE_SPD:
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		return VIDEO_DIP_ENABLE_SPD;
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	case HDMI_INFOFRAME_TYPE_VENDOR:
		return VIDEO_DIP_ENABLE_VENDOR;
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	default:
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		DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
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		return 0;
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	}
}

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static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
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{
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	switch (type) {
	case HDMI_INFOFRAME_TYPE_AVI:
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		return VIDEO_DIP_ENABLE_AVI_HSW;
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	case HDMI_INFOFRAME_TYPE_SPD:
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		return VIDEO_DIP_ENABLE_SPD_HSW;
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	case HDMI_INFOFRAME_TYPE_VENDOR:
		return VIDEO_DIP_ENABLE_VS_HSW;
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	default:
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		DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
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		return 0;
	}
}

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static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,
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				  enum transcoder cpu_transcoder,
				  struct drm_i915_private *dev_priv)
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{
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	switch (type) {
	case HDMI_INFOFRAME_TYPE_AVI:
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		return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
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	case HDMI_INFOFRAME_TYPE_SPD:
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		return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
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	case HDMI_INFOFRAME_TYPE_VENDOR:
		return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder);
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	default:
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		DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
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		return 0;
	}
}

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static void g4x_write_infoframe(struct drm_encoder *encoder,
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				enum hdmi_infoframe_type type,
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				const void *frame, ssize_t len)
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{
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	const uint32_t *data = frame;
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	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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	u32 val = I915_READ(VIDEO_DIP_CTL);
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	int i;
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	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");

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	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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	val |= g4x_infoframe_index(type);
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	val &= ~g4x_infoframe_enable(type);
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	I915_WRITE(VIDEO_DIP_CTL, val);
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	mmiowb();
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	for (i = 0; i < len; i += 4) {
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		I915_WRITE(VIDEO_DIP_DATA, *data);
		data++;
	}
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	/* Write every possible data byte to force correct ECC calculation. */
	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
		I915_WRITE(VIDEO_DIP_DATA, 0);
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	mmiowb();
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	val |= g4x_infoframe_enable(type);
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	val &= ~VIDEO_DIP_FREQ_MASK;
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	val |= VIDEO_DIP_FREQ_VSYNC;
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	I915_WRITE(VIDEO_DIP_CTL, val);
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	POSTING_READ(VIDEO_DIP_CTL);
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}

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static bool g4x_infoframe_enabled(struct drm_encoder *encoder)
{
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
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	u32 val = I915_READ(VIDEO_DIP_CTL);

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	if ((val & VIDEO_DIP_ENABLE) == 0)
		return false;
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	if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
		return false;

	return val & (VIDEO_DIP_ENABLE_AVI |
		      VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
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}

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static void ibx_write_infoframe(struct drm_encoder *encoder,
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				enum hdmi_infoframe_type type,
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				const void *frame, ssize_t len)
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{
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	const uint32_t *data = frame;
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	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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	int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
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	u32 val = I915_READ(reg);

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	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");

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	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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	val |= g4x_infoframe_index(type);
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	val &= ~g4x_infoframe_enable(type);
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	I915_WRITE(reg, val);

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	mmiowb();
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	for (i = 0; i < len; i += 4) {
		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
		data++;
	}
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	/* Write every possible data byte to force correct ECC calculation. */
	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
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	mmiowb();
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	val |= g4x_infoframe_enable(type);
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	val &= ~VIDEO_DIP_FREQ_MASK;
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	val |= VIDEO_DIP_FREQ_VSYNC;
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	I915_WRITE(reg, val);
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	POSTING_READ(reg);
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}

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static bool ibx_infoframe_enabled(struct drm_encoder *encoder)
{
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
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	int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
	u32 val = I915_READ(reg);

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	if ((val & VIDEO_DIP_ENABLE) == 0)
		return false;

	if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
		return false;
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	return val & (VIDEO_DIP_ENABLE_AVI |
		      VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
		      VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
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}

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static void cpt_write_infoframe(struct drm_encoder *encoder,
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				enum hdmi_infoframe_type type,
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				const void *frame, ssize_t len)
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{
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	const uint32_t *data = frame;
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	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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	int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
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	u32 val = I915_READ(reg);
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	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");

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	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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	val |= g4x_infoframe_index(type);
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	/* The DIP control register spec says that we need to update the AVI
	 * infoframe without clearing its enable bit */
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	if (type != HDMI_INFOFRAME_TYPE_AVI)
		val &= ~g4x_infoframe_enable(type);
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	I915_WRITE(reg, val);
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	mmiowb();
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	for (i = 0; i < len; i += 4) {
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		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
		data++;
	}
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	/* Write every possible data byte to force correct ECC calculation. */
	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
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	mmiowb();
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	val |= g4x_infoframe_enable(type);
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	val &= ~VIDEO_DIP_FREQ_MASK;
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	val |= VIDEO_DIP_FREQ_VSYNC;
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	I915_WRITE(reg, val);
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	POSTING_READ(reg);
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}
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static bool cpt_infoframe_enabled(struct drm_encoder *encoder)
{
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
	u32 val = I915_READ(reg);

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	if ((val & VIDEO_DIP_ENABLE) == 0)
		return false;

	return val & (VIDEO_DIP_ENABLE_AVI |
		      VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
		      VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
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}

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static void vlv_write_infoframe(struct drm_encoder *encoder,
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				enum hdmi_infoframe_type type,
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				const void *frame, ssize_t len)
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{
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	const uint32_t *data = frame;
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	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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	int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
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	u32 val = I915_READ(reg);
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	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");

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	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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	val |= g4x_infoframe_index(type);
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	val &= ~g4x_infoframe_enable(type);
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	I915_WRITE(reg, val);
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	mmiowb();
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	for (i = 0; i < len; i += 4) {
		I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
		data++;
	}
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	/* Write every possible data byte to force correct ECC calculation. */
	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
		I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
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	mmiowb();
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	val |= g4x_infoframe_enable(type);
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	val &= ~VIDEO_DIP_FREQ_MASK;
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	val |= VIDEO_DIP_FREQ_VSYNC;
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	I915_WRITE(reg, val);
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	POSTING_READ(reg);
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}

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static bool vlv_infoframe_enabled(struct drm_encoder *encoder)
{
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
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	int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
	u32 val = I915_READ(reg);

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	if ((val & VIDEO_DIP_ENABLE) == 0)
		return false;

	if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
		return false;
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	return val & (VIDEO_DIP_ENABLE_AVI |
		      VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
		      VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
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}

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static void hsw_write_infoframe(struct drm_encoder *encoder,
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				enum hdmi_infoframe_type type,
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				const void *frame, ssize_t len)
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{
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	const uint32_t *data = frame;
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	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
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	u32 data_reg;
	int i;
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	u32 val = I915_READ(ctl_reg);
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	data_reg = hsw_infoframe_data_reg(type,
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					  intel_crtc->config->cpu_transcoder,
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					  dev_priv);
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	if (data_reg == 0)
		return;

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	val &= ~hsw_infoframe_enable(type);
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	I915_WRITE(ctl_reg, val);

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	mmiowb();
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	for (i = 0; i < len; i += 4) {
		I915_WRITE(data_reg + i, *data);
		data++;
	}
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	/* Write every possible data byte to force correct ECC calculation. */
	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
		I915_WRITE(data_reg + i, 0);
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	mmiowb();
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	val |= hsw_infoframe_enable(type);
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	I915_WRITE(ctl_reg, val);
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	POSTING_READ(ctl_reg);
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}

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static bool hsw_infoframe_enabled(struct drm_encoder *encoder)
{
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
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	u32 val = I915_READ(ctl_reg);

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	return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
		      VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
		      VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
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}

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/*
 * The data we write to the DIP data buffer registers is 1 byte bigger than the
 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 * used for both technologies.
 *
 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 * DW1:       DB3       | DB2 | DB1 | DB0
 * DW2:       DB7       | DB6 | DB5 | DB4
 * DW3: ...
 *
 * (HB is Header Byte, DB is Data Byte)
 *
 * The hdmi pack() functions don't know about that hardware specific hole so we
 * trick them by giving an offset into the buffer and moving back the header
 * bytes by one.
 */
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static void intel_write_infoframe(struct drm_encoder *encoder,
				  union hdmi_infoframe *frame)
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{
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
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	uint8_t buffer[VIDEO_DIP_DATA_SIZE];
	ssize_t len;
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	/* see comment above for the reason for this offset */
	len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
	if (len < 0)
		return;

	/* Insert the 'hole' (see big comment above) at position 3 */
	buffer[0] = buffer[1];
	buffer[1] = buffer[2];
	buffer[2] = buffer[3];
	buffer[3] = 0;
	len++;
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	intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
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}

449
static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
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					 const struct drm_display_mode *adjusted_mode)
451
{
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	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
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	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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	union hdmi_infoframe frame;
	int ret;
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	ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
						       adjusted_mode);
	if (ret < 0) {
		DRM_ERROR("couldn't fill AVI infoframe\n");
		return;
	}
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Paulo Zanoni 已提交
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	if (intel_hdmi->rgb_quant_range_selectable) {
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		if (intel_crtc->config->limited_color_range)
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			frame.avi.quantization_range =
				HDMI_QUANTIZATION_RANGE_LIMITED;
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		else
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			frame.avi.quantization_range =
				HDMI_QUANTIZATION_RANGE_FULL;
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	}

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	intel_write_infoframe(encoder, &frame);
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}

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static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
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{
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	union hdmi_infoframe frame;
	int ret;

	ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
	if (ret < 0) {
		DRM_ERROR("couldn't fill SPD infoframe\n");
		return;
	}
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	frame.spd.sdi = HDMI_SPD_SDI_PC;
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	intel_write_infoframe(encoder, &frame);
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}

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static void
intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
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			      const struct drm_display_mode *adjusted_mode)
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{
	union hdmi_infoframe frame;
	int ret;

	ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
							  adjusted_mode);
	if (ret < 0)
		return;

	intel_write_infoframe(encoder, &frame);
}

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static void g4x_set_infoframes(struct drm_encoder *encoder,
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			       bool enable,
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			       const struct drm_display_mode *adjusted_mode)
510
{
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	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
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	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
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	u32 reg = VIDEO_DIP_CTL;
	u32 val = I915_READ(reg);
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	u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
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	assert_hdmi_port_disabled(intel_hdmi);

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	/* If the registers were not initialized yet, they might be zeroes,
	 * which means we're selecting the AVI DIP and we're setting its
	 * frequency to once. This seems to really confuse the HW and make
	 * things stop working (the register spec says the AVI always needs to
	 * be sent every VSync). So here we avoid writing to the register more
	 * than we need and also explicitly select the AVI DIP and explicitly
	 * set its frequency to every VSync. Avoiding to write it twice seems to
	 * be enough to solve the problem, but being defensive shouldn't hurt us
	 * either. */
	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;

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	if (!enable) {
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		if (!(val & VIDEO_DIP_ENABLE))
			return;
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		if (port != (val & VIDEO_DIP_PORT_MASK)) {
			DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
				      (val & VIDEO_DIP_PORT_MASK) >> 29);
			return;
		}
		val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
			 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
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		I915_WRITE(reg, val);
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		POSTING_READ(reg);
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		return;
	}

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	if (port != (val & VIDEO_DIP_PORT_MASK)) {
		if (val & VIDEO_DIP_ENABLE) {
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			DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
				      (val & VIDEO_DIP_PORT_MASK) >> 29);
			return;
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		}
		val &= ~VIDEO_DIP_PORT_MASK;
		val |= port;
	}

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	val |= VIDEO_DIP_ENABLE;
557 558
	val &= ~(VIDEO_DIP_ENABLE_AVI |
		 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
559

560
	I915_WRITE(reg, val);
561
	POSTING_READ(reg);
562

563 564
	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
	intel_hdmi_set_spd_infoframe(encoder);
565
	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
566 567
}

568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586
static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder)
{
	struct drm_device *dev = encoder->dev;
	struct drm_connector *connector;

	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));

	/*
	 * HDMI cloning is only supported on g4x which doesn't
	 * support deep color or GCP infoframes anyway so no
	 * need to worry about multiple HDMI sinks here.
	 */
	list_for_each_entry(connector, &dev->mode_config.connector_list, head)
		if (connector->encoder == encoder)
			return connector->display_info.bpc > 8;

	return false;
}

587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629
/*
 * Determine if default_phase=1 can be indicated in the GCP infoframe.
 *
 * From HDMI specification 1.4a:
 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
 *   phase of 0
 */
static bool gcp_default_phase_possible(int pipe_bpp,
				       const struct drm_display_mode *mode)
{
	unsigned int pixels_per_group;

	switch (pipe_bpp) {
	case 30:
		/* 4 pixels in 5 clocks */
		pixels_per_group = 4;
		break;
	case 36:
		/* 2 pixels in 3 clocks */
		pixels_per_group = 2;
		break;
	case 48:
		/* 1 pixel in 2 clocks */
		pixels_per_group = 1;
		break;
	default:
		/* phase information not relevant for 8bpc */
		return false;
	}

	return mode->crtc_hdisplay % pixels_per_group == 0 &&
		mode->crtc_htotal % pixels_per_group == 0 &&
		mode->crtc_hblank_start % pixels_per_group == 0 &&
		mode->crtc_hblank_end % pixels_per_group == 0 &&
		mode->crtc_hsync_start % pixels_per_group == 0 &&
		mode->crtc_hsync_end % pixels_per_group == 0 &&
		((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
		 mode->crtc_htotal/2 % pixels_per_group == 0);
}

630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648
static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder)
{
	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
	struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
	u32 reg, val = 0;

	if (HAS_DDI(dev_priv))
		reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder);
	else if (IS_VALLEYVIEW(dev_priv))
		reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
	else if (HAS_PCH_SPLIT(dev_priv->dev))
		reg = TVIDEO_DIP_GCP(crtc->pipe);
	else
		return false;

	/* Indicate color depth whenever the sink supports deep color */
	if (hdmi_sink_is_deep_color(encoder))
		val |= GCP_COLOR_INDICATION;

649 650 651 652 653
	/* Enable default_phase whenever the display mode is suitably aligned */
	if (gcp_default_phase_possible(crtc->config->pipe_bpp,
				       &crtc->config->base.adjusted_mode))
		val |= GCP_DEFAULT_PHASE_ENABLE;

654 655 656 657 658
	I915_WRITE(reg, val);

	return val != 0;
}

659
static void ibx_set_infoframes(struct drm_encoder *encoder,
660
			       bool enable,
661
			       const struct drm_display_mode *adjusted_mode)
662
{
663 664
	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
665 666
	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
667 668
	u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
	u32 val = I915_READ(reg);
669
	u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
670

671 672
	assert_hdmi_port_disabled(intel_hdmi);

673 674 675
	/* See the big comment in g4x_set_infoframes() */
	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;

676
	if (!enable) {
677 678
		if (!(val & VIDEO_DIP_ENABLE))
			return;
679 680 681
		val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
			 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
			 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
682
		I915_WRITE(reg, val);
683
		POSTING_READ(reg);
684 685 686
		return;
	}

687
	if (port != (val & VIDEO_DIP_PORT_MASK)) {
688 689 690
		WARN(val & VIDEO_DIP_ENABLE,
		     "DIP already enabled on port %c\n",
		     (val & VIDEO_DIP_PORT_MASK) >> 29);
691 692 693 694
		val &= ~VIDEO_DIP_PORT_MASK;
		val |= port;
	}

695
	val |= VIDEO_DIP_ENABLE;
696 697 698
	val &= ~(VIDEO_DIP_ENABLE_AVI |
		 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
		 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
699

700 701 702
	if (intel_hdmi_set_gcp_infoframe(encoder))
		val |= VIDEO_DIP_ENABLE_GCP;

703
	I915_WRITE(reg, val);
704
	POSTING_READ(reg);
705

706 707
	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
	intel_hdmi_set_spd_infoframe(encoder);
708
	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
709 710 711
}

static void cpt_set_infoframes(struct drm_encoder *encoder,
712
			       bool enable,
713
			       const struct drm_display_mode *adjusted_mode)
714
{
715 716 717 718 719 720
	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
	u32 val = I915_READ(reg);

721 722
	assert_hdmi_port_disabled(intel_hdmi);

723 724 725
	/* See the big comment in g4x_set_infoframes() */
	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;

726
	if (!enable) {
727 728
		if (!(val & VIDEO_DIP_ENABLE))
			return;
729 730 731
		val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
			 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
			 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
732
		I915_WRITE(reg, val);
733
		POSTING_READ(reg);
734 735 736
		return;
	}

737 738
	/* Set both together, unset both together: see the spec. */
	val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
739
	val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
740
		 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
741

742 743 744
	if (intel_hdmi_set_gcp_infoframe(encoder))
		val |= VIDEO_DIP_ENABLE_GCP;

745
	I915_WRITE(reg, val);
746
	POSTING_READ(reg);
747

748 749
	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
	intel_hdmi_set_spd_infoframe(encoder);
750
	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
751 752 753
}

static void vlv_set_infoframes(struct drm_encoder *encoder,
754
			       bool enable,
755
			       const struct drm_display_mode *adjusted_mode)
756
{
757
	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
758
	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
759 760 761 762
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
	u32 val = I915_READ(reg);
763
	u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
764

765 766
	assert_hdmi_port_disabled(intel_hdmi);

767 768 769
	/* See the big comment in g4x_set_infoframes() */
	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;

770
	if (!enable) {
771 772
		if (!(val & VIDEO_DIP_ENABLE))
			return;
773 774 775
		val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
			 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
			 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
776
		I915_WRITE(reg, val);
777
		POSTING_READ(reg);
778 779 780
		return;
	}

781
	if (port != (val & VIDEO_DIP_PORT_MASK)) {
782 783 784
		WARN(val & VIDEO_DIP_ENABLE,
		     "DIP already enabled on port %c\n",
		     (val & VIDEO_DIP_PORT_MASK) >> 29);
785 786 787 788
		val &= ~VIDEO_DIP_PORT_MASK;
		val |= port;
	}

789
	val |= VIDEO_DIP_ENABLE;
790 791 792
	val &= ~(VIDEO_DIP_ENABLE_AVI |
		 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
		 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
793

794 795 796
	if (intel_hdmi_set_gcp_infoframe(encoder))
		val |= VIDEO_DIP_ENABLE_GCP;

797
	I915_WRITE(reg, val);
798
	POSTING_READ(reg);
799

800 801
	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
	intel_hdmi_set_spd_infoframe(encoder);
802
	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
803 804 805
}

static void hsw_set_infoframes(struct drm_encoder *encoder,
806
			       bool enable,
807
			       const struct drm_display_mode *adjusted_mode)
808
{
809 810 811
	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
812
	u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
813
	u32 val = I915_READ(reg);
814

815 816
	assert_hdmi_port_disabled(intel_hdmi);

817 818 819 820
	val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
		 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
		 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);

821
	if (!enable) {
822
		I915_WRITE(reg, val);
823
		POSTING_READ(reg);
824 825 826
		return;
	}

827 828 829
	if (intel_hdmi_set_gcp_infoframe(encoder))
		val |= VIDEO_DIP_ENABLE_GCP_HSW;

830
	I915_WRITE(reg, val);
831
	POSTING_READ(reg);
832

833 834
	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
	intel_hdmi_set_spd_infoframe(encoder);
835
	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
836 837
}

838
static void intel_hdmi_prepare(struct intel_encoder *encoder)
839
{
840
	struct drm_device *dev = encoder->base.dev;
841
	struct drm_i915_private *dev_priv = dev->dev_private;
842 843
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
844
	const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
845
	u32 hdmi_val;
846

847
	hdmi_val = SDVO_ENCODING_HDMI;
848 849
	if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range)
		hdmi_val |= HDMI_COLOR_RANGE_16_235;
850
	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
851
		hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
852
	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
853
		hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
854

855
	if (crtc->config->pipe_bpp > 24)
856
		hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
857
	else
858
		hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
859

860
	if (crtc->config->has_hdmi_sink)
861
		hdmi_val |= HDMI_MODE_SELECT_HDMI;
862

863
	if (HAS_PCH_CPT(dev))
864
		hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
865 866
	else if (IS_CHERRYVIEW(dev))
		hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
867
	else
868
		hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
869

870 871
	I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
	POSTING_READ(intel_hdmi->hdmi_reg);
872 873
}

874 875
static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
				    enum pipe *pipe)
876
{
877
	struct drm_device *dev = encoder->base.dev;
878
	struct drm_i915_private *dev_priv = dev->dev_private;
879
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
880
	enum intel_display_power_domain power_domain;
881 882
	u32 tmp;

883
	power_domain = intel_display_port_power_domain(encoder);
884
	if (!intel_display_power_is_enabled(dev_priv, power_domain))
885 886
		return false;

887
	tmp = I915_READ(intel_hdmi->hdmi_reg);
888 889 890 891 892 893

	if (!(tmp & SDVO_ENABLE))
		return false;

	if (HAS_PCH_CPT(dev))
		*pipe = PORT_TO_PIPE_CPT(tmp);
894 895
	else if (IS_CHERRYVIEW(dev))
		*pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
896 897 898 899 900 901
	else
		*pipe = PORT_TO_PIPE(tmp);

	return true;
}

902
static void intel_hdmi_get_config(struct intel_encoder *encoder,
903
				  struct intel_crtc_state *pipe_config)
904 905
{
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
906 907
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
908
	u32 tmp, flags = 0;
909
	int dotclock;
910 911 912 913 914 915 916 917 918 919 920 921 922

	tmp = I915_READ(intel_hdmi->hdmi_reg);

	if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
		flags |= DRM_MODE_FLAG_PHSYNC;
	else
		flags |= DRM_MODE_FLAG_NHSYNC;

	if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
		flags |= DRM_MODE_FLAG_PVSYNC;
	else
		flags |= DRM_MODE_FLAG_NVSYNC;

923 924 925
	if (tmp & HDMI_MODE_SELECT_HDMI)
		pipe_config->has_hdmi_sink = true;

926 927 928
	if (intel_hdmi->infoframe_enabled(&encoder->base))
		pipe_config->has_infoframe = true;

929
	if (tmp & SDVO_AUDIO_ENABLE)
930 931
		pipe_config->has_audio = true;

932 933 934 935
	if (!HAS_PCH_SPLIT(dev) &&
	    tmp & HDMI_COLOR_RANGE_16_235)
		pipe_config->limited_color_range = true;

936
	pipe_config->base.adjusted_mode.flags |= flags;
937 938 939 940 941 942

	if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
		dotclock = pipe_config->port_clock * 2 / 3;
	else
		dotclock = pipe_config->port_clock;

943 944 945
	if (pipe_config->pixel_multiplier)
		dotclock /= pipe_config->pixel_multiplier;

946 947 948
	if (HAS_PCH_SPLIT(dev_priv->dev))
		ironlake_check_encoder_dotclock(pipe_config, dotclock);

949
	pipe_config->base.adjusted_mode.crtc_clock = dotclock;
950 951
}

952 953 954 955 956 957 958 959 960 961
static void intel_enable_hdmi_audio(struct intel_encoder *encoder)
{
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);

	WARN_ON(!crtc->config->has_hdmi_sink);
	DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
			 pipe_name(crtc->pipe));
	intel_audio_codec_enable(encoder);
}

962
static void g4x_enable_hdmi(struct intel_encoder *encoder)
963
{
964
	struct drm_device *dev = encoder->base.dev;
965
	struct drm_i915_private *dev_priv = dev->dev_private;
966
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
967
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
968 969
	u32 temp;

970
	temp = I915_READ(intel_hdmi->hdmi_reg);
971

972 973 974
	temp |= SDVO_ENABLE;
	if (crtc->config->has_audio)
		temp |= SDVO_AUDIO_ENABLE;
975

976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991
	I915_WRITE(intel_hdmi->hdmi_reg, temp);
	POSTING_READ(intel_hdmi->hdmi_reg);

	if (crtc->config->has_audio)
		intel_enable_hdmi_audio(encoder);
}

static void ibx_enable_hdmi(struct intel_encoder *encoder)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
	u32 temp;

	temp = I915_READ(intel_hdmi->hdmi_reg);
992

993 994 995
	temp |= SDVO_ENABLE;
	if (crtc->config->has_audio)
		temp |= SDVO_AUDIO_ENABLE;
996

997 998 999 1000 1001 1002
	/*
	 * HW workaround, need to write this twice for issue
	 * that may result in first write getting masked.
	 */
	I915_WRITE(intel_hdmi->hdmi_reg, temp);
	POSTING_READ(intel_hdmi->hdmi_reg);
1003 1004
	I915_WRITE(intel_hdmi->hdmi_reg, temp);
	POSTING_READ(intel_hdmi->hdmi_reg);
1005

1006 1007 1008 1009 1010 1011
	/*
	 * HW workaround, need to toggle enable bit off and on
	 * for 12bpc with pixel repeat.
	 *
	 * FIXME: BSpec says this should be done at the end of
	 * of the modeset sequence, so not sure if this isn't too soon.
1012
	 */
1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023
	if (crtc->config->pipe_bpp > 24 &&
	    crtc->config->pixel_multiplier > 1) {
		I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
		POSTING_READ(intel_hdmi->hdmi_reg);

		/*
		 * HW workaround, need to write this twice for issue
		 * that may result in first write getting masked.
		 */
		I915_WRITE(intel_hdmi->hdmi_reg, temp);
		POSTING_READ(intel_hdmi->hdmi_reg);
1024 1025
		I915_WRITE(intel_hdmi->hdmi_reg, temp);
		POSTING_READ(intel_hdmi->hdmi_reg);
1026
	}
1027

1028
	if (crtc->config->has_audio)
1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063
		intel_enable_hdmi_audio(encoder);
}

static void cpt_enable_hdmi(struct intel_encoder *encoder)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
	enum pipe pipe = crtc->pipe;
	u32 temp;

	temp = I915_READ(intel_hdmi->hdmi_reg);

	temp |= SDVO_ENABLE;
	if (crtc->config->has_audio)
		temp |= SDVO_AUDIO_ENABLE;

	/*
	 * WaEnableHDMI8bpcBefore12bpc:snb,ivb
	 *
	 * The procedure for 12bpc is as follows:
	 * 1. disable HDMI clock gating
	 * 2. enable HDMI with 8bpc
	 * 3. enable HDMI with 12bpc
	 * 4. enable HDMI clock gating
	 */

	if (crtc->config->pipe_bpp > 24) {
		I915_WRITE(TRANS_CHICKEN1(pipe),
			   I915_READ(TRANS_CHICKEN1(pipe)) |
			   TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);

		temp &= ~SDVO_COLOR_FORMAT_MASK;
		temp |= SDVO_COLOR_FORMAT_8bpc;
1064
	}
1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082

	I915_WRITE(intel_hdmi->hdmi_reg, temp);
	POSTING_READ(intel_hdmi->hdmi_reg);

	if (crtc->config->pipe_bpp > 24) {
		temp &= ~SDVO_COLOR_FORMAT_MASK;
		temp |= HDMI_COLOR_FORMAT_12bpc;

		I915_WRITE(intel_hdmi->hdmi_reg, temp);
		POSTING_READ(intel_hdmi->hdmi_reg);

		I915_WRITE(TRANS_CHICKEN1(pipe),
			   I915_READ(TRANS_CHICKEN1(pipe)) &
			   ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
	}

	if (crtc->config->has_audio)
		intel_enable_hdmi_audio(encoder);
1083
}
1084

1085 1086
static void vlv_enable_hdmi(struct intel_encoder *encoder)
{
1087 1088 1089 1090 1091 1092 1093
}

static void intel_disable_hdmi(struct intel_encoder *encoder)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1094
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1095 1096
	u32 temp;

1097
	temp = I915_READ(intel_hdmi->hdmi_reg);
1098

1099
	temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1100 1101
	I915_WRITE(intel_hdmi->hdmi_reg, temp);
	POSTING_READ(intel_hdmi->hdmi_reg);
1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123

	/*
	 * HW workaround for IBX, we need to move the port
	 * to transcoder A after disabling it to allow the
	 * matching DP port to be enabled on transcoder A.
	 */
	if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) {
		temp &= ~SDVO_PIPE_B_SELECT;
		temp |= SDVO_ENABLE;
		/*
		 * HW workaround, need to write this twice for issue
		 * that may result in first write getting masked.
		 */
		I915_WRITE(intel_hdmi->hdmi_reg, temp);
		POSTING_READ(intel_hdmi->hdmi_reg);
		I915_WRITE(intel_hdmi->hdmi_reg, temp);
		POSTING_READ(intel_hdmi->hdmi_reg);

		temp &= ~SDVO_ENABLE;
		I915_WRITE(intel_hdmi->hdmi_reg, temp);
		POSTING_READ(intel_hdmi->hdmi_reg);
	}
1124

1125
	intel_hdmi->set_infoframes(&encoder->base, false, NULL);
1126 1127
}

1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150
static void g4x_disable_hdmi(struct intel_encoder *encoder)
{
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);

	if (crtc->config->has_audio)
		intel_audio_codec_disable(encoder);

	intel_disable_hdmi(encoder);
}

static void pch_disable_hdmi(struct intel_encoder *encoder)
{
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);

	if (crtc->config->has_audio)
		intel_audio_codec_disable(encoder);
}

static void pch_post_disable_hdmi(struct intel_encoder *encoder)
{
	intel_disable_hdmi(encoder);
}

1151
static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
1152 1153 1154
{
	struct drm_device *dev = intel_hdmi_to_dev(hdmi);

1155
	if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev))
1156
		return 165000;
1157
	else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
1158 1159 1160 1161 1162
		return 300000;
	else
		return 225000;
}

1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173
static enum drm_mode_status
hdmi_port_clock_valid(struct intel_hdmi *hdmi,
		      int clock, bool respect_dvi_limit)
{
	struct drm_device *dev = intel_hdmi_to_dev(hdmi);

	if (clock < 25000)
		return MODE_CLOCK_LOW;
	if (clock > hdmi_port_clock_limit(hdmi, respect_dvi_limit))
		return MODE_CLOCK_HIGH;

1174 1175 1176 1177 1178 1179
	/* BXT DPLL can't generate 223-240 MHz */
	if (IS_BROXTON(dev) && clock > 223333 && clock < 240000)
		return MODE_CLOCK_RANGE;

	/* CHV DPLL can't generate 216-240 MHz */
	if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000)
1180 1181 1182 1183 1184
		return MODE_CLOCK_RANGE;

	return MODE_OK;
}

1185 1186 1187
static enum drm_mode_status
intel_hdmi_mode_valid(struct drm_connector *connector,
		      struct drm_display_mode *mode)
1188
{
1189 1190 1191 1192 1193 1194 1195
	struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
	struct drm_device *dev = intel_hdmi_to_dev(hdmi);
	enum drm_mode_status status;
	int clock;

	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
		return MODE_NO_DBLESCAN;
1196

1197
	clock = mode->clock;
1198 1199 1200
	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
		clock *= 2;

1201 1202
	/* check if we can do 8bpc */
	status = hdmi_port_clock_valid(hdmi, clock, true);
1203

1204 1205 1206
	/* if we can't do 8bpc we may still be able to do 12bpc */
	if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK)
		status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true);
1207

1208
	return status;
1209 1210
}

1211
static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
1212
{
1213 1214
	struct drm_device *dev = crtc_state->base.crtc->dev;
	struct drm_atomic_state *state;
1215
	struct intel_encoder *encoder;
1216
	struct drm_connector *connector;
1217
	struct drm_connector_state *connector_state;
1218
	int count = 0, count_hdmi = 0;
1219
	int i;
1220

1221
	if (HAS_GMCH_DISPLAY(dev))
1222 1223
		return false;

1224 1225
	state = crtc_state->base.state;

1226
	for_each_connector_in_state(state, connector, connector_state, i) {
1227 1228 1229 1230 1231
		if (connector_state->crtc != crtc_state->base.crtc)
			continue;

		encoder = to_intel_encoder(connector_state->best_encoder);

1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242
		count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
		count++;
	}

	/*
	 * HDMI 12bpc affects the clocks, so it's only possible
	 * when not cloning with other encoder types.
	 */
	return count_hdmi > 0 && count_hdmi == count;
}

1243
bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1244
			       struct intel_crtc_state *pipe_config)
1245
{
1246 1247
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
1248
	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1249 1250
	int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
	int clock_12bpc = clock_8bpc * 3 / 2;
1251
	int desired_bpp;
1252

1253 1254
	pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;

1255 1256 1257
	if (pipe_config->has_hdmi_sink)
		pipe_config->has_infoframe = true;

1258 1259
	if (intel_hdmi->color_range_auto) {
		/* See CEA-861-E - 5.1 Default Encoding Parameters */
1260 1261 1262 1263 1264 1265
		pipe_config->limited_color_range =
			pipe_config->has_hdmi_sink &&
			drm_match_cea_mode(adjusted_mode) > 1;
	} else {
		pipe_config->limited_color_range =
			intel_hdmi->limited_color_range;
1266 1267
	}

1268 1269
	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
		pipe_config->pixel_multiplier = 2;
1270
		clock_8bpc *= 2;
1271
		clock_12bpc *= 2;
1272 1273
	}

1274 1275 1276
	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
		pipe_config->has_pch_encoder = true;

1277 1278 1279
	if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
		pipe_config->has_audio = true;

1280 1281 1282
	/*
	 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
	 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1283 1284
	 * outputs. We also need to check that the higher clock still fits
	 * within limits.
1285
	 */
1286
	if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
1287
	    hdmi_port_clock_valid(intel_hdmi, clock_12bpc, false) == MODE_OK &&
1288
	    hdmi_12bpc_possible(pipe_config)) {
1289 1290
		DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
		desired_bpp = 12*3;
1291 1292

		/* Need to adjust the port link by 1.5x for 12bpc. */
1293
		pipe_config->port_clock = clock_12bpc;
1294
	} else {
1295 1296
		DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
		desired_bpp = 8*3;
1297 1298

		pipe_config->port_clock = clock_8bpc;
1299 1300 1301 1302 1303
	}

	if (!pipe_config->bw_constrained) {
		DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
		pipe_config->pipe_bpp = desired_bpp;
1304 1305
	}

1306 1307 1308
	if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
				  false) != MODE_OK) {
		DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1309 1310 1311
		return false;
	}

1312 1313 1314
	/* Set user selected PAR to incoming mode's member */
	adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;

1315 1316 1317
	return true;
}

1318 1319
static void
intel_hdmi_unset_edid(struct drm_connector *connector)
1320
{
1321
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1322

1323 1324 1325 1326 1327 1328 1329 1330 1331
	intel_hdmi->has_hdmi_sink = false;
	intel_hdmi->has_audio = false;
	intel_hdmi->rgb_quant_range_selectable = false;

	kfree(to_intel_connector(connector)->detect_edid);
	to_intel_connector(connector)->detect_edid = NULL;
}

static bool
1332
intel_hdmi_set_edid(struct drm_connector *connector, bool force)
1333 1334 1335 1336 1337 1338
{
	struct drm_i915_private *dev_priv = to_i915(connector->dev);
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
	struct intel_encoder *intel_encoder =
		&hdmi_to_dig_port(intel_hdmi)->base;
	enum intel_display_power_domain power_domain;
1339
	struct edid *edid = NULL;
1340
	bool connected = false;
1341

1342 1343 1344
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_get(dev_priv, power_domain);

1345 1346 1347 1348
	if (force)
		edid = drm_get_edid(connector,
				    intel_gmbus_get_adapter(dev_priv,
				    intel_hdmi->ddc_bus));
1349

1350
	intel_display_power_put(dev_priv, power_domain);
1351

1352 1353 1354 1355 1356 1357
	to_intel_connector(connector)->detect_edid = edid;
	if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
		intel_hdmi->rgb_quant_range_selectable =
			drm_rgb_quant_range_selectable(edid);

		intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1358 1359
		if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
			intel_hdmi->has_audio =
1360 1361 1362 1363 1364 1365 1366
				intel_hdmi->force_audio == HDMI_AUDIO_ON;

		if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
			intel_hdmi->has_hdmi_sink =
				drm_detect_hdmi_monitor(edid);

		connected = true;
1367 1368
	}

1369 1370 1371
	return connected;
}

1372
static void intel_hdmi_hot_plug(struct intel_encoder *intel_encoder)
1373
{
1374 1375 1376 1377 1378
	struct intel_hdmi *intel_hdmi =
			enc_to_intel_hdmi(&intel_encoder->base);
	struct intel_connector *intel_connector =
				intel_hdmi->attached_connector;
	struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
1379 1380
	bool live_status = false;
	unsigned int retry = 3;
1381

1382 1383 1384 1385 1386 1387 1388 1389 1390
	while (!live_status && --retry) {
		live_status = intel_digital_port_connected(dev_priv,
				hdmi_to_dig_port(intel_hdmi));
		mdelay(10);
	}

	if (!live_status)
		DRM_DEBUG_KMS("Live status not up!");

1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401
	/*
	 * We are here, means there is a hotplug or a force
	 * detection. Clear the cached EDID and probe the
	 * DDC bus to check the current status of HDMI.
	 */
	intel_hdmi_unset_edid(&intel_connector->base);
	if (intel_hdmi_set_edid(&intel_connector->base, live_status))
		DRM_DEBUG_DRIVER("DDC probe: got EDID\n");
	else
		DRM_DEBUG_DRIVER("DDC probe: no EDID\n");
}
1402

1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423
static enum drm_connector_status
intel_hdmi_detect(struct drm_connector *connector, bool force)
{
	enum drm_connector_status status;
	struct intel_connector *intel_connector =
				to_intel_connector(connector);

	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
		      connector->base.id, connector->name);

	/*
	 * There are many userspace calls which probe EDID from
	 * detect path. In case of multiple hotplug/unplug, these
	 * can cause race conditions while probing EDID. Also its
	 * waste of CPU cycles to read the EDID again and again
	 * unless there is a real hotplug.
	 * So, rely on hotplugs and init to read edid.
	 * Check connector status based on availability of cached EDID.
	 */

	if (intel_connector->detect_edid) {
1424 1425 1426 1427
		struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);

		hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
		status = connector_status_connected;
1428 1429
		DRM_DEBUG_DRIVER("hdmi status = connected\n");
	} else {
1430
		status = connector_status_disconnected;
1431 1432
		DRM_DEBUG_DRIVER("hdmi status = disconnected\n");
	}
1433

1434
	return status;
1435 1436
}

1437 1438
static void
intel_hdmi_force(struct drm_connector *connector)
1439
{
1440
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1441

1442 1443
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
		      connector->base.id, connector->name);
1444

1445
	intel_hdmi_unset_edid(connector);
1446

1447 1448
	if (connector->status != connector_status_connected)
		return;
1449

1450
	intel_hdmi_set_edid(connector, true);
1451 1452
	hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
}
1453

1454 1455 1456 1457 1458 1459 1460
static int intel_hdmi_get_modes(struct drm_connector *connector)
{
	struct edid *edid;

	edid = to_intel_connector(connector)->detect_edid;
	if (edid == NULL)
		return 0;
1461

1462
	return intel_connector_update_modes(connector, edid);
1463 1464
}

1465 1466 1467 1468
static bool
intel_hdmi_detect_audio(struct drm_connector *connector)
{
	bool has_audio = false;
1469
	struct edid *edid;
1470

1471 1472 1473
	edid = to_intel_connector(connector)->detect_edid;
	if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
		has_audio = drm_detect_monitor_audio(edid);
1474

1475 1476 1477
	return has_audio;
}

1478 1479
static int
intel_hdmi_set_property(struct drm_connector *connector,
1480 1481
			struct drm_property *property,
			uint64_t val)
1482 1483
{
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1484 1485
	struct intel_digital_port *intel_dig_port =
		hdmi_to_dig_port(intel_hdmi);
1486
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
1487 1488
	int ret;

1489
	ret = drm_object_property_set_value(&connector->base, property, val);
1490 1491 1492
	if (ret)
		return ret;

1493
	if (property == dev_priv->force_audio_property) {
1494
		enum hdmi_force_audio i = val;
1495 1496 1497
		bool has_audio;

		if (i == intel_hdmi->force_audio)
1498 1499
			return 0;

1500
		intel_hdmi->force_audio = i;
1501

1502
		if (i == HDMI_AUDIO_AUTO)
1503 1504
			has_audio = intel_hdmi_detect_audio(connector);
		else
1505
			has_audio = (i == HDMI_AUDIO_ON);
1506

1507 1508
		if (i == HDMI_AUDIO_OFF_DVI)
			intel_hdmi->has_hdmi_sink = 0;
1509

1510
		intel_hdmi->has_audio = has_audio;
1511 1512 1513
		goto done;
	}

1514
	if (property == dev_priv->broadcast_rgb_property) {
1515
		bool old_auto = intel_hdmi->color_range_auto;
1516
		bool old_range = intel_hdmi->limited_color_range;
1517

1518 1519 1520 1521 1522 1523
		switch (val) {
		case INTEL_BROADCAST_RGB_AUTO:
			intel_hdmi->color_range_auto = true;
			break;
		case INTEL_BROADCAST_RGB_FULL:
			intel_hdmi->color_range_auto = false;
1524
			intel_hdmi->limited_color_range = false;
1525 1526 1527
			break;
		case INTEL_BROADCAST_RGB_LIMITED:
			intel_hdmi->color_range_auto = false;
1528
			intel_hdmi->limited_color_range = true;
1529 1530 1531 1532
			break;
		default:
			return -EINVAL;
		}
1533 1534

		if (old_auto == intel_hdmi->color_range_auto &&
1535
		    old_range == intel_hdmi->limited_color_range)
1536 1537
			return 0;

1538 1539 1540
		goto done;
	}

1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557
	if (property == connector->dev->mode_config.aspect_ratio_property) {
		switch (val) {
		case DRM_MODE_PICTURE_ASPECT_NONE:
			intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
			break;
		case DRM_MODE_PICTURE_ASPECT_4_3:
			intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
			break;
		case DRM_MODE_PICTURE_ASPECT_16_9:
			intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
			break;
		default:
			return -EINVAL;
		}
		goto done;
	}

1558 1559 1560
	return -EINVAL;

done:
1561 1562
	if (intel_dig_port->base.base.crtc)
		intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1563 1564 1565 1566

	return 0;
}

1567 1568 1569 1570
static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
{
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1571
	const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1572

1573 1574
	intel_hdmi_prepare(encoder);

1575
	intel_hdmi->set_infoframes(&encoder->base,
1576
				   intel_crtc->config->has_hdmi_sink,
1577
				   adjusted_mode);
1578 1579
}

1580
static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1581 1582
{
	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1583
	struct intel_hdmi *intel_hdmi = &dport->hdmi;
1584 1585 1586 1587
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
1588
	const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1589
	enum dpio_channel port = vlv_dport_to_channel(dport);
1590 1591 1592 1593
	int pipe = intel_crtc->pipe;
	u32 val;

	/* Enable clock channels for this port */
V
Ville Syrjälä 已提交
1594
	mutex_lock(&dev_priv->sb_lock);
1595
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1596 1597 1598 1599 1600 1601
	val = 0;
	if (pipe)
		val |= (1<<21);
	else
		val &= ~(1<<21);
	val |= 0x001000c4;
1602
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1603 1604

	/* HDMI 1.0V-2dB */
1605 1606 1607 1608 1609 1610 1611 1612
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
	vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1613 1614

	/* Program lane clock */
1615 1616
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
V
Ville Syrjälä 已提交
1617
	mutex_unlock(&dev_priv->sb_lock);
1618

1619
	intel_hdmi->set_infoframes(&encoder->base,
1620
				   intel_crtc->config->has_hdmi_sink,
1621
				   adjusted_mode);
1622

1623
	g4x_enable_hdmi(encoder);
1624

1625
	vlv_wait_port_ready(dev_priv, dport, 0x0);
1626 1627
}

1628
static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1629 1630 1631 1632
{
	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
1633 1634
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
1635
	enum dpio_channel port = vlv_dport_to_channel(dport);
1636
	int pipe = intel_crtc->pipe;
1637

1638 1639
	intel_hdmi_prepare(encoder);

1640
	/* Program Tx lane resets to default */
V
Ville Syrjälä 已提交
1641
	mutex_lock(&dev_priv->sb_lock);
1642
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1643 1644
			 DPIO_PCS_TX_LANE2_RESET |
			 DPIO_PCS_TX_LANE1_RESET);
1645
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1646 1647 1648 1649 1650 1651
			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
			 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
			 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
			 DPIO_PCS_CLK_SOFT_RESET);

	/* Fix up inter-pair skew failure */
1652 1653 1654 1655 1656 1657
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);

	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
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	mutex_unlock(&dev_priv->sb_lock);
1659 1660
}

1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704
static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
				     bool reset)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
	enum pipe pipe = crtc->pipe;
	uint32_t val;

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
	if (reset)
		val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
	else
		val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);

	if (crtc->config->lane_count > 2) {
		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
		if (reset)
			val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
		else
			val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
	}

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
	val |= CHV_PCS_REQ_SOFTRESET_EN;
	if (reset)
		val &= ~DPIO_PCS_CLK_SOFT_RESET;
	else
		val |= DPIO_PCS_CLK_SOFT_RESET;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);

	if (crtc->config->lane_count > 2) {
		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
		val |= CHV_PCS_REQ_SOFTRESET_EN;
		if (reset)
			val &= ~DPIO_PCS_CLK_SOFT_RESET;
		else
			val |= DPIO_PCS_CLK_SOFT_RESET;
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
	}
}

1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715
static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
{
	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
	enum dpio_channel ch = vlv_dport_to_channel(dport);
	enum pipe pipe = intel_crtc->pipe;
	u32 val;

1716 1717
	intel_hdmi_prepare(encoder);

1718 1719 1720 1721 1722 1723 1724 1725
	/*
	 * Must trick the second common lane into life.
	 * Otherwise we can't even access the PLL.
	 */
	if (ch == DPIO_CH0 && pipe == PIPE_B)
		dport->release_cl2_override =
			!chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);

1726 1727
	chv_phy_powergate_lanes(encoder, true, 0x0);

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1728
	mutex_lock(&dev_priv->sb_lock);
1729

1730 1731 1732
	/* Assert data lane reset */
	chv_data_lane_soft_reset(encoder, true);

1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751
	/* program left/right clock distribution */
	if (pipe != PIPE_B) {
		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
		if (ch == DPIO_CH0)
			val |= CHV_BUFLEFTENA1_FORCE;
		if (ch == DPIO_CH1)
			val |= CHV_BUFRIGHTENA1_FORCE;
		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
	} else {
		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
		if (ch == DPIO_CH0)
			val |= CHV_BUFLEFTENA2_FORCE;
		if (ch == DPIO_CH1)
			val |= CHV_BUFRIGHTENA2_FORCE;
		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
	}

1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780
	/* program clock channel usage */
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
	if (pipe != PIPE_B)
		val &= ~CHV_PCS_USEDCLKCHANNEL;
	else
		val |= CHV_PCS_USEDCLKCHANNEL;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
	if (pipe != PIPE_B)
		val &= ~CHV_PCS_USEDCLKCHANNEL;
	else
		val |= CHV_PCS_USEDCLKCHANNEL;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);

	/*
	 * This a a bit weird since generally CL
	 * matches the pipe, but here we need to
	 * pick the CL based on the port.
	 */
	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
	if (pipe != PIPE_B)
		val &= ~CHV_CMN_USEDCLKCHANNEL;
	else
		val |= CHV_CMN_USEDCLKCHANNEL;
	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);

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	mutex_unlock(&dev_priv->sb_lock);
1782 1783
}

1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803
static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
	u32 val;

	mutex_lock(&dev_priv->sb_lock);

	/* disable left/right clock distribution */
	if (pipe != PIPE_B) {
		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
	} else {
		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
	}

	mutex_unlock(&dev_priv->sb_lock);
1804

1805 1806 1807 1808 1809 1810 1811 1812 1813
	/*
	 * Leave the power down bit cleared for at least one
	 * lane so that chv_powergate_phy_ch() will power
	 * on something when the channel is otherwise unused.
	 * When the port is off and the override is removed
	 * the lanes power down anyway, so otherwise it doesn't
	 * really matter what the state of power down bits is
	 * after this.
	 */
1814
	chv_phy_powergate_lanes(encoder, false, 0x0);
1815 1816
}

1817
static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
1818 1819 1820
{
	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1821 1822
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
1823
	enum dpio_channel port = vlv_dport_to_channel(dport);
1824
	int pipe = intel_crtc->pipe;
1825 1826

	/* Reset lanes to avoid HDMI flicker (VLV w/a) */
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1827
	mutex_lock(&dev_priv->sb_lock);
1828 1829
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
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1830
	mutex_unlock(&dev_priv->sb_lock);
1831 1832
}

1833 1834 1835 1836 1837
static void chv_hdmi_post_disable(struct intel_encoder *encoder)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

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1838
	mutex_lock(&dev_priv->sb_lock);
1839

1840 1841
	/* Assert data lane reset */
	chv_data_lane_soft_reset(encoder, true);
1842

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1843
	mutex_unlock(&dev_priv->sb_lock);
1844 1845
}

1846 1847 1848
static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
{
	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1849
	struct intel_hdmi *intel_hdmi = &dport->hdmi;
1850 1851 1852 1853
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
1854
	const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1855 1856
	enum dpio_channel ch = vlv_dport_to_channel(dport);
	int pipe = intel_crtc->pipe;
1857
	int data, i, stagger;
1858 1859
	u32 val;

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	mutex_lock(&dev_priv->sb_lock);
1861

1862 1863 1864 1865 1866 1867 1868 1869 1870
	/* allow hardware to manage TX FIFO reset source */
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);

1871
	/* Program Tx latency optimal setting */
1872 1873 1874 1875 1876 1877 1878 1879
	for (i = 0; i < 4; i++) {
		/* Set the upar bit */
		data = (i == 1) ? 0x0 : 0x1;
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
				data << DPIO_UPAR_SHIFT);
	}

	/* Data lane stagger programming */
1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911
	if (intel_crtc->config->port_clock > 270000)
		stagger = 0x18;
	else if (intel_crtc->config->port_clock > 135000)
		stagger = 0xd;
	else if (intel_crtc->config->port_clock > 67500)
		stagger = 0x7;
	else if (intel_crtc->config->port_clock > 33750)
		stagger = 0x4;
	else
		stagger = 0x2;

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
	val |= DPIO_TX2_STAGGER_MASK(0x1f);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
	val |= DPIO_TX2_STAGGER_MASK(0x1f);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);

	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
		       DPIO_LANESTAGGER_STRAP(stagger) |
		       DPIO_LANESTAGGER_STRAP_OVRD |
		       DPIO_TX1_STAGGER_MASK(0x1f) |
		       DPIO_TX1_STAGGER_MULT(6) |
		       DPIO_TX2_STAGGER_MULT(0));

	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
		       DPIO_LANESTAGGER_STRAP(stagger) |
		       DPIO_LANESTAGGER_STRAP_OVRD |
		       DPIO_TX1_STAGGER_MASK(0x1f) |
		       DPIO_TX1_STAGGER_MULT(7) |
		       DPIO_TX2_STAGGER_MULT(5));
1912

1913 1914 1915
	/* Deassert data lane reset */
	chv_data_lane_soft_reset(encoder, false);

1916
	/* Clear calc init */
1917 1918
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1919 1920
	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1921 1922 1923 1924
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1925 1926
	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1927
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1928

1929 1930 1931 1932 1933 1934 1935 1936 1937 1938
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);

1939 1940
	/* FIXME: Program the support xxx V-dB */
	/* Use 800mV-0dB */
1941 1942 1943 1944 1945 1946
	for (i = 0; i < 4; i++) {
		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
		val &= ~DPIO_SWING_DEEMPH9P5_MASK;
		val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
	}
1947

1948 1949
	for (i = 0; i < 4; i++) {
		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1950

1951 1952
		val &= ~DPIO_SWING_MARGIN000_MASK;
		val |= 102 << DPIO_SWING_MARGIN000_SHIFT;
1953 1954 1955 1956 1957 1958 1959 1960 1961

		/*
		 * Supposedly this value shouldn't matter when unique transition
		 * scale is disabled, but in fact it does matter. Let's just
		 * always program the same value and hope it's OK.
		 */
		val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
		val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;

1962 1963
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
	}
1964

1965 1966 1967 1968 1969 1970
	/*
	 * The document said it needs to set bit 27 for ch0 and bit 26
	 * for ch1. Might be a typo in the doc.
	 * For now, for this unique transition scale selection, set bit
	 * 27 for ch0 and ch1.
	 */
1971 1972 1973 1974 1975
	for (i = 0; i < 4; i++) {
		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
		val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
	}
1976 1977

	/* Start swing calculation */
1978 1979 1980 1981 1982 1983 1984
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1985

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1986
	mutex_unlock(&dev_priv->sb_lock);
1987

1988
	intel_hdmi->set_infoframes(&encoder->base,
1989
				   intel_crtc->config->has_hdmi_sink,
1990 1991
				   adjusted_mode);

1992
	g4x_enable_hdmi(encoder);
1993

1994
	vlv_wait_port_ready(dev_priv, dport, 0x0);
1995 1996 1997 1998 1999 2000

	/* Second common lane will stay alive on its own now */
	if (dport->release_cl2_override) {
		chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
		dport->release_cl2_override = false;
	}
2001 2002
}

2003 2004
static void intel_hdmi_destroy(struct drm_connector *connector)
{
2005
	kfree(to_intel_connector(connector)->detect_edid);
2006
	drm_connector_cleanup(connector);
2007
	kfree(connector);
2008 2009 2010
}

static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2011
	.dpms = drm_atomic_helper_connector_dpms,
2012
	.detect = intel_hdmi_detect,
2013
	.force = intel_hdmi_force,
2014
	.fill_modes = drm_helper_probe_single_connector_modes,
2015
	.set_property = intel_hdmi_set_property,
2016
	.atomic_get_property = intel_connector_atomic_get_property,
2017
	.destroy = intel_hdmi_destroy,
2018
	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2019
	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
2020 2021 2022 2023 2024
};

static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
	.get_modes = intel_hdmi_get_modes,
	.mode_valid = intel_hdmi_mode_valid,
2025
	.best_encoder = intel_best_encoder,
2026 2027 2028
};

static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
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2029
	.destroy = intel_encoder_destroy,
2030 2031
};

2032 2033 2034
static void
intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
{
2035
	intel_attach_force_audio_property(connector);
2036
	intel_attach_broadcast_rgb_property(connector);
2037
	intel_hdmi->color_range_auto = true;
2038 2039
	intel_attach_aspect_ratio_property(connector);
	intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2040 2041
}

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Paulo Zanoni 已提交
2042 2043
void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
			       struct intel_connector *intel_connector)
2044
{
2045 2046 2047 2048
	struct drm_connector *connector = &intel_connector->base;
	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct drm_device *dev = intel_encoder->base.dev;
2049
	struct drm_i915_private *dev_priv = dev->dev_private;
2050
	enum port port = intel_dig_port->port;
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Xiong Zhang 已提交
2051
	uint8_t alternate_ddc_pin;
2052

2053
	drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
2054
			   DRM_MODE_CONNECTOR_HDMIA);
2055 2056
	drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);

2057
	connector->interlace_allowed = 1;
2058
	connector->doublescan_allowed = 0;
2059
	connector->stereo_allowed = 1;
2060

2061 2062
	switch (port) {
	case PORT_B:
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2063 2064 2065 2066
		if (IS_BROXTON(dev_priv))
			intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT;
		else
			intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
2067 2068 2069 2070 2071 2072 2073 2074
		/*
		 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
		 * interrupts to check the external panel connection.
		 */
		if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0))
			intel_encoder->hpd_pin = HPD_PORT_A;
		else
			intel_encoder->hpd_pin = HPD_PORT_B;
2075 2076
		break;
	case PORT_C:
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2077 2078 2079 2080
		if (IS_BROXTON(dev_priv))
			intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT;
		else
			intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
2081
		intel_encoder->hpd_pin = HPD_PORT_C;
2082 2083
		break;
	case PORT_D:
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2084 2085 2086
		if (WARN_ON(IS_BROXTON(dev_priv)))
			intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED;
		else if (IS_CHERRYVIEW(dev_priv))
2087
			intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV;
2088
		else
2089
			intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
2090
		intel_encoder->hpd_pin = HPD_PORT_D;
2091
		break;
X
Xiong Zhang 已提交
2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111
	case PORT_E:
		/* On SKL PORT E doesn't have seperate GMBUS pin
		 *  We rely on VBT to set a proper alternate GMBUS pin. */
		alternate_ddc_pin =
			dev_priv->vbt.ddi_port_info[PORT_E].alternate_ddc_pin;
		switch (alternate_ddc_pin) {
		case DDC_PIN_B:
			intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
			break;
		case DDC_PIN_C:
			intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
			break;
		case DDC_PIN_D:
			intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
			break;
		default:
			MISSING_CASE(alternate_ddc_pin);
		}
		intel_encoder->hpd_pin = HPD_PORT_E;
		break;
2112
	case PORT_A:
2113
		intel_encoder->hpd_pin = HPD_PORT_A;
2114 2115
		/* Internal port only for eDP. */
	default:
2116
		BUG();
2117
	}
2118

2119
	if (IS_VALLEYVIEW(dev)) {
2120
		intel_hdmi->write_infoframe = vlv_write_infoframe;
2121
		intel_hdmi->set_infoframes = vlv_set_infoframes;
2122
		intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
2123
	} else if (IS_G4X(dev)) {
2124 2125
		intel_hdmi->write_infoframe = g4x_write_infoframe;
		intel_hdmi->set_infoframes = g4x_set_infoframes;
2126
		intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
2127
	} else if (HAS_DDI(dev)) {
2128
		intel_hdmi->write_infoframe = hsw_write_infoframe;
2129
		intel_hdmi->set_infoframes = hsw_set_infoframes;
2130
		intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
2131 2132
	} else if (HAS_PCH_IBX(dev)) {
		intel_hdmi->write_infoframe = ibx_write_infoframe;
2133
		intel_hdmi->set_infoframes = ibx_set_infoframes;
2134
		intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
2135 2136
	} else {
		intel_hdmi->write_infoframe = cpt_write_infoframe;
2137
		intel_hdmi->set_infoframes = cpt_set_infoframes;
2138
		intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
2139
	}
2140

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2141
	if (HAS_DDI(dev))
2142 2143 2144
		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
	else
		intel_connector->get_hw_state = intel_connector_get_hw_state;
2145
	intel_connector->unregister = intel_connector_unregister;
2146 2147

	intel_hdmi_add_properties(intel_hdmi, connector);
2148
	intel_encoder->hot_plug = intel_hdmi_hot_plug;
2149 2150

	intel_connector_attach_encoder(intel_connector, intel_encoder);
2151
	drm_connector_register(connector);
2152
	intel_hdmi->attached_connector = intel_connector;
2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163

	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
	 * 0xd.  Failure to do so will result in spurious interrupts being
	 * generated on the port when a cable is not attached.
	 */
	if (IS_G4X(dev) && !IS_GM45(dev)) {
		u32 temp = I915_READ(PEG_BAND_GAP_DATA);
		I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
	}
}

2164
void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
2165 2166 2167 2168 2169
{
	struct intel_digital_port *intel_dig_port;
	struct intel_encoder *intel_encoder;
	struct intel_connector *intel_connector;

2170
	intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2171 2172 2173
	if (!intel_dig_port)
		return;

2174
	intel_connector = intel_connector_alloc();
2175 2176 2177 2178 2179 2180 2181 2182 2183
	if (!intel_connector) {
		kfree(intel_dig_port);
		return;
	}

	intel_encoder = &intel_dig_port->base;

	drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
			 DRM_MODE_ENCODER_TMDS);
P
Paulo Zanoni 已提交
2184

2185
	intel_encoder->compute_config = intel_hdmi_compute_config;
2186 2187 2188 2189 2190 2191
	if (HAS_PCH_SPLIT(dev)) {
		intel_encoder->disable = pch_disable_hdmi;
		intel_encoder->post_disable = pch_post_disable_hdmi;
	} else {
		intel_encoder->disable = g4x_disable_hdmi;
	}
P
Paulo Zanoni 已提交
2192
	intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
2193
	intel_encoder->get_config = intel_hdmi_get_config;
2194
	if (IS_CHERRYVIEW(dev)) {
2195
		intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
2196 2197
		intel_encoder->pre_enable = chv_hdmi_pre_enable;
		intel_encoder->enable = vlv_enable_hdmi;
2198
		intel_encoder->post_disable = chv_hdmi_post_disable;
2199
		intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
2200
	} else if (IS_VALLEYVIEW(dev)) {
2201 2202
		intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
		intel_encoder->pre_enable = vlv_hdmi_pre_enable;
2203
		intel_encoder->enable = vlv_enable_hdmi;
2204
		intel_encoder->post_disable = vlv_hdmi_post_disable;
2205
	} else {
2206
		intel_encoder->pre_enable = intel_hdmi_pre_enable;
2207 2208
		if (HAS_PCH_CPT(dev))
			intel_encoder->enable = cpt_enable_hdmi;
2209 2210
		else if (HAS_PCH_IBX(dev))
			intel_encoder->enable = ibx_enable_hdmi;
2211
		else
2212
			intel_encoder->enable = g4x_enable_hdmi;
2213
	}
2214

2215
	intel_encoder->type = INTEL_OUTPUT_HDMI;
2216 2217 2218 2219 2220 2221 2222 2223
	if (IS_CHERRYVIEW(dev)) {
		if (port == PORT_D)
			intel_encoder->crtc_mask = 1 << 2;
		else
			intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
	} else {
		intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
	}
2224
	intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
2225 2226 2227 2228 2229 2230 2231
	/*
	 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
	 * to work on real hardware. And since g4x can send infoframes to
	 * only one port anyway, nothing is lost by allowing it.
	 */
	if (IS_G4X(dev))
		intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
2232

2233
	intel_dig_port->port = port;
2234
	intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
2235
	intel_dig_port->dp.output_reg = 0;
2236

2237
	intel_hdmi_init_connector(intel_dig_port, intel_connector);
2238
}